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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52 3; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=SI %s4; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=VI %s5; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s6; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s7; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s8 9define <11 x float> @bitcast_v11i32_to_v11f32(<11 x i32> %a, i32 %b) {10; SI-LABEL: bitcast_v11i32_to_v11f32:11; SI:       ; %bb.0:12; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)13; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1114; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc15; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]16; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]17; SI-NEXT:    s_cbranch_execz .LBB0_218; SI-NEXT:  ; %bb.1: ; %cmp.true19; SI-NEXT:    v_add_i32_e32 v10, vcc, 3, v1020; SI-NEXT:    v_add_i32_e32 v9, vcc, 3, v921; SI-NEXT:    v_add_i32_e32 v8, vcc, 3, v822; SI-NEXT:    v_add_i32_e32 v7, vcc, 3, v723; SI-NEXT:    v_add_i32_e32 v6, vcc, 3, v624; SI-NEXT:    v_add_i32_e32 v5, vcc, 3, v525; SI-NEXT:    v_add_i32_e32 v4, vcc, 3, v426; SI-NEXT:    v_add_i32_e32 v3, vcc, 3, v327; SI-NEXT:    v_add_i32_e32 v2, vcc, 3, v228; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v129; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v030; SI-NEXT:  .LBB0_2: ; %end31; SI-NEXT:    s_or_b64 exec, exec, s[4:5]32; SI-NEXT:    s_setpc_b64 s[30:31]33;34; VI-LABEL: bitcast_v11i32_to_v11f32:35; VI:       ; %bb.0:36; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)37; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1138; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc39; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]40; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]41; VI-NEXT:    s_cbranch_execz .LBB0_242; VI-NEXT:  ; %bb.1: ; %cmp.true43; VI-NEXT:    v_add_u32_e32 v10, vcc, 3, v1044; VI-NEXT:    v_add_u32_e32 v9, vcc, 3, v945; VI-NEXT:    v_add_u32_e32 v8, vcc, 3, v846; VI-NEXT:    v_add_u32_e32 v7, vcc, 3, v747; VI-NEXT:    v_add_u32_e32 v6, vcc, 3, v648; VI-NEXT:    v_add_u32_e32 v5, vcc, 3, v549; VI-NEXT:    v_add_u32_e32 v4, vcc, 3, v450; VI-NEXT:    v_add_u32_e32 v3, vcc, 3, v351; VI-NEXT:    v_add_u32_e32 v2, vcc, 3, v252; VI-NEXT:    v_add_u32_e32 v1, vcc, 3, v153; VI-NEXT:    v_add_u32_e32 v0, vcc, 3, v054; VI-NEXT:  .LBB0_2: ; %end55; VI-NEXT:    s_or_b64 exec, exec, s[4:5]56; VI-NEXT:    s_setpc_b64 s[30:31]57;58; GFX9-LABEL: bitcast_v11i32_to_v11f32:59; GFX9:       ; %bb.0:60; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)61; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1162; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc63; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]64; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]65; GFX9-NEXT:    s_cbranch_execz .LBB0_266; GFX9-NEXT:  ; %bb.1: ; %cmp.true67; GFX9-NEXT:    v_add_u32_e32 v10, 3, v1068; GFX9-NEXT:    v_add_u32_e32 v9, 3, v969; GFX9-NEXT:    v_add_u32_e32 v8, 3, v870; GFX9-NEXT:    v_add_u32_e32 v7, 3, v771; GFX9-NEXT:    v_add_u32_e32 v6, 3, v672; GFX9-NEXT:    v_add_u32_e32 v5, 3, v573; GFX9-NEXT:    v_add_u32_e32 v4, 3, v474; GFX9-NEXT:    v_add_u32_e32 v3, 3, v375; GFX9-NEXT:    v_add_u32_e32 v2, 3, v276; GFX9-NEXT:    v_add_u32_e32 v1, 3, v177; GFX9-NEXT:    v_add_u32_e32 v0, 3, v078; GFX9-NEXT:  .LBB0_2: ; %end79; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]80; GFX9-NEXT:    s_setpc_b64 s[30:31]81;82; GFX11-LABEL: bitcast_v11i32_to_v11f32:83; GFX11:       ; %bb.0:84; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)85; GFX11-NEXT:    s_mov_b32 s0, exec_lo86; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v1187; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s088; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)89; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s090; GFX11-NEXT:    s_cbranch_execz .LBB0_291; GFX11-NEXT:  ; %bb.1: ; %cmp.true92; GFX11-NEXT:    v_add_nc_u32_e32 v10, 3, v1093; GFX11-NEXT:    v_add_nc_u32_e32 v9, 3, v994; GFX11-NEXT:    v_add_nc_u32_e32 v8, 3, v895; GFX11-NEXT:    v_add_nc_u32_e32 v7, 3, v796; GFX11-NEXT:    v_add_nc_u32_e32 v6, 3, v697; GFX11-NEXT:    v_add_nc_u32_e32 v5, 3, v598; GFX11-NEXT:    v_add_nc_u32_e32 v4, 3, v499; GFX11-NEXT:    v_add_nc_u32_e32 v3, 3, v3100; GFX11-NEXT:    v_add_nc_u32_e32 v2, 3, v2101; GFX11-NEXT:    v_add_nc_u32_e32 v1, 3, v1102; GFX11-NEXT:    v_add_nc_u32_e32 v0, 3, v0103; GFX11-NEXT:  .LBB0_2: ; %end104; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0105; GFX11-NEXT:    s_setpc_b64 s[30:31]106  %cmp = icmp eq i32 %b, 0107  br i1 %cmp, label %cmp.true, label %cmp.false108 109cmp.true:110  %a1 = add <11 x i32> %a, splat (i32 3)111  %a2 = bitcast <11 x i32> %a1 to <11 x float>112  br label %end113 114cmp.false:115  %a3 = bitcast <11 x i32> %a to <11 x float>116  br label %end117 118end:119  %phi = phi <11 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]120  ret <11 x float> %phi121}122 123define inreg <11 x float> @bitcast_v11i32_to_v11f32_scalar(<11 x i32> inreg %a, i32 inreg %b) {124; SI-LABEL: bitcast_v11i32_to_v11f32_scalar:125; SI:       ; %bb.0:126; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)127; SI-NEXT:    s_cmp_lg_u32 s27, 0128; SI-NEXT:    s_cbranch_scc0 .LBB1_4129; SI-NEXT:  ; %bb.1: ; %cmp.false130; SI-NEXT:    s_cbranch_execnz .LBB1_3131; SI-NEXT:  .LBB1_2: ; %cmp.true132; SI-NEXT:    s_add_i32 s26, s26, 3133; SI-NEXT:    s_add_i32 s25, s25, 3134; SI-NEXT:    s_add_i32 s24, s24, 3135; SI-NEXT:    s_add_i32 s23, s23, 3136; SI-NEXT:    s_add_i32 s22, s22, 3137; SI-NEXT:    s_add_i32 s21, s21, 3138; SI-NEXT:    s_add_i32 s20, s20, 3139; SI-NEXT:    s_add_i32 s19, s19, 3140; SI-NEXT:    s_add_i32 s18, s18, 3141; SI-NEXT:    s_add_i32 s17, s17, 3142; SI-NEXT:    s_add_i32 s16, s16, 3143; SI-NEXT:  .LBB1_3: ; %end144; SI-NEXT:    v_mov_b32_e32 v0, s16145; SI-NEXT:    v_mov_b32_e32 v1, s17146; SI-NEXT:    v_mov_b32_e32 v2, s18147; SI-NEXT:    v_mov_b32_e32 v3, s19148; SI-NEXT:    v_mov_b32_e32 v4, s20149; SI-NEXT:    v_mov_b32_e32 v5, s21150; SI-NEXT:    v_mov_b32_e32 v6, s22151; SI-NEXT:    v_mov_b32_e32 v7, s23152; SI-NEXT:    v_mov_b32_e32 v8, s24153; SI-NEXT:    v_mov_b32_e32 v9, s25154; SI-NEXT:    v_mov_b32_e32 v10, s26155; SI-NEXT:    s_setpc_b64 s[30:31]156; SI-NEXT:  .LBB1_4:157; SI-NEXT:    s_branch .LBB1_2158;159; VI-LABEL: bitcast_v11i32_to_v11f32_scalar:160; VI:       ; %bb.0:161; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)162; VI-NEXT:    s_cmp_lg_u32 s27, 0163; VI-NEXT:    s_cbranch_scc0 .LBB1_4164; VI-NEXT:  ; %bb.1: ; %cmp.false165; VI-NEXT:    s_cbranch_execnz .LBB1_3166; VI-NEXT:  .LBB1_2: ; %cmp.true167; VI-NEXT:    s_add_i32 s26, s26, 3168; VI-NEXT:    s_add_i32 s25, s25, 3169; VI-NEXT:    s_add_i32 s24, s24, 3170; VI-NEXT:    s_add_i32 s23, s23, 3171; VI-NEXT:    s_add_i32 s22, s22, 3172; VI-NEXT:    s_add_i32 s21, s21, 3173; VI-NEXT:    s_add_i32 s20, s20, 3174; VI-NEXT:    s_add_i32 s19, s19, 3175; VI-NEXT:    s_add_i32 s18, s18, 3176; VI-NEXT:    s_add_i32 s17, s17, 3177; VI-NEXT:    s_add_i32 s16, s16, 3178; VI-NEXT:  .LBB1_3: ; %end179; VI-NEXT:    v_mov_b32_e32 v0, s16180; VI-NEXT:    v_mov_b32_e32 v1, s17181; VI-NEXT:    v_mov_b32_e32 v2, s18182; VI-NEXT:    v_mov_b32_e32 v3, s19183; VI-NEXT:    v_mov_b32_e32 v4, s20184; VI-NEXT:    v_mov_b32_e32 v5, s21185; VI-NEXT:    v_mov_b32_e32 v6, s22186; VI-NEXT:    v_mov_b32_e32 v7, s23187; VI-NEXT:    v_mov_b32_e32 v8, s24188; VI-NEXT:    v_mov_b32_e32 v9, s25189; VI-NEXT:    v_mov_b32_e32 v10, s26190; VI-NEXT:    s_setpc_b64 s[30:31]191; VI-NEXT:  .LBB1_4:192; VI-NEXT:    s_branch .LBB1_2193;194; GFX9-LABEL: bitcast_v11i32_to_v11f32_scalar:195; GFX9:       ; %bb.0:196; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)197; GFX9-NEXT:    s_cmp_lg_u32 s27, 0198; GFX9-NEXT:    s_cbranch_scc0 .LBB1_4199; GFX9-NEXT:  ; %bb.1: ; %cmp.false200; GFX9-NEXT:    s_cbranch_execnz .LBB1_3201; GFX9-NEXT:  .LBB1_2: ; %cmp.true202; GFX9-NEXT:    s_add_i32 s26, s26, 3203; GFX9-NEXT:    s_add_i32 s25, s25, 3204; GFX9-NEXT:    s_add_i32 s24, s24, 3205; GFX9-NEXT:    s_add_i32 s23, s23, 3206; GFX9-NEXT:    s_add_i32 s22, s22, 3207; GFX9-NEXT:    s_add_i32 s21, s21, 3208; GFX9-NEXT:    s_add_i32 s20, s20, 3209; GFX9-NEXT:    s_add_i32 s19, s19, 3210; GFX9-NEXT:    s_add_i32 s18, s18, 3211; GFX9-NEXT:    s_add_i32 s17, s17, 3212; GFX9-NEXT:    s_add_i32 s16, s16, 3213; GFX9-NEXT:  .LBB1_3: ; %end214; GFX9-NEXT:    v_mov_b32_e32 v0, s16215; GFX9-NEXT:    v_mov_b32_e32 v1, s17216; GFX9-NEXT:    v_mov_b32_e32 v2, s18217; GFX9-NEXT:    v_mov_b32_e32 v3, s19218; GFX9-NEXT:    v_mov_b32_e32 v4, s20219; GFX9-NEXT:    v_mov_b32_e32 v5, s21220; GFX9-NEXT:    v_mov_b32_e32 v6, s22221; GFX9-NEXT:    v_mov_b32_e32 v7, s23222; GFX9-NEXT:    v_mov_b32_e32 v8, s24223; GFX9-NEXT:    v_mov_b32_e32 v9, s25224; GFX9-NEXT:    v_mov_b32_e32 v10, s26225; GFX9-NEXT:    s_setpc_b64 s[30:31]226; GFX9-NEXT:  .LBB1_4:227; GFX9-NEXT:    s_branch .LBB1_2228;229; GFX11-LABEL: bitcast_v11i32_to_v11f32_scalar:230; GFX11:       ; %bb.0:231; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)232; GFX11-NEXT:    s_cmp_lg_u32 s23, 0233; GFX11-NEXT:    s_mov_b32 s4, 0234; GFX11-NEXT:    s_cbranch_scc0 .LBB1_4235; GFX11-NEXT:  ; %bb.1: ; %Flow236; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s4237; GFX11-NEXT:    s_cbranch_vccnz .LBB1_3238; GFX11-NEXT:  .LBB1_2: ; %cmp.true239; GFX11-NEXT:    s_add_i32 s22, s22, 3240; GFX11-NEXT:    s_add_i32 s21, s21, 3241; GFX11-NEXT:    s_add_i32 s20, s20, 3242; GFX11-NEXT:    s_add_i32 s19, s19, 3243; GFX11-NEXT:    s_add_i32 s18, s18, 3244; GFX11-NEXT:    s_add_i32 s17, s17, 3245; GFX11-NEXT:    s_add_i32 s16, s16, 3246; GFX11-NEXT:    s_add_i32 s3, s3, 3247; GFX11-NEXT:    s_add_i32 s2, s2, 3248; GFX11-NEXT:    s_add_i32 s1, s1, 3249; GFX11-NEXT:    s_add_i32 s0, s0, 3250; GFX11-NEXT:  .LBB1_3: ; %end251; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)252; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1253; GFX11-NEXT:    v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3254; GFX11-NEXT:    v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17255; GFX11-NEXT:    v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19256; GFX11-NEXT:    v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21257; GFX11-NEXT:    v_mov_b32_e32 v10, s22258; GFX11-NEXT:    s_setpc_b64 s[30:31]259; GFX11-NEXT:  .LBB1_4:260; GFX11-NEXT:    s_branch .LBB1_2261  %cmp = icmp eq i32 %b, 0262  br i1 %cmp, label %cmp.true, label %cmp.false263 264cmp.true:265  %a1 = add <11 x i32> %a, splat (i32 3)266  %a2 = bitcast <11 x i32> %a1 to <11 x float>267  br label %end268 269cmp.false:270  %a3 = bitcast <11 x i32> %a to <11 x float>271  br label %end272 273end:274  %phi = phi <11 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]275  ret <11 x float> %phi276}277 278define <11 x i32> @bitcast_v11f32_to_v11i32(<11 x float> %a, i32 %b) {279; SI-LABEL: bitcast_v11f32_to_v11i32:280; SI:       ; %bb.0:281; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)282; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11283; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc284; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]285; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]286; SI-NEXT:    s_cbranch_execz .LBB2_2287; SI-NEXT:  ; %bb.1: ; %cmp.true288; SI-NEXT:    v_add_f32_e32 v10, 1.0, v10289; SI-NEXT:    v_add_f32_e32 v9, 1.0, v9290; SI-NEXT:    v_add_f32_e32 v8, 1.0, v8291; SI-NEXT:    v_add_f32_e32 v7, 1.0, v7292; SI-NEXT:    v_add_f32_e32 v6, 1.0, v6293; SI-NEXT:    v_add_f32_e32 v5, 1.0, v5294; SI-NEXT:    v_add_f32_e32 v4, 1.0, v4295; SI-NEXT:    v_add_f32_e32 v3, 1.0, v3296; SI-NEXT:    v_add_f32_e32 v2, 1.0, v2297; SI-NEXT:    v_add_f32_e32 v1, 1.0, v1298; SI-NEXT:    v_add_f32_e32 v0, 1.0, v0299; SI-NEXT:  .LBB2_2: ; %end300; SI-NEXT:    s_or_b64 exec, exec, s[4:5]301; SI-NEXT:    s_setpc_b64 s[30:31]302;303; VI-LABEL: bitcast_v11f32_to_v11i32:304; VI:       ; %bb.0:305; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)306; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11307; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc308; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]309; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]310; VI-NEXT:    s_cbranch_execz .LBB2_2311; VI-NEXT:  ; %bb.1: ; %cmp.true312; VI-NEXT:    v_add_f32_e32 v10, 1.0, v10313; VI-NEXT:    v_add_f32_e32 v9, 1.0, v9314; VI-NEXT:    v_add_f32_e32 v8, 1.0, v8315; VI-NEXT:    v_add_f32_e32 v7, 1.0, v7316; VI-NEXT:    v_add_f32_e32 v6, 1.0, v6317; VI-NEXT:    v_add_f32_e32 v5, 1.0, v5318; VI-NEXT:    v_add_f32_e32 v4, 1.0, v4319; VI-NEXT:    v_add_f32_e32 v3, 1.0, v3320; VI-NEXT:    v_add_f32_e32 v2, 1.0, v2321; VI-NEXT:    v_add_f32_e32 v1, 1.0, v1322; VI-NEXT:    v_add_f32_e32 v0, 1.0, v0323; VI-NEXT:  .LBB2_2: ; %end324; VI-NEXT:    s_or_b64 exec, exec, s[4:5]325; VI-NEXT:    s_setpc_b64 s[30:31]326;327; GFX9-LABEL: bitcast_v11f32_to_v11i32:328; GFX9:       ; %bb.0:329; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)330; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11331; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc332; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]333; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]334; GFX9-NEXT:    s_cbranch_execz .LBB2_2335; GFX9-NEXT:  ; %bb.1: ; %cmp.true336; GFX9-NEXT:    v_add_f32_e32 v10, 1.0, v10337; GFX9-NEXT:    v_add_f32_e32 v9, 1.0, v9338; GFX9-NEXT:    v_add_f32_e32 v8, 1.0, v8339; GFX9-NEXT:    v_add_f32_e32 v7, 1.0, v7340; GFX9-NEXT:    v_add_f32_e32 v6, 1.0, v6341; GFX9-NEXT:    v_add_f32_e32 v5, 1.0, v5342; GFX9-NEXT:    v_add_f32_e32 v4, 1.0, v4343; GFX9-NEXT:    v_add_f32_e32 v3, 1.0, v3344; GFX9-NEXT:    v_add_f32_e32 v2, 1.0, v2345; GFX9-NEXT:    v_add_f32_e32 v1, 1.0, v1346; GFX9-NEXT:    v_add_f32_e32 v0, 1.0, v0347; GFX9-NEXT:  .LBB2_2: ; %end348; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]349; GFX9-NEXT:    s_setpc_b64 s[30:31]350;351; GFX11-LABEL: bitcast_v11f32_to_v11i32:352; GFX11:       ; %bb.0:353; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)354; GFX11-NEXT:    s_mov_b32 s0, exec_lo355; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v11356; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0357; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)358; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0359; GFX11-NEXT:  ; %bb.1: ; %cmp.true360; GFX11-NEXT:    v_dual_add_f32 v10, 1.0, v10 :: v_dual_add_f32 v9, 1.0, v9361; GFX11-NEXT:    v_dual_add_f32 v8, 1.0, v8 :: v_dual_add_f32 v7, 1.0, v7362; GFX11-NEXT:    v_dual_add_f32 v6, 1.0, v6 :: v_dual_add_f32 v5, 1.0, v5363; GFX11-NEXT:    v_dual_add_f32 v4, 1.0, v4 :: v_dual_add_f32 v3, 1.0, v3364; GFX11-NEXT:    v_dual_add_f32 v2, 1.0, v2 :: v_dual_add_f32 v1, 1.0, v1365; GFX11-NEXT:    v_add_f32_e32 v0, 1.0, v0366; GFX11-NEXT:  ; %bb.2: ; %end367; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0368; GFX11-NEXT:    s_setpc_b64 s[30:31]369  %cmp = icmp eq i32 %b, 0370  br i1 %cmp, label %cmp.true, label %cmp.false371 372cmp.true:373  %a1 = fadd <11 x float> %a, splat (float 1.000000e+00)374  %a2 = bitcast <11 x float> %a1 to <11 x i32>375  br label %end376 377cmp.false:378  %a3 = bitcast <11 x float> %a to <11 x i32>379  br label %end380 381end:382  %phi = phi <11 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]383  ret <11 x i32> %phi384}385 386define inreg <11 x i32> @bitcast_v11f32_to_v11i32_scalar(<11 x float> inreg %a, i32 inreg %b) {387; SI-LABEL: bitcast_v11f32_to_v11i32_scalar:388; SI:       ; %bb.0:389; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)390; SI-NEXT:    s_cmp_lg_u32 s27, 0391; SI-NEXT:    s_cbranch_scc0 .LBB3_3392; SI-NEXT:  ; %bb.1: ; %cmp.false393; SI-NEXT:    s_cbranch_execnz .LBB3_4394; SI-NEXT:  .LBB3_2: ; %cmp.true395; SI-NEXT:    v_add_f32_e64 v10, s26, 1.0396; SI-NEXT:    v_add_f32_e64 v9, s25, 1.0397; SI-NEXT:    v_add_f32_e64 v8, s24, 1.0398; SI-NEXT:    v_add_f32_e64 v7, s23, 1.0399; SI-NEXT:    v_add_f32_e64 v6, s22, 1.0400; SI-NEXT:    v_add_f32_e64 v5, s21, 1.0401; SI-NEXT:    v_add_f32_e64 v4, s20, 1.0402; SI-NEXT:    v_add_f32_e64 v3, s19, 1.0403; SI-NEXT:    v_add_f32_e64 v2, s18, 1.0404; SI-NEXT:    v_add_f32_e64 v1, s17, 1.0405; SI-NEXT:    v_add_f32_e64 v0, s16, 1.0406; SI-NEXT:    s_setpc_b64 s[30:31]407; SI-NEXT:  .LBB3_3:408; SI-NEXT:    s_branch .LBB3_2409; SI-NEXT:  .LBB3_4:410; SI-NEXT:    v_mov_b32_e32 v0, s16411; SI-NEXT:    v_mov_b32_e32 v1, s17412; SI-NEXT:    v_mov_b32_e32 v2, s18413; SI-NEXT:    v_mov_b32_e32 v3, s19414; SI-NEXT:    v_mov_b32_e32 v4, s20415; SI-NEXT:    v_mov_b32_e32 v5, s21416; SI-NEXT:    v_mov_b32_e32 v6, s22417; SI-NEXT:    v_mov_b32_e32 v7, s23418; SI-NEXT:    v_mov_b32_e32 v8, s24419; SI-NEXT:    v_mov_b32_e32 v9, s25420; SI-NEXT:    v_mov_b32_e32 v10, s26421; SI-NEXT:    s_setpc_b64 s[30:31]422;423; VI-LABEL: bitcast_v11f32_to_v11i32_scalar:424; VI:       ; %bb.0:425; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)426; VI-NEXT:    s_cmp_lg_u32 s27, 0427; VI-NEXT:    s_cbranch_scc0 .LBB3_3428; VI-NEXT:  ; %bb.1: ; %cmp.false429; VI-NEXT:    s_cbranch_execnz .LBB3_4430; VI-NEXT:  .LBB3_2: ; %cmp.true431; VI-NEXT:    v_add_f32_e64 v10, s26, 1.0432; VI-NEXT:    v_add_f32_e64 v9, s25, 1.0433; VI-NEXT:    v_add_f32_e64 v8, s24, 1.0434; VI-NEXT:    v_add_f32_e64 v7, s23, 1.0435; VI-NEXT:    v_add_f32_e64 v6, s22, 1.0436; VI-NEXT:    v_add_f32_e64 v5, s21, 1.0437; VI-NEXT:    v_add_f32_e64 v4, s20, 1.0438; VI-NEXT:    v_add_f32_e64 v3, s19, 1.0439; VI-NEXT:    v_add_f32_e64 v2, s18, 1.0440; VI-NEXT:    v_add_f32_e64 v1, s17, 1.0441; VI-NEXT:    v_add_f32_e64 v0, s16, 1.0442; VI-NEXT:    s_setpc_b64 s[30:31]443; VI-NEXT:  .LBB3_3:444; VI-NEXT:    s_branch .LBB3_2445; VI-NEXT:  .LBB3_4:446; VI-NEXT:    v_mov_b32_e32 v0, s16447; VI-NEXT:    v_mov_b32_e32 v1, s17448; VI-NEXT:    v_mov_b32_e32 v2, s18449; VI-NEXT:    v_mov_b32_e32 v3, s19450; VI-NEXT:    v_mov_b32_e32 v4, s20451; VI-NEXT:    v_mov_b32_e32 v5, s21452; VI-NEXT:    v_mov_b32_e32 v6, s22453; VI-NEXT:    v_mov_b32_e32 v7, s23454; VI-NEXT:    v_mov_b32_e32 v8, s24455; VI-NEXT:    v_mov_b32_e32 v9, s25456; VI-NEXT:    v_mov_b32_e32 v10, s26457; VI-NEXT:    s_setpc_b64 s[30:31]458;459; GFX9-LABEL: bitcast_v11f32_to_v11i32_scalar:460; GFX9:       ; %bb.0:461; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)462; GFX9-NEXT:    s_cmp_lg_u32 s27, 0463; GFX9-NEXT:    s_cbranch_scc0 .LBB3_3464; GFX9-NEXT:  ; %bb.1: ; %cmp.false465; GFX9-NEXT:    s_cbranch_execnz .LBB3_4466; GFX9-NEXT:  .LBB3_2: ; %cmp.true467; GFX9-NEXT:    v_add_f32_e64 v10, s26, 1.0468; GFX9-NEXT:    v_add_f32_e64 v9, s25, 1.0469; GFX9-NEXT:    v_add_f32_e64 v8, s24, 1.0470; GFX9-NEXT:    v_add_f32_e64 v7, s23, 1.0471; GFX9-NEXT:    v_add_f32_e64 v6, s22, 1.0472; GFX9-NEXT:    v_add_f32_e64 v5, s21, 1.0473; GFX9-NEXT:    v_add_f32_e64 v4, s20, 1.0474; GFX9-NEXT:    v_add_f32_e64 v3, s19, 1.0475; GFX9-NEXT:    v_add_f32_e64 v2, s18, 1.0476; GFX9-NEXT:    v_add_f32_e64 v1, s17, 1.0477; GFX9-NEXT:    v_add_f32_e64 v0, s16, 1.0478; GFX9-NEXT:    s_setpc_b64 s[30:31]479; GFX9-NEXT:  .LBB3_3:480; GFX9-NEXT:    s_branch .LBB3_2481; GFX9-NEXT:  .LBB3_4:482; GFX9-NEXT:    v_mov_b32_e32 v0, s16483; GFX9-NEXT:    v_mov_b32_e32 v1, s17484; GFX9-NEXT:    v_mov_b32_e32 v2, s18485; GFX9-NEXT:    v_mov_b32_e32 v3, s19486; GFX9-NEXT:    v_mov_b32_e32 v4, s20487; GFX9-NEXT:    v_mov_b32_e32 v5, s21488; GFX9-NEXT:    v_mov_b32_e32 v6, s22489; GFX9-NEXT:    v_mov_b32_e32 v7, s23490; GFX9-NEXT:    v_mov_b32_e32 v8, s24491; GFX9-NEXT:    v_mov_b32_e32 v9, s25492; GFX9-NEXT:    v_mov_b32_e32 v10, s26493; GFX9-NEXT:    s_setpc_b64 s[30:31]494;495; GFX11-LABEL: bitcast_v11f32_to_v11i32_scalar:496; GFX11:       ; %bb.0:497; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)498; GFX11-NEXT:    s_mov_b32 s15, s3499; GFX11-NEXT:    s_mov_b32 s14, s2500; GFX11-NEXT:    s_mov_b32 s13, s1501; GFX11-NEXT:    s_mov_b32 s12, s0502; GFX11-NEXT:    s_cmp_lg_u32 s23, 0503; GFX11-NEXT:    s_mov_b32 s0, 0504; GFX11-NEXT:    s_cbranch_scc0 .LBB3_3505; GFX11-NEXT:  ; %bb.1: ; %Flow506; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s0507; GFX11-NEXT:    s_cbranch_vccnz .LBB3_4508; GFX11-NEXT:  .LBB3_2: ; %cmp.true509; GFX11-NEXT:    v_add_f32_e64 v10, s22, 1.0510; GFX11-NEXT:    v_add_f32_e64 v9, s21, 1.0511; GFX11-NEXT:    v_add_f32_e64 v8, s20, 1.0512; GFX11-NEXT:    v_add_f32_e64 v7, s19, 1.0513; GFX11-NEXT:    v_add_f32_e64 v6, s18, 1.0514; GFX11-NEXT:    v_add_f32_e64 v5, s17, 1.0515; GFX11-NEXT:    v_add_f32_e64 v4, s16, 1.0516; GFX11-NEXT:    v_add_f32_e64 v3, s15, 1.0517; GFX11-NEXT:    v_add_f32_e64 v2, s14, 1.0518; GFX11-NEXT:    v_add_f32_e64 v1, s13, 1.0519; GFX11-NEXT:    v_add_f32_e64 v0, s12, 1.0520; GFX11-NEXT:    s_setpc_b64 s[30:31]521; GFX11-NEXT:  .LBB3_3:522; GFX11-NEXT:    s_branch .LBB3_2523; GFX11-NEXT:  .LBB3_4:524; GFX11-NEXT:    v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13525; GFX11-NEXT:    v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15526; GFX11-NEXT:    v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17527; GFX11-NEXT:    v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19528; GFX11-NEXT:    v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21529; GFX11-NEXT:    v_mov_b32_e32 v10, s22530; GFX11-NEXT:    s_setpc_b64 s[30:31]531  %cmp = icmp eq i32 %b, 0532  br i1 %cmp, label %cmp.true, label %cmp.false533 534cmp.true:535  %a1 = fadd <11 x float> %a, splat (float 1.000000e+00)536  %a2 = bitcast <11 x float> %a1 to <11 x i32>537  br label %end538 539cmp.false:540  %a3 = bitcast <11 x float> %a to <11 x i32>541  br label %end542 543end:544  %phi = phi <11 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]545  ret <11 x i32> %phi546}547 548define <22 x i16> @bitcast_v11i32_to_v22i16(<11 x i32> %a, i32 %b) {549; SI-LABEL: bitcast_v11i32_to_v22i16:550; SI:       ; %bb.0:551; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)552; SI-NEXT:    v_mov_b32_e32 v20, v10553; SI-NEXT:    v_mov_b32_e32 v18, v9554; SI-NEXT:    v_mov_b32_e32 v16, v8555; SI-NEXT:    v_mov_b32_e32 v14, v7556; SI-NEXT:    v_mov_b32_e32 v12, v6557; SI-NEXT:    v_mov_b32_e32 v10, v5558; SI-NEXT:    v_mov_b32_e32 v8, v4559; SI-NEXT:    v_mov_b32_e32 v6, v3560; SI-NEXT:    v_mov_b32_e32 v4, v2561; SI-NEXT:    v_mov_b32_e32 v2, v1562; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11563; SI-NEXT:    ; implicit-def: $vgpr1564; SI-NEXT:    ; implicit-def: $vgpr3565; SI-NEXT:    ; implicit-def: $vgpr5566; SI-NEXT:    ; implicit-def: $vgpr7567; SI-NEXT:    ; implicit-def: $vgpr9568; SI-NEXT:    ; implicit-def: $vgpr11569; SI-NEXT:    ; implicit-def: $vgpr13570; SI-NEXT:    ; implicit-def: $vgpr15571; SI-NEXT:    ; implicit-def: $vgpr17572; SI-NEXT:    ; implicit-def: $vgpr19573; SI-NEXT:    ; implicit-def: $vgpr21574; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc575; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]576; SI-NEXT:    s_cbranch_execnz .LBB4_3577; SI-NEXT:  ; %bb.1: ; %Flow578; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]579; SI-NEXT:    s_cbranch_execnz .LBB4_4580; SI-NEXT:  .LBB4_2: ; %end581; SI-NEXT:    s_or_b64 exec, exec, s[4:5]582; SI-NEXT:    s_setpc_b64 s[30:31]583; SI-NEXT:  .LBB4_3: ; %cmp.false584; SI-NEXT:    v_alignbit_b32 v21, v0, v20, 16585; SI-NEXT:    v_alignbit_b32 v17, v18, v16, 16586; SI-NEXT:    v_alignbit_b32 v13, v14, v12, 16587; SI-NEXT:    v_alignbit_b32 v9, v10, v8, 16588; SI-NEXT:    v_alignbit_b32 v5, v6, v4, 16589; SI-NEXT:    v_alignbit_b32 v1, v2, v0, 16590; SI-NEXT:    v_lshrrev_b32_e32 v19, 16, v18591; SI-NEXT:    v_lshrrev_b32_e32 v15, 16, v14592; SI-NEXT:    v_lshrrev_b32_e32 v11, 16, v10593; SI-NEXT:    v_lshrrev_b32_e32 v7, 16, v6594; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v2595; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]596; SI-NEXT:    s_cbranch_execz .LBB4_2597; SI-NEXT:  .LBB4_4: ; %cmp.true598; SI-NEXT:    v_add_i32_e32 v20, vcc, 3, v20599; SI-NEXT:    v_add_i32_e32 v2, vcc, 3, v2600; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v0601; SI-NEXT:    v_add_i32_e32 v6, vcc, 3, v6602; SI-NEXT:    v_add_i32_e32 v4, vcc, 3, v4603; SI-NEXT:    v_add_i32_e32 v10, vcc, 3, v10604; SI-NEXT:    v_add_i32_e32 v8, vcc, 3, v8605; SI-NEXT:    v_add_i32_e32 v14, vcc, 3, v14606; SI-NEXT:    v_add_i32_e32 v12, vcc, 3, v12607; SI-NEXT:    v_add_i32_e32 v18, vcc, 3, v18608; SI-NEXT:    v_add_i32_e32 v16, vcc, 3, v16609; SI-NEXT:    v_alignbit_b32 v17, v18, v16, 16610; SI-NEXT:    v_alignbit_b32 v13, v14, v12, 16611; SI-NEXT:    v_alignbit_b32 v9, v10, v8, 16612; SI-NEXT:    v_alignbit_b32 v5, v6, v4, 16613; SI-NEXT:    v_alignbit_b32 v1, v2, v0, 16614; SI-NEXT:    v_alignbit_b32 v21, v0, v20, 16615; SI-NEXT:    v_lshrrev_b32_e32 v19, 16, v18616; SI-NEXT:    v_lshrrev_b32_e32 v15, 16, v14617; SI-NEXT:    v_lshrrev_b32_e32 v11, 16, v10618; SI-NEXT:    v_lshrrev_b32_e32 v7, 16, v6619; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v2620; SI-NEXT:    s_or_b64 exec, exec, s[4:5]621; SI-NEXT:    s_setpc_b64 s[30:31]622;623; VI-LABEL: bitcast_v11i32_to_v22i16:624; VI:       ; %bb.0:625; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)626; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11627; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc628; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]629; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]630; VI-NEXT:    s_cbranch_execz .LBB4_2631; VI-NEXT:  ; %bb.1: ; %cmp.true632; VI-NEXT:    v_add_u32_e32 v10, vcc, 3, v10633; VI-NEXT:    v_add_u32_e32 v9, vcc, 3, v9634; VI-NEXT:    v_add_u32_e32 v8, vcc, 3, v8635; VI-NEXT:    v_add_u32_e32 v7, vcc, 3, v7636; VI-NEXT:    v_add_u32_e32 v6, vcc, 3, v6637; VI-NEXT:    v_add_u32_e32 v5, vcc, 3, v5638; VI-NEXT:    v_add_u32_e32 v4, vcc, 3, v4639; VI-NEXT:    v_add_u32_e32 v3, vcc, 3, v3640; VI-NEXT:    v_add_u32_e32 v2, vcc, 3, v2641; VI-NEXT:    v_add_u32_e32 v1, vcc, 3, v1642; VI-NEXT:    v_add_u32_e32 v0, vcc, 3, v0643; VI-NEXT:  .LBB4_2: ; %end644; VI-NEXT:    s_or_b64 exec, exec, s[4:5]645; VI-NEXT:    s_setpc_b64 s[30:31]646;647; GFX9-LABEL: bitcast_v11i32_to_v22i16:648; GFX9:       ; %bb.0:649; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)650; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11651; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc652; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]653; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]654; GFX9-NEXT:    s_cbranch_execz .LBB4_2655; GFX9-NEXT:  ; %bb.1: ; %cmp.true656; GFX9-NEXT:    v_add_u32_e32 v10, 3, v10657; GFX9-NEXT:    v_add_u32_e32 v9, 3, v9658; GFX9-NEXT:    v_add_u32_e32 v8, 3, v8659; GFX9-NEXT:    v_add_u32_e32 v7, 3, v7660; GFX9-NEXT:    v_add_u32_e32 v6, 3, v6661; GFX9-NEXT:    v_add_u32_e32 v5, 3, v5662; GFX9-NEXT:    v_add_u32_e32 v4, 3, v4663; GFX9-NEXT:    v_add_u32_e32 v3, 3, v3664; GFX9-NEXT:    v_add_u32_e32 v2, 3, v2665; GFX9-NEXT:    v_add_u32_e32 v1, 3, v1666; GFX9-NEXT:    v_add_u32_e32 v0, 3, v0667; GFX9-NEXT:  .LBB4_2: ; %end668; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]669; GFX9-NEXT:    s_setpc_b64 s[30:31]670;671; GFX11-LABEL: bitcast_v11i32_to_v22i16:672; GFX11:       ; %bb.0:673; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)674; GFX11-NEXT:    s_mov_b32 s0, exec_lo675; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v11676; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0677; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)678; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0679; GFX11-NEXT:    s_cbranch_execz .LBB4_2680; GFX11-NEXT:  ; %bb.1: ; %cmp.true681; GFX11-NEXT:    v_add_nc_u32_e32 v10, 3, v10682; GFX11-NEXT:    v_add_nc_u32_e32 v9, 3, v9683; GFX11-NEXT:    v_add_nc_u32_e32 v8, 3, v8684; GFX11-NEXT:    v_add_nc_u32_e32 v7, 3, v7685; GFX11-NEXT:    v_add_nc_u32_e32 v6, 3, v6686; GFX11-NEXT:    v_add_nc_u32_e32 v5, 3, v5687; GFX11-NEXT:    v_add_nc_u32_e32 v4, 3, v4688; GFX11-NEXT:    v_add_nc_u32_e32 v3, 3, v3689; GFX11-NEXT:    v_add_nc_u32_e32 v2, 3, v2690; GFX11-NEXT:    v_add_nc_u32_e32 v1, 3, v1691; GFX11-NEXT:    v_add_nc_u32_e32 v0, 3, v0692; GFX11-NEXT:  .LBB4_2: ; %end693; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0694; GFX11-NEXT:    s_setpc_b64 s[30:31]695  %cmp = icmp eq i32 %b, 0696  br i1 %cmp, label %cmp.true, label %cmp.false697 698cmp.true:699  %a1 = add <11 x i32> %a, splat (i32 3)700  %a2 = bitcast <11 x i32> %a1 to <22 x i16>701  br label %end702 703cmp.false:704  %a3 = bitcast <11 x i32> %a to <22 x i16>705  br label %end706 707end:708  %phi = phi <22 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]709  ret <22 x i16> %phi710}711 712define inreg <22 x i16> @bitcast_v11i32_to_v22i16_scalar(<11 x i32> inreg %a, i32 inreg %b) {713; SI-LABEL: bitcast_v11i32_to_v22i16_scalar:714; SI:       ; %bb.0:715; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)716; SI-NEXT:    s_cmp_lg_u32 s27, 0717; SI-NEXT:    s_cbranch_scc0 .LBB5_4718; SI-NEXT:  ; %bb.1: ; %cmp.false719; SI-NEXT:    s_lshr_b32 s27, s25, 16720; SI-NEXT:    s_lshr_b32 s40, s23, 16721; SI-NEXT:    s_lshr_b32 s41, s21, 16722; SI-NEXT:    s_lshr_b32 s42, s19, 16723; SI-NEXT:    s_lshr_b32 s43, s17, 16724; SI-NEXT:    s_lshr_b64 s[10:11], s[26:27], 16725; SI-NEXT:    s_lshr_b64 s[4:5], s[24:25], 16726; SI-NEXT:    s_lshr_b64 s[6:7], s[22:23], 16727; SI-NEXT:    s_lshr_b64 s[8:9], s[20:21], 16728; SI-NEXT:    s_lshr_b64 s[12:13], s[18:19], 16729; SI-NEXT:    s_lshr_b64 s[14:15], s[16:17], 16730; SI-NEXT:    s_cbranch_execnz .LBB5_3731; SI-NEXT:  .LBB5_2: ; %cmp.true732; SI-NEXT:    s_add_i32 s25, s25, 3733; SI-NEXT:    s_add_i32 s26, s26, 3734; SI-NEXT:    s_add_i32 s17, s17, 3735; SI-NEXT:    s_add_i32 s16, s16, 3736; SI-NEXT:    s_add_i32 s19, s19, 3737; SI-NEXT:    s_add_i32 s18, s18, 3738; SI-NEXT:    s_add_i32 s21, s21, 3739; SI-NEXT:    s_add_i32 s20, s20, 3740; SI-NEXT:    s_add_i32 s23, s23, 3741; SI-NEXT:    s_add_i32 s22, s22, 3742; SI-NEXT:    s_add_i32 s24, s24, 3743; SI-NEXT:    s_lshr_b32 s27, s25, 16744; SI-NEXT:    s_lshr_b64 s[4:5], s[24:25], 16745; SI-NEXT:    s_lshr_b64 s[6:7], s[22:23], 16746; SI-NEXT:    s_lshr_b64 s[8:9], s[20:21], 16747; SI-NEXT:    s_lshr_b64 s[12:13], s[18:19], 16748; SI-NEXT:    s_lshr_b64 s[14:15], s[16:17], 16749; SI-NEXT:    s_lshr_b32 s40, s23, 16750; SI-NEXT:    s_lshr_b32 s41, s21, 16751; SI-NEXT:    s_lshr_b32 s42, s19, 16752; SI-NEXT:    s_lshr_b32 s43, s17, 16753; SI-NEXT:    s_lshr_b64 s[10:11], s[26:27], 16754; SI-NEXT:  .LBB5_3: ; %end755; SI-NEXT:    v_mov_b32_e32 v0, s16756; SI-NEXT:    v_mov_b32_e32 v1, s14757; SI-NEXT:    v_mov_b32_e32 v2, s17758; SI-NEXT:    v_mov_b32_e32 v3, s43759; SI-NEXT:    v_mov_b32_e32 v4, s18760; SI-NEXT:    v_mov_b32_e32 v5, s12761; SI-NEXT:    v_mov_b32_e32 v6, s19762; SI-NEXT:    v_mov_b32_e32 v7, s42763; SI-NEXT:    v_mov_b32_e32 v8, s20764; SI-NEXT:    v_mov_b32_e32 v9, s8765; SI-NEXT:    v_mov_b32_e32 v10, s21766; SI-NEXT:    v_mov_b32_e32 v11, s41767; SI-NEXT:    v_mov_b32_e32 v12, s22768; SI-NEXT:    v_mov_b32_e32 v13, s6769; SI-NEXT:    v_mov_b32_e32 v14, s23770; SI-NEXT:    v_mov_b32_e32 v15, s40771; SI-NEXT:    v_mov_b32_e32 v16, s24772; SI-NEXT:    v_mov_b32_e32 v17, s4773; SI-NEXT:    v_mov_b32_e32 v18, s25774; SI-NEXT:    v_mov_b32_e32 v19, s27775; SI-NEXT:    v_mov_b32_e32 v20, s26776; SI-NEXT:    v_mov_b32_e32 v21, s10777; SI-NEXT:    s_setpc_b64 s[30:31]778; SI-NEXT:  .LBB5_4:779; SI-NEXT:    ; implicit-def: $sgpr14780; SI-NEXT:    ; implicit-def: $sgpr43781; SI-NEXT:    ; implicit-def: $sgpr12782; SI-NEXT:    ; implicit-def: $sgpr42783; SI-NEXT:    ; implicit-def: $sgpr8784; SI-NEXT:    ; implicit-def: $sgpr41785; SI-NEXT:    ; implicit-def: $sgpr6786; SI-NEXT:    ; implicit-def: $sgpr40787; SI-NEXT:    ; implicit-def: $sgpr4788; SI-NEXT:    ; implicit-def: $sgpr27789; SI-NEXT:    ; implicit-def: $sgpr10790; SI-NEXT:    s_branch .LBB5_2791;792; VI-LABEL: bitcast_v11i32_to_v22i16_scalar:793; VI:       ; %bb.0:794; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)795; VI-NEXT:    s_cmp_lg_u32 s27, 0796; VI-NEXT:    s_cbranch_scc0 .LBB5_4797; VI-NEXT:  ; %bb.1: ; %cmp.false798; VI-NEXT:    s_cbranch_execnz .LBB5_3799; VI-NEXT:  .LBB5_2: ; %cmp.true800; VI-NEXT:    s_add_i32 s26, s26, 3801; VI-NEXT:    s_add_i32 s25, s25, 3802; VI-NEXT:    s_add_i32 s24, s24, 3803; VI-NEXT:    s_add_i32 s23, s23, 3804; VI-NEXT:    s_add_i32 s22, s22, 3805; VI-NEXT:    s_add_i32 s21, s21, 3806; VI-NEXT:    s_add_i32 s20, s20, 3807; VI-NEXT:    s_add_i32 s19, s19, 3808; VI-NEXT:    s_add_i32 s18, s18, 3809; VI-NEXT:    s_add_i32 s17, s17, 3810; VI-NEXT:    s_add_i32 s16, s16, 3811; VI-NEXT:  .LBB5_3: ; %end812; VI-NEXT:    v_mov_b32_e32 v0, s16813; VI-NEXT:    v_mov_b32_e32 v1, s17814; VI-NEXT:    v_mov_b32_e32 v2, s18815; VI-NEXT:    v_mov_b32_e32 v3, s19816; VI-NEXT:    v_mov_b32_e32 v4, s20817; VI-NEXT:    v_mov_b32_e32 v5, s21818; VI-NEXT:    v_mov_b32_e32 v6, s22819; VI-NEXT:    v_mov_b32_e32 v7, s23820; VI-NEXT:    v_mov_b32_e32 v8, s24821; VI-NEXT:    v_mov_b32_e32 v9, s25822; VI-NEXT:    v_mov_b32_e32 v10, s26823; VI-NEXT:    s_setpc_b64 s[30:31]824; VI-NEXT:  .LBB5_4:825; VI-NEXT:    s_branch .LBB5_2826;827; GFX9-LABEL: bitcast_v11i32_to_v22i16_scalar:828; GFX9:       ; %bb.0:829; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)830; GFX9-NEXT:    s_cmp_lg_u32 s27, 0831; GFX9-NEXT:    s_cbranch_scc0 .LBB5_4832; GFX9-NEXT:  ; %bb.1: ; %cmp.false833; GFX9-NEXT:    s_cbranch_execnz .LBB5_3834; GFX9-NEXT:  .LBB5_2: ; %cmp.true835; GFX9-NEXT:    s_add_i32 s26, s26, 3836; GFX9-NEXT:    s_add_i32 s25, s25, 3837; GFX9-NEXT:    s_add_i32 s24, s24, 3838; GFX9-NEXT:    s_add_i32 s23, s23, 3839; GFX9-NEXT:    s_add_i32 s22, s22, 3840; GFX9-NEXT:    s_add_i32 s21, s21, 3841; GFX9-NEXT:    s_add_i32 s20, s20, 3842; GFX9-NEXT:    s_add_i32 s19, s19, 3843; GFX9-NEXT:    s_add_i32 s18, s18, 3844; GFX9-NEXT:    s_add_i32 s17, s17, 3845; GFX9-NEXT:    s_add_i32 s16, s16, 3846; GFX9-NEXT:  .LBB5_3: ; %end847; GFX9-NEXT:    v_mov_b32_e32 v0, s16848; GFX9-NEXT:    v_mov_b32_e32 v1, s17849; GFX9-NEXT:    v_mov_b32_e32 v2, s18850; GFX9-NEXT:    v_mov_b32_e32 v3, s19851; GFX9-NEXT:    v_mov_b32_e32 v4, s20852; GFX9-NEXT:    v_mov_b32_e32 v5, s21853; GFX9-NEXT:    v_mov_b32_e32 v6, s22854; GFX9-NEXT:    v_mov_b32_e32 v7, s23855; GFX9-NEXT:    v_mov_b32_e32 v8, s24856; GFX9-NEXT:    v_mov_b32_e32 v9, s25857; GFX9-NEXT:    v_mov_b32_e32 v10, s26858; GFX9-NEXT:    s_setpc_b64 s[30:31]859; GFX9-NEXT:  .LBB5_4:860; GFX9-NEXT:    s_branch .LBB5_2861;862; GFX11-LABEL: bitcast_v11i32_to_v22i16_scalar:863; GFX11:       ; %bb.0:864; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)865; GFX11-NEXT:    s_cmp_lg_u32 s23, 0866; GFX11-NEXT:    s_mov_b32 s4, 0867; GFX11-NEXT:    s_cbranch_scc0 .LBB5_4868; GFX11-NEXT:  ; %bb.1: ; %Flow869; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s4870; GFX11-NEXT:    s_cbranch_vccnz .LBB5_3871; GFX11-NEXT:  .LBB5_2: ; %cmp.true872; GFX11-NEXT:    s_add_i32 s22, s22, 3873; GFX11-NEXT:    s_add_i32 s21, s21, 3874; GFX11-NEXT:    s_add_i32 s20, s20, 3875; GFX11-NEXT:    s_add_i32 s19, s19, 3876; GFX11-NEXT:    s_add_i32 s18, s18, 3877; GFX11-NEXT:    s_add_i32 s17, s17, 3878; GFX11-NEXT:    s_add_i32 s16, s16, 3879; GFX11-NEXT:    s_add_i32 s3, s3, 3880; GFX11-NEXT:    s_add_i32 s2, s2, 3881; GFX11-NEXT:    s_add_i32 s1, s1, 3882; GFX11-NEXT:    s_add_i32 s0, s0, 3883; GFX11-NEXT:  .LBB5_3: ; %end884; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)885; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1886; GFX11-NEXT:    v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3887; GFX11-NEXT:    v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17888; GFX11-NEXT:    v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19889; GFX11-NEXT:    v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21890; GFX11-NEXT:    v_mov_b32_e32 v10, s22891; GFX11-NEXT:    s_setpc_b64 s[30:31]892; GFX11-NEXT:  .LBB5_4:893; GFX11-NEXT:    s_branch .LBB5_2894  %cmp = icmp eq i32 %b, 0895  br i1 %cmp, label %cmp.true, label %cmp.false896 897cmp.true:898  %a1 = add <11 x i32> %a, splat (i32 3)899  %a2 = bitcast <11 x i32> %a1 to <22 x i16>900  br label %end901 902cmp.false:903  %a3 = bitcast <11 x i32> %a to <22 x i16>904  br label %end905 906end:907  %phi = phi <22 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]908  ret <22 x i16> %phi909}910 911define <11 x i32> @bitcast_v22i16_to_v11i32(<22 x i16> %a, i32 %b) {912; SI-LABEL: bitcast_v22i16_to_v11i32:913; SI:       ; %bb.0:914; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)915; SI-NEXT:    v_mov_b32_e32 v28, v10916; SI-NEXT:    v_mov_b32_e32 v27, v8917; SI-NEXT:    v_mov_b32_e32 v26, v6918; SI-NEXT:    v_mov_b32_e32 v25, v4919; SI-NEXT:    v_mov_b32_e32 v24, v2920; SI-NEXT:    v_mov_b32_e32 v23, v0921; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v22922; SI-NEXT:    v_lshlrev_b32_e32 v35, 16, v1923; SI-NEXT:    v_lshlrev_b32_e32 v34, 16, v3924; SI-NEXT:    v_lshlrev_b32_e32 v33, 16, v5925; SI-NEXT:    v_lshlrev_b32_e32 v32, 16, v7926; SI-NEXT:    v_lshlrev_b32_e32 v31, 16, v9927; SI-NEXT:    v_lshlrev_b32_e32 v30, 16, v11928; SI-NEXT:    v_lshlrev_b32_e32 v29, 16, v13929; SI-NEXT:    v_lshlrev_b32_e32 v22, 16, v15930; SI-NEXT:    v_lshlrev_b32_e32 v15, 16, v17931; SI-NEXT:    v_lshlrev_b32_e32 v13, 16, v19932; SI-NEXT:    v_lshlrev_b32_e32 v11, 16, v21933; SI-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10934; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc935; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]936; SI-NEXT:    s_cbranch_execnz .LBB6_3937; SI-NEXT:  ; %bb.1: ; %Flow938; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]939; SI-NEXT:    s_cbranch_execnz .LBB6_4940; SI-NEXT:  .LBB6_2: ; %end941; SI-NEXT:    s_or_b64 exec, exec, s[4:5]942; SI-NEXT:    s_setpc_b64 s[30:31]943; SI-NEXT:  .LBB6_3: ; %cmp.false944; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v23945; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v24946; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v25947; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v26948; SI-NEXT:    v_and_b32_e32 v4, 0xffff, v27949; SI-NEXT:    v_and_b32_e32 v5, 0xffff, v28950; SI-NEXT:    v_and_b32_e32 v6, 0xffff, v12951; SI-NEXT:    v_and_b32_e32 v7, 0xffff, v14952; SI-NEXT:    v_and_b32_e32 v8, 0xffff, v16953; SI-NEXT:    v_and_b32_e32 v9, 0xffff, v18954; SI-NEXT:    v_and_b32_e32 v10, 0xffff, v20955; SI-NEXT:    v_or_b32_e32 v0, v0, v35956; SI-NEXT:    v_or_b32_e32 v1, v1, v34957; SI-NEXT:    v_or_b32_e32 v2, v2, v33958; SI-NEXT:    v_or_b32_e32 v3, v3, v32959; SI-NEXT:    v_or_b32_e32 v4, v4, v31960; SI-NEXT:    v_or_b32_e32 v5, v5, v30961; SI-NEXT:    v_or_b32_e32 v6, v6, v29962; SI-NEXT:    v_or_b32_e32 v7, v7, v22963; SI-NEXT:    v_or_b32_e32 v8, v8, v15964; SI-NEXT:    v_or_b32_e32 v9, v9, v13965; SI-NEXT:    v_or_b32_e32 v10, v10, v11966; SI-NEXT:    ; implicit-def: $vgpr23967; SI-NEXT:    ; implicit-def: $vgpr24968; SI-NEXT:    ; implicit-def: $vgpr25969; SI-NEXT:    ; implicit-def: $vgpr26970; SI-NEXT:    ; implicit-def: $vgpr27971; SI-NEXT:    ; implicit-def: $vgpr28972; SI-NEXT:    ; implicit-def: $vgpr12973; SI-NEXT:    ; implicit-def: $vgpr14974; SI-NEXT:    ; implicit-def: $vgpr16975; SI-NEXT:    ; implicit-def: $vgpr18976; SI-NEXT:    ; implicit-def: $vgpr20977; SI-NEXT:    ; implicit-def: $vgpr35978; SI-NEXT:    ; implicit-def: $vgpr34979; SI-NEXT:    ; implicit-def: $vgpr33980; SI-NEXT:    ; implicit-def: $vgpr32981; SI-NEXT:    ; implicit-def: $vgpr31982; SI-NEXT:    ; implicit-def: $vgpr30983; SI-NEXT:    ; implicit-def: $vgpr29984; SI-NEXT:    ; implicit-def: $vgpr22985; SI-NEXT:    ; implicit-def: $vgpr15986; SI-NEXT:    ; implicit-def: $vgpr13987; SI-NEXT:    ; implicit-def: $vgpr11988; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]989; SI-NEXT:    s_cbranch_execz .LBB6_2990; SI-NEXT:  .LBB6_4: ; %cmp.true991; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v23992; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v24993; SI-NEXT:    v_add_i32_e32 v2, vcc, 3, v25994; SI-NEXT:    v_add_i32_e32 v3, vcc, 3, v26995; SI-NEXT:    v_add_i32_e32 v4, vcc, 3, v27996; SI-NEXT:    v_add_i32_e32 v5, vcc, 3, v28997; SI-NEXT:    v_add_i32_e32 v6, vcc, 3, v12998; SI-NEXT:    v_add_i32_e32 v7, vcc, 3, v14999; SI-NEXT:    v_add_i32_e32 v8, vcc, 3, v161000; SI-NEXT:    v_add_i32_e32 v9, vcc, 3, v181001; SI-NEXT:    v_add_i32_e32 v10, vcc, 3, v201002; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v01003; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v11004; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v21005; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v31006; SI-NEXT:    v_and_b32_e32 v4, 0xffff, v41007; SI-NEXT:    v_and_b32_e32 v5, 0xffff, v51008; SI-NEXT:    v_and_b32_e32 v6, 0xffff, v61009; SI-NEXT:    v_and_b32_e32 v7, 0xffff, v71010; SI-NEXT:    v_and_b32_e32 v8, 0xffff, v81011; SI-NEXT:    v_and_b32_e32 v9, 0xffff, v91012; SI-NEXT:    v_and_b32_e32 v10, 0xffff, v101013; SI-NEXT:    v_or_b32_e32 v0, v35, v01014; SI-NEXT:    s_mov_b32 s6, 0x300001015; SI-NEXT:    v_or_b32_e32 v1, v34, v11016; SI-NEXT:    v_or_b32_e32 v2, v33, v21017; SI-NEXT:    v_or_b32_e32 v3, v32, v31018; SI-NEXT:    v_or_b32_e32 v4, v31, v41019; SI-NEXT:    v_or_b32_e32 v5, v30, v51020; SI-NEXT:    v_or_b32_e32 v6, v29, v61021; SI-NEXT:    v_or_b32_e32 v7, v22, v71022; SI-NEXT:    v_or_b32_e32 v8, v15, v81023; SI-NEXT:    v_or_b32_e32 v9, v13, v91024; SI-NEXT:    v_or_b32_e32 v10, v11, v101025; SI-NEXT:    v_add_i32_e32 v0, vcc, 0x30000, v01026; SI-NEXT:    v_add_i32_e32 v1, vcc, s6, v11027; SI-NEXT:    v_add_i32_e32 v2, vcc, s6, v21028; SI-NEXT:    v_add_i32_e32 v3, vcc, s6, v31029; SI-NEXT:    v_add_i32_e32 v4, vcc, s6, v41030; SI-NEXT:    v_add_i32_e32 v5, vcc, s6, v51031; SI-NEXT:    v_add_i32_e32 v6, vcc, s6, v61032; SI-NEXT:    v_add_i32_e32 v7, vcc, s6, v71033; SI-NEXT:    v_add_i32_e32 v8, vcc, 0x30000, v81034; SI-NEXT:    v_add_i32_e32 v9, vcc, 0x30000, v91035; SI-NEXT:    v_add_i32_e32 v10, vcc, 0x30000, v101036; SI-NEXT:    s_or_b64 exec, exec, s[4:5]1037; SI-NEXT:    s_setpc_b64 s[30:31]1038;1039; VI-LABEL: bitcast_v22i16_to_v11i32:1040; VI:       ; %bb.0:1041; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1042; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v111043; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc1044; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]1045; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1046; VI-NEXT:    s_cbranch_execz .LBB6_21047; VI-NEXT:  ; %bb.1: ; %cmp.true1048; VI-NEXT:    v_mov_b32_e32 v12, 31049; VI-NEXT:    v_add_u16_e32 v11, 3, v101050; VI-NEXT:    v_add_u16_sdwa v10, v10, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1051; VI-NEXT:    v_or_b32_e32 v10, v11, v101052; VI-NEXT:    v_add_u16_e32 v11, 3, v91053; VI-NEXT:    v_add_u16_sdwa v9, v9, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1054; VI-NEXT:    v_or_b32_e32 v9, v11, v91055; VI-NEXT:    v_add_u16_e32 v11, 3, v81056; VI-NEXT:    v_add_u16_sdwa v8, v8, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1057; VI-NEXT:    v_or_b32_e32 v8, v11, v81058; VI-NEXT:    v_add_u16_e32 v11, 3, v71059; VI-NEXT:    v_add_u16_sdwa v7, v7, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1060; VI-NEXT:    v_or_b32_e32 v7, v11, v71061; VI-NEXT:    v_add_u16_e32 v11, 3, v61062; VI-NEXT:    v_add_u16_sdwa v6, v6, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1063; VI-NEXT:    v_or_b32_e32 v6, v11, v61064; VI-NEXT:    v_add_u16_e32 v11, 3, v51065; VI-NEXT:    v_add_u16_sdwa v5, v5, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1066; VI-NEXT:    v_or_b32_e32 v5, v11, v51067; VI-NEXT:    v_add_u16_e32 v11, 3, v41068; VI-NEXT:    v_add_u16_sdwa v4, v4, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1069; VI-NEXT:    v_or_b32_e32 v4, v11, v41070; VI-NEXT:    v_add_u16_e32 v11, 3, v31071; VI-NEXT:    v_add_u16_sdwa v3, v3, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1072; VI-NEXT:    v_or_b32_e32 v3, v11, v31073; VI-NEXT:    v_add_u16_e32 v11, 3, v21074; VI-NEXT:    v_add_u16_sdwa v2, v2, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1075; VI-NEXT:    v_or_b32_e32 v2, v11, v21076; VI-NEXT:    v_add_u16_e32 v11, 3, v11077; VI-NEXT:    v_add_u16_sdwa v1, v1, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1078; VI-NEXT:    v_or_b32_e32 v1, v11, v11079; VI-NEXT:    v_add_u16_e32 v11, 3, v01080; VI-NEXT:    v_add_u16_sdwa v0, v0, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1081; VI-NEXT:    v_or_b32_e32 v0, v11, v01082; VI-NEXT:  .LBB6_2: ; %end1083; VI-NEXT:    s_or_b64 exec, exec, s[4:5]1084; VI-NEXT:    s_setpc_b64 s[30:31]1085;1086; GFX9-LABEL: bitcast_v22i16_to_v11i32:1087; GFX9:       ; %bb.0:1088; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1089; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v111090; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc1091; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]1092; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1093; GFX9-NEXT:    s_cbranch_execz .LBB6_21094; GFX9-NEXT:  ; %bb.1: ; %cmp.true1095; GFX9-NEXT:    v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]1096; GFX9-NEXT:    v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]1097; GFX9-NEXT:    v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]1098; GFX9-NEXT:    v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]1099; GFX9-NEXT:    v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]1100; GFX9-NEXT:    v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]1101; GFX9-NEXT:    v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]1102; GFX9-NEXT:    v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]1103; GFX9-NEXT:    v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]1104; GFX9-NEXT:    v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]1105; GFX9-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]1106; GFX9-NEXT:  .LBB6_2: ; %end1107; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]1108; GFX9-NEXT:    s_setpc_b64 s[30:31]1109;1110; GFX11-LABEL: bitcast_v22i16_to_v11i32:1111; GFX11:       ; %bb.0:1112; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1113; GFX11-NEXT:    s_mov_b32 s0, exec_lo1114; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v111115; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s01116; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)1117; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s01118; GFX11-NEXT:    s_cbranch_execz .LBB6_21119; GFX11-NEXT:  ; %bb.1: ; %cmp.true1120; GFX11-NEXT:    v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]1121; GFX11-NEXT:    v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]1122; GFX11-NEXT:    v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]1123; GFX11-NEXT:    v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]1124; GFX11-NEXT:    v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]1125; GFX11-NEXT:    v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]1126; GFX11-NEXT:    v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]1127; GFX11-NEXT:    v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]1128; GFX11-NEXT:    v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]1129; GFX11-NEXT:    v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]1130; GFX11-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]1131; GFX11-NEXT:  .LBB6_2: ; %end1132; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s01133; GFX11-NEXT:    s_setpc_b64 s[30:31]1134  %cmp = icmp eq i32 %b, 01135  br i1 %cmp, label %cmp.true, label %cmp.false1136 1137cmp.true:1138  %a1 = add <22 x i16> %a, splat (i16 3)1139  %a2 = bitcast <22 x i16> %a1 to <11 x i32>1140  br label %end1141 1142cmp.false:1143  %a3 = bitcast <22 x i16> %a to <11 x i32>1144  br label %end1145 1146end:1147  %phi = phi <11 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]1148  ret <11 x i32> %phi1149}1150 1151define inreg <11 x i32> @bitcast_v22i16_to_v11i32_scalar(<22 x i16> inreg %a, i32 inreg %b) {1152; SI-LABEL: bitcast_v22i16_to_v11i32_scalar:1153; SI:       ; %bb.0:1154; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1155; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v81156; SI-NEXT:    v_mov_b32_e32 v11, v61157; SI-NEXT:    v_mov_b32_e32 v12, v41158; SI-NEXT:    v_mov_b32_e32 v13, v21159; SI-NEXT:    v_mov_b32_e32 v14, v01160; SI-NEXT:    s_and_b64 s[4:5], vcc, exec1161; SI-NEXT:    v_lshlrev_b32_e32 v18, 16, v11162; SI-NEXT:    v_lshlrev_b32_e32 v17, 16, v31163; SI-NEXT:    v_lshlrev_b32_e32 v16, 16, v51164; SI-NEXT:    v_lshlrev_b32_e32 v15, 16, v71165; SI-NEXT:    s_cbranch_scc0 .LBB7_41166; SI-NEXT:  ; %bb.1: ; %cmp.false1167; SI-NEXT:    s_and_b32 s4, s16, 0xffff1168; SI-NEXT:    s_lshl_b32 s5, s17, 161169; SI-NEXT:    s_or_b32 s4, s4, s51170; SI-NEXT:    s_and_b32 s5, s18, 0xffff1171; SI-NEXT:    s_lshl_b32 s6, s19, 161172; SI-NEXT:    s_or_b32 s5, s5, s61173; SI-NEXT:    s_and_b32 s6, s20, 0xffff1174; SI-NEXT:    s_lshl_b32 s7, s21, 161175; SI-NEXT:    s_or_b32 s6, s6, s71176; SI-NEXT:    s_and_b32 s7, s22, 0xffff1177; SI-NEXT:    s_lshl_b32 s8, s23, 161178; SI-NEXT:    s_or_b32 s7, s7, s81179; SI-NEXT:    s_and_b32 s8, s24, 0xffff1180; SI-NEXT:    s_lshl_b32 s9, s25, 161181; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v141182; SI-NEXT:    s_or_b32 s8, s8, s91183; SI-NEXT:    s_and_b32 s9, s26, 0xffff1184; SI-NEXT:    s_lshl_b32 s10, s27, 161185; SI-NEXT:    v_or_b32_e32 v7, v0, v181186; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v131187; SI-NEXT:    s_or_b32 s9, s9, s101188; SI-NEXT:    s_and_b32 s10, s28, 0xffff1189; SI-NEXT:    s_lshl_b32 s11, s29, 161190; SI-NEXT:    v_or_b32_e32 v8, v0, v171191; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v121192; SI-NEXT:    s_or_b32 s10, s10, s111193; SI-NEXT:    v_or_b32_e32 v9, v0, v161194; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v111195; SI-NEXT:    v_or_b32_e32 v10, v0, v151196; SI-NEXT:    v_mov_b32_e32 v0, s41197; SI-NEXT:    v_mov_b32_e32 v1, s51198; SI-NEXT:    v_mov_b32_e32 v2, s61199; SI-NEXT:    v_mov_b32_e32 v3, s71200; SI-NEXT:    v_mov_b32_e32 v4, s81201; SI-NEXT:    v_mov_b32_e32 v5, s91202; SI-NEXT:    v_mov_b32_e32 v6, s101203; SI-NEXT:    s_cbranch_execnz .LBB7_31204; SI-NEXT:  .LBB7_2: ; %cmp.true1205; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v141206; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v01207; SI-NEXT:    s_add_i32 s16, s16, 31208; SI-NEXT:    v_or_b32_e32 v0, v18, v01209; SI-NEXT:    s_and_b32 s4, s16, 0xffff1210; SI-NEXT:    s_lshl_b32 s5, s17, 161211; SI-NEXT:    s_add_i32 s18, s18, 31212; SI-NEXT:    v_add_i32_e32 v7, vcc, 0x30000, v01213; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v131214; SI-NEXT:    s_or_b32 s4, s5, s41215; SI-NEXT:    s_and_b32 s5, s18, 0xffff1216; SI-NEXT:    s_lshl_b32 s6, s19, 161217; SI-NEXT:    s_add_i32 s20, s20, 31218; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v01219; SI-NEXT:    s_or_b32 s5, s6, s51220; SI-NEXT:    s_and_b32 s6, s20, 0xffff1221; SI-NEXT:    s_lshl_b32 s7, s21, 161222; SI-NEXT:    s_add_i32 s22, s22, 31223; SI-NEXT:    v_or_b32_e32 v0, v17, v01224; SI-NEXT:    s_or_b32 s6, s7, s61225; SI-NEXT:    s_and_b32 s7, s22, 0xffff1226; SI-NEXT:    s_lshl_b32 s8, s23, 161227; SI-NEXT:    s_add_i32 s24, s24, 31228; SI-NEXT:    v_add_i32_e32 v8, vcc, 0x30000, v01229; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v121230; SI-NEXT:    s_or_b32 s7, s8, s71231; SI-NEXT:    s_and_b32 s8, s24, 0xffff1232; SI-NEXT:    s_lshl_b32 s9, s25, 161233; SI-NEXT:    s_add_i32 s26, s26, 31234; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v01235; SI-NEXT:    s_or_b32 s8, s9, s81236; SI-NEXT:    s_and_b32 s9, s26, 0xffff1237; SI-NEXT:    s_lshl_b32 s10, s27, 161238; SI-NEXT:    s_add_i32 s28, s28, 31239; SI-NEXT:    v_or_b32_e32 v0, v16, v01240; SI-NEXT:    s_or_b32 s9, s10, s91241; SI-NEXT:    s_and_b32 s10, s28, 0xffff1242; SI-NEXT:    s_lshl_b32 s11, s29, 161243; SI-NEXT:    v_add_i32_e32 v9, vcc, 0x30000, v01244; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v111245; SI-NEXT:    s_or_b32 s10, s11, s101246; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v01247; SI-NEXT:    s_add_i32 s4, s4, 0x300001248; SI-NEXT:    s_add_i32 s5, s5, 0x300001249; SI-NEXT:    s_add_i32 s6, s6, 0x300001250; SI-NEXT:    s_add_i32 s7, s7, 0x300001251; SI-NEXT:    s_add_i32 s8, s8, 0x300001252; SI-NEXT:    s_add_i32 s9, s9, 0x300001253; SI-NEXT:    s_add_i32 s10, s10, 0x300001254; SI-NEXT:    v_or_b32_e32 v0, v15, v01255; SI-NEXT:    v_add_i32_e32 v10, vcc, 0x30000, v01256; SI-NEXT:    v_mov_b32_e32 v0, s41257; SI-NEXT:    v_mov_b32_e32 v1, s51258; SI-NEXT:    v_mov_b32_e32 v2, s61259; SI-NEXT:    v_mov_b32_e32 v3, s71260; SI-NEXT:    v_mov_b32_e32 v4, s81261; SI-NEXT:    v_mov_b32_e32 v5, s91262; SI-NEXT:    v_mov_b32_e32 v6, s101263; SI-NEXT:  .LBB7_3: ; %end1264; SI-NEXT:    s_setpc_b64 s[30:31]1265; SI-NEXT:  .LBB7_4:1266; SI-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr101267; SI-NEXT:    s_branch .LBB7_21268;1269; VI-LABEL: bitcast_v22i16_to_v11i32_scalar:1270; VI:       ; %bb.0:1271; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1272; VI-NEXT:    s_cmp_lg_u32 s27, 01273; VI-NEXT:    s_cbranch_scc0 .LBB7_41274; VI-NEXT:  ; %bb.1: ; %cmp.false1275; VI-NEXT:    s_cbranch_execnz .LBB7_31276; VI-NEXT:  .LBB7_2: ; %cmp.true1277; VI-NEXT:    s_add_i32 s5, s26, 31278; VI-NEXT:    s_and_b32 s4, s26, 0xffff00001279; VI-NEXT:    s_and_b32 s5, s5, 0xffff1280; VI-NEXT:    s_or_b32 s4, s4, s51281; VI-NEXT:    s_add_i32 s5, s25, 31282; VI-NEXT:    s_add_i32 s26, s4, 0x300001283; VI-NEXT:    s_and_b32 s4, s25, 0xffff00001284; VI-NEXT:    s_and_b32 s5, s5, 0xffff1285; VI-NEXT:    s_or_b32 s4, s4, s51286; VI-NEXT:    s_add_i32 s5, s24, 31287; VI-NEXT:    s_add_i32 s25, s4, 0x300001288; VI-NEXT:    s_and_b32 s4, s24, 0xffff00001289; VI-NEXT:    s_and_b32 s5, s5, 0xffff1290; VI-NEXT:    s_or_b32 s4, s4, s51291; VI-NEXT:    s_add_i32 s5, s23, 31292; VI-NEXT:    s_add_i32 s24, s4, 0x300001293; VI-NEXT:    s_and_b32 s4, s23, 0xffff00001294; VI-NEXT:    s_and_b32 s5, s5, 0xffff1295; VI-NEXT:    s_or_b32 s4, s4, s51296; VI-NEXT:    s_add_i32 s5, s22, 31297; VI-NEXT:    s_add_i32 s23, s4, 0x300001298; VI-NEXT:    s_and_b32 s4, s22, 0xffff00001299; VI-NEXT:    s_and_b32 s5, s5, 0xffff1300; VI-NEXT:    s_or_b32 s4, s4, s51301; VI-NEXT:    s_add_i32 s5, s21, 31302; VI-NEXT:    s_add_i32 s22, s4, 0x300001303; VI-NEXT:    s_and_b32 s4, s21, 0xffff00001304; VI-NEXT:    s_and_b32 s5, s5, 0xffff1305; VI-NEXT:    s_or_b32 s4, s4, s51306; VI-NEXT:    s_add_i32 s5, s20, 31307; VI-NEXT:    s_add_i32 s21, s4, 0x300001308; VI-NEXT:    s_and_b32 s4, s20, 0xffff00001309; VI-NEXT:    s_and_b32 s5, s5, 0xffff1310; VI-NEXT:    s_or_b32 s4, s4, s51311; VI-NEXT:    s_add_i32 s5, s19, 31312; VI-NEXT:    s_add_i32 s20, s4, 0x300001313; VI-NEXT:    s_and_b32 s4, s19, 0xffff00001314; VI-NEXT:    s_and_b32 s5, s5, 0xffff1315; VI-NEXT:    s_or_b32 s4, s4, s51316; VI-NEXT:    s_add_i32 s5, s18, 31317; VI-NEXT:    s_add_i32 s19, s4, 0x300001318; VI-NEXT:    s_and_b32 s4, s18, 0xffff00001319; VI-NEXT:    s_and_b32 s5, s5, 0xffff1320; VI-NEXT:    s_or_b32 s4, s4, s51321; VI-NEXT:    s_add_i32 s5, s17, 31322; VI-NEXT:    s_add_i32 s18, s4, 0x300001323; VI-NEXT:    s_and_b32 s4, s17, 0xffff00001324; VI-NEXT:    s_and_b32 s5, s5, 0xffff1325; VI-NEXT:    s_or_b32 s4, s4, s51326; VI-NEXT:    s_add_i32 s5, s16, 31327; VI-NEXT:    s_add_i32 s17, s4, 0x300001328; VI-NEXT:    s_and_b32 s4, s16, 0xffff00001329; VI-NEXT:    s_and_b32 s5, s5, 0xffff1330; VI-NEXT:    s_or_b32 s4, s4, s51331; VI-NEXT:    s_add_i32 s16, s4, 0x300001332; VI-NEXT:  .LBB7_3: ; %end1333; VI-NEXT:    v_mov_b32_e32 v0, s161334; VI-NEXT:    v_mov_b32_e32 v1, s171335; VI-NEXT:    v_mov_b32_e32 v2, s181336; VI-NEXT:    v_mov_b32_e32 v3, s191337; VI-NEXT:    v_mov_b32_e32 v4, s201338; VI-NEXT:    v_mov_b32_e32 v5, s211339; VI-NEXT:    v_mov_b32_e32 v6, s221340; VI-NEXT:    v_mov_b32_e32 v7, s231341; VI-NEXT:    v_mov_b32_e32 v8, s241342; VI-NEXT:    v_mov_b32_e32 v9, s251343; VI-NEXT:    v_mov_b32_e32 v10, s261344; VI-NEXT:    s_setpc_b64 s[30:31]1345; VI-NEXT:  .LBB7_4:1346; VI-NEXT:    s_branch .LBB7_21347;1348; GFX9-LABEL: bitcast_v22i16_to_v11i32_scalar:1349; GFX9:       ; %bb.0:1350; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1351; GFX9-NEXT:    s_cmp_lg_u32 s27, 01352; GFX9-NEXT:    s_cbranch_scc0 .LBB7_31353; GFX9-NEXT:  ; %bb.1: ; %cmp.false1354; GFX9-NEXT:    s_cbranch_execnz .LBB7_41355; GFX9-NEXT:  .LBB7_2: ; %cmp.true1356; GFX9-NEXT:    v_pk_add_u16 v10, s26, 3 op_sel_hi:[1,0]1357; GFX9-NEXT:    v_pk_add_u16 v9, s25, 3 op_sel_hi:[1,0]1358; GFX9-NEXT:    v_pk_add_u16 v8, s24, 3 op_sel_hi:[1,0]1359; GFX9-NEXT:    v_pk_add_u16 v7, s23, 3 op_sel_hi:[1,0]1360; GFX9-NEXT:    v_pk_add_u16 v6, s22, 3 op_sel_hi:[1,0]1361; GFX9-NEXT:    v_pk_add_u16 v5, s21, 3 op_sel_hi:[1,0]1362; GFX9-NEXT:    v_pk_add_u16 v4, s20, 3 op_sel_hi:[1,0]1363; GFX9-NEXT:    v_pk_add_u16 v3, s19, 3 op_sel_hi:[1,0]1364; GFX9-NEXT:    v_pk_add_u16 v2, s18, 3 op_sel_hi:[1,0]1365; GFX9-NEXT:    v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]1366; GFX9-NEXT:    v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]1367; GFX9-NEXT:    s_setpc_b64 s[30:31]1368; GFX9-NEXT:  .LBB7_3:1369; GFX9-NEXT:    s_branch .LBB7_21370; GFX9-NEXT:  .LBB7_4:1371; GFX9-NEXT:    v_mov_b32_e32 v0, s161372; GFX9-NEXT:    v_mov_b32_e32 v1, s171373; GFX9-NEXT:    v_mov_b32_e32 v2, s181374; GFX9-NEXT:    v_mov_b32_e32 v3, s191375; GFX9-NEXT:    v_mov_b32_e32 v4, s201376; GFX9-NEXT:    v_mov_b32_e32 v5, s211377; GFX9-NEXT:    v_mov_b32_e32 v6, s221378; GFX9-NEXT:    v_mov_b32_e32 v7, s231379; GFX9-NEXT:    v_mov_b32_e32 v8, s241380; GFX9-NEXT:    v_mov_b32_e32 v9, s251381; GFX9-NEXT:    v_mov_b32_e32 v10, s261382; GFX9-NEXT:    s_setpc_b64 s[30:31]1383;1384; GFX11-LABEL: bitcast_v22i16_to_v11i32_scalar:1385; GFX11:       ; %bb.0:1386; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1387; GFX11-NEXT:    s_mov_b32 s15, s31388; GFX11-NEXT:    s_mov_b32 s14, s21389; GFX11-NEXT:    s_mov_b32 s13, s11390; GFX11-NEXT:    s_mov_b32 s12, s01391; GFX11-NEXT:    s_cmp_lg_u32 s23, 01392; GFX11-NEXT:    s_mov_b32 s0, 01393; GFX11-NEXT:    s_cbranch_scc0 .LBB7_31394; GFX11-NEXT:  ; %bb.1: ; %Flow1395; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s01396; GFX11-NEXT:    s_cbranch_vccnz .LBB7_41397; GFX11-NEXT:  .LBB7_2: ; %cmp.true1398; GFX11-NEXT:    v_pk_add_u16 v10, s22, 3 op_sel_hi:[1,0]1399; GFX11-NEXT:    v_pk_add_u16 v9, s21, 3 op_sel_hi:[1,0]1400; GFX11-NEXT:    v_pk_add_u16 v8, s20, 3 op_sel_hi:[1,0]1401; GFX11-NEXT:    v_pk_add_u16 v7, s19, 3 op_sel_hi:[1,0]1402; GFX11-NEXT:    v_pk_add_u16 v6, s18, 3 op_sel_hi:[1,0]1403; GFX11-NEXT:    v_pk_add_u16 v5, s17, 3 op_sel_hi:[1,0]1404; GFX11-NEXT:    v_pk_add_u16 v4, s16, 3 op_sel_hi:[1,0]1405; GFX11-NEXT:    v_pk_add_u16 v3, s15, 3 op_sel_hi:[1,0]1406; GFX11-NEXT:    v_pk_add_u16 v2, s14, 3 op_sel_hi:[1,0]1407; GFX11-NEXT:    v_pk_add_u16 v1, s13, 3 op_sel_hi:[1,0]1408; GFX11-NEXT:    v_pk_add_u16 v0, s12, 3 op_sel_hi:[1,0]1409; GFX11-NEXT:    s_setpc_b64 s[30:31]1410; GFX11-NEXT:  .LBB7_3:1411; GFX11-NEXT:    s_branch .LBB7_21412; GFX11-NEXT:  .LBB7_4:1413; GFX11-NEXT:    v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s131414; GFX11-NEXT:    v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s151415; GFX11-NEXT:    v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s171416; GFX11-NEXT:    v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s191417; GFX11-NEXT:    v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s211418; GFX11-NEXT:    v_mov_b32_e32 v10, s221419; GFX11-NEXT:    s_setpc_b64 s[30:31]1420  %cmp = icmp eq i32 %b, 01421  br i1 %cmp, label %cmp.true, label %cmp.false1422 1423cmp.true:1424  %a1 = add <22 x i16> %a, splat (i16 3)1425  %a2 = bitcast <22 x i16> %a1 to <11 x i32>1426  br label %end1427 1428cmp.false:1429  %a3 = bitcast <22 x i16> %a to <11 x i32>1430  br label %end1431 1432end:1433  %phi = phi <11 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]1434  ret <11 x i32> %phi1435}1436 1437define <22 x half> @bitcast_v11i32_to_v22f16(<11 x i32> %a, i32 %b) {1438; SI-LABEL: bitcast_v11i32_to_v22f16:1439; SI:       ; %bb.0:1440; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1441; SI-NEXT:    v_mov_b32_e32 v32, v101442; SI-NEXT:    v_mov_b32_e32 v31, v91443; SI-NEXT:    v_mov_b32_e32 v30, v81444; SI-NEXT:    v_mov_b32_e32 v29, v71445; SI-NEXT:    v_mov_b32_e32 v28, v61446; SI-NEXT:    v_mov_b32_e32 v27, v51447; SI-NEXT:    v_mov_b32_e32 v26, v41448; SI-NEXT:    v_mov_b32_e32 v25, v31449; SI-NEXT:    v_mov_b32_e32 v24, v21450; SI-NEXT:    v_mov_b32_e32 v23, v11451; SI-NEXT:    v_mov_b32_e32 v22, v01452; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v111453; SI-NEXT:    ; implicit-def: $vgpr01454; SI-NEXT:    ; implicit-def: $vgpr11455; SI-NEXT:    ; implicit-def: $vgpr21456; SI-NEXT:    ; implicit-def: $vgpr31457; SI-NEXT:    ; implicit-def: $vgpr41458; SI-NEXT:    ; implicit-def: $vgpr51459; SI-NEXT:    ; implicit-def: $vgpr61460; SI-NEXT:    ; implicit-def: $vgpr71461; SI-NEXT:    ; implicit-def: $vgpr81462; SI-NEXT:    ; implicit-def: $vgpr91463; SI-NEXT:    ; implicit-def: $vgpr101464; SI-NEXT:    ; implicit-def: $vgpr111465; SI-NEXT:    ; implicit-def: $vgpr121466; SI-NEXT:    ; implicit-def: $vgpr131467; SI-NEXT:    ; implicit-def: $vgpr141468; SI-NEXT:    ; implicit-def: $vgpr151469; SI-NEXT:    ; implicit-def: $vgpr161470; SI-NEXT:    ; implicit-def: $vgpr171471; SI-NEXT:    ; implicit-def: $vgpr181472; SI-NEXT:    ; implicit-def: $vgpr191473; SI-NEXT:    ; implicit-def: $vgpr201474; SI-NEXT:    ; implicit-def: $vgpr211475; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc1476; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]1477; SI-NEXT:    s_cbranch_execnz .LBB8_31478; SI-NEXT:  ; %bb.1: ; %Flow1479; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1480; SI-NEXT:    s_cbranch_execnz .LBB8_41481; SI-NEXT:  .LBB8_2: ; %end1482; SI-NEXT:    s_or_b64 exec, exec, s[4:5]1483; SI-NEXT:    s_setpc_b64 s[30:31]1484; SI-NEXT:  .LBB8_3: ; %cmp.false1485; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v321486; SI-NEXT:    v_cvt_f32_f16_e32 v21, v01487; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v311488; SI-NEXT:    v_cvt_f32_f16_e32 v19, v01489; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v301490; SI-NEXT:    v_cvt_f32_f16_e32 v17, v01491; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v291492; SI-NEXT:    v_cvt_f32_f16_e32 v15, v01493; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v281494; SI-NEXT:    v_cvt_f32_f16_e32 v13, v01495; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v271496; SI-NEXT:    v_cvt_f32_f16_e32 v11, v01497; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v261498; SI-NEXT:    v_cvt_f32_f16_e32 v9, v01499; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v251500; SI-NEXT:    v_cvt_f32_f16_e32 v7, v01501; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v241502; SI-NEXT:    v_cvt_f32_f16_e32 v5, v01503; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v231504; SI-NEXT:    v_cvt_f32_f16_e32 v3, v01505; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v221506; SI-NEXT:    v_cvt_f32_f16_e32 v1, v01507; SI-NEXT:    v_cvt_f32_f16_e32 v20, v321508; SI-NEXT:    v_cvt_f32_f16_e32 v18, v311509; SI-NEXT:    v_cvt_f32_f16_e32 v16, v301510; SI-NEXT:    v_cvt_f32_f16_e32 v14, v291511; SI-NEXT:    v_cvt_f32_f16_e32 v12, v281512; SI-NEXT:    v_cvt_f32_f16_e32 v10, v271513; SI-NEXT:    v_cvt_f32_f16_e32 v8, v261514; SI-NEXT:    v_cvt_f32_f16_e32 v6, v251515; SI-NEXT:    v_cvt_f32_f16_e32 v4, v241516; SI-NEXT:    v_cvt_f32_f16_e32 v2, v231517; SI-NEXT:    v_cvt_f32_f16_e32 v0, v221518; SI-NEXT:    ; implicit-def: $vgpr221519; SI-NEXT:    ; implicit-def: $vgpr231520; SI-NEXT:    ; implicit-def: $vgpr241521; SI-NEXT:    ; implicit-def: $vgpr251522; SI-NEXT:    ; implicit-def: $vgpr261523; SI-NEXT:    ; implicit-def: $vgpr271524; SI-NEXT:    ; implicit-def: $vgpr281525; SI-NEXT:    ; implicit-def: $vgpr291526; SI-NEXT:    ; implicit-def: $vgpr301527; SI-NEXT:    ; implicit-def: $vgpr311528; SI-NEXT:    ; implicit-def: $vgpr321529; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1530; SI-NEXT:    s_cbranch_execz .LBB8_21531; SI-NEXT:  .LBB8_4: ; %cmp.true1532; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v221533; SI-NEXT:    v_add_i32_e32 v3, vcc, 3, v231534; SI-NEXT:    v_add_i32_e32 v5, vcc, 3, v241535; SI-NEXT:    v_add_i32_e32 v7, vcc, 3, v251536; SI-NEXT:    v_add_i32_e32 v9, vcc, 3, v261537; SI-NEXT:    v_add_i32_e32 v11, vcc, 3, v271538; SI-NEXT:    v_add_i32_e32 v13, vcc, 3, v281539; SI-NEXT:    v_add_i32_e32 v15, vcc, 3, v291540; SI-NEXT:    v_add_i32_e32 v17, vcc, 3, v301541; SI-NEXT:    v_add_i32_e32 v19, vcc, 3, v311542; SI-NEXT:    v_add_i32_e32 v21, vcc, 3, v321543; SI-NEXT:    v_cvt_f32_f16_e32 v20, v211544; SI-NEXT:    v_cvt_f32_f16_e32 v18, v191545; SI-NEXT:    v_cvt_f32_f16_e32 v16, v171546; SI-NEXT:    v_cvt_f32_f16_e32 v14, v151547; SI-NEXT:    v_cvt_f32_f16_e32 v12, v131548; SI-NEXT:    v_cvt_f32_f16_e32 v10, v111549; SI-NEXT:    v_cvt_f32_f16_e32 v8, v91550; SI-NEXT:    v_cvt_f32_f16_e32 v6, v71551; SI-NEXT:    v_cvt_f32_f16_e32 v4, v51552; SI-NEXT:    v_cvt_f32_f16_e32 v2, v31553; SI-NEXT:    v_cvt_f32_f16_e32 v0, v11554; SI-NEXT:    v_lshrrev_b32_e32 v21, 16, v211555; SI-NEXT:    v_lshrrev_b32_e32 v19, 16, v191556; SI-NEXT:    v_lshrrev_b32_e32 v17, 16, v171557; SI-NEXT:    v_lshrrev_b32_e32 v15, 16, v151558; SI-NEXT:    v_lshrrev_b32_e32 v13, 16, v131559; SI-NEXT:    v_lshrrev_b32_e32 v11, 16, v111560; SI-NEXT:    v_lshrrev_b32_e32 v9, 16, v91561; SI-NEXT:    v_lshrrev_b32_e32 v7, 16, v71562; SI-NEXT:    v_lshrrev_b32_e32 v5, 16, v51563; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v31564; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v11565; SI-NEXT:    v_cvt_f32_f16_e32 v21, v211566; SI-NEXT:    v_cvt_f32_f16_e32 v19, v191567; SI-NEXT:    v_cvt_f32_f16_e32 v17, v171568; SI-NEXT:    v_cvt_f32_f16_e32 v15, v151569; SI-NEXT:    v_cvt_f32_f16_e32 v13, v131570; SI-NEXT:    v_cvt_f32_f16_e32 v11, v111571; SI-NEXT:    v_cvt_f32_f16_e32 v9, v91572; SI-NEXT:    v_cvt_f32_f16_e32 v7, v71573; SI-NEXT:    v_cvt_f32_f16_e32 v5, v51574; SI-NEXT:    v_cvt_f32_f16_e32 v3, v31575; SI-NEXT:    v_cvt_f32_f16_e32 v1, v11576; SI-NEXT:    s_or_b64 exec, exec, s[4:5]1577; SI-NEXT:    s_setpc_b64 s[30:31]1578;1579; VI-LABEL: bitcast_v11i32_to_v22f16:1580; VI:       ; %bb.0:1581; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1582; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v111583; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc1584; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]1585; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1586; VI-NEXT:    s_cbranch_execz .LBB8_21587; VI-NEXT:  ; %bb.1: ; %cmp.true1588; VI-NEXT:    v_add_u32_e32 v10, vcc, 3, v101589; VI-NEXT:    v_add_u32_e32 v9, vcc, 3, v91590; VI-NEXT:    v_add_u32_e32 v8, vcc, 3, v81591; VI-NEXT:    v_add_u32_e32 v7, vcc, 3, v71592; VI-NEXT:    v_add_u32_e32 v6, vcc, 3, v61593; VI-NEXT:    v_add_u32_e32 v5, vcc, 3, v51594; VI-NEXT:    v_add_u32_e32 v4, vcc, 3, v41595; VI-NEXT:    v_add_u32_e32 v3, vcc, 3, v31596; VI-NEXT:    v_add_u32_e32 v2, vcc, 3, v21597; VI-NEXT:    v_add_u32_e32 v1, vcc, 3, v11598; VI-NEXT:    v_add_u32_e32 v0, vcc, 3, v01599; VI-NEXT:  .LBB8_2: ; %end1600; VI-NEXT:    s_or_b64 exec, exec, s[4:5]1601; VI-NEXT:    s_setpc_b64 s[30:31]1602;1603; GFX9-LABEL: bitcast_v11i32_to_v22f16:1604; GFX9:       ; %bb.0:1605; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1606; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v111607; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc1608; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]1609; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1610; GFX9-NEXT:    s_cbranch_execz .LBB8_21611; GFX9-NEXT:  ; %bb.1: ; %cmp.true1612; GFX9-NEXT:    v_add_u32_e32 v10, 3, v101613; GFX9-NEXT:    v_add_u32_e32 v9, 3, v91614; GFX9-NEXT:    v_add_u32_e32 v8, 3, v81615; GFX9-NEXT:    v_add_u32_e32 v7, 3, v71616; GFX9-NEXT:    v_add_u32_e32 v6, 3, v61617; GFX9-NEXT:    v_add_u32_e32 v5, 3, v51618; GFX9-NEXT:    v_add_u32_e32 v4, 3, v41619; GFX9-NEXT:    v_add_u32_e32 v3, 3, v31620; GFX9-NEXT:    v_add_u32_e32 v2, 3, v21621; GFX9-NEXT:    v_add_u32_e32 v1, 3, v11622; GFX9-NEXT:    v_add_u32_e32 v0, 3, v01623; GFX9-NEXT:  .LBB8_2: ; %end1624; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]1625; GFX9-NEXT:    s_setpc_b64 s[30:31]1626;1627; GFX11-LABEL: bitcast_v11i32_to_v22f16:1628; GFX11:       ; %bb.0:1629; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1630; GFX11-NEXT:    s_mov_b32 s0, exec_lo1631; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v111632; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s01633; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)1634; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s01635; GFX11-NEXT:    s_cbranch_execz .LBB8_21636; GFX11-NEXT:  ; %bb.1: ; %cmp.true1637; GFX11-NEXT:    v_add_nc_u32_e32 v10, 3, v101638; GFX11-NEXT:    v_add_nc_u32_e32 v9, 3, v91639; GFX11-NEXT:    v_add_nc_u32_e32 v8, 3, v81640; GFX11-NEXT:    v_add_nc_u32_e32 v7, 3, v71641; GFX11-NEXT:    v_add_nc_u32_e32 v6, 3, v61642; GFX11-NEXT:    v_add_nc_u32_e32 v5, 3, v51643; GFX11-NEXT:    v_add_nc_u32_e32 v4, 3, v41644; GFX11-NEXT:    v_add_nc_u32_e32 v3, 3, v31645; GFX11-NEXT:    v_add_nc_u32_e32 v2, 3, v21646; GFX11-NEXT:    v_add_nc_u32_e32 v1, 3, v11647; GFX11-NEXT:    v_add_nc_u32_e32 v0, 3, v01648; GFX11-NEXT:  .LBB8_2: ; %end1649; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s01650; GFX11-NEXT:    s_setpc_b64 s[30:31]1651  %cmp = icmp eq i32 %b, 01652  br i1 %cmp, label %cmp.true, label %cmp.false1653 1654cmp.true:1655  %a1 = add <11 x i32> %a, splat (i32 3)1656  %a2 = bitcast <11 x i32> %a1 to <22 x half>1657  br label %end1658 1659cmp.false:1660  %a3 = bitcast <11 x i32> %a to <22 x half>1661  br label %end1662 1663end:1664  %phi = phi <22 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]1665  ret <22 x half> %phi1666}1667 1668define inreg <22 x half> @bitcast_v11i32_to_v22f16_scalar(<11 x i32> inreg %a, i32 inreg %b) {1669; SI-LABEL: bitcast_v11i32_to_v22f16_scalar:1670; SI:       ; %bb.0:1671; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1672; SI-NEXT:    s_cmp_lg_u32 s27, 01673; SI-NEXT:    s_cbranch_scc0 .LBB9_41674; SI-NEXT:  ; %bb.1: ; %cmp.false1675; SI-NEXT:    s_lshr_b32 s4, s26, 161676; SI-NEXT:    v_cvt_f32_f16_e32 v21, s41677; SI-NEXT:    s_lshr_b32 s4, s25, 161678; SI-NEXT:    v_cvt_f32_f16_e32 v19, s41679; SI-NEXT:    s_lshr_b32 s4, s24, 161680; SI-NEXT:    v_cvt_f32_f16_e32 v17, s41681; SI-NEXT:    s_lshr_b32 s4, s23, 161682; SI-NEXT:    v_cvt_f32_f16_e32 v15, s41683; SI-NEXT:    s_lshr_b32 s4, s22, 161684; SI-NEXT:    v_cvt_f32_f16_e32 v13, s41685; SI-NEXT:    s_lshr_b32 s4, s21, 161686; SI-NEXT:    v_cvt_f32_f16_e32 v11, s41687; SI-NEXT:    s_lshr_b32 s4, s20, 161688; SI-NEXT:    v_cvt_f32_f16_e32 v9, s41689; SI-NEXT:    s_lshr_b32 s4, s19, 161690; SI-NEXT:    v_cvt_f32_f16_e32 v7, s41691; SI-NEXT:    s_lshr_b32 s4, s18, 161692; SI-NEXT:    v_cvt_f32_f16_e32 v5, s41693; SI-NEXT:    s_lshr_b32 s4, s17, 161694; SI-NEXT:    v_cvt_f32_f16_e32 v3, s41695; SI-NEXT:    s_lshr_b32 s4, s16, 161696; SI-NEXT:    v_cvt_f32_f16_e32 v1, s41697; SI-NEXT:    v_cvt_f32_f16_e32 v20, s261698; SI-NEXT:    v_cvt_f32_f16_e32 v18, s251699; SI-NEXT:    v_cvt_f32_f16_e32 v16, s241700; SI-NEXT:    v_cvt_f32_f16_e32 v14, s231701; SI-NEXT:    v_cvt_f32_f16_e32 v12, s221702; SI-NEXT:    v_cvt_f32_f16_e32 v10, s211703; SI-NEXT:    v_cvt_f32_f16_e32 v8, s201704; SI-NEXT:    v_cvt_f32_f16_e32 v6, s191705; SI-NEXT:    v_cvt_f32_f16_e32 v4, s181706; SI-NEXT:    v_cvt_f32_f16_e32 v2, s171707; SI-NEXT:    v_cvt_f32_f16_e32 v0, s161708; SI-NEXT:    s_cbranch_execnz .LBB9_31709; SI-NEXT:  .LBB9_2: ; %cmp.true1710; SI-NEXT:    s_add_i32 s26, s26, 31711; SI-NEXT:    s_add_i32 s25, s25, 31712; SI-NEXT:    s_lshr_b32 s4, s26, 161713; SI-NEXT:    s_add_i32 s24, s24, 31714; SI-NEXT:    v_cvt_f32_f16_e32 v21, s41715; SI-NEXT:    s_lshr_b32 s4, s25, 161716; SI-NEXT:    s_add_i32 s23, s23, 31717; SI-NEXT:    v_cvt_f32_f16_e32 v19, s41718; SI-NEXT:    s_lshr_b32 s4, s24, 161719; SI-NEXT:    s_add_i32 s22, s22, 31720; SI-NEXT:    v_cvt_f32_f16_e32 v17, s41721; SI-NEXT:    s_lshr_b32 s4, s23, 161722; SI-NEXT:    s_add_i32 s21, s21, 31723; SI-NEXT:    v_cvt_f32_f16_e32 v15, s41724; SI-NEXT:    s_lshr_b32 s4, s22, 161725; SI-NEXT:    s_add_i32 s20, s20, 31726; SI-NEXT:    v_cvt_f32_f16_e32 v13, s41727; SI-NEXT:    s_lshr_b32 s4, s21, 161728; SI-NEXT:    s_add_i32 s19, s19, 31729; SI-NEXT:    v_cvt_f32_f16_e32 v11, s41730; SI-NEXT:    s_lshr_b32 s4, s20, 161731; SI-NEXT:    s_add_i32 s18, s18, 31732; SI-NEXT:    v_cvt_f32_f16_e32 v9, s41733; SI-NEXT:    s_lshr_b32 s4, s19, 161734; SI-NEXT:    s_add_i32 s16, s16, 31735; SI-NEXT:    s_add_i32 s17, s17, 31736; SI-NEXT:    v_cvt_f32_f16_e32 v7, s41737; SI-NEXT:    s_lshr_b32 s4, s18, 161738; SI-NEXT:    v_cvt_f32_f16_e32 v5, s41739; SI-NEXT:    s_lshr_b32 s4, s17, 161740; SI-NEXT:    s_lshr_b32 s5, s16, 161741; SI-NEXT:    v_cvt_f32_f16_e32 v20, s261742; SI-NEXT:    v_cvt_f32_f16_e32 v18, s251743; SI-NEXT:    v_cvt_f32_f16_e32 v16, s241744; SI-NEXT:    v_cvt_f32_f16_e32 v14, s231745; SI-NEXT:    v_cvt_f32_f16_e32 v12, s221746; SI-NEXT:    v_cvt_f32_f16_e32 v10, s211747; SI-NEXT:    v_cvt_f32_f16_e32 v8, s201748; SI-NEXT:    v_cvt_f32_f16_e32 v6, s191749; SI-NEXT:    v_cvt_f32_f16_e32 v4, s181750; SI-NEXT:    v_cvt_f32_f16_e32 v2, s171751; SI-NEXT:    v_cvt_f32_f16_e32 v0, s161752; SI-NEXT:    v_cvt_f32_f16_e32 v3, s41753; SI-NEXT:    v_cvt_f32_f16_e32 v1, s51754; SI-NEXT:  .LBB9_3: ; %end1755; SI-NEXT:    s_setpc_b64 s[30:31]1756; SI-NEXT:  .LBB9_4:1757; SI-NEXT:    ; implicit-def: $vgpr01758; SI-NEXT:    ; implicit-def: $vgpr11759; SI-NEXT:    ; implicit-def: $vgpr21760; SI-NEXT:    ; implicit-def: $vgpr31761; SI-NEXT:    ; implicit-def: $vgpr41762; SI-NEXT:    ; implicit-def: $vgpr51763; SI-NEXT:    ; implicit-def: $vgpr61764; SI-NEXT:    ; implicit-def: $vgpr71765; SI-NEXT:    ; implicit-def: $vgpr81766; SI-NEXT:    ; implicit-def: $vgpr91767; SI-NEXT:    ; implicit-def: $vgpr101768; SI-NEXT:    ; implicit-def: $vgpr111769; SI-NEXT:    ; implicit-def: $vgpr121770; SI-NEXT:    ; implicit-def: $vgpr131771; SI-NEXT:    ; implicit-def: $vgpr141772; SI-NEXT:    ; implicit-def: $vgpr151773; SI-NEXT:    ; implicit-def: $vgpr161774; SI-NEXT:    ; implicit-def: $vgpr171775; SI-NEXT:    ; implicit-def: $vgpr181776; SI-NEXT:    ; implicit-def: $vgpr191777; SI-NEXT:    ; implicit-def: $vgpr201778; SI-NEXT:    ; implicit-def: $vgpr211779; SI-NEXT:    s_branch .LBB9_21780;1781; VI-LABEL: bitcast_v11i32_to_v22f16_scalar:1782; VI:       ; %bb.0:1783; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1784; VI-NEXT:    s_cmp_lg_u32 s27, 01785; VI-NEXT:    s_cbranch_scc0 .LBB9_41786; VI-NEXT:  ; %bb.1: ; %cmp.false1787; VI-NEXT:    s_cbranch_execnz .LBB9_31788; VI-NEXT:  .LBB9_2: ; %cmp.true1789; VI-NEXT:    s_add_i32 s26, s26, 31790; VI-NEXT:    s_add_i32 s25, s25, 31791; VI-NEXT:    s_add_i32 s24, s24, 31792; VI-NEXT:    s_add_i32 s23, s23, 31793; VI-NEXT:    s_add_i32 s22, s22, 31794; VI-NEXT:    s_add_i32 s21, s21, 31795; VI-NEXT:    s_add_i32 s20, s20, 31796; VI-NEXT:    s_add_i32 s19, s19, 31797; VI-NEXT:    s_add_i32 s18, s18, 31798; VI-NEXT:    s_add_i32 s17, s17, 31799; VI-NEXT:    s_add_i32 s16, s16, 31800; VI-NEXT:  .LBB9_3: ; %end1801; VI-NEXT:    v_mov_b32_e32 v0, s161802; VI-NEXT:    v_mov_b32_e32 v1, s171803; VI-NEXT:    v_mov_b32_e32 v2, s181804; VI-NEXT:    v_mov_b32_e32 v3, s191805; VI-NEXT:    v_mov_b32_e32 v4, s201806; VI-NEXT:    v_mov_b32_e32 v5, s211807; VI-NEXT:    v_mov_b32_e32 v6, s221808; VI-NEXT:    v_mov_b32_e32 v7, s231809; VI-NEXT:    v_mov_b32_e32 v8, s241810; VI-NEXT:    v_mov_b32_e32 v9, s251811; VI-NEXT:    v_mov_b32_e32 v10, s261812; VI-NEXT:    s_setpc_b64 s[30:31]1813; VI-NEXT:  .LBB9_4:1814; VI-NEXT:    s_branch .LBB9_21815;1816; GFX9-LABEL: bitcast_v11i32_to_v22f16_scalar:1817; GFX9:       ; %bb.0:1818; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1819; GFX9-NEXT:    s_cmp_lg_u32 s27, 01820; GFX9-NEXT:    s_cbranch_scc0 .LBB9_41821; GFX9-NEXT:  ; %bb.1: ; %cmp.false1822; GFX9-NEXT:    s_cbranch_execnz .LBB9_31823; GFX9-NEXT:  .LBB9_2: ; %cmp.true1824; GFX9-NEXT:    s_add_i32 s26, s26, 31825; GFX9-NEXT:    s_add_i32 s25, s25, 31826; GFX9-NEXT:    s_add_i32 s24, s24, 31827; GFX9-NEXT:    s_add_i32 s23, s23, 31828; GFX9-NEXT:    s_add_i32 s22, s22, 31829; GFX9-NEXT:    s_add_i32 s21, s21, 31830; GFX9-NEXT:    s_add_i32 s20, s20, 31831; GFX9-NEXT:    s_add_i32 s19, s19, 31832; GFX9-NEXT:    s_add_i32 s18, s18, 31833; GFX9-NEXT:    s_add_i32 s17, s17, 31834; GFX9-NEXT:    s_add_i32 s16, s16, 31835; GFX9-NEXT:  .LBB9_3: ; %end1836; GFX9-NEXT:    v_mov_b32_e32 v0, s161837; GFX9-NEXT:    v_mov_b32_e32 v1, s171838; GFX9-NEXT:    v_mov_b32_e32 v2, s181839; GFX9-NEXT:    v_mov_b32_e32 v3, s191840; GFX9-NEXT:    v_mov_b32_e32 v4, s201841; GFX9-NEXT:    v_mov_b32_e32 v5, s211842; GFX9-NEXT:    v_mov_b32_e32 v6, s221843; GFX9-NEXT:    v_mov_b32_e32 v7, s231844; GFX9-NEXT:    v_mov_b32_e32 v8, s241845; GFX9-NEXT:    v_mov_b32_e32 v9, s251846; GFX9-NEXT:    v_mov_b32_e32 v10, s261847; GFX9-NEXT:    s_setpc_b64 s[30:31]1848; GFX9-NEXT:  .LBB9_4:1849; GFX9-NEXT:    s_branch .LBB9_21850;1851; GFX11-LABEL: bitcast_v11i32_to_v22f16_scalar:1852; GFX11:       ; %bb.0:1853; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1854; GFX11-NEXT:    s_cmp_lg_u32 s23, 01855; GFX11-NEXT:    s_mov_b32 s4, 01856; GFX11-NEXT:    s_cbranch_scc0 .LBB9_41857; GFX11-NEXT:  ; %bb.1: ; %Flow1858; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s41859; GFX11-NEXT:    s_cbranch_vccnz .LBB9_31860; GFX11-NEXT:  .LBB9_2: ; %cmp.true1861; GFX11-NEXT:    s_add_i32 s22, s22, 31862; GFX11-NEXT:    s_add_i32 s21, s21, 31863; GFX11-NEXT:    s_add_i32 s20, s20, 31864; GFX11-NEXT:    s_add_i32 s19, s19, 31865; GFX11-NEXT:    s_add_i32 s18, s18, 31866; GFX11-NEXT:    s_add_i32 s17, s17, 31867; GFX11-NEXT:    s_add_i32 s16, s16, 31868; GFX11-NEXT:    s_add_i32 s3, s3, 31869; GFX11-NEXT:    s_add_i32 s2, s2, 31870; GFX11-NEXT:    s_add_i32 s1, s1, 31871; GFX11-NEXT:    s_add_i32 s0, s0, 31872; GFX11-NEXT:  .LBB9_3: ; %end1873; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)1874; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s11875; GFX11-NEXT:    v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s31876; GFX11-NEXT:    v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s171877; GFX11-NEXT:    v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s191878; GFX11-NEXT:    v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s211879; GFX11-NEXT:    v_mov_b32_e32 v10, s221880; GFX11-NEXT:    s_setpc_b64 s[30:31]1881; GFX11-NEXT:  .LBB9_4:1882; GFX11-NEXT:    s_branch .LBB9_21883  %cmp = icmp eq i32 %b, 01884  br i1 %cmp, label %cmp.true, label %cmp.false1885 1886cmp.true:1887  %a1 = add <11 x i32> %a, splat (i32 3)1888  %a2 = bitcast <11 x i32> %a1 to <22 x half>1889  br label %end1890 1891cmp.false:1892  %a3 = bitcast <11 x i32> %a to <22 x half>1893  br label %end1894 1895end:1896  %phi = phi <22 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]1897  ret <22 x half> %phi1898}1899 1900define <11 x i32> @bitcast_v22f16_to_v11i32(<22 x half> %a, i32 %b) {1901; SI-LABEL: bitcast_v22f16_to_v11i32:1902; SI:       ; %bb.0:1903; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1904; SI-NEXT:    v_cvt_f16_f32_e32 v38, v11905; SI-NEXT:    v_cvt_f16_f32_e32 v37, v01906; SI-NEXT:    v_cvt_f16_f32_e32 v36, v31907; SI-NEXT:    v_cvt_f16_f32_e32 v35, v21908; SI-NEXT:    v_cvt_f16_f32_e32 v34, v51909; SI-NEXT:    v_cvt_f16_f32_e32 v33, v41910; SI-NEXT:    v_cvt_f16_f32_e32 v32, v71911; SI-NEXT:    v_cvt_f16_f32_e32 v31, v61912; SI-NEXT:    v_cvt_f16_f32_e32 v30, v91913; SI-NEXT:    v_cvt_f16_f32_e32 v29, v81914; SI-NEXT:    v_cvt_f16_f32_e32 v28, v111915; SI-NEXT:    v_cvt_f16_f32_e32 v27, v101916; SI-NEXT:    v_cvt_f16_f32_e32 v26, v131917; SI-NEXT:    v_cvt_f16_f32_e32 v25, v121918; SI-NEXT:    v_cvt_f16_f32_e32 v24, v151919; SI-NEXT:    v_cvt_f16_f32_e32 v23, v141920; SI-NEXT:    v_cvt_f16_f32_e32 v17, v171921; SI-NEXT:    v_cvt_f16_f32_e32 v15, v161922; SI-NEXT:    v_cvt_f16_f32_e32 v14, v191923; SI-NEXT:    v_cvt_f16_f32_e32 v13, v181924; SI-NEXT:    v_cvt_f16_f32_e32 v12, v211925; SI-NEXT:    v_cvt_f16_f32_e32 v11, v201926; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v221927; SI-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr101928; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc1929; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]1930; SI-NEXT:    s_cbranch_execnz .LBB10_31931; SI-NEXT:  ; %bb.1: ; %Flow1932; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1933; SI-NEXT:    s_cbranch_execnz .LBB10_41934; SI-NEXT:  .LBB10_2: ; %end1935; SI-NEXT:    s_or_b64 exec, exec, s[4:5]1936; SI-NEXT:    s_setpc_b64 s[30:31]1937; SI-NEXT:  .LBB10_3: ; %cmp.false1938; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v381939; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v361940; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v341941; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v321942; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v301943; SI-NEXT:    v_lshlrev_b32_e32 v5, 16, v281944; SI-NEXT:    v_lshlrev_b32_e32 v6, 16, v261945; SI-NEXT:    v_lshlrev_b32_e32 v7, 16, v241946; SI-NEXT:    v_lshlrev_b32_e32 v8, 16, v171947; SI-NEXT:    v_lshlrev_b32_e32 v9, 16, v141948; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v121949; SI-NEXT:    v_or_b32_e32 v0, v37, v01950; SI-NEXT:    v_or_b32_e32 v1, v35, v11951; SI-NEXT:    v_or_b32_e32 v2, v33, v21952; SI-NEXT:    v_or_b32_e32 v3, v31, v31953; SI-NEXT:    v_or_b32_e32 v4, v29, v41954; SI-NEXT:    v_or_b32_e32 v5, v27, v51955; SI-NEXT:    v_or_b32_e32 v6, v25, v61956; SI-NEXT:    v_or_b32_e32 v7, v23, v71957; SI-NEXT:    v_or_b32_e32 v8, v15, v81958; SI-NEXT:    v_or_b32_e32 v9, v13, v91959; SI-NEXT:    v_or_b32_e32 v10, v11, v101960; SI-NEXT:    ; implicit-def: $vgpr381961; SI-NEXT:    ; implicit-def: $vgpr371962; SI-NEXT:    ; implicit-def: $vgpr361963; SI-NEXT:    ; implicit-def: $vgpr351964; SI-NEXT:    ; implicit-def: $vgpr341965; SI-NEXT:    ; implicit-def: $vgpr331966; SI-NEXT:    ; implicit-def: $vgpr321967; SI-NEXT:    ; implicit-def: $vgpr311968; SI-NEXT:    ; implicit-def: $vgpr301969; SI-NEXT:    ; implicit-def: $vgpr291970; SI-NEXT:    ; implicit-def: $vgpr281971; SI-NEXT:    ; implicit-def: $vgpr271972; SI-NEXT:    ; implicit-def: $vgpr261973; SI-NEXT:    ; implicit-def: $vgpr251974; SI-NEXT:    ; implicit-def: $vgpr241975; SI-NEXT:    ; implicit-def: $vgpr231976; SI-NEXT:    ; implicit-def: $vgpr171977; SI-NEXT:    ; implicit-def: $vgpr151978; SI-NEXT:    ; implicit-def: $vgpr141979; SI-NEXT:    ; implicit-def: $vgpr131980; SI-NEXT:    ; implicit-def: $vgpr121981; SI-NEXT:    ; implicit-def: $vgpr111982; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1983; SI-NEXT:    s_cbranch_execz .LBB10_21984; SI-NEXT:  .LBB10_4: ; %cmp.true1985; SI-NEXT:    v_cvt_f32_f16_e32 v0, v381986; SI-NEXT:    v_cvt_f32_f16_e32 v1, v371987; SI-NEXT:    v_cvt_f32_f16_e32 v2, v361988; SI-NEXT:    v_cvt_f32_f16_e32 v3, v351989; SI-NEXT:    v_add_f32_e32 v0, 0x38000000, v01990; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v11991; SI-NEXT:    v_cvt_f16_f32_e32 v0, v01992; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v21993; SI-NEXT:    v_cvt_f16_f32_e32 v1, v11994; SI-NEXT:    v_cvt_f16_f32_e32 v2, v21995; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v01996; SI-NEXT:    v_cvt_f32_f16_e32 v4, v331997; SI-NEXT:    v_or_b32_e32 v0, v1, v01998; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v21999; SI-NEXT:    v_cvt_f32_f16_e32 v2, v342000; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v32001; SI-NEXT:    v_cvt_f16_f32_e32 v3, v32002; SI-NEXT:    v_add_f32_e32 v4, 0x38000000, v42003; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v22004; SI-NEXT:    v_cvt_f16_f32_e32 v2, v22005; SI-NEXT:    v_cvt_f16_f32_e32 v4, v42006; SI-NEXT:    v_or_b32_e32 v1, v3, v12007; SI-NEXT:    v_cvt_f32_f16_e32 v3, v322008; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v22009; SI-NEXT:    v_or_b32_e32 v2, v4, v22010; SI-NEXT:    v_cvt_f32_f16_e32 v4, v312011; SI-NEXT:    v_cvt_f32_f16_e32 v5, v302012; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v32013; SI-NEXT:    v_cvt_f16_f32_e32 v3, v32014; SI-NEXT:    v_add_f32_e32 v4, 0x38000000, v42015; SI-NEXT:    v_add_f32_e32 v5, 0x38000000, v52016; SI-NEXT:    v_cvt_f16_f32_e32 v4, v42017; SI-NEXT:    v_cvt_f16_f32_e32 v5, v52018; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v32019; SI-NEXT:    v_cvt_f32_f16_e32 v6, v292020; SI-NEXT:    v_or_b32_e32 v3, v4, v32021; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v52022; SI-NEXT:    v_cvt_f32_f16_e32 v5, v282023; SI-NEXT:    v_cvt_f32_f16_e32 v7, v272024; SI-NEXT:    v_add_f32_e32 v6, 0x38000000, v62025; SI-NEXT:    v_cvt_f16_f32_e32 v6, v62026; SI-NEXT:    v_add_f32_e32 v5, 0x38000000, v52027; SI-NEXT:    v_cvt_f16_f32_e32 v5, v52028; SI-NEXT:    v_add_f32_e32 v7, 0x38000000, v72029; SI-NEXT:    v_cvt_f16_f32_e32 v7, v72030; SI-NEXT:    v_or_b32_e32 v4, v6, v42031; SI-NEXT:    v_cvt_f32_f16_e32 v6, v262032; SI-NEXT:    v_lshlrev_b32_e32 v5, 16, v52033; SI-NEXT:    v_or_b32_e32 v5, v7, v52034; SI-NEXT:    v_cvt_f32_f16_e32 v7, v252035; SI-NEXT:    v_cvt_f32_f16_e32 v8, v242036; SI-NEXT:    v_add_f32_e32 v6, 0x38000000, v62037; SI-NEXT:    v_cvt_f16_f32_e32 v6, v62038; SI-NEXT:    v_add_f32_e32 v7, 0x38000000, v72039; SI-NEXT:    v_add_f32_e32 v8, 0x38000000, v82040; SI-NEXT:    v_cvt_f16_f32_e32 v7, v72041; SI-NEXT:    v_cvt_f16_f32_e32 v8, v82042; SI-NEXT:    v_lshlrev_b32_e32 v6, 16, v62043; SI-NEXT:    v_cvt_f32_f16_e32 v9, v232044; SI-NEXT:    v_or_b32_e32 v6, v7, v62045; SI-NEXT:    v_lshlrev_b32_e32 v7, 16, v82046; SI-NEXT:    v_cvt_f32_f16_e32 v8, v172047; SI-NEXT:    v_cvt_f32_f16_e32 v10, v152048; SI-NEXT:    v_add_f32_e32 v9, 0x38000000, v92049; SI-NEXT:    v_cvt_f16_f32_e32 v9, v92050; SI-NEXT:    v_add_f32_e32 v8, 0x38000000, v82051; SI-NEXT:    v_cvt_f16_f32_e32 v8, v82052; SI-NEXT:    v_add_f32_e32 v10, 0x38000000, v102053; SI-NEXT:    v_cvt_f16_f32_e32 v10, v102054; SI-NEXT:    v_or_b32_e32 v7, v9, v72055; SI-NEXT:    v_cvt_f32_f16_e32 v9, v142056; SI-NEXT:    v_lshlrev_b32_e32 v8, 16, v82057; SI-NEXT:    v_or_b32_e32 v8, v10, v82058; SI-NEXT:    v_cvt_f32_f16_e32 v10, v132059; SI-NEXT:    v_cvt_f32_f16_e32 v12, v122060; SI-NEXT:    v_cvt_f32_f16_e32 v11, v112061; SI-NEXT:    v_add_f32_e32 v9, 0x38000000, v92062; SI-NEXT:    v_cvt_f16_f32_e32 v9, v92063; SI-NEXT:    v_add_f32_e32 v10, 0x38000000, v102064; SI-NEXT:    v_add_f32_e32 v12, 0x38000000, v122065; SI-NEXT:    v_cvt_f16_f32_e32 v10, v102066; SI-NEXT:    v_cvt_f16_f32_e32 v12, v122067; SI-NEXT:    v_add_f32_e32 v11, 0x38000000, v112068; SI-NEXT:    v_cvt_f16_f32_e32 v11, v112069; SI-NEXT:    v_lshlrev_b32_e32 v9, 16, v92070; SI-NEXT:    v_or_b32_e32 v9, v10, v92071; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v122072; SI-NEXT:    v_or_b32_e32 v10, v11, v102073; SI-NEXT:    s_or_b64 exec, exec, s[4:5]2074; SI-NEXT:    s_setpc_b64 s[30:31]2075;2076; VI-LABEL: bitcast_v22f16_to_v11i32:2077; VI:       ; %bb.0:2078; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2079; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v112080; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc2081; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]2082; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]2083; VI-NEXT:    s_cbranch_execz .LBB10_22084; VI-NEXT:  ; %bb.1: ; %cmp.true2085; VI-NEXT:    v_mov_b32_e32 v11, 0x2002086; VI-NEXT:    v_add_f16_sdwa v12, v10, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2087; VI-NEXT:    v_add_f16_e32 v10, 0x200, v102088; VI-NEXT:    v_or_b32_e32 v10, v10, v122089; VI-NEXT:    v_add_f16_sdwa v12, v9, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2090; VI-NEXT:    v_add_f16_e32 v9, 0x200, v92091; VI-NEXT:    v_or_b32_e32 v9, v9, v122092; VI-NEXT:    v_add_f16_sdwa v12, v8, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2093; VI-NEXT:    v_add_f16_e32 v8, 0x200, v82094; VI-NEXT:    v_or_b32_e32 v8, v8, v122095; VI-NEXT:    v_add_f16_sdwa v12, v7, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2096; VI-NEXT:    v_add_f16_e32 v7, 0x200, v72097; VI-NEXT:    v_or_b32_e32 v7, v7, v122098; VI-NEXT:    v_add_f16_sdwa v12, v6, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2099; VI-NEXT:    v_add_f16_e32 v6, 0x200, v62100; VI-NEXT:    v_or_b32_e32 v6, v6, v122101; VI-NEXT:    v_add_f16_sdwa v12, v5, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2102; VI-NEXT:    v_add_f16_e32 v5, 0x200, v52103; VI-NEXT:    v_or_b32_e32 v5, v5, v122104; VI-NEXT:    v_add_f16_sdwa v12, v4, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2105; VI-NEXT:    v_add_f16_e32 v4, 0x200, v42106; VI-NEXT:    v_or_b32_e32 v4, v4, v122107; VI-NEXT:    v_add_f16_sdwa v12, v3, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2108; VI-NEXT:    v_add_f16_e32 v3, 0x200, v32109; VI-NEXT:    v_or_b32_e32 v3, v3, v122110; VI-NEXT:    v_add_f16_sdwa v12, v2, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2111; VI-NEXT:    v_add_f16_e32 v2, 0x200, v22112; VI-NEXT:    v_or_b32_e32 v2, v2, v122113; VI-NEXT:    v_add_f16_sdwa v12, v1, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2114; VI-NEXT:    v_add_f16_e32 v1, 0x200, v12115; VI-NEXT:    v_add_f16_sdwa v11, v0, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2116; VI-NEXT:    v_add_f16_e32 v0, 0x200, v02117; VI-NEXT:    v_or_b32_e32 v1, v1, v122118; VI-NEXT:    v_or_b32_e32 v0, v0, v112119; VI-NEXT:  .LBB10_2: ; %end2120; VI-NEXT:    s_or_b64 exec, exec, s[4:5]2121; VI-NEXT:    s_setpc_b64 s[30:31]2122;2123; GFX9-LABEL: bitcast_v22f16_to_v11i32:2124; GFX9:       ; %bb.0:2125; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2126; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v112127; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc2128; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]2129; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]2130; GFX9-NEXT:    s_cbranch_execz .LBB10_22131; GFX9-NEXT:  ; %bb.1: ; %cmp.true2132; GFX9-NEXT:    s_movk_i32 s6, 0x2002133; GFX9-NEXT:    v_pk_add_f16 v10, v10, s6 op_sel_hi:[1,0]2134; GFX9-NEXT:    v_pk_add_f16 v9, v9, s6 op_sel_hi:[1,0]2135; GFX9-NEXT:    v_pk_add_f16 v8, v8, s6 op_sel_hi:[1,0]2136; GFX9-NEXT:    v_pk_add_f16 v7, v7, s6 op_sel_hi:[1,0]2137; GFX9-NEXT:    v_pk_add_f16 v6, v6, s6 op_sel_hi:[1,0]2138; GFX9-NEXT:    v_pk_add_f16 v5, v5, s6 op_sel_hi:[1,0]2139; GFX9-NEXT:    v_pk_add_f16 v4, v4, s6 op_sel_hi:[1,0]2140; GFX9-NEXT:    v_pk_add_f16 v3, v3, s6 op_sel_hi:[1,0]2141; GFX9-NEXT:    v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]2142; GFX9-NEXT:    v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]2143; GFX9-NEXT:    v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]2144; GFX9-NEXT:  .LBB10_2: ; %end2145; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]2146; GFX9-NEXT:    s_setpc_b64 s[30:31]2147;2148; GFX11-LABEL: bitcast_v22f16_to_v11i32:2149; GFX11:       ; %bb.0:2150; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2151; GFX11-NEXT:    s_mov_b32 s0, exec_lo2152; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v112153; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s02154; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)2155; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s02156; GFX11-NEXT:    s_cbranch_execz .LBB10_22157; GFX11-NEXT:  ; %bb.1: ; %cmp.true2158; GFX11-NEXT:    v_pk_add_f16 v10, 0x200, v10 op_sel_hi:[0,1]2159; GFX11-NEXT:    v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1]2160; GFX11-NEXT:    v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1]2161; GFX11-NEXT:    v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]2162; GFX11-NEXT:    v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]2163; GFX11-NEXT:    v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]2164; GFX11-NEXT:    v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]2165; GFX11-NEXT:    v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]2166; GFX11-NEXT:    v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]2167; GFX11-NEXT:    v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]2168; GFX11-NEXT:    v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]2169; GFX11-NEXT:  .LBB10_2: ; %end2170; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s02171; GFX11-NEXT:    s_setpc_b64 s[30:31]2172  %cmp = icmp eq i32 %b, 02173  br i1 %cmp, label %cmp.true, label %cmp.false2174 2175cmp.true:2176  %a1 = fadd <22 x half> %a, splat (half 0xH0200)2177  %a2 = bitcast <22 x half> %a1 to <11 x i32>2178  br label %end2179 2180cmp.false:2181  %a3 = bitcast <22 x half> %a to <11 x i32>2182  br label %end2183 2184end:2185  %phi = phi <11 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]2186  ret <11 x i32> %phi2187}2188 2189define inreg <11 x i32> @bitcast_v22f16_to_v11i32_scalar(<22 x half> inreg %a, i32 inreg %b) {2190; SI-LABEL: bitcast_v22f16_to_v11i32_scalar:2191; SI:       ; %bb.0:2192; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2193; SI-NEXT:    v_cvt_f16_f32_e32 v32, s172194; SI-NEXT:    v_cvt_f16_f32_e32 v31, s162195; SI-NEXT:    v_cvt_f16_f32_e32 v30, s192196; SI-NEXT:    v_cvt_f16_f32_e32 v29, s182197; SI-NEXT:    v_cvt_f16_f32_e32 v28, s212198; SI-NEXT:    v_cvt_f16_f32_e32 v27, s202199; SI-NEXT:    v_cvt_f16_f32_e32 v26, s232200; SI-NEXT:    v_cvt_f16_f32_e32 v25, s222201; SI-NEXT:    v_cvt_f16_f32_e32 v24, s252202; SI-NEXT:    v_cvt_f16_f32_e32 v23, s242203; SI-NEXT:    v_cvt_f16_f32_e32 v22, s272204; SI-NEXT:    v_cvt_f16_f32_e32 v20, s262205; SI-NEXT:    v_cvt_f16_f32_e32 v18, v12206; SI-NEXT:    v_cvt_f16_f32_e32 v17, v02207; SI-NEXT:    v_cvt_f16_f32_e32 v16, v32208; SI-NEXT:    v_cvt_f16_f32_e32 v15, v22209; SI-NEXT:    v_cvt_f16_f32_e32 v14, v52210; SI-NEXT:    v_cvt_f16_f32_e32 v13, v42211; SI-NEXT:    v_cvt_f16_f32_e32 v12, v72212; SI-NEXT:    v_cvt_f16_f32_e32 v11, v62213; SI-NEXT:    v_cvt_f16_f32_e32 v21, s292214; SI-NEXT:    v_cvt_f16_f32_e32 v19, s282215; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v82216; SI-NEXT:    s_and_b64 s[4:5], vcc, exec2217; SI-NEXT:    s_cbranch_scc0 .LBB11_42218; SI-NEXT:  ; %bb.1: ; %cmp.false2219; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v322220; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v302221; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v282222; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v262223; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v242224; SI-NEXT:    v_lshlrev_b32_e32 v5, 16, v222225; SI-NEXT:    v_lshlrev_b32_e32 v6, 16, v212226; SI-NEXT:    v_lshlrev_b32_e32 v7, 16, v182227; SI-NEXT:    v_lshlrev_b32_e32 v8, 16, v162228; SI-NEXT:    v_lshlrev_b32_e32 v9, 16, v142229; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v122230; SI-NEXT:    v_or_b32_e32 v0, v31, v02231; SI-NEXT:    v_or_b32_e32 v1, v29, v12232; SI-NEXT:    v_or_b32_e32 v2, v27, v22233; SI-NEXT:    v_or_b32_e32 v3, v25, v32234; SI-NEXT:    v_or_b32_e32 v4, v23, v42235; SI-NEXT:    v_or_b32_e32 v5, v20, v52236; SI-NEXT:    v_or_b32_e32 v6, v19, v62237; SI-NEXT:    v_or_b32_e32 v7, v17, v72238; SI-NEXT:    v_or_b32_e32 v8, v15, v82239; SI-NEXT:    v_or_b32_e32 v9, v13, v92240; SI-NEXT:    v_or_b32_e32 v10, v11, v102241; SI-NEXT:    s_cbranch_execnz .LBB11_32242; SI-NEXT:  .LBB11_2: ; %cmp.true2243; SI-NEXT:    v_cvt_f32_f16_e32 v0, v322244; SI-NEXT:    v_cvt_f32_f16_e32 v1, v312245; SI-NEXT:    v_cvt_f32_f16_e32 v2, v302246; SI-NEXT:    v_cvt_f32_f16_e32 v3, v292247; SI-NEXT:    v_add_f32_e32 v0, 0x38000000, v02248; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v12249; SI-NEXT:    v_cvt_f16_f32_e32 v0, v02250; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v22251; SI-NEXT:    v_cvt_f16_f32_e32 v1, v12252; SI-NEXT:    v_cvt_f16_f32_e32 v2, v22253; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v02254; SI-NEXT:    v_cvt_f32_f16_e32 v4, v272255; SI-NEXT:    v_or_b32_e32 v0, v1, v02256; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v22257; SI-NEXT:    v_cvt_f32_f16_e32 v2, v282258; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v32259; SI-NEXT:    v_cvt_f16_f32_e32 v3, v32260; SI-NEXT:    v_add_f32_e32 v4, 0x38000000, v42261; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v22262; SI-NEXT:    v_cvt_f16_f32_e32 v2, v22263; SI-NEXT:    v_cvt_f16_f32_e32 v4, v42264; SI-NEXT:    v_or_b32_e32 v1, v3, v12265; SI-NEXT:    v_cvt_f32_f16_e32 v3, v262266; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v22267; SI-NEXT:    v_or_b32_e32 v2, v4, v22268; SI-NEXT:    v_cvt_f32_f16_e32 v4, v252269; SI-NEXT:    v_cvt_f32_f16_e32 v5, v242270; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v32271; SI-NEXT:    v_cvt_f16_f32_e32 v3, v32272; SI-NEXT:    v_add_f32_e32 v4, 0x38000000, v42273; SI-NEXT:    v_add_f32_e32 v5, 0x38000000, v52274; SI-NEXT:    v_cvt_f16_f32_e32 v4, v42275; SI-NEXT:    v_cvt_f16_f32_e32 v5, v52276; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v32277; SI-NEXT:    v_cvt_f32_f16_e32 v6, v232278; SI-NEXT:    v_or_b32_e32 v3, v4, v32279; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v52280; SI-NEXT:    v_cvt_f32_f16_e32 v5, v222281; SI-NEXT:    v_cvt_f32_f16_e32 v7, v202282; SI-NEXT:    v_add_f32_e32 v6, 0x38000000, v62283; SI-NEXT:    v_cvt_f16_f32_e32 v6, v62284; SI-NEXT:    v_add_f32_e32 v5, 0x38000000, v52285; SI-NEXT:    v_cvt_f16_f32_e32 v5, v52286; SI-NEXT:    v_add_f32_e32 v7, 0x38000000, v72287; SI-NEXT:    v_cvt_f16_f32_e32 v7, v72288; SI-NEXT:    v_or_b32_e32 v4, v6, v42289; SI-NEXT:    v_cvt_f32_f16_e32 v6, v212290; SI-NEXT:    v_lshlrev_b32_e32 v5, 16, v52291; SI-NEXT:    v_or_b32_e32 v5, v7, v52292; SI-NEXT:    v_cvt_f32_f16_e32 v7, v192293; SI-NEXT:    v_cvt_f32_f16_e32 v8, v182294; SI-NEXT:    v_add_f32_e32 v6, 0x38000000, v62295; SI-NEXT:    v_cvt_f16_f32_e32 v6, v62296; SI-NEXT:    v_add_f32_e32 v7, 0x38000000, v72297; SI-NEXT:    v_add_f32_e32 v8, 0x38000000, v82298; SI-NEXT:    v_cvt_f16_f32_e32 v7, v72299; SI-NEXT:    v_cvt_f16_f32_e32 v8, v82300; SI-NEXT:    v_lshlrev_b32_e32 v6, 16, v62301; SI-NEXT:    v_cvt_f32_f16_e32 v9, v172302; SI-NEXT:    v_or_b32_e32 v6, v7, v62303; SI-NEXT:    v_lshlrev_b32_e32 v7, 16, v82304; SI-NEXT:    v_cvt_f32_f16_e32 v8, v162305; SI-NEXT:    v_cvt_f32_f16_e32 v10, v152306; SI-NEXT:    v_add_f32_e32 v9, 0x38000000, v92307; SI-NEXT:    v_cvt_f16_f32_e32 v9, v92308; SI-NEXT:    v_add_f32_e32 v8, 0x38000000, v82309; SI-NEXT:    v_cvt_f16_f32_e32 v8, v82310; SI-NEXT:    v_add_f32_e32 v10, 0x38000000, v102311; SI-NEXT:    v_cvt_f16_f32_e32 v10, v102312; SI-NEXT:    v_or_b32_e32 v7, v9, v72313; SI-NEXT:    v_cvt_f32_f16_e32 v9, v142314; SI-NEXT:    v_lshlrev_b32_e32 v8, 16, v82315; SI-NEXT:    v_or_b32_e32 v8, v10, v82316; SI-NEXT:    v_cvt_f32_f16_e32 v10, v132317; SI-NEXT:    v_cvt_f32_f16_e32 v12, v122318; SI-NEXT:    v_cvt_f32_f16_e32 v11, v112319; SI-NEXT:    v_add_f32_e32 v9, 0x38000000, v92320; SI-NEXT:    v_cvt_f16_f32_e32 v9, v92321; SI-NEXT:    v_add_f32_e32 v10, 0x38000000, v102322; SI-NEXT:    v_add_f32_e32 v12, 0x38000000, v122323; SI-NEXT:    v_cvt_f16_f32_e32 v10, v102324; SI-NEXT:    v_cvt_f16_f32_e32 v12, v122325; SI-NEXT:    v_add_f32_e32 v11, 0x38000000, v112326; SI-NEXT:    v_cvt_f16_f32_e32 v11, v112327; SI-NEXT:    v_lshlrev_b32_e32 v9, 16, v92328; SI-NEXT:    v_or_b32_e32 v9, v10, v92329; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v122330; SI-NEXT:    v_or_b32_e32 v10, v11, v102331; SI-NEXT:  .LBB11_3: ; %end2332; SI-NEXT:    s_setpc_b64 s[30:31]2333; SI-NEXT:  .LBB11_4:2334; SI-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr102335; SI-NEXT:    s_branch .LBB11_22336;2337; VI-LABEL: bitcast_v22f16_to_v11i32_scalar:2338; VI:       ; %bb.0:2339; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2340; VI-NEXT:    s_cmp_lg_u32 s27, 02341; VI-NEXT:    s_cbranch_scc0 .LBB11_32342; VI-NEXT:  ; %bb.1: ; %cmp.false2343; VI-NEXT:    s_cbranch_execnz .LBB11_42344; VI-NEXT:  .LBB11_2: ; %cmp.true2345; VI-NEXT:    s_lshr_b32 s4, s26, 162346; VI-NEXT:    v_mov_b32_e32 v0, 0x2002347; VI-NEXT:    v_mov_b32_e32 v1, s42348; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2349; VI-NEXT:    v_add_f16_e32 v2, s26, v02350; VI-NEXT:    s_lshr_b32 s4, s25, 162351; VI-NEXT:    v_or_b32_e32 v10, v2, v12352; VI-NEXT:    v_mov_b32_e32 v1, s42353; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2354; VI-NEXT:    v_add_f16_e32 v2, s25, v02355; VI-NEXT:    s_lshr_b32 s4, s24, 162356; VI-NEXT:    v_or_b32_e32 v9, v2, v12357; VI-NEXT:    v_mov_b32_e32 v1, s42358; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2359; VI-NEXT:    v_add_f16_e32 v2, s24, v02360; VI-NEXT:    s_lshr_b32 s4, s23, 162361; VI-NEXT:    v_or_b32_e32 v8, v2, v12362; VI-NEXT:    v_mov_b32_e32 v1, s42363; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2364; VI-NEXT:    v_add_f16_e32 v2, s23, v02365; VI-NEXT:    s_lshr_b32 s4, s22, 162366; VI-NEXT:    v_or_b32_e32 v7, v2, v12367; VI-NEXT:    v_mov_b32_e32 v1, s42368; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2369; VI-NEXT:    v_add_f16_e32 v2, s22, v02370; VI-NEXT:    s_lshr_b32 s4, s21, 162371; VI-NEXT:    v_or_b32_e32 v6, v2, v12372; VI-NEXT:    v_mov_b32_e32 v1, s42373; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2374; VI-NEXT:    v_add_f16_e32 v2, s21, v02375; VI-NEXT:    s_lshr_b32 s4, s20, 162376; VI-NEXT:    v_or_b32_e32 v5, v2, v12377; VI-NEXT:    v_mov_b32_e32 v1, s42378; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2379; VI-NEXT:    v_add_f16_e32 v2, s20, v02380; VI-NEXT:    s_lshr_b32 s4, s19, 162381; VI-NEXT:    v_or_b32_e32 v4, v2, v12382; VI-NEXT:    v_mov_b32_e32 v1, s42383; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2384; VI-NEXT:    v_add_f16_e32 v2, s19, v02385; VI-NEXT:    s_lshr_b32 s4, s18, 162386; VI-NEXT:    v_or_b32_e32 v3, v2, v12387; VI-NEXT:    v_mov_b32_e32 v1, s42388; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2389; VI-NEXT:    v_add_f16_e32 v2, s18, v02390; VI-NEXT:    s_lshr_b32 s4, s17, 162391; VI-NEXT:    v_or_b32_e32 v2, v2, v12392; VI-NEXT:    v_mov_b32_e32 v1, s42393; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2394; VI-NEXT:    v_add_f16_e32 v11, s17, v02395; VI-NEXT:    s_lshr_b32 s4, s16, 162396; VI-NEXT:    v_or_b32_e32 v1, v11, v12397; VI-NEXT:    v_mov_b32_e32 v11, s42398; VI-NEXT:    v_add_f16_sdwa v11, v11, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2399; VI-NEXT:    v_add_f16_e32 v0, s16, v02400; VI-NEXT:    v_or_b32_e32 v0, v0, v112401; VI-NEXT:    s_setpc_b64 s[30:31]2402; VI-NEXT:  .LBB11_3:2403; VI-NEXT:    s_branch .LBB11_22404; VI-NEXT:  .LBB11_4:2405; VI-NEXT:    v_mov_b32_e32 v0, s162406; VI-NEXT:    v_mov_b32_e32 v1, s172407; VI-NEXT:    v_mov_b32_e32 v2, s182408; VI-NEXT:    v_mov_b32_e32 v3, s192409; VI-NEXT:    v_mov_b32_e32 v4, s202410; VI-NEXT:    v_mov_b32_e32 v5, s212411; VI-NEXT:    v_mov_b32_e32 v6, s222412; VI-NEXT:    v_mov_b32_e32 v7, s232413; VI-NEXT:    v_mov_b32_e32 v8, s242414; VI-NEXT:    v_mov_b32_e32 v9, s252415; VI-NEXT:    v_mov_b32_e32 v10, s262416; VI-NEXT:    s_setpc_b64 s[30:31]2417;2418; GFX9-LABEL: bitcast_v22f16_to_v11i32_scalar:2419; GFX9:       ; %bb.0:2420; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2421; GFX9-NEXT:    s_cmp_lg_u32 s27, 02422; GFX9-NEXT:    s_cbranch_scc0 .LBB11_32423; GFX9-NEXT:  ; %bb.1: ; %cmp.false2424; GFX9-NEXT:    s_cbranch_execnz .LBB11_42425; GFX9-NEXT:  .LBB11_2: ; %cmp.true2426; GFX9-NEXT:    v_mov_b32_e32 v0, 0x2002427; GFX9-NEXT:    v_pk_add_f16 v10, s26, v0 op_sel_hi:[1,0]2428; GFX9-NEXT:    v_pk_add_f16 v9, s25, v0 op_sel_hi:[1,0]2429; GFX9-NEXT:    v_pk_add_f16 v8, s24, v0 op_sel_hi:[1,0]2430; GFX9-NEXT:    v_pk_add_f16 v7, s23, v0 op_sel_hi:[1,0]2431; GFX9-NEXT:    v_pk_add_f16 v6, s22, v0 op_sel_hi:[1,0]2432; GFX9-NEXT:    v_pk_add_f16 v5, s21, v0 op_sel_hi:[1,0]2433; GFX9-NEXT:    v_pk_add_f16 v4, s20, v0 op_sel_hi:[1,0]2434; GFX9-NEXT:    v_pk_add_f16 v3, s19, v0 op_sel_hi:[1,0]2435; GFX9-NEXT:    v_pk_add_f16 v2, s18, v0 op_sel_hi:[1,0]2436; GFX9-NEXT:    v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]2437; GFX9-NEXT:    v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]2438; GFX9-NEXT:    s_setpc_b64 s[30:31]2439; GFX9-NEXT:  .LBB11_3:2440; GFX9-NEXT:    s_branch .LBB11_22441; GFX9-NEXT:  .LBB11_4:2442; GFX9-NEXT:    v_mov_b32_e32 v0, s162443; GFX9-NEXT:    v_mov_b32_e32 v1, s172444; GFX9-NEXT:    v_mov_b32_e32 v2, s182445; GFX9-NEXT:    v_mov_b32_e32 v3, s192446; GFX9-NEXT:    v_mov_b32_e32 v4, s202447; GFX9-NEXT:    v_mov_b32_e32 v5, s212448; GFX9-NEXT:    v_mov_b32_e32 v6, s222449; GFX9-NEXT:    v_mov_b32_e32 v7, s232450; GFX9-NEXT:    v_mov_b32_e32 v8, s242451; GFX9-NEXT:    v_mov_b32_e32 v9, s252452; GFX9-NEXT:    v_mov_b32_e32 v10, s262453; GFX9-NEXT:    s_setpc_b64 s[30:31]2454;2455; GFX11-LABEL: bitcast_v22f16_to_v11i32_scalar:2456; GFX11:       ; %bb.0:2457; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2458; GFX11-NEXT:    s_mov_b32 s15, s32459; GFX11-NEXT:    s_mov_b32 s14, s22460; GFX11-NEXT:    s_mov_b32 s13, s12461; GFX11-NEXT:    s_mov_b32 s12, s02462; GFX11-NEXT:    s_cmp_lg_u32 s23, 02463; GFX11-NEXT:    s_mov_b32 s0, 02464; GFX11-NEXT:    s_cbranch_scc0 .LBB11_32465; GFX11-NEXT:  ; %bb.1: ; %Flow2466; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s02467; GFX11-NEXT:    s_cbranch_vccnz .LBB11_42468; GFX11-NEXT:  .LBB11_2: ; %cmp.true2469; GFX11-NEXT:    v_pk_add_f16 v10, 0x200, s22 op_sel_hi:[0,1]2470; GFX11-NEXT:    v_pk_add_f16 v9, 0x200, s21 op_sel_hi:[0,1]2471; GFX11-NEXT:    v_pk_add_f16 v8, 0x200, s20 op_sel_hi:[0,1]2472; GFX11-NEXT:    v_pk_add_f16 v7, 0x200, s19 op_sel_hi:[0,1]2473; GFX11-NEXT:    v_pk_add_f16 v6, 0x200, s18 op_sel_hi:[0,1]2474; GFX11-NEXT:    v_pk_add_f16 v5, 0x200, s17 op_sel_hi:[0,1]2475; GFX11-NEXT:    v_pk_add_f16 v4, 0x200, s16 op_sel_hi:[0,1]2476; GFX11-NEXT:    v_pk_add_f16 v3, 0x200, s15 op_sel_hi:[0,1]2477; GFX11-NEXT:    v_pk_add_f16 v2, 0x200, s14 op_sel_hi:[0,1]2478; GFX11-NEXT:    v_pk_add_f16 v1, 0x200, s13 op_sel_hi:[0,1]2479; GFX11-NEXT:    v_pk_add_f16 v0, 0x200, s12 op_sel_hi:[0,1]2480; GFX11-NEXT:    s_setpc_b64 s[30:31]2481; GFX11-NEXT:  .LBB11_3:2482; GFX11-NEXT:    s_branch .LBB11_22483; GFX11-NEXT:  .LBB11_4:2484; GFX11-NEXT:    v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s132485; GFX11-NEXT:    v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s152486; GFX11-NEXT:    v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s172487; GFX11-NEXT:    v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s192488; GFX11-NEXT:    v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s212489; GFX11-NEXT:    v_mov_b32_e32 v10, s222490; GFX11-NEXT:    s_setpc_b64 s[30:31]2491  %cmp = icmp eq i32 %b, 02492  br i1 %cmp, label %cmp.true, label %cmp.false2493 2494cmp.true:2495  %a1 = fadd <22 x half> %a, splat (half 0xH0200)2496  %a2 = bitcast <22 x half> %a1 to <11 x i32>2497  br label %end2498 2499cmp.false:2500  %a3 = bitcast <22 x half> %a to <11 x i32>2501  br label %end2502 2503end:2504  %phi = phi <11 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]2505  ret <11 x i32> %phi2506}2507 2508define <22 x i16> @bitcast_v11f32_to_v22i16(<11 x float> %a, i32 %b) {2509; SI-LABEL: bitcast_v11f32_to_v22i16:2510; SI:       ; %bb.0:2511; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2512; SI-NEXT:    v_mov_b32_e32 v20, v102513; SI-NEXT:    v_mov_b32_e32 v18, v92514; SI-NEXT:    v_mov_b32_e32 v16, v82515; SI-NEXT:    v_mov_b32_e32 v14, v72516; SI-NEXT:    v_mov_b32_e32 v12, v62517; SI-NEXT:    v_mov_b32_e32 v10, v52518; SI-NEXT:    v_mov_b32_e32 v8, v42519; SI-NEXT:    v_mov_b32_e32 v6, v32520; SI-NEXT:    v_mov_b32_e32 v4, v22521; SI-NEXT:    v_mov_b32_e32 v2, v12522; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v112523; SI-NEXT:    ; implicit-def: $vgpr12524; SI-NEXT:    ; implicit-def: $vgpr32525; SI-NEXT:    ; implicit-def: $vgpr52526; SI-NEXT:    ; implicit-def: $vgpr72527; SI-NEXT:    ; implicit-def: $vgpr92528; SI-NEXT:    ; implicit-def: $vgpr112529; SI-NEXT:    ; implicit-def: $vgpr132530; SI-NEXT:    ; implicit-def: $vgpr152531; SI-NEXT:    ; implicit-def: $vgpr172532; SI-NEXT:    ; implicit-def: $vgpr192533; SI-NEXT:    ; implicit-def: $vgpr212534; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc2535; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]2536; SI-NEXT:    s_cbranch_execnz .LBB12_32537; SI-NEXT:  ; %bb.1: ; %Flow2538; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]2539; SI-NEXT:    s_cbranch_execnz .LBB12_42540; SI-NEXT:  .LBB12_2: ; %end2541; SI-NEXT:    s_or_b64 exec, exec, s[4:5]2542; SI-NEXT:    s_setpc_b64 s[30:31]2543; SI-NEXT:  .LBB12_3: ; %cmp.false2544; SI-NEXT:    v_alignbit_b32 v21, v0, v20, 162545; SI-NEXT:    v_alignbit_b32 v17, v18, v16, 162546; SI-NEXT:    v_alignbit_b32 v13, v14, v12, 162547; SI-NEXT:    v_alignbit_b32 v9, v10, v8, 162548; SI-NEXT:    v_alignbit_b32 v5, v6, v4, 162549; SI-NEXT:    v_alignbit_b32 v1, v2, v0, 162550; SI-NEXT:    v_lshrrev_b32_e32 v19, 16, v182551; SI-NEXT:    v_lshrrev_b32_e32 v15, 16, v142552; SI-NEXT:    v_lshrrev_b32_e32 v11, 16, v102553; SI-NEXT:    v_lshrrev_b32_e32 v7, 16, v62554; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v22555; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]2556; SI-NEXT:    s_cbranch_execz .LBB12_22557; SI-NEXT:  .LBB12_4: ; %cmp.true2558; SI-NEXT:    v_add_f32_e32 v20, 1.0, v202559; SI-NEXT:    v_add_f32_e32 v2, 1.0, v22560; SI-NEXT:    v_add_f32_e32 v0, 1.0, v02561; SI-NEXT:    v_add_f32_e32 v6, 1.0, v62562; SI-NEXT:    v_add_f32_e32 v4, 1.0, v42563; SI-NEXT:    v_add_f32_e32 v10, 1.0, v102564; SI-NEXT:    v_add_f32_e32 v8, 1.0, v82565; SI-NEXT:    v_add_f32_e32 v14, 1.0, v142566; SI-NEXT:    v_add_f32_e32 v12, 1.0, v122567; SI-NEXT:    v_add_f32_e32 v18, 1.0, v182568; SI-NEXT:    v_add_f32_e32 v16, 1.0, v162569; SI-NEXT:    v_alignbit_b32 v17, v18, v16, 162570; SI-NEXT:    v_alignbit_b32 v13, v14, v12, 162571; SI-NEXT:    v_alignbit_b32 v9, v10, v8, 162572; SI-NEXT:    v_alignbit_b32 v5, v6, v4, 162573; SI-NEXT:    v_alignbit_b32 v1, v2, v0, 162574; SI-NEXT:    v_alignbit_b32 v21, v0, v20, 162575; SI-NEXT:    v_lshrrev_b32_e32 v19, 16, v182576; SI-NEXT:    v_lshrrev_b32_e32 v15, 16, v142577; SI-NEXT:    v_lshrrev_b32_e32 v11, 16, v102578; SI-NEXT:    v_lshrrev_b32_e32 v7, 16, v62579; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v22580; SI-NEXT:    s_or_b64 exec, exec, s[4:5]2581; SI-NEXT:    s_setpc_b64 s[30:31]2582;2583; VI-LABEL: bitcast_v11f32_to_v22i16:2584; VI:       ; %bb.0:2585; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2586; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v112587; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc2588; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]2589; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]2590; VI-NEXT:    s_cbranch_execz .LBB12_22591; VI-NEXT:  ; %bb.1: ; %cmp.true2592; VI-NEXT:    v_add_f32_e32 v10, 1.0, v102593; VI-NEXT:    v_add_f32_e32 v9, 1.0, v92594; VI-NEXT:    v_add_f32_e32 v8, 1.0, v82595; VI-NEXT:    v_add_f32_e32 v7, 1.0, v72596; VI-NEXT:    v_add_f32_e32 v6, 1.0, v62597; VI-NEXT:    v_add_f32_e32 v5, 1.0, v52598; VI-NEXT:    v_add_f32_e32 v4, 1.0, v42599; VI-NEXT:    v_add_f32_e32 v3, 1.0, v32600; VI-NEXT:    v_add_f32_e32 v2, 1.0, v22601; VI-NEXT:    v_add_f32_e32 v1, 1.0, v12602; VI-NEXT:    v_add_f32_e32 v0, 1.0, v02603; VI-NEXT:  .LBB12_2: ; %end2604; VI-NEXT:    s_or_b64 exec, exec, s[4:5]2605; VI-NEXT:    s_setpc_b64 s[30:31]2606;2607; GFX9-LABEL: bitcast_v11f32_to_v22i16:2608; GFX9:       ; %bb.0:2609; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2610; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v112611; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc2612; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]2613; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]2614; GFX9-NEXT:    s_cbranch_execz .LBB12_22615; GFX9-NEXT:  ; %bb.1: ; %cmp.true2616; GFX9-NEXT:    v_add_f32_e32 v10, 1.0, v102617; GFX9-NEXT:    v_add_f32_e32 v9, 1.0, v92618; GFX9-NEXT:    v_add_f32_e32 v8, 1.0, v82619; GFX9-NEXT:    v_add_f32_e32 v7, 1.0, v72620; GFX9-NEXT:    v_add_f32_e32 v6, 1.0, v62621; GFX9-NEXT:    v_add_f32_e32 v5, 1.0, v52622; GFX9-NEXT:    v_add_f32_e32 v4, 1.0, v42623; GFX9-NEXT:    v_add_f32_e32 v3, 1.0, v32624; GFX9-NEXT:    v_add_f32_e32 v2, 1.0, v22625; GFX9-NEXT:    v_add_f32_e32 v1, 1.0, v12626; GFX9-NEXT:    v_add_f32_e32 v0, 1.0, v02627; GFX9-NEXT:  .LBB12_2: ; %end2628; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]2629; GFX9-NEXT:    s_setpc_b64 s[30:31]2630;2631; GFX11-LABEL: bitcast_v11f32_to_v22i16:2632; GFX11:       ; %bb.0:2633; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2634; GFX11-NEXT:    s_mov_b32 s0, exec_lo2635; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v112636; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s02637; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)2638; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s02639; GFX11-NEXT:  ; %bb.1: ; %cmp.true2640; GFX11-NEXT:    v_dual_add_f32 v10, 1.0, v10 :: v_dual_add_f32 v9, 1.0, v92641; GFX11-NEXT:    v_dual_add_f32 v8, 1.0, v8 :: v_dual_add_f32 v7, 1.0, v72642; GFX11-NEXT:    v_dual_add_f32 v6, 1.0, v6 :: v_dual_add_f32 v5, 1.0, v52643; GFX11-NEXT:    v_dual_add_f32 v4, 1.0, v4 :: v_dual_add_f32 v3, 1.0, v32644; GFX11-NEXT:    v_dual_add_f32 v2, 1.0, v2 :: v_dual_add_f32 v1, 1.0, v12645; GFX11-NEXT:    v_add_f32_e32 v0, 1.0, v02646; GFX11-NEXT:  ; %bb.2: ; %end2647; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s02648; GFX11-NEXT:    s_setpc_b64 s[30:31]2649  %cmp = icmp eq i32 %b, 02650  br i1 %cmp, label %cmp.true, label %cmp.false2651 2652cmp.true:2653  %a1 = fadd <11 x float> %a, splat (float 1.000000e+00)2654  %a2 = bitcast <11 x float> %a1 to <22 x i16>2655  br label %end2656 2657cmp.false:2658  %a3 = bitcast <11 x float> %a to <22 x i16>2659  br label %end2660 2661end:2662  %phi = phi <22 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]2663  ret <22 x i16> %phi2664}2665 2666define inreg <22 x i16> @bitcast_v11f32_to_v22i16_scalar(<11 x float> inreg %a, i32 inreg %b) {2667; SI-LABEL: bitcast_v11f32_to_v22i16_scalar:2668; SI:       ; %bb.0:2669; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2670; SI-NEXT:    s_cmp_lg_u32 s27, 02671; SI-NEXT:    s_cbranch_scc0 .LBB13_32672; SI-NEXT:  ; %bb.1: ; %cmp.false2673; SI-NEXT:    s_lshr_b32 s27, s17, 162674; SI-NEXT:    s_lshr_b32 s43, s25, 162675; SI-NEXT:    s_lshr_b32 s42, s23, 162676; SI-NEXT:    s_lshr_b32 s41, s21, 162677; SI-NEXT:    s_lshr_b32 s40, s19, 162678; SI-NEXT:    s_lshr_b64 s[8:9], s[26:27], 162679; SI-NEXT:    s_lshr_b64 s[4:5], s[24:25], 162680; SI-NEXT:    s_lshr_b64 s[6:7], s[22:23], 162681; SI-NEXT:    s_lshr_b64 s[10:11], s[20:21], 162682; SI-NEXT:    s_lshr_b64 s[12:13], s[18:19], 162683; SI-NEXT:    s_lshr_b64 s[14:15], s[16:17], 162684; SI-NEXT:    s_cbranch_execnz .LBB13_42685; SI-NEXT:  .LBB13_2: ; %cmp.true2686; SI-NEXT:    v_add_f32_e64 v20, s26, 1.02687; SI-NEXT:    v_add_f32_e64 v32, s17, 1.02688; SI-NEXT:    v_add_f32_e64 v31, s16, 1.02689; SI-NEXT:    v_add_f32_e64 v30, s19, 1.02690; SI-NEXT:    v_add_f32_e64 v29, s18, 1.02691; SI-NEXT:    v_add_f32_e64 v28, s21, 1.02692; SI-NEXT:    v_add_f32_e64 v27, s20, 1.02693; SI-NEXT:    v_add_f32_e64 v26, s23, 1.02694; SI-NEXT:    v_add_f32_e64 v25, s22, 1.02695; SI-NEXT:    v_add_f32_e64 v24, s25, 1.02696; SI-NEXT:    v_add_f32_e64 v23, s24, 1.02697; SI-NEXT:    v_lshr_b64 v[17:18], v[23:24], 162698; SI-NEXT:    v_lshr_b64 v[13:14], v[25:26], 162699; SI-NEXT:    v_lshr_b64 v[9:10], v[27:28], 162700; SI-NEXT:    v_lshr_b64 v[5:6], v[29:30], 162701; SI-NEXT:    v_lshr_b64 v[1:2], v[31:32], 162702; SI-NEXT:    v_lshr_b64 v[21:22], v[20:21], 162703; SI-NEXT:    v_lshrrev_b32_e32 v19, 16, v242704; SI-NEXT:    v_lshrrev_b32_e32 v15, 16, v262705; SI-NEXT:    v_lshrrev_b32_e32 v11, 16, v282706; SI-NEXT:    v_lshrrev_b32_e32 v7, 16, v302707; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v322708; SI-NEXT:    s_branch .LBB13_52709; SI-NEXT:  .LBB13_3:2710; SI-NEXT:    ; implicit-def: $sgpr142711; SI-NEXT:    ; implicit-def: $sgpr272712; SI-NEXT:    ; implicit-def: $sgpr122713; SI-NEXT:    ; implicit-def: $sgpr402714; SI-NEXT:    ; implicit-def: $sgpr102715; SI-NEXT:    ; implicit-def: $sgpr412716; SI-NEXT:    ; implicit-def: $sgpr62717; SI-NEXT:    ; implicit-def: $sgpr422718; SI-NEXT:    ; implicit-def: $sgpr42719; SI-NEXT:    ; implicit-def: $sgpr432720; SI-NEXT:    ; implicit-def: $sgpr82721; SI-NEXT:    s_branch .LBB13_22722; SI-NEXT:  .LBB13_4:2723; SI-NEXT:    v_mov_b32_e32 v31, s162724; SI-NEXT:    v_mov_b32_e32 v32, s172725; SI-NEXT:    v_mov_b32_e32 v29, s182726; SI-NEXT:    v_mov_b32_e32 v30, s192727; SI-NEXT:    v_mov_b32_e32 v27, s202728; SI-NEXT:    v_mov_b32_e32 v28, s212729; SI-NEXT:    v_mov_b32_e32 v25, s222730; SI-NEXT:    v_mov_b32_e32 v26, s232731; SI-NEXT:    v_mov_b32_e32 v23, s242732; SI-NEXT:    v_mov_b32_e32 v24, s252733; SI-NEXT:    v_mov_b32_e32 v20, s262734; SI-NEXT:    v_mov_b32_e32 v3, s272735; SI-NEXT:    v_mov_b32_e32 v7, s402736; SI-NEXT:    v_mov_b32_e32 v11, s412737; SI-NEXT:    v_mov_b32_e32 v15, s422738; SI-NEXT:    v_mov_b32_e32 v19, s432739; SI-NEXT:    v_mov_b32_e32 v21, s82740; SI-NEXT:    v_mov_b32_e32 v1, s142741; SI-NEXT:    v_mov_b32_e32 v5, s122742; SI-NEXT:    v_mov_b32_e32 v9, s102743; SI-NEXT:    v_mov_b32_e32 v13, s62744; SI-NEXT:    v_mov_b32_e32 v17, s42745; SI-NEXT:  .LBB13_5: ; %end2746; SI-NEXT:    v_mov_b32_e32 v0, v312747; SI-NEXT:    v_mov_b32_e32 v2, v322748; SI-NEXT:    v_mov_b32_e32 v4, v292749; SI-NEXT:    v_mov_b32_e32 v6, v302750; SI-NEXT:    v_mov_b32_e32 v8, v272751; SI-NEXT:    v_mov_b32_e32 v10, v282752; SI-NEXT:    v_mov_b32_e32 v12, v252753; SI-NEXT:    v_mov_b32_e32 v14, v262754; SI-NEXT:    v_mov_b32_e32 v16, v232755; SI-NEXT:    v_mov_b32_e32 v18, v242756; SI-NEXT:    s_setpc_b64 s[30:31]2757;2758; VI-LABEL: bitcast_v11f32_to_v22i16_scalar:2759; VI:       ; %bb.0:2760; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2761; VI-NEXT:    s_cmp_lg_u32 s27, 02762; VI-NEXT:    s_cbranch_scc0 .LBB13_32763; VI-NEXT:  ; %bb.1: ; %cmp.false2764; VI-NEXT:    s_cbranch_execnz .LBB13_42765; VI-NEXT:  .LBB13_2: ; %cmp.true2766; VI-NEXT:    v_add_f32_e64 v10, s26, 1.02767; VI-NEXT:    v_add_f32_e64 v9, s25, 1.02768; VI-NEXT:    v_add_f32_e64 v8, s24, 1.02769; VI-NEXT:    v_add_f32_e64 v7, s23, 1.02770; VI-NEXT:    v_add_f32_e64 v6, s22, 1.02771; VI-NEXT:    v_add_f32_e64 v5, s21, 1.02772; VI-NEXT:    v_add_f32_e64 v4, s20, 1.02773; VI-NEXT:    v_add_f32_e64 v3, s19, 1.02774; VI-NEXT:    v_add_f32_e64 v2, s18, 1.02775; VI-NEXT:    v_add_f32_e64 v1, s17, 1.02776; VI-NEXT:    v_add_f32_e64 v0, s16, 1.02777; VI-NEXT:    s_setpc_b64 s[30:31]2778; VI-NEXT:  .LBB13_3:2779; VI-NEXT:    s_branch .LBB13_22780; VI-NEXT:  .LBB13_4:2781; VI-NEXT:    v_mov_b32_e32 v0, s162782; VI-NEXT:    v_mov_b32_e32 v1, s172783; VI-NEXT:    v_mov_b32_e32 v2, s182784; VI-NEXT:    v_mov_b32_e32 v3, s192785; VI-NEXT:    v_mov_b32_e32 v4, s202786; VI-NEXT:    v_mov_b32_e32 v5, s212787; VI-NEXT:    v_mov_b32_e32 v6, s222788; VI-NEXT:    v_mov_b32_e32 v7, s232789; VI-NEXT:    v_mov_b32_e32 v8, s242790; VI-NEXT:    v_mov_b32_e32 v9, s252791; VI-NEXT:    v_mov_b32_e32 v10, s262792; VI-NEXT:    v_mov_b32_e32 v11, s272793; VI-NEXT:    v_mov_b32_e32 v12, s282794; VI-NEXT:    v_mov_b32_e32 v13, s292795; VI-NEXT:    v_mov_b32_e32 v14, s302796; VI-NEXT:    v_mov_b32_e32 v15, s312797; VI-NEXT:    s_setpc_b64 s[30:31]2798;2799; GFX9-LABEL: bitcast_v11f32_to_v22i16_scalar:2800; GFX9:       ; %bb.0:2801; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2802; GFX9-NEXT:    s_cmp_lg_u32 s27, 02803; GFX9-NEXT:    s_cbranch_scc0 .LBB13_32804; GFX9-NEXT:  ; %bb.1: ; %cmp.false2805; GFX9-NEXT:    s_cbranch_execnz .LBB13_42806; GFX9-NEXT:  .LBB13_2: ; %cmp.true2807; GFX9-NEXT:    v_add_f32_e64 v10, s26, 1.02808; GFX9-NEXT:    v_add_f32_e64 v9, s25, 1.02809; GFX9-NEXT:    v_add_f32_e64 v8, s24, 1.02810; GFX9-NEXT:    v_add_f32_e64 v7, s23, 1.02811; GFX9-NEXT:    v_add_f32_e64 v6, s22, 1.02812; GFX9-NEXT:    v_add_f32_e64 v5, s21, 1.02813; GFX9-NEXT:    v_add_f32_e64 v4, s20, 1.02814; GFX9-NEXT:    v_add_f32_e64 v3, s19, 1.02815; GFX9-NEXT:    v_add_f32_e64 v2, s18, 1.02816; GFX9-NEXT:    v_add_f32_e64 v1, s17, 1.02817; GFX9-NEXT:    v_add_f32_e64 v0, s16, 1.02818; GFX9-NEXT:    s_setpc_b64 s[30:31]2819; GFX9-NEXT:  .LBB13_3:2820; GFX9-NEXT:    s_branch .LBB13_22821; GFX9-NEXT:  .LBB13_4:2822; GFX9-NEXT:    v_mov_b32_e32 v0, s162823; GFX9-NEXT:    v_mov_b32_e32 v1, s172824; GFX9-NEXT:    v_mov_b32_e32 v2, s182825; GFX9-NEXT:    v_mov_b32_e32 v3, s192826; GFX9-NEXT:    v_mov_b32_e32 v4, s202827; GFX9-NEXT:    v_mov_b32_e32 v5, s212828; GFX9-NEXT:    v_mov_b32_e32 v6, s222829; GFX9-NEXT:    v_mov_b32_e32 v7, s232830; GFX9-NEXT:    v_mov_b32_e32 v8, s242831; GFX9-NEXT:    v_mov_b32_e32 v9, s252832; GFX9-NEXT:    v_mov_b32_e32 v10, s262833; GFX9-NEXT:    v_mov_b32_e32 v11, s272834; GFX9-NEXT:    v_mov_b32_e32 v12, s282835; GFX9-NEXT:    v_mov_b32_e32 v13, s292836; GFX9-NEXT:    v_mov_b32_e32 v14, s302837; GFX9-NEXT:    v_mov_b32_e32 v15, s312838; GFX9-NEXT:    s_setpc_b64 s[30:31]2839;2840; GFX11-LABEL: bitcast_v11f32_to_v22i16_scalar:2841; GFX11:       ; %bb.0:2842; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2843; GFX11-NEXT:    s_mov_b32 s15, s32844; GFX11-NEXT:    s_mov_b32 s14, s22845; GFX11-NEXT:    s_mov_b32 s13, s12846; GFX11-NEXT:    s_mov_b32 s12, s02847; GFX11-NEXT:    s_cmp_lg_u32 s23, 02848; GFX11-NEXT:    s_mov_b32 s0, 02849; GFX11-NEXT:    s_cbranch_scc0 .LBB13_32850; GFX11-NEXT:  ; %bb.1: ; %Flow2851; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s02852; GFX11-NEXT:    s_cbranch_vccnz .LBB13_42853; GFX11-NEXT:  .LBB13_2: ; %cmp.true2854; GFX11-NEXT:    v_add_f32_e64 v10, s22, 1.02855; GFX11-NEXT:    v_add_f32_e64 v9, s21, 1.02856; GFX11-NEXT:    v_add_f32_e64 v8, s20, 1.02857; GFX11-NEXT:    v_add_f32_e64 v7, s19, 1.02858; GFX11-NEXT:    v_add_f32_e64 v6, s18, 1.02859; GFX11-NEXT:    v_add_f32_e64 v5, s17, 1.02860; GFX11-NEXT:    v_add_f32_e64 v4, s16, 1.02861; GFX11-NEXT:    v_add_f32_e64 v3, s15, 1.02862; GFX11-NEXT:    v_add_f32_e64 v2, s14, 1.02863; GFX11-NEXT:    v_add_f32_e64 v1, s13, 1.02864; GFX11-NEXT:    v_add_f32_e64 v0, s12, 1.02865; GFX11-NEXT:    s_setpc_b64 s[30:31]2866; GFX11-NEXT:  .LBB13_3:2867; GFX11-NEXT:    s_branch .LBB13_22868; GFX11-NEXT:  .LBB13_4:2869; GFX11-NEXT:    v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s132870; GFX11-NEXT:    v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s152871; GFX11-NEXT:    v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s172872; GFX11-NEXT:    v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s192873; GFX11-NEXT:    v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s212874; GFX11-NEXT:    v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s232875; GFX11-NEXT:    v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s252876; GFX11-NEXT:    v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s272877; GFX11-NEXT:    s_setpc_b64 s[30:31]2878  %cmp = icmp eq i32 %b, 02879  br i1 %cmp, label %cmp.true, label %cmp.false2880 2881cmp.true:2882  %a1 = fadd <11 x float> %a, splat (float 1.000000e+00)2883  %a2 = bitcast <11 x float> %a1 to <22 x i16>2884  br label %end2885 2886cmp.false:2887  %a3 = bitcast <11 x float> %a to <22 x i16>2888  br label %end2889 2890end:2891  %phi = phi <22 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]2892  ret <22 x i16> %phi2893}2894 2895define <11 x float> @bitcast_v22i16_to_v11f32(<22 x i16> %a, i32 %b) {2896; SI-LABEL: bitcast_v22i16_to_v11f32:2897; SI:       ; %bb.0:2898; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2899; SI-NEXT:    v_mov_b32_e32 v28, v102900; SI-NEXT:    v_mov_b32_e32 v27, v82901; SI-NEXT:    v_mov_b32_e32 v26, v62902; SI-NEXT:    v_mov_b32_e32 v25, v42903; SI-NEXT:    v_mov_b32_e32 v24, v22904; SI-NEXT:    v_mov_b32_e32 v23, v02905; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v222906; SI-NEXT:    v_lshlrev_b32_e32 v35, 16, v12907; SI-NEXT:    v_lshlrev_b32_e32 v34, 16, v32908; SI-NEXT:    v_lshlrev_b32_e32 v33, 16, v52909; SI-NEXT:    v_lshlrev_b32_e32 v32, 16, v72910; SI-NEXT:    v_lshlrev_b32_e32 v31, 16, v92911; SI-NEXT:    v_lshlrev_b32_e32 v30, 16, v112912; SI-NEXT:    v_lshlrev_b32_e32 v29, 16, v132913; SI-NEXT:    v_lshlrev_b32_e32 v22, 16, v152914; SI-NEXT:    v_lshlrev_b32_e32 v15, 16, v172915; SI-NEXT:    v_lshlrev_b32_e32 v13, 16, v192916; SI-NEXT:    v_lshlrev_b32_e32 v11, 16, v212917; SI-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr102918; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc2919; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]2920; SI-NEXT:    s_cbranch_execnz .LBB14_32921; SI-NEXT:  ; %bb.1: ; %Flow2922; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]2923; SI-NEXT:    s_cbranch_execnz .LBB14_42924; SI-NEXT:  .LBB14_2: ; %end2925; SI-NEXT:    s_or_b64 exec, exec, s[4:5]2926; SI-NEXT:    s_setpc_b64 s[30:31]2927; SI-NEXT:  .LBB14_3: ; %cmp.false2928; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v232929; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v242930; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v252931; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v262932; SI-NEXT:    v_and_b32_e32 v4, 0xffff, v272933; SI-NEXT:    v_and_b32_e32 v5, 0xffff, v282934; SI-NEXT:    v_and_b32_e32 v6, 0xffff, v122935; SI-NEXT:    v_and_b32_e32 v7, 0xffff, v142936; SI-NEXT:    v_and_b32_e32 v8, 0xffff, v162937; SI-NEXT:    v_and_b32_e32 v9, 0xffff, v182938; SI-NEXT:    v_and_b32_e32 v10, 0xffff, v202939; SI-NEXT:    v_or_b32_e32 v0, v0, v352940; SI-NEXT:    v_or_b32_e32 v1, v1, v342941; SI-NEXT:    v_or_b32_e32 v2, v2, v332942; SI-NEXT:    v_or_b32_e32 v3, v3, v322943; SI-NEXT:    v_or_b32_e32 v4, v4, v312944; SI-NEXT:    v_or_b32_e32 v5, v5, v302945; SI-NEXT:    v_or_b32_e32 v6, v6, v292946; SI-NEXT:    v_or_b32_e32 v7, v7, v222947; SI-NEXT:    v_or_b32_e32 v8, v8, v152948; SI-NEXT:    v_or_b32_e32 v9, v9, v132949; SI-NEXT:    v_or_b32_e32 v10, v10, v112950; SI-NEXT:    ; implicit-def: $vgpr232951; SI-NEXT:    ; implicit-def: $vgpr242952; SI-NEXT:    ; implicit-def: $vgpr252953; SI-NEXT:    ; implicit-def: $vgpr262954; SI-NEXT:    ; implicit-def: $vgpr272955; SI-NEXT:    ; implicit-def: $vgpr282956; SI-NEXT:    ; implicit-def: $vgpr122957; SI-NEXT:    ; implicit-def: $vgpr142958; SI-NEXT:    ; implicit-def: $vgpr162959; SI-NEXT:    ; implicit-def: $vgpr182960; SI-NEXT:    ; implicit-def: $vgpr202961; SI-NEXT:    ; implicit-def: $vgpr352962; SI-NEXT:    ; implicit-def: $vgpr342963; SI-NEXT:    ; implicit-def: $vgpr332964; SI-NEXT:    ; implicit-def: $vgpr322965; SI-NEXT:    ; implicit-def: $vgpr312966; SI-NEXT:    ; implicit-def: $vgpr302967; SI-NEXT:    ; implicit-def: $vgpr292968; SI-NEXT:    ; implicit-def: $vgpr222969; SI-NEXT:    ; implicit-def: $vgpr152970; SI-NEXT:    ; implicit-def: $vgpr132971; SI-NEXT:    ; implicit-def: $vgpr112972; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]2973; SI-NEXT:    s_cbranch_execz .LBB14_22974; SI-NEXT:  .LBB14_4: ; %cmp.true2975; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v232976; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v242977; SI-NEXT:    v_add_i32_e32 v2, vcc, 3, v252978; SI-NEXT:    v_add_i32_e32 v3, vcc, 3, v262979; SI-NEXT:    v_add_i32_e32 v4, vcc, 3, v272980; SI-NEXT:    v_add_i32_e32 v5, vcc, 3, v282981; SI-NEXT:    v_add_i32_e32 v6, vcc, 3, v122982; SI-NEXT:    v_add_i32_e32 v7, vcc, 3, v142983; SI-NEXT:    v_add_i32_e32 v8, vcc, 3, v162984; SI-NEXT:    v_add_i32_e32 v9, vcc, 3, v182985; SI-NEXT:    v_add_i32_e32 v10, vcc, 3, v202986; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v02987; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v12988; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v22989; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v32990; SI-NEXT:    v_and_b32_e32 v4, 0xffff, v42991; SI-NEXT:    v_and_b32_e32 v5, 0xffff, v52992; SI-NEXT:    v_and_b32_e32 v6, 0xffff, v62993; SI-NEXT:    v_and_b32_e32 v7, 0xffff, v72994; SI-NEXT:    v_and_b32_e32 v8, 0xffff, v82995; SI-NEXT:    v_and_b32_e32 v9, 0xffff, v92996; SI-NEXT:    v_and_b32_e32 v10, 0xffff, v102997; SI-NEXT:    v_or_b32_e32 v0, v35, v02998; SI-NEXT:    s_mov_b32 s6, 0x300002999; SI-NEXT:    v_or_b32_e32 v1, v34, v13000; SI-NEXT:    v_or_b32_e32 v2, v33, v23001; SI-NEXT:    v_or_b32_e32 v3, v32, v33002; SI-NEXT:    v_or_b32_e32 v4, v31, v43003; SI-NEXT:    v_or_b32_e32 v5, v30, v53004; SI-NEXT:    v_or_b32_e32 v6, v29, v63005; SI-NEXT:    v_or_b32_e32 v7, v22, v73006; SI-NEXT:    v_or_b32_e32 v8, v15, v83007; SI-NEXT:    v_or_b32_e32 v9, v13, v93008; SI-NEXT:    v_or_b32_e32 v10, v11, v103009; SI-NEXT:    v_add_i32_e32 v0, vcc, 0x30000, v03010; SI-NEXT:    v_add_i32_e32 v1, vcc, s6, v13011; SI-NEXT:    v_add_i32_e32 v2, vcc, s6, v23012; SI-NEXT:    v_add_i32_e32 v3, vcc, s6, v33013; SI-NEXT:    v_add_i32_e32 v4, vcc, s6, v43014; SI-NEXT:    v_add_i32_e32 v5, vcc, s6, v53015; SI-NEXT:    v_add_i32_e32 v6, vcc, s6, v63016; SI-NEXT:    v_add_i32_e32 v7, vcc, s6, v73017; SI-NEXT:    v_add_i32_e32 v8, vcc, 0x30000, v83018; SI-NEXT:    v_add_i32_e32 v9, vcc, 0x30000, v93019; SI-NEXT:    v_add_i32_e32 v10, vcc, 0x30000, v103020; SI-NEXT:    s_or_b64 exec, exec, s[4:5]3021; SI-NEXT:    s_setpc_b64 s[30:31]3022;3023; VI-LABEL: bitcast_v22i16_to_v11f32:3024; VI:       ; %bb.0:3025; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3026; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v113027; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc3028; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]3029; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]3030; VI-NEXT:    s_cbranch_execz .LBB14_23031; VI-NEXT:  ; %bb.1: ; %cmp.true3032; VI-NEXT:    v_mov_b32_e32 v12, 33033; VI-NEXT:    v_add_u16_e32 v11, 3, v103034; VI-NEXT:    v_add_u16_sdwa v10, v10, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3035; VI-NEXT:    v_or_b32_e32 v10, v11, v103036; VI-NEXT:    v_add_u16_e32 v11, 3, v93037; VI-NEXT:    v_add_u16_sdwa v9, v9, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3038; VI-NEXT:    v_or_b32_e32 v9, v11, v93039; VI-NEXT:    v_add_u16_e32 v11, 3, v83040; VI-NEXT:    v_add_u16_sdwa v8, v8, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3041; VI-NEXT:    v_or_b32_e32 v8, v11, v83042; VI-NEXT:    v_add_u16_e32 v11, 3, v73043; VI-NEXT:    v_add_u16_sdwa v7, v7, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3044; VI-NEXT:    v_or_b32_e32 v7, v11, v73045; VI-NEXT:    v_add_u16_e32 v11, 3, v63046; VI-NEXT:    v_add_u16_sdwa v6, v6, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3047; VI-NEXT:    v_or_b32_e32 v6, v11, v63048; VI-NEXT:    v_add_u16_e32 v11, 3, v53049; VI-NEXT:    v_add_u16_sdwa v5, v5, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3050; VI-NEXT:    v_or_b32_e32 v5, v11, v53051; VI-NEXT:    v_add_u16_e32 v11, 3, v43052; VI-NEXT:    v_add_u16_sdwa v4, v4, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3053; VI-NEXT:    v_or_b32_e32 v4, v11, v43054; VI-NEXT:    v_add_u16_e32 v11, 3, v33055; VI-NEXT:    v_add_u16_sdwa v3, v3, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3056; VI-NEXT:    v_or_b32_e32 v3, v11, v33057; VI-NEXT:    v_add_u16_e32 v11, 3, v23058; VI-NEXT:    v_add_u16_sdwa v2, v2, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3059; VI-NEXT:    v_or_b32_e32 v2, v11, v23060; VI-NEXT:    v_add_u16_e32 v11, 3, v13061; VI-NEXT:    v_add_u16_sdwa v1, v1, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3062; VI-NEXT:    v_or_b32_e32 v1, v11, v13063; VI-NEXT:    v_add_u16_e32 v11, 3, v03064; VI-NEXT:    v_add_u16_sdwa v0, v0, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3065; VI-NEXT:    v_or_b32_e32 v0, v11, v03066; VI-NEXT:  .LBB14_2: ; %end3067; VI-NEXT:    s_or_b64 exec, exec, s[4:5]3068; VI-NEXT:    s_setpc_b64 s[30:31]3069;3070; GFX9-LABEL: bitcast_v22i16_to_v11f32:3071; GFX9:       ; %bb.0:3072; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3073; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v113074; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc3075; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]3076; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]3077; GFX9-NEXT:    s_cbranch_execz .LBB14_23078; GFX9-NEXT:  ; %bb.1: ; %cmp.true3079; GFX9-NEXT:    v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]3080; GFX9-NEXT:    v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]3081; GFX9-NEXT:    v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]3082; GFX9-NEXT:    v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]3083; GFX9-NEXT:    v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]3084; GFX9-NEXT:    v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]3085; GFX9-NEXT:    v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]3086; GFX9-NEXT:    v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]3087; GFX9-NEXT:    v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]3088; GFX9-NEXT:    v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]3089; GFX9-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]3090; GFX9-NEXT:  .LBB14_2: ; %end3091; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]3092; GFX9-NEXT:    s_setpc_b64 s[30:31]3093;3094; GFX11-LABEL: bitcast_v22i16_to_v11f32:3095; GFX11:       ; %bb.0:3096; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3097; GFX11-NEXT:    s_mov_b32 s0, exec_lo3098; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v113099; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s03100; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)3101; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s03102; GFX11-NEXT:    s_cbranch_execz .LBB14_23103; GFX11-NEXT:  ; %bb.1: ; %cmp.true3104; GFX11-NEXT:    v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]3105; GFX11-NEXT:    v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]3106; GFX11-NEXT:    v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]3107; GFX11-NEXT:    v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]3108; GFX11-NEXT:    v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]3109; GFX11-NEXT:    v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]3110; GFX11-NEXT:    v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]3111; GFX11-NEXT:    v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]3112; GFX11-NEXT:    v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]3113; GFX11-NEXT:    v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]3114; GFX11-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]3115; GFX11-NEXT:  .LBB14_2: ; %end3116; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s03117; GFX11-NEXT:    s_setpc_b64 s[30:31]3118  %cmp = icmp eq i32 %b, 03119  br i1 %cmp, label %cmp.true, label %cmp.false3120 3121cmp.true:3122  %a1 = add <22 x i16> %a, splat (i16 3)3123  %a2 = bitcast <22 x i16> %a1 to <11 x float>3124  br label %end3125 3126cmp.false:3127  %a3 = bitcast <22 x i16> %a to <11 x float>3128  br label %end3129 3130end:3131  %phi = phi <11 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]3132  ret <11 x float> %phi3133}3134 3135define inreg <11 x float> @bitcast_v22i16_to_v11f32_scalar(<22 x i16> inreg %a, i32 inreg %b) {3136; SI-LABEL: bitcast_v22i16_to_v11f32_scalar:3137; SI:       ; %bb.0:3138; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3139; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v83140; SI-NEXT:    v_mov_b32_e32 v11, v63141; SI-NEXT:    v_mov_b32_e32 v12, v43142; SI-NEXT:    v_mov_b32_e32 v13, v23143; SI-NEXT:    v_mov_b32_e32 v14, v03144; SI-NEXT:    s_and_b64 s[4:5], vcc, exec3145; SI-NEXT:    v_lshlrev_b32_e32 v18, 16, v13146; SI-NEXT:    v_lshlrev_b32_e32 v17, 16, v33147; SI-NEXT:    v_lshlrev_b32_e32 v16, 16, v53148; SI-NEXT:    v_lshlrev_b32_e32 v15, 16, v73149; SI-NEXT:    s_cbranch_scc0 .LBB15_43150; SI-NEXT:  ; %bb.1: ; %cmp.false3151; SI-NEXT:    s_and_b32 s4, s16, 0xffff3152; SI-NEXT:    s_lshl_b32 s5, s17, 163153; SI-NEXT:    s_or_b32 s4, s4, s53154; SI-NEXT:    s_and_b32 s5, s18, 0xffff3155; SI-NEXT:    s_lshl_b32 s6, s19, 163156; SI-NEXT:    s_or_b32 s5, s5, s63157; SI-NEXT:    s_and_b32 s6, s20, 0xffff3158; SI-NEXT:    s_lshl_b32 s7, s21, 163159; SI-NEXT:    s_or_b32 s6, s6, s73160; SI-NEXT:    s_and_b32 s7, s22, 0xffff3161; SI-NEXT:    s_lshl_b32 s8, s23, 163162; SI-NEXT:    s_or_b32 s7, s7, s83163; SI-NEXT:    s_and_b32 s8, s24, 0xffff3164; SI-NEXT:    s_lshl_b32 s9, s25, 163165; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v143166; SI-NEXT:    s_or_b32 s8, s8, s93167; SI-NEXT:    s_and_b32 s9, s26, 0xffff3168; SI-NEXT:    s_lshl_b32 s10, s27, 163169; SI-NEXT:    v_or_b32_e32 v7, v0, v183170; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v133171; SI-NEXT:    s_or_b32 s9, s9, s103172; SI-NEXT:    s_and_b32 s10, s28, 0xffff3173; SI-NEXT:    s_lshl_b32 s11, s29, 163174; SI-NEXT:    v_or_b32_e32 v8, v0, v173175; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v123176; SI-NEXT:    s_or_b32 s10, s10, s113177; SI-NEXT:    v_or_b32_e32 v9, v0, v163178; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v113179; SI-NEXT:    v_or_b32_e32 v10, v0, v153180; SI-NEXT:    v_mov_b32_e32 v0, s43181; SI-NEXT:    v_mov_b32_e32 v1, s53182; SI-NEXT:    v_mov_b32_e32 v2, s63183; SI-NEXT:    v_mov_b32_e32 v3, s73184; SI-NEXT:    v_mov_b32_e32 v4, s83185; SI-NEXT:    v_mov_b32_e32 v5, s93186; SI-NEXT:    v_mov_b32_e32 v6, s103187; SI-NEXT:    s_cbranch_execnz .LBB15_33188; SI-NEXT:  .LBB15_2: ; %cmp.true3189; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v143190; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v03191; SI-NEXT:    s_add_i32 s16, s16, 33192; SI-NEXT:    v_or_b32_e32 v0, v18, v03193; SI-NEXT:    s_and_b32 s4, s16, 0xffff3194; SI-NEXT:    s_lshl_b32 s5, s17, 163195; SI-NEXT:    s_add_i32 s18, s18, 33196; SI-NEXT:    v_add_i32_e32 v7, vcc, 0x30000, v03197; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v133198; SI-NEXT:    s_or_b32 s4, s5, s43199; SI-NEXT:    s_and_b32 s5, s18, 0xffff3200; SI-NEXT:    s_lshl_b32 s6, s19, 163201; SI-NEXT:    s_add_i32 s20, s20, 33202; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v03203; SI-NEXT:    s_or_b32 s5, s6, s53204; SI-NEXT:    s_and_b32 s6, s20, 0xffff3205; SI-NEXT:    s_lshl_b32 s7, s21, 163206; SI-NEXT:    s_add_i32 s22, s22, 33207; SI-NEXT:    v_or_b32_e32 v0, v17, v03208; SI-NEXT:    s_or_b32 s6, s7, s63209; SI-NEXT:    s_and_b32 s7, s22, 0xffff3210; SI-NEXT:    s_lshl_b32 s8, s23, 163211; SI-NEXT:    s_add_i32 s24, s24, 33212; SI-NEXT:    v_add_i32_e32 v8, vcc, 0x30000, v03213; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v123214; SI-NEXT:    s_or_b32 s7, s8, s73215; SI-NEXT:    s_and_b32 s8, s24, 0xffff3216; SI-NEXT:    s_lshl_b32 s9, s25, 163217; SI-NEXT:    s_add_i32 s26, s26, 33218; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v03219; SI-NEXT:    s_or_b32 s8, s9, s83220; SI-NEXT:    s_and_b32 s9, s26, 0xffff3221; SI-NEXT:    s_lshl_b32 s10, s27, 163222; SI-NEXT:    s_add_i32 s28, s28, 33223; SI-NEXT:    v_or_b32_e32 v0, v16, v03224; SI-NEXT:    s_or_b32 s9, s10, s93225; SI-NEXT:    s_and_b32 s10, s28, 0xffff3226; SI-NEXT:    s_lshl_b32 s11, s29, 163227; SI-NEXT:    v_add_i32_e32 v9, vcc, 0x30000, v03228; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v113229; SI-NEXT:    s_or_b32 s10, s11, s103230; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v03231; SI-NEXT:    s_add_i32 s4, s4, 0x300003232; SI-NEXT:    s_add_i32 s5, s5, 0x300003233; SI-NEXT:    s_add_i32 s6, s6, 0x300003234; SI-NEXT:    s_add_i32 s7, s7, 0x300003235; SI-NEXT:    s_add_i32 s8, s8, 0x300003236; SI-NEXT:    s_add_i32 s9, s9, 0x300003237; SI-NEXT:    s_add_i32 s10, s10, 0x300003238; SI-NEXT:    v_or_b32_e32 v0, v15, v03239; SI-NEXT:    v_add_i32_e32 v10, vcc, 0x30000, v03240; SI-NEXT:    v_mov_b32_e32 v0, s43241; SI-NEXT:    v_mov_b32_e32 v1, s53242; SI-NEXT:    v_mov_b32_e32 v2, s63243; SI-NEXT:    v_mov_b32_e32 v3, s73244; SI-NEXT:    v_mov_b32_e32 v4, s83245; SI-NEXT:    v_mov_b32_e32 v5, s93246; SI-NEXT:    v_mov_b32_e32 v6, s103247; SI-NEXT:  .LBB15_3: ; %end3248; SI-NEXT:    s_setpc_b64 s[30:31]3249; SI-NEXT:  .LBB15_4:3250; SI-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr103251; SI-NEXT:    s_branch .LBB15_23252;3253; VI-LABEL: bitcast_v22i16_to_v11f32_scalar:3254; VI:       ; %bb.0:3255; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3256; VI-NEXT:    s_cmp_lg_u32 s27, 03257; VI-NEXT:    s_cbranch_scc0 .LBB15_43258; VI-NEXT:  ; %bb.1: ; %cmp.false3259; VI-NEXT:    s_cbranch_execnz .LBB15_33260; VI-NEXT:  .LBB15_2: ; %cmp.true3261; VI-NEXT:    s_add_i32 s5, s26, 33262; VI-NEXT:    s_and_b32 s4, s26, 0xffff00003263; VI-NEXT:    s_and_b32 s5, s5, 0xffff3264; VI-NEXT:    s_or_b32 s4, s4, s53265; VI-NEXT:    s_add_i32 s5, s25, 33266; VI-NEXT:    s_add_i32 s26, s4, 0x300003267; VI-NEXT:    s_and_b32 s4, s25, 0xffff00003268; VI-NEXT:    s_and_b32 s5, s5, 0xffff3269; VI-NEXT:    s_or_b32 s4, s4, s53270; VI-NEXT:    s_add_i32 s5, s24, 33271; VI-NEXT:    s_add_i32 s25, s4, 0x300003272; VI-NEXT:    s_and_b32 s4, s24, 0xffff00003273; VI-NEXT:    s_and_b32 s5, s5, 0xffff3274; VI-NEXT:    s_or_b32 s4, s4, s53275; VI-NEXT:    s_add_i32 s5, s23, 33276; VI-NEXT:    s_add_i32 s24, s4, 0x300003277; VI-NEXT:    s_and_b32 s4, s23, 0xffff00003278; VI-NEXT:    s_and_b32 s5, s5, 0xffff3279; VI-NEXT:    s_or_b32 s4, s4, s53280; VI-NEXT:    s_add_i32 s5, s22, 33281; VI-NEXT:    s_add_i32 s23, s4, 0x300003282; VI-NEXT:    s_and_b32 s4, s22, 0xffff00003283; VI-NEXT:    s_and_b32 s5, s5, 0xffff3284; VI-NEXT:    s_or_b32 s4, s4, s53285; VI-NEXT:    s_add_i32 s5, s21, 33286; VI-NEXT:    s_add_i32 s22, s4, 0x300003287; VI-NEXT:    s_and_b32 s4, s21, 0xffff00003288; VI-NEXT:    s_and_b32 s5, s5, 0xffff3289; VI-NEXT:    s_or_b32 s4, s4, s53290; VI-NEXT:    s_add_i32 s5, s20, 33291; VI-NEXT:    s_add_i32 s21, s4, 0x300003292; VI-NEXT:    s_and_b32 s4, s20, 0xffff00003293; VI-NEXT:    s_and_b32 s5, s5, 0xffff3294; VI-NEXT:    s_or_b32 s4, s4, s53295; VI-NEXT:    s_add_i32 s5, s19, 33296; VI-NEXT:    s_add_i32 s20, s4, 0x300003297; VI-NEXT:    s_and_b32 s4, s19, 0xffff00003298; VI-NEXT:    s_and_b32 s5, s5, 0xffff3299; VI-NEXT:    s_or_b32 s4, s4, s53300; VI-NEXT:    s_add_i32 s5, s18, 33301; VI-NEXT:    s_add_i32 s19, s4, 0x300003302; VI-NEXT:    s_and_b32 s4, s18, 0xffff00003303; VI-NEXT:    s_and_b32 s5, s5, 0xffff3304; VI-NEXT:    s_or_b32 s4, s4, s53305; VI-NEXT:    s_add_i32 s5, s17, 33306; VI-NEXT:    s_add_i32 s18, s4, 0x300003307; VI-NEXT:    s_and_b32 s4, s17, 0xffff00003308; VI-NEXT:    s_and_b32 s5, s5, 0xffff3309; VI-NEXT:    s_or_b32 s4, s4, s53310; VI-NEXT:    s_add_i32 s5, s16, 33311; VI-NEXT:    s_add_i32 s17, s4, 0x300003312; VI-NEXT:    s_and_b32 s4, s16, 0xffff00003313; VI-NEXT:    s_and_b32 s5, s5, 0xffff3314; VI-NEXT:    s_or_b32 s4, s4, s53315; VI-NEXT:    s_add_i32 s16, s4, 0x300003316; VI-NEXT:  .LBB15_3: ; %end3317; VI-NEXT:    v_mov_b32_e32 v0, s163318; VI-NEXT:    v_mov_b32_e32 v1, s173319; VI-NEXT:    v_mov_b32_e32 v2, s183320; VI-NEXT:    v_mov_b32_e32 v3, s193321; VI-NEXT:    v_mov_b32_e32 v4, s203322; VI-NEXT:    v_mov_b32_e32 v5, s213323; VI-NEXT:    v_mov_b32_e32 v6, s223324; VI-NEXT:    v_mov_b32_e32 v7, s233325; VI-NEXT:    v_mov_b32_e32 v8, s243326; VI-NEXT:    v_mov_b32_e32 v9, s253327; VI-NEXT:    v_mov_b32_e32 v10, s263328; VI-NEXT:    s_setpc_b64 s[30:31]3329; VI-NEXT:  .LBB15_4:3330; VI-NEXT:    s_branch .LBB15_23331;3332; GFX9-LABEL: bitcast_v22i16_to_v11f32_scalar:3333; GFX9:       ; %bb.0:3334; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3335; GFX9-NEXT:    s_cmp_lg_u32 s27, 03336; GFX9-NEXT:    s_cbranch_scc0 .LBB15_33337; GFX9-NEXT:  ; %bb.1: ; %cmp.false3338; GFX9-NEXT:    s_cbranch_execnz .LBB15_43339; GFX9-NEXT:  .LBB15_2: ; %cmp.true3340; GFX9-NEXT:    v_pk_add_u16 v10, s26, 3 op_sel_hi:[1,0]3341; GFX9-NEXT:    v_pk_add_u16 v9, s25, 3 op_sel_hi:[1,0]3342; GFX9-NEXT:    v_pk_add_u16 v8, s24, 3 op_sel_hi:[1,0]3343; GFX9-NEXT:    v_pk_add_u16 v7, s23, 3 op_sel_hi:[1,0]3344; GFX9-NEXT:    v_pk_add_u16 v6, s22, 3 op_sel_hi:[1,0]3345; GFX9-NEXT:    v_pk_add_u16 v5, s21, 3 op_sel_hi:[1,0]3346; GFX9-NEXT:    v_pk_add_u16 v4, s20, 3 op_sel_hi:[1,0]3347; GFX9-NEXT:    v_pk_add_u16 v3, s19, 3 op_sel_hi:[1,0]3348; GFX9-NEXT:    v_pk_add_u16 v2, s18, 3 op_sel_hi:[1,0]3349; GFX9-NEXT:    v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]3350; GFX9-NEXT:    v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]3351; GFX9-NEXT:    s_setpc_b64 s[30:31]3352; GFX9-NEXT:  .LBB15_3:3353; GFX9-NEXT:    s_branch .LBB15_23354; GFX9-NEXT:  .LBB15_4:3355; GFX9-NEXT:    v_mov_b32_e32 v0, s163356; GFX9-NEXT:    v_mov_b32_e32 v1, s173357; GFX9-NEXT:    v_mov_b32_e32 v2, s183358; GFX9-NEXT:    v_mov_b32_e32 v3, s193359; GFX9-NEXT:    v_mov_b32_e32 v4, s203360; GFX9-NEXT:    v_mov_b32_e32 v5, s213361; GFX9-NEXT:    v_mov_b32_e32 v6, s223362; GFX9-NEXT:    v_mov_b32_e32 v7, s233363; GFX9-NEXT:    v_mov_b32_e32 v8, s243364; GFX9-NEXT:    v_mov_b32_e32 v9, s253365; GFX9-NEXT:    v_mov_b32_e32 v10, s263366; GFX9-NEXT:    s_setpc_b64 s[30:31]3367;3368; GFX11-LABEL: bitcast_v22i16_to_v11f32_scalar:3369; GFX11:       ; %bb.0:3370; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3371; GFX11-NEXT:    s_mov_b32 s15, s33372; GFX11-NEXT:    s_mov_b32 s14, s23373; GFX11-NEXT:    s_mov_b32 s13, s13374; GFX11-NEXT:    s_mov_b32 s12, s03375; GFX11-NEXT:    s_cmp_lg_u32 s23, 03376; GFX11-NEXT:    s_mov_b32 s0, 03377; GFX11-NEXT:    s_cbranch_scc0 .LBB15_33378; GFX11-NEXT:  ; %bb.1: ; %Flow3379; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s03380; GFX11-NEXT:    s_cbranch_vccnz .LBB15_43381; GFX11-NEXT:  .LBB15_2: ; %cmp.true3382; GFX11-NEXT:    v_pk_add_u16 v10, s22, 3 op_sel_hi:[1,0]3383; GFX11-NEXT:    v_pk_add_u16 v9, s21, 3 op_sel_hi:[1,0]3384; GFX11-NEXT:    v_pk_add_u16 v8, s20, 3 op_sel_hi:[1,0]3385; GFX11-NEXT:    v_pk_add_u16 v7, s19, 3 op_sel_hi:[1,0]3386; GFX11-NEXT:    v_pk_add_u16 v6, s18, 3 op_sel_hi:[1,0]3387; GFX11-NEXT:    v_pk_add_u16 v5, s17, 3 op_sel_hi:[1,0]3388; GFX11-NEXT:    v_pk_add_u16 v4, s16, 3 op_sel_hi:[1,0]3389; GFX11-NEXT:    v_pk_add_u16 v3, s15, 3 op_sel_hi:[1,0]3390; GFX11-NEXT:    v_pk_add_u16 v2, s14, 3 op_sel_hi:[1,0]3391; GFX11-NEXT:    v_pk_add_u16 v1, s13, 3 op_sel_hi:[1,0]3392; GFX11-NEXT:    v_pk_add_u16 v0, s12, 3 op_sel_hi:[1,0]3393; GFX11-NEXT:    s_setpc_b64 s[30:31]3394; GFX11-NEXT:  .LBB15_3:3395; GFX11-NEXT:    s_branch .LBB15_23396; GFX11-NEXT:  .LBB15_4:3397; GFX11-NEXT:    v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s133398; GFX11-NEXT:    v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s153399; GFX11-NEXT:    v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s173400; GFX11-NEXT:    v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s193401; GFX11-NEXT:    v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s213402; GFX11-NEXT:    v_mov_b32_e32 v10, s223403; GFX11-NEXT:    s_setpc_b64 s[30:31]3404  %cmp = icmp eq i32 %b, 03405  br i1 %cmp, label %cmp.true, label %cmp.false3406 3407cmp.true:3408  %a1 = add <22 x i16> %a, splat (i16 3)3409  %a2 = bitcast <22 x i16> %a1 to <11 x float>3410  br label %end3411 3412cmp.false:3413  %a3 = bitcast <22 x i16> %a to <11 x float>3414  br label %end3415 3416end:3417  %phi = phi <11 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]3418  ret <11 x float> %phi3419}3420 3421define <22 x half> @bitcast_v11f32_to_v22f16(<11 x float> %a, i32 %b) {3422; SI-LABEL: bitcast_v11f32_to_v22f16:3423; SI:       ; %bb.0:3424; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3425; SI-NEXT:    v_mov_b32_e32 v32, v103426; SI-NEXT:    v_mov_b32_e32 v31, v93427; SI-NEXT:    v_mov_b32_e32 v30, v83428; SI-NEXT:    v_mov_b32_e32 v29, v73429; SI-NEXT:    v_mov_b32_e32 v28, v63430; SI-NEXT:    v_mov_b32_e32 v27, v53431; SI-NEXT:    v_mov_b32_e32 v26, v43432; SI-NEXT:    v_mov_b32_e32 v25, v33433; SI-NEXT:    v_mov_b32_e32 v24, v23434; SI-NEXT:    v_mov_b32_e32 v23, v13435; SI-NEXT:    v_mov_b32_e32 v22, v03436; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v113437; SI-NEXT:    ; implicit-def: $vgpr03438; SI-NEXT:    ; implicit-def: $vgpr13439; SI-NEXT:    ; implicit-def: $vgpr23440; SI-NEXT:    ; implicit-def: $vgpr33441; SI-NEXT:    ; implicit-def: $vgpr43442; SI-NEXT:    ; implicit-def: $vgpr53443; SI-NEXT:    ; implicit-def: $vgpr63444; SI-NEXT:    ; implicit-def: $vgpr73445; SI-NEXT:    ; implicit-def: $vgpr83446; SI-NEXT:    ; implicit-def: $vgpr93447; SI-NEXT:    ; implicit-def: $vgpr103448; SI-NEXT:    ; implicit-def: $vgpr113449; SI-NEXT:    ; implicit-def: $vgpr123450; SI-NEXT:    ; implicit-def: $vgpr133451; SI-NEXT:    ; implicit-def: $vgpr143452; SI-NEXT:    ; implicit-def: $vgpr153453; SI-NEXT:    ; implicit-def: $vgpr163454; SI-NEXT:    ; implicit-def: $vgpr173455; SI-NEXT:    ; implicit-def: $vgpr183456; SI-NEXT:    ; implicit-def: $vgpr193457; SI-NEXT:    ; implicit-def: $vgpr203458; SI-NEXT:    ; implicit-def: $vgpr213459; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc3460; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]3461; SI-NEXT:    s_cbranch_execnz .LBB16_33462; SI-NEXT:  ; %bb.1: ; %Flow3463; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]3464; SI-NEXT:    s_cbranch_execnz .LBB16_43465; SI-NEXT:  .LBB16_2: ; %end3466; SI-NEXT:    s_or_b64 exec, exec, s[4:5]3467; SI-NEXT:    s_setpc_b64 s[30:31]3468; SI-NEXT:  .LBB16_3: ; %cmp.false3469; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v323470; SI-NEXT:    v_cvt_f32_f16_e32 v21, v03471; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v313472; SI-NEXT:    v_cvt_f32_f16_e32 v19, v03473; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v303474; SI-NEXT:    v_cvt_f32_f16_e32 v17, v03475; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v293476; SI-NEXT:    v_cvt_f32_f16_e32 v15, v03477; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v283478; SI-NEXT:    v_cvt_f32_f16_e32 v13, v03479; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v273480; SI-NEXT:    v_cvt_f32_f16_e32 v11, v03481; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v263482; SI-NEXT:    v_cvt_f32_f16_e32 v9, v03483; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v253484; SI-NEXT:    v_cvt_f32_f16_e32 v7, v03485; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v243486; SI-NEXT:    v_cvt_f32_f16_e32 v5, v03487; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v233488; SI-NEXT:    v_cvt_f32_f16_e32 v3, v03489; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v223490; SI-NEXT:    v_cvt_f32_f16_e32 v1, v03491; SI-NEXT:    v_cvt_f32_f16_e32 v20, v323492; SI-NEXT:    v_cvt_f32_f16_e32 v18, v313493; SI-NEXT:    v_cvt_f32_f16_e32 v16, v303494; SI-NEXT:    v_cvt_f32_f16_e32 v14, v293495; SI-NEXT:    v_cvt_f32_f16_e32 v12, v283496; SI-NEXT:    v_cvt_f32_f16_e32 v10, v273497; SI-NEXT:    v_cvt_f32_f16_e32 v8, v263498; SI-NEXT:    v_cvt_f32_f16_e32 v6, v253499; SI-NEXT:    v_cvt_f32_f16_e32 v4, v243500; SI-NEXT:    v_cvt_f32_f16_e32 v2, v233501; SI-NEXT:    v_cvt_f32_f16_e32 v0, v223502; SI-NEXT:    ; implicit-def: $vgpr223503; SI-NEXT:    ; implicit-def: $vgpr233504; SI-NEXT:    ; implicit-def: $vgpr243505; SI-NEXT:    ; implicit-def: $vgpr253506; SI-NEXT:    ; implicit-def: $vgpr263507; SI-NEXT:    ; implicit-def: $vgpr273508; SI-NEXT:    ; implicit-def: $vgpr283509; SI-NEXT:    ; implicit-def: $vgpr293510; SI-NEXT:    ; implicit-def: $vgpr303511; SI-NEXT:    ; implicit-def: $vgpr313512; SI-NEXT:    ; implicit-def: $vgpr323513; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]3514; SI-NEXT:    s_cbranch_execz .LBB16_23515; SI-NEXT:  .LBB16_4: ; %cmp.true3516; SI-NEXT:    v_add_f32_e32 v1, 1.0, v223517; SI-NEXT:    v_add_f32_e32 v3, 1.0, v233518; SI-NEXT:    v_add_f32_e32 v5, 1.0, v243519; SI-NEXT:    v_add_f32_e32 v7, 1.0, v253520; SI-NEXT:    v_add_f32_e32 v9, 1.0, v263521; SI-NEXT:    v_add_f32_e32 v11, 1.0, v273522; SI-NEXT:    v_add_f32_e32 v13, 1.0, v283523; SI-NEXT:    v_add_f32_e32 v15, 1.0, v293524; SI-NEXT:    v_add_f32_e32 v17, 1.0, v303525; SI-NEXT:    v_add_f32_e32 v19, 1.0, v313526; SI-NEXT:    v_add_f32_e32 v21, 1.0, v323527; SI-NEXT:    v_cvt_f32_f16_e32 v20, v213528; SI-NEXT:    v_cvt_f32_f16_e32 v18, v193529; SI-NEXT:    v_cvt_f32_f16_e32 v16, v173530; SI-NEXT:    v_cvt_f32_f16_e32 v14, v153531; SI-NEXT:    v_cvt_f32_f16_e32 v12, v133532; SI-NEXT:    v_cvt_f32_f16_e32 v10, v113533; SI-NEXT:    v_cvt_f32_f16_e32 v8, v93534; SI-NEXT:    v_cvt_f32_f16_e32 v6, v73535; SI-NEXT:    v_cvt_f32_f16_e32 v4, v53536; SI-NEXT:    v_cvt_f32_f16_e32 v2, v33537; SI-NEXT:    v_cvt_f32_f16_e32 v0, v13538; SI-NEXT:    v_lshrrev_b32_e32 v21, 16, v213539; SI-NEXT:    v_lshrrev_b32_e32 v19, 16, v193540; SI-NEXT:    v_lshrrev_b32_e32 v17, 16, v173541; SI-NEXT:    v_lshrrev_b32_e32 v15, 16, v153542; SI-NEXT:    v_lshrrev_b32_e32 v13, 16, v133543; SI-NEXT:    v_lshrrev_b32_e32 v11, 16, v113544; SI-NEXT:    v_lshrrev_b32_e32 v9, 16, v93545; SI-NEXT:    v_lshrrev_b32_e32 v7, 16, v73546; SI-NEXT:    v_lshrrev_b32_e32 v5, 16, v53547; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v33548; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v13549; SI-NEXT:    v_cvt_f32_f16_e32 v21, v213550; SI-NEXT:    v_cvt_f32_f16_e32 v19, v193551; SI-NEXT:    v_cvt_f32_f16_e32 v17, v173552; SI-NEXT:    v_cvt_f32_f16_e32 v15, v153553; SI-NEXT:    v_cvt_f32_f16_e32 v13, v133554; SI-NEXT:    v_cvt_f32_f16_e32 v11, v113555; SI-NEXT:    v_cvt_f32_f16_e32 v9, v93556; SI-NEXT:    v_cvt_f32_f16_e32 v7, v73557; SI-NEXT:    v_cvt_f32_f16_e32 v5, v53558; SI-NEXT:    v_cvt_f32_f16_e32 v3, v33559; SI-NEXT:    v_cvt_f32_f16_e32 v1, v13560; SI-NEXT:    s_or_b64 exec, exec, s[4:5]3561; SI-NEXT:    s_setpc_b64 s[30:31]3562;3563; VI-LABEL: bitcast_v11f32_to_v22f16:3564; VI:       ; %bb.0:3565; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3566; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v113567; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc3568; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]3569; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]3570; VI-NEXT:    s_cbranch_execz .LBB16_23571; VI-NEXT:  ; %bb.1: ; %cmp.true3572; VI-NEXT:    v_add_f32_e32 v10, 1.0, v103573; VI-NEXT:    v_add_f32_e32 v9, 1.0, v93574; VI-NEXT:    v_add_f32_e32 v8, 1.0, v83575; VI-NEXT:    v_add_f32_e32 v7, 1.0, v73576; VI-NEXT:    v_add_f32_e32 v6, 1.0, v63577; VI-NEXT:    v_add_f32_e32 v5, 1.0, v53578; VI-NEXT:    v_add_f32_e32 v4, 1.0, v43579; VI-NEXT:    v_add_f32_e32 v3, 1.0, v33580; VI-NEXT:    v_add_f32_e32 v2, 1.0, v23581; VI-NEXT:    v_add_f32_e32 v1, 1.0, v13582; VI-NEXT:    v_add_f32_e32 v0, 1.0, v03583; VI-NEXT:  .LBB16_2: ; %end3584; VI-NEXT:    s_or_b64 exec, exec, s[4:5]3585; VI-NEXT:    s_setpc_b64 s[30:31]3586;3587; GFX9-LABEL: bitcast_v11f32_to_v22f16:3588; GFX9:       ; %bb.0:3589; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3590; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v113591; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc3592; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]3593; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]3594; GFX9-NEXT:    s_cbranch_execz .LBB16_23595; GFX9-NEXT:  ; %bb.1: ; %cmp.true3596; GFX9-NEXT:    v_add_f32_e32 v10, 1.0, v103597; GFX9-NEXT:    v_add_f32_e32 v9, 1.0, v93598; GFX9-NEXT:    v_add_f32_e32 v8, 1.0, v83599; GFX9-NEXT:    v_add_f32_e32 v7, 1.0, v73600; GFX9-NEXT:    v_add_f32_e32 v6, 1.0, v63601; GFX9-NEXT:    v_add_f32_e32 v5, 1.0, v53602; GFX9-NEXT:    v_add_f32_e32 v4, 1.0, v43603; GFX9-NEXT:    v_add_f32_e32 v3, 1.0, v33604; GFX9-NEXT:    v_add_f32_e32 v2, 1.0, v23605; GFX9-NEXT:    v_add_f32_e32 v1, 1.0, v13606; GFX9-NEXT:    v_add_f32_e32 v0, 1.0, v03607; GFX9-NEXT:  .LBB16_2: ; %end3608; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]3609; GFX9-NEXT:    s_setpc_b64 s[30:31]3610;3611; GFX11-LABEL: bitcast_v11f32_to_v22f16:3612; GFX11:       ; %bb.0:3613; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3614; GFX11-NEXT:    s_mov_b32 s0, exec_lo3615; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v113616; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s03617; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)3618; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s03619; GFX11-NEXT:  ; %bb.1: ; %cmp.true3620; GFX11-NEXT:    v_dual_add_f32 v10, 1.0, v10 :: v_dual_add_f32 v9, 1.0, v93621; GFX11-NEXT:    v_dual_add_f32 v8, 1.0, v8 :: v_dual_add_f32 v7, 1.0, v73622; GFX11-NEXT:    v_dual_add_f32 v6, 1.0, v6 :: v_dual_add_f32 v5, 1.0, v53623; GFX11-NEXT:    v_dual_add_f32 v4, 1.0, v4 :: v_dual_add_f32 v3, 1.0, v33624; GFX11-NEXT:    v_dual_add_f32 v2, 1.0, v2 :: v_dual_add_f32 v1, 1.0, v13625; GFX11-NEXT:    v_add_f32_e32 v0, 1.0, v03626; GFX11-NEXT:  ; %bb.2: ; %end3627; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s03628; GFX11-NEXT:    s_setpc_b64 s[30:31]3629  %cmp = icmp eq i32 %b, 03630  br i1 %cmp, label %cmp.true, label %cmp.false3631 3632cmp.true:3633  %a1 = fadd <11 x float> %a, splat (float 1.000000e+00)3634  %a2 = bitcast <11 x float> %a1 to <22 x half>3635  br label %end3636 3637cmp.false:3638  %a3 = bitcast <11 x float> %a to <22 x half>3639  br label %end3640 3641end:3642  %phi = phi <22 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]3643  ret <22 x half> %phi3644}3645 3646define inreg <22 x half> @bitcast_v11f32_to_v22f16_scalar(<11 x float> inreg %a, i32 inreg %b) {3647; SI-LABEL: bitcast_v11f32_to_v22f16_scalar:3648; SI:       ; %bb.0:3649; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3650; SI-NEXT:    s_cmp_lg_u32 s27, 03651; SI-NEXT:    s_cbranch_scc0 .LBB17_43652; SI-NEXT:  ; %bb.1: ; %cmp.false3653; SI-NEXT:    s_lshr_b32 s4, s26, 163654; SI-NEXT:    v_cvt_f32_f16_e32 v21, s43655; SI-NEXT:    s_lshr_b32 s4, s25, 163656; SI-NEXT:    v_cvt_f32_f16_e32 v19, s43657; SI-NEXT:    s_lshr_b32 s4, s24, 163658; SI-NEXT:    v_cvt_f32_f16_e32 v17, s43659; SI-NEXT:    s_lshr_b32 s4, s23, 163660; SI-NEXT:    v_cvt_f32_f16_e32 v15, s43661; SI-NEXT:    s_lshr_b32 s4, s22, 163662; SI-NEXT:    v_cvt_f32_f16_e32 v13, s43663; SI-NEXT:    s_lshr_b32 s4, s21, 163664; SI-NEXT:    v_cvt_f32_f16_e32 v11, s43665; SI-NEXT:    s_lshr_b32 s4, s20, 163666; SI-NEXT:    v_cvt_f32_f16_e32 v9, s43667; SI-NEXT:    s_lshr_b32 s4, s19, 163668; SI-NEXT:    v_cvt_f32_f16_e32 v7, s43669; SI-NEXT:    s_lshr_b32 s4, s18, 163670; SI-NEXT:    v_cvt_f32_f16_e32 v5, s43671; SI-NEXT:    s_lshr_b32 s4, s17, 163672; SI-NEXT:    v_cvt_f32_f16_e32 v3, s43673; SI-NEXT:    s_lshr_b32 s4, s16, 163674; SI-NEXT:    v_cvt_f32_f16_e32 v1, s43675; SI-NEXT:    v_cvt_f32_f16_e32 v20, s263676; SI-NEXT:    v_cvt_f32_f16_e32 v18, s253677; SI-NEXT:    v_cvt_f32_f16_e32 v16, s243678; SI-NEXT:    v_cvt_f32_f16_e32 v14, s233679; SI-NEXT:    v_cvt_f32_f16_e32 v12, s223680; SI-NEXT:    v_cvt_f32_f16_e32 v10, s213681; SI-NEXT:    v_cvt_f32_f16_e32 v8, s203682; SI-NEXT:    v_cvt_f32_f16_e32 v6, s193683; SI-NEXT:    v_cvt_f32_f16_e32 v4, s183684; SI-NEXT:    v_cvt_f32_f16_e32 v2, s173685; SI-NEXT:    v_cvt_f32_f16_e32 v0, s163686; SI-NEXT:    s_cbranch_execnz .LBB17_33687; SI-NEXT:  .LBB17_2: ; %cmp.true3688; SI-NEXT:    v_add_f32_e64 v1, s18, 1.03689; SI-NEXT:    v_add_f32_e64 v5, s20, 1.03690; SI-NEXT:    v_add_f32_e64 v9, s22, 1.03691; SI-NEXT:    v_add_f32_e64 v13, s24, 1.03692; SI-NEXT:    v_add_f32_e64 v17, s26, 1.03693; SI-NEXT:    v_add_f32_e64 v0, s17, 1.03694; SI-NEXT:    v_add_f32_e64 v3, s19, 1.03695; SI-NEXT:    v_add_f32_e64 v7, s21, 1.03696; SI-NEXT:    v_add_f32_e64 v11, s23, 1.03697; SI-NEXT:    v_add_f32_e64 v15, s25, 1.03698; SI-NEXT:    v_cvt_f32_f16_e32 v20, v173699; SI-NEXT:    v_cvt_f32_f16_e32 v16, v133700; SI-NEXT:    v_cvt_f32_f16_e32 v12, v93701; SI-NEXT:    v_cvt_f32_f16_e32 v8, v53702; SI-NEXT:    v_cvt_f32_f16_e32 v4, v13703; SI-NEXT:    v_lshrrev_b32_e32 v17, 16, v173704; SI-NEXT:    v_lshrrev_b32_e32 v13, 16, v133705; SI-NEXT:    v_lshrrev_b32_e32 v9, 16, v93706; SI-NEXT:    v_lshrrev_b32_e32 v5, 16, v53707; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v13708; SI-NEXT:    v_cvt_f32_f16_e32 v18, v153709; SI-NEXT:    v_cvt_f32_f16_e32 v14, v113710; SI-NEXT:    v_cvt_f32_f16_e32 v10, v73711; SI-NEXT:    v_cvt_f32_f16_e32 v6, v33712; SI-NEXT:    v_cvt_f32_f16_e32 v2, v03713; SI-NEXT:    v_cvt_f32_f16_e32 v21, v173714; SI-NEXT:    v_lshrrev_b32_e32 v15, 16, v153715; SI-NEXT:    v_cvt_f32_f16_e32 v17, v133716; SI-NEXT:    v_lshrrev_b32_e32 v11, 16, v113717; SI-NEXT:    v_cvt_f32_f16_e32 v13, v93718; SI-NEXT:    v_lshrrev_b32_e32 v7, 16, v73719; SI-NEXT:    v_cvt_f32_f16_e32 v9, v53720; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v33721; SI-NEXT:    v_cvt_f32_f16_e32 v5, v13722; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v03723; SI-NEXT:    v_add_f32_e64 v1, s16, 1.03724; SI-NEXT:    v_cvt_f32_f16_e32 v19, v153725; SI-NEXT:    v_cvt_f32_f16_e32 v15, v113726; SI-NEXT:    v_cvt_f32_f16_e32 v11, v73727; SI-NEXT:    v_cvt_f32_f16_e32 v7, v33728; SI-NEXT:    v_cvt_f32_f16_e32 v3, v03729; SI-NEXT:    v_cvt_f32_f16_e32 v0, v13730; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v13731; SI-NEXT:    v_cvt_f32_f16_e32 v1, v13732; SI-NEXT:  .LBB17_3: ; %end3733; SI-NEXT:    s_setpc_b64 s[30:31]3734; SI-NEXT:  .LBB17_4:3735; SI-NEXT:    ; implicit-def: $vgpr03736; SI-NEXT:    ; implicit-def: $vgpr13737; SI-NEXT:    ; implicit-def: $vgpr23738; SI-NEXT:    ; implicit-def: $vgpr33739; SI-NEXT:    ; implicit-def: $vgpr43740; SI-NEXT:    ; implicit-def: $vgpr53741; SI-NEXT:    ; implicit-def: $vgpr63742; SI-NEXT:    ; implicit-def: $vgpr73743; SI-NEXT:    ; implicit-def: $vgpr83744; SI-NEXT:    ; implicit-def: $vgpr93745; SI-NEXT:    ; implicit-def: $vgpr103746; SI-NEXT:    ; implicit-def: $vgpr113747; SI-NEXT:    ; implicit-def: $vgpr123748; SI-NEXT:    ; implicit-def: $vgpr133749; SI-NEXT:    ; implicit-def: $vgpr143750; SI-NEXT:    ; implicit-def: $vgpr153751; SI-NEXT:    ; implicit-def: $vgpr163752; SI-NEXT:    ; implicit-def: $vgpr173753; SI-NEXT:    ; implicit-def: $vgpr183754; SI-NEXT:    ; implicit-def: $vgpr193755; SI-NEXT:    ; implicit-def: $vgpr203756; SI-NEXT:    ; implicit-def: $vgpr213757; SI-NEXT:    s_branch .LBB17_23758;3759; VI-LABEL: bitcast_v11f32_to_v22f16_scalar:3760; VI:       ; %bb.0:3761; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3762; VI-NEXT:    s_cmp_lg_u32 s27, 03763; VI-NEXT:    s_cbranch_scc0 .LBB17_33764; VI-NEXT:  ; %bb.1: ; %cmp.false3765; VI-NEXT:    s_cbranch_execnz .LBB17_43766; VI-NEXT:  .LBB17_2: ; %cmp.true3767; VI-NEXT:    v_add_f32_e64 v10, s26, 1.03768; VI-NEXT:    v_add_f32_e64 v9, s25, 1.03769; VI-NEXT:    v_add_f32_e64 v8, s24, 1.03770; VI-NEXT:    v_add_f32_e64 v7, s23, 1.03771; VI-NEXT:    v_add_f32_e64 v6, s22, 1.03772; VI-NEXT:    v_add_f32_e64 v5, s21, 1.03773; VI-NEXT:    v_add_f32_e64 v4, s20, 1.03774; VI-NEXT:    v_add_f32_e64 v3, s19, 1.03775; VI-NEXT:    v_add_f32_e64 v2, s18, 1.03776; VI-NEXT:    v_add_f32_e64 v1, s17, 1.03777; VI-NEXT:    v_add_f32_e64 v0, s16, 1.03778; VI-NEXT:    s_setpc_b64 s[30:31]3779; VI-NEXT:  .LBB17_3:3780; VI-NEXT:    s_branch .LBB17_23781; VI-NEXT:  .LBB17_4:3782; VI-NEXT:    v_mov_b32_e32 v0, s163783; VI-NEXT:    v_mov_b32_e32 v1, s173784; VI-NEXT:    v_mov_b32_e32 v2, s183785; VI-NEXT:    v_mov_b32_e32 v3, s193786; VI-NEXT:    v_mov_b32_e32 v4, s203787; VI-NEXT:    v_mov_b32_e32 v5, s213788; VI-NEXT:    v_mov_b32_e32 v6, s223789; VI-NEXT:    v_mov_b32_e32 v7, s233790; VI-NEXT:    v_mov_b32_e32 v8, s243791; VI-NEXT:    v_mov_b32_e32 v9, s253792; VI-NEXT:    v_mov_b32_e32 v10, s263793; VI-NEXT:    v_mov_b32_e32 v11, s273794; VI-NEXT:    v_mov_b32_e32 v12, s283795; VI-NEXT:    v_mov_b32_e32 v13, s293796; VI-NEXT:    v_mov_b32_e32 v14, s303797; VI-NEXT:    v_mov_b32_e32 v15, s313798; VI-NEXT:    s_setpc_b64 s[30:31]3799;3800; GFX9-LABEL: bitcast_v11f32_to_v22f16_scalar:3801; GFX9:       ; %bb.0:3802; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3803; GFX9-NEXT:    s_cmp_lg_u32 s27, 03804; GFX9-NEXT:    s_cbranch_scc0 .LBB17_33805; GFX9-NEXT:  ; %bb.1: ; %cmp.false3806; GFX9-NEXT:    s_cbranch_execnz .LBB17_43807; GFX9-NEXT:  .LBB17_2: ; %cmp.true3808; GFX9-NEXT:    v_add_f32_e64 v10, s26, 1.03809; GFX9-NEXT:    v_add_f32_e64 v9, s25, 1.03810; GFX9-NEXT:    v_add_f32_e64 v8, s24, 1.03811; GFX9-NEXT:    v_add_f32_e64 v7, s23, 1.03812; GFX9-NEXT:    v_add_f32_e64 v6, s22, 1.03813; GFX9-NEXT:    v_add_f32_e64 v5, s21, 1.03814; GFX9-NEXT:    v_add_f32_e64 v4, s20, 1.03815; GFX9-NEXT:    v_add_f32_e64 v3, s19, 1.03816; GFX9-NEXT:    v_add_f32_e64 v2, s18, 1.03817; GFX9-NEXT:    v_add_f32_e64 v1, s17, 1.03818; GFX9-NEXT:    v_add_f32_e64 v0, s16, 1.03819; GFX9-NEXT:    s_setpc_b64 s[30:31]3820; GFX9-NEXT:  .LBB17_3:3821; GFX9-NEXT:    s_branch .LBB17_23822; GFX9-NEXT:  .LBB17_4:3823; GFX9-NEXT:    v_mov_b32_e32 v0, s163824; GFX9-NEXT:    v_mov_b32_e32 v1, s173825; GFX9-NEXT:    v_mov_b32_e32 v2, s183826; GFX9-NEXT:    v_mov_b32_e32 v3, s193827; GFX9-NEXT:    v_mov_b32_e32 v4, s203828; GFX9-NEXT:    v_mov_b32_e32 v5, s213829; GFX9-NEXT:    v_mov_b32_e32 v6, s223830; GFX9-NEXT:    v_mov_b32_e32 v7, s233831; GFX9-NEXT:    v_mov_b32_e32 v8, s243832; GFX9-NEXT:    v_mov_b32_e32 v9, s253833; GFX9-NEXT:    v_mov_b32_e32 v10, s263834; GFX9-NEXT:    v_mov_b32_e32 v11, s273835; GFX9-NEXT:    v_mov_b32_e32 v12, s283836; GFX9-NEXT:    v_mov_b32_e32 v13, s293837; GFX9-NEXT:    v_mov_b32_e32 v14, s303838; GFX9-NEXT:    v_mov_b32_e32 v15, s313839; GFX9-NEXT:    s_setpc_b64 s[30:31]3840;3841; GFX11-LABEL: bitcast_v11f32_to_v22f16_scalar:3842; GFX11:       ; %bb.0:3843; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3844; GFX11-NEXT:    s_mov_b32 s15, s33845; GFX11-NEXT:    s_mov_b32 s14, s23846; GFX11-NEXT:    s_mov_b32 s13, s13847; GFX11-NEXT:    s_mov_b32 s12, s03848; GFX11-NEXT:    s_cmp_lg_u32 s23, 03849; GFX11-NEXT:    s_mov_b32 s0, 03850; GFX11-NEXT:    s_cbranch_scc0 .LBB17_33851; GFX11-NEXT:  ; %bb.1: ; %Flow3852; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s03853; GFX11-NEXT:    s_cbranch_vccnz .LBB17_43854; GFX11-NEXT:  .LBB17_2: ; %cmp.true3855; GFX11-NEXT:    v_add_f32_e64 v10, s22, 1.03856; GFX11-NEXT:    v_add_f32_e64 v9, s21, 1.03857; GFX11-NEXT:    v_add_f32_e64 v8, s20, 1.03858; GFX11-NEXT:    v_add_f32_e64 v7, s19, 1.03859; GFX11-NEXT:    v_add_f32_e64 v6, s18, 1.03860; GFX11-NEXT:    v_add_f32_e64 v5, s17, 1.03861; GFX11-NEXT:    v_add_f32_e64 v4, s16, 1.03862; GFX11-NEXT:    v_add_f32_e64 v3, s15, 1.03863; GFX11-NEXT:    v_add_f32_e64 v2, s14, 1.03864; GFX11-NEXT:    v_add_f32_e64 v1, s13, 1.03865; GFX11-NEXT:    v_add_f32_e64 v0, s12, 1.03866; GFX11-NEXT:    s_setpc_b64 s[30:31]3867; GFX11-NEXT:  .LBB17_3:3868; GFX11-NEXT:    s_branch .LBB17_23869; GFX11-NEXT:  .LBB17_4:3870; GFX11-NEXT:    v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s133871; GFX11-NEXT:    v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s153872; GFX11-NEXT:    v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s173873; GFX11-NEXT:    v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s193874; GFX11-NEXT:    v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s213875; GFX11-NEXT:    v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s233876; GFX11-NEXT:    v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s253877; GFX11-NEXT:    v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s273878; GFX11-NEXT:    s_setpc_b64 s[30:31]3879  %cmp = icmp eq i32 %b, 03880  br i1 %cmp, label %cmp.true, label %cmp.false3881 3882cmp.true:3883  %a1 = fadd <11 x float> %a, splat (float 1.000000e+00)3884  %a2 = bitcast <11 x float> %a1 to <22 x half>3885  br label %end3886 3887cmp.false:3888  %a3 = bitcast <11 x float> %a to <22 x half>3889  br label %end3890 3891end:3892  %phi = phi <22 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]3893  ret <22 x half> %phi3894}3895 3896define <11 x float> @bitcast_v22f16_to_v11f32(<22 x half> %a, i32 %b) {3897; SI-LABEL: bitcast_v22f16_to_v11f32:3898; SI:       ; %bb.0:3899; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3900; SI-NEXT:    v_cvt_f16_f32_e32 v38, v13901; SI-NEXT:    v_cvt_f16_f32_e32 v37, v03902; SI-NEXT:    v_cvt_f16_f32_e32 v36, v33903; SI-NEXT:    v_cvt_f16_f32_e32 v35, v23904; SI-NEXT:    v_cvt_f16_f32_e32 v34, v53905; SI-NEXT:    v_cvt_f16_f32_e32 v33, v43906; SI-NEXT:    v_cvt_f16_f32_e32 v32, v73907; SI-NEXT:    v_cvt_f16_f32_e32 v31, v63908; SI-NEXT:    v_cvt_f16_f32_e32 v30, v93909; SI-NEXT:    v_cvt_f16_f32_e32 v29, v83910; SI-NEXT:    v_cvt_f16_f32_e32 v28, v113911; SI-NEXT:    v_cvt_f16_f32_e32 v27, v103912; SI-NEXT:    v_cvt_f16_f32_e32 v26, v133913; SI-NEXT:    v_cvt_f16_f32_e32 v25, v123914; SI-NEXT:    v_cvt_f16_f32_e32 v24, v153915; SI-NEXT:    v_cvt_f16_f32_e32 v23, v143916; SI-NEXT:    v_cvt_f16_f32_e32 v17, v173917; SI-NEXT:    v_cvt_f16_f32_e32 v15, v163918; SI-NEXT:    v_cvt_f16_f32_e32 v14, v193919; SI-NEXT:    v_cvt_f16_f32_e32 v13, v183920; SI-NEXT:    v_cvt_f16_f32_e32 v12, v213921; SI-NEXT:    v_cvt_f16_f32_e32 v11, v203922; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v223923; SI-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr103924; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc3925; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]3926; SI-NEXT:    s_cbranch_execnz .LBB18_33927; SI-NEXT:  ; %bb.1: ; %Flow3928; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]3929; SI-NEXT:    s_cbranch_execnz .LBB18_43930; SI-NEXT:  .LBB18_2: ; %end3931; SI-NEXT:    s_or_b64 exec, exec, s[4:5]3932; SI-NEXT:    s_setpc_b64 s[30:31]3933; SI-NEXT:  .LBB18_3: ; %cmp.false3934; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v383935; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v363936; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v343937; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v323938; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v303939; SI-NEXT:    v_lshlrev_b32_e32 v5, 16, v283940; SI-NEXT:    v_lshlrev_b32_e32 v6, 16, v263941; SI-NEXT:    v_lshlrev_b32_e32 v7, 16, v243942; SI-NEXT:    v_lshlrev_b32_e32 v8, 16, v173943; SI-NEXT:    v_lshlrev_b32_e32 v9, 16, v143944; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v123945; SI-NEXT:    v_or_b32_e32 v0, v37, v03946; SI-NEXT:    v_or_b32_e32 v1, v35, v13947; SI-NEXT:    v_or_b32_e32 v2, v33, v23948; SI-NEXT:    v_or_b32_e32 v3, v31, v33949; SI-NEXT:    v_or_b32_e32 v4, v29, v43950; SI-NEXT:    v_or_b32_e32 v5, v27, v53951; SI-NEXT:    v_or_b32_e32 v6, v25, v63952; SI-NEXT:    v_or_b32_e32 v7, v23, v73953; SI-NEXT:    v_or_b32_e32 v8, v15, v83954; SI-NEXT:    v_or_b32_e32 v9, v13, v93955; SI-NEXT:    v_or_b32_e32 v10, v11, v103956; SI-NEXT:    ; implicit-def: $vgpr383957; SI-NEXT:    ; implicit-def: $vgpr373958; SI-NEXT:    ; implicit-def: $vgpr363959; SI-NEXT:    ; implicit-def: $vgpr353960; SI-NEXT:    ; implicit-def: $vgpr343961; SI-NEXT:    ; implicit-def: $vgpr333962; SI-NEXT:    ; implicit-def: $vgpr323963; SI-NEXT:    ; implicit-def: $vgpr313964; SI-NEXT:    ; implicit-def: $vgpr303965; SI-NEXT:    ; implicit-def: $vgpr293966; SI-NEXT:    ; implicit-def: $vgpr283967; SI-NEXT:    ; implicit-def: $vgpr273968; SI-NEXT:    ; implicit-def: $vgpr263969; SI-NEXT:    ; implicit-def: $vgpr253970; SI-NEXT:    ; implicit-def: $vgpr243971; SI-NEXT:    ; implicit-def: $vgpr233972; SI-NEXT:    ; implicit-def: $vgpr173973; SI-NEXT:    ; implicit-def: $vgpr153974; SI-NEXT:    ; implicit-def: $vgpr143975; SI-NEXT:    ; implicit-def: $vgpr133976; SI-NEXT:    ; implicit-def: $vgpr123977; SI-NEXT:    ; implicit-def: $vgpr113978; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]3979; SI-NEXT:    s_cbranch_execz .LBB18_23980; SI-NEXT:  .LBB18_4: ; %cmp.true3981; SI-NEXT:    v_cvt_f32_f16_e32 v0, v383982; SI-NEXT:    v_cvt_f32_f16_e32 v1, v373983; SI-NEXT:    v_cvt_f32_f16_e32 v2, v363984; SI-NEXT:    v_cvt_f32_f16_e32 v3, v353985; SI-NEXT:    v_add_f32_e32 v0, 0x38000000, v03986; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v13987; SI-NEXT:    v_cvt_f16_f32_e32 v0, v03988; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v23989; SI-NEXT:    v_cvt_f16_f32_e32 v1, v13990; SI-NEXT:    v_cvt_f16_f32_e32 v2, v23991; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v03992; SI-NEXT:    v_cvt_f32_f16_e32 v4, v333993; SI-NEXT:    v_or_b32_e32 v0, v1, v03994; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v23995; SI-NEXT:    v_cvt_f32_f16_e32 v2, v343996; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v33997; SI-NEXT:    v_cvt_f16_f32_e32 v3, v33998; SI-NEXT:    v_add_f32_e32 v4, 0x38000000, v43999; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v24000; SI-NEXT:    v_cvt_f16_f32_e32 v2, v24001; SI-NEXT:    v_cvt_f16_f32_e32 v4, v44002; SI-NEXT:    v_or_b32_e32 v1, v3, v14003; SI-NEXT:    v_cvt_f32_f16_e32 v3, v324004; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v24005; SI-NEXT:    v_or_b32_e32 v2, v4, v24006; SI-NEXT:    v_cvt_f32_f16_e32 v4, v314007; SI-NEXT:    v_cvt_f32_f16_e32 v5, v304008; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v34009; SI-NEXT:    v_cvt_f16_f32_e32 v3, v34010; SI-NEXT:    v_add_f32_e32 v4, 0x38000000, v44011; SI-NEXT:    v_add_f32_e32 v5, 0x38000000, v54012; SI-NEXT:    v_cvt_f16_f32_e32 v4, v44013; SI-NEXT:    v_cvt_f16_f32_e32 v5, v54014; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v34015; SI-NEXT:    v_cvt_f32_f16_e32 v6, v294016; SI-NEXT:    v_or_b32_e32 v3, v4, v34017; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v54018; SI-NEXT:    v_cvt_f32_f16_e32 v5, v284019; SI-NEXT:    v_cvt_f32_f16_e32 v7, v274020; SI-NEXT:    v_add_f32_e32 v6, 0x38000000, v64021; SI-NEXT:    v_cvt_f16_f32_e32 v6, v64022; SI-NEXT:    v_add_f32_e32 v5, 0x38000000, v54023; SI-NEXT:    v_cvt_f16_f32_e32 v5, v54024; SI-NEXT:    v_add_f32_e32 v7, 0x38000000, v74025; SI-NEXT:    v_cvt_f16_f32_e32 v7, v74026; SI-NEXT:    v_or_b32_e32 v4, v6, v44027; SI-NEXT:    v_cvt_f32_f16_e32 v6, v264028; SI-NEXT:    v_lshlrev_b32_e32 v5, 16, v54029; SI-NEXT:    v_or_b32_e32 v5, v7, v54030; SI-NEXT:    v_cvt_f32_f16_e32 v7, v254031; SI-NEXT:    v_cvt_f32_f16_e32 v8, v244032; SI-NEXT:    v_add_f32_e32 v6, 0x38000000, v64033; SI-NEXT:    v_cvt_f16_f32_e32 v6, v64034; SI-NEXT:    v_add_f32_e32 v7, 0x38000000, v74035; SI-NEXT:    v_add_f32_e32 v8, 0x38000000, v84036; SI-NEXT:    v_cvt_f16_f32_e32 v7, v74037; SI-NEXT:    v_cvt_f16_f32_e32 v8, v84038; SI-NEXT:    v_lshlrev_b32_e32 v6, 16, v64039; SI-NEXT:    v_cvt_f32_f16_e32 v9, v234040; SI-NEXT:    v_or_b32_e32 v6, v7, v64041; SI-NEXT:    v_lshlrev_b32_e32 v7, 16, v84042; SI-NEXT:    v_cvt_f32_f16_e32 v8, v174043; SI-NEXT:    v_cvt_f32_f16_e32 v10, v154044; SI-NEXT:    v_add_f32_e32 v9, 0x38000000, v94045; SI-NEXT:    v_cvt_f16_f32_e32 v9, v94046; SI-NEXT:    v_add_f32_e32 v8, 0x38000000, v84047; SI-NEXT:    v_cvt_f16_f32_e32 v8, v84048; SI-NEXT:    v_add_f32_e32 v10, 0x38000000, v104049; SI-NEXT:    v_cvt_f16_f32_e32 v10, v104050; SI-NEXT:    v_or_b32_e32 v7, v9, v74051; SI-NEXT:    v_cvt_f32_f16_e32 v9, v144052; SI-NEXT:    v_lshlrev_b32_e32 v8, 16, v84053; SI-NEXT:    v_or_b32_e32 v8, v10, v84054; SI-NEXT:    v_cvt_f32_f16_e32 v10, v134055; SI-NEXT:    v_cvt_f32_f16_e32 v12, v124056; SI-NEXT:    v_cvt_f32_f16_e32 v11, v114057; SI-NEXT:    v_add_f32_e32 v9, 0x38000000, v94058; SI-NEXT:    v_cvt_f16_f32_e32 v9, v94059; SI-NEXT:    v_add_f32_e32 v10, 0x38000000, v104060; SI-NEXT:    v_add_f32_e32 v12, 0x38000000, v124061; SI-NEXT:    v_cvt_f16_f32_e32 v10, v104062; SI-NEXT:    v_cvt_f16_f32_e32 v12, v124063; SI-NEXT:    v_add_f32_e32 v11, 0x38000000, v114064; SI-NEXT:    v_cvt_f16_f32_e32 v11, v114065; SI-NEXT:    v_lshlrev_b32_e32 v9, 16, v94066; SI-NEXT:    v_or_b32_e32 v9, v10, v94067; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v124068; SI-NEXT:    v_or_b32_e32 v10, v11, v104069; SI-NEXT:    s_or_b64 exec, exec, s[4:5]4070; SI-NEXT:    s_setpc_b64 s[30:31]4071;4072; VI-LABEL: bitcast_v22f16_to_v11f32:4073; VI:       ; %bb.0:4074; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4075; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v114076; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc4077; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]4078; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]4079; VI-NEXT:    s_cbranch_execz .LBB18_24080; VI-NEXT:  ; %bb.1: ; %cmp.true4081; VI-NEXT:    v_mov_b32_e32 v11, 0x2004082; VI-NEXT:    v_add_f16_sdwa v12, v10, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4083; VI-NEXT:    v_add_f16_e32 v10, 0x200, v104084; VI-NEXT:    v_or_b32_e32 v10, v10, v124085; VI-NEXT:    v_add_f16_sdwa v12, v9, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4086; VI-NEXT:    v_add_f16_e32 v9, 0x200, v94087; VI-NEXT:    v_or_b32_e32 v9, v9, v124088; VI-NEXT:    v_add_f16_sdwa v12, v8, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4089; VI-NEXT:    v_add_f16_e32 v8, 0x200, v84090; VI-NEXT:    v_or_b32_e32 v8, v8, v124091; VI-NEXT:    v_add_f16_sdwa v12, v7, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4092; VI-NEXT:    v_add_f16_e32 v7, 0x200, v74093; VI-NEXT:    v_or_b32_e32 v7, v7, v124094; VI-NEXT:    v_add_f16_sdwa v12, v6, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4095; VI-NEXT:    v_add_f16_e32 v6, 0x200, v64096; VI-NEXT:    v_or_b32_e32 v6, v6, v124097; VI-NEXT:    v_add_f16_sdwa v12, v5, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4098; VI-NEXT:    v_add_f16_e32 v5, 0x200, v54099; VI-NEXT:    v_or_b32_e32 v5, v5, v124100; VI-NEXT:    v_add_f16_sdwa v12, v4, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4101; VI-NEXT:    v_add_f16_e32 v4, 0x200, v44102; VI-NEXT:    v_or_b32_e32 v4, v4, v124103; VI-NEXT:    v_add_f16_sdwa v12, v3, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4104; VI-NEXT:    v_add_f16_e32 v3, 0x200, v34105; VI-NEXT:    v_or_b32_e32 v3, v3, v124106; VI-NEXT:    v_add_f16_sdwa v12, v2, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4107; VI-NEXT:    v_add_f16_e32 v2, 0x200, v24108; VI-NEXT:    v_or_b32_e32 v2, v2, v124109; VI-NEXT:    v_add_f16_sdwa v12, v1, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4110; VI-NEXT:    v_add_f16_e32 v1, 0x200, v14111; VI-NEXT:    v_add_f16_sdwa v11, v0, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4112; VI-NEXT:    v_add_f16_e32 v0, 0x200, v04113; VI-NEXT:    v_or_b32_e32 v1, v1, v124114; VI-NEXT:    v_or_b32_e32 v0, v0, v114115; VI-NEXT:  .LBB18_2: ; %end4116; VI-NEXT:    s_or_b64 exec, exec, s[4:5]4117; VI-NEXT:    s_setpc_b64 s[30:31]4118;4119; GFX9-LABEL: bitcast_v22f16_to_v11f32:4120; GFX9:       ; %bb.0:4121; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4122; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v114123; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc4124; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]4125; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]4126; GFX9-NEXT:    s_cbranch_execz .LBB18_24127; GFX9-NEXT:  ; %bb.1: ; %cmp.true4128; GFX9-NEXT:    s_movk_i32 s6, 0x2004129; GFX9-NEXT:    v_pk_add_f16 v10, v10, s6 op_sel_hi:[1,0]4130; GFX9-NEXT:    v_pk_add_f16 v9, v9, s6 op_sel_hi:[1,0]4131; GFX9-NEXT:    v_pk_add_f16 v8, v8, s6 op_sel_hi:[1,0]4132; GFX9-NEXT:    v_pk_add_f16 v7, v7, s6 op_sel_hi:[1,0]4133; GFX9-NEXT:    v_pk_add_f16 v6, v6, s6 op_sel_hi:[1,0]4134; GFX9-NEXT:    v_pk_add_f16 v5, v5, s6 op_sel_hi:[1,0]4135; GFX9-NEXT:    v_pk_add_f16 v4, v4, s6 op_sel_hi:[1,0]4136; GFX9-NEXT:    v_pk_add_f16 v3, v3, s6 op_sel_hi:[1,0]4137; GFX9-NEXT:    v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]4138; GFX9-NEXT:    v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]4139; GFX9-NEXT:    v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]4140; GFX9-NEXT:  .LBB18_2: ; %end4141; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]4142; GFX9-NEXT:    s_setpc_b64 s[30:31]4143;4144; GFX11-LABEL: bitcast_v22f16_to_v11f32:4145; GFX11:       ; %bb.0:4146; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4147; GFX11-NEXT:    s_mov_b32 s0, exec_lo4148; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v114149; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s04150; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)4151; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s04152; GFX11-NEXT:    s_cbranch_execz .LBB18_24153; GFX11-NEXT:  ; %bb.1: ; %cmp.true4154; GFX11-NEXT:    v_pk_add_f16 v10, 0x200, v10 op_sel_hi:[0,1]4155; GFX11-NEXT:    v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1]4156; GFX11-NEXT:    v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1]4157; GFX11-NEXT:    v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]4158; GFX11-NEXT:    v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]4159; GFX11-NEXT:    v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]4160; GFX11-NEXT:    v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]4161; GFX11-NEXT:    v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]4162; GFX11-NEXT:    v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]4163; GFX11-NEXT:    v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]4164; GFX11-NEXT:    v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]4165; GFX11-NEXT:  .LBB18_2: ; %end4166; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s04167; GFX11-NEXT:    s_setpc_b64 s[30:31]4168  %cmp = icmp eq i32 %b, 04169  br i1 %cmp, label %cmp.true, label %cmp.false4170 4171cmp.true:4172  %a1 = fadd <22 x half> %a, splat (half 0xH0200)4173  %a2 = bitcast <22 x half> %a1 to <11 x float>4174  br label %end4175 4176cmp.false:4177  %a3 = bitcast <22 x half> %a to <11 x float>4178  br label %end4179 4180end:4181  %phi = phi <11 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]4182  ret <11 x float> %phi4183}4184 4185define inreg <11 x float> @bitcast_v22f16_to_v11f32_scalar(<22 x half> inreg %a, i32 inreg %b) {4186; SI-LABEL: bitcast_v22f16_to_v11f32_scalar:4187; SI:       ; %bb.0:4188; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4189; SI-NEXT:    v_cvt_f16_f32_e32 v32, s174190; SI-NEXT:    v_cvt_f16_f32_e32 v31, s164191; SI-NEXT:    v_cvt_f16_f32_e32 v30, s194192; SI-NEXT:    v_cvt_f16_f32_e32 v29, s184193; SI-NEXT:    v_cvt_f16_f32_e32 v28, s214194; SI-NEXT:    v_cvt_f16_f32_e32 v27, s204195; SI-NEXT:    v_cvt_f16_f32_e32 v26, s234196; SI-NEXT:    v_cvt_f16_f32_e32 v25, s224197; SI-NEXT:    v_cvt_f16_f32_e32 v24, s254198; SI-NEXT:    v_cvt_f16_f32_e32 v23, s244199; SI-NEXT:    v_cvt_f16_f32_e32 v22, s274200; SI-NEXT:    v_cvt_f16_f32_e32 v20, s264201; SI-NEXT:    v_cvt_f16_f32_e32 v18, v14202; SI-NEXT:    v_cvt_f16_f32_e32 v17, v04203; SI-NEXT:    v_cvt_f16_f32_e32 v16, v34204; SI-NEXT:    v_cvt_f16_f32_e32 v15, v24205; SI-NEXT:    v_cvt_f16_f32_e32 v14, v54206; SI-NEXT:    v_cvt_f16_f32_e32 v13, v44207; SI-NEXT:    v_cvt_f16_f32_e32 v12, v74208; SI-NEXT:    v_cvt_f16_f32_e32 v11, v64209; SI-NEXT:    v_cvt_f16_f32_e32 v21, s294210; SI-NEXT:    v_cvt_f16_f32_e32 v19, s284211; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v84212; SI-NEXT:    s_and_b64 s[4:5], vcc, exec4213; SI-NEXT:    s_cbranch_scc0 .LBB19_44214; SI-NEXT:  ; %bb.1: ; %cmp.false4215; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v324216; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v304217; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v284218; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v264219; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v244220; SI-NEXT:    v_lshlrev_b32_e32 v5, 16, v224221; SI-NEXT:    v_lshlrev_b32_e32 v6, 16, v214222; SI-NEXT:    v_lshlrev_b32_e32 v7, 16, v184223; SI-NEXT:    v_lshlrev_b32_e32 v8, 16, v164224; SI-NEXT:    v_lshlrev_b32_e32 v9, 16, v144225; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v124226; SI-NEXT:    v_or_b32_e32 v0, v31, v04227; SI-NEXT:    v_or_b32_e32 v1, v29, v14228; SI-NEXT:    v_or_b32_e32 v2, v27, v24229; SI-NEXT:    v_or_b32_e32 v3, v25, v34230; SI-NEXT:    v_or_b32_e32 v4, v23, v44231; SI-NEXT:    v_or_b32_e32 v5, v20, v54232; SI-NEXT:    v_or_b32_e32 v6, v19, v64233; SI-NEXT:    v_or_b32_e32 v7, v17, v74234; SI-NEXT:    v_or_b32_e32 v8, v15, v84235; SI-NEXT:    v_or_b32_e32 v9, v13, v94236; SI-NEXT:    v_or_b32_e32 v10, v11, v104237; SI-NEXT:    s_cbranch_execnz .LBB19_34238; SI-NEXT:  .LBB19_2: ; %cmp.true4239; SI-NEXT:    v_cvt_f32_f16_e32 v0, v324240; SI-NEXT:    v_cvt_f32_f16_e32 v1, v314241; SI-NEXT:    v_cvt_f32_f16_e32 v2, v304242; SI-NEXT:    v_cvt_f32_f16_e32 v3, v294243; SI-NEXT:    v_add_f32_e32 v0, 0x38000000, v04244; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v14245; SI-NEXT:    v_cvt_f16_f32_e32 v0, v04246; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v24247; SI-NEXT:    v_cvt_f16_f32_e32 v1, v14248; SI-NEXT:    v_cvt_f16_f32_e32 v2, v24249; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v04250; SI-NEXT:    v_cvt_f32_f16_e32 v4, v274251; SI-NEXT:    v_or_b32_e32 v0, v1, v04252; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v24253; SI-NEXT:    v_cvt_f32_f16_e32 v2, v284254; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v34255; SI-NEXT:    v_cvt_f16_f32_e32 v3, v34256; SI-NEXT:    v_add_f32_e32 v4, 0x38000000, v44257; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v24258; SI-NEXT:    v_cvt_f16_f32_e32 v2, v24259; SI-NEXT:    v_cvt_f16_f32_e32 v4, v44260; SI-NEXT:    v_or_b32_e32 v1, v3, v14261; SI-NEXT:    v_cvt_f32_f16_e32 v3, v264262; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v24263; SI-NEXT:    v_or_b32_e32 v2, v4, v24264; SI-NEXT:    v_cvt_f32_f16_e32 v4, v254265; SI-NEXT:    v_cvt_f32_f16_e32 v5, v244266; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v34267; SI-NEXT:    v_cvt_f16_f32_e32 v3, v34268; SI-NEXT:    v_add_f32_e32 v4, 0x38000000, v44269; SI-NEXT:    v_add_f32_e32 v5, 0x38000000, v54270; SI-NEXT:    v_cvt_f16_f32_e32 v4, v44271; SI-NEXT:    v_cvt_f16_f32_e32 v5, v54272; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v34273; SI-NEXT:    v_cvt_f32_f16_e32 v6, v234274; SI-NEXT:    v_or_b32_e32 v3, v4, v34275; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v54276; SI-NEXT:    v_cvt_f32_f16_e32 v5, v224277; SI-NEXT:    v_cvt_f32_f16_e32 v7, v204278; SI-NEXT:    v_add_f32_e32 v6, 0x38000000, v64279; SI-NEXT:    v_cvt_f16_f32_e32 v6, v64280; SI-NEXT:    v_add_f32_e32 v5, 0x38000000, v54281; SI-NEXT:    v_cvt_f16_f32_e32 v5, v54282; SI-NEXT:    v_add_f32_e32 v7, 0x38000000, v74283; SI-NEXT:    v_cvt_f16_f32_e32 v7, v74284; SI-NEXT:    v_or_b32_e32 v4, v6, v44285; SI-NEXT:    v_cvt_f32_f16_e32 v6, v214286; SI-NEXT:    v_lshlrev_b32_e32 v5, 16, v54287; SI-NEXT:    v_or_b32_e32 v5, v7, v54288; SI-NEXT:    v_cvt_f32_f16_e32 v7, v194289; SI-NEXT:    v_cvt_f32_f16_e32 v8, v184290; SI-NEXT:    v_add_f32_e32 v6, 0x38000000, v64291; SI-NEXT:    v_cvt_f16_f32_e32 v6, v64292; SI-NEXT:    v_add_f32_e32 v7, 0x38000000, v74293; SI-NEXT:    v_add_f32_e32 v8, 0x38000000, v84294; SI-NEXT:    v_cvt_f16_f32_e32 v7, v74295; SI-NEXT:    v_cvt_f16_f32_e32 v8, v84296; SI-NEXT:    v_lshlrev_b32_e32 v6, 16, v64297; SI-NEXT:    v_cvt_f32_f16_e32 v9, v174298; SI-NEXT:    v_or_b32_e32 v6, v7, v64299; SI-NEXT:    v_lshlrev_b32_e32 v7, 16, v84300; SI-NEXT:    v_cvt_f32_f16_e32 v8, v164301; SI-NEXT:    v_cvt_f32_f16_e32 v10, v154302; SI-NEXT:    v_add_f32_e32 v9, 0x38000000, v94303; SI-NEXT:    v_cvt_f16_f32_e32 v9, v94304; SI-NEXT:    v_add_f32_e32 v8, 0x38000000, v84305; SI-NEXT:    v_cvt_f16_f32_e32 v8, v84306; SI-NEXT:    v_add_f32_e32 v10, 0x38000000, v104307; SI-NEXT:    v_cvt_f16_f32_e32 v10, v104308; SI-NEXT:    v_or_b32_e32 v7, v9, v74309; SI-NEXT:    v_cvt_f32_f16_e32 v9, v144310; SI-NEXT:    v_lshlrev_b32_e32 v8, 16, v84311; SI-NEXT:    v_or_b32_e32 v8, v10, v84312; SI-NEXT:    v_cvt_f32_f16_e32 v10, v134313; SI-NEXT:    v_cvt_f32_f16_e32 v12, v124314; SI-NEXT:    v_cvt_f32_f16_e32 v11, v114315; SI-NEXT:    v_add_f32_e32 v9, 0x38000000, v94316; SI-NEXT:    v_cvt_f16_f32_e32 v9, v94317; SI-NEXT:    v_add_f32_e32 v10, 0x38000000, v104318; SI-NEXT:    v_add_f32_e32 v12, 0x38000000, v124319; SI-NEXT:    v_cvt_f16_f32_e32 v10, v104320; SI-NEXT:    v_cvt_f16_f32_e32 v12, v124321; SI-NEXT:    v_add_f32_e32 v11, 0x38000000, v114322; SI-NEXT:    v_cvt_f16_f32_e32 v11, v114323; SI-NEXT:    v_lshlrev_b32_e32 v9, 16, v94324; SI-NEXT:    v_or_b32_e32 v9, v10, v94325; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v124326; SI-NEXT:    v_or_b32_e32 v10, v11, v104327; SI-NEXT:  .LBB19_3: ; %end4328; SI-NEXT:    s_setpc_b64 s[30:31]4329; SI-NEXT:  .LBB19_4:4330; SI-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr104331; SI-NEXT:    s_branch .LBB19_24332;4333; VI-LABEL: bitcast_v22f16_to_v11f32_scalar:4334; VI:       ; %bb.0:4335; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4336; VI-NEXT:    s_cmp_lg_u32 s27, 04337; VI-NEXT:    s_cbranch_scc0 .LBB19_34338; VI-NEXT:  ; %bb.1: ; %cmp.false4339; VI-NEXT:    s_cbranch_execnz .LBB19_44340; VI-NEXT:  .LBB19_2: ; %cmp.true4341; VI-NEXT:    s_lshr_b32 s4, s26, 164342; VI-NEXT:    v_mov_b32_e32 v0, 0x2004343; VI-NEXT:    v_mov_b32_e32 v1, s44344; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD4345; VI-NEXT:    v_add_f16_e32 v2, s26, v04346; VI-NEXT:    s_lshr_b32 s4, s25, 164347; VI-NEXT:    v_or_b32_e32 v10, v2, v14348; VI-NEXT:    v_mov_b32_e32 v1, s44349; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD4350; VI-NEXT:    v_add_f16_e32 v2, s25, v04351; VI-NEXT:    s_lshr_b32 s4, s24, 164352; VI-NEXT:    v_or_b32_e32 v9, v2, v14353; VI-NEXT:    v_mov_b32_e32 v1, s44354; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD4355; VI-NEXT:    v_add_f16_e32 v2, s24, v04356; VI-NEXT:    s_lshr_b32 s4, s23, 164357; VI-NEXT:    v_or_b32_e32 v8, v2, v14358; VI-NEXT:    v_mov_b32_e32 v1, s44359; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD4360; VI-NEXT:    v_add_f16_e32 v2, s23, v04361; VI-NEXT:    s_lshr_b32 s4, s22, 164362; VI-NEXT:    v_or_b32_e32 v7, v2, v14363; VI-NEXT:    v_mov_b32_e32 v1, s44364; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD4365; VI-NEXT:    v_add_f16_e32 v2, s22, v04366; VI-NEXT:    s_lshr_b32 s4, s21, 164367; VI-NEXT:    v_or_b32_e32 v6, v2, v14368; VI-NEXT:    v_mov_b32_e32 v1, s44369; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD4370; VI-NEXT:    v_add_f16_e32 v2, s21, v04371; VI-NEXT:    s_lshr_b32 s4, s20, 164372; VI-NEXT:    v_or_b32_e32 v5, v2, v14373; VI-NEXT:    v_mov_b32_e32 v1, s44374; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD4375; VI-NEXT:    v_add_f16_e32 v2, s20, v04376; VI-NEXT:    s_lshr_b32 s4, s19, 164377; VI-NEXT:    v_or_b32_e32 v4, v2, v14378; VI-NEXT:    v_mov_b32_e32 v1, s44379; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD4380; VI-NEXT:    v_add_f16_e32 v2, s19, v04381; VI-NEXT:    s_lshr_b32 s4, s18, 164382; VI-NEXT:    v_or_b32_e32 v3, v2, v14383; VI-NEXT:    v_mov_b32_e32 v1, s44384; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD4385; VI-NEXT:    v_add_f16_e32 v2, s18, v04386; VI-NEXT:    s_lshr_b32 s4, s17, 164387; VI-NEXT:    v_or_b32_e32 v2, v2, v14388; VI-NEXT:    v_mov_b32_e32 v1, s44389; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD4390; VI-NEXT:    v_add_f16_e32 v11, s17, v04391; VI-NEXT:    s_lshr_b32 s4, s16, 164392; VI-NEXT:    v_or_b32_e32 v1, v11, v14393; VI-NEXT:    v_mov_b32_e32 v11, s44394; VI-NEXT:    v_add_f16_sdwa v11, v11, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD4395; VI-NEXT:    v_add_f16_e32 v0, s16, v04396; VI-NEXT:    v_or_b32_e32 v0, v0, v114397; VI-NEXT:    s_setpc_b64 s[30:31]4398; VI-NEXT:  .LBB19_3:4399; VI-NEXT:    s_branch .LBB19_24400; VI-NEXT:  .LBB19_4:4401; VI-NEXT:    v_mov_b32_e32 v0, s164402; VI-NEXT:    v_mov_b32_e32 v1, s174403; VI-NEXT:    v_mov_b32_e32 v2, s184404; VI-NEXT:    v_mov_b32_e32 v3, s194405; VI-NEXT:    v_mov_b32_e32 v4, s204406; VI-NEXT:    v_mov_b32_e32 v5, s214407; VI-NEXT:    v_mov_b32_e32 v6, s224408; VI-NEXT:    v_mov_b32_e32 v7, s234409; VI-NEXT:    v_mov_b32_e32 v8, s244410; VI-NEXT:    v_mov_b32_e32 v9, s254411; VI-NEXT:    v_mov_b32_e32 v10, s264412; VI-NEXT:    s_setpc_b64 s[30:31]4413;4414; GFX9-LABEL: bitcast_v22f16_to_v11f32_scalar:4415; GFX9:       ; %bb.0:4416; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4417; GFX9-NEXT:    s_cmp_lg_u32 s27, 04418; GFX9-NEXT:    s_cbranch_scc0 .LBB19_34419; GFX9-NEXT:  ; %bb.1: ; %cmp.false4420; GFX9-NEXT:    s_cbranch_execnz .LBB19_44421; GFX9-NEXT:  .LBB19_2: ; %cmp.true4422; GFX9-NEXT:    v_mov_b32_e32 v0, 0x2004423; GFX9-NEXT:    v_pk_add_f16 v10, s26, v0 op_sel_hi:[1,0]4424; GFX9-NEXT:    v_pk_add_f16 v9, s25, v0 op_sel_hi:[1,0]4425; GFX9-NEXT:    v_pk_add_f16 v8, s24, v0 op_sel_hi:[1,0]4426; GFX9-NEXT:    v_pk_add_f16 v7, s23, v0 op_sel_hi:[1,0]4427; GFX9-NEXT:    v_pk_add_f16 v6, s22, v0 op_sel_hi:[1,0]4428; GFX9-NEXT:    v_pk_add_f16 v5, s21, v0 op_sel_hi:[1,0]4429; GFX9-NEXT:    v_pk_add_f16 v4, s20, v0 op_sel_hi:[1,0]4430; GFX9-NEXT:    v_pk_add_f16 v3, s19, v0 op_sel_hi:[1,0]4431; GFX9-NEXT:    v_pk_add_f16 v2, s18, v0 op_sel_hi:[1,0]4432; GFX9-NEXT:    v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]4433; GFX9-NEXT:    v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]4434; GFX9-NEXT:    s_setpc_b64 s[30:31]4435; GFX9-NEXT:  .LBB19_3:4436; GFX9-NEXT:    s_branch .LBB19_24437; GFX9-NEXT:  .LBB19_4:4438; GFX9-NEXT:    v_mov_b32_e32 v0, s164439; GFX9-NEXT:    v_mov_b32_e32 v1, s174440; GFX9-NEXT:    v_mov_b32_e32 v2, s184441; GFX9-NEXT:    v_mov_b32_e32 v3, s194442; GFX9-NEXT:    v_mov_b32_e32 v4, s204443; GFX9-NEXT:    v_mov_b32_e32 v5, s214444; GFX9-NEXT:    v_mov_b32_e32 v6, s224445; GFX9-NEXT:    v_mov_b32_e32 v7, s234446; GFX9-NEXT:    v_mov_b32_e32 v8, s244447; GFX9-NEXT:    v_mov_b32_e32 v9, s254448; GFX9-NEXT:    v_mov_b32_e32 v10, s264449; GFX9-NEXT:    s_setpc_b64 s[30:31]4450;4451; GFX11-LABEL: bitcast_v22f16_to_v11f32_scalar:4452; GFX11:       ; %bb.0:4453; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4454; GFX11-NEXT:    s_mov_b32 s15, s34455; GFX11-NEXT:    s_mov_b32 s14, s24456; GFX11-NEXT:    s_mov_b32 s13, s14457; GFX11-NEXT:    s_mov_b32 s12, s04458; GFX11-NEXT:    s_cmp_lg_u32 s23, 04459; GFX11-NEXT:    s_mov_b32 s0, 04460; GFX11-NEXT:    s_cbranch_scc0 .LBB19_34461; GFX11-NEXT:  ; %bb.1: ; %Flow4462; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s04463; GFX11-NEXT:    s_cbranch_vccnz .LBB19_44464; GFX11-NEXT:  .LBB19_2: ; %cmp.true4465; GFX11-NEXT:    v_pk_add_f16 v10, 0x200, s22 op_sel_hi:[0,1]4466; GFX11-NEXT:    v_pk_add_f16 v9, 0x200, s21 op_sel_hi:[0,1]4467; GFX11-NEXT:    v_pk_add_f16 v8, 0x200, s20 op_sel_hi:[0,1]4468; GFX11-NEXT:    v_pk_add_f16 v7, 0x200, s19 op_sel_hi:[0,1]4469; GFX11-NEXT:    v_pk_add_f16 v6, 0x200, s18 op_sel_hi:[0,1]4470; GFX11-NEXT:    v_pk_add_f16 v5, 0x200, s17 op_sel_hi:[0,1]4471; GFX11-NEXT:    v_pk_add_f16 v4, 0x200, s16 op_sel_hi:[0,1]4472; GFX11-NEXT:    v_pk_add_f16 v3, 0x200, s15 op_sel_hi:[0,1]4473; GFX11-NEXT:    v_pk_add_f16 v2, 0x200, s14 op_sel_hi:[0,1]4474; GFX11-NEXT:    v_pk_add_f16 v1, 0x200, s13 op_sel_hi:[0,1]4475; GFX11-NEXT:    v_pk_add_f16 v0, 0x200, s12 op_sel_hi:[0,1]4476; GFX11-NEXT:    s_setpc_b64 s[30:31]4477; GFX11-NEXT:  .LBB19_3:4478; GFX11-NEXT:    s_branch .LBB19_24479; GFX11-NEXT:  .LBB19_4:4480; GFX11-NEXT:    v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s134481; GFX11-NEXT:    v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s154482; GFX11-NEXT:    v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s174483; GFX11-NEXT:    v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s194484; GFX11-NEXT:    v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s214485; GFX11-NEXT:    v_mov_b32_e32 v10, s224486; GFX11-NEXT:    s_setpc_b64 s[30:31]4487  %cmp = icmp eq i32 %b, 04488  br i1 %cmp, label %cmp.true, label %cmp.false4489 4490cmp.true:4491  %a1 = fadd <22 x half> %a, splat (half 0xH0200)4492  %a2 = bitcast <22 x half> %a1 to <11 x float>4493  br label %end4494 4495cmp.false:4496  %a3 = bitcast <22 x half> %a to <11 x float>4497  br label %end4498 4499end:4500  %phi = phi <11 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]4501  ret <11 x float> %phi4502}4503 4504define <22 x half> @bitcast_v22i16_to_v22f16(<22 x i16> %a, i32 %b) {4505; SI-LABEL: bitcast_v22i16_to_v22f16:4506; SI:       ; %bb.0:4507; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4508; SI-NEXT:    v_mov_b32_e32 v51, v214509; SI-NEXT:    v_mov_b32_e32 v50, v204510; SI-NEXT:    v_mov_b32_e32 v49, v194511; SI-NEXT:    v_mov_b32_e32 v48, v184512; SI-NEXT:    v_mov_b32_e32 v39, v174513; SI-NEXT:    v_mov_b32_e32 v38, v164514; SI-NEXT:    v_mov_b32_e32 v37, v154515; SI-NEXT:    v_mov_b32_e32 v36, v144516; SI-NEXT:    v_mov_b32_e32 v35, v134517; SI-NEXT:    v_mov_b32_e32 v34, v124518; SI-NEXT:    v_mov_b32_e32 v33, v114519; SI-NEXT:    v_mov_b32_e32 v32, v104520; SI-NEXT:    v_mov_b32_e32 v31, v94521; SI-NEXT:    v_mov_b32_e32 v30, v84522; SI-NEXT:    v_mov_b32_e32 v29, v74523; SI-NEXT:    v_mov_b32_e32 v28, v64524; SI-NEXT:    v_mov_b32_e32 v27, v54525; SI-NEXT:    v_mov_b32_e32 v26, v44526; SI-NEXT:    v_mov_b32_e32 v25, v34527; SI-NEXT:    v_mov_b32_e32 v24, v24528; SI-NEXT:    v_mov_b32_e32 v23, v14529; SI-NEXT:    v_mov_b32_e32 v52, v04530; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v224531; SI-NEXT:    ; implicit-def: $vgpr04532; SI-NEXT:    ; implicit-def: $vgpr14533; SI-NEXT:    ; implicit-def: $vgpr24534; SI-NEXT:    ; implicit-def: $vgpr34535; SI-NEXT:    ; implicit-def: $vgpr44536; SI-NEXT:    ; implicit-def: $vgpr54537; SI-NEXT:    ; implicit-def: $vgpr64538; SI-NEXT:    ; implicit-def: $vgpr74539; SI-NEXT:    ; implicit-def: $vgpr84540; SI-NEXT:    ; implicit-def: $vgpr94541; SI-NEXT:    ; implicit-def: $vgpr104542; SI-NEXT:    ; implicit-def: $vgpr114543; SI-NEXT:    ; implicit-def: $vgpr124544; SI-NEXT:    ; implicit-def: $vgpr134545; SI-NEXT:    ; implicit-def: $vgpr144546; SI-NEXT:    ; implicit-def: $vgpr154547; SI-NEXT:    ; implicit-def: $vgpr164548; SI-NEXT:    ; implicit-def: $vgpr174549; SI-NEXT:    ; implicit-def: $vgpr184550; SI-NEXT:    ; implicit-def: $vgpr194551; SI-NEXT:    ; implicit-def: $vgpr204552; SI-NEXT:    ; implicit-def: $vgpr214553; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc4554; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]4555; SI-NEXT:    s_cbranch_execnz .LBB20_34556; SI-NEXT:  ; %bb.1: ; %Flow4557; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]4558; SI-NEXT:    s_cbranch_execnz .LBB20_44559; SI-NEXT:  .LBB20_2: ; %end4560; SI-NEXT:    s_or_b64 exec, exec, s[4:5]4561; SI-NEXT:    s_setpc_b64 s[30:31]4562; SI-NEXT:  .LBB20_3: ; %cmp.false4563; SI-NEXT:    v_cvt_f32_f16_e32 v0, v524564; SI-NEXT:    v_cvt_f32_f16_e32 v1, v234565; SI-NEXT:    v_cvt_f32_f16_e32 v2, v244566; SI-NEXT:    v_cvt_f32_f16_e32 v3, v254567; SI-NEXT:    v_cvt_f32_f16_e32 v4, v264568; SI-NEXT:    v_cvt_f32_f16_e32 v5, v274569; SI-NEXT:    v_cvt_f32_f16_e32 v6, v284570; SI-NEXT:    v_cvt_f32_f16_e32 v7, v294571; SI-NEXT:    v_cvt_f32_f16_e32 v8, v304572; SI-NEXT:    v_cvt_f32_f16_e32 v9, v314573; SI-NEXT:    v_cvt_f32_f16_e32 v10, v324574; SI-NEXT:    v_cvt_f32_f16_e32 v11, v334575; SI-NEXT:    v_cvt_f32_f16_e32 v12, v344576; SI-NEXT:    v_cvt_f32_f16_e32 v13, v354577; SI-NEXT:    v_cvt_f32_f16_e32 v14, v364578; SI-NEXT:    v_cvt_f32_f16_e32 v15, v374579; SI-NEXT:    v_cvt_f32_f16_e32 v16, v384580; SI-NEXT:    v_cvt_f32_f16_e32 v17, v394581; SI-NEXT:    v_cvt_f32_f16_e32 v18, v484582; SI-NEXT:    v_cvt_f32_f16_e32 v19, v494583; SI-NEXT:    v_cvt_f32_f16_e32 v20, v504584; SI-NEXT:    v_cvt_f32_f16_e32 v21, v514585; SI-NEXT:    ; implicit-def: $vgpr524586; SI-NEXT:    ; implicit-def: $vgpr234587; SI-NEXT:    ; implicit-def: $vgpr244588; SI-NEXT:    ; implicit-def: $vgpr254589; SI-NEXT:    ; implicit-def: $vgpr264590; SI-NEXT:    ; implicit-def: $vgpr274591; SI-NEXT:    ; implicit-def: $vgpr284592; SI-NEXT:    ; implicit-def: $vgpr294593; SI-NEXT:    ; implicit-def: $vgpr304594; SI-NEXT:    ; implicit-def: $vgpr314595; SI-NEXT:    ; implicit-def: $vgpr324596; SI-NEXT:    ; implicit-def: $vgpr334597; SI-NEXT:    ; implicit-def: $vgpr344598; SI-NEXT:    ; implicit-def: $vgpr354599; SI-NEXT:    ; implicit-def: $vgpr364600; SI-NEXT:    ; implicit-def: $vgpr374601; SI-NEXT:    ; implicit-def: $vgpr384602; SI-NEXT:    ; implicit-def: $vgpr394603; SI-NEXT:    ; implicit-def: $vgpr484604; SI-NEXT:    ; implicit-def: $vgpr494605; SI-NEXT:    ; implicit-def: $vgpr504606; SI-NEXT:    ; implicit-def: $vgpr514607; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]4608; SI-NEXT:    s_cbranch_execz .LBB20_24609; SI-NEXT:  .LBB20_4: ; %cmp.true4610; SI-NEXT:    v_add_i32_e32 v21, vcc, 3, v514611; SI-NEXT:    v_add_i32_e32 v20, vcc, 3, v504612; SI-NEXT:    v_add_i32_e32 v19, vcc, 3, v494613; SI-NEXT:    v_add_i32_e32 v18, vcc, 3, v484614; SI-NEXT:    v_add_i32_e32 v17, vcc, 3, v394615; SI-NEXT:    v_add_i32_e32 v16, vcc, 3, v384616; SI-NEXT:    v_add_i32_e32 v15, vcc, 3, v374617; SI-NEXT:    v_add_i32_e32 v14, vcc, 3, v364618; SI-NEXT:    v_add_i32_e32 v13, vcc, 3, v354619; SI-NEXT:    v_add_i32_e32 v12, vcc, 3, v344620; SI-NEXT:    v_add_i32_e32 v11, vcc, 3, v334621; SI-NEXT:    v_add_i32_e32 v10, vcc, 3, v324622; SI-NEXT:    v_add_i32_e32 v9, vcc, 3, v314623; SI-NEXT:    v_add_i32_e32 v8, vcc, 3, v304624; SI-NEXT:    v_add_i32_e32 v7, vcc, 3, v294625; SI-NEXT:    v_add_i32_e32 v6, vcc, 3, v284626; SI-NEXT:    v_add_i32_e32 v5, vcc, 3, v274627; SI-NEXT:    v_add_i32_e32 v4, vcc, 3, v264628; SI-NEXT:    v_add_i32_e32 v3, vcc, 3, v254629; SI-NEXT:    v_add_i32_e32 v2, vcc, 3, v244630; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v234631; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v524632; SI-NEXT:    v_cvt_f32_f16_e32 v0, v04633; SI-NEXT:    v_cvt_f32_f16_e32 v1, v14634; SI-NEXT:    v_cvt_f32_f16_e32 v2, v24635; SI-NEXT:    v_cvt_f32_f16_e32 v3, v34636; SI-NEXT:    v_cvt_f32_f16_e32 v4, v44637; SI-NEXT:    v_cvt_f32_f16_e32 v5, v54638; SI-NEXT:    v_cvt_f32_f16_e32 v6, v64639; SI-NEXT:    v_cvt_f32_f16_e32 v7, v74640; SI-NEXT:    v_cvt_f32_f16_e32 v8, v84641; SI-NEXT:    v_cvt_f32_f16_e32 v9, v94642; SI-NEXT:    v_cvt_f32_f16_e32 v10, v104643; SI-NEXT:    v_cvt_f32_f16_e32 v11, v114644; SI-NEXT:    v_cvt_f32_f16_e32 v12, v124645; SI-NEXT:    v_cvt_f32_f16_e32 v13, v134646; SI-NEXT:    v_cvt_f32_f16_e32 v14, v144647; SI-NEXT:    v_cvt_f32_f16_e32 v15, v154648; SI-NEXT:    v_cvt_f32_f16_e32 v16, v164649; SI-NEXT:    v_cvt_f32_f16_e32 v17, v174650; SI-NEXT:    v_cvt_f32_f16_e32 v18, v184651; SI-NEXT:    v_cvt_f32_f16_e32 v19, v194652; SI-NEXT:    v_cvt_f32_f16_e32 v20, v204653; SI-NEXT:    v_cvt_f32_f16_e32 v21, v214654; SI-NEXT:    s_or_b64 exec, exec, s[4:5]4655; SI-NEXT:    s_setpc_b64 s[30:31]4656;4657; VI-LABEL: bitcast_v22i16_to_v22f16:4658; VI:       ; %bb.0:4659; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4660; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v114661; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc4662; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]4663; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]4664; VI-NEXT:    s_cbranch_execz .LBB20_24665; VI-NEXT:  ; %bb.1: ; %cmp.true4666; VI-NEXT:    v_mov_b32_e32 v11, 34667; VI-NEXT:    v_add_u16_sdwa v19, v10, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4668; VI-NEXT:    v_add_u16_e32 v10, 3, v104669; VI-NEXT:    v_or_b32_e32 v10, v10, v194670; VI-NEXT:    v_add_u16_sdwa v19, v9, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4671; VI-NEXT:    v_add_u16_e32 v9, 3, v94672; VI-NEXT:    v_add_u16_sdwa v12, v0, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4673; VI-NEXT:    v_add_u16_sdwa v13, v1, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4674; VI-NEXT:    v_add_u16_sdwa v14, v2, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4675; VI-NEXT:    v_add_u16_sdwa v15, v3, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4676; VI-NEXT:    v_add_u16_sdwa v16, v4, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4677; VI-NEXT:    v_add_u16_sdwa v17, v5, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4678; VI-NEXT:    v_add_u16_sdwa v18, v6, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4679; VI-NEXT:    v_or_b32_e32 v9, v9, v194680; VI-NEXT:    v_add_u16_sdwa v19, v7, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4681; VI-NEXT:    v_add_u16_sdwa v11, v8, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4682; VI-NEXT:    v_add_u16_e32 v8, 3, v84683; VI-NEXT:    v_add_u16_e32 v7, 3, v74684; VI-NEXT:    v_add_u16_e32 v6, 3, v64685; VI-NEXT:    v_add_u16_e32 v5, 3, v54686; VI-NEXT:    v_add_u16_e32 v4, 3, v44687; VI-NEXT:    v_add_u16_e32 v3, 3, v34688; VI-NEXT:    v_add_u16_e32 v2, 3, v24689; VI-NEXT:    v_add_u16_e32 v1, 3, v14690; VI-NEXT:    v_add_u16_e32 v0, 3, v04691; VI-NEXT:    v_or_b32_e32 v8, v8, v114692; VI-NEXT:    v_or_b32_e32 v7, v7, v194693; VI-NEXT:    v_or_b32_e32 v6, v6, v184694; VI-NEXT:    v_or_b32_e32 v5, v5, v174695; VI-NEXT:    v_or_b32_e32 v4, v4, v164696; VI-NEXT:    v_or_b32_e32 v3, v3, v154697; VI-NEXT:    v_or_b32_e32 v2, v2, v144698; VI-NEXT:    v_or_b32_e32 v1, v1, v134699; VI-NEXT:    v_or_b32_e32 v0, v0, v124700; VI-NEXT:  .LBB20_2: ; %end4701; VI-NEXT:    s_or_b64 exec, exec, s[4:5]4702; VI-NEXT:    s_setpc_b64 s[30:31]4703;4704; GFX9-LABEL: bitcast_v22i16_to_v22f16:4705; GFX9:       ; %bb.0:4706; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4707; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v114708; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc4709; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]4710; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]4711; GFX9-NEXT:    s_cbranch_execz .LBB20_24712; GFX9-NEXT:  ; %bb.1: ; %cmp.true4713; GFX9-NEXT:    v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]4714; GFX9-NEXT:    v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]4715; GFX9-NEXT:    v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]4716; GFX9-NEXT:    v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]4717; GFX9-NEXT:    v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]4718; GFX9-NEXT:    v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]4719; GFX9-NEXT:    v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]4720; GFX9-NEXT:    v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]4721; GFX9-NEXT:    v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]4722; GFX9-NEXT:    v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]4723; GFX9-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]4724; GFX9-NEXT:  .LBB20_2: ; %end4725; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]4726; GFX9-NEXT:    s_setpc_b64 s[30:31]4727;4728; GFX11-LABEL: bitcast_v22i16_to_v22f16:4729; GFX11:       ; %bb.0:4730; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4731; GFX11-NEXT:    s_mov_b32 s0, exec_lo4732; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v114733; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s04734; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)4735; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s04736; GFX11-NEXT:    s_cbranch_execz .LBB20_24737; GFX11-NEXT:  ; %bb.1: ; %cmp.true4738; GFX11-NEXT:    v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]4739; GFX11-NEXT:    v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]4740; GFX11-NEXT:    v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]4741; GFX11-NEXT:    v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]4742; GFX11-NEXT:    v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]4743; GFX11-NEXT:    v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]4744; GFX11-NEXT:    v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]4745; GFX11-NEXT:    v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]4746; GFX11-NEXT:    v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]4747; GFX11-NEXT:    v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]4748; GFX11-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]4749; GFX11-NEXT:  .LBB20_2: ; %end4750; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s04751; GFX11-NEXT:    s_setpc_b64 s[30:31]4752  %cmp = icmp eq i32 %b, 04753  br i1 %cmp, label %cmp.true, label %cmp.false4754 4755cmp.true:4756  %a1 = add <22 x i16> %a, splat (i16 3)4757  %a2 = bitcast <22 x i16> %a1 to <22 x half>4758  br label %end4759 4760cmp.false:4761  %a3 = bitcast <22 x i16> %a to <22 x half>4762  br label %end4763 4764end:4765  %phi = phi <22 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]4766  ret <22 x half> %phi4767}4768 4769define inreg <22 x half> @bitcast_v22i16_to_v22f16_scalar(<22 x i16> inreg %a, i32 inreg %b) {4770; SI-LABEL: bitcast_v22i16_to_v22f16_scalar:4771; SI:       ; %bb.0:4772; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4773; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v84774; SI-NEXT:    v_mov_b32_e32 v26, v74775; SI-NEXT:    v_mov_b32_e32 v25, v64776; SI-NEXT:    v_mov_b32_e32 v24, v54777; SI-NEXT:    v_mov_b32_e32 v23, v44778; SI-NEXT:    v_mov_b32_e32 v22, v34779; SI-NEXT:    v_mov_b32_e32 v29, v24780; SI-NEXT:    v_mov_b32_e32 v28, v14781; SI-NEXT:    v_mov_b32_e32 v27, v04782; SI-NEXT:    s_and_b64 s[4:5], vcc, exec4783; SI-NEXT:    s_cbranch_scc0 .LBB21_44784; SI-NEXT:  ; %bb.1: ; %cmp.false4785; SI-NEXT:    v_cvt_f32_f16_e32 v0, s164786; SI-NEXT:    v_cvt_f32_f16_e32 v1, s174787; SI-NEXT:    v_cvt_f32_f16_e32 v2, s184788; SI-NEXT:    v_cvt_f32_f16_e32 v3, s194789; SI-NEXT:    v_cvt_f32_f16_e32 v4, s204790; SI-NEXT:    v_cvt_f32_f16_e32 v5, s214791; SI-NEXT:    v_cvt_f32_f16_e32 v6, s224792; SI-NEXT:    v_cvt_f32_f16_e32 v7, s234793; SI-NEXT:    v_cvt_f32_f16_e32 v8, s244794; SI-NEXT:    v_cvt_f32_f16_e32 v9, s254795; SI-NEXT:    v_cvt_f32_f16_e32 v10, s264796; SI-NEXT:    v_cvt_f32_f16_e32 v11, s274797; SI-NEXT:    v_cvt_f32_f16_e32 v12, s284798; SI-NEXT:    v_cvt_f32_f16_e32 v13, s294799; SI-NEXT:    v_cvt_f32_f16_e32 v14, v274800; SI-NEXT:    v_cvt_f32_f16_e32 v15, v284801; SI-NEXT:    v_cvt_f32_f16_e32 v16, v294802; SI-NEXT:    v_cvt_f32_f16_e32 v17, v224803; SI-NEXT:    v_cvt_f32_f16_e32 v18, v234804; SI-NEXT:    v_cvt_f32_f16_e32 v19, v244805; SI-NEXT:    v_cvt_f32_f16_e32 v20, v254806; SI-NEXT:    v_cvt_f32_f16_e32 v21, v264807; SI-NEXT:    s_cbranch_execnz .LBB21_34808; SI-NEXT:  .LBB21_2: ; %cmp.true4809; SI-NEXT:    v_add_i32_e32 v21, vcc, 3, v264810; SI-NEXT:    v_add_i32_e32 v20, vcc, 3, v254811; SI-NEXT:    v_add_i32_e32 v19, vcc, 3, v244812; SI-NEXT:    v_add_i32_e32 v18, vcc, 3, v234813; SI-NEXT:    v_add_i32_e32 v17, vcc, 3, v224814; SI-NEXT:    v_add_i32_e32 v16, vcc, 3, v294815; SI-NEXT:    v_add_i32_e32 v15, vcc, 3, v284816; SI-NEXT:    v_add_i32_e32 v14, vcc, 3, v274817; SI-NEXT:    s_add_i32 s29, s29, 34818; SI-NEXT:    s_add_i32 s28, s28, 34819; SI-NEXT:    s_add_i32 s27, s27, 34820; SI-NEXT:    s_add_i32 s26, s26, 34821; SI-NEXT:    s_add_i32 s25, s25, 34822; SI-NEXT:    s_add_i32 s24, s24, 34823; SI-NEXT:    s_add_i32 s23, s23, 34824; SI-NEXT:    s_add_i32 s22, s22, 34825; SI-NEXT:    s_add_i32 s21, s21, 34826; SI-NEXT:    s_add_i32 s20, s20, 34827; SI-NEXT:    s_add_i32 s19, s19, 34828; SI-NEXT:    s_add_i32 s18, s18, 34829; SI-NEXT:    s_add_i32 s17, s17, 34830; SI-NEXT:    s_add_i32 s16, s16, 34831; SI-NEXT:    v_cvt_f32_f16_e32 v0, s164832; SI-NEXT:    v_cvt_f32_f16_e32 v1, s174833; SI-NEXT:    v_cvt_f32_f16_e32 v2, s184834; SI-NEXT:    v_cvt_f32_f16_e32 v3, s194835; SI-NEXT:    v_cvt_f32_f16_e32 v4, s204836; SI-NEXT:    v_cvt_f32_f16_e32 v5, s214837; SI-NEXT:    v_cvt_f32_f16_e32 v6, s224838; SI-NEXT:    v_cvt_f32_f16_e32 v7, s234839; SI-NEXT:    v_cvt_f32_f16_e32 v8, s244840; SI-NEXT:    v_cvt_f32_f16_e32 v9, s254841; SI-NEXT:    v_cvt_f32_f16_e32 v10, s264842; SI-NEXT:    v_cvt_f32_f16_e32 v11, s274843; SI-NEXT:    v_cvt_f32_f16_e32 v12, s284844; SI-NEXT:    v_cvt_f32_f16_e32 v13, s294845; SI-NEXT:    v_cvt_f32_f16_e32 v14, v144846; SI-NEXT:    v_cvt_f32_f16_e32 v15, v154847; SI-NEXT:    v_cvt_f32_f16_e32 v16, v164848; SI-NEXT:    v_cvt_f32_f16_e32 v17, v174849; SI-NEXT:    v_cvt_f32_f16_e32 v18, v184850; SI-NEXT:    v_cvt_f32_f16_e32 v19, v194851; SI-NEXT:    v_cvt_f32_f16_e32 v20, v204852; SI-NEXT:    v_cvt_f32_f16_e32 v21, v214853; SI-NEXT:  .LBB21_3: ; %end4854; SI-NEXT:    s_setpc_b64 s[30:31]4855; SI-NEXT:  .LBB21_4:4856; SI-NEXT:    ; implicit-def: $vgpr04857; SI-NEXT:    ; implicit-def: $vgpr14858; SI-NEXT:    ; implicit-def: $vgpr24859; SI-NEXT:    ; implicit-def: $vgpr34860; SI-NEXT:    ; implicit-def: $vgpr44861; SI-NEXT:    ; implicit-def: $vgpr54862; SI-NEXT:    ; implicit-def: $vgpr64863; SI-NEXT:    ; implicit-def: $vgpr74864; SI-NEXT:    ; implicit-def: $vgpr84865; SI-NEXT:    ; implicit-def: $vgpr94866; SI-NEXT:    ; implicit-def: $vgpr104867; SI-NEXT:    ; implicit-def: $vgpr114868; SI-NEXT:    ; implicit-def: $vgpr124869; SI-NEXT:    ; implicit-def: $vgpr134870; SI-NEXT:    ; implicit-def: $vgpr144871; SI-NEXT:    ; implicit-def: $vgpr154872; SI-NEXT:    ; implicit-def: $vgpr164873; SI-NEXT:    ; implicit-def: $vgpr174874; SI-NEXT:    ; implicit-def: $vgpr184875; SI-NEXT:    ; implicit-def: $vgpr194876; SI-NEXT:    ; implicit-def: $vgpr204877; SI-NEXT:    ; implicit-def: $vgpr214878; SI-NEXT:    s_branch .LBB21_24879;4880; VI-LABEL: bitcast_v22i16_to_v22f16_scalar:4881; VI:       ; %bb.0:4882; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4883; VI-NEXT:    s_cmp_lg_u32 s27, 04884; VI-NEXT:    s_cbranch_scc0 .LBB21_44885; VI-NEXT:  ; %bb.1: ; %cmp.false4886; VI-NEXT:    s_cbranch_execnz .LBB21_34887; VI-NEXT:  .LBB21_2: ; %cmp.true4888; VI-NEXT:    s_and_b32 s4, s16, 0xffff00004889; VI-NEXT:    s_add_i32 s5, s16, 34890; VI-NEXT:    s_and_b32 s6, s17, 0xffff00004891; VI-NEXT:    s_add_i32 s7, s17, 34892; VI-NEXT:    s_and_b32 s8, s18, 0xffff00004893; VI-NEXT:    s_add_i32 s9, s18, 34894; VI-NEXT:    s_and_b32 s10, s19, 0xffff00004895; VI-NEXT:    s_add_i32 s11, s19, 34896; VI-NEXT:    s_add_i32 s13, s20, 34897; VI-NEXT:    s_and_b32 s14, s21, 0xffff00004898; VI-NEXT:    s_add_i32 s15, s21, 34899; VI-NEXT:    s_and_b32 s16, s22, 0xffff00004900; VI-NEXT:    s_add_i32 s17, s22, 34901; VI-NEXT:    s_and_b32 s18, s23, 0xffff00004902; VI-NEXT:    s_add_i32 s19, s23, 34903; VI-NEXT:    s_add_i32 s21, s24, 34904; VI-NEXT:    s_and_b32 s22, s25, 0xffff00004905; VI-NEXT:    s_add_i32 s23, s25, 34906; VI-NEXT:    s_add_i32 s25, s26, 34907; VI-NEXT:    s_and_b32 s12, s20, 0xffff00004908; VI-NEXT:    s_and_b32 s20, s24, 0xffff00004909; VI-NEXT:    s_and_b32 s24, s26, 0xffff00004910; VI-NEXT:    s_and_b32 s25, s25, 0xffff4911; VI-NEXT:    s_and_b32 s23, s23, 0xffff4912; VI-NEXT:    s_and_b32 s21, s21, 0xffff4913; VI-NEXT:    s_and_b32 s19, s19, 0xffff4914; VI-NEXT:    s_and_b32 s17, s17, 0xffff4915; VI-NEXT:    s_and_b32 s15, s15, 0xffff4916; VI-NEXT:    s_and_b32 s13, s13, 0xffff4917; VI-NEXT:    s_and_b32 s11, s11, 0xffff4918; VI-NEXT:    s_and_b32 s9, s9, 0xffff4919; VI-NEXT:    s_and_b32 s7, s7, 0xffff4920; VI-NEXT:    s_and_b32 s5, s5, 0xffff4921; VI-NEXT:    s_or_b32 s24, s24, s254922; VI-NEXT:    s_or_b32 s22, s22, s234923; VI-NEXT:    s_or_b32 s20, s20, s214924; VI-NEXT:    s_or_b32 s18, s18, s194925; VI-NEXT:    s_or_b32 s16, s16, s174926; VI-NEXT:    s_or_b32 s14, s14, s154927; VI-NEXT:    s_or_b32 s12, s12, s134928; VI-NEXT:    s_or_b32 s10, s10, s114929; VI-NEXT:    s_or_b32 s8, s8, s94930; VI-NEXT:    s_or_b32 s6, s6, s74931; VI-NEXT:    s_or_b32 s4, s4, s54932; VI-NEXT:    s_add_i32 s26, s24, 0x300004933; VI-NEXT:    s_add_i32 s25, s22, 0x300004934; VI-NEXT:    s_add_i32 s24, s20, 0x300004935; VI-NEXT:    s_add_i32 s23, s18, 0x300004936; VI-NEXT:    s_add_i32 s22, s16, 0x300004937; VI-NEXT:    s_add_i32 s21, s14, 0x300004938; VI-NEXT:    s_add_i32 s20, s12, 0x300004939; VI-NEXT:    s_add_i32 s19, s10, 0x300004940; VI-NEXT:    s_add_i32 s18, s8, 0x300004941; VI-NEXT:    s_add_i32 s17, s6, 0x300004942; VI-NEXT:    s_add_i32 s16, s4, 0x300004943; VI-NEXT:  .LBB21_3: ; %end4944; VI-NEXT:    v_mov_b32_e32 v0, s164945; VI-NEXT:    v_mov_b32_e32 v1, s174946; VI-NEXT:    v_mov_b32_e32 v2, s184947; VI-NEXT:    v_mov_b32_e32 v3, s194948; VI-NEXT:    v_mov_b32_e32 v4, s204949; VI-NEXT:    v_mov_b32_e32 v5, s214950; VI-NEXT:    v_mov_b32_e32 v6, s224951; VI-NEXT:    v_mov_b32_e32 v7, s234952; VI-NEXT:    v_mov_b32_e32 v8, s244953; VI-NEXT:    v_mov_b32_e32 v9, s254954; VI-NEXT:    v_mov_b32_e32 v10, s264955; VI-NEXT:    s_setpc_b64 s[30:31]4956; VI-NEXT:  .LBB21_4:4957; VI-NEXT:    s_branch .LBB21_24958;4959; GFX9-LABEL: bitcast_v22i16_to_v22f16_scalar:4960; GFX9:       ; %bb.0:4961; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4962; GFX9-NEXT:    s_cmp_lg_u32 s27, 04963; GFX9-NEXT:    s_cbranch_scc0 .LBB21_34964; GFX9-NEXT:  ; %bb.1: ; %cmp.false4965; GFX9-NEXT:    s_cbranch_execnz .LBB21_44966; GFX9-NEXT:  .LBB21_2: ; %cmp.true4967; GFX9-NEXT:    v_pk_add_u16 v10, s26, 3 op_sel_hi:[1,0]4968; GFX9-NEXT:    v_pk_add_u16 v9, s25, 3 op_sel_hi:[1,0]4969; GFX9-NEXT:    v_pk_add_u16 v8, s24, 3 op_sel_hi:[1,0]4970; GFX9-NEXT:    v_pk_add_u16 v7, s23, 3 op_sel_hi:[1,0]4971; GFX9-NEXT:    v_pk_add_u16 v6, s22, 3 op_sel_hi:[1,0]4972; GFX9-NEXT:    v_pk_add_u16 v5, s21, 3 op_sel_hi:[1,0]4973; GFX9-NEXT:    v_pk_add_u16 v4, s20, 3 op_sel_hi:[1,0]4974; GFX9-NEXT:    v_pk_add_u16 v3, s19, 3 op_sel_hi:[1,0]4975; GFX9-NEXT:    v_pk_add_u16 v2, s18, 3 op_sel_hi:[1,0]4976; GFX9-NEXT:    v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]4977; GFX9-NEXT:    v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]4978; GFX9-NEXT:    s_setpc_b64 s[30:31]4979; GFX9-NEXT:  .LBB21_3:4980; GFX9-NEXT:    s_branch .LBB21_24981; GFX9-NEXT:  .LBB21_4:4982; GFX9-NEXT:    v_mov_b32_e32 v0, s164983; GFX9-NEXT:    v_mov_b32_e32 v1, s174984; GFX9-NEXT:    v_mov_b32_e32 v2, s184985; GFX9-NEXT:    v_mov_b32_e32 v3, s194986; GFX9-NEXT:    v_mov_b32_e32 v4, s204987; GFX9-NEXT:    v_mov_b32_e32 v5, s214988; GFX9-NEXT:    v_mov_b32_e32 v6, s224989; GFX9-NEXT:    v_mov_b32_e32 v7, s234990; GFX9-NEXT:    v_mov_b32_e32 v8, s244991; GFX9-NEXT:    v_mov_b32_e32 v9, s254992; GFX9-NEXT:    v_mov_b32_e32 v10, s264993; GFX9-NEXT:    v_mov_b32_e32 v11, s274994; GFX9-NEXT:    v_mov_b32_e32 v12, s284995; GFX9-NEXT:    v_mov_b32_e32 v13, s294996; GFX9-NEXT:    v_mov_b32_e32 v14, s304997; GFX9-NEXT:    v_mov_b32_e32 v15, s314998; GFX9-NEXT:    s_setpc_b64 s[30:31]4999;5000; GFX11-LABEL: bitcast_v22i16_to_v22f16_scalar:5001; GFX11:       ; %bb.0:5002; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5003; GFX11-NEXT:    s_mov_b32 s15, s35004; GFX11-NEXT:    s_mov_b32 s14, s25005; GFX11-NEXT:    s_mov_b32 s13, s15006; GFX11-NEXT:    s_mov_b32 s12, s05007; GFX11-NEXT:    s_cmp_lg_u32 s23, 05008; GFX11-NEXT:    s_mov_b32 s0, 05009; GFX11-NEXT:    s_cbranch_scc0 .LBB21_35010; GFX11-NEXT:  ; %bb.1: ; %Flow5011; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s05012; GFX11-NEXT:    s_cbranch_vccnz .LBB21_45013; GFX11-NEXT:  .LBB21_2: ; %cmp.true5014; GFX11-NEXT:    v_pk_add_u16 v10, s22, 3 op_sel_hi:[1,0]5015; GFX11-NEXT:    v_pk_add_u16 v9, s21, 3 op_sel_hi:[1,0]5016; GFX11-NEXT:    v_pk_add_u16 v8, s20, 3 op_sel_hi:[1,0]5017; GFX11-NEXT:    v_pk_add_u16 v7, s19, 3 op_sel_hi:[1,0]5018; GFX11-NEXT:    v_pk_add_u16 v6, s18, 3 op_sel_hi:[1,0]5019; GFX11-NEXT:    v_pk_add_u16 v5, s17, 3 op_sel_hi:[1,0]5020; GFX11-NEXT:    v_pk_add_u16 v4, s16, 3 op_sel_hi:[1,0]5021; GFX11-NEXT:    v_pk_add_u16 v3, s15, 3 op_sel_hi:[1,0]5022; GFX11-NEXT:    v_pk_add_u16 v2, s14, 3 op_sel_hi:[1,0]5023; GFX11-NEXT:    v_pk_add_u16 v1, s13, 3 op_sel_hi:[1,0]5024; GFX11-NEXT:    v_pk_add_u16 v0, s12, 3 op_sel_hi:[1,0]5025; GFX11-NEXT:    s_setpc_b64 s[30:31]5026; GFX11-NEXT:  .LBB21_3:5027; GFX11-NEXT:    s_branch .LBB21_25028; GFX11-NEXT:  .LBB21_4:5029; GFX11-NEXT:    v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s135030; GFX11-NEXT:    v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s155031; GFX11-NEXT:    v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s175032; GFX11-NEXT:    v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s195033; GFX11-NEXT:    v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s215034; GFX11-NEXT:    v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s235035; GFX11-NEXT:    v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s255036; GFX11-NEXT:    v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s275037; GFX11-NEXT:    s_setpc_b64 s[30:31]5038  %cmp = icmp eq i32 %b, 05039  br i1 %cmp, label %cmp.true, label %cmp.false5040 5041cmp.true:5042  %a1 = add <22 x i16> %a, splat (i16 3)5043  %a2 = bitcast <22 x i16> %a1 to <22 x half>5044  br label %end5045 5046cmp.false:5047  %a3 = bitcast <22 x i16> %a to <22 x half>5048  br label %end5049 5050end:5051  %phi = phi <22 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]5052  ret <22 x half> %phi5053}5054 5055define <22 x i16> @bitcast_v22f16_to_v22i16(<22 x half> %a, i32 %b) {5056; SI-LABEL: bitcast_v22f16_to_v22i16:5057; SI:       ; %bb.0:5058; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5059; SI-NEXT:    v_cvt_f16_f32_e32 v0, v05060; SI-NEXT:    v_cvt_f16_f32_e32 v1, v15061; SI-NEXT:    v_cvt_f16_f32_e32 v2, v25062; SI-NEXT:    v_cvt_f16_f32_e32 v3, v35063; SI-NEXT:    v_cvt_f16_f32_e32 v4, v45064; SI-NEXT:    v_cvt_f16_f32_e32 v5, v55065; SI-NEXT:    v_cvt_f16_f32_e32 v6, v65066; SI-NEXT:    v_cvt_f16_f32_e32 v7, v75067; SI-NEXT:    v_cvt_f16_f32_e32 v8, v85068; SI-NEXT:    v_cvt_f16_f32_e32 v9, v95069; SI-NEXT:    v_cvt_f16_f32_e32 v10, v105070; SI-NEXT:    v_cvt_f16_f32_e32 v11, v115071; SI-NEXT:    v_cvt_f16_f32_e32 v12, v125072; SI-NEXT:    v_cvt_f16_f32_e32 v13, v135073; SI-NEXT:    v_cvt_f16_f32_e32 v14, v145074; SI-NEXT:    v_cvt_f16_f32_e32 v15, v155075; SI-NEXT:    v_cvt_f16_f32_e32 v16, v165076; SI-NEXT:    v_cvt_f16_f32_e32 v17, v175077; SI-NEXT:    v_cvt_f16_f32_e32 v18, v185078; SI-NEXT:    v_cvt_f16_f32_e32 v19, v195079; SI-NEXT:    v_cvt_f16_f32_e32 v20, v205080; SI-NEXT:    v_cvt_f16_f32_e32 v21, v215081; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v225082; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc5083; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]5084; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]5085; SI-NEXT:    s_cbranch_execz .LBB22_25086; SI-NEXT:  ; %bb.1: ; %cmp.true5087; SI-NEXT:    v_cvt_f32_f16_e32 v21, v215088; SI-NEXT:    v_cvt_f32_f16_e32 v20, v205089; SI-NEXT:    v_cvt_f32_f16_e32 v19, v195090; SI-NEXT:    v_cvt_f32_f16_e32 v18, v185091; SI-NEXT:    v_cvt_f32_f16_e32 v15, v155092; SI-NEXT:    v_cvt_f32_f16_e32 v14, v145093; SI-NEXT:    v_cvt_f32_f16_e32 v11, v115094; SI-NEXT:    v_add_f32_e32 v21, 0x38000000, v215095; SI-NEXT:    v_cvt_f32_f16_e32 v10, v105096; SI-NEXT:    v_cvt_f32_f16_e32 v7, v75097; SI-NEXT:    v_add_f32_e32 v20, 0x38000000, v205098; SI-NEXT:    v_cvt_f16_f32_e32 v21, v215099; SI-NEXT:    v_add_f32_e32 v19, 0x38000000, v195100; SI-NEXT:    v_cvt_f32_f16_e32 v6, v65101; SI-NEXT:    v_cvt_f32_f16_e32 v3, v35102; SI-NEXT:    v_cvt_f16_f32_e32 v20, v205103; SI-NEXT:    v_cvt_f16_f32_e32 v19, v195104; SI-NEXT:    v_add_f32_e32 v18, 0x38000000, v185105; SI-NEXT:    v_add_f32_e32 v15, 0x38000000, v155106; SI-NEXT:    v_cvt_f32_f16_e32 v2, v25107; SI-NEXT:    v_cvt_f32_f16_e32 v1, v15108; SI-NEXT:    v_cvt_f32_f16_e32 v5, v55109; SI-NEXT:    v_cvt_f32_f16_e32 v9, v95110; SI-NEXT:    v_cvt_f32_f16_e32 v13, v135111; SI-NEXT:    v_cvt_f32_f16_e32 v17, v175112; SI-NEXT:    v_cvt_f16_f32_e32 v18, v185113; SI-NEXT:    v_cvt_f16_f32_e32 v15, v155114; SI-NEXT:    v_add_f32_e32 v14, 0x38000000, v145115; SI-NEXT:    v_add_f32_e32 v11, 0x38000000, v115116; SI-NEXT:    v_cvt_f32_f16_e32 v0, v05117; SI-NEXT:    v_cvt_f32_f16_e32 v4, v45118; SI-NEXT:    v_cvt_f32_f16_e32 v8, v85119; SI-NEXT:    v_cvt_f32_f16_e32 v12, v125120; SI-NEXT:    v_cvt_f32_f16_e32 v16, v165121; SI-NEXT:    v_cvt_f16_f32_e32 v14, v145122; SI-NEXT:    v_cvt_f16_f32_e32 v11, v115123; SI-NEXT:    v_add_f32_e32 v10, 0x38000000, v105124; SI-NEXT:    v_add_f32_e32 v7, 0x38000000, v75125; SI-NEXT:    v_lshlrev_b32_e32 v22, 16, v215126; SI-NEXT:    v_cvt_f16_f32_e32 v10, v105127; SI-NEXT:    v_cvt_f16_f32_e32 v7, v75128; SI-NEXT:    v_add_f32_e32 v6, 0x38000000, v65129; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v35130; SI-NEXT:    v_or_b32_e32 v20, v20, v225131; SI-NEXT:    v_lshlrev_b32_e32 v22, 16, v195132; SI-NEXT:    v_cvt_f16_f32_e32 v6, v65133; SI-NEXT:    v_cvt_f16_f32_e32 v3, v35134; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v25135; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v15136; SI-NEXT:    v_add_f32_e32 v5, 0x38000000, v55137; SI-NEXT:    v_add_f32_e32 v9, 0x38000000, v95138; SI-NEXT:    v_add_f32_e32 v13, 0x38000000, v135139; SI-NEXT:    v_add_f32_e32 v17, 0x38000000, v175140; SI-NEXT:    v_or_b32_e32 v18, v18, v225141; SI-NEXT:    v_lshlrev_b32_e32 v22, 16, v155142; SI-NEXT:    v_cvt_f16_f32_e32 v2, v25143; SI-NEXT:    v_cvt_f16_f32_e32 v1, v15144; SI-NEXT:    v_add_f32_e32 v0, 0x38000000, v05145; SI-NEXT:    v_cvt_f16_f32_e32 v5, v55146; SI-NEXT:    v_add_f32_e32 v4, 0x38000000, v45147; SI-NEXT:    v_cvt_f16_f32_e32 v9, v95148; SI-NEXT:    v_add_f32_e32 v8, 0x38000000, v85149; SI-NEXT:    v_cvt_f16_f32_e32 v13, v135150; SI-NEXT:    v_add_f32_e32 v12, 0x38000000, v125151; SI-NEXT:    v_cvt_f16_f32_e32 v17, v175152; SI-NEXT:    v_add_f32_e32 v16, 0x38000000, v165153; SI-NEXT:    v_or_b32_e32 v14, v14, v225154; SI-NEXT:    v_lshlrev_b32_e32 v22, 16, v115155; SI-NEXT:    v_cvt_f16_f32_e32 v0, v05156; SI-NEXT:    v_cvt_f16_f32_e32 v4, v45157; SI-NEXT:    v_cvt_f16_f32_e32 v8, v85158; SI-NEXT:    v_cvt_f16_f32_e32 v12, v125159; SI-NEXT:    v_cvt_f16_f32_e32 v16, v165160; SI-NEXT:    v_or_b32_e32 v10, v10, v225161; SI-NEXT:    v_lshlrev_b32_e32 v22, 16, v75162; SI-NEXT:    v_or_b32_e32 v6, v6, v225163; SI-NEXT:    v_lshlrev_b32_e32 v22, 16, v35164; SI-NEXT:    v_or_b32_e32 v2, v2, v225165; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v15166; SI-NEXT:    v_lshlrev_b32_e32 v5, 16, v55167; SI-NEXT:    v_lshlrev_b32_e32 v9, 16, v95168; SI-NEXT:    v_lshlrev_b32_e32 v13, 16, v135169; SI-NEXT:    v_lshlrev_b32_e32 v17, 16, v175170; SI-NEXT:    v_or_b32_e32 v0, v0, v15171; SI-NEXT:    v_or_b32_e32 v4, v4, v55172; SI-NEXT:    v_or_b32_e32 v8, v8, v95173; SI-NEXT:    v_or_b32_e32 v12, v12, v135174; SI-NEXT:    v_or_b32_e32 v16, v16, v175175; SI-NEXT:    v_alignbit_b32 v1, v2, v1, 165176; SI-NEXT:    v_alignbit_b32 v5, v6, v5, 165177; SI-NEXT:    v_alignbit_b32 v9, v10, v9, 165178; SI-NEXT:    v_alignbit_b32 v13, v14, v13, 165179; SI-NEXT:    v_alignbit_b32 v17, v18, v17, 165180; SI-NEXT:  .LBB22_2: ; %end5181; SI-NEXT:    s_or_b64 exec, exec, s[4:5]5182; SI-NEXT:    s_setpc_b64 s[30:31]5183;5184; VI-LABEL: bitcast_v22f16_to_v22i16:5185; VI:       ; %bb.0:5186; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5187; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v115188; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc5189; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]5190; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]5191; VI-NEXT:    s_cbranch_execz .LBB22_25192; VI-NEXT:  ; %bb.1: ; %cmp.true5193; VI-NEXT:    v_mov_b32_e32 v12, 0x2005194; VI-NEXT:    v_add_f16_e32 v19, 0x200, v105195; VI-NEXT:    v_add_f16_sdwa v10, v10, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD5196; VI-NEXT:    v_or_b32_e32 v10, v19, v105197; VI-NEXT:    v_add_f16_e32 v19, 0x200, v95198; VI-NEXT:    v_add_f16_sdwa v9, v9, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD5199; VI-NEXT:    v_add_f16_e32 v11, 0x200, v05200; VI-NEXT:    v_add_f16_sdwa v0, v0, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD5201; VI-NEXT:    v_add_f16_e32 v13, 0x200, v15202; VI-NEXT:    v_add_f16_sdwa v1, v1, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD5203; VI-NEXT:    v_add_f16_e32 v14, 0x200, v25204; VI-NEXT:    v_add_f16_sdwa v2, v2, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD5205; VI-NEXT:    v_add_f16_e32 v15, 0x200, v35206; VI-NEXT:    v_add_f16_sdwa v3, v3, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD5207; VI-NEXT:    v_add_f16_e32 v16, 0x200, v45208; VI-NEXT:    v_add_f16_sdwa v4, v4, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD5209; VI-NEXT:    v_add_f16_e32 v17, 0x200, v55210; VI-NEXT:    v_add_f16_sdwa v5, v5, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD5211; VI-NEXT:    v_add_f16_e32 v18, 0x200, v65212; VI-NEXT:    v_add_f16_sdwa v6, v6, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD5213; VI-NEXT:    v_or_b32_e32 v9, v19, v95214; VI-NEXT:    v_add_f16_e32 v19, 0x200, v75215; VI-NEXT:    v_add_f16_sdwa v7, v7, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD5216; VI-NEXT:    v_add_f16_sdwa v12, v8, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD5217; VI-NEXT:    v_add_f16_e32 v8, 0x200, v85218; VI-NEXT:    v_or_b32_e32 v8, v8, v125219; VI-NEXT:    v_or_b32_e32 v7, v19, v75220; VI-NEXT:    v_or_b32_e32 v6, v18, v65221; VI-NEXT:    v_or_b32_e32 v5, v17, v55222; VI-NEXT:    v_or_b32_e32 v4, v16, v45223; VI-NEXT:    v_or_b32_e32 v3, v15, v35224; VI-NEXT:    v_or_b32_e32 v2, v14, v25225; VI-NEXT:    v_or_b32_e32 v1, v13, v15226; VI-NEXT:    v_or_b32_e32 v0, v11, v05227; VI-NEXT:  .LBB22_2: ; %end5228; VI-NEXT:    s_or_b64 exec, exec, s[4:5]5229; VI-NEXT:    s_setpc_b64 s[30:31]5230;5231; GFX9-LABEL: bitcast_v22f16_to_v22i16:5232; GFX9:       ; %bb.0:5233; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5234; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v115235; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc5236; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]5237; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]5238; GFX9-NEXT:    s_cbranch_execz .LBB22_25239; GFX9-NEXT:  ; %bb.1: ; %cmp.true5240; GFX9-NEXT:    s_movk_i32 s6, 0x2005241; GFX9-NEXT:    v_pk_add_f16 v10, v10, s6 op_sel_hi:[1,0]5242; GFX9-NEXT:    v_pk_add_f16 v9, v9, s6 op_sel_hi:[1,0]5243; GFX9-NEXT:    v_pk_add_f16 v8, v8, s6 op_sel_hi:[1,0]5244; GFX9-NEXT:    v_pk_add_f16 v7, v7, s6 op_sel_hi:[1,0]5245; GFX9-NEXT:    v_pk_add_f16 v6, v6, s6 op_sel_hi:[1,0]5246; GFX9-NEXT:    v_pk_add_f16 v5, v5, s6 op_sel_hi:[1,0]5247; GFX9-NEXT:    v_pk_add_f16 v4, v4, s6 op_sel_hi:[1,0]5248; GFX9-NEXT:    v_pk_add_f16 v3, v3, s6 op_sel_hi:[1,0]5249; GFX9-NEXT:    v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]5250; GFX9-NEXT:    v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]5251; GFX9-NEXT:    v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]5252; GFX9-NEXT:  .LBB22_2: ; %end5253; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]5254; GFX9-NEXT:    s_setpc_b64 s[30:31]5255;5256; GFX11-LABEL: bitcast_v22f16_to_v22i16:5257; GFX11:       ; %bb.0:5258; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5259; GFX11-NEXT:    s_mov_b32 s0, exec_lo5260; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v115261; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s05262; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)5263; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s05264; GFX11-NEXT:    s_cbranch_execz .LBB22_25265; GFX11-NEXT:  ; %bb.1: ; %cmp.true5266; GFX11-NEXT:    v_pk_add_f16 v10, 0x200, v10 op_sel_hi:[0,1]5267; GFX11-NEXT:    v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1]5268; GFX11-NEXT:    v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1]5269; GFX11-NEXT:    v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]5270; GFX11-NEXT:    v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]5271; GFX11-NEXT:    v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]5272; GFX11-NEXT:    v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]5273; GFX11-NEXT:    v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]5274; GFX11-NEXT:    v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]5275; GFX11-NEXT:    v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]5276; GFX11-NEXT:    v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]5277; GFX11-NEXT:  .LBB22_2: ; %end5278; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s05279; GFX11-NEXT:    s_setpc_b64 s[30:31]5280  %cmp = icmp eq i32 %b, 05281  br i1 %cmp, label %cmp.true, label %cmp.false5282 5283cmp.true:5284  %a1 = fadd <22 x half> %a, splat (half 0xH0200)5285  %a2 = bitcast <22 x half> %a1 to <22 x i16>5286  br label %end5287 5288cmp.false:5289  %a3 = bitcast <22 x half> %a to <22 x i16>5290  br label %end5291 5292end:5293  %phi = phi <22 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]5294  ret <22 x i16> %phi5295}5296 5297define inreg <22 x i16> @bitcast_v22f16_to_v22i16_scalar(<22 x half> inreg %a, i32 inreg %b) {5298; SI-LABEL: bitcast_v22f16_to_v22i16_scalar:5299; SI:       ; %bb.0:5300; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5301; SI-NEXT:    v_mov_b32_e32 v9, v75302; SI-NEXT:    v_mov_b32_e32 v10, v45303; SI-NEXT:    v_mov_b32_e32 v13, v35304; SI-NEXT:    v_mov_b32_e32 v14, v05305; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v85306; SI-NEXT:    v_cvt_f16_f32_e32 v0, s165307; SI-NEXT:    v_cvt_f16_f32_e32 v23, s175308; SI-NEXT:    v_cvt_f16_f32_e32 v3, s195309; SI-NEXT:    v_cvt_f16_f32_e32 v4, s205310; SI-NEXT:    v_cvt_f16_f32_e32 v7, s235311; SI-NEXT:    v_cvt_f16_f32_e32 v8, s245312; SI-NEXT:    v_cvt_f16_f32_e32 v11, s275313; SI-NEXT:    v_cvt_f16_f32_e32 v12, s285314; SI-NEXT:    v_cvt_f16_f32_e32 v14, v145315; SI-NEXT:    v_cvt_f16_f32_e32 v15, v15316; SI-NEXT:    v_cvt_f16_f32_e32 v16, v25317; SI-NEXT:    v_cvt_f16_f32_e32 v27, v135318; SI-NEXT:    v_cvt_f16_f32_e32 v18, v105319; SI-NEXT:    v_cvt_f16_f32_e32 v19, v55320; SI-NEXT:    v_cvt_f16_f32_e32 v20, v65321; SI-NEXT:    v_cvt_f16_f32_e32 v21, v95322; SI-NEXT:    v_cvt_f16_f32_e32 v2, s185323; SI-NEXT:    v_cvt_f16_f32_e32 v24, s215324; SI-NEXT:    v_cvt_f16_f32_e32 v6, s225325; SI-NEXT:    v_cvt_f16_f32_e32 v25, s255326; SI-NEXT:    v_cvt_f16_f32_e32 v10, s265327; SI-NEXT:    v_cvt_f16_f32_e32 v26, s295328; SI-NEXT:    s_and_b64 s[4:5], vcc, exec5329; SI-NEXT:    s_cbranch_scc0 .LBB23_45330; SI-NEXT:  ; %bb.1: ; %cmp.false5331; SI-NEXT:    s_cbranch_execnz .LBB23_35332; SI-NEXT:  .LBB23_2: ; %cmp.true5333; SI-NEXT:    v_cvt_f32_f16_e32 v3, v35334; SI-NEXT:    v_cvt_f32_f16_e32 v2, v25335; SI-NEXT:    v_cvt_f32_f16_e32 v7, v75336; SI-NEXT:    v_cvt_f32_f16_e32 v6, v65337; SI-NEXT:    v_cvt_f32_f16_e32 v11, v115338; SI-NEXT:    v_cvt_f32_f16_e32 v10, v105339; SI-NEXT:    v_cvt_f32_f16_e32 v15, v155340; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v35341; SI-NEXT:    v_cvt_f32_f16_e32 v14, v145342; SI-NEXT:    v_cvt_f16_f32_e32 v3, v35343; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v25344; SI-NEXT:    v_add_f32_e32 v7, 0x38000000, v75345; SI-NEXT:    v_cvt_f16_f32_e32 v2, v25346; SI-NEXT:    v_cvt_f16_f32_e32 v7, v75347; SI-NEXT:    v_add_f32_e32 v6, 0x38000000, v65348; SI-NEXT:    v_add_f32_e32 v11, 0x38000000, v115349; SI-NEXT:    v_cvt_f16_f32_e32 v6, v65350; SI-NEXT:    v_cvt_f16_f32_e32 v11, v115351; SI-NEXT:    v_add_f32_e32 v10, 0x38000000, v105352; SI-NEXT:    v_add_f32_e32 v15, 0x38000000, v155353; SI-NEXT:    v_cvt_f16_f32_e32 v10, v105354; SI-NEXT:    v_cvt_f16_f32_e32 v15, v155355; SI-NEXT:    v_add_f32_e32 v14, 0x38000000, v145356; SI-NEXT:    v_cvt_f32_f16_e32 v1, v235357; SI-NEXT:    v_lshlrev_b32_e32 v5, 16, v35358; SI-NEXT:    v_cvt_f16_f32_e32 v14, v145359; SI-NEXT:    v_or_b32_e32 v2, v2, v55360; SI-NEXT:    v_cvt_f32_f16_e32 v5, v245361; SI-NEXT:    v_lshlrev_b32_e32 v9, 16, v75362; SI-NEXT:    v_or_b32_e32 v6, v6, v95363; SI-NEXT:    v_cvt_f32_f16_e32 v9, v255364; SI-NEXT:    v_lshlrev_b32_e32 v13, 16, v115365; SI-NEXT:    v_or_b32_e32 v10, v10, v135366; SI-NEXT:    v_cvt_f32_f16_e32 v13, v265367; SI-NEXT:    v_lshlrev_b32_e32 v17, 16, v155368; SI-NEXT:    v_cvt_f32_f16_e32 v19, v195369; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v15370; SI-NEXT:    v_or_b32_e32 v14, v14, v175371; SI-NEXT:    v_cvt_f32_f16_e32 v17, v275372; SI-NEXT:    v_cvt_f32_f16_e32 v18, v185373; SI-NEXT:    v_cvt_f16_f32_e32 v1, v15374; SI-NEXT:    v_add_f32_e32 v5, 0x38000000, v55375; SI-NEXT:    v_cvt_f32_f16_e32 v21, v215376; SI-NEXT:    v_cvt_f16_f32_e32 v5, v55377; SI-NEXT:    v_add_f32_e32 v9, 0x38000000, v95378; SI-NEXT:    v_cvt_f32_f16_e32 v20, v205379; SI-NEXT:    v_cvt_f32_f16_e32 v0, v05380; SI-NEXT:    v_cvt_f32_f16_e32 v4, v45381; SI-NEXT:    v_cvt_f32_f16_e32 v8, v85382; SI-NEXT:    v_cvt_f32_f16_e32 v12, v125383; SI-NEXT:    v_cvt_f32_f16_e32 v16, v165384; SI-NEXT:    v_cvt_f16_f32_e32 v9, v95385; SI-NEXT:    v_add_f32_e32 v13, 0x38000000, v135386; SI-NEXT:    v_add_f32_e32 v19, 0x38000000, v195387; SI-NEXT:    v_cvt_f16_f32_e32 v13, v135388; SI-NEXT:    v_add_f32_e32 v17, 0x38000000, v175389; SI-NEXT:    v_cvt_f16_f32_e32 v19, v195390; SI-NEXT:    v_add_f32_e32 v18, 0x38000000, v185391; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v15392; SI-NEXT:    v_cvt_f16_f32_e32 v18, v185393; SI-NEXT:    v_cvt_f16_f32_e32 v17, v175394; SI-NEXT:    v_add_f32_e32 v21, 0x38000000, v215395; SI-NEXT:    v_lshlrev_b32_e32 v5, 16, v55396; SI-NEXT:    v_cvt_f16_f32_e32 v21, v215397; SI-NEXT:    v_add_f32_e32 v20, 0x38000000, v205398; SI-NEXT:    v_add_f32_e32 v0, 0x38000000, v05399; SI-NEXT:    v_add_f32_e32 v4, 0x38000000, v45400; SI-NEXT:    v_add_f32_e32 v8, 0x38000000, v85401; SI-NEXT:    v_add_f32_e32 v12, 0x38000000, v125402; SI-NEXT:    v_add_f32_e32 v16, 0x38000000, v165403; SI-NEXT:    v_lshr_b64 v[23:24], v[1:2], 165404; SI-NEXT:    v_lshlrev_b32_e32 v9, 16, v95405; SI-NEXT:    v_cvt_f16_f32_e32 v20, v205406; SI-NEXT:    v_cvt_f16_f32_e32 v0, v05407; SI-NEXT:    v_cvt_f16_f32_e32 v4, v45408; SI-NEXT:    v_cvt_f16_f32_e32 v8, v85409; SI-NEXT:    v_cvt_f16_f32_e32 v12, v125410; SI-NEXT:    v_cvt_f16_f32_e32 v16, v165411; SI-NEXT:    v_lshr_b64 v[24:25], v[5:6], 165412; SI-NEXT:    v_lshlrev_b32_e32 v13, 16, v135413; SI-NEXT:    v_lshlrev_b32_e32 v22, 16, v195414; SI-NEXT:    v_lshr_b64 v[25:26], v[9:10], 165415; SI-NEXT:    v_or_b32_e32 v18, v18, v225416; SI-NEXT:    v_lshlrev_b32_e32 v17, 16, v175417; SI-NEXT:    v_lshr_b64 v[26:27], v[13:14], 165418; SI-NEXT:    v_lshlrev_b32_e32 v22, 16, v215419; SI-NEXT:    v_lshr_b64 v[27:28], v[17:18], 165420; SI-NEXT:    v_or_b32_e32 v20, v20, v225421; SI-NEXT:    v_or_b32_e32 v0, v0, v15422; SI-NEXT:    v_or_b32_e32 v4, v4, v55423; SI-NEXT:    v_or_b32_e32 v8, v8, v95424; SI-NEXT:    v_or_b32_e32 v12, v12, v135425; SI-NEXT:    v_or_b32_e32 v16, v16, v175426; SI-NEXT:  .LBB23_3: ; %end5427; SI-NEXT:    v_mov_b32_e32 v1, v235428; SI-NEXT:    v_mov_b32_e32 v5, v245429; SI-NEXT:    v_mov_b32_e32 v9, v255430; SI-NEXT:    v_mov_b32_e32 v13, v265431; SI-NEXT:    v_mov_b32_e32 v17, v275432; SI-NEXT:    s_setpc_b64 s[30:31]5433; SI-NEXT:  .LBB23_4:5434; SI-NEXT:    s_branch .LBB23_25435;5436; VI-LABEL: bitcast_v22f16_to_v22i16_scalar:5437; VI:       ; %bb.0:5438; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5439; VI-NEXT:    s_cmp_lg_u32 s27, 05440; VI-NEXT:    s_cbranch_scc0 .LBB23_35441; VI-NEXT:  ; %bb.1: ; %cmp.false5442; VI-NEXT:    s_cbranch_execnz .LBB23_45443; VI-NEXT:  .LBB23_2: ; %cmp.true5444; VI-NEXT:    s_lshr_b32 s5, s25, 165445; VI-NEXT:    v_mov_b32_e32 v0, 0x2005446; VI-NEXT:    v_mov_b32_e32 v2, s55447; VI-NEXT:    s_lshr_b32 s5, s26, 165448; VI-NEXT:    v_add_f16_e32 v1, s25, v05449; VI-NEXT:    v_add_f16_sdwa v2, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD5450; VI-NEXT:    v_mov_b32_e32 v4, s55451; VI-NEXT:    s_lshr_b32 s5, s24, 165452; VI-NEXT:    v_or_b32_e32 v9, v1, v25453; VI-NEXT:    v_mov_b32_e32 v2, s55454; VI-NEXT:    v_add_f16_e32 v1, s24, v05455; VI-NEXT:    v_add_f16_sdwa v2, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD5456; VI-NEXT:    s_lshr_b32 s5, s23, 165457; VI-NEXT:    v_or_b32_e32 v8, v1, v25458; VI-NEXT:    v_mov_b32_e32 v2, s55459; VI-NEXT:    v_add_f16_e32 v1, s23, v05460; VI-NEXT:    v_add_f16_sdwa v2, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD5461; VI-NEXT:    s_lshr_b32 s5, s22, 165462; VI-NEXT:    v_or_b32_e32 v7, v1, v25463; VI-NEXT:    v_mov_b32_e32 v2, s55464; VI-NEXT:    v_add_f16_e32 v1, s22, v05465; VI-NEXT:    v_add_f16_sdwa v2, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD5466; VI-NEXT:    s_lshr_b32 s5, s21, 165467; VI-NEXT:    v_or_b32_e32 v6, v1, v25468; VI-NEXT:    v_mov_b32_e32 v2, s55469; VI-NEXT:    v_add_f16_e32 v1, s21, v05470; VI-NEXT:    v_add_f16_sdwa v2, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD5471; VI-NEXT:    s_lshr_b32 s5, s20, 165472; VI-NEXT:    v_or_b32_e32 v5, v1, v25473; VI-NEXT:    v_mov_b32_e32 v2, s55474; VI-NEXT:    v_add_f16_e32 v3, s26, v05475; VI-NEXT:    v_add_f16_sdwa v4, v4, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD5476; VI-NEXT:    v_add_f16_e32 v1, s20, v05477; VI-NEXT:    v_add_f16_sdwa v2, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD5478; VI-NEXT:    s_lshr_b32 s5, s19, 165479; VI-NEXT:    v_or_b32_e32 v10, v3, v45480; VI-NEXT:    v_or_b32_e32 v4, v1, v25481; VI-NEXT:    v_mov_b32_e32 v2, s55482; VI-NEXT:    v_add_f16_e32 v1, s19, v05483; VI-NEXT:    v_add_f16_sdwa v2, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD5484; VI-NEXT:    s_lshr_b32 s5, s18, 165485; VI-NEXT:    v_or_b32_e32 v3, v1, v25486; VI-NEXT:    v_mov_b32_e32 v2, s55487; VI-NEXT:    s_lshr_b32 s4, s16, 165488; VI-NEXT:    v_add_f16_e32 v1, s18, v05489; VI-NEXT:    v_add_f16_sdwa v2, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD5490; VI-NEXT:    v_or_b32_e32 v2, v1, v25491; VI-NEXT:    v_mov_b32_e32 v1, s45492; VI-NEXT:    s_lshr_b32 s4, s17, 165493; VI-NEXT:    v_add_f16_sdwa v12, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD5494; VI-NEXT:    v_mov_b32_e32 v1, s45495; VI-NEXT:    v_add_f16_e32 v11, s16, v05496; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD5497; VI-NEXT:    v_add_f16_e32 v0, s17, v05498; VI-NEXT:    v_or_b32_e32 v1, v0, v15499; VI-NEXT:    v_or_b32_e32 v0, v11, v125500; VI-NEXT:    s_setpc_b64 s[30:31]5501; VI-NEXT:  .LBB23_3:5502; VI-NEXT:    s_branch .LBB23_25503; VI-NEXT:  .LBB23_4:5504; VI-NEXT:    v_mov_b32_e32 v0, s165505; VI-NEXT:    v_mov_b32_e32 v1, s175506; VI-NEXT:    v_mov_b32_e32 v2, s185507; VI-NEXT:    v_mov_b32_e32 v3, s195508; VI-NEXT:    v_mov_b32_e32 v4, s205509; VI-NEXT:    v_mov_b32_e32 v5, s215510; VI-NEXT:    v_mov_b32_e32 v6, s225511; VI-NEXT:    v_mov_b32_e32 v7, s235512; VI-NEXT:    v_mov_b32_e32 v8, s245513; VI-NEXT:    v_mov_b32_e32 v9, s255514; VI-NEXT:    v_mov_b32_e32 v10, s265515; VI-NEXT:    v_mov_b32_e32 v11, s275516; VI-NEXT:    v_mov_b32_e32 v12, s285517; VI-NEXT:    v_mov_b32_e32 v13, s295518; VI-NEXT:    v_mov_b32_e32 v14, s305519; VI-NEXT:    v_mov_b32_e32 v15, s315520; VI-NEXT:    s_setpc_b64 s[30:31]5521;5522; GFX9-LABEL: bitcast_v22f16_to_v22i16_scalar:5523; GFX9:       ; %bb.0:5524; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5525; GFX9-NEXT:    s_cmp_lg_u32 s27, 05526; GFX9-NEXT:    s_cbranch_scc0 .LBB23_35527; GFX9-NEXT:  ; %bb.1: ; %cmp.false5528; GFX9-NEXT:    s_cbranch_execnz .LBB23_45529; GFX9-NEXT:  .LBB23_2: ; %cmp.true5530; GFX9-NEXT:    v_mov_b32_e32 v0, 0x2005531; GFX9-NEXT:    v_pk_add_f16 v10, s26, v0 op_sel_hi:[1,0]5532; GFX9-NEXT:    v_pk_add_f16 v9, s25, v0 op_sel_hi:[1,0]5533; GFX9-NEXT:    v_pk_add_f16 v8, s24, v0 op_sel_hi:[1,0]5534; GFX9-NEXT:    v_pk_add_f16 v7, s23, v0 op_sel_hi:[1,0]5535; GFX9-NEXT:    v_pk_add_f16 v6, s22, v0 op_sel_hi:[1,0]5536; GFX9-NEXT:    v_pk_add_f16 v5, s21, v0 op_sel_hi:[1,0]5537; GFX9-NEXT:    v_pk_add_f16 v4, s20, v0 op_sel_hi:[1,0]5538; GFX9-NEXT:    v_pk_add_f16 v3, s19, v0 op_sel_hi:[1,0]5539; GFX9-NEXT:    v_pk_add_f16 v2, s18, v0 op_sel_hi:[1,0]5540; GFX9-NEXT:    v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]5541; GFX9-NEXT:    v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]5542; GFX9-NEXT:    s_setpc_b64 s[30:31]5543; GFX9-NEXT:  .LBB23_3:5544; GFX9-NEXT:    s_branch .LBB23_25545; GFX9-NEXT:  .LBB23_4:5546; GFX9-NEXT:    v_mov_b32_e32 v0, s165547; GFX9-NEXT:    v_mov_b32_e32 v1, s175548; GFX9-NEXT:    v_mov_b32_e32 v2, s185549; GFX9-NEXT:    v_mov_b32_e32 v3, s195550; GFX9-NEXT:    v_mov_b32_e32 v4, s205551; GFX9-NEXT:    v_mov_b32_e32 v5, s215552; GFX9-NEXT:    v_mov_b32_e32 v6, s225553; GFX9-NEXT:    v_mov_b32_e32 v7, s235554; GFX9-NEXT:    v_mov_b32_e32 v8, s245555; GFX9-NEXT:    v_mov_b32_e32 v9, s255556; GFX9-NEXT:    v_mov_b32_e32 v10, s265557; GFX9-NEXT:    v_mov_b32_e32 v11, s275558; GFX9-NEXT:    v_mov_b32_e32 v12, s285559; GFX9-NEXT:    v_mov_b32_e32 v13, s295560; GFX9-NEXT:    v_mov_b32_e32 v14, s305561; GFX9-NEXT:    v_mov_b32_e32 v15, s315562; GFX9-NEXT:    s_setpc_b64 s[30:31]5563;5564; GFX11-LABEL: bitcast_v22f16_to_v22i16_scalar:5565; GFX11:       ; %bb.0:5566; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5567; GFX11-NEXT:    s_mov_b32 s15, s35568; GFX11-NEXT:    s_mov_b32 s14, s25569; GFX11-NEXT:    s_mov_b32 s13, s15570; GFX11-NEXT:    s_mov_b32 s12, s05571; GFX11-NEXT:    s_cmp_lg_u32 s23, 05572; GFX11-NEXT:    s_mov_b32 s0, 05573; GFX11-NEXT:    s_cbranch_scc0 .LBB23_35574; GFX11-NEXT:  ; %bb.1: ; %Flow5575; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s05576; GFX11-NEXT:    s_cbranch_vccnz .LBB23_45577; GFX11-NEXT:  .LBB23_2: ; %cmp.true5578; GFX11-NEXT:    v_pk_add_f16 v10, 0x200, s22 op_sel_hi:[0,1]5579; GFX11-NEXT:    v_pk_add_f16 v9, 0x200, s21 op_sel_hi:[0,1]5580; GFX11-NEXT:    v_pk_add_f16 v8, 0x200, s20 op_sel_hi:[0,1]5581; GFX11-NEXT:    v_pk_add_f16 v7, 0x200, s19 op_sel_hi:[0,1]5582; GFX11-NEXT:    v_pk_add_f16 v6, 0x200, s18 op_sel_hi:[0,1]5583; GFX11-NEXT:    v_pk_add_f16 v5, 0x200, s17 op_sel_hi:[0,1]5584; GFX11-NEXT:    v_pk_add_f16 v4, 0x200, s16 op_sel_hi:[0,1]5585; GFX11-NEXT:    v_pk_add_f16 v3, 0x200, s15 op_sel_hi:[0,1]5586; GFX11-NEXT:    v_pk_add_f16 v2, 0x200, s14 op_sel_hi:[0,1]5587; GFX11-NEXT:    v_pk_add_f16 v1, 0x200, s13 op_sel_hi:[0,1]5588; GFX11-NEXT:    v_pk_add_f16 v0, 0x200, s12 op_sel_hi:[0,1]5589; GFX11-NEXT:    s_setpc_b64 s[30:31]5590; GFX11-NEXT:  .LBB23_3:5591; GFX11-NEXT:    s_branch .LBB23_25592; GFX11-NEXT:  .LBB23_4:5593; GFX11-NEXT:    v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s135594; GFX11-NEXT:    v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s155595; GFX11-NEXT:    v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s175596; GFX11-NEXT:    v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s195597; GFX11-NEXT:    v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s215598; GFX11-NEXT:    v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s235599; GFX11-NEXT:    v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s255600; GFX11-NEXT:    v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s275601; GFX11-NEXT:    s_setpc_b64 s[30:31]5602  %cmp = icmp eq i32 %b, 05603  br i1 %cmp, label %cmp.true, label %cmp.false5604 5605cmp.true:5606  %a1 = fadd <22 x half> %a, splat (half 0xH0200)5607  %a2 = bitcast <22 x half> %a1 to <22 x i16>5608  br label %end5609 5610cmp.false:5611  %a3 = bitcast <22 x half> %a to <22 x i16>5612  br label %end5613 5614end:5615  %phi = phi <22 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]5616  ret <22 x i16> %phi5617}5618;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:5619; GFX11-FAKE16: {{.*}}5620; GFX11-TRUE16: {{.*}}5621