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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52 3; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=SI %s4; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=VI %s5; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s6; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s7; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s8 9define <14 x float> @bitcast_v14i32_to_v14f32(<14 x i32> %a, i32 %b) {10; SI-LABEL: bitcast_v14i32_to_v14f32:11; SI: ; %bb.0:12; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)13; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1414; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc15; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]16; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]17; SI-NEXT: s_cbranch_execz .LBB0_218; SI-NEXT: ; %bb.1: ; %cmp.true19; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v1320; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v1221; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v1122; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v1023; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v924; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v825; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v726; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v627; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v528; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v429; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v330; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v231; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v132; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v033; SI-NEXT: .LBB0_2: ; %end34; SI-NEXT: s_or_b64 exec, exec, s[4:5]35; SI-NEXT: s_setpc_b64 s[30:31]36;37; VI-LABEL: bitcast_v14i32_to_v14f32:38; VI: ; %bb.0:39; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)40; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1441; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc42; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]43; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]44; VI-NEXT: s_cbranch_execz .LBB0_245; VI-NEXT: ; %bb.1: ; %cmp.true46; VI-NEXT: v_add_u32_e32 v13, vcc, 3, v1347; VI-NEXT: v_add_u32_e32 v12, vcc, 3, v1248; VI-NEXT: v_add_u32_e32 v11, vcc, 3, v1149; VI-NEXT: v_add_u32_e32 v10, vcc, 3, v1050; VI-NEXT: v_add_u32_e32 v9, vcc, 3, v951; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v852; VI-NEXT: v_add_u32_e32 v7, vcc, 3, v753; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v654; VI-NEXT: v_add_u32_e32 v5, vcc, 3, v555; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v456; VI-NEXT: v_add_u32_e32 v3, vcc, 3, v357; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v258; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v159; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v060; VI-NEXT: .LBB0_2: ; %end61; VI-NEXT: s_or_b64 exec, exec, s[4:5]62; VI-NEXT: s_setpc_b64 s[30:31]63;64; GFX9-LABEL: bitcast_v14i32_to_v14f32:65; GFX9: ; %bb.0:66; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)67; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1468; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc69; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]70; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]71; GFX9-NEXT: s_cbranch_execz .LBB0_272; GFX9-NEXT: ; %bb.1: ; %cmp.true73; GFX9-NEXT: v_add_u32_e32 v13, 3, v1374; GFX9-NEXT: v_add_u32_e32 v12, 3, v1275; GFX9-NEXT: v_add_u32_e32 v11, 3, v1176; GFX9-NEXT: v_add_u32_e32 v10, 3, v1077; GFX9-NEXT: v_add_u32_e32 v9, 3, v978; GFX9-NEXT: v_add_u32_e32 v8, 3, v879; GFX9-NEXT: v_add_u32_e32 v7, 3, v780; GFX9-NEXT: v_add_u32_e32 v6, 3, v681; GFX9-NEXT: v_add_u32_e32 v5, 3, v582; GFX9-NEXT: v_add_u32_e32 v4, 3, v483; GFX9-NEXT: v_add_u32_e32 v3, 3, v384; GFX9-NEXT: v_add_u32_e32 v2, 3, v285; GFX9-NEXT: v_add_u32_e32 v1, 3, v186; GFX9-NEXT: v_add_u32_e32 v0, 3, v087; GFX9-NEXT: .LBB0_2: ; %end88; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]89; GFX9-NEXT: s_setpc_b64 s[30:31]90;91; GFX11-LABEL: bitcast_v14i32_to_v14f32:92; GFX11: ; %bb.0:93; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)94; GFX11-NEXT: s_mov_b32 s0, exec_lo95; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v1496; GFX11-NEXT: s_xor_b32 s0, exec_lo, s097; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)98; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s099; GFX11-NEXT: s_cbranch_execz .LBB0_2100; GFX11-NEXT: ; %bb.1: ; %cmp.true101; GFX11-NEXT: v_add_nc_u32_e32 v13, 3, v13102; GFX11-NEXT: v_add_nc_u32_e32 v12, 3, v12103; GFX11-NEXT: v_add_nc_u32_e32 v11, 3, v11104; GFX11-NEXT: v_add_nc_u32_e32 v10, 3, v10105; GFX11-NEXT: v_add_nc_u32_e32 v9, 3, v9106; GFX11-NEXT: v_add_nc_u32_e32 v8, 3, v8107; GFX11-NEXT: v_add_nc_u32_e32 v7, 3, v7108; GFX11-NEXT: v_add_nc_u32_e32 v6, 3, v6109; GFX11-NEXT: v_add_nc_u32_e32 v5, 3, v5110; GFX11-NEXT: v_add_nc_u32_e32 v4, 3, v4111; GFX11-NEXT: v_add_nc_u32_e32 v3, 3, v3112; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2113; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1114; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0115; GFX11-NEXT: .LBB0_2: ; %end116; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0117; GFX11-NEXT: s_setpc_b64 s[30:31]118 %cmp = icmp eq i32 %b, 0119 br i1 %cmp, label %cmp.true, label %cmp.false120 121cmp.true:122 %a1 = add <14 x i32> %a, splat (i32 3)123 %a2 = bitcast <14 x i32> %a1 to <14 x float>124 br label %end125 126cmp.false:127 %a3 = bitcast <14 x i32> %a to <14 x float>128 br label %end129 130end:131 %phi = phi <14 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]132 ret <14 x float> %phi133}134 135define inreg <14 x float> @bitcast_v14i32_to_v14f32_scalar(<14 x i32> inreg %a, i32 inreg %b) {136; SI-LABEL: bitcast_v14i32_to_v14f32_scalar:137; SI: ; %bb.0:138; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)139; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0140; SI-NEXT: s_and_b64 s[4:5], vcc, exec141; SI-NEXT: s_cbranch_scc0 .LBB1_4142; SI-NEXT: ; %bb.1: ; %cmp.false143; SI-NEXT: s_cbranch_execnz .LBB1_3144; SI-NEXT: .LBB1_2: ; %cmp.true145; SI-NEXT: s_add_i32 s29, s29, 3146; SI-NEXT: s_add_i32 s28, s28, 3147; SI-NEXT: s_add_i32 s27, s27, 3148; SI-NEXT: s_add_i32 s26, s26, 3149; SI-NEXT: s_add_i32 s25, s25, 3150; SI-NEXT: s_add_i32 s24, s24, 3151; SI-NEXT: s_add_i32 s23, s23, 3152; SI-NEXT: s_add_i32 s22, s22, 3153; SI-NEXT: s_add_i32 s21, s21, 3154; SI-NEXT: s_add_i32 s20, s20, 3155; SI-NEXT: s_add_i32 s19, s19, 3156; SI-NEXT: s_add_i32 s18, s18, 3157; SI-NEXT: s_add_i32 s17, s17, 3158; SI-NEXT: s_add_i32 s16, s16, 3159; SI-NEXT: .LBB1_3: ; %end160; SI-NEXT: v_mov_b32_e32 v0, s16161; SI-NEXT: v_mov_b32_e32 v1, s17162; SI-NEXT: v_mov_b32_e32 v2, s18163; SI-NEXT: v_mov_b32_e32 v3, s19164; SI-NEXT: v_mov_b32_e32 v4, s20165; SI-NEXT: v_mov_b32_e32 v5, s21166; SI-NEXT: v_mov_b32_e32 v6, s22167; SI-NEXT: v_mov_b32_e32 v7, s23168; SI-NEXT: v_mov_b32_e32 v8, s24169; SI-NEXT: v_mov_b32_e32 v9, s25170; SI-NEXT: v_mov_b32_e32 v10, s26171; SI-NEXT: v_mov_b32_e32 v11, s27172; SI-NEXT: v_mov_b32_e32 v12, s28173; SI-NEXT: v_mov_b32_e32 v13, s29174; SI-NEXT: s_setpc_b64 s[30:31]175; SI-NEXT: .LBB1_4:176; SI-NEXT: s_branch .LBB1_2177;178; VI-LABEL: bitcast_v14i32_to_v14f32_scalar:179; VI: ; %bb.0:180; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)181; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0182; VI-NEXT: s_and_b64 s[4:5], vcc, exec183; VI-NEXT: s_cbranch_scc0 .LBB1_4184; VI-NEXT: ; %bb.1: ; %cmp.false185; VI-NEXT: s_cbranch_execnz .LBB1_3186; VI-NEXT: .LBB1_2: ; %cmp.true187; VI-NEXT: s_add_i32 s29, s29, 3188; VI-NEXT: s_add_i32 s28, s28, 3189; VI-NEXT: s_add_i32 s27, s27, 3190; VI-NEXT: s_add_i32 s26, s26, 3191; VI-NEXT: s_add_i32 s25, s25, 3192; VI-NEXT: s_add_i32 s24, s24, 3193; VI-NEXT: s_add_i32 s23, s23, 3194; VI-NEXT: s_add_i32 s22, s22, 3195; VI-NEXT: s_add_i32 s21, s21, 3196; VI-NEXT: s_add_i32 s20, s20, 3197; VI-NEXT: s_add_i32 s19, s19, 3198; VI-NEXT: s_add_i32 s18, s18, 3199; VI-NEXT: s_add_i32 s17, s17, 3200; VI-NEXT: s_add_i32 s16, s16, 3201; VI-NEXT: .LBB1_3: ; %end202; VI-NEXT: v_mov_b32_e32 v0, s16203; VI-NEXT: v_mov_b32_e32 v1, s17204; VI-NEXT: v_mov_b32_e32 v2, s18205; VI-NEXT: v_mov_b32_e32 v3, s19206; VI-NEXT: v_mov_b32_e32 v4, s20207; VI-NEXT: v_mov_b32_e32 v5, s21208; VI-NEXT: v_mov_b32_e32 v6, s22209; VI-NEXT: v_mov_b32_e32 v7, s23210; VI-NEXT: v_mov_b32_e32 v8, s24211; VI-NEXT: v_mov_b32_e32 v9, s25212; VI-NEXT: v_mov_b32_e32 v10, s26213; VI-NEXT: v_mov_b32_e32 v11, s27214; VI-NEXT: v_mov_b32_e32 v12, s28215; VI-NEXT: v_mov_b32_e32 v13, s29216; VI-NEXT: s_setpc_b64 s[30:31]217; VI-NEXT: .LBB1_4:218; VI-NEXT: s_branch .LBB1_2219;220; GFX9-LABEL: bitcast_v14i32_to_v14f32_scalar:221; GFX9: ; %bb.0:222; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)223; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0224; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec225; GFX9-NEXT: s_cbranch_scc0 .LBB1_4226; GFX9-NEXT: ; %bb.1: ; %cmp.false227; GFX9-NEXT: s_cbranch_execnz .LBB1_3228; GFX9-NEXT: .LBB1_2: ; %cmp.true229; GFX9-NEXT: s_add_i32 s29, s29, 3230; GFX9-NEXT: s_add_i32 s28, s28, 3231; GFX9-NEXT: s_add_i32 s27, s27, 3232; GFX9-NEXT: s_add_i32 s26, s26, 3233; GFX9-NEXT: s_add_i32 s25, s25, 3234; GFX9-NEXT: s_add_i32 s24, s24, 3235; GFX9-NEXT: s_add_i32 s23, s23, 3236; GFX9-NEXT: s_add_i32 s22, s22, 3237; GFX9-NEXT: s_add_i32 s21, s21, 3238; GFX9-NEXT: s_add_i32 s20, s20, 3239; GFX9-NEXT: s_add_i32 s19, s19, 3240; GFX9-NEXT: s_add_i32 s18, s18, 3241; GFX9-NEXT: s_add_i32 s17, s17, 3242; GFX9-NEXT: s_add_i32 s16, s16, 3243; GFX9-NEXT: .LBB1_3: ; %end244; GFX9-NEXT: v_mov_b32_e32 v0, s16245; GFX9-NEXT: v_mov_b32_e32 v1, s17246; GFX9-NEXT: v_mov_b32_e32 v2, s18247; GFX9-NEXT: v_mov_b32_e32 v3, s19248; GFX9-NEXT: v_mov_b32_e32 v4, s20249; GFX9-NEXT: v_mov_b32_e32 v5, s21250; GFX9-NEXT: v_mov_b32_e32 v6, s22251; GFX9-NEXT: v_mov_b32_e32 v7, s23252; GFX9-NEXT: v_mov_b32_e32 v8, s24253; GFX9-NEXT: v_mov_b32_e32 v9, s25254; GFX9-NEXT: v_mov_b32_e32 v10, s26255; GFX9-NEXT: v_mov_b32_e32 v11, s27256; GFX9-NEXT: v_mov_b32_e32 v12, s28257; GFX9-NEXT: v_mov_b32_e32 v13, s29258; GFX9-NEXT: s_setpc_b64 s[30:31]259; GFX9-NEXT: .LBB1_4:260; GFX9-NEXT: s_branch .LBB1_2261;262; GFX11-LABEL: bitcast_v14i32_to_v14f32_scalar:263; GFX11: ; %bb.0:264; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)265; GFX11-NEXT: s_cmp_lg_u32 s26, 0266; GFX11-NEXT: s_mov_b32 s4, 0267; GFX11-NEXT: s_cbranch_scc0 .LBB1_4268; GFX11-NEXT: ; %bb.1: ; %Flow269; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4270; GFX11-NEXT: s_cbranch_vccnz .LBB1_3271; GFX11-NEXT: .LBB1_2: ; %cmp.true272; GFX11-NEXT: s_add_i32 s25, s25, 3273; GFX11-NEXT: s_add_i32 s24, s24, 3274; GFX11-NEXT: s_add_i32 s23, s23, 3275; GFX11-NEXT: s_add_i32 s22, s22, 3276; GFX11-NEXT: s_add_i32 s21, s21, 3277; GFX11-NEXT: s_add_i32 s20, s20, 3278; GFX11-NEXT: s_add_i32 s19, s19, 3279; GFX11-NEXT: s_add_i32 s18, s18, 3280; GFX11-NEXT: s_add_i32 s17, s17, 3281; GFX11-NEXT: s_add_i32 s16, s16, 3282; GFX11-NEXT: s_add_i32 s3, s3, 3283; GFX11-NEXT: s_add_i32 s2, s2, 3284; GFX11-NEXT: s_add_i32 s1, s1, 3285; GFX11-NEXT: s_add_i32 s0, s0, 3286; GFX11-NEXT: .LBB1_3: ; %end287; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)288; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1289; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3290; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17291; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19292; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21293; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23294; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25295; GFX11-NEXT: s_setpc_b64 s[30:31]296; GFX11-NEXT: .LBB1_4:297; GFX11-NEXT: s_branch .LBB1_2298 %cmp = icmp eq i32 %b, 0299 br i1 %cmp, label %cmp.true, label %cmp.false300 301cmp.true:302 %a1 = add <14 x i32> %a, splat (i32 3)303 %a2 = bitcast <14 x i32> %a1 to <14 x float>304 br label %end305 306cmp.false:307 %a3 = bitcast <14 x i32> %a to <14 x float>308 br label %end309 310end:311 %phi = phi <14 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]312 ret <14 x float> %phi313}314 315define <14 x i32> @bitcast_v14f32_to_v14i32(<14 x float> %a, i32 %b) {316; SI-LABEL: bitcast_v14f32_to_v14i32:317; SI: ; %bb.0:318; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)319; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14320; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc321; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]322; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]323; SI-NEXT: s_cbranch_execz .LBB2_2324; SI-NEXT: ; %bb.1: ; %cmp.true325; SI-NEXT: v_add_f32_e32 v13, 1.0, v13326; SI-NEXT: v_add_f32_e32 v12, 1.0, v12327; SI-NEXT: v_add_f32_e32 v11, 1.0, v11328; SI-NEXT: v_add_f32_e32 v10, 1.0, v10329; SI-NEXT: v_add_f32_e32 v9, 1.0, v9330; SI-NEXT: v_add_f32_e32 v8, 1.0, v8331; SI-NEXT: v_add_f32_e32 v7, 1.0, v7332; SI-NEXT: v_add_f32_e32 v6, 1.0, v6333; SI-NEXT: v_add_f32_e32 v5, 1.0, v5334; SI-NEXT: v_add_f32_e32 v4, 1.0, v4335; SI-NEXT: v_add_f32_e32 v3, 1.0, v3336; SI-NEXT: v_add_f32_e32 v2, 1.0, v2337; SI-NEXT: v_add_f32_e32 v1, 1.0, v1338; SI-NEXT: v_add_f32_e32 v0, 1.0, v0339; SI-NEXT: .LBB2_2: ; %end340; SI-NEXT: s_or_b64 exec, exec, s[4:5]341; SI-NEXT: s_setpc_b64 s[30:31]342;343; VI-LABEL: bitcast_v14f32_to_v14i32:344; VI: ; %bb.0:345; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)346; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14347; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc348; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]349; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]350; VI-NEXT: s_cbranch_execz .LBB2_2351; VI-NEXT: ; %bb.1: ; %cmp.true352; VI-NEXT: v_add_f32_e32 v13, 1.0, v13353; VI-NEXT: v_add_f32_e32 v12, 1.0, v12354; VI-NEXT: v_add_f32_e32 v11, 1.0, v11355; VI-NEXT: v_add_f32_e32 v10, 1.0, v10356; VI-NEXT: v_add_f32_e32 v9, 1.0, v9357; VI-NEXT: v_add_f32_e32 v8, 1.0, v8358; VI-NEXT: v_add_f32_e32 v7, 1.0, v7359; VI-NEXT: v_add_f32_e32 v6, 1.0, v6360; VI-NEXT: v_add_f32_e32 v5, 1.0, v5361; VI-NEXT: v_add_f32_e32 v4, 1.0, v4362; VI-NEXT: v_add_f32_e32 v3, 1.0, v3363; VI-NEXT: v_add_f32_e32 v2, 1.0, v2364; VI-NEXT: v_add_f32_e32 v1, 1.0, v1365; VI-NEXT: v_add_f32_e32 v0, 1.0, v0366; VI-NEXT: .LBB2_2: ; %end367; VI-NEXT: s_or_b64 exec, exec, s[4:5]368; VI-NEXT: s_setpc_b64 s[30:31]369;370; GFX9-LABEL: bitcast_v14f32_to_v14i32:371; GFX9: ; %bb.0:372; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)373; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14374; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc375; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]376; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]377; GFX9-NEXT: s_cbranch_execz .LBB2_2378; GFX9-NEXT: ; %bb.1: ; %cmp.true379; GFX9-NEXT: v_add_f32_e32 v13, 1.0, v13380; GFX9-NEXT: v_add_f32_e32 v12, 1.0, v12381; GFX9-NEXT: v_add_f32_e32 v11, 1.0, v11382; GFX9-NEXT: v_add_f32_e32 v10, 1.0, v10383; GFX9-NEXT: v_add_f32_e32 v9, 1.0, v9384; GFX9-NEXT: v_add_f32_e32 v8, 1.0, v8385; GFX9-NEXT: v_add_f32_e32 v7, 1.0, v7386; GFX9-NEXT: v_add_f32_e32 v6, 1.0, v6387; GFX9-NEXT: v_add_f32_e32 v5, 1.0, v5388; GFX9-NEXT: v_add_f32_e32 v4, 1.0, v4389; GFX9-NEXT: v_add_f32_e32 v3, 1.0, v3390; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2391; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1392; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0393; GFX9-NEXT: .LBB2_2: ; %end394; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]395; GFX9-NEXT: s_setpc_b64 s[30:31]396;397; GFX11-LABEL: bitcast_v14f32_to_v14i32:398; GFX11: ; %bb.0:399; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)400; GFX11-NEXT: s_mov_b32 s0, exec_lo401; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v14402; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0403; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)404; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0405; GFX11-NEXT: s_cbranch_execz .LBB2_2406; GFX11-NEXT: ; %bb.1: ; %cmp.true407; GFX11-NEXT: v_dual_add_f32 v13, 1.0, v13 :: v_dual_add_f32 v12, 1.0, v12408; GFX11-NEXT: v_dual_add_f32 v11, 1.0, v11 :: v_dual_add_f32 v10, 1.0, v10409; GFX11-NEXT: v_dual_add_f32 v9, 1.0, v9 :: v_dual_add_f32 v8, 1.0, v8410; GFX11-NEXT: v_dual_add_f32 v7, 1.0, v7 :: v_dual_add_f32 v6, 1.0, v6411; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4412; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2413; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0414; GFX11-NEXT: .LBB2_2: ; %end415; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0416; GFX11-NEXT: s_setpc_b64 s[30:31]417 %cmp = icmp eq i32 %b, 0418 br i1 %cmp, label %cmp.true, label %cmp.false419 420cmp.true:421 %a1 = fadd <14 x float> %a, splat (float 1.000000e+00)422 %a2 = bitcast <14 x float> %a1 to <14 x i32>423 br label %end424 425cmp.false:426 %a3 = bitcast <14 x float> %a to <14 x i32>427 br label %end428 429end:430 %phi = phi <14 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]431 ret <14 x i32> %phi432}433 434define inreg <14 x i32> @bitcast_v14f32_to_v14i32_scalar(<14 x float> inreg %a, i32 inreg %b) {435; SI-LABEL: bitcast_v14f32_to_v14i32_scalar:436; SI: ; %bb.0:437; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)438; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0439; SI-NEXT: s_and_b64 s[4:5], vcc, exec440; SI-NEXT: s_cbranch_scc0 .LBB3_3441; SI-NEXT: ; %bb.1: ; %cmp.false442; SI-NEXT: s_cbranch_execnz .LBB3_4443; SI-NEXT: .LBB3_2: ; %cmp.true444; SI-NEXT: v_add_f32_e64 v13, s29, 1.0445; SI-NEXT: v_add_f32_e64 v12, s28, 1.0446; SI-NEXT: v_add_f32_e64 v11, s27, 1.0447; SI-NEXT: v_add_f32_e64 v10, s26, 1.0448; SI-NEXT: v_add_f32_e64 v9, s25, 1.0449; SI-NEXT: v_add_f32_e64 v8, s24, 1.0450; SI-NEXT: v_add_f32_e64 v7, s23, 1.0451; SI-NEXT: v_add_f32_e64 v6, s22, 1.0452; SI-NEXT: v_add_f32_e64 v5, s21, 1.0453; SI-NEXT: v_add_f32_e64 v4, s20, 1.0454; SI-NEXT: v_add_f32_e64 v3, s19, 1.0455; SI-NEXT: v_add_f32_e64 v2, s18, 1.0456; SI-NEXT: v_add_f32_e64 v1, s17, 1.0457; SI-NEXT: v_add_f32_e64 v0, s16, 1.0458; SI-NEXT: s_setpc_b64 s[30:31]459; SI-NEXT: .LBB3_3:460; SI-NEXT: s_branch .LBB3_2461; SI-NEXT: .LBB3_4:462; SI-NEXT: v_mov_b32_e32 v0, s16463; SI-NEXT: v_mov_b32_e32 v1, s17464; SI-NEXT: v_mov_b32_e32 v2, s18465; SI-NEXT: v_mov_b32_e32 v3, s19466; SI-NEXT: v_mov_b32_e32 v4, s20467; SI-NEXT: v_mov_b32_e32 v5, s21468; SI-NEXT: v_mov_b32_e32 v6, s22469; SI-NEXT: v_mov_b32_e32 v7, s23470; SI-NEXT: v_mov_b32_e32 v8, s24471; SI-NEXT: v_mov_b32_e32 v9, s25472; SI-NEXT: v_mov_b32_e32 v10, s26473; SI-NEXT: v_mov_b32_e32 v11, s27474; SI-NEXT: v_mov_b32_e32 v12, s28475; SI-NEXT: v_mov_b32_e32 v13, s29476; SI-NEXT: v_mov_b32_e32 v14, s30477; SI-NEXT: v_mov_b32_e32 v15, s31478; SI-NEXT: s_setpc_b64 s[30:31]479;480; VI-LABEL: bitcast_v14f32_to_v14i32_scalar:481; VI: ; %bb.0:482; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)483; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0484; VI-NEXT: s_and_b64 s[4:5], vcc, exec485; VI-NEXT: s_cbranch_scc0 .LBB3_3486; VI-NEXT: ; %bb.1: ; %cmp.false487; VI-NEXT: s_cbranch_execnz .LBB3_4488; VI-NEXT: .LBB3_2: ; %cmp.true489; VI-NEXT: v_add_f32_e64 v13, s29, 1.0490; VI-NEXT: v_add_f32_e64 v12, s28, 1.0491; VI-NEXT: v_add_f32_e64 v11, s27, 1.0492; VI-NEXT: v_add_f32_e64 v10, s26, 1.0493; VI-NEXT: v_add_f32_e64 v9, s25, 1.0494; VI-NEXT: v_add_f32_e64 v8, s24, 1.0495; VI-NEXT: v_add_f32_e64 v7, s23, 1.0496; VI-NEXT: v_add_f32_e64 v6, s22, 1.0497; VI-NEXT: v_add_f32_e64 v5, s21, 1.0498; VI-NEXT: v_add_f32_e64 v4, s20, 1.0499; VI-NEXT: v_add_f32_e64 v3, s19, 1.0500; VI-NEXT: v_add_f32_e64 v2, s18, 1.0501; VI-NEXT: v_add_f32_e64 v1, s17, 1.0502; VI-NEXT: v_add_f32_e64 v0, s16, 1.0503; VI-NEXT: s_setpc_b64 s[30:31]504; VI-NEXT: .LBB3_3:505; VI-NEXT: s_branch .LBB3_2506; VI-NEXT: .LBB3_4:507; VI-NEXT: v_mov_b32_e32 v0, s16508; VI-NEXT: v_mov_b32_e32 v1, s17509; VI-NEXT: v_mov_b32_e32 v2, s18510; VI-NEXT: v_mov_b32_e32 v3, s19511; VI-NEXT: v_mov_b32_e32 v4, s20512; VI-NEXT: v_mov_b32_e32 v5, s21513; VI-NEXT: v_mov_b32_e32 v6, s22514; VI-NEXT: v_mov_b32_e32 v7, s23515; VI-NEXT: v_mov_b32_e32 v8, s24516; VI-NEXT: v_mov_b32_e32 v9, s25517; VI-NEXT: v_mov_b32_e32 v10, s26518; VI-NEXT: v_mov_b32_e32 v11, s27519; VI-NEXT: v_mov_b32_e32 v12, s28520; VI-NEXT: v_mov_b32_e32 v13, s29521; VI-NEXT: v_mov_b32_e32 v14, s30522; VI-NEXT: v_mov_b32_e32 v15, s31523; VI-NEXT: s_setpc_b64 s[30:31]524;525; GFX9-LABEL: bitcast_v14f32_to_v14i32_scalar:526; GFX9: ; %bb.0:527; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)528; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0529; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec530; GFX9-NEXT: s_cbranch_scc0 .LBB3_3531; GFX9-NEXT: ; %bb.1: ; %cmp.false532; GFX9-NEXT: s_cbranch_execnz .LBB3_4533; GFX9-NEXT: .LBB3_2: ; %cmp.true534; GFX9-NEXT: v_add_f32_e64 v13, s29, 1.0535; GFX9-NEXT: v_add_f32_e64 v12, s28, 1.0536; GFX9-NEXT: v_add_f32_e64 v11, s27, 1.0537; GFX9-NEXT: v_add_f32_e64 v10, s26, 1.0538; GFX9-NEXT: v_add_f32_e64 v9, s25, 1.0539; GFX9-NEXT: v_add_f32_e64 v8, s24, 1.0540; GFX9-NEXT: v_add_f32_e64 v7, s23, 1.0541; GFX9-NEXT: v_add_f32_e64 v6, s22, 1.0542; GFX9-NEXT: v_add_f32_e64 v5, s21, 1.0543; GFX9-NEXT: v_add_f32_e64 v4, s20, 1.0544; GFX9-NEXT: v_add_f32_e64 v3, s19, 1.0545; GFX9-NEXT: v_add_f32_e64 v2, s18, 1.0546; GFX9-NEXT: v_add_f32_e64 v1, s17, 1.0547; GFX9-NEXT: v_add_f32_e64 v0, s16, 1.0548; GFX9-NEXT: s_setpc_b64 s[30:31]549; GFX9-NEXT: .LBB3_3:550; GFX9-NEXT: s_branch .LBB3_2551; GFX9-NEXT: .LBB3_4:552; GFX9-NEXT: v_mov_b32_e32 v0, s16553; GFX9-NEXT: v_mov_b32_e32 v1, s17554; GFX9-NEXT: v_mov_b32_e32 v2, s18555; GFX9-NEXT: v_mov_b32_e32 v3, s19556; GFX9-NEXT: v_mov_b32_e32 v4, s20557; GFX9-NEXT: v_mov_b32_e32 v5, s21558; GFX9-NEXT: v_mov_b32_e32 v6, s22559; GFX9-NEXT: v_mov_b32_e32 v7, s23560; GFX9-NEXT: v_mov_b32_e32 v8, s24561; GFX9-NEXT: v_mov_b32_e32 v9, s25562; GFX9-NEXT: v_mov_b32_e32 v10, s26563; GFX9-NEXT: v_mov_b32_e32 v11, s27564; GFX9-NEXT: v_mov_b32_e32 v12, s28565; GFX9-NEXT: v_mov_b32_e32 v13, s29566; GFX9-NEXT: v_mov_b32_e32 v14, s30567; GFX9-NEXT: v_mov_b32_e32 v15, s31568; GFX9-NEXT: s_setpc_b64 s[30:31]569;570; GFX11-LABEL: bitcast_v14f32_to_v14i32_scalar:571; GFX11: ; %bb.0:572; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)573; GFX11-NEXT: s_mov_b32 s15, s3574; GFX11-NEXT: s_mov_b32 s14, s2575; GFX11-NEXT: s_mov_b32 s13, s1576; GFX11-NEXT: s_mov_b32 s12, s0577; GFX11-NEXT: s_cmp_lg_u32 s26, 0578; GFX11-NEXT: s_mov_b32 s0, 0579; GFX11-NEXT: s_cbranch_scc0 .LBB3_3580; GFX11-NEXT: ; %bb.1: ; %Flow581; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0582; GFX11-NEXT: s_cbranch_vccnz .LBB3_4583; GFX11-NEXT: .LBB3_2: ; %cmp.true584; GFX11-NEXT: v_add_f32_e64 v13, s25, 1.0585; GFX11-NEXT: v_add_f32_e64 v12, s24, 1.0586; GFX11-NEXT: v_add_f32_e64 v11, s23, 1.0587; GFX11-NEXT: v_add_f32_e64 v10, s22, 1.0588; GFX11-NEXT: v_add_f32_e64 v9, s21, 1.0589; GFX11-NEXT: v_add_f32_e64 v8, s20, 1.0590; GFX11-NEXT: v_add_f32_e64 v7, s19, 1.0591; GFX11-NEXT: v_add_f32_e64 v6, s18, 1.0592; GFX11-NEXT: v_add_f32_e64 v5, s17, 1.0593; GFX11-NEXT: v_add_f32_e64 v4, s16, 1.0594; GFX11-NEXT: v_add_f32_e64 v3, s15, 1.0595; GFX11-NEXT: v_add_f32_e64 v2, s14, 1.0596; GFX11-NEXT: v_add_f32_e64 v1, s13, 1.0597; GFX11-NEXT: v_add_f32_e64 v0, s12, 1.0598; GFX11-NEXT: s_setpc_b64 s[30:31]599; GFX11-NEXT: .LBB3_3:600; GFX11-NEXT: s_branch .LBB3_2601; GFX11-NEXT: .LBB3_4:602; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13603; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15604; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17605; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19606; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21607; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23608; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25609; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27610; GFX11-NEXT: s_setpc_b64 s[30:31]611 %cmp = icmp eq i32 %b, 0612 br i1 %cmp, label %cmp.true, label %cmp.false613 614cmp.true:615 %a1 = fadd <14 x float> %a, splat (float 1.000000e+00)616 %a2 = bitcast <14 x float> %a1 to <14 x i32>617 br label %end618 619cmp.false:620 %a3 = bitcast <14 x float> %a to <14 x i32>621 br label %end622 623end:624 %phi = phi <14 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]625 ret <14 x i32> %phi626}627 628define <7 x i64> @bitcast_v14i32_to_v7i64(<14 x i32> %a, i32 %b) {629; SI-LABEL: bitcast_v14i32_to_v7i64:630; SI: ; %bb.0:631; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)632; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14633; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc634; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]635; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]636; SI-NEXT: s_cbranch_execz .LBB4_2637; SI-NEXT: ; %bb.1: ; %cmp.true638; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13639; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12640; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v11641; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10642; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v9643; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8644; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7645; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6646; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5647; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4648; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3649; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2650; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1651; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0652; SI-NEXT: .LBB4_2: ; %end653; SI-NEXT: s_or_b64 exec, exec, s[4:5]654; SI-NEXT: s_setpc_b64 s[30:31]655;656; VI-LABEL: bitcast_v14i32_to_v7i64:657; VI: ; %bb.0:658; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)659; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14660; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc661; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]662; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]663; VI-NEXT: s_cbranch_execz .LBB4_2664; VI-NEXT: ; %bb.1: ; %cmp.true665; VI-NEXT: v_add_u32_e32 v13, vcc, 3, v13666; VI-NEXT: v_add_u32_e32 v12, vcc, 3, v12667; VI-NEXT: v_add_u32_e32 v11, vcc, 3, v11668; VI-NEXT: v_add_u32_e32 v10, vcc, 3, v10669; VI-NEXT: v_add_u32_e32 v9, vcc, 3, v9670; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v8671; VI-NEXT: v_add_u32_e32 v7, vcc, 3, v7672; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6673; VI-NEXT: v_add_u32_e32 v5, vcc, 3, v5674; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4675; VI-NEXT: v_add_u32_e32 v3, vcc, 3, v3676; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2677; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1678; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0679; VI-NEXT: .LBB4_2: ; %end680; VI-NEXT: s_or_b64 exec, exec, s[4:5]681; VI-NEXT: s_setpc_b64 s[30:31]682;683; GFX9-LABEL: bitcast_v14i32_to_v7i64:684; GFX9: ; %bb.0:685; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)686; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14687; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc688; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]689; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]690; GFX9-NEXT: s_cbranch_execz .LBB4_2691; GFX9-NEXT: ; %bb.1: ; %cmp.true692; GFX9-NEXT: v_add_u32_e32 v13, 3, v13693; GFX9-NEXT: v_add_u32_e32 v12, 3, v12694; GFX9-NEXT: v_add_u32_e32 v11, 3, v11695; GFX9-NEXT: v_add_u32_e32 v10, 3, v10696; GFX9-NEXT: v_add_u32_e32 v9, 3, v9697; GFX9-NEXT: v_add_u32_e32 v8, 3, v8698; GFX9-NEXT: v_add_u32_e32 v7, 3, v7699; GFX9-NEXT: v_add_u32_e32 v6, 3, v6700; GFX9-NEXT: v_add_u32_e32 v5, 3, v5701; GFX9-NEXT: v_add_u32_e32 v4, 3, v4702; GFX9-NEXT: v_add_u32_e32 v3, 3, v3703; GFX9-NEXT: v_add_u32_e32 v2, 3, v2704; GFX9-NEXT: v_add_u32_e32 v1, 3, v1705; GFX9-NEXT: v_add_u32_e32 v0, 3, v0706; GFX9-NEXT: .LBB4_2: ; %end707; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]708; GFX9-NEXT: s_setpc_b64 s[30:31]709;710; GFX11-LABEL: bitcast_v14i32_to_v7i64:711; GFX11: ; %bb.0:712; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)713; GFX11-NEXT: s_mov_b32 s0, exec_lo714; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v14715; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0716; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)717; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0718; GFX11-NEXT: s_cbranch_execz .LBB4_2719; GFX11-NEXT: ; %bb.1: ; %cmp.true720; GFX11-NEXT: v_add_nc_u32_e32 v13, 3, v13721; GFX11-NEXT: v_add_nc_u32_e32 v12, 3, v12722; GFX11-NEXT: v_add_nc_u32_e32 v11, 3, v11723; GFX11-NEXT: v_add_nc_u32_e32 v10, 3, v10724; GFX11-NEXT: v_add_nc_u32_e32 v9, 3, v9725; GFX11-NEXT: v_add_nc_u32_e32 v8, 3, v8726; GFX11-NEXT: v_add_nc_u32_e32 v7, 3, v7727; GFX11-NEXT: v_add_nc_u32_e32 v6, 3, v6728; GFX11-NEXT: v_add_nc_u32_e32 v5, 3, v5729; GFX11-NEXT: v_add_nc_u32_e32 v4, 3, v4730; GFX11-NEXT: v_add_nc_u32_e32 v3, 3, v3731; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2732; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1733; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0734; GFX11-NEXT: .LBB4_2: ; %end735; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0736; GFX11-NEXT: s_setpc_b64 s[30:31]737 %cmp = icmp eq i32 %b, 0738 br i1 %cmp, label %cmp.true, label %cmp.false739 740cmp.true:741 %a1 = add <14 x i32> %a, splat (i32 3)742 %a2 = bitcast <14 x i32> %a1 to <7 x i64>743 br label %end744 745cmp.false:746 %a3 = bitcast <14 x i32> %a to <7 x i64>747 br label %end748 749end:750 %phi = phi <7 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]751 ret <7 x i64> %phi752}753 754define inreg <7 x i64> @bitcast_v14i32_to_v7i64_scalar(<14 x i32> inreg %a, i32 inreg %b) {755; SI-LABEL: bitcast_v14i32_to_v7i64_scalar:756; SI: ; %bb.0:757; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)758; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0759; SI-NEXT: s_and_b64 s[4:5], vcc, exec760; SI-NEXT: s_cbranch_scc0 .LBB5_4761; SI-NEXT: ; %bb.1: ; %cmp.false762; SI-NEXT: s_cbranch_execnz .LBB5_3763; SI-NEXT: .LBB5_2: ; %cmp.true764; SI-NEXT: s_add_i32 s29, s29, 3765; SI-NEXT: s_add_i32 s28, s28, 3766; SI-NEXT: s_add_i32 s27, s27, 3767; SI-NEXT: s_add_i32 s26, s26, 3768; SI-NEXT: s_add_i32 s25, s25, 3769; SI-NEXT: s_add_i32 s24, s24, 3770; SI-NEXT: s_add_i32 s23, s23, 3771; SI-NEXT: s_add_i32 s22, s22, 3772; SI-NEXT: s_add_i32 s21, s21, 3773; SI-NEXT: s_add_i32 s20, s20, 3774; SI-NEXT: s_add_i32 s19, s19, 3775; SI-NEXT: s_add_i32 s18, s18, 3776; SI-NEXT: s_add_i32 s17, s17, 3777; SI-NEXT: s_add_i32 s16, s16, 3778; SI-NEXT: .LBB5_3: ; %end779; SI-NEXT: v_mov_b32_e32 v0, s16780; SI-NEXT: v_mov_b32_e32 v1, s17781; SI-NEXT: v_mov_b32_e32 v2, s18782; SI-NEXT: v_mov_b32_e32 v3, s19783; SI-NEXT: v_mov_b32_e32 v4, s20784; SI-NEXT: v_mov_b32_e32 v5, s21785; SI-NEXT: v_mov_b32_e32 v6, s22786; SI-NEXT: v_mov_b32_e32 v7, s23787; SI-NEXT: v_mov_b32_e32 v8, s24788; SI-NEXT: v_mov_b32_e32 v9, s25789; SI-NEXT: v_mov_b32_e32 v10, s26790; SI-NEXT: v_mov_b32_e32 v11, s27791; SI-NEXT: v_mov_b32_e32 v12, s28792; SI-NEXT: v_mov_b32_e32 v13, s29793; SI-NEXT: s_setpc_b64 s[30:31]794; SI-NEXT: .LBB5_4:795; SI-NEXT: s_branch .LBB5_2796;797; VI-LABEL: bitcast_v14i32_to_v7i64_scalar:798; VI: ; %bb.0:799; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)800; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0801; VI-NEXT: s_and_b64 s[4:5], vcc, exec802; VI-NEXT: s_cbranch_scc0 .LBB5_4803; VI-NEXT: ; %bb.1: ; %cmp.false804; VI-NEXT: s_cbranch_execnz .LBB5_3805; VI-NEXT: .LBB5_2: ; %cmp.true806; VI-NEXT: s_add_i32 s29, s29, 3807; VI-NEXT: s_add_i32 s28, s28, 3808; VI-NEXT: s_add_i32 s27, s27, 3809; VI-NEXT: s_add_i32 s26, s26, 3810; VI-NEXT: s_add_i32 s25, s25, 3811; VI-NEXT: s_add_i32 s24, s24, 3812; VI-NEXT: s_add_i32 s23, s23, 3813; VI-NEXT: s_add_i32 s22, s22, 3814; VI-NEXT: s_add_i32 s21, s21, 3815; VI-NEXT: s_add_i32 s20, s20, 3816; VI-NEXT: s_add_i32 s19, s19, 3817; VI-NEXT: s_add_i32 s18, s18, 3818; VI-NEXT: s_add_i32 s17, s17, 3819; VI-NEXT: s_add_i32 s16, s16, 3820; VI-NEXT: .LBB5_3: ; %end821; VI-NEXT: v_mov_b32_e32 v0, s16822; VI-NEXT: v_mov_b32_e32 v1, s17823; VI-NEXT: v_mov_b32_e32 v2, s18824; VI-NEXT: v_mov_b32_e32 v3, s19825; VI-NEXT: v_mov_b32_e32 v4, s20826; VI-NEXT: v_mov_b32_e32 v5, s21827; VI-NEXT: v_mov_b32_e32 v6, s22828; VI-NEXT: v_mov_b32_e32 v7, s23829; VI-NEXT: v_mov_b32_e32 v8, s24830; VI-NEXT: v_mov_b32_e32 v9, s25831; VI-NEXT: v_mov_b32_e32 v10, s26832; VI-NEXT: v_mov_b32_e32 v11, s27833; VI-NEXT: v_mov_b32_e32 v12, s28834; VI-NEXT: v_mov_b32_e32 v13, s29835; VI-NEXT: s_setpc_b64 s[30:31]836; VI-NEXT: .LBB5_4:837; VI-NEXT: s_branch .LBB5_2838;839; GFX9-LABEL: bitcast_v14i32_to_v7i64_scalar:840; GFX9: ; %bb.0:841; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)842; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0843; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec844; GFX9-NEXT: s_cbranch_scc0 .LBB5_4845; GFX9-NEXT: ; %bb.1: ; %cmp.false846; GFX9-NEXT: s_cbranch_execnz .LBB5_3847; GFX9-NEXT: .LBB5_2: ; %cmp.true848; GFX9-NEXT: s_add_i32 s29, s29, 3849; GFX9-NEXT: s_add_i32 s28, s28, 3850; GFX9-NEXT: s_add_i32 s27, s27, 3851; GFX9-NEXT: s_add_i32 s26, s26, 3852; GFX9-NEXT: s_add_i32 s25, s25, 3853; GFX9-NEXT: s_add_i32 s24, s24, 3854; GFX9-NEXT: s_add_i32 s23, s23, 3855; GFX9-NEXT: s_add_i32 s22, s22, 3856; GFX9-NEXT: s_add_i32 s21, s21, 3857; GFX9-NEXT: s_add_i32 s20, s20, 3858; GFX9-NEXT: s_add_i32 s19, s19, 3859; GFX9-NEXT: s_add_i32 s18, s18, 3860; GFX9-NEXT: s_add_i32 s17, s17, 3861; GFX9-NEXT: s_add_i32 s16, s16, 3862; GFX9-NEXT: .LBB5_3: ; %end863; GFX9-NEXT: v_mov_b32_e32 v0, s16864; GFX9-NEXT: v_mov_b32_e32 v1, s17865; GFX9-NEXT: v_mov_b32_e32 v2, s18866; GFX9-NEXT: v_mov_b32_e32 v3, s19867; GFX9-NEXT: v_mov_b32_e32 v4, s20868; GFX9-NEXT: v_mov_b32_e32 v5, s21869; GFX9-NEXT: v_mov_b32_e32 v6, s22870; GFX9-NEXT: v_mov_b32_e32 v7, s23871; GFX9-NEXT: v_mov_b32_e32 v8, s24872; GFX9-NEXT: v_mov_b32_e32 v9, s25873; GFX9-NEXT: v_mov_b32_e32 v10, s26874; GFX9-NEXT: v_mov_b32_e32 v11, s27875; GFX9-NEXT: v_mov_b32_e32 v12, s28876; GFX9-NEXT: v_mov_b32_e32 v13, s29877; GFX9-NEXT: s_setpc_b64 s[30:31]878; GFX9-NEXT: .LBB5_4:879; GFX9-NEXT: s_branch .LBB5_2880;881; GFX11-LABEL: bitcast_v14i32_to_v7i64_scalar:882; GFX11: ; %bb.0:883; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)884; GFX11-NEXT: s_cmp_lg_u32 s26, 0885; GFX11-NEXT: s_mov_b32 s4, 0886; GFX11-NEXT: s_cbranch_scc0 .LBB5_4887; GFX11-NEXT: ; %bb.1: ; %Flow888; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4889; GFX11-NEXT: s_cbranch_vccnz .LBB5_3890; GFX11-NEXT: .LBB5_2: ; %cmp.true891; GFX11-NEXT: s_add_i32 s25, s25, 3892; GFX11-NEXT: s_add_i32 s24, s24, 3893; GFX11-NEXT: s_add_i32 s23, s23, 3894; GFX11-NEXT: s_add_i32 s22, s22, 3895; GFX11-NEXT: s_add_i32 s21, s21, 3896; GFX11-NEXT: s_add_i32 s20, s20, 3897; GFX11-NEXT: s_add_i32 s19, s19, 3898; GFX11-NEXT: s_add_i32 s18, s18, 3899; GFX11-NEXT: s_add_i32 s17, s17, 3900; GFX11-NEXT: s_add_i32 s16, s16, 3901; GFX11-NEXT: s_add_i32 s3, s3, 3902; GFX11-NEXT: s_add_i32 s2, s2, 3903; GFX11-NEXT: s_add_i32 s1, s1, 3904; GFX11-NEXT: s_add_i32 s0, s0, 3905; GFX11-NEXT: .LBB5_3: ; %end906; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)907; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1908; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3909; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17910; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19911; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21912; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23913; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25914; GFX11-NEXT: s_setpc_b64 s[30:31]915; GFX11-NEXT: .LBB5_4:916; GFX11-NEXT: s_branch .LBB5_2917 %cmp = icmp eq i32 %b, 0918 br i1 %cmp, label %cmp.true, label %cmp.false919 920cmp.true:921 %a1 = add <14 x i32> %a, splat (i32 3)922 %a2 = bitcast <14 x i32> %a1 to <7 x i64>923 br label %end924 925cmp.false:926 %a3 = bitcast <14 x i32> %a to <7 x i64>927 br label %end928 929end:930 %phi = phi <7 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]931 ret <7 x i64> %phi932}933 934define <14 x i32> @bitcast_v7i64_to_v14i32(<7 x i64> %a, i32 %b) {935; SI-LABEL: bitcast_v7i64_to_v14i32:936; SI: ; %bb.0:937; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)938; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14939; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc940; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]941; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]942; SI-NEXT: s_cbranch_execz .LBB6_2943; SI-NEXT: ; %bb.1: ; %cmp.true944; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12945; SI-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc946; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10947; SI-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc948; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8949; SI-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc950; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6951; SI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc952; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4953; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc954; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2955; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc956; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0957; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc958; SI-NEXT: .LBB6_2: ; %end959; SI-NEXT: s_or_b64 exec, exec, s[4:5]960; SI-NEXT: s_setpc_b64 s[30:31]961;962; VI-LABEL: bitcast_v7i64_to_v14i32:963; VI: ; %bb.0:964; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)965; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14966; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc967; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]968; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]969; VI-NEXT: s_cbranch_execz .LBB6_2970; VI-NEXT: ; %bb.1: ; %cmp.true971; VI-NEXT: v_add_u32_e32 v12, vcc, 3, v12972; VI-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc973; VI-NEXT: v_add_u32_e32 v10, vcc, 3, v10974; VI-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc975; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v8976; VI-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc977; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6978; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc979; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4980; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc981; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2982; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc983; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0984; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc985; VI-NEXT: .LBB6_2: ; %end986; VI-NEXT: s_or_b64 exec, exec, s[4:5]987; VI-NEXT: s_setpc_b64 s[30:31]988;989; GFX9-LABEL: bitcast_v7i64_to_v14i32:990; GFX9: ; %bb.0:991; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)992; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14993; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc994; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]995; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]996; GFX9-NEXT: s_cbranch_execz .LBB6_2997; GFX9-NEXT: ; %bb.1: ; %cmp.true998; GFX9-NEXT: v_add_co_u32_e32 v12, vcc, 3, v12999; GFX9-NEXT: v_addc_co_u32_e32 v13, vcc, 0, v13, vcc1000; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, 3, v101001; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v11, vcc1002; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, 3, v81003; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v9, vcc1004; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, 3, v61005; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v7, vcc1006; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, 3, v41007; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc1008; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 3, v21009; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc1010; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v01011; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc1012; GFX9-NEXT: .LBB6_2: ; %end1013; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]1014; GFX9-NEXT: s_setpc_b64 s[30:31]1015;1016; GFX11-LABEL: bitcast_v7i64_to_v14i32:1017; GFX11: ; %bb.0:1018; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1019; GFX11-NEXT: s_mov_b32 s0, exec_lo1020; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v141021; GFX11-NEXT: s_xor_b32 s0, exec_lo, s01022; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)1023; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s01024; GFX11-NEXT: s_cbranch_execz .LBB6_21025; GFX11-NEXT: ; %bb.1: ; %cmp.true1026; GFX11-NEXT: v_add_co_u32 v12, vcc_lo, v12, 31027; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)1028; GFX11-NEXT: v_add_co_ci_u32_e64 v13, null, 0, v13, vcc_lo1029; GFX11-NEXT: v_add_co_u32 v10, vcc_lo, v10, 31030; GFX11-NEXT: v_add_co_ci_u32_e64 v11, null, 0, v11, vcc_lo1031; GFX11-NEXT: v_add_co_u32 v8, vcc_lo, v8, 31032; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)1033; GFX11-NEXT: v_add_co_ci_u32_e64 v9, null, 0, v9, vcc_lo1034; GFX11-NEXT: v_add_co_u32 v6, vcc_lo, v6, 31035; GFX11-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v7, vcc_lo1036; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v4, 31037; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)1038; GFX11-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo1039; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, 31040; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo1041; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 31042; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)1043; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo1044; GFX11-NEXT: .LBB6_2: ; %end1045; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s01046; GFX11-NEXT: s_setpc_b64 s[30:31]1047 %cmp = icmp eq i32 %b, 01048 br i1 %cmp, label %cmp.true, label %cmp.false1049 1050cmp.true:1051 %a1 = add <7 x i64> %a, splat (i64 3)1052 %a2 = bitcast <7 x i64> %a1 to <14 x i32>1053 br label %end1054 1055cmp.false:1056 %a3 = bitcast <7 x i64> %a to <14 x i32>1057 br label %end1058 1059end:1060 %phi = phi <14 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]1061 ret <14 x i32> %phi1062}1063 1064define inreg <14 x i32> @bitcast_v7i64_to_v14i32_scalar(<7 x i64> inreg %a, i32 inreg %b) {1065; SI-LABEL: bitcast_v7i64_to_v14i32_scalar:1066; SI: ; %bb.0:1067; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1068; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v01069; SI-NEXT: s_and_b64 s[4:5], vcc, exec1070; SI-NEXT: s_cbranch_scc0 .LBB7_41071; SI-NEXT: ; %bb.1: ; %cmp.false1072; SI-NEXT: s_cbranch_execnz .LBB7_31073; SI-NEXT: .LBB7_2: ; %cmp.true1074; SI-NEXT: s_add_u32 s28, s28, 31075; SI-NEXT: s_addc_u32 s29, s29, 01076; SI-NEXT: s_add_u32 s26, s26, 31077; SI-NEXT: s_addc_u32 s27, s27, 01078; SI-NEXT: s_add_u32 s24, s24, 31079; SI-NEXT: s_addc_u32 s25, s25, 01080; SI-NEXT: s_add_u32 s22, s22, 31081; SI-NEXT: s_addc_u32 s23, s23, 01082; SI-NEXT: s_add_u32 s20, s20, 31083; SI-NEXT: s_addc_u32 s21, s21, 01084; SI-NEXT: s_add_u32 s18, s18, 31085; SI-NEXT: s_addc_u32 s19, s19, 01086; SI-NEXT: s_add_u32 s16, s16, 31087; SI-NEXT: s_addc_u32 s17, s17, 01088; SI-NEXT: .LBB7_3: ; %end1089; SI-NEXT: v_mov_b32_e32 v0, s161090; SI-NEXT: v_mov_b32_e32 v1, s171091; SI-NEXT: v_mov_b32_e32 v2, s181092; SI-NEXT: v_mov_b32_e32 v3, s191093; SI-NEXT: v_mov_b32_e32 v4, s201094; SI-NEXT: v_mov_b32_e32 v5, s211095; SI-NEXT: v_mov_b32_e32 v6, s221096; SI-NEXT: v_mov_b32_e32 v7, s231097; SI-NEXT: v_mov_b32_e32 v8, s241098; SI-NEXT: v_mov_b32_e32 v9, s251099; SI-NEXT: v_mov_b32_e32 v10, s261100; SI-NEXT: v_mov_b32_e32 v11, s271101; SI-NEXT: v_mov_b32_e32 v12, s281102; SI-NEXT: v_mov_b32_e32 v13, s291103; SI-NEXT: s_setpc_b64 s[30:31]1104; SI-NEXT: .LBB7_4:1105; SI-NEXT: s_branch .LBB7_21106;1107; VI-LABEL: bitcast_v7i64_to_v14i32_scalar:1108; VI: ; %bb.0:1109; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1110; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v01111; VI-NEXT: s_and_b64 s[4:5], vcc, exec1112; VI-NEXT: s_cbranch_scc0 .LBB7_41113; VI-NEXT: ; %bb.1: ; %cmp.false1114; VI-NEXT: s_cbranch_execnz .LBB7_31115; VI-NEXT: .LBB7_2: ; %cmp.true1116; VI-NEXT: s_add_u32 s28, s28, 31117; VI-NEXT: s_addc_u32 s29, s29, 01118; VI-NEXT: s_add_u32 s26, s26, 31119; VI-NEXT: s_addc_u32 s27, s27, 01120; VI-NEXT: s_add_u32 s24, s24, 31121; VI-NEXT: s_addc_u32 s25, s25, 01122; VI-NEXT: s_add_u32 s22, s22, 31123; VI-NEXT: s_addc_u32 s23, s23, 01124; VI-NEXT: s_add_u32 s20, s20, 31125; VI-NEXT: s_addc_u32 s21, s21, 01126; VI-NEXT: s_add_u32 s18, s18, 31127; VI-NEXT: s_addc_u32 s19, s19, 01128; VI-NEXT: s_add_u32 s16, s16, 31129; VI-NEXT: s_addc_u32 s17, s17, 01130; VI-NEXT: .LBB7_3: ; %end1131; VI-NEXT: v_mov_b32_e32 v0, s161132; VI-NEXT: v_mov_b32_e32 v1, s171133; VI-NEXT: v_mov_b32_e32 v2, s181134; VI-NEXT: v_mov_b32_e32 v3, s191135; VI-NEXT: v_mov_b32_e32 v4, s201136; VI-NEXT: v_mov_b32_e32 v5, s211137; VI-NEXT: v_mov_b32_e32 v6, s221138; VI-NEXT: v_mov_b32_e32 v7, s231139; VI-NEXT: v_mov_b32_e32 v8, s241140; VI-NEXT: v_mov_b32_e32 v9, s251141; VI-NEXT: v_mov_b32_e32 v10, s261142; VI-NEXT: v_mov_b32_e32 v11, s271143; VI-NEXT: v_mov_b32_e32 v12, s281144; VI-NEXT: v_mov_b32_e32 v13, s291145; VI-NEXT: s_setpc_b64 s[30:31]1146; VI-NEXT: .LBB7_4:1147; VI-NEXT: s_branch .LBB7_21148;1149; GFX9-LABEL: bitcast_v7i64_to_v14i32_scalar:1150; GFX9: ; %bb.0:1151; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1152; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v01153; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec1154; GFX9-NEXT: s_cbranch_scc0 .LBB7_41155; GFX9-NEXT: ; %bb.1: ; %cmp.false1156; GFX9-NEXT: s_cbranch_execnz .LBB7_31157; GFX9-NEXT: .LBB7_2: ; %cmp.true1158; GFX9-NEXT: s_add_u32 s28, s28, 31159; GFX9-NEXT: s_addc_u32 s29, s29, 01160; GFX9-NEXT: s_add_u32 s26, s26, 31161; GFX9-NEXT: s_addc_u32 s27, s27, 01162; GFX9-NEXT: s_add_u32 s24, s24, 31163; GFX9-NEXT: s_addc_u32 s25, s25, 01164; GFX9-NEXT: s_add_u32 s22, s22, 31165; GFX9-NEXT: s_addc_u32 s23, s23, 01166; GFX9-NEXT: s_add_u32 s20, s20, 31167; GFX9-NEXT: s_addc_u32 s21, s21, 01168; GFX9-NEXT: s_add_u32 s18, s18, 31169; GFX9-NEXT: s_addc_u32 s19, s19, 01170; GFX9-NEXT: s_add_u32 s16, s16, 31171; GFX9-NEXT: s_addc_u32 s17, s17, 01172; GFX9-NEXT: .LBB7_3: ; %end1173; GFX9-NEXT: v_mov_b32_e32 v0, s161174; GFX9-NEXT: v_mov_b32_e32 v1, s171175; GFX9-NEXT: v_mov_b32_e32 v2, s181176; GFX9-NEXT: v_mov_b32_e32 v3, s191177; GFX9-NEXT: v_mov_b32_e32 v4, s201178; GFX9-NEXT: v_mov_b32_e32 v5, s211179; GFX9-NEXT: v_mov_b32_e32 v6, s221180; GFX9-NEXT: v_mov_b32_e32 v7, s231181; GFX9-NEXT: v_mov_b32_e32 v8, s241182; GFX9-NEXT: v_mov_b32_e32 v9, s251183; GFX9-NEXT: v_mov_b32_e32 v10, s261184; GFX9-NEXT: v_mov_b32_e32 v11, s271185; GFX9-NEXT: v_mov_b32_e32 v12, s281186; GFX9-NEXT: v_mov_b32_e32 v13, s291187; GFX9-NEXT: s_setpc_b64 s[30:31]1188; GFX9-NEXT: .LBB7_4:1189; GFX9-NEXT: s_branch .LBB7_21190;1191; GFX11-LABEL: bitcast_v7i64_to_v14i32_scalar:1192; GFX11: ; %bb.0:1193; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1194; GFX11-NEXT: s_cmp_lg_u32 s26, 01195; GFX11-NEXT: s_mov_b32 s4, 01196; GFX11-NEXT: s_cbranch_scc0 .LBB7_41197; GFX11-NEXT: ; %bb.1: ; %Flow1198; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s41199; GFX11-NEXT: s_cbranch_vccnz .LBB7_31200; GFX11-NEXT: .LBB7_2: ; %cmp.true1201; GFX11-NEXT: s_add_u32 s24, s24, 31202; GFX11-NEXT: s_addc_u32 s25, s25, 01203; GFX11-NEXT: s_add_u32 s22, s22, 31204; GFX11-NEXT: s_addc_u32 s23, s23, 01205; GFX11-NEXT: s_add_u32 s20, s20, 31206; GFX11-NEXT: s_addc_u32 s21, s21, 01207; GFX11-NEXT: s_add_u32 s18, s18, 31208; GFX11-NEXT: s_addc_u32 s19, s19, 01209; GFX11-NEXT: s_add_u32 s16, s16, 31210; GFX11-NEXT: s_addc_u32 s17, s17, 01211; GFX11-NEXT: s_add_u32 s2, s2, 31212; GFX11-NEXT: s_addc_u32 s3, s3, 01213; GFX11-NEXT: s_add_u32 s0, s0, 31214; GFX11-NEXT: s_addc_u32 s1, s1, 01215; GFX11-NEXT: .LBB7_3: ; %end1216; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)1217; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s11218; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s31219; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s171220; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s191221; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s211222; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s231223; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s251224; GFX11-NEXT: s_setpc_b64 s[30:31]1225; GFX11-NEXT: .LBB7_4:1226; GFX11-NEXT: s_branch .LBB7_21227 %cmp = icmp eq i32 %b, 01228 br i1 %cmp, label %cmp.true, label %cmp.false1229 1230cmp.true:1231 %a1 = add <7 x i64> %a, splat (i64 3)1232 %a2 = bitcast <7 x i64> %a1 to <14 x i32>1233 br label %end1234 1235cmp.false:1236 %a3 = bitcast <7 x i64> %a to <14 x i32>1237 br label %end1238 1239end:1240 %phi = phi <14 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]1241 ret <14 x i32> %phi1242}1243 1244define <7 x double> @bitcast_v14i32_to_v7f64(<14 x i32> %a, i32 %b) {1245; SI-LABEL: bitcast_v14i32_to_v7f64:1246; SI: ; %bb.0:1247; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1248; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v141249; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc1250; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]1251; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1252; SI-NEXT: s_cbranch_execz .LBB8_21253; SI-NEXT: ; %bb.1: ; %cmp.true1254; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v131255; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v121256; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v111257; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v101258; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v91259; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v81260; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v71261; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v61262; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v51263; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v41264; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v31265; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v21266; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v11267; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v01268; SI-NEXT: .LBB8_2: ; %end1269; SI-NEXT: s_or_b64 exec, exec, s[4:5]1270; SI-NEXT: s_setpc_b64 s[30:31]1271;1272; VI-LABEL: bitcast_v14i32_to_v7f64:1273; VI: ; %bb.0:1274; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1275; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v141276; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc1277; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]1278; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1279; VI-NEXT: s_cbranch_execz .LBB8_21280; VI-NEXT: ; %bb.1: ; %cmp.true1281; VI-NEXT: v_add_u32_e32 v13, vcc, 3, v131282; VI-NEXT: v_add_u32_e32 v12, vcc, 3, v121283; VI-NEXT: v_add_u32_e32 v11, vcc, 3, v111284; VI-NEXT: v_add_u32_e32 v10, vcc, 3, v101285; VI-NEXT: v_add_u32_e32 v9, vcc, 3, v91286; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v81287; VI-NEXT: v_add_u32_e32 v7, vcc, 3, v71288; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v61289; VI-NEXT: v_add_u32_e32 v5, vcc, 3, v51290; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v41291; VI-NEXT: v_add_u32_e32 v3, vcc, 3, v31292; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v21293; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v11294; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v01295; VI-NEXT: .LBB8_2: ; %end1296; VI-NEXT: s_or_b64 exec, exec, s[4:5]1297; VI-NEXT: s_setpc_b64 s[30:31]1298;1299; GFX9-LABEL: bitcast_v14i32_to_v7f64:1300; GFX9: ; %bb.0:1301; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1302; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v141303; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc1304; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]1305; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1306; GFX9-NEXT: s_cbranch_execz .LBB8_21307; GFX9-NEXT: ; %bb.1: ; %cmp.true1308; GFX9-NEXT: v_add_u32_e32 v13, 3, v131309; GFX9-NEXT: v_add_u32_e32 v12, 3, v121310; GFX9-NEXT: v_add_u32_e32 v11, 3, v111311; GFX9-NEXT: v_add_u32_e32 v10, 3, v101312; GFX9-NEXT: v_add_u32_e32 v9, 3, v91313; GFX9-NEXT: v_add_u32_e32 v8, 3, v81314; GFX9-NEXT: v_add_u32_e32 v7, 3, v71315; GFX9-NEXT: v_add_u32_e32 v6, 3, v61316; GFX9-NEXT: v_add_u32_e32 v5, 3, v51317; GFX9-NEXT: v_add_u32_e32 v4, 3, v41318; GFX9-NEXT: v_add_u32_e32 v3, 3, v31319; GFX9-NEXT: v_add_u32_e32 v2, 3, v21320; GFX9-NEXT: v_add_u32_e32 v1, 3, v11321; GFX9-NEXT: v_add_u32_e32 v0, 3, v01322; GFX9-NEXT: .LBB8_2: ; %end1323; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]1324; GFX9-NEXT: s_setpc_b64 s[30:31]1325;1326; GFX11-LABEL: bitcast_v14i32_to_v7f64:1327; GFX11: ; %bb.0:1328; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1329; GFX11-NEXT: s_mov_b32 s0, exec_lo1330; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v141331; GFX11-NEXT: s_xor_b32 s0, exec_lo, s01332; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)1333; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s01334; GFX11-NEXT: s_cbranch_execz .LBB8_21335; GFX11-NEXT: ; %bb.1: ; %cmp.true1336; GFX11-NEXT: v_add_nc_u32_e32 v13, 3, v131337; GFX11-NEXT: v_add_nc_u32_e32 v12, 3, v121338; GFX11-NEXT: v_add_nc_u32_e32 v11, 3, v111339; GFX11-NEXT: v_add_nc_u32_e32 v10, 3, v101340; GFX11-NEXT: v_add_nc_u32_e32 v9, 3, v91341; GFX11-NEXT: v_add_nc_u32_e32 v8, 3, v81342; GFX11-NEXT: v_add_nc_u32_e32 v7, 3, v71343; GFX11-NEXT: v_add_nc_u32_e32 v6, 3, v61344; GFX11-NEXT: v_add_nc_u32_e32 v5, 3, v51345; GFX11-NEXT: v_add_nc_u32_e32 v4, 3, v41346; GFX11-NEXT: v_add_nc_u32_e32 v3, 3, v31347; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v21348; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v11349; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v01350; GFX11-NEXT: .LBB8_2: ; %end1351; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s01352; GFX11-NEXT: s_setpc_b64 s[30:31]1353 %cmp = icmp eq i32 %b, 01354 br i1 %cmp, label %cmp.true, label %cmp.false1355 1356cmp.true:1357 %a1 = add <14 x i32> %a, splat (i32 3)1358 %a2 = bitcast <14 x i32> %a1 to <7 x double>1359 br label %end1360 1361cmp.false:1362 %a3 = bitcast <14 x i32> %a to <7 x double>1363 br label %end1364 1365end:1366 %phi = phi <7 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]1367 ret <7 x double> %phi1368}1369 1370define inreg <7 x double> @bitcast_v14i32_to_v7f64_scalar(<14 x i32> inreg %a, i32 inreg %b) {1371; SI-LABEL: bitcast_v14i32_to_v7f64_scalar:1372; SI: ; %bb.0:1373; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1374; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v01375; SI-NEXT: s_and_b64 s[4:5], vcc, exec1376; SI-NEXT: s_cbranch_scc0 .LBB9_41377; SI-NEXT: ; %bb.1: ; %cmp.false1378; SI-NEXT: s_cbranch_execnz .LBB9_31379; SI-NEXT: .LBB9_2: ; %cmp.true1380; SI-NEXT: s_add_i32 s29, s29, 31381; SI-NEXT: s_add_i32 s28, s28, 31382; SI-NEXT: s_add_i32 s27, s27, 31383; SI-NEXT: s_add_i32 s26, s26, 31384; SI-NEXT: s_add_i32 s25, s25, 31385; SI-NEXT: s_add_i32 s24, s24, 31386; SI-NEXT: s_add_i32 s23, s23, 31387; SI-NEXT: s_add_i32 s22, s22, 31388; SI-NEXT: s_add_i32 s21, s21, 31389; SI-NEXT: s_add_i32 s20, s20, 31390; SI-NEXT: s_add_i32 s19, s19, 31391; SI-NEXT: s_add_i32 s18, s18, 31392; SI-NEXT: s_add_i32 s17, s17, 31393; SI-NEXT: s_add_i32 s16, s16, 31394; SI-NEXT: .LBB9_3: ; %end1395; SI-NEXT: v_mov_b32_e32 v0, s161396; SI-NEXT: v_mov_b32_e32 v1, s171397; SI-NEXT: v_mov_b32_e32 v2, s181398; SI-NEXT: v_mov_b32_e32 v3, s191399; SI-NEXT: v_mov_b32_e32 v4, s201400; SI-NEXT: v_mov_b32_e32 v5, s211401; SI-NEXT: v_mov_b32_e32 v6, s221402; SI-NEXT: v_mov_b32_e32 v7, s231403; SI-NEXT: v_mov_b32_e32 v8, s241404; SI-NEXT: v_mov_b32_e32 v9, s251405; SI-NEXT: v_mov_b32_e32 v10, s261406; SI-NEXT: v_mov_b32_e32 v11, s271407; SI-NEXT: v_mov_b32_e32 v12, s281408; SI-NEXT: v_mov_b32_e32 v13, s291409; SI-NEXT: s_setpc_b64 s[30:31]1410; SI-NEXT: .LBB9_4:1411; SI-NEXT: s_branch .LBB9_21412;1413; VI-LABEL: bitcast_v14i32_to_v7f64_scalar:1414; VI: ; %bb.0:1415; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1416; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v01417; VI-NEXT: s_and_b64 s[4:5], vcc, exec1418; VI-NEXT: s_cbranch_scc0 .LBB9_41419; VI-NEXT: ; %bb.1: ; %cmp.false1420; VI-NEXT: s_cbranch_execnz .LBB9_31421; VI-NEXT: .LBB9_2: ; %cmp.true1422; VI-NEXT: s_add_i32 s29, s29, 31423; VI-NEXT: s_add_i32 s28, s28, 31424; VI-NEXT: s_add_i32 s27, s27, 31425; VI-NEXT: s_add_i32 s26, s26, 31426; VI-NEXT: s_add_i32 s25, s25, 31427; VI-NEXT: s_add_i32 s24, s24, 31428; VI-NEXT: s_add_i32 s23, s23, 31429; VI-NEXT: s_add_i32 s22, s22, 31430; VI-NEXT: s_add_i32 s21, s21, 31431; VI-NEXT: s_add_i32 s20, s20, 31432; VI-NEXT: s_add_i32 s19, s19, 31433; VI-NEXT: s_add_i32 s18, s18, 31434; VI-NEXT: s_add_i32 s17, s17, 31435; VI-NEXT: s_add_i32 s16, s16, 31436; VI-NEXT: .LBB9_3: ; %end1437; VI-NEXT: v_mov_b32_e32 v0, s161438; VI-NEXT: v_mov_b32_e32 v1, s171439; VI-NEXT: v_mov_b32_e32 v2, s181440; VI-NEXT: v_mov_b32_e32 v3, s191441; VI-NEXT: v_mov_b32_e32 v4, s201442; VI-NEXT: v_mov_b32_e32 v5, s211443; VI-NEXT: v_mov_b32_e32 v6, s221444; VI-NEXT: v_mov_b32_e32 v7, s231445; VI-NEXT: v_mov_b32_e32 v8, s241446; VI-NEXT: v_mov_b32_e32 v9, s251447; VI-NEXT: v_mov_b32_e32 v10, s261448; VI-NEXT: v_mov_b32_e32 v11, s271449; VI-NEXT: v_mov_b32_e32 v12, s281450; VI-NEXT: v_mov_b32_e32 v13, s291451; VI-NEXT: s_setpc_b64 s[30:31]1452; VI-NEXT: .LBB9_4:1453; VI-NEXT: s_branch .LBB9_21454;1455; GFX9-LABEL: bitcast_v14i32_to_v7f64_scalar:1456; GFX9: ; %bb.0:1457; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1458; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v01459; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec1460; GFX9-NEXT: s_cbranch_scc0 .LBB9_41461; GFX9-NEXT: ; %bb.1: ; %cmp.false1462; GFX9-NEXT: s_cbranch_execnz .LBB9_31463; GFX9-NEXT: .LBB9_2: ; %cmp.true1464; GFX9-NEXT: s_add_i32 s29, s29, 31465; GFX9-NEXT: s_add_i32 s28, s28, 31466; GFX9-NEXT: s_add_i32 s27, s27, 31467; GFX9-NEXT: s_add_i32 s26, s26, 31468; GFX9-NEXT: s_add_i32 s25, s25, 31469; GFX9-NEXT: s_add_i32 s24, s24, 31470; GFX9-NEXT: s_add_i32 s23, s23, 31471; GFX9-NEXT: s_add_i32 s22, s22, 31472; GFX9-NEXT: s_add_i32 s21, s21, 31473; GFX9-NEXT: s_add_i32 s20, s20, 31474; GFX9-NEXT: s_add_i32 s19, s19, 31475; GFX9-NEXT: s_add_i32 s18, s18, 31476; GFX9-NEXT: s_add_i32 s17, s17, 31477; GFX9-NEXT: s_add_i32 s16, s16, 31478; GFX9-NEXT: .LBB9_3: ; %end1479; GFX9-NEXT: v_mov_b32_e32 v0, s161480; GFX9-NEXT: v_mov_b32_e32 v1, s171481; GFX9-NEXT: v_mov_b32_e32 v2, s181482; GFX9-NEXT: v_mov_b32_e32 v3, s191483; GFX9-NEXT: v_mov_b32_e32 v4, s201484; GFX9-NEXT: v_mov_b32_e32 v5, s211485; GFX9-NEXT: v_mov_b32_e32 v6, s221486; GFX9-NEXT: v_mov_b32_e32 v7, s231487; GFX9-NEXT: v_mov_b32_e32 v8, s241488; GFX9-NEXT: v_mov_b32_e32 v9, s251489; GFX9-NEXT: v_mov_b32_e32 v10, s261490; GFX9-NEXT: v_mov_b32_e32 v11, s271491; GFX9-NEXT: v_mov_b32_e32 v12, s281492; GFX9-NEXT: v_mov_b32_e32 v13, s291493; GFX9-NEXT: s_setpc_b64 s[30:31]1494; GFX9-NEXT: .LBB9_4:1495; GFX9-NEXT: s_branch .LBB9_21496;1497; GFX11-LABEL: bitcast_v14i32_to_v7f64_scalar:1498; GFX11: ; %bb.0:1499; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1500; GFX11-NEXT: s_cmp_lg_u32 s26, 01501; GFX11-NEXT: s_mov_b32 s4, 01502; GFX11-NEXT: s_cbranch_scc0 .LBB9_41503; GFX11-NEXT: ; %bb.1: ; %Flow1504; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s41505; GFX11-NEXT: s_cbranch_vccnz .LBB9_31506; GFX11-NEXT: .LBB9_2: ; %cmp.true1507; GFX11-NEXT: s_add_i32 s25, s25, 31508; GFX11-NEXT: s_add_i32 s24, s24, 31509; GFX11-NEXT: s_add_i32 s23, s23, 31510; GFX11-NEXT: s_add_i32 s22, s22, 31511; GFX11-NEXT: s_add_i32 s21, s21, 31512; GFX11-NEXT: s_add_i32 s20, s20, 31513; GFX11-NEXT: s_add_i32 s19, s19, 31514; GFX11-NEXT: s_add_i32 s18, s18, 31515; GFX11-NEXT: s_add_i32 s17, s17, 31516; GFX11-NEXT: s_add_i32 s16, s16, 31517; GFX11-NEXT: s_add_i32 s3, s3, 31518; GFX11-NEXT: s_add_i32 s2, s2, 31519; GFX11-NEXT: s_add_i32 s1, s1, 31520; GFX11-NEXT: s_add_i32 s0, s0, 31521; GFX11-NEXT: .LBB9_3: ; %end1522; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)1523; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s11524; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s31525; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s171526; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s191527; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s211528; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s231529; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s251530; GFX11-NEXT: s_setpc_b64 s[30:31]1531; GFX11-NEXT: .LBB9_4:1532; GFX11-NEXT: s_branch .LBB9_21533 %cmp = icmp eq i32 %b, 01534 br i1 %cmp, label %cmp.true, label %cmp.false1535 1536cmp.true:1537 %a1 = add <14 x i32> %a, splat (i32 3)1538 %a2 = bitcast <14 x i32> %a1 to <7 x double>1539 br label %end1540 1541cmp.false:1542 %a3 = bitcast <14 x i32> %a to <7 x double>1543 br label %end1544 1545end:1546 %phi = phi <7 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]1547 ret <7 x double> %phi1548}1549 1550define <14 x i32> @bitcast_v7f64_to_v14i32(<7 x double> %a, i32 %b) {1551; SI-LABEL: bitcast_v7f64_to_v14i32:1552; SI: ; %bb.0:1553; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1554; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v141555; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc1556; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]1557; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1558; SI-NEXT: s_cbranch_execz .LBB10_21559; SI-NEXT: ; %bb.1: ; %cmp.true1560; SI-NEXT: v_add_f64 v[12:13], v[12:13], 1.01561; SI-NEXT: v_add_f64 v[10:11], v[10:11], 1.01562; SI-NEXT: v_add_f64 v[8:9], v[8:9], 1.01563; SI-NEXT: v_add_f64 v[6:7], v[6:7], 1.01564; SI-NEXT: v_add_f64 v[4:5], v[4:5], 1.01565; SI-NEXT: v_add_f64 v[2:3], v[2:3], 1.01566; SI-NEXT: v_add_f64 v[0:1], v[0:1], 1.01567; SI-NEXT: .LBB10_2: ; %end1568; SI-NEXT: s_or_b64 exec, exec, s[4:5]1569; SI-NEXT: s_setpc_b64 s[30:31]1570;1571; VI-LABEL: bitcast_v7f64_to_v14i32:1572; VI: ; %bb.0:1573; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1574; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v141575; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc1576; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]1577; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1578; VI-NEXT: s_cbranch_execz .LBB10_21579; VI-NEXT: ; %bb.1: ; %cmp.true1580; VI-NEXT: v_add_f64 v[12:13], v[12:13], 1.01581; VI-NEXT: v_add_f64 v[10:11], v[10:11], 1.01582; VI-NEXT: v_add_f64 v[8:9], v[8:9], 1.01583; VI-NEXT: v_add_f64 v[6:7], v[6:7], 1.01584; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.01585; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.01586; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.01587; VI-NEXT: .LBB10_2: ; %end1588; VI-NEXT: s_or_b64 exec, exec, s[4:5]1589; VI-NEXT: s_setpc_b64 s[30:31]1590;1591; GFX9-LABEL: bitcast_v7f64_to_v14i32:1592; GFX9: ; %bb.0:1593; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1594; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v141595; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc1596; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]1597; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1598; GFX9-NEXT: s_cbranch_execz .LBB10_21599; GFX9-NEXT: ; %bb.1: ; %cmp.true1600; GFX9-NEXT: v_add_f64 v[12:13], v[12:13], 1.01601; GFX9-NEXT: v_add_f64 v[10:11], v[10:11], 1.01602; GFX9-NEXT: v_add_f64 v[8:9], v[8:9], 1.01603; GFX9-NEXT: v_add_f64 v[6:7], v[6:7], 1.01604; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.01605; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.01606; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.01607; GFX9-NEXT: .LBB10_2: ; %end1608; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]1609; GFX9-NEXT: s_setpc_b64 s[30:31]1610;1611; GFX11-LABEL: bitcast_v7f64_to_v14i32:1612; GFX11: ; %bb.0:1613; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1614; GFX11-NEXT: s_mov_b32 s0, exec_lo1615; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v141616; GFX11-NEXT: s_xor_b32 s0, exec_lo, s01617; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)1618; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s01619; GFX11-NEXT: s_cbranch_execz .LBB10_21620; GFX11-NEXT: ; %bb.1: ; %cmp.true1621; GFX11-NEXT: v_add_f64 v[12:13], v[12:13], 1.01622; GFX11-NEXT: v_add_f64 v[10:11], v[10:11], 1.01623; GFX11-NEXT: v_add_f64 v[8:9], v[8:9], 1.01624; GFX11-NEXT: v_add_f64 v[6:7], v[6:7], 1.01625; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.01626; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.01627; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.01628; GFX11-NEXT: .LBB10_2: ; %end1629; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s01630; GFX11-NEXT: s_setpc_b64 s[30:31]1631 %cmp = icmp eq i32 %b, 01632 br i1 %cmp, label %cmp.true, label %cmp.false1633 1634cmp.true:1635 %a1 = fadd <7 x double> %a, splat (double 1.000000e+00)1636 %a2 = bitcast <7 x double> %a1 to <14 x i32>1637 br label %end1638 1639cmp.false:1640 %a3 = bitcast <7 x double> %a to <14 x i32>1641 br label %end1642 1643end:1644 %phi = phi <14 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]1645 ret <14 x i32> %phi1646}1647 1648define inreg <14 x i32> @bitcast_v7f64_to_v14i32_scalar(<7 x double> inreg %a, i32 inreg %b) {1649; SI-LABEL: bitcast_v7f64_to_v14i32_scalar:1650; SI: ; %bb.0:1651; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1652; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v01653; SI-NEXT: s_and_b64 s[4:5], vcc, exec1654; SI-NEXT: s_cbranch_scc0 .LBB11_31655; SI-NEXT: ; %bb.1: ; %cmp.false1656; SI-NEXT: s_cbranch_execnz .LBB11_41657; SI-NEXT: .LBB11_2: ; %cmp.true1658; SI-NEXT: v_add_f64 v[12:13], s[28:29], 1.01659; SI-NEXT: v_add_f64 v[10:11], s[26:27], 1.01660; SI-NEXT: v_add_f64 v[8:9], s[24:25], 1.01661; SI-NEXT: v_add_f64 v[6:7], s[22:23], 1.01662; SI-NEXT: v_add_f64 v[4:5], s[20:21], 1.01663; SI-NEXT: v_add_f64 v[2:3], s[18:19], 1.01664; SI-NEXT: v_add_f64 v[0:1], s[16:17], 1.01665; SI-NEXT: s_setpc_b64 s[30:31]1666; SI-NEXT: .LBB11_3:1667; SI-NEXT: s_branch .LBB11_21668; SI-NEXT: .LBB11_4:1669; SI-NEXT: v_mov_b32_e32 v0, s161670; SI-NEXT: v_mov_b32_e32 v1, s171671; SI-NEXT: v_mov_b32_e32 v2, s181672; SI-NEXT: v_mov_b32_e32 v3, s191673; SI-NEXT: v_mov_b32_e32 v4, s201674; SI-NEXT: v_mov_b32_e32 v5, s211675; SI-NEXT: v_mov_b32_e32 v6, s221676; SI-NEXT: v_mov_b32_e32 v7, s231677; SI-NEXT: v_mov_b32_e32 v8, s241678; SI-NEXT: v_mov_b32_e32 v9, s251679; SI-NEXT: v_mov_b32_e32 v10, s261680; SI-NEXT: v_mov_b32_e32 v11, s271681; SI-NEXT: v_mov_b32_e32 v12, s281682; SI-NEXT: v_mov_b32_e32 v13, s291683; SI-NEXT: v_mov_b32_e32 v14, s301684; SI-NEXT: v_mov_b32_e32 v15, s311685; SI-NEXT: s_setpc_b64 s[30:31]1686;1687; VI-LABEL: bitcast_v7f64_to_v14i32_scalar:1688; VI: ; %bb.0:1689; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1690; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v01691; VI-NEXT: s_and_b64 s[4:5], vcc, exec1692; VI-NEXT: s_cbranch_scc0 .LBB11_31693; VI-NEXT: ; %bb.1: ; %cmp.false1694; VI-NEXT: s_cbranch_execnz .LBB11_41695; VI-NEXT: .LBB11_2: ; %cmp.true1696; VI-NEXT: v_add_f64 v[12:13], s[28:29], 1.01697; VI-NEXT: v_add_f64 v[10:11], s[26:27], 1.01698; VI-NEXT: v_add_f64 v[8:9], s[24:25], 1.01699; VI-NEXT: v_add_f64 v[6:7], s[22:23], 1.01700; VI-NEXT: v_add_f64 v[4:5], s[20:21], 1.01701; VI-NEXT: v_add_f64 v[2:3], s[18:19], 1.01702; VI-NEXT: v_add_f64 v[0:1], s[16:17], 1.01703; VI-NEXT: s_setpc_b64 s[30:31]1704; VI-NEXT: .LBB11_3:1705; VI-NEXT: s_branch .LBB11_21706; VI-NEXT: .LBB11_4:1707; VI-NEXT: v_mov_b32_e32 v0, s161708; VI-NEXT: v_mov_b32_e32 v1, s171709; VI-NEXT: v_mov_b32_e32 v2, s181710; VI-NEXT: v_mov_b32_e32 v3, s191711; VI-NEXT: v_mov_b32_e32 v4, s201712; VI-NEXT: v_mov_b32_e32 v5, s211713; VI-NEXT: v_mov_b32_e32 v6, s221714; VI-NEXT: v_mov_b32_e32 v7, s231715; VI-NEXT: v_mov_b32_e32 v8, s241716; VI-NEXT: v_mov_b32_e32 v9, s251717; VI-NEXT: v_mov_b32_e32 v10, s261718; VI-NEXT: v_mov_b32_e32 v11, s271719; VI-NEXT: v_mov_b32_e32 v12, s281720; VI-NEXT: v_mov_b32_e32 v13, s291721; VI-NEXT: v_mov_b32_e32 v14, s301722; VI-NEXT: v_mov_b32_e32 v15, s311723; VI-NEXT: s_setpc_b64 s[30:31]1724;1725; GFX9-LABEL: bitcast_v7f64_to_v14i32_scalar:1726; GFX9: ; %bb.0:1727; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1728; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v01729; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec1730; GFX9-NEXT: s_cbranch_scc0 .LBB11_31731; GFX9-NEXT: ; %bb.1: ; %cmp.false1732; GFX9-NEXT: s_cbranch_execnz .LBB11_41733; GFX9-NEXT: .LBB11_2: ; %cmp.true1734; GFX9-NEXT: v_add_f64 v[12:13], s[28:29], 1.01735; GFX9-NEXT: v_add_f64 v[10:11], s[26:27], 1.01736; GFX9-NEXT: v_add_f64 v[8:9], s[24:25], 1.01737; GFX9-NEXT: v_add_f64 v[6:7], s[22:23], 1.01738; GFX9-NEXT: v_add_f64 v[4:5], s[20:21], 1.01739; GFX9-NEXT: v_add_f64 v[2:3], s[18:19], 1.01740; GFX9-NEXT: v_add_f64 v[0:1], s[16:17], 1.01741; GFX9-NEXT: s_setpc_b64 s[30:31]1742; GFX9-NEXT: .LBB11_3:1743; GFX9-NEXT: s_branch .LBB11_21744; GFX9-NEXT: .LBB11_4:1745; GFX9-NEXT: v_mov_b32_e32 v0, s161746; GFX9-NEXT: v_mov_b32_e32 v1, s171747; GFX9-NEXT: v_mov_b32_e32 v2, s181748; GFX9-NEXT: v_mov_b32_e32 v3, s191749; GFX9-NEXT: v_mov_b32_e32 v4, s201750; GFX9-NEXT: v_mov_b32_e32 v5, s211751; GFX9-NEXT: v_mov_b32_e32 v6, s221752; GFX9-NEXT: v_mov_b32_e32 v7, s231753; GFX9-NEXT: v_mov_b32_e32 v8, s241754; GFX9-NEXT: v_mov_b32_e32 v9, s251755; GFX9-NEXT: v_mov_b32_e32 v10, s261756; GFX9-NEXT: v_mov_b32_e32 v11, s271757; GFX9-NEXT: v_mov_b32_e32 v12, s281758; GFX9-NEXT: v_mov_b32_e32 v13, s291759; GFX9-NEXT: v_mov_b32_e32 v14, s301760; GFX9-NEXT: v_mov_b32_e32 v15, s311761; GFX9-NEXT: s_setpc_b64 s[30:31]1762;1763; GFX11-LABEL: bitcast_v7f64_to_v14i32_scalar:1764; GFX11: ; %bb.0:1765; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1766; GFX11-NEXT: s_mov_b32 s15, s31767; GFX11-NEXT: s_mov_b32 s14, s21768; GFX11-NEXT: s_mov_b32 s13, s11769; GFX11-NEXT: s_mov_b32 s12, s01770; GFX11-NEXT: s_cmp_lg_u32 s26, 01771; GFX11-NEXT: s_mov_b32 s0, 01772; GFX11-NEXT: s_cbranch_scc0 .LBB11_31773; GFX11-NEXT: ; %bb.1: ; %Flow1774; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s01775; GFX11-NEXT: s_cbranch_vccnz .LBB11_41776; GFX11-NEXT: .LBB11_2: ; %cmp.true1777; GFX11-NEXT: v_add_f64 v[12:13], s[24:25], 1.01778; GFX11-NEXT: v_add_f64 v[10:11], s[22:23], 1.01779; GFX11-NEXT: v_add_f64 v[8:9], s[20:21], 1.01780; GFX11-NEXT: v_add_f64 v[6:7], s[18:19], 1.01781; GFX11-NEXT: v_add_f64 v[4:5], s[16:17], 1.01782; GFX11-NEXT: v_add_f64 v[2:3], s[14:15], 1.01783; GFX11-NEXT: v_add_f64 v[0:1], s[12:13], 1.01784; GFX11-NEXT: s_setpc_b64 s[30:31]1785; GFX11-NEXT: .LBB11_3:1786; GFX11-NEXT: s_branch .LBB11_21787; GFX11-NEXT: .LBB11_4:1788; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s131789; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s151790; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s171791; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s191792; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s211793; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s231794; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s251795; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s271796; GFX11-NEXT: s_setpc_b64 s[30:31]1797 %cmp = icmp eq i32 %b, 01798 br i1 %cmp, label %cmp.true, label %cmp.false1799 1800cmp.true:1801 %a1 = fadd <7 x double> %a, splat (double 1.000000e+00)1802 %a2 = bitcast <7 x double> %a1 to <14 x i32>1803 br label %end1804 1805cmp.false:1806 %a3 = bitcast <7 x double> %a to <14 x i32>1807 br label %end1808 1809end:1810 %phi = phi <14 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]1811 ret <14 x i32> %phi1812}1813 1814define <28 x i16> @bitcast_v14i32_to_v28i16(<14 x i32> %a, i32 %b) {1815; SI-LABEL: bitcast_v14i32_to_v28i16:1816; SI: ; %bb.0:1817; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1818; SI-NEXT: v_mov_b32_e32 v26, v131819; SI-NEXT: v_mov_b32_e32 v24, v121820; SI-NEXT: v_mov_b32_e32 v22, v111821; SI-NEXT: v_mov_b32_e32 v20, v101822; SI-NEXT: v_mov_b32_e32 v18, v91823; SI-NEXT: v_mov_b32_e32 v16, v81824; SI-NEXT: v_mov_b32_e32 v28, v71825; SI-NEXT: v_mov_b32_e32 v12, v61826; SI-NEXT: v_mov_b32_e32 v10, v51827; SI-NEXT: v_mov_b32_e32 v8, v41828; SI-NEXT: v_mov_b32_e32 v6, v31829; SI-NEXT: v_mov_b32_e32 v4, v21830; SI-NEXT: v_mov_b32_e32 v2, v11831; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v141832; SI-NEXT: ; implicit-def: $vgpr11833; SI-NEXT: ; implicit-def: $vgpr31834; SI-NEXT: ; implicit-def: $vgpr51835; SI-NEXT: ; implicit-def: $vgpr71836; SI-NEXT: ; implicit-def: $vgpr91837; SI-NEXT: ; implicit-def: $vgpr111838; SI-NEXT: ; implicit-def: $vgpr131839; SI-NEXT: ; implicit-def: $vgpr151840; SI-NEXT: ; implicit-def: $vgpr171841; SI-NEXT: ; implicit-def: $vgpr191842; SI-NEXT: ; implicit-def: $vgpr211843; SI-NEXT: ; implicit-def: $vgpr231844; SI-NEXT: ; implicit-def: $vgpr251845; SI-NEXT: ; implicit-def: $vgpr271846; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc1847; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]1848; SI-NEXT: s_cbranch_execz .LBB12_21849; SI-NEXT: ; %bb.1: ; %cmp.false1850; SI-NEXT: v_alignbit_b32 v25, v26, v24, 161851; SI-NEXT: v_alignbit_b32 v21, v22, v20, 161852; SI-NEXT: v_alignbit_b32 v17, v18, v16, 161853; SI-NEXT: v_alignbit_b32 v13, v28, v12, 161854; SI-NEXT: v_alignbit_b32 v9, v10, v8, 161855; SI-NEXT: v_alignbit_b32 v5, v6, v4, 161856; SI-NEXT: v_alignbit_b32 v1, v2, v0, 161857; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v261858; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v221859; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v181860; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v281861; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v101862; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v61863; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v21864; SI-NEXT: .LBB12_2: ; %Flow1865; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1866; SI-NEXT: s_cbranch_execz .LBB12_41867; SI-NEXT: ; %bb.3: ; %cmp.true1868; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v21869; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v01870; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v61871; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v41872; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v101873; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v81874; SI-NEXT: v_add_i32_e32 v28, vcc, 3, v281875; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v121876; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v181877; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v161878; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v221879; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v201880; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v261881; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v241882; SI-NEXT: v_alignbit_b32 v25, v26, v24, 161883; SI-NEXT: v_alignbit_b32 v21, v22, v20, 161884; SI-NEXT: v_alignbit_b32 v17, v18, v16, 161885; SI-NEXT: v_alignbit_b32 v13, v28, v12, 161886; SI-NEXT: v_alignbit_b32 v9, v10, v8, 161887; SI-NEXT: v_alignbit_b32 v5, v6, v4, 161888; SI-NEXT: v_alignbit_b32 v1, v2, v0, 161889; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v261890; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v221891; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v181892; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v281893; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v101894; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v61895; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v21896; SI-NEXT: .LBB12_4: ; %end1897; SI-NEXT: s_or_b64 exec, exec, s[4:5]1898; SI-NEXT: v_mov_b32_e32 v14, v281899; SI-NEXT: s_setpc_b64 s[30:31]1900;1901; VI-LABEL: bitcast_v14i32_to_v28i16:1902; VI: ; %bb.0:1903; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1904; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v141905; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc1906; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]1907; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1908; VI-NEXT: s_cbranch_execz .LBB12_21909; VI-NEXT: ; %bb.1: ; %cmp.true1910; VI-NEXT: v_add_u32_e32 v13, vcc, 3, v131911; VI-NEXT: v_add_u32_e32 v12, vcc, 3, v121912; VI-NEXT: v_add_u32_e32 v11, vcc, 3, v111913; VI-NEXT: v_add_u32_e32 v10, vcc, 3, v101914; VI-NEXT: v_add_u32_e32 v9, vcc, 3, v91915; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v81916; VI-NEXT: v_add_u32_e32 v7, vcc, 3, v71917; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v61918; VI-NEXT: v_add_u32_e32 v5, vcc, 3, v51919; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v41920; VI-NEXT: v_add_u32_e32 v3, vcc, 3, v31921; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v21922; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v11923; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v01924; VI-NEXT: .LBB12_2: ; %end1925; VI-NEXT: s_or_b64 exec, exec, s[4:5]1926; VI-NEXT: s_setpc_b64 s[30:31]1927;1928; GFX9-LABEL: bitcast_v14i32_to_v28i16:1929; GFX9: ; %bb.0:1930; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1931; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v141932; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc1933; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]1934; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1935; GFX9-NEXT: s_cbranch_execz .LBB12_21936; GFX9-NEXT: ; %bb.1: ; %cmp.true1937; GFX9-NEXT: v_add_u32_e32 v13, 3, v131938; GFX9-NEXT: v_add_u32_e32 v12, 3, v121939; GFX9-NEXT: v_add_u32_e32 v11, 3, v111940; GFX9-NEXT: v_add_u32_e32 v10, 3, v101941; GFX9-NEXT: v_add_u32_e32 v9, 3, v91942; GFX9-NEXT: v_add_u32_e32 v8, 3, v81943; GFX9-NEXT: v_add_u32_e32 v7, 3, v71944; GFX9-NEXT: v_add_u32_e32 v6, 3, v61945; GFX9-NEXT: v_add_u32_e32 v5, 3, v51946; GFX9-NEXT: v_add_u32_e32 v4, 3, v41947; GFX9-NEXT: v_add_u32_e32 v3, 3, v31948; GFX9-NEXT: v_add_u32_e32 v2, 3, v21949; GFX9-NEXT: v_add_u32_e32 v1, 3, v11950; GFX9-NEXT: v_add_u32_e32 v0, 3, v01951; GFX9-NEXT: .LBB12_2: ; %end1952; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]1953; GFX9-NEXT: s_setpc_b64 s[30:31]1954;1955; GFX11-LABEL: bitcast_v14i32_to_v28i16:1956; GFX11: ; %bb.0:1957; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1958; GFX11-NEXT: s_mov_b32 s0, exec_lo1959; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v141960; GFX11-NEXT: s_xor_b32 s0, exec_lo, s01961; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)1962; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s01963; GFX11-NEXT: s_cbranch_execz .LBB12_21964; GFX11-NEXT: ; %bb.1: ; %cmp.true1965; GFX11-NEXT: v_add_nc_u32_e32 v13, 3, v131966; GFX11-NEXT: v_add_nc_u32_e32 v12, 3, v121967; GFX11-NEXT: v_add_nc_u32_e32 v11, 3, v111968; GFX11-NEXT: v_add_nc_u32_e32 v10, 3, v101969; GFX11-NEXT: v_add_nc_u32_e32 v9, 3, v91970; GFX11-NEXT: v_add_nc_u32_e32 v8, 3, v81971; GFX11-NEXT: v_add_nc_u32_e32 v7, 3, v71972; GFX11-NEXT: v_add_nc_u32_e32 v6, 3, v61973; GFX11-NEXT: v_add_nc_u32_e32 v5, 3, v51974; GFX11-NEXT: v_add_nc_u32_e32 v4, 3, v41975; GFX11-NEXT: v_add_nc_u32_e32 v3, 3, v31976; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v21977; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v11978; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v01979; GFX11-NEXT: .LBB12_2: ; %end1980; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s01981; GFX11-NEXT: s_setpc_b64 s[30:31]1982 %cmp = icmp eq i32 %b, 01983 br i1 %cmp, label %cmp.true, label %cmp.false1984 1985cmp.true:1986 %a1 = add <14 x i32> %a, splat (i32 3)1987 %a2 = bitcast <14 x i32> %a1 to <28 x i16>1988 br label %end1989 1990cmp.false:1991 %a3 = bitcast <14 x i32> %a to <28 x i16>1992 br label %end1993 1994end:1995 %phi = phi <28 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]1996 ret <28 x i16> %phi1997}1998 1999define inreg <28 x i16> @bitcast_v14i32_to_v28i16_scalar(<14 x i32> inreg %a, i32 inreg %b) {2000; SI-LABEL: bitcast_v14i32_to_v28i16_scalar:2001; SI: ; %bb.0:2002; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2003; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v02004; SI-NEXT: s_and_b64 s[4:5], vcc, exec2005; SI-NEXT: s_cbranch_scc0 .LBB13_42006; SI-NEXT: ; %bb.1: ; %cmp.false2007; SI-NEXT: s_lshr_b32 s44, s29, 162008; SI-NEXT: s_lshr_b32 s45, s27, 162009; SI-NEXT: s_lshr_b32 s46, s25, 162010; SI-NEXT: s_lshr_b32 s47, s23, 162011; SI-NEXT: s_lshr_b32 s56, s21, 162012; SI-NEXT: s_lshr_b32 s57, s19, 162013; SI-NEXT: s_lshr_b32 s58, s17, 162014; SI-NEXT: s_lshr_b64 s[4:5], s[28:29], 162015; SI-NEXT: s_lshr_b64 s[6:7], s[26:27], 162016; SI-NEXT: s_lshr_b64 s[8:9], s[24:25], 162017; SI-NEXT: s_lshr_b64 s[10:11], s[22:23], 162018; SI-NEXT: s_lshr_b64 s[12:13], s[20:21], 162019; SI-NEXT: s_lshr_b64 s[14:15], s[18:19], 162020; SI-NEXT: s_lshr_b64 s[40:41], s[16:17], 162021; SI-NEXT: s_cbranch_execnz .LBB13_32022; SI-NEXT: .LBB13_2: ; %cmp.true2023; SI-NEXT: s_add_i32 s17, s17, 32024; SI-NEXT: s_add_i32 s16, s16, 32025; SI-NEXT: s_add_i32 s19, s19, 32026; SI-NEXT: s_add_i32 s18, s18, 32027; SI-NEXT: s_add_i32 s21, s21, 32028; SI-NEXT: s_add_i32 s20, s20, 32029; SI-NEXT: s_add_i32 s23, s23, 32030; SI-NEXT: s_add_i32 s22, s22, 32031; SI-NEXT: s_add_i32 s25, s25, 32032; SI-NEXT: s_add_i32 s24, s24, 32033; SI-NEXT: s_add_i32 s27, s27, 32034; SI-NEXT: s_add_i32 s26, s26, 32035; SI-NEXT: s_add_i32 s29, s29, 32036; SI-NEXT: s_add_i32 s28, s28, 32037; SI-NEXT: s_lshr_b64 s[4:5], s[28:29], 162038; SI-NEXT: s_lshr_b64 s[6:7], s[26:27], 162039; SI-NEXT: s_lshr_b64 s[8:9], s[24:25], 162040; SI-NEXT: s_lshr_b64 s[10:11], s[22:23], 162041; SI-NEXT: s_lshr_b64 s[12:13], s[20:21], 162042; SI-NEXT: s_lshr_b64 s[14:15], s[18:19], 162043; SI-NEXT: s_lshr_b64 s[40:41], s[16:17], 162044; SI-NEXT: s_lshr_b32 s44, s29, 162045; SI-NEXT: s_lshr_b32 s45, s27, 162046; SI-NEXT: s_lshr_b32 s46, s25, 162047; SI-NEXT: s_lshr_b32 s47, s23, 162048; SI-NEXT: s_lshr_b32 s56, s21, 162049; SI-NEXT: s_lshr_b32 s57, s19, 162050; SI-NEXT: s_lshr_b32 s58, s17, 162051; SI-NEXT: .LBB13_3: ; %end2052; SI-NEXT: v_mov_b32_e32 v0, s162053; SI-NEXT: v_mov_b32_e32 v1, s402054; SI-NEXT: v_mov_b32_e32 v2, s172055; SI-NEXT: v_mov_b32_e32 v3, s582056; SI-NEXT: v_mov_b32_e32 v4, s182057; SI-NEXT: v_mov_b32_e32 v5, s142058; SI-NEXT: v_mov_b32_e32 v6, s192059; SI-NEXT: v_mov_b32_e32 v7, s572060; SI-NEXT: v_mov_b32_e32 v8, s202061; SI-NEXT: v_mov_b32_e32 v9, s122062; SI-NEXT: v_mov_b32_e32 v10, s212063; SI-NEXT: v_mov_b32_e32 v11, s562064; SI-NEXT: v_mov_b32_e32 v12, s222065; SI-NEXT: v_mov_b32_e32 v13, s102066; SI-NEXT: v_mov_b32_e32 v14, s232067; SI-NEXT: v_mov_b32_e32 v15, s472068; SI-NEXT: v_mov_b32_e32 v16, s242069; SI-NEXT: v_mov_b32_e32 v17, s82070; SI-NEXT: v_mov_b32_e32 v18, s252071; SI-NEXT: v_mov_b32_e32 v19, s462072; SI-NEXT: v_mov_b32_e32 v20, s262073; SI-NEXT: v_mov_b32_e32 v21, s62074; SI-NEXT: v_mov_b32_e32 v22, s272075; SI-NEXT: v_mov_b32_e32 v23, s452076; SI-NEXT: v_mov_b32_e32 v24, s282077; SI-NEXT: v_mov_b32_e32 v25, s42078; SI-NEXT: v_mov_b32_e32 v26, s292079; SI-NEXT: v_mov_b32_e32 v27, s442080; SI-NEXT: s_setpc_b64 s[30:31]2081; SI-NEXT: .LBB13_4:2082; SI-NEXT: ; implicit-def: $sgpr402083; SI-NEXT: ; implicit-def: $sgpr582084; SI-NEXT: ; implicit-def: $sgpr142085; SI-NEXT: ; implicit-def: $sgpr572086; SI-NEXT: ; implicit-def: $sgpr122087; SI-NEXT: ; implicit-def: $sgpr562088; SI-NEXT: ; implicit-def: $sgpr102089; SI-NEXT: ; implicit-def: $sgpr472090; SI-NEXT: ; implicit-def: $sgpr82091; SI-NEXT: ; implicit-def: $sgpr462092; SI-NEXT: ; implicit-def: $sgpr62093; SI-NEXT: ; implicit-def: $sgpr452094; SI-NEXT: ; implicit-def: $sgpr42095; SI-NEXT: ; implicit-def: $sgpr442096; SI-NEXT: s_branch .LBB13_22097;2098; VI-LABEL: bitcast_v14i32_to_v28i16_scalar:2099; VI: ; %bb.0:2100; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2101; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v02102; VI-NEXT: s_and_b64 s[4:5], vcc, exec2103; VI-NEXT: s_cbranch_scc0 .LBB13_42104; VI-NEXT: ; %bb.1: ; %cmp.false2105; VI-NEXT: s_cbranch_execnz .LBB13_32106; VI-NEXT: .LBB13_2: ; %cmp.true2107; VI-NEXT: s_add_i32 s29, s29, 32108; VI-NEXT: s_add_i32 s28, s28, 32109; VI-NEXT: s_add_i32 s27, s27, 32110; VI-NEXT: s_add_i32 s26, s26, 32111; VI-NEXT: s_add_i32 s25, s25, 32112; VI-NEXT: s_add_i32 s24, s24, 32113; VI-NEXT: s_add_i32 s23, s23, 32114; VI-NEXT: s_add_i32 s22, s22, 32115; VI-NEXT: s_add_i32 s21, s21, 32116; VI-NEXT: s_add_i32 s20, s20, 32117; VI-NEXT: s_add_i32 s19, s19, 32118; VI-NEXT: s_add_i32 s18, s18, 32119; VI-NEXT: s_add_i32 s17, s17, 32120; VI-NEXT: s_add_i32 s16, s16, 32121; VI-NEXT: .LBB13_3: ; %end2122; VI-NEXT: v_mov_b32_e32 v0, s162123; VI-NEXT: v_mov_b32_e32 v1, s172124; VI-NEXT: v_mov_b32_e32 v2, s182125; VI-NEXT: v_mov_b32_e32 v3, s192126; VI-NEXT: v_mov_b32_e32 v4, s202127; VI-NEXT: v_mov_b32_e32 v5, s212128; VI-NEXT: v_mov_b32_e32 v6, s222129; VI-NEXT: v_mov_b32_e32 v7, s232130; VI-NEXT: v_mov_b32_e32 v8, s242131; VI-NEXT: v_mov_b32_e32 v9, s252132; VI-NEXT: v_mov_b32_e32 v10, s262133; VI-NEXT: v_mov_b32_e32 v11, s272134; VI-NEXT: v_mov_b32_e32 v12, s282135; VI-NEXT: v_mov_b32_e32 v13, s292136; VI-NEXT: s_setpc_b64 s[30:31]2137; VI-NEXT: .LBB13_4:2138; VI-NEXT: s_branch .LBB13_22139;2140; GFX9-LABEL: bitcast_v14i32_to_v28i16_scalar:2141; GFX9: ; %bb.0:2142; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2143; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v02144; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec2145; GFX9-NEXT: s_cbranch_scc0 .LBB13_42146; GFX9-NEXT: ; %bb.1: ; %cmp.false2147; GFX9-NEXT: s_cbranch_execnz .LBB13_32148; GFX9-NEXT: .LBB13_2: ; %cmp.true2149; GFX9-NEXT: s_add_i32 s29, s29, 32150; GFX9-NEXT: s_add_i32 s28, s28, 32151; GFX9-NEXT: s_add_i32 s27, s27, 32152; GFX9-NEXT: s_add_i32 s26, s26, 32153; GFX9-NEXT: s_add_i32 s25, s25, 32154; GFX9-NEXT: s_add_i32 s24, s24, 32155; GFX9-NEXT: s_add_i32 s23, s23, 32156; GFX9-NEXT: s_add_i32 s22, s22, 32157; GFX9-NEXT: s_add_i32 s21, s21, 32158; GFX9-NEXT: s_add_i32 s20, s20, 32159; GFX9-NEXT: s_add_i32 s19, s19, 32160; GFX9-NEXT: s_add_i32 s18, s18, 32161; GFX9-NEXT: s_add_i32 s17, s17, 32162; GFX9-NEXT: s_add_i32 s16, s16, 32163; GFX9-NEXT: .LBB13_3: ; %end2164; GFX9-NEXT: v_mov_b32_e32 v0, s162165; GFX9-NEXT: v_mov_b32_e32 v1, s172166; GFX9-NEXT: v_mov_b32_e32 v2, s182167; GFX9-NEXT: v_mov_b32_e32 v3, s192168; GFX9-NEXT: v_mov_b32_e32 v4, s202169; GFX9-NEXT: v_mov_b32_e32 v5, s212170; GFX9-NEXT: v_mov_b32_e32 v6, s222171; GFX9-NEXT: v_mov_b32_e32 v7, s232172; GFX9-NEXT: v_mov_b32_e32 v8, s242173; GFX9-NEXT: v_mov_b32_e32 v9, s252174; GFX9-NEXT: v_mov_b32_e32 v10, s262175; GFX9-NEXT: v_mov_b32_e32 v11, s272176; GFX9-NEXT: v_mov_b32_e32 v12, s282177; GFX9-NEXT: v_mov_b32_e32 v13, s292178; GFX9-NEXT: s_setpc_b64 s[30:31]2179; GFX9-NEXT: .LBB13_4:2180; GFX9-NEXT: s_branch .LBB13_22181;2182; GFX11-LABEL: bitcast_v14i32_to_v28i16_scalar:2183; GFX11: ; %bb.0:2184; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2185; GFX11-NEXT: s_cmp_lg_u32 s26, 02186; GFX11-NEXT: s_mov_b32 s4, 02187; GFX11-NEXT: s_cbranch_scc0 .LBB13_42188; GFX11-NEXT: ; %bb.1: ; %Flow2189; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42190; GFX11-NEXT: s_cbranch_vccnz .LBB13_32191; GFX11-NEXT: .LBB13_2: ; %cmp.true2192; GFX11-NEXT: s_add_i32 s25, s25, 32193; GFX11-NEXT: s_add_i32 s24, s24, 32194; GFX11-NEXT: s_add_i32 s23, s23, 32195; GFX11-NEXT: s_add_i32 s22, s22, 32196; GFX11-NEXT: s_add_i32 s21, s21, 32197; GFX11-NEXT: s_add_i32 s20, s20, 32198; GFX11-NEXT: s_add_i32 s19, s19, 32199; GFX11-NEXT: s_add_i32 s18, s18, 32200; GFX11-NEXT: s_add_i32 s17, s17, 32201; GFX11-NEXT: s_add_i32 s16, s16, 32202; GFX11-NEXT: s_add_i32 s3, s3, 32203; GFX11-NEXT: s_add_i32 s2, s2, 32204; GFX11-NEXT: s_add_i32 s1, s1, 32205; GFX11-NEXT: s_add_i32 s0, s0, 32206; GFX11-NEXT: .LBB13_3: ; %end2207; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)2208; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s12209; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s32210; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s172211; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s192212; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s212213; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s232214; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s252215; GFX11-NEXT: s_setpc_b64 s[30:31]2216; GFX11-NEXT: .LBB13_4:2217; GFX11-NEXT: s_branch .LBB13_22218 %cmp = icmp eq i32 %b, 02219 br i1 %cmp, label %cmp.true, label %cmp.false2220 2221cmp.true:2222 %a1 = add <14 x i32> %a, splat (i32 3)2223 %a2 = bitcast <14 x i32> %a1 to <28 x i16>2224 br label %end2225 2226cmp.false:2227 %a3 = bitcast <14 x i32> %a to <28 x i16>2228 br label %end2229 2230end:2231 %phi = phi <28 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]2232 ret <28 x i16> %phi2233}2234 2235define <14 x i32> @bitcast_v28i16_to_v14i32(<28 x i16> %a, i32 %b) {2236; SI-LABEL: bitcast_v28i16_to_v14i32:2237; SI: ; %bb.0:2238; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2239; SI-NEXT: v_mov_b32_e32 v36, v142240; SI-NEXT: v_mov_b32_e32 v35, v122241; SI-NEXT: v_mov_b32_e32 v34, v102242; SI-NEXT: v_mov_b32_e32 v33, v82243; SI-NEXT: v_mov_b32_e32 v32, v62244; SI-NEXT: v_mov_b32_e32 v31, v42245; SI-NEXT: v_mov_b32_e32 v30, v22246; SI-NEXT: v_mov_b32_e32 v29, v02247; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v282248; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v12249; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v32250; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v52251; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v72252; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v92253; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v112254; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v132255; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v152256; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v172257; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v192258; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v212259; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v232260; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v252261; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v272262; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr152263; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc2264; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]2265; SI-NEXT: s_cbranch_execnz .LBB14_32266; SI-NEXT: ; %bb.1: ; %Flow2267; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]2268; SI-NEXT: s_cbranch_execnz .LBB14_42269; SI-NEXT: .LBB14_2: ; %end2270; SI-NEXT: s_or_b64 exec, exec, s[4:5]2271; SI-NEXT: s_setpc_b64 s[30:31]2272; SI-NEXT: .LBB14_3: ; %cmp.false2273; SI-NEXT: v_and_b32_e32 v0, 0xffff, v292274; SI-NEXT: v_and_b32_e32 v1, 0xffff, v302275; SI-NEXT: v_and_b32_e32 v2, 0xffff, v312276; SI-NEXT: v_and_b32_e32 v3, 0xffff, v322277; SI-NEXT: v_and_b32_e32 v4, 0xffff, v332278; SI-NEXT: v_and_b32_e32 v5, 0xffff, v342279; SI-NEXT: v_and_b32_e32 v6, 0xffff, v352280; SI-NEXT: v_and_b32_e32 v7, 0xffff, v362281; SI-NEXT: v_and_b32_e32 v8, 0xffff, v162282; SI-NEXT: v_and_b32_e32 v9, 0xffff, v182283; SI-NEXT: v_and_b32_e32 v10, 0xffff, v202284; SI-NEXT: v_and_b32_e32 v11, 0xffff, v222285; SI-NEXT: v_and_b32_e32 v12, 0xffff, v242286; SI-NEXT: v_and_b32_e32 v13, 0xffff, v262287; SI-NEXT: v_or_b32_e32 v0, v0, v542288; SI-NEXT: v_or_b32_e32 v1, v1, v532289; SI-NEXT: v_or_b32_e32 v2, v2, v522290; SI-NEXT: v_or_b32_e32 v3, v3, v512291; SI-NEXT: v_or_b32_e32 v4, v4, v502292; SI-NEXT: v_or_b32_e32 v5, v5, v492293; SI-NEXT: v_or_b32_e32 v6, v6, v482294; SI-NEXT: v_or_b32_e32 v7, v7, v392295; SI-NEXT: v_or_b32_e32 v8, v8, v382296; SI-NEXT: v_or_b32_e32 v9, v9, v372297; SI-NEXT: v_or_b32_e32 v10, v10, v282298; SI-NEXT: v_or_b32_e32 v11, v11, v212299; SI-NEXT: v_or_b32_e32 v12, v12, v192300; SI-NEXT: v_or_b32_e32 v13, v13, v172301; SI-NEXT: ; implicit-def: $vgpr292302; SI-NEXT: ; implicit-def: $vgpr302303; SI-NEXT: ; implicit-def: $vgpr312304; SI-NEXT: ; implicit-def: $vgpr322305; SI-NEXT: ; implicit-def: $vgpr332306; SI-NEXT: ; implicit-def: $vgpr342307; SI-NEXT: ; implicit-def: $vgpr352308; SI-NEXT: ; implicit-def: $vgpr362309; SI-NEXT: ; implicit-def: $vgpr162310; SI-NEXT: ; implicit-def: $vgpr182311; SI-NEXT: ; implicit-def: $vgpr202312; SI-NEXT: ; implicit-def: $vgpr222313; SI-NEXT: ; implicit-def: $vgpr242314; SI-NEXT: ; implicit-def: $vgpr262315; SI-NEXT: ; implicit-def: $vgpr542316; SI-NEXT: ; implicit-def: $vgpr532317; SI-NEXT: ; implicit-def: $vgpr522318; SI-NEXT: ; implicit-def: $vgpr512319; SI-NEXT: ; implicit-def: $vgpr502320; SI-NEXT: ; implicit-def: $vgpr492321; SI-NEXT: ; implicit-def: $vgpr482322; SI-NEXT: ; implicit-def: $vgpr392323; SI-NEXT: ; implicit-def: $vgpr382324; SI-NEXT: ; implicit-def: $vgpr372325; SI-NEXT: ; implicit-def: $vgpr282326; SI-NEXT: ; implicit-def: $vgpr212327; SI-NEXT: ; implicit-def: $vgpr192328; SI-NEXT: ; implicit-def: $vgpr172329; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]2330; SI-NEXT: s_cbranch_execz .LBB14_22331; SI-NEXT: .LBB14_4: ; %cmp.true2332; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v292333; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v302334; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v312335; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v322336; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v332337; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v342338; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v352339; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v362340; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v162341; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v182342; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v202343; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v222344; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v242345; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v262346; SI-NEXT: v_and_b32_e32 v0, 0xffff, v02347; SI-NEXT: v_and_b32_e32 v1, 0xffff, v12348; SI-NEXT: v_and_b32_e32 v2, 0xffff, v22349; SI-NEXT: v_and_b32_e32 v3, 0xffff, v32350; SI-NEXT: v_and_b32_e32 v4, 0xffff, v42351; SI-NEXT: v_and_b32_e32 v5, 0xffff, v52352; SI-NEXT: v_and_b32_e32 v6, 0xffff, v62353; SI-NEXT: v_and_b32_e32 v7, 0xffff, v72354; SI-NEXT: v_and_b32_e32 v8, 0xffff, v82355; SI-NEXT: v_and_b32_e32 v9, 0xffff, v92356; SI-NEXT: v_and_b32_e32 v10, 0xffff, v102357; SI-NEXT: v_and_b32_e32 v11, 0xffff, v112358; SI-NEXT: v_and_b32_e32 v12, 0xffff, v122359; SI-NEXT: v_and_b32_e32 v13, 0xffff, v132360; SI-NEXT: v_or_b32_e32 v0, v54, v02361; SI-NEXT: s_mov_b32 s6, 0x300002362; SI-NEXT: v_or_b32_e32 v1, v53, v12363; SI-NEXT: v_or_b32_e32 v2, v52, v22364; SI-NEXT: v_or_b32_e32 v3, v51, v32365; SI-NEXT: v_or_b32_e32 v4, v50, v42366; SI-NEXT: v_or_b32_e32 v5, v49, v52367; SI-NEXT: v_or_b32_e32 v6, v48, v62368; SI-NEXT: v_or_b32_e32 v7, v39, v72369; SI-NEXT: v_or_b32_e32 v8, v38, v82370; SI-NEXT: v_or_b32_e32 v9, v37, v92371; SI-NEXT: v_or_b32_e32 v10, v28, v102372; SI-NEXT: v_or_b32_e32 v11, v21, v112373; SI-NEXT: v_or_b32_e32 v12, v19, v122374; SI-NEXT: v_or_b32_e32 v13, v17, v132375; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v02376; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v12377; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v22378; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v32379; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v42380; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v52381; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v62382; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v72383; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v82384; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v92385; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v102386; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v112387; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v122388; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v132389; SI-NEXT: s_or_b64 exec, exec, s[4:5]2390; SI-NEXT: s_setpc_b64 s[30:31]2391;2392; VI-LABEL: bitcast_v28i16_to_v14i32:2393; VI: ; %bb.0:2394; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2395; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v142396; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc2397; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]2398; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]2399; VI-NEXT: s_cbranch_execz .LBB14_22400; VI-NEXT: ; %bb.1: ; %cmp.true2401; VI-NEXT: v_mov_b32_e32 v15, 32402; VI-NEXT: v_add_u16_e32 v14, 3, v132403; VI-NEXT: v_add_u16_sdwa v13, v13, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2404; VI-NEXT: v_or_b32_e32 v13, v14, v132405; VI-NEXT: v_add_u16_e32 v14, 3, v122406; VI-NEXT: v_add_u16_sdwa v12, v12, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2407; VI-NEXT: v_or_b32_e32 v12, v14, v122408; VI-NEXT: v_add_u16_e32 v14, 3, v112409; VI-NEXT: v_add_u16_sdwa v11, v11, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2410; VI-NEXT: v_or_b32_e32 v11, v14, v112411; VI-NEXT: v_add_u16_e32 v14, 3, v102412; VI-NEXT: v_add_u16_sdwa v10, v10, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2413; VI-NEXT: v_or_b32_e32 v10, v14, v102414; VI-NEXT: v_add_u16_e32 v14, 3, v92415; VI-NEXT: v_add_u16_sdwa v9, v9, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2416; VI-NEXT: v_or_b32_e32 v9, v14, v92417; VI-NEXT: v_add_u16_e32 v14, 3, v82418; VI-NEXT: v_add_u16_sdwa v8, v8, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2419; VI-NEXT: v_or_b32_e32 v8, v14, v82420; VI-NEXT: v_add_u16_e32 v14, 3, v72421; VI-NEXT: v_add_u16_sdwa v7, v7, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2422; VI-NEXT: v_or_b32_e32 v7, v14, v72423; VI-NEXT: v_add_u16_e32 v14, 3, v62424; VI-NEXT: v_add_u16_sdwa v6, v6, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2425; VI-NEXT: v_or_b32_e32 v6, v14, v62426; VI-NEXT: v_add_u16_e32 v14, 3, v52427; VI-NEXT: v_add_u16_sdwa v5, v5, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2428; VI-NEXT: v_or_b32_e32 v5, v14, v52429; VI-NEXT: v_add_u16_e32 v14, 3, v42430; VI-NEXT: v_add_u16_sdwa v4, v4, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2431; VI-NEXT: v_or_b32_e32 v4, v14, v42432; VI-NEXT: v_add_u16_e32 v14, 3, v32433; VI-NEXT: v_add_u16_sdwa v3, v3, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2434; VI-NEXT: v_or_b32_e32 v3, v14, v32435; VI-NEXT: v_add_u16_e32 v14, 3, v22436; VI-NEXT: v_add_u16_sdwa v2, v2, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2437; VI-NEXT: v_or_b32_e32 v2, v14, v22438; VI-NEXT: v_add_u16_e32 v14, 3, v12439; VI-NEXT: v_add_u16_sdwa v1, v1, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2440; VI-NEXT: v_or_b32_e32 v1, v14, v12441; VI-NEXT: v_add_u16_e32 v14, 3, v02442; VI-NEXT: v_add_u16_sdwa v0, v0, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2443; VI-NEXT: v_or_b32_e32 v0, v14, v02444; VI-NEXT: .LBB14_2: ; %end2445; VI-NEXT: s_or_b64 exec, exec, s[4:5]2446; VI-NEXT: s_setpc_b64 s[30:31]2447;2448; GFX9-LABEL: bitcast_v28i16_to_v14i32:2449; GFX9: ; %bb.0:2450; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2451; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v142452; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc2453; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]2454; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]2455; GFX9-NEXT: s_cbranch_execz .LBB14_22456; GFX9-NEXT: ; %bb.1: ; %cmp.true2457; GFX9-NEXT: v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0]2458; GFX9-NEXT: v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0]2459; GFX9-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]2460; GFX9-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]2461; GFX9-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]2462; GFX9-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]2463; GFX9-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]2464; GFX9-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]2465; GFX9-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]2466; GFX9-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]2467; GFX9-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]2468; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]2469; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]2470; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]2471; GFX9-NEXT: .LBB14_2: ; %end2472; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]2473; GFX9-NEXT: s_setpc_b64 s[30:31]2474;2475; GFX11-LABEL: bitcast_v28i16_to_v14i32:2476; GFX11: ; %bb.0:2477; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2478; GFX11-NEXT: s_mov_b32 s0, exec_lo2479; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v142480; GFX11-NEXT: s_xor_b32 s0, exec_lo, s02481; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)2482; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s02483; GFX11-NEXT: s_cbranch_execz .LBB14_22484; GFX11-NEXT: ; %bb.1: ; %cmp.true2485; GFX11-NEXT: v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0]2486; GFX11-NEXT: v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0]2487; GFX11-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]2488; GFX11-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]2489; GFX11-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]2490; GFX11-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]2491; GFX11-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]2492; GFX11-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]2493; GFX11-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]2494; GFX11-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]2495; GFX11-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]2496; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]2497; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]2498; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]2499; GFX11-NEXT: .LBB14_2: ; %end2500; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s02501; GFX11-NEXT: s_setpc_b64 s[30:31]2502 %cmp = icmp eq i32 %b, 02503 br i1 %cmp, label %cmp.true, label %cmp.false2504 2505cmp.true:2506 %a1 = add <28 x i16> %a, splat (i16 3)2507 %a2 = bitcast <28 x i16> %a1 to <14 x i32>2508 br label %end2509 2510cmp.false:2511 %a3 = bitcast <28 x i16> %a to <14 x i32>2512 br label %end2513 2514end:2515 %phi = phi <14 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]2516 ret <14 x i32> %phi2517}2518 2519define inreg <14 x i32> @bitcast_v28i16_to_v14i32_scalar(<28 x i16> inreg %a, i32 inreg %b) {2520; SI-LABEL: bitcast_v28i16_to_v14i32_scalar:2521; SI: ; %bb.0:2522; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2523; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v142524; SI-NEXT: v_mov_b32_e32 v16, v122525; SI-NEXT: v_mov_b32_e32 v17, v102526; SI-NEXT: v_mov_b32_e32 v18, v82527; SI-NEXT: v_mov_b32_e32 v19, v62528; SI-NEXT: v_mov_b32_e32 v20, v42529; SI-NEXT: v_mov_b32_e32 v21, v22530; SI-NEXT: v_mov_b32_e32 v22, v02531; SI-NEXT: s_and_b64 s[4:5], vcc, exec2532; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v12533; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v32534; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v52535; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v72536; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v92537; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v112538; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v132539; SI-NEXT: s_cbranch_scc0 .LBB15_42540; SI-NEXT: ; %bb.1: ; %cmp.false2541; SI-NEXT: s_and_b32 s4, s16, 0xffff2542; SI-NEXT: s_lshl_b32 s5, s17, 162543; SI-NEXT: s_or_b32 s4, s4, s52544; SI-NEXT: s_and_b32 s5, s18, 0xffff2545; SI-NEXT: s_lshl_b32 s6, s19, 162546; SI-NEXT: v_and_b32_e32 v0, 0xffff, v222547; SI-NEXT: s_or_b32 s5, s5, s62548; SI-NEXT: s_and_b32 s6, s20, 0xffff2549; SI-NEXT: s_lshl_b32 s7, s21, 162550; SI-NEXT: v_or_b32_e32 v7, v0, v292551; SI-NEXT: v_and_b32_e32 v0, 0xffff, v202552; SI-NEXT: s_or_b32 s6, s6, s72553; SI-NEXT: s_and_b32 s7, s22, 0xffff2554; SI-NEXT: s_lshl_b32 s8, s23, 162555; SI-NEXT: v_or_b32_e32 v9, v0, v272556; SI-NEXT: v_and_b32_e32 v0, 0xffff, v192557; SI-NEXT: s_or_b32 s7, s7, s82558; SI-NEXT: s_and_b32 s8, s24, 0xffff2559; SI-NEXT: s_lshl_b32 s9, s25, 162560; SI-NEXT: v_or_b32_e32 v10, v0, v262561; SI-NEXT: v_and_b32_e32 v0, 0xffff, v182562; SI-NEXT: s_or_b32 s8, s8, s92563; SI-NEXT: s_and_b32 s9, s26, 0xffff2564; SI-NEXT: s_lshl_b32 s10, s27, 162565; SI-NEXT: v_or_b32_e32 v11, v0, v252566; SI-NEXT: v_and_b32_e32 v0, 0xffff, v172567; SI-NEXT: s_or_b32 s9, s9, s102568; SI-NEXT: s_and_b32 s10, s28, 0xffff2569; SI-NEXT: s_lshl_b32 s11, s29, 162570; SI-NEXT: v_and_b32_e32 v1, 0xffff, v212571; SI-NEXT: v_or_b32_e32 v12, v0, v242572; SI-NEXT: v_and_b32_e32 v0, 0xffff, v162573; SI-NEXT: s_or_b32 s10, s10, s112574; SI-NEXT: v_or_b32_e32 v8, v1, v282575; SI-NEXT: v_or_b32_e32 v13, v0, v232576; SI-NEXT: v_mov_b32_e32 v0, s42577; SI-NEXT: v_mov_b32_e32 v1, s52578; SI-NEXT: v_mov_b32_e32 v2, s62579; SI-NEXT: v_mov_b32_e32 v3, s72580; SI-NEXT: v_mov_b32_e32 v4, s82581; SI-NEXT: v_mov_b32_e32 v5, s92582; SI-NEXT: v_mov_b32_e32 v6, s102583; SI-NEXT: s_cbranch_execnz .LBB15_32584; SI-NEXT: .LBB15_2: ; %cmp.true2585; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v222586; SI-NEXT: v_and_b32_e32 v0, 0xffff, v02587; SI-NEXT: v_or_b32_e32 v0, v29, v02588; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v02589; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v212590; SI-NEXT: v_and_b32_e32 v0, 0xffff, v02591; SI-NEXT: v_or_b32_e32 v0, v28, v02592; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v02593; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v202594; SI-NEXT: v_and_b32_e32 v0, 0xffff, v02595; SI-NEXT: v_or_b32_e32 v0, v27, v02596; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v02597; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v192598; SI-NEXT: v_and_b32_e32 v0, 0xffff, v02599; SI-NEXT: s_add_i32 s16, s16, 32600; SI-NEXT: v_or_b32_e32 v0, v26, v02601; SI-NEXT: s_and_b32 s4, s16, 0xffff2602; SI-NEXT: s_lshl_b32 s5, s17, 162603; SI-NEXT: s_add_i32 s18, s18, 32604; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v02605; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v182606; SI-NEXT: s_or_b32 s4, s5, s42607; SI-NEXT: s_and_b32 s5, s18, 0xffff2608; SI-NEXT: s_lshl_b32 s6, s19, 162609; SI-NEXT: s_add_i32 s20, s20, 32610; SI-NEXT: v_and_b32_e32 v0, 0xffff, v02611; SI-NEXT: s_or_b32 s5, s6, s52612; SI-NEXT: s_and_b32 s6, s20, 0xffff2613; SI-NEXT: s_lshl_b32 s7, s21, 162614; SI-NEXT: s_add_i32 s22, s22, 32615; SI-NEXT: v_or_b32_e32 v0, v25, v02616; SI-NEXT: s_or_b32 s6, s7, s62617; SI-NEXT: s_and_b32 s7, s22, 0xffff2618; SI-NEXT: s_lshl_b32 s8, s23, 162619; SI-NEXT: s_add_i32 s24, s24, 32620; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v02621; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v172622; SI-NEXT: s_or_b32 s7, s8, s72623; SI-NEXT: s_and_b32 s8, s24, 0xffff2624; SI-NEXT: s_lshl_b32 s9, s25, 162625; SI-NEXT: s_add_i32 s26, s26, 32626; SI-NEXT: v_and_b32_e32 v0, 0xffff, v02627; SI-NEXT: s_or_b32 s8, s9, s82628; SI-NEXT: s_and_b32 s9, s26, 0xffff2629; SI-NEXT: s_lshl_b32 s10, s27, 162630; SI-NEXT: s_add_i32 s28, s28, 32631; SI-NEXT: v_or_b32_e32 v0, v24, v02632; SI-NEXT: s_or_b32 s9, s10, s92633; SI-NEXT: s_and_b32 s10, s28, 0xffff2634; SI-NEXT: s_lshl_b32 s11, s29, 162635; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v02636; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v162637; SI-NEXT: s_or_b32 s10, s11, s102638; SI-NEXT: v_and_b32_e32 v0, 0xffff, v02639; SI-NEXT: s_add_i32 s4, s4, 0x300002640; SI-NEXT: s_add_i32 s5, s5, 0x300002641; SI-NEXT: s_add_i32 s6, s6, 0x300002642; SI-NEXT: s_add_i32 s7, s7, 0x300002643; SI-NEXT: s_add_i32 s8, s8, 0x300002644; SI-NEXT: s_add_i32 s9, s9, 0x300002645; SI-NEXT: s_add_i32 s10, s10, 0x300002646; SI-NEXT: v_or_b32_e32 v0, v23, v02647; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v02648; SI-NEXT: v_mov_b32_e32 v0, s42649; SI-NEXT: v_mov_b32_e32 v1, s52650; SI-NEXT: v_mov_b32_e32 v2, s62651; SI-NEXT: v_mov_b32_e32 v3, s72652; SI-NEXT: v_mov_b32_e32 v4, s82653; SI-NEXT: v_mov_b32_e32 v5, s92654; SI-NEXT: v_mov_b32_e32 v6, s102655; SI-NEXT: .LBB15_3: ; %end2656; SI-NEXT: s_setpc_b64 s[30:31]2657; SI-NEXT: .LBB15_4:2658; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr152659; SI-NEXT: s_branch .LBB15_22660;2661; VI-LABEL: bitcast_v28i16_to_v14i32_scalar:2662; VI: ; %bb.0:2663; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2664; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v02665; VI-NEXT: s_and_b64 s[4:5], vcc, exec2666; VI-NEXT: s_cbranch_scc0 .LBB15_42667; VI-NEXT: ; %bb.1: ; %cmp.false2668; VI-NEXT: s_cbranch_execnz .LBB15_32669; VI-NEXT: .LBB15_2: ; %cmp.true2670; VI-NEXT: s_add_i32 s5, s29, 32671; VI-NEXT: s_and_b32 s4, s29, 0xffff00002672; VI-NEXT: s_and_b32 s5, s5, 0xffff2673; VI-NEXT: s_or_b32 s4, s4, s52674; VI-NEXT: s_add_i32 s5, s28, 32675; VI-NEXT: s_add_i32 s29, s4, 0x300002676; VI-NEXT: s_and_b32 s4, s28, 0xffff00002677; VI-NEXT: s_and_b32 s5, s5, 0xffff2678; VI-NEXT: s_or_b32 s4, s4, s52679; VI-NEXT: s_add_i32 s5, s27, 32680; VI-NEXT: s_add_i32 s28, s4, 0x300002681; VI-NEXT: s_and_b32 s4, s27, 0xffff00002682; VI-NEXT: s_and_b32 s5, s5, 0xffff2683; VI-NEXT: s_or_b32 s4, s4, s52684; VI-NEXT: s_add_i32 s5, s26, 32685; VI-NEXT: s_add_i32 s27, s4, 0x300002686; VI-NEXT: s_and_b32 s4, s26, 0xffff00002687; VI-NEXT: s_and_b32 s5, s5, 0xffff2688; VI-NEXT: s_or_b32 s4, s4, s52689; VI-NEXT: s_add_i32 s5, s25, 32690; VI-NEXT: s_add_i32 s26, s4, 0x300002691; VI-NEXT: s_and_b32 s4, s25, 0xffff00002692; VI-NEXT: s_and_b32 s5, s5, 0xffff2693; VI-NEXT: s_or_b32 s4, s4, s52694; VI-NEXT: s_add_i32 s5, s24, 32695; VI-NEXT: s_add_i32 s25, s4, 0x300002696; VI-NEXT: s_and_b32 s4, s24, 0xffff00002697; VI-NEXT: s_and_b32 s5, s5, 0xffff2698; VI-NEXT: s_or_b32 s4, s4, s52699; VI-NEXT: s_add_i32 s5, s23, 32700; VI-NEXT: s_add_i32 s24, s4, 0x300002701; VI-NEXT: s_and_b32 s4, s23, 0xffff00002702; VI-NEXT: s_and_b32 s5, s5, 0xffff2703; VI-NEXT: s_or_b32 s4, s4, s52704; VI-NEXT: s_add_i32 s5, s22, 32705; VI-NEXT: s_add_i32 s23, s4, 0x300002706; VI-NEXT: s_and_b32 s4, s22, 0xffff00002707; VI-NEXT: s_and_b32 s5, s5, 0xffff2708; VI-NEXT: s_or_b32 s4, s4, s52709; VI-NEXT: s_add_i32 s5, s21, 32710; VI-NEXT: s_add_i32 s22, s4, 0x300002711; VI-NEXT: s_and_b32 s4, s21, 0xffff00002712; VI-NEXT: s_and_b32 s5, s5, 0xffff2713; VI-NEXT: s_or_b32 s4, s4, s52714; VI-NEXT: s_add_i32 s5, s20, 32715; VI-NEXT: s_add_i32 s21, s4, 0x300002716; VI-NEXT: s_and_b32 s4, s20, 0xffff00002717; VI-NEXT: s_and_b32 s5, s5, 0xffff2718; VI-NEXT: s_or_b32 s4, s4, s52719; VI-NEXT: s_add_i32 s5, s19, 32720; VI-NEXT: s_add_i32 s20, s4, 0x300002721; VI-NEXT: s_and_b32 s4, s19, 0xffff00002722; VI-NEXT: s_and_b32 s5, s5, 0xffff2723; VI-NEXT: s_or_b32 s4, s4, s52724; VI-NEXT: s_add_i32 s5, s18, 32725; VI-NEXT: s_add_i32 s19, s4, 0x300002726; VI-NEXT: s_and_b32 s4, s18, 0xffff00002727; VI-NEXT: s_and_b32 s5, s5, 0xffff2728; VI-NEXT: s_or_b32 s4, s4, s52729; VI-NEXT: s_add_i32 s5, s17, 32730; VI-NEXT: s_add_i32 s18, s4, 0x300002731; VI-NEXT: s_and_b32 s4, s17, 0xffff00002732; VI-NEXT: s_and_b32 s5, s5, 0xffff2733; VI-NEXT: s_or_b32 s4, s4, s52734; VI-NEXT: s_add_i32 s5, s16, 32735; VI-NEXT: s_add_i32 s17, s4, 0x300002736; VI-NEXT: s_and_b32 s4, s16, 0xffff00002737; VI-NEXT: s_and_b32 s5, s5, 0xffff2738; VI-NEXT: s_or_b32 s4, s4, s52739; VI-NEXT: s_add_i32 s16, s4, 0x300002740; VI-NEXT: .LBB15_3: ; %end2741; VI-NEXT: v_mov_b32_e32 v0, s162742; VI-NEXT: v_mov_b32_e32 v1, s172743; VI-NEXT: v_mov_b32_e32 v2, s182744; VI-NEXT: v_mov_b32_e32 v3, s192745; VI-NEXT: v_mov_b32_e32 v4, s202746; VI-NEXT: v_mov_b32_e32 v5, s212747; VI-NEXT: v_mov_b32_e32 v6, s222748; VI-NEXT: v_mov_b32_e32 v7, s232749; VI-NEXT: v_mov_b32_e32 v8, s242750; VI-NEXT: v_mov_b32_e32 v9, s252751; VI-NEXT: v_mov_b32_e32 v10, s262752; VI-NEXT: v_mov_b32_e32 v11, s272753; VI-NEXT: v_mov_b32_e32 v12, s282754; VI-NEXT: v_mov_b32_e32 v13, s292755; VI-NEXT: s_setpc_b64 s[30:31]2756; VI-NEXT: .LBB15_4:2757; VI-NEXT: s_branch .LBB15_22758;2759; GFX9-LABEL: bitcast_v28i16_to_v14i32_scalar:2760; GFX9: ; %bb.0:2761; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2762; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v02763; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec2764; GFX9-NEXT: s_cbranch_scc0 .LBB15_32765; GFX9-NEXT: ; %bb.1: ; %cmp.false2766; GFX9-NEXT: s_cbranch_execnz .LBB15_42767; GFX9-NEXT: .LBB15_2: ; %cmp.true2768; GFX9-NEXT: v_pk_add_u16 v13, s29, 3 op_sel_hi:[1,0]2769; GFX9-NEXT: v_pk_add_u16 v12, s28, 3 op_sel_hi:[1,0]2770; GFX9-NEXT: v_pk_add_u16 v11, s27, 3 op_sel_hi:[1,0]2771; GFX9-NEXT: v_pk_add_u16 v10, s26, 3 op_sel_hi:[1,0]2772; GFX9-NEXT: v_pk_add_u16 v9, s25, 3 op_sel_hi:[1,0]2773; GFX9-NEXT: v_pk_add_u16 v8, s24, 3 op_sel_hi:[1,0]2774; GFX9-NEXT: v_pk_add_u16 v7, s23, 3 op_sel_hi:[1,0]2775; GFX9-NEXT: v_pk_add_u16 v6, s22, 3 op_sel_hi:[1,0]2776; GFX9-NEXT: v_pk_add_u16 v5, s21, 3 op_sel_hi:[1,0]2777; GFX9-NEXT: v_pk_add_u16 v4, s20, 3 op_sel_hi:[1,0]2778; GFX9-NEXT: v_pk_add_u16 v3, s19, 3 op_sel_hi:[1,0]2779; GFX9-NEXT: v_pk_add_u16 v2, s18, 3 op_sel_hi:[1,0]2780; GFX9-NEXT: v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]2781; GFX9-NEXT: v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]2782; GFX9-NEXT: s_setpc_b64 s[30:31]2783; GFX9-NEXT: .LBB15_3:2784; GFX9-NEXT: s_branch .LBB15_22785; GFX9-NEXT: .LBB15_4:2786; GFX9-NEXT: v_mov_b32_e32 v0, s162787; GFX9-NEXT: v_mov_b32_e32 v1, s172788; GFX9-NEXT: v_mov_b32_e32 v2, s182789; GFX9-NEXT: v_mov_b32_e32 v3, s192790; GFX9-NEXT: v_mov_b32_e32 v4, s202791; GFX9-NEXT: v_mov_b32_e32 v5, s212792; GFX9-NEXT: v_mov_b32_e32 v6, s222793; GFX9-NEXT: v_mov_b32_e32 v7, s232794; GFX9-NEXT: v_mov_b32_e32 v8, s242795; GFX9-NEXT: v_mov_b32_e32 v9, s252796; GFX9-NEXT: v_mov_b32_e32 v10, s262797; GFX9-NEXT: v_mov_b32_e32 v11, s272798; GFX9-NEXT: v_mov_b32_e32 v12, s282799; GFX9-NEXT: v_mov_b32_e32 v13, s292800; GFX9-NEXT: v_mov_b32_e32 v14, s302801; GFX9-NEXT: v_mov_b32_e32 v15, s312802; GFX9-NEXT: s_setpc_b64 s[30:31]2803;2804; GFX11-LABEL: bitcast_v28i16_to_v14i32_scalar:2805; GFX11: ; %bb.0:2806; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2807; GFX11-NEXT: s_mov_b32 s15, s32808; GFX11-NEXT: s_mov_b32 s14, s22809; GFX11-NEXT: s_mov_b32 s13, s12810; GFX11-NEXT: s_mov_b32 s12, s02811; GFX11-NEXT: s_cmp_lg_u32 s26, 02812; GFX11-NEXT: s_mov_b32 s0, 02813; GFX11-NEXT: s_cbranch_scc0 .LBB15_32814; GFX11-NEXT: ; %bb.1: ; %Flow2815; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s02816; GFX11-NEXT: s_cbranch_vccnz .LBB15_42817; GFX11-NEXT: .LBB15_2: ; %cmp.true2818; GFX11-NEXT: v_pk_add_u16 v13, s25, 3 op_sel_hi:[1,0]2819; GFX11-NEXT: v_pk_add_u16 v12, s24, 3 op_sel_hi:[1,0]2820; GFX11-NEXT: v_pk_add_u16 v11, s23, 3 op_sel_hi:[1,0]2821; GFX11-NEXT: v_pk_add_u16 v10, s22, 3 op_sel_hi:[1,0]2822; GFX11-NEXT: v_pk_add_u16 v9, s21, 3 op_sel_hi:[1,0]2823; GFX11-NEXT: v_pk_add_u16 v8, s20, 3 op_sel_hi:[1,0]2824; GFX11-NEXT: v_pk_add_u16 v7, s19, 3 op_sel_hi:[1,0]2825; GFX11-NEXT: v_pk_add_u16 v6, s18, 3 op_sel_hi:[1,0]2826; GFX11-NEXT: v_pk_add_u16 v5, s17, 3 op_sel_hi:[1,0]2827; GFX11-NEXT: v_pk_add_u16 v4, s16, 3 op_sel_hi:[1,0]2828; GFX11-NEXT: v_pk_add_u16 v3, s15, 3 op_sel_hi:[1,0]2829; GFX11-NEXT: v_pk_add_u16 v2, s14, 3 op_sel_hi:[1,0]2830; GFX11-NEXT: v_pk_add_u16 v1, s13, 3 op_sel_hi:[1,0]2831; GFX11-NEXT: v_pk_add_u16 v0, s12, 3 op_sel_hi:[1,0]2832; GFX11-NEXT: s_setpc_b64 s[30:31]2833; GFX11-NEXT: .LBB15_3:2834; GFX11-NEXT: s_branch .LBB15_22835; GFX11-NEXT: .LBB15_4:2836; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s132837; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s152838; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s172839; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s192840; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s212841; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s232842; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s252843; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s272844; GFX11-NEXT: s_setpc_b64 s[30:31]2845 %cmp = icmp eq i32 %b, 02846 br i1 %cmp, label %cmp.true, label %cmp.false2847 2848cmp.true:2849 %a1 = add <28 x i16> %a, splat (i16 3)2850 %a2 = bitcast <28 x i16> %a1 to <14 x i32>2851 br label %end2852 2853cmp.false:2854 %a3 = bitcast <28 x i16> %a to <14 x i32>2855 br label %end2856 2857end:2858 %phi = phi <14 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]2859 ret <14 x i32> %phi2860}2861 2862define <28 x half> @bitcast_v14i32_to_v28f16(<14 x i32> %a, i32 %b) {2863; SI-LABEL: bitcast_v14i32_to_v28f16:2864; SI: ; %bb.0:2865; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2866; SI-NEXT: v_mov_b32_e32 v28, v132867; SI-NEXT: v_mov_b32_e32 v29, v122868; SI-NEXT: v_mov_b32_e32 v30, v112869; SI-NEXT: v_mov_b32_e32 v31, v102870; SI-NEXT: v_mov_b32_e32 v32, v92871; SI-NEXT: v_mov_b32_e32 v33, v82872; SI-NEXT: v_mov_b32_e32 v34, v72873; SI-NEXT: v_mov_b32_e32 v35, v62874; SI-NEXT: v_mov_b32_e32 v36, v52875; SI-NEXT: v_mov_b32_e32 v37, v42876; SI-NEXT: v_mov_b32_e32 v38, v32877; SI-NEXT: v_mov_b32_e32 v39, v22878; SI-NEXT: v_mov_b32_e32 v48, v12879; SI-NEXT: v_mov_b32_e32 v49, v02880; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v142881; SI-NEXT: ; implicit-def: $vgpr02882; SI-NEXT: ; implicit-def: $vgpr12883; SI-NEXT: ; implicit-def: $vgpr22884; SI-NEXT: ; implicit-def: $vgpr32885; SI-NEXT: ; implicit-def: $vgpr42886; SI-NEXT: ; implicit-def: $vgpr52887; SI-NEXT: ; implicit-def: $vgpr62888; SI-NEXT: ; implicit-def: $vgpr72889; SI-NEXT: ; implicit-def: $vgpr82890; SI-NEXT: ; implicit-def: $vgpr92891; SI-NEXT: ; implicit-def: $vgpr102892; SI-NEXT: ; implicit-def: $vgpr112893; SI-NEXT: ; implicit-def: $vgpr122894; SI-NEXT: ; implicit-def: $vgpr132895; SI-NEXT: ; implicit-def: $vgpr142896; SI-NEXT: ; implicit-def: $vgpr152897; SI-NEXT: ; implicit-def: $vgpr162898; SI-NEXT: ; implicit-def: $vgpr172899; SI-NEXT: ; implicit-def: $vgpr182900; SI-NEXT: ; implicit-def: $vgpr192901; SI-NEXT: ; implicit-def: $vgpr202902; SI-NEXT: ; implicit-def: $vgpr212903; SI-NEXT: ; implicit-def: $vgpr222904; SI-NEXT: ; implicit-def: $vgpr232905; SI-NEXT: ; implicit-def: $vgpr242906; SI-NEXT: ; implicit-def: $vgpr252907; SI-NEXT: ; implicit-def: $vgpr262908; SI-NEXT: ; implicit-def: $vgpr272909; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc2910; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]2911; SI-NEXT: s_cbranch_execnz .LBB16_32912; SI-NEXT: ; %bb.1: ; %Flow2913; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]2914; SI-NEXT: s_cbranch_execnz .LBB16_42915; SI-NEXT: .LBB16_2: ; %end2916; SI-NEXT: s_or_b64 exec, exec, s[4:5]2917; SI-NEXT: s_setpc_b64 s[30:31]2918; SI-NEXT: .LBB16_3: ; %cmp.false2919; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v282920; SI-NEXT: v_cvt_f32_f16_e32 v27, v02921; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v292922; SI-NEXT: v_cvt_f32_f16_e32 v25, v02923; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v302924; SI-NEXT: v_cvt_f32_f16_e32 v23, v02925; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v312926; SI-NEXT: v_cvt_f32_f16_e32 v21, v02927; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v322928; SI-NEXT: v_cvt_f32_f16_e32 v19, v02929; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v332930; SI-NEXT: v_cvt_f32_f16_e32 v17, v02931; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v342932; SI-NEXT: v_cvt_f32_f16_e32 v15, v02933; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v352934; SI-NEXT: v_cvt_f32_f16_e32 v13, v02935; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v362936; SI-NEXT: v_cvt_f32_f16_e32 v11, v02937; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v372938; SI-NEXT: v_cvt_f32_f16_e32 v9, v02939; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v382940; SI-NEXT: v_cvt_f32_f16_e32 v7, v02941; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v392942; SI-NEXT: v_cvt_f32_f16_e32 v5, v02943; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v482944; SI-NEXT: v_cvt_f32_f16_e32 v3, v02945; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v492946; SI-NEXT: v_cvt_f32_f16_e32 v1, v02947; SI-NEXT: v_cvt_f32_f16_e32 v26, v282948; SI-NEXT: v_cvt_f32_f16_e32 v24, v292949; SI-NEXT: v_cvt_f32_f16_e32 v22, v302950; SI-NEXT: v_cvt_f32_f16_e32 v20, v312951; SI-NEXT: v_cvt_f32_f16_e32 v18, v322952; SI-NEXT: v_cvt_f32_f16_e32 v16, v332953; SI-NEXT: v_cvt_f32_f16_e32 v14, v342954; SI-NEXT: v_cvt_f32_f16_e32 v12, v352955; SI-NEXT: v_cvt_f32_f16_e32 v10, v362956; SI-NEXT: v_cvt_f32_f16_e32 v8, v372957; SI-NEXT: v_cvt_f32_f16_e32 v6, v382958; SI-NEXT: v_cvt_f32_f16_e32 v4, v392959; SI-NEXT: v_cvt_f32_f16_e32 v2, v482960; SI-NEXT: v_cvt_f32_f16_e32 v0, v492961; SI-NEXT: ; implicit-def: $vgpr492962; SI-NEXT: ; implicit-def: $vgpr482963; SI-NEXT: ; implicit-def: $vgpr392964; SI-NEXT: ; implicit-def: $vgpr382965; SI-NEXT: ; implicit-def: $vgpr372966; SI-NEXT: ; implicit-def: $vgpr362967; SI-NEXT: ; implicit-def: $vgpr352968; SI-NEXT: ; implicit-def: $vgpr342969; SI-NEXT: ; implicit-def: $vgpr332970; SI-NEXT: ; implicit-def: $vgpr322971; SI-NEXT: ; implicit-def: $vgpr312972; SI-NEXT: ; implicit-def: $vgpr302973; SI-NEXT: ; implicit-def: $vgpr292974; SI-NEXT: ; implicit-def: $vgpr282975; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]2976; SI-NEXT: s_cbranch_execz .LBB16_22977; SI-NEXT: .LBB16_4: ; %cmp.true2978; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v492979; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v482980; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v392981; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v382982; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v372983; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v362984; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v352985; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v342986; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v332987; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v322988; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v312989; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v302990; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v292991; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v282992; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v02993; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v22994; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v42995; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v62996; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v82997; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v102998; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v122999; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v143000; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v163001; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v183002; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v203003; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v223004; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v243005; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v263006; SI-NEXT: v_cvt_f32_f16_e32 v26, v263007; SI-NEXT: v_cvt_f32_f16_e32 v24, v243008; SI-NEXT: v_cvt_f32_f16_e32 v22, v223009; SI-NEXT: v_cvt_f32_f16_e32 v20, v203010; SI-NEXT: v_cvt_f32_f16_e32 v18, v183011; SI-NEXT: v_cvt_f32_f16_e32 v16, v163012; SI-NEXT: v_cvt_f32_f16_e32 v14, v143013; SI-NEXT: v_cvt_f32_f16_e32 v12, v123014; SI-NEXT: v_cvt_f32_f16_e32 v10, v103015; SI-NEXT: v_cvt_f32_f16_e32 v8, v83016; SI-NEXT: v_cvt_f32_f16_e32 v6, v63017; SI-NEXT: v_cvt_f32_f16_e32 v4, v43018; SI-NEXT: v_cvt_f32_f16_e32 v2, v23019; SI-NEXT: v_cvt_f32_f16_e32 v0, v03020; SI-NEXT: v_cvt_f32_f16_e32 v27, v273021; SI-NEXT: v_cvt_f32_f16_e32 v25, v253022; SI-NEXT: v_cvt_f32_f16_e32 v23, v233023; SI-NEXT: v_cvt_f32_f16_e32 v21, v213024; SI-NEXT: v_cvt_f32_f16_e32 v19, v193025; SI-NEXT: v_cvt_f32_f16_e32 v17, v173026; SI-NEXT: v_cvt_f32_f16_e32 v15, v153027; SI-NEXT: v_cvt_f32_f16_e32 v13, v133028; SI-NEXT: v_cvt_f32_f16_e32 v11, v113029; SI-NEXT: v_cvt_f32_f16_e32 v9, v93030; SI-NEXT: v_cvt_f32_f16_e32 v7, v73031; SI-NEXT: v_cvt_f32_f16_e32 v5, v53032; SI-NEXT: v_cvt_f32_f16_e32 v3, v33033; SI-NEXT: v_cvt_f32_f16_e32 v1, v13034; SI-NEXT: s_or_b64 exec, exec, s[4:5]3035; SI-NEXT: s_setpc_b64 s[30:31]3036;3037; VI-LABEL: bitcast_v14i32_to_v28f16:3038; VI: ; %bb.0:3039; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3040; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v143041; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc3042; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]3043; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]3044; VI-NEXT: s_cbranch_execz .LBB16_23045; VI-NEXT: ; %bb.1: ; %cmp.true3046; VI-NEXT: v_add_u32_e32 v13, vcc, 3, v133047; VI-NEXT: v_add_u32_e32 v12, vcc, 3, v123048; VI-NEXT: v_add_u32_e32 v11, vcc, 3, v113049; VI-NEXT: v_add_u32_e32 v10, vcc, 3, v103050; VI-NEXT: v_add_u32_e32 v9, vcc, 3, v93051; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v83052; VI-NEXT: v_add_u32_e32 v7, vcc, 3, v73053; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v63054; VI-NEXT: v_add_u32_e32 v5, vcc, 3, v53055; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v43056; VI-NEXT: v_add_u32_e32 v3, vcc, 3, v33057; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v23058; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v13059; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v03060; VI-NEXT: .LBB16_2: ; %end3061; VI-NEXT: s_or_b64 exec, exec, s[4:5]3062; VI-NEXT: s_setpc_b64 s[30:31]3063;3064; GFX9-LABEL: bitcast_v14i32_to_v28f16:3065; GFX9: ; %bb.0:3066; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3067; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v143068; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc3069; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]3070; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]3071; GFX9-NEXT: s_cbranch_execz .LBB16_23072; GFX9-NEXT: ; %bb.1: ; %cmp.true3073; GFX9-NEXT: v_add_u32_e32 v13, 3, v133074; GFX9-NEXT: v_add_u32_e32 v12, 3, v123075; GFX9-NEXT: v_add_u32_e32 v11, 3, v113076; GFX9-NEXT: v_add_u32_e32 v10, 3, v103077; GFX9-NEXT: v_add_u32_e32 v9, 3, v93078; GFX9-NEXT: v_add_u32_e32 v8, 3, v83079; GFX9-NEXT: v_add_u32_e32 v7, 3, v73080; GFX9-NEXT: v_add_u32_e32 v6, 3, v63081; GFX9-NEXT: v_add_u32_e32 v5, 3, v53082; GFX9-NEXT: v_add_u32_e32 v4, 3, v43083; GFX9-NEXT: v_add_u32_e32 v3, 3, v33084; GFX9-NEXT: v_add_u32_e32 v2, 3, v23085; GFX9-NEXT: v_add_u32_e32 v1, 3, v13086; GFX9-NEXT: v_add_u32_e32 v0, 3, v03087; GFX9-NEXT: .LBB16_2: ; %end3088; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]3089; GFX9-NEXT: s_setpc_b64 s[30:31]3090;3091; GFX11-LABEL: bitcast_v14i32_to_v28f16:3092; GFX11: ; %bb.0:3093; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3094; GFX11-NEXT: s_mov_b32 s0, exec_lo3095; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v143096; GFX11-NEXT: s_xor_b32 s0, exec_lo, s03097; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)3098; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s03099; GFX11-NEXT: s_cbranch_execz .LBB16_23100; GFX11-NEXT: ; %bb.1: ; %cmp.true3101; GFX11-NEXT: v_add_nc_u32_e32 v13, 3, v133102; GFX11-NEXT: v_add_nc_u32_e32 v12, 3, v123103; GFX11-NEXT: v_add_nc_u32_e32 v11, 3, v113104; GFX11-NEXT: v_add_nc_u32_e32 v10, 3, v103105; GFX11-NEXT: v_add_nc_u32_e32 v9, 3, v93106; GFX11-NEXT: v_add_nc_u32_e32 v8, 3, v83107; GFX11-NEXT: v_add_nc_u32_e32 v7, 3, v73108; GFX11-NEXT: v_add_nc_u32_e32 v6, 3, v63109; GFX11-NEXT: v_add_nc_u32_e32 v5, 3, v53110; GFX11-NEXT: v_add_nc_u32_e32 v4, 3, v43111; GFX11-NEXT: v_add_nc_u32_e32 v3, 3, v33112; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v23113; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v13114; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v03115; GFX11-NEXT: .LBB16_2: ; %end3116; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s03117; GFX11-NEXT: s_setpc_b64 s[30:31]3118 %cmp = icmp eq i32 %b, 03119 br i1 %cmp, label %cmp.true, label %cmp.false3120 3121cmp.true:3122 %a1 = add <14 x i32> %a, splat (i32 3)3123 %a2 = bitcast <14 x i32> %a1 to <28 x half>3124 br label %end3125 3126cmp.false:3127 %a3 = bitcast <14 x i32> %a to <28 x half>3128 br label %end3129 3130end:3131 %phi = phi <28 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]3132 ret <28 x half> %phi3133}3134 3135define inreg <28 x half> @bitcast_v14i32_to_v28f16_scalar(<14 x i32> inreg %a, i32 inreg %b) {3136; SI-LABEL: bitcast_v14i32_to_v28f16_scalar:3137; SI: ; %bb.0:3138; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3139; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v03140; SI-NEXT: s_and_b64 s[4:5], vcc, exec3141; SI-NEXT: s_cbranch_scc0 .LBB17_43142; SI-NEXT: ; %bb.1: ; %cmp.false3143; SI-NEXT: s_lshr_b32 s4, s29, 163144; SI-NEXT: v_cvt_f32_f16_e32 v27, s43145; SI-NEXT: s_lshr_b32 s4, s28, 163146; SI-NEXT: v_cvt_f32_f16_e32 v25, s43147; SI-NEXT: s_lshr_b32 s4, s27, 163148; SI-NEXT: v_cvt_f32_f16_e32 v23, s43149; SI-NEXT: s_lshr_b32 s4, s26, 163150; SI-NEXT: v_cvt_f32_f16_e32 v21, s43151; SI-NEXT: s_lshr_b32 s4, s25, 163152; SI-NEXT: v_cvt_f32_f16_e32 v19, s43153; SI-NEXT: s_lshr_b32 s4, s24, 163154; SI-NEXT: v_cvt_f32_f16_e32 v17, s43155; SI-NEXT: s_lshr_b32 s4, s23, 163156; SI-NEXT: v_cvt_f32_f16_e32 v15, s43157; SI-NEXT: s_lshr_b32 s4, s22, 163158; SI-NEXT: v_cvt_f32_f16_e32 v13, s43159; SI-NEXT: s_lshr_b32 s4, s21, 163160; SI-NEXT: v_cvt_f32_f16_e32 v11, s43161; SI-NEXT: s_lshr_b32 s4, s20, 163162; SI-NEXT: v_cvt_f32_f16_e32 v9, s43163; SI-NEXT: s_lshr_b32 s4, s19, 163164; SI-NEXT: v_cvt_f32_f16_e32 v7, s43165; SI-NEXT: s_lshr_b32 s4, s18, 163166; SI-NEXT: v_cvt_f32_f16_e32 v5, s43167; SI-NEXT: s_lshr_b32 s4, s17, 163168; SI-NEXT: v_cvt_f32_f16_e32 v3, s43169; SI-NEXT: s_lshr_b32 s4, s16, 163170; SI-NEXT: v_cvt_f32_f16_e32 v1, s43171; SI-NEXT: v_cvt_f32_f16_e32 v26, s293172; SI-NEXT: v_cvt_f32_f16_e32 v24, s283173; SI-NEXT: v_cvt_f32_f16_e32 v22, s273174; SI-NEXT: v_cvt_f32_f16_e32 v20, s263175; SI-NEXT: v_cvt_f32_f16_e32 v18, s253176; SI-NEXT: v_cvt_f32_f16_e32 v16, s243177; SI-NEXT: v_cvt_f32_f16_e32 v14, s233178; SI-NEXT: v_cvt_f32_f16_e32 v12, s223179; SI-NEXT: v_cvt_f32_f16_e32 v10, s213180; SI-NEXT: v_cvt_f32_f16_e32 v8, s203181; SI-NEXT: v_cvt_f32_f16_e32 v6, s193182; SI-NEXT: v_cvt_f32_f16_e32 v4, s183183; SI-NEXT: v_cvt_f32_f16_e32 v2, s173184; SI-NEXT: v_cvt_f32_f16_e32 v0, s163185; SI-NEXT: s_cbranch_execnz .LBB17_33186; SI-NEXT: .LBB17_2: ; %cmp.true3187; SI-NEXT: s_add_i32 s16, s16, 33188; SI-NEXT: s_add_i32 s17, s17, 33189; SI-NEXT: s_add_i32 s18, s18, 33190; SI-NEXT: s_add_i32 s19, s19, 33191; SI-NEXT: s_add_i32 s20, s20, 33192; SI-NEXT: s_add_i32 s21, s21, 33193; SI-NEXT: s_add_i32 s22, s22, 33194; SI-NEXT: s_add_i32 s23, s23, 33195; SI-NEXT: s_add_i32 s24, s24, 33196; SI-NEXT: s_add_i32 s25, s25, 33197; SI-NEXT: s_add_i32 s26, s26, 33198; SI-NEXT: s_add_i32 s27, s27, 33199; SI-NEXT: s_add_i32 s28, s28, 33200; SI-NEXT: s_add_i32 s29, s29, 33201; SI-NEXT: s_lshr_b32 s4, s16, 163202; SI-NEXT: s_lshr_b32 s5, s17, 163203; SI-NEXT: s_lshr_b32 s6, s18, 163204; SI-NEXT: s_lshr_b32 s7, s19, 163205; SI-NEXT: s_lshr_b32 s8, s20, 163206; SI-NEXT: s_lshr_b32 s9, s21, 163207; SI-NEXT: s_lshr_b32 s10, s22, 163208; SI-NEXT: s_lshr_b32 s11, s23, 163209; SI-NEXT: s_lshr_b32 s12, s24, 163210; SI-NEXT: s_lshr_b32 s13, s25, 163211; SI-NEXT: s_lshr_b32 s14, s26, 163212; SI-NEXT: s_lshr_b32 s15, s27, 163213; SI-NEXT: s_lshr_b32 s40, s28, 163214; SI-NEXT: s_lshr_b32 s41, s29, 163215; SI-NEXT: v_cvt_f32_f16_e32 v26, s293216; SI-NEXT: v_cvt_f32_f16_e32 v24, s283217; SI-NEXT: v_cvt_f32_f16_e32 v22, s273218; SI-NEXT: v_cvt_f32_f16_e32 v20, s263219; SI-NEXT: v_cvt_f32_f16_e32 v18, s253220; SI-NEXT: v_cvt_f32_f16_e32 v16, s243221; SI-NEXT: v_cvt_f32_f16_e32 v14, s233222; SI-NEXT: v_cvt_f32_f16_e32 v12, s223223; SI-NEXT: v_cvt_f32_f16_e32 v10, s213224; SI-NEXT: v_cvt_f32_f16_e32 v8, s203225; SI-NEXT: v_cvt_f32_f16_e32 v6, s193226; SI-NEXT: v_cvt_f32_f16_e32 v4, s183227; SI-NEXT: v_cvt_f32_f16_e32 v2, s173228; SI-NEXT: v_cvt_f32_f16_e32 v0, s163229; SI-NEXT: v_cvt_f32_f16_e32 v27, s413230; SI-NEXT: v_cvt_f32_f16_e32 v25, s403231; SI-NEXT: v_cvt_f32_f16_e32 v23, s153232; SI-NEXT: v_cvt_f32_f16_e32 v21, s143233; SI-NEXT: v_cvt_f32_f16_e32 v19, s133234; SI-NEXT: v_cvt_f32_f16_e32 v17, s123235; SI-NEXT: v_cvt_f32_f16_e32 v15, s113236; SI-NEXT: v_cvt_f32_f16_e32 v13, s103237; SI-NEXT: v_cvt_f32_f16_e32 v11, s93238; SI-NEXT: v_cvt_f32_f16_e32 v9, s83239; SI-NEXT: v_cvt_f32_f16_e32 v7, s73240; SI-NEXT: v_cvt_f32_f16_e32 v5, s63241; SI-NEXT: v_cvt_f32_f16_e32 v3, s53242; SI-NEXT: v_cvt_f32_f16_e32 v1, s43243; SI-NEXT: .LBB17_3: ; %end3244; SI-NEXT: s_setpc_b64 s[30:31]3245; SI-NEXT: .LBB17_4:3246; SI-NEXT: ; implicit-def: $vgpr03247; SI-NEXT: ; implicit-def: $vgpr13248; SI-NEXT: ; implicit-def: $vgpr23249; SI-NEXT: ; implicit-def: $vgpr33250; SI-NEXT: ; implicit-def: $vgpr43251; SI-NEXT: ; implicit-def: $vgpr53252; SI-NEXT: ; implicit-def: $vgpr63253; SI-NEXT: ; implicit-def: $vgpr73254; SI-NEXT: ; implicit-def: $vgpr83255; SI-NEXT: ; implicit-def: $vgpr93256; SI-NEXT: ; implicit-def: $vgpr103257; SI-NEXT: ; implicit-def: $vgpr113258; SI-NEXT: ; implicit-def: $vgpr123259; SI-NEXT: ; implicit-def: $vgpr133260; SI-NEXT: ; implicit-def: $vgpr143261; SI-NEXT: ; implicit-def: $vgpr153262; SI-NEXT: ; implicit-def: $vgpr163263; SI-NEXT: ; implicit-def: $vgpr173264; SI-NEXT: ; implicit-def: $vgpr183265; SI-NEXT: ; implicit-def: $vgpr193266; SI-NEXT: ; implicit-def: $vgpr203267; SI-NEXT: ; implicit-def: $vgpr213268; SI-NEXT: ; implicit-def: $vgpr223269; SI-NEXT: ; implicit-def: $vgpr233270; SI-NEXT: ; implicit-def: $vgpr243271; SI-NEXT: ; implicit-def: $vgpr253272; SI-NEXT: ; implicit-def: $vgpr263273; SI-NEXT: ; implicit-def: $vgpr273274; SI-NEXT: s_branch .LBB17_23275;3276; VI-LABEL: bitcast_v14i32_to_v28f16_scalar:3277; VI: ; %bb.0:3278; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3279; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v03280; VI-NEXT: s_and_b64 s[4:5], vcc, exec3281; VI-NEXT: s_cbranch_scc0 .LBB17_43282; VI-NEXT: ; %bb.1: ; %cmp.false3283; VI-NEXT: s_cbranch_execnz .LBB17_33284; VI-NEXT: .LBB17_2: ; %cmp.true3285; VI-NEXT: s_add_i32 s29, s29, 33286; VI-NEXT: s_add_i32 s28, s28, 33287; VI-NEXT: s_add_i32 s27, s27, 33288; VI-NEXT: s_add_i32 s26, s26, 33289; VI-NEXT: s_add_i32 s25, s25, 33290; VI-NEXT: s_add_i32 s24, s24, 33291; VI-NEXT: s_add_i32 s23, s23, 33292; VI-NEXT: s_add_i32 s22, s22, 33293; VI-NEXT: s_add_i32 s21, s21, 33294; VI-NEXT: s_add_i32 s20, s20, 33295; VI-NEXT: s_add_i32 s19, s19, 33296; VI-NEXT: s_add_i32 s18, s18, 33297; VI-NEXT: s_add_i32 s17, s17, 33298; VI-NEXT: s_add_i32 s16, s16, 33299; VI-NEXT: .LBB17_3: ; %end3300; VI-NEXT: v_mov_b32_e32 v0, s163301; VI-NEXT: v_mov_b32_e32 v1, s173302; VI-NEXT: v_mov_b32_e32 v2, s183303; VI-NEXT: v_mov_b32_e32 v3, s193304; VI-NEXT: v_mov_b32_e32 v4, s203305; VI-NEXT: v_mov_b32_e32 v5, s213306; VI-NEXT: v_mov_b32_e32 v6, s223307; VI-NEXT: v_mov_b32_e32 v7, s233308; VI-NEXT: v_mov_b32_e32 v8, s243309; VI-NEXT: v_mov_b32_e32 v9, s253310; VI-NEXT: v_mov_b32_e32 v10, s263311; VI-NEXT: v_mov_b32_e32 v11, s273312; VI-NEXT: v_mov_b32_e32 v12, s283313; VI-NEXT: v_mov_b32_e32 v13, s293314; VI-NEXT: s_setpc_b64 s[30:31]3315; VI-NEXT: .LBB17_4:3316; VI-NEXT: s_branch .LBB17_23317;3318; GFX9-LABEL: bitcast_v14i32_to_v28f16_scalar:3319; GFX9: ; %bb.0:3320; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3321; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v03322; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec3323; GFX9-NEXT: s_cbranch_scc0 .LBB17_43324; GFX9-NEXT: ; %bb.1: ; %cmp.false3325; GFX9-NEXT: s_cbranch_execnz .LBB17_33326; GFX9-NEXT: .LBB17_2: ; %cmp.true3327; GFX9-NEXT: s_add_i32 s29, s29, 33328; GFX9-NEXT: s_add_i32 s28, s28, 33329; GFX9-NEXT: s_add_i32 s27, s27, 33330; GFX9-NEXT: s_add_i32 s26, s26, 33331; GFX9-NEXT: s_add_i32 s25, s25, 33332; GFX9-NEXT: s_add_i32 s24, s24, 33333; GFX9-NEXT: s_add_i32 s23, s23, 33334; GFX9-NEXT: s_add_i32 s22, s22, 33335; GFX9-NEXT: s_add_i32 s21, s21, 33336; GFX9-NEXT: s_add_i32 s20, s20, 33337; GFX9-NEXT: s_add_i32 s19, s19, 33338; GFX9-NEXT: s_add_i32 s18, s18, 33339; GFX9-NEXT: s_add_i32 s17, s17, 33340; GFX9-NEXT: s_add_i32 s16, s16, 33341; GFX9-NEXT: .LBB17_3: ; %end3342; GFX9-NEXT: v_mov_b32_e32 v0, s163343; GFX9-NEXT: v_mov_b32_e32 v1, s173344; GFX9-NEXT: v_mov_b32_e32 v2, s183345; GFX9-NEXT: v_mov_b32_e32 v3, s193346; GFX9-NEXT: v_mov_b32_e32 v4, s203347; GFX9-NEXT: v_mov_b32_e32 v5, s213348; GFX9-NEXT: v_mov_b32_e32 v6, s223349; GFX9-NEXT: v_mov_b32_e32 v7, s233350; GFX9-NEXT: v_mov_b32_e32 v8, s243351; GFX9-NEXT: v_mov_b32_e32 v9, s253352; GFX9-NEXT: v_mov_b32_e32 v10, s263353; GFX9-NEXT: v_mov_b32_e32 v11, s273354; GFX9-NEXT: v_mov_b32_e32 v12, s283355; GFX9-NEXT: v_mov_b32_e32 v13, s293356; GFX9-NEXT: s_setpc_b64 s[30:31]3357; GFX9-NEXT: .LBB17_4:3358; GFX9-NEXT: s_branch .LBB17_23359;3360; GFX11-LABEL: bitcast_v14i32_to_v28f16_scalar:3361; GFX11: ; %bb.0:3362; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3363; GFX11-NEXT: s_cmp_lg_u32 s26, 03364; GFX11-NEXT: s_mov_b32 s4, 03365; GFX11-NEXT: s_cbranch_scc0 .LBB17_43366; GFX11-NEXT: ; %bb.1: ; %Flow3367; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s43368; GFX11-NEXT: s_cbranch_vccnz .LBB17_33369; GFX11-NEXT: .LBB17_2: ; %cmp.true3370; GFX11-NEXT: s_add_i32 s25, s25, 33371; GFX11-NEXT: s_add_i32 s24, s24, 33372; GFX11-NEXT: s_add_i32 s23, s23, 33373; GFX11-NEXT: s_add_i32 s22, s22, 33374; GFX11-NEXT: s_add_i32 s21, s21, 33375; GFX11-NEXT: s_add_i32 s20, s20, 33376; GFX11-NEXT: s_add_i32 s19, s19, 33377; GFX11-NEXT: s_add_i32 s18, s18, 33378; GFX11-NEXT: s_add_i32 s17, s17, 33379; GFX11-NEXT: s_add_i32 s16, s16, 33380; GFX11-NEXT: s_add_i32 s3, s3, 33381; GFX11-NEXT: s_add_i32 s2, s2, 33382; GFX11-NEXT: s_add_i32 s1, s1, 33383; GFX11-NEXT: s_add_i32 s0, s0, 33384; GFX11-NEXT: .LBB17_3: ; %end3385; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)3386; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s13387; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s33388; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s173389; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s193390; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s213391; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s233392; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s253393; GFX11-NEXT: s_setpc_b64 s[30:31]3394; GFX11-NEXT: .LBB17_4:3395; GFX11-NEXT: s_branch .LBB17_23396 %cmp = icmp eq i32 %b, 03397 br i1 %cmp, label %cmp.true, label %cmp.false3398 3399cmp.true:3400 %a1 = add <14 x i32> %a, splat (i32 3)3401 %a2 = bitcast <14 x i32> %a1 to <28 x half>3402 br label %end3403 3404cmp.false:3405 %a3 = bitcast <14 x i32> %a to <28 x half>3406 br label %end3407 3408end:3409 %phi = phi <28 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]3410 ret <28 x half> %phi3411}3412 3413define <14 x i32> @bitcast_v28f16_to_v14i32(<28 x half> %a, i32 %b) {3414; SI-LABEL: bitcast_v28f16_to_v14i32:3415; SI: ; %bb.0:3416; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3417; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill3418; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill3419; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 ; 4-byte Folded Spill3420; SI-NEXT: s_waitcnt expcnt(0)3421; SI-NEXT: v_cvt_f16_f32_e32 v42, v13422; SI-NEXT: v_cvt_f16_f32_e32 v41, v03423; SI-NEXT: v_cvt_f16_f32_e32 v40, v33424; SI-NEXT: v_cvt_f16_f32_e32 v55, v23425; SI-NEXT: v_cvt_f16_f32_e32 v54, v53426; SI-NEXT: v_cvt_f16_f32_e32 v53, v43427; SI-NEXT: v_cvt_f16_f32_e32 v52, v73428; SI-NEXT: v_cvt_f16_f32_e32 v51, v63429; SI-NEXT: v_cvt_f16_f32_e32 v50, v93430; SI-NEXT: v_cvt_f16_f32_e32 v49, v83431; SI-NEXT: v_cvt_f16_f32_e32 v48, v113432; SI-NEXT: v_cvt_f16_f32_e32 v39, v103433; SI-NEXT: v_cvt_f16_f32_e32 v38, v133434; SI-NEXT: v_cvt_f16_f32_e32 v37, v123435; SI-NEXT: v_cvt_f16_f32_e32 v36, v153436; SI-NEXT: v_cvt_f16_f32_e32 v35, v143437; SI-NEXT: v_cvt_f16_f32_e32 v34, v173438; SI-NEXT: v_cvt_f16_f32_e32 v33, v163439; SI-NEXT: v_cvt_f16_f32_e32 v32, v193440; SI-NEXT: v_cvt_f16_f32_e32 v31, v183441; SI-NEXT: v_cvt_f16_f32_e32 v30, v213442; SI-NEXT: v_cvt_f16_f32_e32 v29, v203443; SI-NEXT: v_cvt_f16_f32_e32 v21, v233444; SI-NEXT: v_cvt_f16_f32_e32 v20, v223445; SI-NEXT: v_cvt_f16_f32_e32 v19, v253446; SI-NEXT: v_cvt_f16_f32_e32 v18, v243447; SI-NEXT: v_cvt_f16_f32_e32 v17, v273448; SI-NEXT: v_cvt_f16_f32_e32 v16, v263449; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v283450; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr153451; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc3452; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]3453; SI-NEXT: s_cbranch_execz .LBB18_23454; SI-NEXT: ; %bb.1: ; %cmp.false3455; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v423456; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v403457; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v543458; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v523459; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v503460; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v483461; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v383462; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v363463; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v343464; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v323465; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v303466; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v213467; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v193468; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v173469; SI-NEXT: v_or_b32_e32 v0, v41, v03470; SI-NEXT: v_or_b32_e32 v1, v55, v13471; SI-NEXT: v_or_b32_e32 v2, v53, v23472; SI-NEXT: v_or_b32_e32 v3, v51, v33473; SI-NEXT: v_or_b32_e32 v4, v49, v43474; SI-NEXT: v_or_b32_e32 v5, v39, v53475; SI-NEXT: v_or_b32_e32 v6, v37, v63476; SI-NEXT: v_or_b32_e32 v7, v35, v73477; SI-NEXT: v_or_b32_e32 v8, v33, v83478; SI-NEXT: v_or_b32_e32 v9, v31, v93479; SI-NEXT: v_or_b32_e32 v10, v29, v103480; SI-NEXT: v_or_b32_e32 v11, v20, v113481; SI-NEXT: v_or_b32_e32 v12, v18, v123482; SI-NEXT: v_or_b32_e32 v13, v16, v133483; SI-NEXT: ; implicit-def: $vgpr423484; SI-NEXT: ; implicit-def: $vgpr413485; SI-NEXT: ; implicit-def: $vgpr403486; SI-NEXT: ; implicit-def: $vgpr553487; SI-NEXT: ; implicit-def: $vgpr543488; SI-NEXT: ; implicit-def: $vgpr533489; SI-NEXT: ; implicit-def: $vgpr523490; SI-NEXT: ; implicit-def: $vgpr513491; SI-NEXT: ; implicit-def: $vgpr503492; SI-NEXT: ; implicit-def: $vgpr493493; SI-NEXT: ; implicit-def: $vgpr483494; SI-NEXT: ; implicit-def: $vgpr393495; SI-NEXT: ; implicit-def: $vgpr383496; SI-NEXT: ; implicit-def: $vgpr373497; SI-NEXT: ; implicit-def: $vgpr363498; SI-NEXT: ; implicit-def: $vgpr353499; SI-NEXT: ; implicit-def: $vgpr343500; SI-NEXT: ; implicit-def: $vgpr333501; SI-NEXT: ; implicit-def: $vgpr323502; SI-NEXT: ; implicit-def: $vgpr313503; SI-NEXT: ; implicit-def: $vgpr303504; SI-NEXT: ; implicit-def: $vgpr293505; SI-NEXT: ; implicit-def: $vgpr213506; SI-NEXT: ; implicit-def: $vgpr203507; SI-NEXT: ; implicit-def: $vgpr193508; SI-NEXT: ; implicit-def: $vgpr183509; SI-NEXT: ; implicit-def: $vgpr173510; SI-NEXT: ; implicit-def: $vgpr163511; SI-NEXT: .LBB18_2: ; %Flow3512; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]3513; SI-NEXT: s_cbranch_execz .LBB18_43514; SI-NEXT: ; %bb.3: ; %cmp.true3515; SI-NEXT: v_cvt_f32_f16_e32 v0, v423516; SI-NEXT: v_cvt_f32_f16_e32 v1, v413517; SI-NEXT: v_cvt_f32_f16_e32 v2, v403518; SI-NEXT: v_cvt_f32_f16_e32 v3, v553519; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v03520; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v13521; SI-NEXT: v_cvt_f16_f32_e32 v0, v03522; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v23523; SI-NEXT: v_cvt_f16_f32_e32 v1, v13524; SI-NEXT: v_cvt_f16_f32_e32 v2, v23525; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v03526; SI-NEXT: v_cvt_f32_f16_e32 v4, v533527; SI-NEXT: v_or_b32_e32 v0, v1, v03528; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v23529; SI-NEXT: v_cvt_f32_f16_e32 v2, v543530; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v33531; SI-NEXT: v_cvt_f16_f32_e32 v3, v33532; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v43533; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v23534; SI-NEXT: v_cvt_f16_f32_e32 v2, v23535; SI-NEXT: v_cvt_f16_f32_e32 v4, v43536; SI-NEXT: v_or_b32_e32 v1, v3, v13537; SI-NEXT: v_cvt_f32_f16_e32 v3, v523538; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v23539; SI-NEXT: v_or_b32_e32 v2, v4, v23540; SI-NEXT: v_cvt_f32_f16_e32 v4, v513541; SI-NEXT: v_cvt_f32_f16_e32 v5, v503542; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v33543; SI-NEXT: v_cvt_f16_f32_e32 v3, v33544; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v43545; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v53546; SI-NEXT: v_cvt_f16_f32_e32 v4, v43547; SI-NEXT: v_cvt_f16_f32_e32 v5, v53548; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v33549; SI-NEXT: v_cvt_f32_f16_e32 v6, v493550; SI-NEXT: v_or_b32_e32 v3, v4, v33551; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v53552; SI-NEXT: v_cvt_f32_f16_e32 v5, v483553; SI-NEXT: v_cvt_f32_f16_e32 v7, v393554; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v63555; SI-NEXT: v_cvt_f16_f32_e32 v6, v63556; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v53557; SI-NEXT: v_cvt_f16_f32_e32 v5, v53558; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v73559; SI-NEXT: v_cvt_f16_f32_e32 v7, v73560; SI-NEXT: v_or_b32_e32 v4, v6, v43561; SI-NEXT: v_cvt_f32_f16_e32 v6, v383562; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v53563; SI-NEXT: v_or_b32_e32 v5, v7, v53564; SI-NEXT: v_cvt_f32_f16_e32 v7, v373565; SI-NEXT: v_cvt_f32_f16_e32 v8, v363566; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v63567; SI-NEXT: v_cvt_f16_f32_e32 v6, v63568; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v73569; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v83570; SI-NEXT: v_cvt_f16_f32_e32 v7, v73571; SI-NEXT: v_cvt_f16_f32_e32 v8, v83572; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v63573; SI-NEXT: v_cvt_f32_f16_e32 v9, v353574; SI-NEXT: v_or_b32_e32 v6, v7, v63575; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v83576; SI-NEXT: v_cvt_f32_f16_e32 v8, v343577; SI-NEXT: v_cvt_f32_f16_e32 v10, v333578; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v93579; SI-NEXT: v_cvt_f16_f32_e32 v9, v93580; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v83581; SI-NEXT: v_cvt_f16_f32_e32 v8, v83582; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v103583; SI-NEXT: v_cvt_f16_f32_e32 v10, v103584; SI-NEXT: v_or_b32_e32 v7, v9, v73585; SI-NEXT: v_cvt_f32_f16_e32 v9, v323586; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v83587; SI-NEXT: v_or_b32_e32 v8, v10, v83588; SI-NEXT: v_cvt_f32_f16_e32 v10, v313589; SI-NEXT: v_cvt_f32_f16_e32 v11, v303590; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v93591; SI-NEXT: v_cvt_f16_f32_e32 v9, v93592; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v103593; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v113594; SI-NEXT: v_cvt_f16_f32_e32 v10, v103595; SI-NEXT: v_cvt_f16_f32_e32 v11, v113596; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v93597; SI-NEXT: v_cvt_f32_f16_e32 v12, v293598; SI-NEXT: v_or_b32_e32 v9, v10, v93599; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v113600; SI-NEXT: v_cvt_f32_f16_e32 v11, v213601; SI-NEXT: v_cvt_f32_f16_e32 v13, v203602; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v123603; SI-NEXT: v_cvt_f16_f32_e32 v12, v123604; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v113605; SI-NEXT: v_cvt_f16_f32_e32 v11, v113606; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v133607; SI-NEXT: v_cvt_f16_f32_e32 v13, v133608; SI-NEXT: v_or_b32_e32 v10, v12, v103609; SI-NEXT: v_cvt_f32_f16_e32 v12, v193610; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v113611; SI-NEXT: v_or_b32_e32 v11, v13, v113612; SI-NEXT: v_cvt_f32_f16_e32 v13, v183613; SI-NEXT: v_cvt_f32_f16_e32 v14, v173614; SI-NEXT: v_cvt_f32_f16_e32 v15, v163615; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v123616; SI-NEXT: v_cvt_f16_f32_e32 v12, v123617; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v133618; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v143619; SI-NEXT: v_cvt_f16_f32_e32 v13, v133620; SI-NEXT: v_cvt_f16_f32_e32 v14, v143621; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v153622; SI-NEXT: v_cvt_f16_f32_e32 v15, v153623; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v123624; SI-NEXT: v_or_b32_e32 v12, v13, v123625; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v143626; SI-NEXT: v_or_b32_e32 v13, v15, v133627; SI-NEXT: .LBB18_4: ; %end3628; SI-NEXT: s_or_b64 exec, exec, s[4:5]3629; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 ; 4-byte Folded Reload3630; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload3631; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload3632; SI-NEXT: s_waitcnt vmcnt(0)3633; SI-NEXT: s_setpc_b64 s[30:31]3634;3635; VI-LABEL: bitcast_v28f16_to_v14i32:3636; VI: ; %bb.0:3637; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3638; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v143639; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc3640; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]3641; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]3642; VI-NEXT: s_cbranch_execz .LBB18_23643; VI-NEXT: ; %bb.1: ; %cmp.true3644; VI-NEXT: v_mov_b32_e32 v14, 0x2003645; VI-NEXT: v_add_f16_sdwa v15, v13, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3646; VI-NEXT: v_add_f16_e32 v13, 0x200, v133647; VI-NEXT: v_or_b32_e32 v13, v13, v153648; VI-NEXT: v_add_f16_sdwa v15, v12, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3649; VI-NEXT: v_add_f16_e32 v12, 0x200, v123650; VI-NEXT: v_or_b32_e32 v12, v12, v153651; VI-NEXT: v_add_f16_sdwa v15, v11, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3652; VI-NEXT: v_add_f16_e32 v11, 0x200, v113653; VI-NEXT: v_or_b32_e32 v11, v11, v153654; VI-NEXT: v_add_f16_sdwa v15, v10, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3655; VI-NEXT: v_add_f16_e32 v10, 0x200, v103656; VI-NEXT: v_or_b32_e32 v10, v10, v153657; VI-NEXT: v_add_f16_sdwa v15, v9, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3658; VI-NEXT: v_add_f16_e32 v9, 0x200, v93659; VI-NEXT: v_or_b32_e32 v9, v9, v153660; VI-NEXT: v_add_f16_sdwa v15, v8, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3661; VI-NEXT: v_add_f16_e32 v8, 0x200, v83662; VI-NEXT: v_or_b32_e32 v8, v8, v153663; VI-NEXT: v_add_f16_sdwa v15, v7, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3664; VI-NEXT: v_add_f16_e32 v7, 0x200, v73665; VI-NEXT: v_or_b32_e32 v7, v7, v153666; VI-NEXT: v_add_f16_sdwa v15, v6, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3667; VI-NEXT: v_add_f16_e32 v6, 0x200, v63668; VI-NEXT: v_or_b32_e32 v6, v6, v153669; VI-NEXT: v_add_f16_sdwa v15, v5, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3670; VI-NEXT: v_add_f16_e32 v5, 0x200, v53671; VI-NEXT: v_or_b32_e32 v5, v5, v153672; VI-NEXT: v_add_f16_sdwa v15, v4, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3673; VI-NEXT: v_add_f16_e32 v4, 0x200, v43674; VI-NEXT: v_or_b32_e32 v4, v4, v153675; VI-NEXT: v_add_f16_sdwa v15, v3, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3676; VI-NEXT: v_add_f16_e32 v3, 0x200, v33677; VI-NEXT: v_or_b32_e32 v3, v3, v153678; VI-NEXT: v_add_f16_sdwa v15, v2, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3679; VI-NEXT: v_add_f16_e32 v2, 0x200, v23680; VI-NEXT: v_or_b32_e32 v2, v2, v153681; VI-NEXT: v_add_f16_sdwa v15, v1, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3682; VI-NEXT: v_add_f16_e32 v1, 0x200, v13683; VI-NEXT: v_add_f16_sdwa v14, v0, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3684; VI-NEXT: v_add_f16_e32 v0, 0x200, v03685; VI-NEXT: v_or_b32_e32 v1, v1, v153686; VI-NEXT: v_or_b32_e32 v0, v0, v143687; VI-NEXT: .LBB18_2: ; %end3688; VI-NEXT: s_or_b64 exec, exec, s[4:5]3689; VI-NEXT: s_setpc_b64 s[30:31]3690;3691; GFX9-LABEL: bitcast_v28f16_to_v14i32:3692; GFX9: ; %bb.0:3693; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3694; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v143695; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc3696; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]3697; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]3698; GFX9-NEXT: s_cbranch_execz .LBB18_23699; GFX9-NEXT: ; %bb.1: ; %cmp.true3700; GFX9-NEXT: s_movk_i32 s6, 0x2003701; GFX9-NEXT: v_pk_add_f16 v13, v13, s6 op_sel_hi:[1,0]3702; GFX9-NEXT: v_pk_add_f16 v12, v12, s6 op_sel_hi:[1,0]3703; GFX9-NEXT: v_pk_add_f16 v11, v11, s6 op_sel_hi:[1,0]3704; GFX9-NEXT: v_pk_add_f16 v10, v10, s6 op_sel_hi:[1,0]3705; GFX9-NEXT: v_pk_add_f16 v9, v9, s6 op_sel_hi:[1,0]3706; GFX9-NEXT: v_pk_add_f16 v8, v8, s6 op_sel_hi:[1,0]3707; GFX9-NEXT: v_pk_add_f16 v7, v7, s6 op_sel_hi:[1,0]3708; GFX9-NEXT: v_pk_add_f16 v6, v6, s6 op_sel_hi:[1,0]3709; GFX9-NEXT: v_pk_add_f16 v5, v5, s6 op_sel_hi:[1,0]3710; GFX9-NEXT: v_pk_add_f16 v4, v4, s6 op_sel_hi:[1,0]3711; GFX9-NEXT: v_pk_add_f16 v3, v3, s6 op_sel_hi:[1,0]3712; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]3713; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]3714; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]3715; GFX9-NEXT: .LBB18_2: ; %end3716; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]3717; GFX9-NEXT: s_setpc_b64 s[30:31]3718;3719; GFX11-LABEL: bitcast_v28f16_to_v14i32:3720; GFX11: ; %bb.0:3721; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3722; GFX11-NEXT: s_mov_b32 s0, exec_lo3723; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v143724; GFX11-NEXT: s_xor_b32 s0, exec_lo, s03725; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)3726; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s03727; GFX11-NEXT: s_cbranch_execz .LBB18_23728; GFX11-NEXT: ; %bb.1: ; %cmp.true3729; GFX11-NEXT: v_pk_add_f16 v13, 0x200, v13 op_sel_hi:[0,1]3730; GFX11-NEXT: v_pk_add_f16 v12, 0x200, v12 op_sel_hi:[0,1]3731; GFX11-NEXT: v_pk_add_f16 v11, 0x200, v11 op_sel_hi:[0,1]3732; GFX11-NEXT: v_pk_add_f16 v10, 0x200, v10 op_sel_hi:[0,1]3733; GFX11-NEXT: v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1]3734; GFX11-NEXT: v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1]3735; GFX11-NEXT: v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]3736; GFX11-NEXT: v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]3737; GFX11-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]3738; GFX11-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]3739; GFX11-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]3740; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]3741; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]3742; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]3743; GFX11-NEXT: .LBB18_2: ; %end3744; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s03745; GFX11-NEXT: s_setpc_b64 s[30:31]3746 %cmp = icmp eq i32 %b, 03747 br i1 %cmp, label %cmp.true, label %cmp.false3748 3749cmp.true:3750 %a1 = fadd <28 x half> %a, splat (half 0xH0200)3751 %a2 = bitcast <28 x half> %a1 to <14 x i32>3752 br label %end3753 3754cmp.false:3755 %a3 = bitcast <28 x half> %a to <14 x i32>3756 br label %end3757 3758end:3759 %phi = phi <14 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]3760 ret <14 x i32> %phi3761}3762 3763define inreg <14 x i32> @bitcast_v28f16_to_v14i32_scalar(<28 x half> inreg %a, i32 inreg %b) {3764; SI-LABEL: bitcast_v28f16_to_v14i32_scalar:3765; SI: ; %bb.0:3766; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3767; SI-NEXT: v_cvt_f16_f32_e32 v51, s173768; SI-NEXT: v_cvt_f16_f32_e32 v50, s163769; SI-NEXT: v_cvt_f16_f32_e32 v49, s193770; SI-NEXT: v_cvt_f16_f32_e32 v38, s183771; SI-NEXT: v_cvt_f16_f32_e32 v36, s213772; SI-NEXT: v_cvt_f16_f32_e32 v35, s203773; SI-NEXT: v_cvt_f16_f32_e32 v29, v13774; SI-NEXT: v_cvt_f16_f32_e32 v28, v03775; SI-NEXT: v_cvt_f16_f32_e32 v27, v33776; SI-NEXT: v_cvt_f16_f32_e32 v26, v23777; SI-NEXT: v_cvt_f16_f32_e32 v25, v53778; SI-NEXT: v_cvt_f16_f32_e32 v24, v43779; SI-NEXT: v_cvt_f16_f32_e32 v23, v73780; SI-NEXT: v_cvt_f16_f32_e32 v22, v63781; SI-NEXT: v_cvt_f16_f32_e32 v21, v93782; SI-NEXT: v_cvt_f16_f32_e32 v20, v83783; SI-NEXT: v_cvt_f16_f32_e32 v19, v113784; SI-NEXT: v_cvt_f16_f32_e32 v18, v103785; SI-NEXT: v_cvt_f16_f32_e32 v17, v133786; SI-NEXT: v_cvt_f16_f32_e32 v16, v123787; SI-NEXT: v_cvt_f16_f32_e32 v48, s233788; SI-NEXT: v_cvt_f16_f32_e32 v39, s223789; SI-NEXT: v_cvt_f16_f32_e32 v37, s253790; SI-NEXT: v_cvt_f16_f32_e32 v34, s243791; SI-NEXT: v_cvt_f16_f32_e32 v33, s273792; SI-NEXT: v_cvt_f16_f32_e32 v32, s263793; SI-NEXT: v_cvt_f16_f32_e32 v31, s293794; SI-NEXT: v_cvt_f16_f32_e32 v30, s283795; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v143796; SI-NEXT: s_and_b64 s[4:5], vcc, exec3797; SI-NEXT: s_cbranch_scc0 .LBB19_43798; SI-NEXT: ; %bb.1: ; %cmp.false3799; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v513800; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v493801; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v363802; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v483803; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v373804; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v333805; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v313806; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v293807; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v273808; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v253809; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v233810; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v213811; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v193812; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v173813; SI-NEXT: v_or_b32_e32 v0, v50, v03814; SI-NEXT: v_or_b32_e32 v1, v38, v13815; SI-NEXT: v_or_b32_e32 v2, v35, v23816; SI-NEXT: v_or_b32_e32 v3, v39, v33817; SI-NEXT: v_or_b32_e32 v4, v34, v43818; SI-NEXT: v_or_b32_e32 v5, v32, v53819; SI-NEXT: v_or_b32_e32 v6, v30, v63820; SI-NEXT: v_or_b32_e32 v7, v28, v73821; SI-NEXT: v_or_b32_e32 v8, v26, v83822; SI-NEXT: v_or_b32_e32 v9, v24, v93823; SI-NEXT: v_or_b32_e32 v10, v22, v103824; SI-NEXT: v_or_b32_e32 v11, v20, v113825; SI-NEXT: v_or_b32_e32 v12, v18, v123826; SI-NEXT: v_or_b32_e32 v13, v16, v133827; SI-NEXT: s_cbranch_execnz .LBB19_33828; SI-NEXT: .LBB19_2: ; %cmp.true3829; SI-NEXT: v_cvt_f32_f16_e32 v0, v513830; SI-NEXT: v_cvt_f32_f16_e32 v1, v503831; SI-NEXT: v_cvt_f32_f16_e32 v2, v493832; SI-NEXT: v_cvt_f32_f16_e32 v3, v383833; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v03834; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v13835; SI-NEXT: v_cvt_f16_f32_e32 v0, v03836; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v23837; SI-NEXT: v_cvt_f16_f32_e32 v1, v13838; SI-NEXT: v_cvt_f16_f32_e32 v2, v23839; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v03840; SI-NEXT: v_cvt_f32_f16_e32 v4, v353841; SI-NEXT: v_or_b32_e32 v0, v1, v03842; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v23843; SI-NEXT: v_cvt_f32_f16_e32 v2, v363844; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v33845; SI-NEXT: v_cvt_f16_f32_e32 v3, v33846; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v43847; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v23848; SI-NEXT: v_cvt_f16_f32_e32 v2, v23849; SI-NEXT: v_cvt_f16_f32_e32 v4, v43850; SI-NEXT: v_or_b32_e32 v1, v3, v13851; SI-NEXT: v_cvt_f32_f16_e32 v3, v483852; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v23853; SI-NEXT: v_or_b32_e32 v2, v4, v23854; SI-NEXT: v_cvt_f32_f16_e32 v4, v393855; SI-NEXT: v_cvt_f32_f16_e32 v5, v373856; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v33857; SI-NEXT: v_cvt_f16_f32_e32 v3, v33858; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v43859; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v53860; SI-NEXT: v_cvt_f16_f32_e32 v4, v43861; SI-NEXT: v_cvt_f16_f32_e32 v5, v53862; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v33863; SI-NEXT: v_cvt_f32_f16_e32 v6, v343864; SI-NEXT: v_or_b32_e32 v3, v4, v33865; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v53866; SI-NEXT: v_cvt_f32_f16_e32 v5, v333867; SI-NEXT: v_cvt_f32_f16_e32 v7, v323868; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v63869; SI-NEXT: v_cvt_f16_f32_e32 v6, v63870; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v53871; SI-NEXT: v_cvt_f16_f32_e32 v5, v53872; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v73873; SI-NEXT: v_cvt_f16_f32_e32 v7, v73874; SI-NEXT: v_or_b32_e32 v4, v6, v43875; SI-NEXT: v_cvt_f32_f16_e32 v6, v313876; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v53877; SI-NEXT: v_or_b32_e32 v5, v7, v53878; SI-NEXT: v_cvt_f32_f16_e32 v7, v303879; SI-NEXT: v_cvt_f32_f16_e32 v8, v293880; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v63881; SI-NEXT: v_cvt_f16_f32_e32 v6, v63882; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v73883; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v83884; SI-NEXT: v_cvt_f16_f32_e32 v7, v73885; SI-NEXT: v_cvt_f16_f32_e32 v8, v83886; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v63887; SI-NEXT: v_cvt_f32_f16_e32 v9, v283888; SI-NEXT: v_or_b32_e32 v6, v7, v63889; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v83890; SI-NEXT: v_cvt_f32_f16_e32 v8, v273891; SI-NEXT: v_cvt_f32_f16_e32 v10, v263892; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v93893; SI-NEXT: v_cvt_f16_f32_e32 v9, v93894; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v83895; SI-NEXT: v_cvt_f16_f32_e32 v8, v83896; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v103897; SI-NEXT: v_cvt_f16_f32_e32 v10, v103898; SI-NEXT: v_or_b32_e32 v7, v9, v73899; SI-NEXT: v_cvt_f32_f16_e32 v9, v253900; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v83901; SI-NEXT: v_or_b32_e32 v8, v10, v83902; SI-NEXT: v_cvt_f32_f16_e32 v10, v243903; SI-NEXT: v_cvt_f32_f16_e32 v11, v233904; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v93905; SI-NEXT: v_cvt_f16_f32_e32 v9, v93906; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v103907; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v113908; SI-NEXT: v_cvt_f16_f32_e32 v10, v103909; SI-NEXT: v_cvt_f16_f32_e32 v11, v113910; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v93911; SI-NEXT: v_cvt_f32_f16_e32 v12, v223912; SI-NEXT: v_or_b32_e32 v9, v10, v93913; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v113914; SI-NEXT: v_cvt_f32_f16_e32 v11, v213915; SI-NEXT: v_cvt_f32_f16_e32 v13, v203916; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v123917; SI-NEXT: v_cvt_f16_f32_e32 v12, v123918; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v113919; SI-NEXT: v_cvt_f16_f32_e32 v11, v113920; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v133921; SI-NEXT: v_cvt_f16_f32_e32 v13, v133922; SI-NEXT: v_or_b32_e32 v10, v12, v103923; SI-NEXT: v_cvt_f32_f16_e32 v12, v193924; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v113925; SI-NEXT: v_or_b32_e32 v11, v13, v113926; SI-NEXT: v_cvt_f32_f16_e32 v13, v183927; SI-NEXT: v_cvt_f32_f16_e32 v14, v173928; SI-NEXT: v_cvt_f32_f16_e32 v15, v163929; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v123930; SI-NEXT: v_cvt_f16_f32_e32 v12, v123931; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v133932; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v143933; SI-NEXT: v_cvt_f16_f32_e32 v13, v133934; SI-NEXT: v_cvt_f16_f32_e32 v14, v143935; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v153936; SI-NEXT: v_cvt_f16_f32_e32 v15, v153937; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v123938; SI-NEXT: v_or_b32_e32 v12, v13, v123939; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v143940; SI-NEXT: v_or_b32_e32 v13, v15, v133941; SI-NEXT: .LBB19_3: ; %end3942; SI-NEXT: s_setpc_b64 s[30:31]3943; SI-NEXT: .LBB19_4:3944; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr153945; SI-NEXT: s_branch .LBB19_23946;3947; VI-LABEL: bitcast_v28f16_to_v14i32_scalar:3948; VI: ; %bb.0:3949; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3950; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v03951; VI-NEXT: s_and_b64 s[4:5], vcc, exec3952; VI-NEXT: s_cbranch_scc0 .LBB19_33953; VI-NEXT: ; %bb.1: ; %cmp.false3954; VI-NEXT: s_cbranch_execnz .LBB19_43955; VI-NEXT: .LBB19_2: ; %cmp.true3956; VI-NEXT: s_lshr_b32 s4, s29, 163957; VI-NEXT: v_mov_b32_e32 v0, 0x2003958; VI-NEXT: v_mov_b32_e32 v1, s43959; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD3960; VI-NEXT: v_add_f16_e32 v2, s29, v03961; VI-NEXT: s_lshr_b32 s4, s28, 163962; VI-NEXT: v_or_b32_e32 v13, v2, v13963; VI-NEXT: v_mov_b32_e32 v1, s43964; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD3965; VI-NEXT: v_add_f16_e32 v2, s28, v03966; VI-NEXT: s_lshr_b32 s4, s27, 163967; VI-NEXT: v_or_b32_e32 v12, v2, v13968; VI-NEXT: v_mov_b32_e32 v1, s43969; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD3970; VI-NEXT: v_add_f16_e32 v2, s27, v03971; VI-NEXT: s_lshr_b32 s4, s26, 163972; VI-NEXT: v_or_b32_e32 v11, v2, v13973; VI-NEXT: v_mov_b32_e32 v1, s43974; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD3975; VI-NEXT: v_add_f16_e32 v2, s26, v03976; VI-NEXT: s_lshr_b32 s4, s25, 163977; VI-NEXT: v_or_b32_e32 v10, v2, v13978; VI-NEXT: v_mov_b32_e32 v1, s43979; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD3980; VI-NEXT: v_add_f16_e32 v2, s25, v03981; VI-NEXT: s_lshr_b32 s4, s24, 163982; VI-NEXT: v_or_b32_e32 v9, v2, v13983; VI-NEXT: v_mov_b32_e32 v1, s43984; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD3985; VI-NEXT: v_add_f16_e32 v2, s24, v03986; VI-NEXT: s_lshr_b32 s4, s23, 163987; VI-NEXT: v_or_b32_e32 v8, v2, v13988; VI-NEXT: v_mov_b32_e32 v1, s43989; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD3990; VI-NEXT: v_add_f16_e32 v2, s23, v03991; VI-NEXT: s_lshr_b32 s4, s22, 163992; VI-NEXT: v_or_b32_e32 v7, v2, v13993; VI-NEXT: v_mov_b32_e32 v1, s43994; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD3995; VI-NEXT: v_add_f16_e32 v2, s22, v03996; VI-NEXT: s_lshr_b32 s4, s21, 163997; VI-NEXT: v_or_b32_e32 v6, v2, v13998; VI-NEXT: v_mov_b32_e32 v1, s43999; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD4000; VI-NEXT: v_add_f16_e32 v2, s21, v04001; VI-NEXT: s_lshr_b32 s4, s20, 164002; VI-NEXT: v_or_b32_e32 v5, v2, v14003; VI-NEXT: v_mov_b32_e32 v1, s44004; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD4005; VI-NEXT: v_add_f16_e32 v2, s20, v04006; VI-NEXT: s_lshr_b32 s4, s19, 164007; VI-NEXT: v_or_b32_e32 v4, v2, v14008; VI-NEXT: v_mov_b32_e32 v1, s44009; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD4010; VI-NEXT: v_add_f16_e32 v2, s19, v04011; VI-NEXT: s_lshr_b32 s4, s18, 164012; VI-NEXT: v_or_b32_e32 v3, v2, v14013; VI-NEXT: v_mov_b32_e32 v1, s44014; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD4015; VI-NEXT: v_add_f16_e32 v2, s18, v04016; VI-NEXT: s_lshr_b32 s4, s17, 164017; VI-NEXT: v_or_b32_e32 v2, v2, v14018; VI-NEXT: v_mov_b32_e32 v1, s44019; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD4020; VI-NEXT: v_add_f16_e32 v14, s17, v04021; VI-NEXT: s_lshr_b32 s4, s16, 164022; VI-NEXT: v_or_b32_e32 v1, v14, v14023; VI-NEXT: v_mov_b32_e32 v14, s44024; VI-NEXT: v_add_f16_sdwa v14, v14, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD4025; VI-NEXT: v_add_f16_e32 v0, s16, v04026; VI-NEXT: v_or_b32_e32 v0, v0, v144027; VI-NEXT: s_setpc_b64 s[30:31]4028; VI-NEXT: .LBB19_3:4029; VI-NEXT: s_branch .LBB19_24030; VI-NEXT: .LBB19_4:4031; VI-NEXT: v_mov_b32_e32 v0, s164032; VI-NEXT: v_mov_b32_e32 v1, s174033; VI-NEXT: v_mov_b32_e32 v2, s184034; VI-NEXT: v_mov_b32_e32 v3, s194035; VI-NEXT: v_mov_b32_e32 v4, s204036; VI-NEXT: v_mov_b32_e32 v5, s214037; VI-NEXT: v_mov_b32_e32 v6, s224038; VI-NEXT: v_mov_b32_e32 v7, s234039; VI-NEXT: v_mov_b32_e32 v8, s244040; VI-NEXT: v_mov_b32_e32 v9, s254041; VI-NEXT: v_mov_b32_e32 v10, s264042; VI-NEXT: v_mov_b32_e32 v11, s274043; VI-NEXT: v_mov_b32_e32 v12, s284044; VI-NEXT: v_mov_b32_e32 v13, s294045; VI-NEXT: v_mov_b32_e32 v14, s304046; VI-NEXT: v_mov_b32_e32 v15, s314047; VI-NEXT: s_setpc_b64 s[30:31]4048;4049; GFX9-LABEL: bitcast_v28f16_to_v14i32_scalar:4050; GFX9: ; %bb.0:4051; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4052; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v04053; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec4054; GFX9-NEXT: s_cbranch_scc0 .LBB19_34055; GFX9-NEXT: ; %bb.1: ; %cmp.false4056; GFX9-NEXT: s_cbranch_execnz .LBB19_44057; GFX9-NEXT: .LBB19_2: ; %cmp.true4058; GFX9-NEXT: v_mov_b32_e32 v0, 0x2004059; GFX9-NEXT: v_pk_add_f16 v13, s29, v0 op_sel_hi:[1,0]4060; GFX9-NEXT: v_pk_add_f16 v12, s28, v0 op_sel_hi:[1,0]4061; GFX9-NEXT: v_pk_add_f16 v11, s27, v0 op_sel_hi:[1,0]4062; GFX9-NEXT: v_pk_add_f16 v10, s26, v0 op_sel_hi:[1,0]4063; GFX9-NEXT: v_pk_add_f16 v9, s25, v0 op_sel_hi:[1,0]4064; GFX9-NEXT: v_pk_add_f16 v8, s24, v0 op_sel_hi:[1,0]4065; GFX9-NEXT: v_pk_add_f16 v7, s23, v0 op_sel_hi:[1,0]4066; GFX9-NEXT: v_pk_add_f16 v6, s22, v0 op_sel_hi:[1,0]4067; GFX9-NEXT: v_pk_add_f16 v5, s21, v0 op_sel_hi:[1,0]4068; GFX9-NEXT: v_pk_add_f16 v4, s20, v0 op_sel_hi:[1,0]4069; GFX9-NEXT: v_pk_add_f16 v3, s19, v0 op_sel_hi:[1,0]4070; GFX9-NEXT: v_pk_add_f16 v2, s18, v0 op_sel_hi:[1,0]4071; GFX9-NEXT: v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]4072; GFX9-NEXT: v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]4073; GFX9-NEXT: s_setpc_b64 s[30:31]4074; GFX9-NEXT: .LBB19_3:4075; GFX9-NEXT: s_branch .LBB19_24076; GFX9-NEXT: .LBB19_4:4077; GFX9-NEXT: v_mov_b32_e32 v0, s164078; GFX9-NEXT: v_mov_b32_e32 v1, s174079; GFX9-NEXT: v_mov_b32_e32 v2, s184080; GFX9-NEXT: v_mov_b32_e32 v3, s194081; GFX9-NEXT: v_mov_b32_e32 v4, s204082; GFX9-NEXT: v_mov_b32_e32 v5, s214083; GFX9-NEXT: v_mov_b32_e32 v6, s224084; GFX9-NEXT: v_mov_b32_e32 v7, s234085; GFX9-NEXT: v_mov_b32_e32 v8, s244086; GFX9-NEXT: v_mov_b32_e32 v9, s254087; GFX9-NEXT: v_mov_b32_e32 v10, s264088; GFX9-NEXT: v_mov_b32_e32 v11, s274089; GFX9-NEXT: v_mov_b32_e32 v12, s284090; GFX9-NEXT: v_mov_b32_e32 v13, s294091; GFX9-NEXT: v_mov_b32_e32 v14, s304092; GFX9-NEXT: v_mov_b32_e32 v15, s314093; GFX9-NEXT: s_setpc_b64 s[30:31]4094;4095; GFX11-LABEL: bitcast_v28f16_to_v14i32_scalar:4096; GFX11: ; %bb.0:4097; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4098; GFX11-NEXT: s_mov_b32 s15, s34099; GFX11-NEXT: s_mov_b32 s14, s24100; GFX11-NEXT: s_mov_b32 s13, s14101; GFX11-NEXT: s_mov_b32 s12, s04102; GFX11-NEXT: s_cmp_lg_u32 s26, 04103; GFX11-NEXT: s_mov_b32 s0, 04104; GFX11-NEXT: s_cbranch_scc0 .LBB19_34105; GFX11-NEXT: ; %bb.1: ; %Flow4106; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s04107; GFX11-NEXT: s_cbranch_vccnz .LBB19_44108; GFX11-NEXT: .LBB19_2: ; %cmp.true4109; GFX11-NEXT: v_pk_add_f16 v13, 0x200, s25 op_sel_hi:[0,1]4110; GFX11-NEXT: v_pk_add_f16 v12, 0x200, s24 op_sel_hi:[0,1]4111; GFX11-NEXT: v_pk_add_f16 v11, 0x200, s23 op_sel_hi:[0,1]4112; GFX11-NEXT: v_pk_add_f16 v10, 0x200, s22 op_sel_hi:[0,1]4113; GFX11-NEXT: v_pk_add_f16 v9, 0x200, s21 op_sel_hi:[0,1]4114; GFX11-NEXT: v_pk_add_f16 v8, 0x200, s20 op_sel_hi:[0,1]4115; GFX11-NEXT: v_pk_add_f16 v7, 0x200, s19 op_sel_hi:[0,1]4116; GFX11-NEXT: v_pk_add_f16 v6, 0x200, s18 op_sel_hi:[0,1]4117; GFX11-NEXT: v_pk_add_f16 v5, 0x200, s17 op_sel_hi:[0,1]4118; GFX11-NEXT: v_pk_add_f16 v4, 0x200, s16 op_sel_hi:[0,1]4119; GFX11-NEXT: v_pk_add_f16 v3, 0x200, s15 op_sel_hi:[0,1]4120; GFX11-NEXT: v_pk_add_f16 v2, 0x200, s14 op_sel_hi:[0,1]4121; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s13 op_sel_hi:[0,1]4122; GFX11-NEXT: v_pk_add_f16 v0, 0x200, s12 op_sel_hi:[0,1]4123; GFX11-NEXT: s_setpc_b64 s[30:31]4124; GFX11-NEXT: .LBB19_3:4125; GFX11-NEXT: s_branch .LBB19_24126; GFX11-NEXT: .LBB19_4:4127; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s134128; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s154129; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s174130; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s194131; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s214132; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s234133; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s254134; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s274135; GFX11-NEXT: s_setpc_b64 s[30:31]4136 %cmp = icmp eq i32 %b, 04137 br i1 %cmp, label %cmp.true, label %cmp.false4138 4139cmp.true:4140 %a1 = fadd <28 x half> %a, splat (half 0xH0200)4141 %a2 = bitcast <28 x half> %a1 to <14 x i32>4142 br label %end4143 4144cmp.false:4145 %a3 = bitcast <28 x half> %a to <14 x i32>4146 br label %end4147 4148end:4149 %phi = phi <14 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]4150 ret <14 x i32> %phi4151}4152 4153define <7 x i64> @bitcast_v14f32_to_v7i64(<14 x float> %a, i32 %b) {4154; SI-LABEL: bitcast_v14f32_to_v7i64:4155; SI: ; %bb.0:4156; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4157; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v144158; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc4159; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]4160; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]4161; SI-NEXT: s_cbranch_execz .LBB20_24162; SI-NEXT: ; %bb.1: ; %cmp.true4163; SI-NEXT: v_add_f32_e32 v13, 1.0, v134164; SI-NEXT: v_add_f32_e32 v12, 1.0, v124165; SI-NEXT: v_add_f32_e32 v11, 1.0, v114166; SI-NEXT: v_add_f32_e32 v10, 1.0, v104167; SI-NEXT: v_add_f32_e32 v9, 1.0, v94168; SI-NEXT: v_add_f32_e32 v8, 1.0, v84169; SI-NEXT: v_add_f32_e32 v7, 1.0, v74170; SI-NEXT: v_add_f32_e32 v6, 1.0, v64171; SI-NEXT: v_add_f32_e32 v5, 1.0, v54172; SI-NEXT: v_add_f32_e32 v4, 1.0, v44173; SI-NEXT: v_add_f32_e32 v3, 1.0, v34174; SI-NEXT: v_add_f32_e32 v2, 1.0, v24175; SI-NEXT: v_add_f32_e32 v1, 1.0, v14176; SI-NEXT: v_add_f32_e32 v0, 1.0, v04177; SI-NEXT: .LBB20_2: ; %end4178; SI-NEXT: s_or_b64 exec, exec, s[4:5]4179; SI-NEXT: s_setpc_b64 s[30:31]4180;4181; VI-LABEL: bitcast_v14f32_to_v7i64:4182; VI: ; %bb.0:4183; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4184; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v144185; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc4186; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]4187; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]4188; VI-NEXT: s_cbranch_execz .LBB20_24189; VI-NEXT: ; %bb.1: ; %cmp.true4190; VI-NEXT: v_add_f32_e32 v13, 1.0, v134191; VI-NEXT: v_add_f32_e32 v12, 1.0, v124192; VI-NEXT: v_add_f32_e32 v11, 1.0, v114193; VI-NEXT: v_add_f32_e32 v10, 1.0, v104194; VI-NEXT: v_add_f32_e32 v9, 1.0, v94195; VI-NEXT: v_add_f32_e32 v8, 1.0, v84196; VI-NEXT: v_add_f32_e32 v7, 1.0, v74197; VI-NEXT: v_add_f32_e32 v6, 1.0, v64198; VI-NEXT: v_add_f32_e32 v5, 1.0, v54199; VI-NEXT: v_add_f32_e32 v4, 1.0, v44200; VI-NEXT: v_add_f32_e32 v3, 1.0, v34201; VI-NEXT: v_add_f32_e32 v2, 1.0, v24202; VI-NEXT: v_add_f32_e32 v1, 1.0, v14203; VI-NEXT: v_add_f32_e32 v0, 1.0, v04204; VI-NEXT: .LBB20_2: ; %end4205; VI-NEXT: s_or_b64 exec, exec, s[4:5]4206; VI-NEXT: s_setpc_b64 s[30:31]4207;4208; GFX9-LABEL: bitcast_v14f32_to_v7i64:4209; GFX9: ; %bb.0:4210; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4211; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v144212; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc4213; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]4214; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]4215; GFX9-NEXT: s_cbranch_execz .LBB20_24216; GFX9-NEXT: ; %bb.1: ; %cmp.true4217; GFX9-NEXT: v_add_f32_e32 v13, 1.0, v134218; GFX9-NEXT: v_add_f32_e32 v12, 1.0, v124219; GFX9-NEXT: v_add_f32_e32 v11, 1.0, v114220; GFX9-NEXT: v_add_f32_e32 v10, 1.0, v104221; GFX9-NEXT: v_add_f32_e32 v9, 1.0, v94222; GFX9-NEXT: v_add_f32_e32 v8, 1.0, v84223; GFX9-NEXT: v_add_f32_e32 v7, 1.0, v74224; GFX9-NEXT: v_add_f32_e32 v6, 1.0, v64225; GFX9-NEXT: v_add_f32_e32 v5, 1.0, v54226; GFX9-NEXT: v_add_f32_e32 v4, 1.0, v44227; GFX9-NEXT: v_add_f32_e32 v3, 1.0, v34228; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v24229; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v14230; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v04231; GFX9-NEXT: .LBB20_2: ; %end4232; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]4233; GFX9-NEXT: s_setpc_b64 s[30:31]4234;4235; GFX11-LABEL: bitcast_v14f32_to_v7i64:4236; GFX11: ; %bb.0:4237; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4238; GFX11-NEXT: s_mov_b32 s0, exec_lo4239; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v144240; GFX11-NEXT: s_xor_b32 s0, exec_lo, s04241; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)4242; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s04243; GFX11-NEXT: s_cbranch_execz .LBB20_24244; GFX11-NEXT: ; %bb.1: ; %cmp.true4245; GFX11-NEXT: v_dual_add_f32 v13, 1.0, v13 :: v_dual_add_f32 v12, 1.0, v124246; GFX11-NEXT: v_dual_add_f32 v11, 1.0, v11 :: v_dual_add_f32 v10, 1.0, v104247; GFX11-NEXT: v_dual_add_f32 v9, 1.0, v9 :: v_dual_add_f32 v8, 1.0, v84248; GFX11-NEXT: v_dual_add_f32 v7, 1.0, v7 :: v_dual_add_f32 v6, 1.0, v64249; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v44250; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v24251; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v04252; GFX11-NEXT: .LBB20_2: ; %end4253; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s04254; GFX11-NEXT: s_setpc_b64 s[30:31]4255 %cmp = icmp eq i32 %b, 04256 br i1 %cmp, label %cmp.true, label %cmp.false4257 4258cmp.true:4259 %a1 = fadd <14 x float> %a, splat (float 1.000000e+00)4260 %a2 = bitcast <14 x float> %a1 to <7 x i64>4261 br label %end4262 4263cmp.false:4264 %a3 = bitcast <14 x float> %a to <7 x i64>4265 br label %end4266 4267end:4268 %phi = phi <7 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]4269 ret <7 x i64> %phi4270}4271 4272define inreg <7 x i64> @bitcast_v14f32_to_v7i64_scalar(<14 x float> inreg %a, i32 inreg %b) {4273; SI-LABEL: bitcast_v14f32_to_v7i64_scalar:4274; SI: ; %bb.0:4275; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4276; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v04277; SI-NEXT: s_and_b64 s[4:5], vcc, exec4278; SI-NEXT: s_cbranch_scc0 .LBB21_34279; SI-NEXT: ; %bb.1: ; %cmp.false4280; SI-NEXT: s_cbranch_execnz .LBB21_44281; SI-NEXT: .LBB21_2: ; %cmp.true4282; SI-NEXT: v_add_f32_e64 v13, s29, 1.04283; SI-NEXT: v_add_f32_e64 v12, s28, 1.04284; SI-NEXT: v_add_f32_e64 v11, s27, 1.04285; SI-NEXT: v_add_f32_e64 v10, s26, 1.04286; SI-NEXT: v_add_f32_e64 v9, s25, 1.04287; SI-NEXT: v_add_f32_e64 v8, s24, 1.04288; SI-NEXT: v_add_f32_e64 v7, s23, 1.04289; SI-NEXT: v_add_f32_e64 v6, s22, 1.04290; SI-NEXT: v_add_f32_e64 v5, s21, 1.04291; SI-NEXT: v_add_f32_e64 v4, s20, 1.04292; SI-NEXT: v_add_f32_e64 v3, s19, 1.04293; SI-NEXT: v_add_f32_e64 v2, s18, 1.04294; SI-NEXT: v_add_f32_e64 v1, s17, 1.04295; SI-NEXT: v_add_f32_e64 v0, s16, 1.04296; SI-NEXT: s_setpc_b64 s[30:31]4297; SI-NEXT: .LBB21_3:4298; SI-NEXT: s_branch .LBB21_24299; SI-NEXT: .LBB21_4:4300; SI-NEXT: v_mov_b32_e32 v0, s164301; SI-NEXT: v_mov_b32_e32 v1, s174302; SI-NEXT: v_mov_b32_e32 v2, s184303; SI-NEXT: v_mov_b32_e32 v3, s194304; SI-NEXT: v_mov_b32_e32 v4, s204305; SI-NEXT: v_mov_b32_e32 v5, s214306; SI-NEXT: v_mov_b32_e32 v6, s224307; SI-NEXT: v_mov_b32_e32 v7, s234308; SI-NEXT: v_mov_b32_e32 v8, s244309; SI-NEXT: v_mov_b32_e32 v9, s254310; SI-NEXT: v_mov_b32_e32 v10, s264311; SI-NEXT: v_mov_b32_e32 v11, s274312; SI-NEXT: v_mov_b32_e32 v12, s284313; SI-NEXT: v_mov_b32_e32 v13, s294314; SI-NEXT: v_mov_b32_e32 v14, s304315; SI-NEXT: v_mov_b32_e32 v15, s314316; SI-NEXT: s_setpc_b64 s[30:31]4317;4318; VI-LABEL: bitcast_v14f32_to_v7i64_scalar:4319; VI: ; %bb.0:4320; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4321; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v04322; VI-NEXT: s_and_b64 s[4:5], vcc, exec4323; VI-NEXT: s_cbranch_scc0 .LBB21_34324; VI-NEXT: ; %bb.1: ; %cmp.false4325; VI-NEXT: s_cbranch_execnz .LBB21_44326; VI-NEXT: .LBB21_2: ; %cmp.true4327; VI-NEXT: v_add_f32_e64 v13, s29, 1.04328; VI-NEXT: v_add_f32_e64 v12, s28, 1.04329; VI-NEXT: v_add_f32_e64 v11, s27, 1.04330; VI-NEXT: v_add_f32_e64 v10, s26, 1.04331; VI-NEXT: v_add_f32_e64 v9, s25, 1.04332; VI-NEXT: v_add_f32_e64 v8, s24, 1.04333; VI-NEXT: v_add_f32_e64 v7, s23, 1.04334; VI-NEXT: v_add_f32_e64 v6, s22, 1.04335; VI-NEXT: v_add_f32_e64 v5, s21, 1.04336; VI-NEXT: v_add_f32_e64 v4, s20, 1.04337; VI-NEXT: v_add_f32_e64 v3, s19, 1.04338; VI-NEXT: v_add_f32_e64 v2, s18, 1.04339; VI-NEXT: v_add_f32_e64 v1, s17, 1.04340; VI-NEXT: v_add_f32_e64 v0, s16, 1.04341; VI-NEXT: s_setpc_b64 s[30:31]4342; VI-NEXT: .LBB21_3:4343; VI-NEXT: s_branch .LBB21_24344; VI-NEXT: .LBB21_4:4345; VI-NEXT: v_mov_b32_e32 v0, s164346; VI-NEXT: v_mov_b32_e32 v1, s174347; VI-NEXT: v_mov_b32_e32 v2, s184348; VI-NEXT: v_mov_b32_e32 v3, s194349; VI-NEXT: v_mov_b32_e32 v4, s204350; VI-NEXT: v_mov_b32_e32 v5, s214351; VI-NEXT: v_mov_b32_e32 v6, s224352; VI-NEXT: v_mov_b32_e32 v7, s234353; VI-NEXT: v_mov_b32_e32 v8, s244354; VI-NEXT: v_mov_b32_e32 v9, s254355; VI-NEXT: v_mov_b32_e32 v10, s264356; VI-NEXT: v_mov_b32_e32 v11, s274357; VI-NEXT: v_mov_b32_e32 v12, s284358; VI-NEXT: v_mov_b32_e32 v13, s294359; VI-NEXT: v_mov_b32_e32 v14, s304360; VI-NEXT: v_mov_b32_e32 v15, s314361; VI-NEXT: s_setpc_b64 s[30:31]4362;4363; GFX9-LABEL: bitcast_v14f32_to_v7i64_scalar:4364; GFX9: ; %bb.0:4365; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4366; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v04367; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec4368; GFX9-NEXT: s_cbranch_scc0 .LBB21_34369; GFX9-NEXT: ; %bb.1: ; %cmp.false4370; GFX9-NEXT: s_cbranch_execnz .LBB21_44371; GFX9-NEXT: .LBB21_2: ; %cmp.true4372; GFX9-NEXT: v_add_f32_e64 v13, s29, 1.04373; GFX9-NEXT: v_add_f32_e64 v12, s28, 1.04374; GFX9-NEXT: v_add_f32_e64 v11, s27, 1.04375; GFX9-NEXT: v_add_f32_e64 v10, s26, 1.04376; GFX9-NEXT: v_add_f32_e64 v9, s25, 1.04377; GFX9-NEXT: v_add_f32_e64 v8, s24, 1.04378; GFX9-NEXT: v_add_f32_e64 v7, s23, 1.04379; GFX9-NEXT: v_add_f32_e64 v6, s22, 1.04380; GFX9-NEXT: v_add_f32_e64 v5, s21, 1.04381; GFX9-NEXT: v_add_f32_e64 v4, s20, 1.04382; GFX9-NEXT: v_add_f32_e64 v3, s19, 1.04383; GFX9-NEXT: v_add_f32_e64 v2, s18, 1.04384; GFX9-NEXT: v_add_f32_e64 v1, s17, 1.04385; GFX9-NEXT: v_add_f32_e64 v0, s16, 1.04386; GFX9-NEXT: s_setpc_b64 s[30:31]4387; GFX9-NEXT: .LBB21_3:4388; GFX9-NEXT: s_branch .LBB21_24389; GFX9-NEXT: .LBB21_4:4390; GFX9-NEXT: v_mov_b32_e32 v0, s164391; GFX9-NEXT: v_mov_b32_e32 v1, s174392; GFX9-NEXT: v_mov_b32_e32 v2, s184393; GFX9-NEXT: v_mov_b32_e32 v3, s194394; GFX9-NEXT: v_mov_b32_e32 v4, s204395; GFX9-NEXT: v_mov_b32_e32 v5, s214396; GFX9-NEXT: v_mov_b32_e32 v6, s224397; GFX9-NEXT: v_mov_b32_e32 v7, s234398; GFX9-NEXT: v_mov_b32_e32 v8, s244399; GFX9-NEXT: v_mov_b32_e32 v9, s254400; GFX9-NEXT: v_mov_b32_e32 v10, s264401; GFX9-NEXT: v_mov_b32_e32 v11, s274402; GFX9-NEXT: v_mov_b32_e32 v12, s284403; GFX9-NEXT: v_mov_b32_e32 v13, s294404; GFX9-NEXT: v_mov_b32_e32 v14, s304405; GFX9-NEXT: v_mov_b32_e32 v15, s314406; GFX9-NEXT: s_setpc_b64 s[30:31]4407;4408; GFX11-LABEL: bitcast_v14f32_to_v7i64_scalar:4409; GFX11: ; %bb.0:4410; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4411; GFX11-NEXT: s_mov_b32 s15, s34412; GFX11-NEXT: s_mov_b32 s14, s24413; GFX11-NEXT: s_mov_b32 s13, s14414; GFX11-NEXT: s_mov_b32 s12, s04415; GFX11-NEXT: s_cmp_lg_u32 s26, 04416; GFX11-NEXT: s_mov_b32 s0, 04417; GFX11-NEXT: s_cbranch_scc0 .LBB21_34418; GFX11-NEXT: ; %bb.1: ; %Flow4419; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s04420; GFX11-NEXT: s_cbranch_vccnz .LBB21_44421; GFX11-NEXT: .LBB21_2: ; %cmp.true4422; GFX11-NEXT: v_add_f32_e64 v13, s25, 1.04423; GFX11-NEXT: v_add_f32_e64 v12, s24, 1.04424; GFX11-NEXT: v_add_f32_e64 v11, s23, 1.04425; GFX11-NEXT: v_add_f32_e64 v10, s22, 1.04426; GFX11-NEXT: v_add_f32_e64 v9, s21, 1.04427; GFX11-NEXT: v_add_f32_e64 v8, s20, 1.04428; GFX11-NEXT: v_add_f32_e64 v7, s19, 1.04429; GFX11-NEXT: v_add_f32_e64 v6, s18, 1.04430; GFX11-NEXT: v_add_f32_e64 v5, s17, 1.04431; GFX11-NEXT: v_add_f32_e64 v4, s16, 1.04432; GFX11-NEXT: v_add_f32_e64 v3, s15, 1.04433; GFX11-NEXT: v_add_f32_e64 v2, s14, 1.04434; GFX11-NEXT: v_add_f32_e64 v1, s13, 1.04435; GFX11-NEXT: v_add_f32_e64 v0, s12, 1.04436; GFX11-NEXT: s_setpc_b64 s[30:31]4437; GFX11-NEXT: .LBB21_3:4438; GFX11-NEXT: s_branch .LBB21_24439; GFX11-NEXT: .LBB21_4:4440; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s134441; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s154442; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s174443; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s194444; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s214445; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s234446; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s254447; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s274448; GFX11-NEXT: s_setpc_b64 s[30:31]4449 %cmp = icmp eq i32 %b, 04450 br i1 %cmp, label %cmp.true, label %cmp.false4451 4452cmp.true:4453 %a1 = fadd <14 x float> %a, splat (float 1.000000e+00)4454 %a2 = bitcast <14 x float> %a1 to <7 x i64>4455 br label %end4456 4457cmp.false:4458 %a3 = bitcast <14 x float> %a to <7 x i64>4459 br label %end4460 4461end:4462 %phi = phi <7 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]4463 ret <7 x i64> %phi4464}4465 4466define <14 x float> @bitcast_v7i64_to_v14f32(<7 x i64> %a, i32 %b) {4467; SI-LABEL: bitcast_v7i64_to_v14f32:4468; SI: ; %bb.0:4469; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4470; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v144471; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc4472; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]4473; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]4474; SI-NEXT: s_cbranch_execz .LBB22_24475; SI-NEXT: ; %bb.1: ; %cmp.true4476; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v124477; SI-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc4478; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v104479; SI-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc4480; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v84481; SI-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc4482; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v64483; SI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc4484; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v44485; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc4486; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v24487; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc4488; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v04489; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc4490; SI-NEXT: .LBB22_2: ; %end4491; SI-NEXT: s_or_b64 exec, exec, s[4:5]4492; SI-NEXT: s_setpc_b64 s[30:31]4493;4494; VI-LABEL: bitcast_v7i64_to_v14f32:4495; VI: ; %bb.0:4496; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4497; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v144498; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc4499; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]4500; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]4501; VI-NEXT: s_cbranch_execz .LBB22_24502; VI-NEXT: ; %bb.1: ; %cmp.true4503; VI-NEXT: v_add_u32_e32 v12, vcc, 3, v124504; VI-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc4505; VI-NEXT: v_add_u32_e32 v10, vcc, 3, v104506; VI-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc4507; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v84508; VI-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc4509; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v64510; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc4511; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v44512; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc4513; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v24514; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc4515; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v04516; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc4517; VI-NEXT: .LBB22_2: ; %end4518; VI-NEXT: s_or_b64 exec, exec, s[4:5]4519; VI-NEXT: s_setpc_b64 s[30:31]4520;4521; GFX9-LABEL: bitcast_v7i64_to_v14f32:4522; GFX9: ; %bb.0:4523; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4524; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v144525; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc4526; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]4527; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]4528; GFX9-NEXT: s_cbranch_execz .LBB22_24529; GFX9-NEXT: ; %bb.1: ; %cmp.true4530; GFX9-NEXT: v_add_co_u32_e32 v12, vcc, 3, v124531; GFX9-NEXT: v_addc_co_u32_e32 v13, vcc, 0, v13, vcc4532; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, 3, v104533; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v11, vcc4534; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, 3, v84535; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v9, vcc4536; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, 3, v64537; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v7, vcc4538; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, 3, v44539; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc4540; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 3, v24541; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc4542; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v04543; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc4544; GFX9-NEXT: .LBB22_2: ; %end4545; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]4546; GFX9-NEXT: s_setpc_b64 s[30:31]4547;4548; GFX11-LABEL: bitcast_v7i64_to_v14f32:4549; GFX11: ; %bb.0:4550; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4551; GFX11-NEXT: s_mov_b32 s0, exec_lo4552; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v144553; GFX11-NEXT: s_xor_b32 s0, exec_lo, s04554; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)4555; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s04556; GFX11-NEXT: s_cbranch_execz .LBB22_24557; GFX11-NEXT: ; %bb.1: ; %cmp.true4558; GFX11-NEXT: v_add_co_u32 v12, vcc_lo, v12, 34559; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)4560; GFX11-NEXT: v_add_co_ci_u32_e64 v13, null, 0, v13, vcc_lo4561; GFX11-NEXT: v_add_co_u32 v10, vcc_lo, v10, 34562; GFX11-NEXT: v_add_co_ci_u32_e64 v11, null, 0, v11, vcc_lo4563; GFX11-NEXT: v_add_co_u32 v8, vcc_lo, v8, 34564; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)4565; GFX11-NEXT: v_add_co_ci_u32_e64 v9, null, 0, v9, vcc_lo4566; GFX11-NEXT: v_add_co_u32 v6, vcc_lo, v6, 34567; GFX11-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v7, vcc_lo4568; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v4, 34569; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)4570; GFX11-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo4571; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, 34572; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo4573; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 34574; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)4575; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo4576; GFX11-NEXT: .LBB22_2: ; %end4577; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s04578; GFX11-NEXT: s_setpc_b64 s[30:31]4579 %cmp = icmp eq i32 %b, 04580 br i1 %cmp, label %cmp.true, label %cmp.false4581 4582cmp.true:4583 %a1 = add <7 x i64> %a, splat (i64 3)4584 %a2 = bitcast <7 x i64> %a1 to <14 x float>4585 br label %end4586 4587cmp.false:4588 %a3 = bitcast <7 x i64> %a to <14 x float>4589 br label %end4590 4591end:4592 %phi = phi <14 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]4593 ret <14 x float> %phi4594}4595 4596define inreg <14 x float> @bitcast_v7i64_to_v14f32_scalar(<7 x i64> inreg %a, i32 inreg %b) {4597; SI-LABEL: bitcast_v7i64_to_v14f32_scalar:4598; SI: ; %bb.0:4599; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4600; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v04601; SI-NEXT: s_and_b64 s[4:5], vcc, exec4602; SI-NEXT: s_cbranch_scc0 .LBB23_44603; SI-NEXT: ; %bb.1: ; %cmp.false4604; SI-NEXT: s_cbranch_execnz .LBB23_34605; SI-NEXT: .LBB23_2: ; %cmp.true4606; SI-NEXT: s_add_u32 s28, s28, 34607; SI-NEXT: s_addc_u32 s29, s29, 04608; SI-NEXT: s_add_u32 s26, s26, 34609; SI-NEXT: s_addc_u32 s27, s27, 04610; SI-NEXT: s_add_u32 s24, s24, 34611; SI-NEXT: s_addc_u32 s25, s25, 04612; SI-NEXT: s_add_u32 s22, s22, 34613; SI-NEXT: s_addc_u32 s23, s23, 04614; SI-NEXT: s_add_u32 s20, s20, 34615; SI-NEXT: s_addc_u32 s21, s21, 04616; SI-NEXT: s_add_u32 s18, s18, 34617; SI-NEXT: s_addc_u32 s19, s19, 04618; SI-NEXT: s_add_u32 s16, s16, 34619; SI-NEXT: s_addc_u32 s17, s17, 04620; SI-NEXT: .LBB23_3: ; %end4621; SI-NEXT: v_mov_b32_e32 v0, s164622; SI-NEXT: v_mov_b32_e32 v1, s174623; SI-NEXT: v_mov_b32_e32 v2, s184624; SI-NEXT: v_mov_b32_e32 v3, s194625; SI-NEXT: v_mov_b32_e32 v4, s204626; SI-NEXT: v_mov_b32_e32 v5, s214627; SI-NEXT: v_mov_b32_e32 v6, s224628; SI-NEXT: v_mov_b32_e32 v7, s234629; SI-NEXT: v_mov_b32_e32 v8, s244630; SI-NEXT: v_mov_b32_e32 v9, s254631; SI-NEXT: v_mov_b32_e32 v10, s264632; SI-NEXT: v_mov_b32_e32 v11, s274633; SI-NEXT: v_mov_b32_e32 v12, s284634; SI-NEXT: v_mov_b32_e32 v13, s294635; SI-NEXT: s_setpc_b64 s[30:31]4636; SI-NEXT: .LBB23_4:4637; SI-NEXT: s_branch .LBB23_24638;4639; VI-LABEL: bitcast_v7i64_to_v14f32_scalar:4640; VI: ; %bb.0:4641; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4642; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v04643; VI-NEXT: s_and_b64 s[4:5], vcc, exec4644; VI-NEXT: s_cbranch_scc0 .LBB23_44645; VI-NEXT: ; %bb.1: ; %cmp.false4646; VI-NEXT: s_cbranch_execnz .LBB23_34647; VI-NEXT: .LBB23_2: ; %cmp.true4648; VI-NEXT: s_add_u32 s28, s28, 34649; VI-NEXT: s_addc_u32 s29, s29, 04650; VI-NEXT: s_add_u32 s26, s26, 34651; VI-NEXT: s_addc_u32 s27, s27, 04652; VI-NEXT: s_add_u32 s24, s24, 34653; VI-NEXT: s_addc_u32 s25, s25, 04654; VI-NEXT: s_add_u32 s22, s22, 34655; VI-NEXT: s_addc_u32 s23, s23, 04656; VI-NEXT: s_add_u32 s20, s20, 34657; VI-NEXT: s_addc_u32 s21, s21, 04658; VI-NEXT: s_add_u32 s18, s18, 34659; VI-NEXT: s_addc_u32 s19, s19, 04660; VI-NEXT: s_add_u32 s16, s16, 34661; VI-NEXT: s_addc_u32 s17, s17, 04662; VI-NEXT: .LBB23_3: ; %end4663; VI-NEXT: v_mov_b32_e32 v0, s164664; VI-NEXT: v_mov_b32_e32 v1, s174665; VI-NEXT: v_mov_b32_e32 v2, s184666; VI-NEXT: v_mov_b32_e32 v3, s194667; VI-NEXT: v_mov_b32_e32 v4, s204668; VI-NEXT: v_mov_b32_e32 v5, s214669; VI-NEXT: v_mov_b32_e32 v6, s224670; VI-NEXT: v_mov_b32_e32 v7, s234671; VI-NEXT: v_mov_b32_e32 v8, s244672; VI-NEXT: v_mov_b32_e32 v9, s254673; VI-NEXT: v_mov_b32_e32 v10, s264674; VI-NEXT: v_mov_b32_e32 v11, s274675; VI-NEXT: v_mov_b32_e32 v12, s284676; VI-NEXT: v_mov_b32_e32 v13, s294677; VI-NEXT: s_setpc_b64 s[30:31]4678; VI-NEXT: .LBB23_4:4679; VI-NEXT: s_branch .LBB23_24680;4681; GFX9-LABEL: bitcast_v7i64_to_v14f32_scalar:4682; GFX9: ; %bb.0:4683; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4684; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v04685; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec4686; GFX9-NEXT: s_cbranch_scc0 .LBB23_44687; GFX9-NEXT: ; %bb.1: ; %cmp.false4688; GFX9-NEXT: s_cbranch_execnz .LBB23_34689; GFX9-NEXT: .LBB23_2: ; %cmp.true4690; GFX9-NEXT: s_add_u32 s28, s28, 34691; GFX9-NEXT: s_addc_u32 s29, s29, 04692; GFX9-NEXT: s_add_u32 s26, s26, 34693; GFX9-NEXT: s_addc_u32 s27, s27, 04694; GFX9-NEXT: s_add_u32 s24, s24, 34695; GFX9-NEXT: s_addc_u32 s25, s25, 04696; GFX9-NEXT: s_add_u32 s22, s22, 34697; GFX9-NEXT: s_addc_u32 s23, s23, 04698; GFX9-NEXT: s_add_u32 s20, s20, 34699; GFX9-NEXT: s_addc_u32 s21, s21, 04700; GFX9-NEXT: s_add_u32 s18, s18, 34701; GFX9-NEXT: s_addc_u32 s19, s19, 04702; GFX9-NEXT: s_add_u32 s16, s16, 34703; GFX9-NEXT: s_addc_u32 s17, s17, 04704; GFX9-NEXT: .LBB23_3: ; %end4705; GFX9-NEXT: v_mov_b32_e32 v0, s164706; GFX9-NEXT: v_mov_b32_e32 v1, s174707; GFX9-NEXT: v_mov_b32_e32 v2, s184708; GFX9-NEXT: v_mov_b32_e32 v3, s194709; GFX9-NEXT: v_mov_b32_e32 v4, s204710; GFX9-NEXT: v_mov_b32_e32 v5, s214711; GFX9-NEXT: v_mov_b32_e32 v6, s224712; GFX9-NEXT: v_mov_b32_e32 v7, s234713; GFX9-NEXT: v_mov_b32_e32 v8, s244714; GFX9-NEXT: v_mov_b32_e32 v9, s254715; GFX9-NEXT: v_mov_b32_e32 v10, s264716; GFX9-NEXT: v_mov_b32_e32 v11, s274717; GFX9-NEXT: v_mov_b32_e32 v12, s284718; GFX9-NEXT: v_mov_b32_e32 v13, s294719; GFX9-NEXT: s_setpc_b64 s[30:31]4720; GFX9-NEXT: .LBB23_4:4721; GFX9-NEXT: s_branch .LBB23_24722;4723; GFX11-LABEL: bitcast_v7i64_to_v14f32_scalar:4724; GFX11: ; %bb.0:4725; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4726; GFX11-NEXT: s_cmp_lg_u32 s26, 04727; GFX11-NEXT: s_mov_b32 s4, 04728; GFX11-NEXT: s_cbranch_scc0 .LBB23_44729; GFX11-NEXT: ; %bb.1: ; %Flow4730; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s44731; GFX11-NEXT: s_cbranch_vccnz .LBB23_34732; GFX11-NEXT: .LBB23_2: ; %cmp.true4733; GFX11-NEXT: s_add_u32 s24, s24, 34734; GFX11-NEXT: s_addc_u32 s25, s25, 04735; GFX11-NEXT: s_add_u32 s22, s22, 34736; GFX11-NEXT: s_addc_u32 s23, s23, 04737; GFX11-NEXT: s_add_u32 s20, s20, 34738; GFX11-NEXT: s_addc_u32 s21, s21, 04739; GFX11-NEXT: s_add_u32 s18, s18, 34740; GFX11-NEXT: s_addc_u32 s19, s19, 04741; GFX11-NEXT: s_add_u32 s16, s16, 34742; GFX11-NEXT: s_addc_u32 s17, s17, 04743; GFX11-NEXT: s_add_u32 s2, s2, 34744; GFX11-NEXT: s_addc_u32 s3, s3, 04745; GFX11-NEXT: s_add_u32 s0, s0, 34746; GFX11-NEXT: s_addc_u32 s1, s1, 04747; GFX11-NEXT: .LBB23_3: ; %end4748; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)4749; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s14750; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s34751; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s174752; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s194753; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s214754; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s234755; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s254756; GFX11-NEXT: s_setpc_b64 s[30:31]4757; GFX11-NEXT: .LBB23_4:4758; GFX11-NEXT: s_branch .LBB23_24759 %cmp = icmp eq i32 %b, 04760 br i1 %cmp, label %cmp.true, label %cmp.false4761 4762cmp.true:4763 %a1 = add <7 x i64> %a, splat (i64 3)4764 %a2 = bitcast <7 x i64> %a1 to <14 x float>4765 br label %end4766 4767cmp.false:4768 %a3 = bitcast <7 x i64> %a to <14 x float>4769 br label %end4770 4771end:4772 %phi = phi <14 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]4773 ret <14 x float> %phi4774}4775 4776define <7 x double> @bitcast_v14f32_to_v7f64(<14 x float> %a, i32 %b) {4777; SI-LABEL: bitcast_v14f32_to_v7f64:4778; SI: ; %bb.0:4779; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4780; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v144781; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc4782; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]4783; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]4784; SI-NEXT: s_cbranch_execz .LBB24_24785; SI-NEXT: ; %bb.1: ; %cmp.true4786; SI-NEXT: v_add_f32_e32 v13, 1.0, v134787; SI-NEXT: v_add_f32_e32 v12, 1.0, v124788; SI-NEXT: v_add_f32_e32 v11, 1.0, v114789; SI-NEXT: v_add_f32_e32 v10, 1.0, v104790; SI-NEXT: v_add_f32_e32 v9, 1.0, v94791; SI-NEXT: v_add_f32_e32 v8, 1.0, v84792; SI-NEXT: v_add_f32_e32 v7, 1.0, v74793; SI-NEXT: v_add_f32_e32 v6, 1.0, v64794; SI-NEXT: v_add_f32_e32 v5, 1.0, v54795; SI-NEXT: v_add_f32_e32 v4, 1.0, v44796; SI-NEXT: v_add_f32_e32 v3, 1.0, v34797; SI-NEXT: v_add_f32_e32 v2, 1.0, v24798; SI-NEXT: v_add_f32_e32 v1, 1.0, v14799; SI-NEXT: v_add_f32_e32 v0, 1.0, v04800; SI-NEXT: .LBB24_2: ; %end4801; SI-NEXT: s_or_b64 exec, exec, s[4:5]4802; SI-NEXT: s_setpc_b64 s[30:31]4803;4804; VI-LABEL: bitcast_v14f32_to_v7f64:4805; VI: ; %bb.0:4806; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4807; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v144808; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc4809; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]4810; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]4811; VI-NEXT: s_cbranch_execz .LBB24_24812; VI-NEXT: ; %bb.1: ; %cmp.true4813; VI-NEXT: v_add_f32_e32 v13, 1.0, v134814; VI-NEXT: v_add_f32_e32 v12, 1.0, v124815; VI-NEXT: v_add_f32_e32 v11, 1.0, v114816; VI-NEXT: v_add_f32_e32 v10, 1.0, v104817; VI-NEXT: v_add_f32_e32 v9, 1.0, v94818; VI-NEXT: v_add_f32_e32 v8, 1.0, v84819; VI-NEXT: v_add_f32_e32 v7, 1.0, v74820; VI-NEXT: v_add_f32_e32 v6, 1.0, v64821; VI-NEXT: v_add_f32_e32 v5, 1.0, v54822; VI-NEXT: v_add_f32_e32 v4, 1.0, v44823; VI-NEXT: v_add_f32_e32 v3, 1.0, v34824; VI-NEXT: v_add_f32_e32 v2, 1.0, v24825; VI-NEXT: v_add_f32_e32 v1, 1.0, v14826; VI-NEXT: v_add_f32_e32 v0, 1.0, v04827; VI-NEXT: .LBB24_2: ; %end4828; VI-NEXT: s_or_b64 exec, exec, s[4:5]4829; VI-NEXT: s_setpc_b64 s[30:31]4830;4831; GFX9-LABEL: bitcast_v14f32_to_v7f64:4832; GFX9: ; %bb.0:4833; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4834; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v144835; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc4836; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]4837; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]4838; GFX9-NEXT: s_cbranch_execz .LBB24_24839; GFX9-NEXT: ; %bb.1: ; %cmp.true4840; GFX9-NEXT: v_add_f32_e32 v13, 1.0, v134841; GFX9-NEXT: v_add_f32_e32 v12, 1.0, v124842; GFX9-NEXT: v_add_f32_e32 v11, 1.0, v114843; GFX9-NEXT: v_add_f32_e32 v10, 1.0, v104844; GFX9-NEXT: v_add_f32_e32 v9, 1.0, v94845; GFX9-NEXT: v_add_f32_e32 v8, 1.0, v84846; GFX9-NEXT: v_add_f32_e32 v7, 1.0, v74847; GFX9-NEXT: v_add_f32_e32 v6, 1.0, v64848; GFX9-NEXT: v_add_f32_e32 v5, 1.0, v54849; GFX9-NEXT: v_add_f32_e32 v4, 1.0, v44850; GFX9-NEXT: v_add_f32_e32 v3, 1.0, v34851; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v24852; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v14853; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v04854; GFX9-NEXT: .LBB24_2: ; %end4855; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]4856; GFX9-NEXT: s_setpc_b64 s[30:31]4857;4858; GFX11-LABEL: bitcast_v14f32_to_v7f64:4859; GFX11: ; %bb.0:4860; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4861; GFX11-NEXT: s_mov_b32 s0, exec_lo4862; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v144863; GFX11-NEXT: s_xor_b32 s0, exec_lo, s04864; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)4865; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s04866; GFX11-NEXT: s_cbranch_execz .LBB24_24867; GFX11-NEXT: ; %bb.1: ; %cmp.true4868; GFX11-NEXT: v_dual_add_f32 v13, 1.0, v13 :: v_dual_add_f32 v12, 1.0, v124869; GFX11-NEXT: v_dual_add_f32 v11, 1.0, v11 :: v_dual_add_f32 v10, 1.0, v104870; GFX11-NEXT: v_dual_add_f32 v9, 1.0, v9 :: v_dual_add_f32 v8, 1.0, v84871; GFX11-NEXT: v_dual_add_f32 v7, 1.0, v7 :: v_dual_add_f32 v6, 1.0, v64872; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v44873; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v24874; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v04875; GFX11-NEXT: .LBB24_2: ; %end4876; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s04877; GFX11-NEXT: s_setpc_b64 s[30:31]4878 %cmp = icmp eq i32 %b, 04879 br i1 %cmp, label %cmp.true, label %cmp.false4880 4881cmp.true:4882 %a1 = fadd <14 x float> %a, splat (float 1.000000e+00)4883 %a2 = bitcast <14 x float> %a1 to <7 x double>4884 br label %end4885 4886cmp.false:4887 %a3 = bitcast <14 x float> %a to <7 x double>4888 br label %end4889 4890end:4891 %phi = phi <7 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]4892 ret <7 x double> %phi4893}4894 4895define inreg <7 x double> @bitcast_v14f32_to_v7f64_scalar(<14 x float> inreg %a, i32 inreg %b) {4896; SI-LABEL: bitcast_v14f32_to_v7f64_scalar:4897; SI: ; %bb.0:4898; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4899; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v04900; SI-NEXT: s_and_b64 s[4:5], vcc, exec4901; SI-NEXT: s_cbranch_scc0 .LBB25_34902; SI-NEXT: ; %bb.1: ; %cmp.false4903; SI-NEXT: s_cbranch_execnz .LBB25_44904; SI-NEXT: .LBB25_2: ; %cmp.true4905; SI-NEXT: v_add_f32_e64 v13, s29, 1.04906; SI-NEXT: v_add_f32_e64 v12, s28, 1.04907; SI-NEXT: v_add_f32_e64 v11, s27, 1.04908; SI-NEXT: v_add_f32_e64 v10, s26, 1.04909; SI-NEXT: v_add_f32_e64 v9, s25, 1.04910; SI-NEXT: v_add_f32_e64 v8, s24, 1.04911; SI-NEXT: v_add_f32_e64 v7, s23, 1.04912; SI-NEXT: v_add_f32_e64 v6, s22, 1.04913; SI-NEXT: v_add_f32_e64 v5, s21, 1.04914; SI-NEXT: v_add_f32_e64 v4, s20, 1.04915; SI-NEXT: v_add_f32_e64 v3, s19, 1.04916; SI-NEXT: v_add_f32_e64 v2, s18, 1.04917; SI-NEXT: v_add_f32_e64 v1, s17, 1.04918; SI-NEXT: v_add_f32_e64 v0, s16, 1.04919; SI-NEXT: s_setpc_b64 s[30:31]4920; SI-NEXT: .LBB25_3:4921; SI-NEXT: s_branch .LBB25_24922; SI-NEXT: .LBB25_4:4923; SI-NEXT: v_mov_b32_e32 v0, s164924; SI-NEXT: v_mov_b32_e32 v1, s174925; SI-NEXT: v_mov_b32_e32 v2, s184926; SI-NEXT: v_mov_b32_e32 v3, s194927; SI-NEXT: v_mov_b32_e32 v4, s204928; SI-NEXT: v_mov_b32_e32 v5, s214929; SI-NEXT: v_mov_b32_e32 v6, s224930; SI-NEXT: v_mov_b32_e32 v7, s234931; SI-NEXT: v_mov_b32_e32 v8, s244932; SI-NEXT: v_mov_b32_e32 v9, s254933; SI-NEXT: v_mov_b32_e32 v10, s264934; SI-NEXT: v_mov_b32_e32 v11, s274935; SI-NEXT: v_mov_b32_e32 v12, s284936; SI-NEXT: v_mov_b32_e32 v13, s294937; SI-NEXT: v_mov_b32_e32 v14, s304938; SI-NEXT: v_mov_b32_e32 v15, s314939; SI-NEXT: s_setpc_b64 s[30:31]4940;4941; VI-LABEL: bitcast_v14f32_to_v7f64_scalar:4942; VI: ; %bb.0:4943; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4944; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v04945; VI-NEXT: s_and_b64 s[4:5], vcc, exec4946; VI-NEXT: s_cbranch_scc0 .LBB25_34947; VI-NEXT: ; %bb.1: ; %cmp.false4948; VI-NEXT: s_cbranch_execnz .LBB25_44949; VI-NEXT: .LBB25_2: ; %cmp.true4950; VI-NEXT: v_add_f32_e64 v13, s29, 1.04951; VI-NEXT: v_add_f32_e64 v12, s28, 1.04952; VI-NEXT: v_add_f32_e64 v11, s27, 1.04953; VI-NEXT: v_add_f32_e64 v10, s26, 1.04954; VI-NEXT: v_add_f32_e64 v9, s25, 1.04955; VI-NEXT: v_add_f32_e64 v8, s24, 1.04956; VI-NEXT: v_add_f32_e64 v7, s23, 1.04957; VI-NEXT: v_add_f32_e64 v6, s22, 1.04958; VI-NEXT: v_add_f32_e64 v5, s21, 1.04959; VI-NEXT: v_add_f32_e64 v4, s20, 1.04960; VI-NEXT: v_add_f32_e64 v3, s19, 1.04961; VI-NEXT: v_add_f32_e64 v2, s18, 1.04962; VI-NEXT: v_add_f32_e64 v1, s17, 1.04963; VI-NEXT: v_add_f32_e64 v0, s16, 1.04964; VI-NEXT: s_setpc_b64 s[30:31]4965; VI-NEXT: .LBB25_3:4966; VI-NEXT: s_branch .LBB25_24967; VI-NEXT: .LBB25_4:4968; VI-NEXT: v_mov_b32_e32 v0, s164969; VI-NEXT: v_mov_b32_e32 v1, s174970; VI-NEXT: v_mov_b32_e32 v2, s184971; VI-NEXT: v_mov_b32_e32 v3, s194972; VI-NEXT: v_mov_b32_e32 v4, s204973; VI-NEXT: v_mov_b32_e32 v5, s214974; VI-NEXT: v_mov_b32_e32 v6, s224975; VI-NEXT: v_mov_b32_e32 v7, s234976; VI-NEXT: v_mov_b32_e32 v8, s244977; VI-NEXT: v_mov_b32_e32 v9, s254978; VI-NEXT: v_mov_b32_e32 v10, s264979; VI-NEXT: v_mov_b32_e32 v11, s274980; VI-NEXT: v_mov_b32_e32 v12, s284981; VI-NEXT: v_mov_b32_e32 v13, s294982; VI-NEXT: v_mov_b32_e32 v14, s304983; VI-NEXT: v_mov_b32_e32 v15, s314984; VI-NEXT: s_setpc_b64 s[30:31]4985;4986; GFX9-LABEL: bitcast_v14f32_to_v7f64_scalar:4987; GFX9: ; %bb.0:4988; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4989; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v04990; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec4991; GFX9-NEXT: s_cbranch_scc0 .LBB25_34992; GFX9-NEXT: ; %bb.1: ; %cmp.false4993; GFX9-NEXT: s_cbranch_execnz .LBB25_44994; GFX9-NEXT: .LBB25_2: ; %cmp.true4995; GFX9-NEXT: v_add_f32_e64 v13, s29, 1.04996; GFX9-NEXT: v_add_f32_e64 v12, s28, 1.04997; GFX9-NEXT: v_add_f32_e64 v11, s27, 1.04998; GFX9-NEXT: v_add_f32_e64 v10, s26, 1.04999; GFX9-NEXT: v_add_f32_e64 v9, s25, 1.05000; GFX9-NEXT: v_add_f32_e64 v8, s24, 1.05001; GFX9-NEXT: v_add_f32_e64 v7, s23, 1.05002; GFX9-NEXT: v_add_f32_e64 v6, s22, 1.05003; GFX9-NEXT: v_add_f32_e64 v5, s21, 1.05004; GFX9-NEXT: v_add_f32_e64 v4, s20, 1.05005; GFX9-NEXT: v_add_f32_e64 v3, s19, 1.05006; GFX9-NEXT: v_add_f32_e64 v2, s18, 1.05007; GFX9-NEXT: v_add_f32_e64 v1, s17, 1.05008; GFX9-NEXT: v_add_f32_e64 v0, s16, 1.05009; GFX9-NEXT: s_setpc_b64 s[30:31]5010; GFX9-NEXT: .LBB25_3:5011; GFX9-NEXT: s_branch .LBB25_25012; GFX9-NEXT: .LBB25_4:5013; GFX9-NEXT: v_mov_b32_e32 v0, s165014; GFX9-NEXT: v_mov_b32_e32 v1, s175015; GFX9-NEXT: v_mov_b32_e32 v2, s185016; GFX9-NEXT: v_mov_b32_e32 v3, s195017; GFX9-NEXT: v_mov_b32_e32 v4, s205018; GFX9-NEXT: v_mov_b32_e32 v5, s215019; GFX9-NEXT: v_mov_b32_e32 v6, s225020; GFX9-NEXT: v_mov_b32_e32 v7, s235021; GFX9-NEXT: v_mov_b32_e32 v8, s245022; GFX9-NEXT: v_mov_b32_e32 v9, s255023; GFX9-NEXT: v_mov_b32_e32 v10, s265024; GFX9-NEXT: v_mov_b32_e32 v11, s275025; GFX9-NEXT: v_mov_b32_e32 v12, s285026; GFX9-NEXT: v_mov_b32_e32 v13, s295027; GFX9-NEXT: v_mov_b32_e32 v14, s305028; GFX9-NEXT: v_mov_b32_e32 v15, s315029; GFX9-NEXT: s_setpc_b64 s[30:31]5030;5031; GFX11-LABEL: bitcast_v14f32_to_v7f64_scalar:5032; GFX11: ; %bb.0:5033; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5034; GFX11-NEXT: s_mov_b32 s15, s35035; GFX11-NEXT: s_mov_b32 s14, s25036; GFX11-NEXT: s_mov_b32 s13, s15037; GFX11-NEXT: s_mov_b32 s12, s05038; GFX11-NEXT: s_cmp_lg_u32 s26, 05039; GFX11-NEXT: s_mov_b32 s0, 05040; GFX11-NEXT: s_cbranch_scc0 .LBB25_35041; GFX11-NEXT: ; %bb.1: ; %Flow5042; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s05043; GFX11-NEXT: s_cbranch_vccnz .LBB25_45044; GFX11-NEXT: .LBB25_2: ; %cmp.true5045; GFX11-NEXT: v_add_f32_e64 v13, s25, 1.05046; GFX11-NEXT: v_add_f32_e64 v12, s24, 1.05047; GFX11-NEXT: v_add_f32_e64 v11, s23, 1.05048; GFX11-NEXT: v_add_f32_e64 v10, s22, 1.05049; GFX11-NEXT: v_add_f32_e64 v9, s21, 1.05050; GFX11-NEXT: v_add_f32_e64 v8, s20, 1.05051; GFX11-NEXT: v_add_f32_e64 v7, s19, 1.05052; GFX11-NEXT: v_add_f32_e64 v6, s18, 1.05053; GFX11-NEXT: v_add_f32_e64 v5, s17, 1.05054; GFX11-NEXT: v_add_f32_e64 v4, s16, 1.05055; GFX11-NEXT: v_add_f32_e64 v3, s15, 1.05056; GFX11-NEXT: v_add_f32_e64 v2, s14, 1.05057; GFX11-NEXT: v_add_f32_e64 v1, s13, 1.05058; GFX11-NEXT: v_add_f32_e64 v0, s12, 1.05059; GFX11-NEXT: s_setpc_b64 s[30:31]5060; GFX11-NEXT: .LBB25_3:5061; GFX11-NEXT: s_branch .LBB25_25062; GFX11-NEXT: .LBB25_4:5063; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s135064; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s155065; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s175066; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s195067; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s215068; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s235069; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s255070; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s275071; GFX11-NEXT: s_setpc_b64 s[30:31]5072 %cmp = icmp eq i32 %b, 05073 br i1 %cmp, label %cmp.true, label %cmp.false5074 5075cmp.true:5076 %a1 = fadd <14 x float> %a, splat (float 1.000000e+00)5077 %a2 = bitcast <14 x float> %a1 to <7 x double>5078 br label %end5079 5080cmp.false:5081 %a3 = bitcast <14 x float> %a to <7 x double>5082 br label %end5083 5084end:5085 %phi = phi <7 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]5086 ret <7 x double> %phi5087}5088 5089define <14 x float> @bitcast_v7f64_to_v14f32(<7 x double> %a, i32 %b) {5090; SI-LABEL: bitcast_v7f64_to_v14f32:5091; SI: ; %bb.0:5092; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5093; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v145094; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc5095; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]5096; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]5097; SI-NEXT: s_cbranch_execz .LBB26_25098; SI-NEXT: ; %bb.1: ; %cmp.true5099; SI-NEXT: v_add_f64 v[12:13], v[12:13], 1.05100; SI-NEXT: v_add_f64 v[10:11], v[10:11], 1.05101; SI-NEXT: v_add_f64 v[8:9], v[8:9], 1.05102; SI-NEXT: v_add_f64 v[6:7], v[6:7], 1.05103; SI-NEXT: v_add_f64 v[4:5], v[4:5], 1.05104; SI-NEXT: v_add_f64 v[2:3], v[2:3], 1.05105; SI-NEXT: v_add_f64 v[0:1], v[0:1], 1.05106; SI-NEXT: .LBB26_2: ; %end5107; SI-NEXT: s_or_b64 exec, exec, s[4:5]5108; SI-NEXT: s_setpc_b64 s[30:31]5109;5110; VI-LABEL: bitcast_v7f64_to_v14f32:5111; VI: ; %bb.0:5112; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5113; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v145114; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc5115; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]5116; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]5117; VI-NEXT: s_cbranch_execz .LBB26_25118; VI-NEXT: ; %bb.1: ; %cmp.true5119; VI-NEXT: v_add_f64 v[12:13], v[12:13], 1.05120; VI-NEXT: v_add_f64 v[10:11], v[10:11], 1.05121; VI-NEXT: v_add_f64 v[8:9], v[8:9], 1.05122; VI-NEXT: v_add_f64 v[6:7], v[6:7], 1.05123; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.05124; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.05125; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.05126; VI-NEXT: .LBB26_2: ; %end5127; VI-NEXT: s_or_b64 exec, exec, s[4:5]5128; VI-NEXT: s_setpc_b64 s[30:31]5129;5130; GFX9-LABEL: bitcast_v7f64_to_v14f32:5131; GFX9: ; %bb.0:5132; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5133; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v145134; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc5135; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]5136; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]5137; GFX9-NEXT: s_cbranch_execz .LBB26_25138; GFX9-NEXT: ; %bb.1: ; %cmp.true5139; GFX9-NEXT: v_add_f64 v[12:13], v[12:13], 1.05140; GFX9-NEXT: v_add_f64 v[10:11], v[10:11], 1.05141; GFX9-NEXT: v_add_f64 v[8:9], v[8:9], 1.05142; GFX9-NEXT: v_add_f64 v[6:7], v[6:7], 1.05143; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.05144; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.05145; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.05146; GFX9-NEXT: .LBB26_2: ; %end5147; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]5148; GFX9-NEXT: s_setpc_b64 s[30:31]5149;5150; GFX11-LABEL: bitcast_v7f64_to_v14f32:5151; GFX11: ; %bb.0:5152; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5153; GFX11-NEXT: s_mov_b32 s0, exec_lo5154; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v145155; GFX11-NEXT: s_xor_b32 s0, exec_lo, s05156; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)5157; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s05158; GFX11-NEXT: s_cbranch_execz .LBB26_25159; GFX11-NEXT: ; %bb.1: ; %cmp.true5160; GFX11-NEXT: v_add_f64 v[12:13], v[12:13], 1.05161; GFX11-NEXT: v_add_f64 v[10:11], v[10:11], 1.05162; GFX11-NEXT: v_add_f64 v[8:9], v[8:9], 1.05163; GFX11-NEXT: v_add_f64 v[6:7], v[6:7], 1.05164; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.05165; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.05166; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.05167; GFX11-NEXT: .LBB26_2: ; %end5168; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s05169; GFX11-NEXT: s_setpc_b64 s[30:31]5170 %cmp = icmp eq i32 %b, 05171 br i1 %cmp, label %cmp.true, label %cmp.false5172 5173cmp.true:5174 %a1 = fadd <7 x double> %a, splat (double 1.000000e+00)5175 %a2 = bitcast <7 x double> %a1 to <14 x float>5176 br label %end5177 5178cmp.false:5179 %a3 = bitcast <7 x double> %a to <14 x float>5180 br label %end5181 5182end:5183 %phi = phi <14 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]5184 ret <14 x float> %phi5185}5186 5187define inreg <14 x float> @bitcast_v7f64_to_v14f32_scalar(<7 x double> inreg %a, i32 inreg %b) {5188; SI-LABEL: bitcast_v7f64_to_v14f32_scalar:5189; SI: ; %bb.0:5190; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5191; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v05192; SI-NEXT: s_and_b64 s[4:5], vcc, exec5193; SI-NEXT: s_cbranch_scc0 .LBB27_35194; SI-NEXT: ; %bb.1: ; %cmp.false5195; SI-NEXT: s_cbranch_execnz .LBB27_45196; SI-NEXT: .LBB27_2: ; %cmp.true5197; SI-NEXT: v_add_f64 v[12:13], s[28:29], 1.05198; SI-NEXT: v_add_f64 v[10:11], s[26:27], 1.05199; SI-NEXT: v_add_f64 v[8:9], s[24:25], 1.05200; SI-NEXT: v_add_f64 v[6:7], s[22:23], 1.05201; SI-NEXT: v_add_f64 v[4:5], s[20:21], 1.05202; SI-NEXT: v_add_f64 v[2:3], s[18:19], 1.05203; SI-NEXT: v_add_f64 v[0:1], s[16:17], 1.05204; SI-NEXT: s_setpc_b64 s[30:31]5205; SI-NEXT: .LBB27_3:5206; SI-NEXT: s_branch .LBB27_25207; SI-NEXT: .LBB27_4:5208; SI-NEXT: v_mov_b32_e32 v0, s165209; SI-NEXT: v_mov_b32_e32 v1, s175210; SI-NEXT: v_mov_b32_e32 v2, s185211; SI-NEXT: v_mov_b32_e32 v3, s195212; SI-NEXT: v_mov_b32_e32 v4, s205213; SI-NEXT: v_mov_b32_e32 v5, s215214; SI-NEXT: v_mov_b32_e32 v6, s225215; SI-NEXT: v_mov_b32_e32 v7, s235216; SI-NEXT: v_mov_b32_e32 v8, s245217; SI-NEXT: v_mov_b32_e32 v9, s255218; SI-NEXT: v_mov_b32_e32 v10, s265219; SI-NEXT: v_mov_b32_e32 v11, s275220; SI-NEXT: v_mov_b32_e32 v12, s285221; SI-NEXT: v_mov_b32_e32 v13, s295222; SI-NEXT: v_mov_b32_e32 v14, s305223; SI-NEXT: v_mov_b32_e32 v15, s315224; SI-NEXT: s_setpc_b64 s[30:31]5225;5226; VI-LABEL: bitcast_v7f64_to_v14f32_scalar:5227; VI: ; %bb.0:5228; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5229; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v05230; VI-NEXT: s_and_b64 s[4:5], vcc, exec5231; VI-NEXT: s_cbranch_scc0 .LBB27_35232; VI-NEXT: ; %bb.1: ; %cmp.false5233; VI-NEXT: s_cbranch_execnz .LBB27_45234; VI-NEXT: .LBB27_2: ; %cmp.true5235; VI-NEXT: v_add_f64 v[12:13], s[28:29], 1.05236; VI-NEXT: v_add_f64 v[10:11], s[26:27], 1.05237; VI-NEXT: v_add_f64 v[8:9], s[24:25], 1.05238; VI-NEXT: v_add_f64 v[6:7], s[22:23], 1.05239; VI-NEXT: v_add_f64 v[4:5], s[20:21], 1.05240; VI-NEXT: v_add_f64 v[2:3], s[18:19], 1.05241; VI-NEXT: v_add_f64 v[0:1], s[16:17], 1.05242; VI-NEXT: s_setpc_b64 s[30:31]5243; VI-NEXT: .LBB27_3:5244; VI-NEXT: s_branch .LBB27_25245; VI-NEXT: .LBB27_4:5246; VI-NEXT: v_mov_b32_e32 v0, s165247; VI-NEXT: v_mov_b32_e32 v1, s175248; VI-NEXT: v_mov_b32_e32 v2, s185249; VI-NEXT: v_mov_b32_e32 v3, s195250; VI-NEXT: v_mov_b32_e32 v4, s205251; VI-NEXT: v_mov_b32_e32 v5, s215252; VI-NEXT: v_mov_b32_e32 v6, s225253; VI-NEXT: v_mov_b32_e32 v7, s235254; VI-NEXT: v_mov_b32_e32 v8, s245255; VI-NEXT: v_mov_b32_e32 v9, s255256; VI-NEXT: v_mov_b32_e32 v10, s265257; VI-NEXT: v_mov_b32_e32 v11, s275258; VI-NEXT: v_mov_b32_e32 v12, s285259; VI-NEXT: v_mov_b32_e32 v13, s295260; VI-NEXT: v_mov_b32_e32 v14, s305261; VI-NEXT: v_mov_b32_e32 v15, s315262; VI-NEXT: s_setpc_b64 s[30:31]5263;5264; GFX9-LABEL: bitcast_v7f64_to_v14f32_scalar:5265; GFX9: ; %bb.0:5266; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5267; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v05268; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec5269; GFX9-NEXT: s_cbranch_scc0 .LBB27_35270; GFX9-NEXT: ; %bb.1: ; %cmp.false5271; GFX9-NEXT: s_cbranch_execnz .LBB27_45272; GFX9-NEXT: .LBB27_2: ; %cmp.true5273; GFX9-NEXT: v_add_f64 v[12:13], s[28:29], 1.05274; GFX9-NEXT: v_add_f64 v[10:11], s[26:27], 1.05275; GFX9-NEXT: v_add_f64 v[8:9], s[24:25], 1.05276; GFX9-NEXT: v_add_f64 v[6:7], s[22:23], 1.05277; GFX9-NEXT: v_add_f64 v[4:5], s[20:21], 1.05278; GFX9-NEXT: v_add_f64 v[2:3], s[18:19], 1.05279; GFX9-NEXT: v_add_f64 v[0:1], s[16:17], 1.05280; GFX9-NEXT: s_setpc_b64 s[30:31]5281; GFX9-NEXT: .LBB27_3:5282; GFX9-NEXT: s_branch .LBB27_25283; GFX9-NEXT: .LBB27_4:5284; GFX9-NEXT: v_mov_b32_e32 v0, s165285; GFX9-NEXT: v_mov_b32_e32 v1, s175286; GFX9-NEXT: v_mov_b32_e32 v2, s185287; GFX9-NEXT: v_mov_b32_e32 v3, s195288; GFX9-NEXT: v_mov_b32_e32 v4, s205289; GFX9-NEXT: v_mov_b32_e32 v5, s215290; GFX9-NEXT: v_mov_b32_e32 v6, s225291; GFX9-NEXT: v_mov_b32_e32 v7, s235292; GFX9-NEXT: v_mov_b32_e32 v8, s245293; GFX9-NEXT: v_mov_b32_e32 v9, s255294; GFX9-NEXT: v_mov_b32_e32 v10, s265295; GFX9-NEXT: v_mov_b32_e32 v11, s275296; GFX9-NEXT: v_mov_b32_e32 v12, s285297; GFX9-NEXT: v_mov_b32_e32 v13, s295298; GFX9-NEXT: v_mov_b32_e32 v14, s305299; GFX9-NEXT: v_mov_b32_e32 v15, s315300; GFX9-NEXT: s_setpc_b64 s[30:31]5301;5302; GFX11-LABEL: bitcast_v7f64_to_v14f32_scalar:5303; GFX11: ; %bb.0:5304; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5305; GFX11-NEXT: s_mov_b32 s15, s35306; GFX11-NEXT: s_mov_b32 s14, s25307; GFX11-NEXT: s_mov_b32 s13, s15308; GFX11-NEXT: s_mov_b32 s12, s05309; GFX11-NEXT: s_cmp_lg_u32 s26, 05310; GFX11-NEXT: s_mov_b32 s0, 05311; GFX11-NEXT: s_cbranch_scc0 .LBB27_35312; GFX11-NEXT: ; %bb.1: ; %Flow5313; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s05314; GFX11-NEXT: s_cbranch_vccnz .LBB27_45315; GFX11-NEXT: .LBB27_2: ; %cmp.true5316; GFX11-NEXT: v_add_f64 v[12:13], s[24:25], 1.05317; GFX11-NEXT: v_add_f64 v[10:11], s[22:23], 1.05318; GFX11-NEXT: v_add_f64 v[8:9], s[20:21], 1.05319; GFX11-NEXT: v_add_f64 v[6:7], s[18:19], 1.05320; GFX11-NEXT: v_add_f64 v[4:5], s[16:17], 1.05321; GFX11-NEXT: v_add_f64 v[2:3], s[14:15], 1.05322; GFX11-NEXT: v_add_f64 v[0:1], s[12:13], 1.05323; GFX11-NEXT: s_setpc_b64 s[30:31]5324; GFX11-NEXT: .LBB27_3:5325; GFX11-NEXT: s_branch .LBB27_25326; GFX11-NEXT: .LBB27_4:5327; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s135328; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s155329; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s175330; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s195331; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s215332; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s235333; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s255334; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s275335; GFX11-NEXT: s_setpc_b64 s[30:31]5336 %cmp = icmp eq i32 %b, 05337 br i1 %cmp, label %cmp.true, label %cmp.false5338 5339cmp.true:5340 %a1 = fadd <7 x double> %a, splat (double 1.000000e+00)5341 %a2 = bitcast <7 x double> %a1 to <14 x float>5342 br label %end5343 5344cmp.false:5345 %a3 = bitcast <7 x double> %a to <14 x float>5346 br label %end5347 5348end:5349 %phi = phi <14 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]5350 ret <14 x float> %phi5351}5352 5353define <28 x i16> @bitcast_v14f32_to_v28i16(<14 x float> %a, i32 %b) {5354; SI-LABEL: bitcast_v14f32_to_v28i16:5355; SI: ; %bb.0:5356; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5357; SI-NEXT: v_mov_b32_e32 v26, v135358; SI-NEXT: v_mov_b32_e32 v24, v125359; SI-NEXT: v_mov_b32_e32 v22, v115360; SI-NEXT: v_mov_b32_e32 v20, v105361; SI-NEXT: v_mov_b32_e32 v18, v95362; SI-NEXT: v_mov_b32_e32 v16, v85363; SI-NEXT: v_mov_b32_e32 v28, v75364; SI-NEXT: v_mov_b32_e32 v12, v65365; SI-NEXT: v_mov_b32_e32 v10, v55366; SI-NEXT: v_mov_b32_e32 v8, v45367; SI-NEXT: v_mov_b32_e32 v6, v35368; SI-NEXT: v_mov_b32_e32 v4, v25369; SI-NEXT: v_mov_b32_e32 v2, v15370; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v145371; SI-NEXT: ; implicit-def: $vgpr15372; SI-NEXT: ; implicit-def: $vgpr35373; SI-NEXT: ; implicit-def: $vgpr55374; SI-NEXT: ; implicit-def: $vgpr75375; SI-NEXT: ; implicit-def: $vgpr95376; SI-NEXT: ; implicit-def: $vgpr115377; SI-NEXT: ; implicit-def: $vgpr135378; SI-NEXT: ; implicit-def: $vgpr155379; SI-NEXT: ; implicit-def: $vgpr175380; SI-NEXT: ; implicit-def: $vgpr195381; SI-NEXT: ; implicit-def: $vgpr215382; SI-NEXT: ; implicit-def: $vgpr235383; SI-NEXT: ; implicit-def: $vgpr255384; SI-NEXT: ; implicit-def: $vgpr275385; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc5386; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]5387; SI-NEXT: s_cbranch_execz .LBB28_25388; SI-NEXT: ; %bb.1: ; %cmp.false5389; SI-NEXT: v_alignbit_b32 v25, v26, v24, 165390; SI-NEXT: v_alignbit_b32 v21, v22, v20, 165391; SI-NEXT: v_alignbit_b32 v17, v18, v16, 165392; SI-NEXT: v_alignbit_b32 v13, v28, v12, 165393; SI-NEXT: v_alignbit_b32 v9, v10, v8, 165394; SI-NEXT: v_alignbit_b32 v5, v6, v4, 165395; SI-NEXT: v_alignbit_b32 v1, v2, v0, 165396; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v265397; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v225398; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v185399; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v285400; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v105401; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v65402; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v25403; SI-NEXT: .LBB28_2: ; %Flow5404; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]5405; SI-NEXT: s_cbranch_execz .LBB28_45406; SI-NEXT: ; %bb.3: ; %cmp.true5407; SI-NEXT: v_add_f32_e32 v2, 1.0, v25408; SI-NEXT: v_add_f32_e32 v0, 1.0, v05409; SI-NEXT: v_add_f32_e32 v6, 1.0, v65410; SI-NEXT: v_add_f32_e32 v4, 1.0, v45411; SI-NEXT: v_add_f32_e32 v10, 1.0, v105412; SI-NEXT: v_add_f32_e32 v8, 1.0, v85413; SI-NEXT: v_add_f32_e32 v28, 1.0, v285414; SI-NEXT: v_add_f32_e32 v12, 1.0, v125415; SI-NEXT: v_add_f32_e32 v18, 1.0, v185416; SI-NEXT: v_add_f32_e32 v16, 1.0, v165417; SI-NEXT: v_add_f32_e32 v22, 1.0, v225418; SI-NEXT: v_add_f32_e32 v20, 1.0, v205419; SI-NEXT: v_add_f32_e32 v26, 1.0, v265420; SI-NEXT: v_add_f32_e32 v24, 1.0, v245421; SI-NEXT: v_alignbit_b32 v25, v26, v24, 165422; SI-NEXT: v_alignbit_b32 v21, v22, v20, 165423; SI-NEXT: v_alignbit_b32 v17, v18, v16, 165424; SI-NEXT: v_alignbit_b32 v13, v28, v12, 165425; SI-NEXT: v_alignbit_b32 v9, v10, v8, 165426; SI-NEXT: v_alignbit_b32 v5, v6, v4, 165427; SI-NEXT: v_alignbit_b32 v1, v2, v0, 165428; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v265429; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v225430; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v185431; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v285432; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v105433; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v65434; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v25435; SI-NEXT: .LBB28_4: ; %end5436; SI-NEXT: s_or_b64 exec, exec, s[4:5]5437; SI-NEXT: v_mov_b32_e32 v14, v285438; SI-NEXT: s_setpc_b64 s[30:31]5439;5440; VI-LABEL: bitcast_v14f32_to_v28i16:5441; VI: ; %bb.0:5442; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5443; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v145444; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc5445; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]5446; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]5447; VI-NEXT: s_cbranch_execz .LBB28_25448; VI-NEXT: ; %bb.1: ; %cmp.true5449; VI-NEXT: v_add_f32_e32 v13, 1.0, v135450; VI-NEXT: v_add_f32_e32 v12, 1.0, v125451; VI-NEXT: v_add_f32_e32 v11, 1.0, v115452; VI-NEXT: v_add_f32_e32 v10, 1.0, v105453; VI-NEXT: v_add_f32_e32 v9, 1.0, v95454; VI-NEXT: v_add_f32_e32 v8, 1.0, v85455; VI-NEXT: v_add_f32_e32 v7, 1.0, v75456; VI-NEXT: v_add_f32_e32 v6, 1.0, v65457; VI-NEXT: v_add_f32_e32 v5, 1.0, v55458; VI-NEXT: v_add_f32_e32 v4, 1.0, v45459; VI-NEXT: v_add_f32_e32 v3, 1.0, v35460; VI-NEXT: v_add_f32_e32 v2, 1.0, v25461; VI-NEXT: v_add_f32_e32 v1, 1.0, v15462; VI-NEXT: v_add_f32_e32 v0, 1.0, v05463; VI-NEXT: .LBB28_2: ; %end5464; VI-NEXT: s_or_b64 exec, exec, s[4:5]5465; VI-NEXT: s_setpc_b64 s[30:31]5466;5467; GFX9-LABEL: bitcast_v14f32_to_v28i16:5468; GFX9: ; %bb.0:5469; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5470; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v145471; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc5472; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]5473; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]5474; GFX9-NEXT: s_cbranch_execz .LBB28_25475; GFX9-NEXT: ; %bb.1: ; %cmp.true5476; GFX9-NEXT: v_add_f32_e32 v13, 1.0, v135477; GFX9-NEXT: v_add_f32_e32 v12, 1.0, v125478; GFX9-NEXT: v_add_f32_e32 v11, 1.0, v115479; GFX9-NEXT: v_add_f32_e32 v10, 1.0, v105480; GFX9-NEXT: v_add_f32_e32 v9, 1.0, v95481; GFX9-NEXT: v_add_f32_e32 v8, 1.0, v85482; GFX9-NEXT: v_add_f32_e32 v7, 1.0, v75483; GFX9-NEXT: v_add_f32_e32 v6, 1.0, v65484; GFX9-NEXT: v_add_f32_e32 v5, 1.0, v55485; GFX9-NEXT: v_add_f32_e32 v4, 1.0, v45486; GFX9-NEXT: v_add_f32_e32 v3, 1.0, v35487; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v25488; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v15489; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v05490; GFX9-NEXT: .LBB28_2: ; %end5491; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]5492; GFX9-NEXT: s_setpc_b64 s[30:31]5493;5494; GFX11-LABEL: bitcast_v14f32_to_v28i16:5495; GFX11: ; %bb.0:5496; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5497; GFX11-NEXT: s_mov_b32 s0, exec_lo5498; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v145499; GFX11-NEXT: s_xor_b32 s0, exec_lo, s05500; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)5501; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s05502; GFX11-NEXT: s_cbranch_execz .LBB28_25503; GFX11-NEXT: ; %bb.1: ; %cmp.true5504; GFX11-NEXT: v_dual_add_f32 v13, 1.0, v13 :: v_dual_add_f32 v12, 1.0, v125505; GFX11-NEXT: v_dual_add_f32 v11, 1.0, v11 :: v_dual_add_f32 v10, 1.0, v105506; GFX11-NEXT: v_dual_add_f32 v9, 1.0, v9 :: v_dual_add_f32 v8, 1.0, v85507; GFX11-NEXT: v_dual_add_f32 v7, 1.0, v7 :: v_dual_add_f32 v6, 1.0, v65508; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v45509; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v25510; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v05511; GFX11-NEXT: .LBB28_2: ; %end5512; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s05513; GFX11-NEXT: s_setpc_b64 s[30:31]5514 %cmp = icmp eq i32 %b, 05515 br i1 %cmp, label %cmp.true, label %cmp.false5516 5517cmp.true:5518 %a1 = fadd <14 x float> %a, splat (float 1.000000e+00)5519 %a2 = bitcast <14 x float> %a1 to <28 x i16>5520 br label %end5521 5522cmp.false:5523 %a3 = bitcast <14 x float> %a to <28 x i16>5524 br label %end5525 5526end:5527 %phi = phi <28 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]5528 ret <28 x i16> %phi5529}5530 5531define inreg <28 x i16> @bitcast_v14f32_to_v28i16_scalar(<14 x float> inreg %a, i32 inreg %b) {5532; SI-LABEL: bitcast_v14f32_to_v28i16_scalar:5533; SI: ; %bb.0:5534; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5535; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v05536; SI-NEXT: s_and_b64 s[4:5], vcc, exec5537; SI-NEXT: s_cbranch_scc0 .LBB29_35538; SI-NEXT: ; %bb.1: ; %cmp.false5539; SI-NEXT: s_lshr_b32 s58, s29, 165540; SI-NEXT: s_lshr_b32 s57, s27, 165541; SI-NEXT: s_lshr_b32 s56, s25, 165542; SI-NEXT: s_lshr_b32 s47, s23, 165543; SI-NEXT: s_lshr_b32 s46, s21, 165544; SI-NEXT: s_lshr_b32 s45, s19, 165545; SI-NEXT: s_lshr_b32 s44, s17, 165546; SI-NEXT: s_lshr_b64 s[4:5], s[28:29], 165547; SI-NEXT: s_lshr_b64 s[6:7], s[26:27], 165548; SI-NEXT: s_lshr_b64 s[8:9], s[24:25], 165549; SI-NEXT: s_lshr_b64 s[10:11], s[22:23], 165550; SI-NEXT: s_lshr_b64 s[12:13], s[20:21], 165551; SI-NEXT: s_lshr_b64 s[14:15], s[18:19], 165552; SI-NEXT: s_lshr_b64 s[40:41], s[16:17], 165553; SI-NEXT: s_cbranch_execnz .LBB29_45554; SI-NEXT: .LBB29_2: ; %cmp.true5555; SI-NEXT: v_add_f32_e64 v49, s17, 1.05556; SI-NEXT: v_add_f32_e64 v48, s16, 1.05557; SI-NEXT: v_add_f32_e64 v39, s19, 1.05558; SI-NEXT: v_add_f32_e64 v38, s18, 1.05559; SI-NEXT: v_add_f32_e64 v37, s21, 1.05560; SI-NEXT: v_add_f32_e64 v36, s20, 1.05561; SI-NEXT: v_add_f32_e64 v35, s23, 1.05562; SI-NEXT: v_add_f32_e64 v34, s22, 1.05563; SI-NEXT: v_add_f32_e64 v33, s25, 1.05564; SI-NEXT: v_add_f32_e64 v32, s24, 1.05565; SI-NEXT: v_add_f32_e64 v31, s27, 1.05566; SI-NEXT: v_add_f32_e64 v30, s26, 1.05567; SI-NEXT: v_add_f32_e64 v29, s29, 1.05568; SI-NEXT: v_add_f32_e64 v28, s28, 1.05569; SI-NEXT: v_lshr_b64 v[25:26], v[28:29], 165570; SI-NEXT: v_lshr_b64 v[21:22], v[30:31], 165571; SI-NEXT: v_lshr_b64 v[17:18], v[32:33], 165572; SI-NEXT: v_lshr_b64 v[13:14], v[34:35], 165573; SI-NEXT: v_lshr_b64 v[9:10], v[36:37], 165574; SI-NEXT: v_lshr_b64 v[5:6], v[38:39], 165575; SI-NEXT: v_lshr_b64 v[1:2], v[48:49], 165576; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v295577; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v315578; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v335579; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v355580; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v375581; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v395582; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v495583; SI-NEXT: s_branch .LBB29_55584; SI-NEXT: .LBB29_3:5585; SI-NEXT: ; implicit-def: $sgpr405586; SI-NEXT: ; implicit-def: $sgpr445587; SI-NEXT: ; implicit-def: $sgpr145588; SI-NEXT: ; implicit-def: $sgpr455589; SI-NEXT: ; implicit-def: $sgpr125590; SI-NEXT: ; implicit-def: $sgpr465591; SI-NEXT: ; implicit-def: $sgpr105592; SI-NEXT: ; implicit-def: $sgpr475593; SI-NEXT: ; implicit-def: $sgpr85594; SI-NEXT: ; implicit-def: $sgpr565595; SI-NEXT: ; implicit-def: $sgpr65596; SI-NEXT: ; implicit-def: $sgpr575597; SI-NEXT: ; implicit-def: $sgpr45598; SI-NEXT: ; implicit-def: $sgpr585599; SI-NEXT: s_branch .LBB29_25600; SI-NEXT: .LBB29_4:5601; SI-NEXT: v_mov_b32_e32 v48, s165602; SI-NEXT: v_mov_b32_e32 v49, s175603; SI-NEXT: v_mov_b32_e32 v38, s185604; SI-NEXT: v_mov_b32_e32 v39, s195605; SI-NEXT: v_mov_b32_e32 v36, s205606; SI-NEXT: v_mov_b32_e32 v37, s215607; SI-NEXT: v_mov_b32_e32 v34, s225608; SI-NEXT: v_mov_b32_e32 v35, s235609; SI-NEXT: v_mov_b32_e32 v32, s245610; SI-NEXT: v_mov_b32_e32 v33, s255611; SI-NEXT: v_mov_b32_e32 v30, s265612; SI-NEXT: v_mov_b32_e32 v31, s275613; SI-NEXT: v_mov_b32_e32 v28, s285614; SI-NEXT: v_mov_b32_e32 v29, s295615; SI-NEXT: v_mov_b32_e32 v3, s445616; SI-NEXT: v_mov_b32_e32 v7, s455617; SI-NEXT: v_mov_b32_e32 v11, s465618; SI-NEXT: v_mov_b32_e32 v15, s475619; SI-NEXT: v_mov_b32_e32 v19, s565620; SI-NEXT: v_mov_b32_e32 v23, s575621; SI-NEXT: v_mov_b32_e32 v27, s585622; SI-NEXT: v_mov_b32_e32 v25, s45623; SI-NEXT: v_mov_b32_e32 v21, s65624; SI-NEXT: v_mov_b32_e32 v17, s85625; SI-NEXT: v_mov_b32_e32 v13, s105626; SI-NEXT: v_mov_b32_e32 v9, s125627; SI-NEXT: v_mov_b32_e32 v5, s145628; SI-NEXT: v_mov_b32_e32 v1, s405629; SI-NEXT: .LBB29_5: ; %end5630; SI-NEXT: v_mov_b32_e32 v0, v485631; SI-NEXT: v_mov_b32_e32 v2, v495632; SI-NEXT: v_mov_b32_e32 v4, v385633; SI-NEXT: v_mov_b32_e32 v6, v395634; SI-NEXT: v_mov_b32_e32 v8, v365635; SI-NEXT: v_mov_b32_e32 v10, v375636; SI-NEXT: v_mov_b32_e32 v12, v345637; SI-NEXT: v_mov_b32_e32 v14, v355638; SI-NEXT: v_mov_b32_e32 v16, v325639; SI-NEXT: v_mov_b32_e32 v18, v335640; SI-NEXT: v_mov_b32_e32 v20, v305641; SI-NEXT: v_mov_b32_e32 v22, v315642; SI-NEXT: v_mov_b32_e32 v24, v285643; SI-NEXT: v_mov_b32_e32 v26, v295644; SI-NEXT: s_setpc_b64 s[30:31]5645;5646; VI-LABEL: bitcast_v14f32_to_v28i16_scalar:5647; VI: ; %bb.0:5648; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5649; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v05650; VI-NEXT: s_and_b64 s[4:5], vcc, exec5651; VI-NEXT: s_cbranch_scc0 .LBB29_35652; VI-NEXT: ; %bb.1: ; %cmp.false5653; VI-NEXT: s_cbranch_execnz .LBB29_45654; VI-NEXT: .LBB29_2: ; %cmp.true5655; VI-NEXT: v_add_f32_e64 v13, s29, 1.05656; VI-NEXT: v_add_f32_e64 v12, s28, 1.05657; VI-NEXT: v_add_f32_e64 v11, s27, 1.05658; VI-NEXT: v_add_f32_e64 v10, s26, 1.05659; VI-NEXT: v_add_f32_e64 v9, s25, 1.05660; VI-NEXT: v_add_f32_e64 v8, s24, 1.05661; VI-NEXT: v_add_f32_e64 v7, s23, 1.05662; VI-NEXT: v_add_f32_e64 v6, s22, 1.05663; VI-NEXT: v_add_f32_e64 v5, s21, 1.05664; VI-NEXT: v_add_f32_e64 v4, s20, 1.05665; VI-NEXT: v_add_f32_e64 v3, s19, 1.05666; VI-NEXT: v_add_f32_e64 v2, s18, 1.05667; VI-NEXT: v_add_f32_e64 v1, s17, 1.05668; VI-NEXT: v_add_f32_e64 v0, s16, 1.05669; VI-NEXT: s_setpc_b64 s[30:31]5670; VI-NEXT: .LBB29_3:5671; VI-NEXT: s_branch .LBB29_25672; VI-NEXT: .LBB29_4:5673; VI-NEXT: v_mov_b32_e32 v0, s165674; VI-NEXT: v_mov_b32_e32 v1, s175675; VI-NEXT: v_mov_b32_e32 v2, s185676; VI-NEXT: v_mov_b32_e32 v3, s195677; VI-NEXT: v_mov_b32_e32 v4, s205678; VI-NEXT: v_mov_b32_e32 v5, s215679; VI-NEXT: v_mov_b32_e32 v6, s225680; VI-NEXT: v_mov_b32_e32 v7, s235681; VI-NEXT: v_mov_b32_e32 v8, s245682; VI-NEXT: v_mov_b32_e32 v9, s255683; VI-NEXT: v_mov_b32_e32 v10, s265684; VI-NEXT: v_mov_b32_e32 v11, s275685; VI-NEXT: v_mov_b32_e32 v12, s285686; VI-NEXT: v_mov_b32_e32 v13, s295687; VI-NEXT: v_mov_b32_e32 v14, s305688; VI-NEXT: v_mov_b32_e32 v15, s315689; VI-NEXT: s_setpc_b64 s[30:31]5690;5691; GFX9-LABEL: bitcast_v14f32_to_v28i16_scalar:5692; GFX9: ; %bb.0:5693; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5694; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v05695; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec5696; GFX9-NEXT: s_cbranch_scc0 .LBB29_35697; GFX9-NEXT: ; %bb.1: ; %cmp.false5698; GFX9-NEXT: s_cbranch_execnz .LBB29_45699; GFX9-NEXT: .LBB29_2: ; %cmp.true5700; GFX9-NEXT: v_add_f32_e64 v13, s29, 1.05701; GFX9-NEXT: v_add_f32_e64 v12, s28, 1.05702; GFX9-NEXT: v_add_f32_e64 v11, s27, 1.05703; GFX9-NEXT: v_add_f32_e64 v10, s26, 1.05704; GFX9-NEXT: v_add_f32_e64 v9, s25, 1.05705; GFX9-NEXT: v_add_f32_e64 v8, s24, 1.05706; GFX9-NEXT: v_add_f32_e64 v7, s23, 1.05707; GFX9-NEXT: v_add_f32_e64 v6, s22, 1.05708; GFX9-NEXT: v_add_f32_e64 v5, s21, 1.05709; GFX9-NEXT: v_add_f32_e64 v4, s20, 1.05710; GFX9-NEXT: v_add_f32_e64 v3, s19, 1.05711; GFX9-NEXT: v_add_f32_e64 v2, s18, 1.05712; GFX9-NEXT: v_add_f32_e64 v1, s17, 1.05713; GFX9-NEXT: v_add_f32_e64 v0, s16, 1.05714; GFX9-NEXT: s_setpc_b64 s[30:31]5715; GFX9-NEXT: .LBB29_3:5716; GFX9-NEXT: s_branch .LBB29_25717; GFX9-NEXT: .LBB29_4:5718; GFX9-NEXT: v_mov_b32_e32 v0, s165719; GFX9-NEXT: v_mov_b32_e32 v1, s175720; GFX9-NEXT: v_mov_b32_e32 v2, s185721; GFX9-NEXT: v_mov_b32_e32 v3, s195722; GFX9-NEXT: v_mov_b32_e32 v4, s205723; GFX9-NEXT: v_mov_b32_e32 v5, s215724; GFX9-NEXT: v_mov_b32_e32 v6, s225725; GFX9-NEXT: v_mov_b32_e32 v7, s235726; GFX9-NEXT: v_mov_b32_e32 v8, s245727; GFX9-NEXT: v_mov_b32_e32 v9, s255728; GFX9-NEXT: v_mov_b32_e32 v10, s265729; GFX9-NEXT: v_mov_b32_e32 v11, s275730; GFX9-NEXT: v_mov_b32_e32 v12, s285731; GFX9-NEXT: v_mov_b32_e32 v13, s295732; GFX9-NEXT: v_mov_b32_e32 v14, s305733; GFX9-NEXT: v_mov_b32_e32 v15, s315734; GFX9-NEXT: s_setpc_b64 s[30:31]5735;5736; GFX11-LABEL: bitcast_v14f32_to_v28i16_scalar:5737; GFX11: ; %bb.0:5738; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5739; GFX11-NEXT: s_mov_b32 s15, s35740; GFX11-NEXT: s_mov_b32 s14, s25741; GFX11-NEXT: s_mov_b32 s13, s15742; GFX11-NEXT: s_mov_b32 s12, s05743; GFX11-NEXT: s_cmp_lg_u32 s26, 05744; GFX11-NEXT: s_mov_b32 s0, 05745; GFX11-NEXT: s_cbranch_scc0 .LBB29_35746; GFX11-NEXT: ; %bb.1: ; %Flow5747; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s05748; GFX11-NEXT: s_cbranch_vccnz .LBB29_45749; GFX11-NEXT: .LBB29_2: ; %cmp.true5750; GFX11-NEXT: v_add_f32_e64 v13, s25, 1.05751; GFX11-NEXT: v_add_f32_e64 v12, s24, 1.05752; GFX11-NEXT: v_add_f32_e64 v11, s23, 1.05753; GFX11-NEXT: v_add_f32_e64 v10, s22, 1.05754; GFX11-NEXT: v_add_f32_e64 v9, s21, 1.05755; GFX11-NEXT: v_add_f32_e64 v8, s20, 1.05756; GFX11-NEXT: v_add_f32_e64 v7, s19, 1.05757; GFX11-NEXT: v_add_f32_e64 v6, s18, 1.05758; GFX11-NEXT: v_add_f32_e64 v5, s17, 1.05759; GFX11-NEXT: v_add_f32_e64 v4, s16, 1.05760; GFX11-NEXT: v_add_f32_e64 v3, s15, 1.05761; GFX11-NEXT: v_add_f32_e64 v2, s14, 1.05762; GFX11-NEXT: v_add_f32_e64 v1, s13, 1.05763; GFX11-NEXT: v_add_f32_e64 v0, s12, 1.05764; GFX11-NEXT: s_setpc_b64 s[30:31]5765; GFX11-NEXT: .LBB29_3:5766; GFX11-NEXT: s_branch .LBB29_25767; GFX11-NEXT: .LBB29_4:5768; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s135769; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s155770; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s175771; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s195772; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s215773; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s235774; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s255775; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s275776; GFX11-NEXT: s_setpc_b64 s[30:31]5777 %cmp = icmp eq i32 %b, 05778 br i1 %cmp, label %cmp.true, label %cmp.false5779 5780cmp.true:5781 %a1 = fadd <14 x float> %a, splat (float 1.000000e+00)5782 %a2 = bitcast <14 x float> %a1 to <28 x i16>5783 br label %end5784 5785cmp.false:5786 %a3 = bitcast <14 x float> %a to <28 x i16>5787 br label %end5788 5789end:5790 %phi = phi <28 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]5791 ret <28 x i16> %phi5792}5793 5794define <14 x float> @bitcast_v28i16_to_v14f32(<28 x i16> %a, i32 %b) {5795; SI-LABEL: bitcast_v28i16_to_v14f32:5796; SI: ; %bb.0:5797; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5798; SI-NEXT: v_mov_b32_e32 v36, v145799; SI-NEXT: v_mov_b32_e32 v35, v125800; SI-NEXT: v_mov_b32_e32 v34, v105801; SI-NEXT: v_mov_b32_e32 v33, v85802; SI-NEXT: v_mov_b32_e32 v32, v65803; SI-NEXT: v_mov_b32_e32 v31, v45804; SI-NEXT: v_mov_b32_e32 v30, v25805; SI-NEXT: v_mov_b32_e32 v29, v05806; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v285807; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v15808; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v35809; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v55810; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v75811; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v95812; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v115813; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v135814; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v155815; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v175816; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v195817; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v215818; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v235819; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v255820; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v275821; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr155822; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc5823; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]5824; SI-NEXT: s_cbranch_execnz .LBB30_35825; SI-NEXT: ; %bb.1: ; %Flow5826; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]5827; SI-NEXT: s_cbranch_execnz .LBB30_45828; SI-NEXT: .LBB30_2: ; %end5829; SI-NEXT: s_or_b64 exec, exec, s[4:5]5830; SI-NEXT: s_setpc_b64 s[30:31]5831; SI-NEXT: .LBB30_3: ; %cmp.false5832; SI-NEXT: v_and_b32_e32 v0, 0xffff, v295833; SI-NEXT: v_and_b32_e32 v1, 0xffff, v305834; SI-NEXT: v_and_b32_e32 v2, 0xffff, v315835; SI-NEXT: v_and_b32_e32 v3, 0xffff, v325836; SI-NEXT: v_and_b32_e32 v4, 0xffff, v335837; SI-NEXT: v_and_b32_e32 v5, 0xffff, v345838; SI-NEXT: v_and_b32_e32 v6, 0xffff, v355839; SI-NEXT: v_and_b32_e32 v7, 0xffff, v365840; SI-NEXT: v_and_b32_e32 v8, 0xffff, v165841; SI-NEXT: v_and_b32_e32 v9, 0xffff, v185842; SI-NEXT: v_and_b32_e32 v10, 0xffff, v205843; SI-NEXT: v_and_b32_e32 v11, 0xffff, v225844; SI-NEXT: v_and_b32_e32 v12, 0xffff, v245845; SI-NEXT: v_and_b32_e32 v13, 0xffff, v265846; SI-NEXT: v_or_b32_e32 v0, v0, v545847; SI-NEXT: v_or_b32_e32 v1, v1, v535848; SI-NEXT: v_or_b32_e32 v2, v2, v525849; SI-NEXT: v_or_b32_e32 v3, v3, v515850; SI-NEXT: v_or_b32_e32 v4, v4, v505851; SI-NEXT: v_or_b32_e32 v5, v5, v495852; SI-NEXT: v_or_b32_e32 v6, v6, v485853; SI-NEXT: v_or_b32_e32 v7, v7, v395854; SI-NEXT: v_or_b32_e32 v8, v8, v385855; SI-NEXT: v_or_b32_e32 v9, v9, v375856; SI-NEXT: v_or_b32_e32 v10, v10, v285857; SI-NEXT: v_or_b32_e32 v11, v11, v215858; SI-NEXT: v_or_b32_e32 v12, v12, v195859; SI-NEXT: v_or_b32_e32 v13, v13, v175860; SI-NEXT: ; implicit-def: $vgpr295861; SI-NEXT: ; implicit-def: $vgpr305862; SI-NEXT: ; implicit-def: $vgpr315863; SI-NEXT: ; implicit-def: $vgpr325864; SI-NEXT: ; implicit-def: $vgpr335865; SI-NEXT: ; implicit-def: $vgpr345866; SI-NEXT: ; implicit-def: $vgpr355867; SI-NEXT: ; implicit-def: $vgpr365868; SI-NEXT: ; implicit-def: $vgpr165869; SI-NEXT: ; implicit-def: $vgpr185870; SI-NEXT: ; implicit-def: $vgpr205871; SI-NEXT: ; implicit-def: $vgpr225872; SI-NEXT: ; implicit-def: $vgpr245873; SI-NEXT: ; implicit-def: $vgpr265874; SI-NEXT: ; implicit-def: $vgpr545875; SI-NEXT: ; implicit-def: $vgpr535876; SI-NEXT: ; implicit-def: $vgpr525877; SI-NEXT: ; implicit-def: $vgpr515878; SI-NEXT: ; implicit-def: $vgpr505879; SI-NEXT: ; implicit-def: $vgpr495880; SI-NEXT: ; implicit-def: $vgpr485881; SI-NEXT: ; implicit-def: $vgpr395882; SI-NEXT: ; implicit-def: $vgpr385883; SI-NEXT: ; implicit-def: $vgpr375884; SI-NEXT: ; implicit-def: $vgpr285885; SI-NEXT: ; implicit-def: $vgpr215886; SI-NEXT: ; implicit-def: $vgpr195887; SI-NEXT: ; implicit-def: $vgpr175888; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]5889; SI-NEXT: s_cbranch_execz .LBB30_25890; SI-NEXT: .LBB30_4: ; %cmp.true5891; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v295892; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v305893; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v315894; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v325895; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v335896; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v345897; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v355898; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v365899; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v165900; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v185901; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v205902; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v225903; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v245904; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v265905; SI-NEXT: v_and_b32_e32 v0, 0xffff, v05906; SI-NEXT: v_and_b32_e32 v1, 0xffff, v15907; SI-NEXT: v_and_b32_e32 v2, 0xffff, v25908; SI-NEXT: v_and_b32_e32 v3, 0xffff, v35909; SI-NEXT: v_and_b32_e32 v4, 0xffff, v45910; SI-NEXT: v_and_b32_e32 v5, 0xffff, v55911; SI-NEXT: v_and_b32_e32 v6, 0xffff, v65912; SI-NEXT: v_and_b32_e32 v7, 0xffff, v75913; SI-NEXT: v_and_b32_e32 v8, 0xffff, v85914; SI-NEXT: v_and_b32_e32 v9, 0xffff, v95915; SI-NEXT: v_and_b32_e32 v10, 0xffff, v105916; SI-NEXT: v_and_b32_e32 v11, 0xffff, v115917; SI-NEXT: v_and_b32_e32 v12, 0xffff, v125918; SI-NEXT: v_and_b32_e32 v13, 0xffff, v135919; SI-NEXT: v_or_b32_e32 v0, v54, v05920; SI-NEXT: s_mov_b32 s6, 0x300005921; SI-NEXT: v_or_b32_e32 v1, v53, v15922; SI-NEXT: v_or_b32_e32 v2, v52, v25923; SI-NEXT: v_or_b32_e32 v3, v51, v35924; SI-NEXT: v_or_b32_e32 v4, v50, v45925; SI-NEXT: v_or_b32_e32 v5, v49, v55926; SI-NEXT: v_or_b32_e32 v6, v48, v65927; SI-NEXT: v_or_b32_e32 v7, v39, v75928; SI-NEXT: v_or_b32_e32 v8, v38, v85929; SI-NEXT: v_or_b32_e32 v9, v37, v95930; SI-NEXT: v_or_b32_e32 v10, v28, v105931; SI-NEXT: v_or_b32_e32 v11, v21, v115932; SI-NEXT: v_or_b32_e32 v12, v19, v125933; SI-NEXT: v_or_b32_e32 v13, v17, v135934; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v05935; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v15936; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v25937; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v35938; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v45939; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v55940; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v65941; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v75942; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v85943; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v95944; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v105945; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v115946; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v125947; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v135948; SI-NEXT: s_or_b64 exec, exec, s[4:5]5949; SI-NEXT: s_setpc_b64 s[30:31]5950;5951; VI-LABEL: bitcast_v28i16_to_v14f32:5952; VI: ; %bb.0:5953; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5954; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v145955; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc5956; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]5957; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]5958; VI-NEXT: s_cbranch_execz .LBB30_25959; VI-NEXT: ; %bb.1: ; %cmp.true5960; VI-NEXT: v_mov_b32_e32 v15, 35961; VI-NEXT: v_add_u16_e32 v14, 3, v135962; VI-NEXT: v_add_u16_sdwa v13, v13, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD5963; VI-NEXT: v_or_b32_e32 v13, v14, v135964; VI-NEXT: v_add_u16_e32 v14, 3, v125965; VI-NEXT: v_add_u16_sdwa v12, v12, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD5966; VI-NEXT: v_or_b32_e32 v12, v14, v125967; VI-NEXT: v_add_u16_e32 v14, 3, v115968; VI-NEXT: v_add_u16_sdwa v11, v11, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD5969; VI-NEXT: v_or_b32_e32 v11, v14, v115970; VI-NEXT: v_add_u16_e32 v14, 3, v105971; VI-NEXT: v_add_u16_sdwa v10, v10, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD5972; VI-NEXT: v_or_b32_e32 v10, v14, v105973; VI-NEXT: v_add_u16_e32 v14, 3, v95974; VI-NEXT: v_add_u16_sdwa v9, v9, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD5975; VI-NEXT: v_or_b32_e32 v9, v14, v95976; VI-NEXT: v_add_u16_e32 v14, 3, v85977; VI-NEXT: v_add_u16_sdwa v8, v8, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD5978; VI-NEXT: v_or_b32_e32 v8, v14, v85979; VI-NEXT: v_add_u16_e32 v14, 3, v75980; VI-NEXT: v_add_u16_sdwa v7, v7, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD5981; VI-NEXT: v_or_b32_e32 v7, v14, v75982; VI-NEXT: v_add_u16_e32 v14, 3, v65983; VI-NEXT: v_add_u16_sdwa v6, v6, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD5984; VI-NEXT: v_or_b32_e32 v6, v14, v65985; VI-NEXT: v_add_u16_e32 v14, 3, v55986; VI-NEXT: v_add_u16_sdwa v5, v5, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD5987; VI-NEXT: v_or_b32_e32 v5, v14, v55988; VI-NEXT: v_add_u16_e32 v14, 3, v45989; VI-NEXT: v_add_u16_sdwa v4, v4, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD5990; VI-NEXT: v_or_b32_e32 v4, v14, v45991; VI-NEXT: v_add_u16_e32 v14, 3, v35992; VI-NEXT: v_add_u16_sdwa v3, v3, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD5993; VI-NEXT: v_or_b32_e32 v3, v14, v35994; VI-NEXT: v_add_u16_e32 v14, 3, v25995; VI-NEXT: v_add_u16_sdwa v2, v2, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD5996; VI-NEXT: v_or_b32_e32 v2, v14, v25997; VI-NEXT: v_add_u16_e32 v14, 3, v15998; VI-NEXT: v_add_u16_sdwa v1, v1, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD5999; VI-NEXT: v_or_b32_e32 v1, v14, v16000; VI-NEXT: v_add_u16_e32 v14, 3, v06001; VI-NEXT: v_add_u16_sdwa v0, v0, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD6002; VI-NEXT: v_or_b32_e32 v0, v14, v06003; VI-NEXT: .LBB30_2: ; %end6004; VI-NEXT: s_or_b64 exec, exec, s[4:5]6005; VI-NEXT: s_setpc_b64 s[30:31]6006;6007; GFX9-LABEL: bitcast_v28i16_to_v14f32:6008; GFX9: ; %bb.0:6009; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6010; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v146011; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc6012; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]6013; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]6014; GFX9-NEXT: s_cbranch_execz .LBB30_26015; GFX9-NEXT: ; %bb.1: ; %cmp.true6016; GFX9-NEXT: v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0]6017; GFX9-NEXT: v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0]6018; GFX9-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]6019; GFX9-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]6020; GFX9-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]6021; GFX9-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]6022; GFX9-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]6023; GFX9-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]6024; GFX9-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]6025; GFX9-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]6026; GFX9-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]6027; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]6028; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]6029; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]6030; GFX9-NEXT: .LBB30_2: ; %end6031; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]6032; GFX9-NEXT: s_setpc_b64 s[30:31]6033;6034; GFX11-LABEL: bitcast_v28i16_to_v14f32:6035; GFX11: ; %bb.0:6036; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6037; GFX11-NEXT: s_mov_b32 s0, exec_lo6038; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v146039; GFX11-NEXT: s_xor_b32 s0, exec_lo, s06040; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)6041; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s06042; GFX11-NEXT: s_cbranch_execz .LBB30_26043; GFX11-NEXT: ; %bb.1: ; %cmp.true6044; GFX11-NEXT: v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0]6045; GFX11-NEXT: v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0]6046; GFX11-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]6047; GFX11-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]6048; GFX11-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]6049; GFX11-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]6050; GFX11-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]6051; GFX11-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]6052; GFX11-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]6053; GFX11-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]6054; GFX11-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]6055; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]6056; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]6057; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]6058; GFX11-NEXT: .LBB30_2: ; %end6059; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s06060; GFX11-NEXT: s_setpc_b64 s[30:31]6061 %cmp = icmp eq i32 %b, 06062 br i1 %cmp, label %cmp.true, label %cmp.false6063 6064cmp.true:6065 %a1 = add <28 x i16> %a, splat (i16 3)6066 %a2 = bitcast <28 x i16> %a1 to <14 x float>6067 br label %end6068 6069cmp.false:6070 %a3 = bitcast <28 x i16> %a to <14 x float>6071 br label %end6072 6073end:6074 %phi = phi <14 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]6075 ret <14 x float> %phi6076}6077 6078define inreg <14 x float> @bitcast_v28i16_to_v14f32_scalar(<28 x i16> inreg %a, i32 inreg %b) {6079; SI-LABEL: bitcast_v28i16_to_v14f32_scalar:6080; SI: ; %bb.0:6081; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6082; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v146083; SI-NEXT: v_mov_b32_e32 v16, v126084; SI-NEXT: v_mov_b32_e32 v17, v106085; SI-NEXT: v_mov_b32_e32 v18, v86086; SI-NEXT: v_mov_b32_e32 v19, v66087; SI-NEXT: v_mov_b32_e32 v20, v46088; SI-NEXT: v_mov_b32_e32 v21, v26089; SI-NEXT: v_mov_b32_e32 v22, v06090; SI-NEXT: s_and_b64 s[4:5], vcc, exec6091; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v16092; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v36093; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v56094; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v76095; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v96096; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v116097; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v136098; SI-NEXT: s_cbranch_scc0 .LBB31_46099; SI-NEXT: ; %bb.1: ; %cmp.false6100; SI-NEXT: s_and_b32 s4, s16, 0xffff6101; SI-NEXT: s_lshl_b32 s5, s17, 166102; SI-NEXT: s_or_b32 s4, s4, s56103; SI-NEXT: s_and_b32 s5, s18, 0xffff6104; SI-NEXT: s_lshl_b32 s6, s19, 166105; SI-NEXT: v_and_b32_e32 v0, 0xffff, v226106; SI-NEXT: s_or_b32 s5, s5, s66107; SI-NEXT: s_and_b32 s6, s20, 0xffff6108; SI-NEXT: s_lshl_b32 s7, s21, 166109; SI-NEXT: v_or_b32_e32 v7, v0, v296110; SI-NEXT: v_and_b32_e32 v0, 0xffff, v206111; SI-NEXT: s_or_b32 s6, s6, s76112; SI-NEXT: s_and_b32 s7, s22, 0xffff6113; SI-NEXT: s_lshl_b32 s8, s23, 166114; SI-NEXT: v_or_b32_e32 v9, v0, v276115; SI-NEXT: v_and_b32_e32 v0, 0xffff, v196116; SI-NEXT: s_or_b32 s7, s7, s86117; SI-NEXT: s_and_b32 s8, s24, 0xffff6118; SI-NEXT: s_lshl_b32 s9, s25, 166119; SI-NEXT: v_or_b32_e32 v10, v0, v266120; SI-NEXT: v_and_b32_e32 v0, 0xffff, v186121; SI-NEXT: s_or_b32 s8, s8, s96122; SI-NEXT: s_and_b32 s9, s26, 0xffff6123; SI-NEXT: s_lshl_b32 s10, s27, 166124; SI-NEXT: v_or_b32_e32 v11, v0, v256125; SI-NEXT: v_and_b32_e32 v0, 0xffff, v176126; SI-NEXT: s_or_b32 s9, s9, s106127; SI-NEXT: s_and_b32 s10, s28, 0xffff6128; SI-NEXT: s_lshl_b32 s11, s29, 166129; SI-NEXT: v_and_b32_e32 v1, 0xffff, v216130; SI-NEXT: v_or_b32_e32 v12, v0, v246131; SI-NEXT: v_and_b32_e32 v0, 0xffff, v166132; SI-NEXT: s_or_b32 s10, s10, s116133; SI-NEXT: v_or_b32_e32 v8, v1, v286134; SI-NEXT: v_or_b32_e32 v13, v0, v236135; SI-NEXT: v_mov_b32_e32 v0, s46136; SI-NEXT: v_mov_b32_e32 v1, s56137; SI-NEXT: v_mov_b32_e32 v2, s66138; SI-NEXT: v_mov_b32_e32 v3, s76139; SI-NEXT: v_mov_b32_e32 v4, s86140; SI-NEXT: v_mov_b32_e32 v5, s96141; SI-NEXT: v_mov_b32_e32 v6, s106142; SI-NEXT: s_cbranch_execnz .LBB31_36143; SI-NEXT: .LBB31_2: ; %cmp.true6144; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v226145; SI-NEXT: v_and_b32_e32 v0, 0xffff, v06146; SI-NEXT: v_or_b32_e32 v0, v29, v06147; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v06148; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v216149; SI-NEXT: v_and_b32_e32 v0, 0xffff, v06150; SI-NEXT: v_or_b32_e32 v0, v28, v06151; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v06152; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v206153; SI-NEXT: v_and_b32_e32 v0, 0xffff, v06154; SI-NEXT: v_or_b32_e32 v0, v27, v06155; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v06156; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v196157; SI-NEXT: v_and_b32_e32 v0, 0xffff, v06158; SI-NEXT: s_add_i32 s16, s16, 36159; SI-NEXT: v_or_b32_e32 v0, v26, v06160; SI-NEXT: s_and_b32 s4, s16, 0xffff6161; SI-NEXT: s_lshl_b32 s5, s17, 166162; SI-NEXT: s_add_i32 s18, s18, 36163; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v06164; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v186165; SI-NEXT: s_or_b32 s4, s5, s46166; SI-NEXT: s_and_b32 s5, s18, 0xffff6167; SI-NEXT: s_lshl_b32 s6, s19, 166168; SI-NEXT: s_add_i32 s20, s20, 36169; SI-NEXT: v_and_b32_e32 v0, 0xffff, v06170; SI-NEXT: s_or_b32 s5, s6, s56171; SI-NEXT: s_and_b32 s6, s20, 0xffff6172; SI-NEXT: s_lshl_b32 s7, s21, 166173; SI-NEXT: s_add_i32 s22, s22, 36174; SI-NEXT: v_or_b32_e32 v0, v25, v06175; SI-NEXT: s_or_b32 s6, s7, s66176; SI-NEXT: s_and_b32 s7, s22, 0xffff6177; SI-NEXT: s_lshl_b32 s8, s23, 166178; SI-NEXT: s_add_i32 s24, s24, 36179; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v06180; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v176181; SI-NEXT: s_or_b32 s7, s8, s76182; SI-NEXT: s_and_b32 s8, s24, 0xffff6183; SI-NEXT: s_lshl_b32 s9, s25, 166184; SI-NEXT: s_add_i32 s26, s26, 36185; SI-NEXT: v_and_b32_e32 v0, 0xffff, v06186; SI-NEXT: s_or_b32 s8, s9, s86187; SI-NEXT: s_and_b32 s9, s26, 0xffff6188; SI-NEXT: s_lshl_b32 s10, s27, 166189; SI-NEXT: s_add_i32 s28, s28, 36190; SI-NEXT: v_or_b32_e32 v0, v24, v06191; SI-NEXT: s_or_b32 s9, s10, s96192; SI-NEXT: s_and_b32 s10, s28, 0xffff6193; SI-NEXT: s_lshl_b32 s11, s29, 166194; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v06195; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v166196; SI-NEXT: s_or_b32 s10, s11, s106197; SI-NEXT: v_and_b32_e32 v0, 0xffff, v06198; SI-NEXT: s_add_i32 s4, s4, 0x300006199; SI-NEXT: s_add_i32 s5, s5, 0x300006200; SI-NEXT: s_add_i32 s6, s6, 0x300006201; SI-NEXT: s_add_i32 s7, s7, 0x300006202; SI-NEXT: s_add_i32 s8, s8, 0x300006203; SI-NEXT: s_add_i32 s9, s9, 0x300006204; SI-NEXT: s_add_i32 s10, s10, 0x300006205; SI-NEXT: v_or_b32_e32 v0, v23, v06206; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v06207; SI-NEXT: v_mov_b32_e32 v0, s46208; SI-NEXT: v_mov_b32_e32 v1, s56209; SI-NEXT: v_mov_b32_e32 v2, s66210; SI-NEXT: v_mov_b32_e32 v3, s76211; SI-NEXT: v_mov_b32_e32 v4, s86212; SI-NEXT: v_mov_b32_e32 v5, s96213; SI-NEXT: v_mov_b32_e32 v6, s106214; SI-NEXT: .LBB31_3: ; %end6215; SI-NEXT: s_setpc_b64 s[30:31]6216; SI-NEXT: .LBB31_4:6217; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr156218; SI-NEXT: s_branch .LBB31_26219;6220; VI-LABEL: bitcast_v28i16_to_v14f32_scalar:6221; VI: ; %bb.0:6222; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6223; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v06224; VI-NEXT: s_and_b64 s[4:5], vcc, exec6225; VI-NEXT: s_cbranch_scc0 .LBB31_46226; VI-NEXT: ; %bb.1: ; %cmp.false6227; VI-NEXT: s_cbranch_execnz .LBB31_36228; VI-NEXT: .LBB31_2: ; %cmp.true6229; VI-NEXT: s_add_i32 s5, s29, 36230; VI-NEXT: s_and_b32 s4, s29, 0xffff00006231; VI-NEXT: s_and_b32 s5, s5, 0xffff6232; VI-NEXT: s_or_b32 s4, s4, s56233; VI-NEXT: s_add_i32 s5, s28, 36234; VI-NEXT: s_add_i32 s29, s4, 0x300006235; VI-NEXT: s_and_b32 s4, s28, 0xffff00006236; VI-NEXT: s_and_b32 s5, s5, 0xffff6237; VI-NEXT: s_or_b32 s4, s4, s56238; VI-NEXT: s_add_i32 s5, s27, 36239; VI-NEXT: s_add_i32 s28, s4, 0x300006240; VI-NEXT: s_and_b32 s4, s27, 0xffff00006241; VI-NEXT: s_and_b32 s5, s5, 0xffff6242; VI-NEXT: s_or_b32 s4, s4, s56243; VI-NEXT: s_add_i32 s5, s26, 36244; VI-NEXT: s_add_i32 s27, s4, 0x300006245; VI-NEXT: s_and_b32 s4, s26, 0xffff00006246; VI-NEXT: s_and_b32 s5, s5, 0xffff6247; VI-NEXT: s_or_b32 s4, s4, s56248; VI-NEXT: s_add_i32 s5, s25, 36249; VI-NEXT: s_add_i32 s26, s4, 0x300006250; VI-NEXT: s_and_b32 s4, s25, 0xffff00006251; VI-NEXT: s_and_b32 s5, s5, 0xffff6252; VI-NEXT: s_or_b32 s4, s4, s56253; VI-NEXT: s_add_i32 s5, s24, 36254; VI-NEXT: s_add_i32 s25, s4, 0x300006255; VI-NEXT: s_and_b32 s4, s24, 0xffff00006256; VI-NEXT: s_and_b32 s5, s5, 0xffff6257; VI-NEXT: s_or_b32 s4, s4, s56258; VI-NEXT: s_add_i32 s5, s23, 36259; VI-NEXT: s_add_i32 s24, s4, 0x300006260; VI-NEXT: s_and_b32 s4, s23, 0xffff00006261; VI-NEXT: s_and_b32 s5, s5, 0xffff6262; VI-NEXT: s_or_b32 s4, s4, s56263; VI-NEXT: s_add_i32 s5, s22, 36264; VI-NEXT: s_add_i32 s23, s4, 0x300006265; VI-NEXT: s_and_b32 s4, s22, 0xffff00006266; VI-NEXT: s_and_b32 s5, s5, 0xffff6267; VI-NEXT: s_or_b32 s4, s4, s56268; VI-NEXT: s_add_i32 s5, s21, 36269; VI-NEXT: s_add_i32 s22, s4, 0x300006270; VI-NEXT: s_and_b32 s4, s21, 0xffff00006271; VI-NEXT: s_and_b32 s5, s5, 0xffff6272; VI-NEXT: s_or_b32 s4, s4, s56273; VI-NEXT: s_add_i32 s5, s20, 36274; VI-NEXT: s_add_i32 s21, s4, 0x300006275; VI-NEXT: s_and_b32 s4, s20, 0xffff00006276; VI-NEXT: s_and_b32 s5, s5, 0xffff6277; VI-NEXT: s_or_b32 s4, s4, s56278; VI-NEXT: s_add_i32 s5, s19, 36279; VI-NEXT: s_add_i32 s20, s4, 0x300006280; VI-NEXT: s_and_b32 s4, s19, 0xffff00006281; VI-NEXT: s_and_b32 s5, s5, 0xffff6282; VI-NEXT: s_or_b32 s4, s4, s56283; VI-NEXT: s_add_i32 s5, s18, 36284; VI-NEXT: s_add_i32 s19, s4, 0x300006285; VI-NEXT: s_and_b32 s4, s18, 0xffff00006286; VI-NEXT: s_and_b32 s5, s5, 0xffff6287; VI-NEXT: s_or_b32 s4, s4, s56288; VI-NEXT: s_add_i32 s5, s17, 36289; VI-NEXT: s_add_i32 s18, s4, 0x300006290; VI-NEXT: s_and_b32 s4, s17, 0xffff00006291; VI-NEXT: s_and_b32 s5, s5, 0xffff6292; VI-NEXT: s_or_b32 s4, s4, s56293; VI-NEXT: s_add_i32 s5, s16, 36294; VI-NEXT: s_add_i32 s17, s4, 0x300006295; VI-NEXT: s_and_b32 s4, s16, 0xffff00006296; VI-NEXT: s_and_b32 s5, s5, 0xffff6297; VI-NEXT: s_or_b32 s4, s4, s56298; VI-NEXT: s_add_i32 s16, s4, 0x300006299; VI-NEXT: .LBB31_3: ; %end6300; VI-NEXT: v_mov_b32_e32 v0, s166301; VI-NEXT: v_mov_b32_e32 v1, s176302; VI-NEXT: v_mov_b32_e32 v2, s186303; VI-NEXT: v_mov_b32_e32 v3, s196304; VI-NEXT: v_mov_b32_e32 v4, s206305; VI-NEXT: v_mov_b32_e32 v5, s216306; VI-NEXT: v_mov_b32_e32 v6, s226307; VI-NEXT: v_mov_b32_e32 v7, s236308; VI-NEXT: v_mov_b32_e32 v8, s246309; VI-NEXT: v_mov_b32_e32 v9, s256310; VI-NEXT: v_mov_b32_e32 v10, s266311; VI-NEXT: v_mov_b32_e32 v11, s276312; VI-NEXT: v_mov_b32_e32 v12, s286313; VI-NEXT: v_mov_b32_e32 v13, s296314; VI-NEXT: s_setpc_b64 s[30:31]6315; VI-NEXT: .LBB31_4:6316; VI-NEXT: s_branch .LBB31_26317;6318; GFX9-LABEL: bitcast_v28i16_to_v14f32_scalar:6319; GFX9: ; %bb.0:6320; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6321; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v06322; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec6323; GFX9-NEXT: s_cbranch_scc0 .LBB31_36324; GFX9-NEXT: ; %bb.1: ; %cmp.false6325; GFX9-NEXT: s_cbranch_execnz .LBB31_46326; GFX9-NEXT: .LBB31_2: ; %cmp.true6327; GFX9-NEXT: v_pk_add_u16 v13, s29, 3 op_sel_hi:[1,0]6328; GFX9-NEXT: v_pk_add_u16 v12, s28, 3 op_sel_hi:[1,0]6329; GFX9-NEXT: v_pk_add_u16 v11, s27, 3 op_sel_hi:[1,0]6330; GFX9-NEXT: v_pk_add_u16 v10, s26, 3 op_sel_hi:[1,0]6331; GFX9-NEXT: v_pk_add_u16 v9, s25, 3 op_sel_hi:[1,0]6332; GFX9-NEXT: v_pk_add_u16 v8, s24, 3 op_sel_hi:[1,0]6333; GFX9-NEXT: v_pk_add_u16 v7, s23, 3 op_sel_hi:[1,0]6334; GFX9-NEXT: v_pk_add_u16 v6, s22, 3 op_sel_hi:[1,0]6335; GFX9-NEXT: v_pk_add_u16 v5, s21, 3 op_sel_hi:[1,0]6336; GFX9-NEXT: v_pk_add_u16 v4, s20, 3 op_sel_hi:[1,0]6337; GFX9-NEXT: v_pk_add_u16 v3, s19, 3 op_sel_hi:[1,0]6338; GFX9-NEXT: v_pk_add_u16 v2, s18, 3 op_sel_hi:[1,0]6339; GFX9-NEXT: v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]6340; GFX9-NEXT: v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]6341; GFX9-NEXT: s_setpc_b64 s[30:31]6342; GFX9-NEXT: .LBB31_3:6343; GFX9-NEXT: s_branch .LBB31_26344; GFX9-NEXT: .LBB31_4:6345; GFX9-NEXT: v_mov_b32_e32 v0, s166346; GFX9-NEXT: v_mov_b32_e32 v1, s176347; GFX9-NEXT: v_mov_b32_e32 v2, s186348; GFX9-NEXT: v_mov_b32_e32 v3, s196349; GFX9-NEXT: v_mov_b32_e32 v4, s206350; GFX9-NEXT: v_mov_b32_e32 v5, s216351; GFX9-NEXT: v_mov_b32_e32 v6, s226352; GFX9-NEXT: v_mov_b32_e32 v7, s236353; GFX9-NEXT: v_mov_b32_e32 v8, s246354; GFX9-NEXT: v_mov_b32_e32 v9, s256355; GFX9-NEXT: v_mov_b32_e32 v10, s266356; GFX9-NEXT: v_mov_b32_e32 v11, s276357; GFX9-NEXT: v_mov_b32_e32 v12, s286358; GFX9-NEXT: v_mov_b32_e32 v13, s296359; GFX9-NEXT: v_mov_b32_e32 v14, s306360; GFX9-NEXT: v_mov_b32_e32 v15, s316361; GFX9-NEXT: s_setpc_b64 s[30:31]6362;6363; GFX11-LABEL: bitcast_v28i16_to_v14f32_scalar:6364; GFX11: ; %bb.0:6365; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6366; GFX11-NEXT: s_mov_b32 s15, s36367; GFX11-NEXT: s_mov_b32 s14, s26368; GFX11-NEXT: s_mov_b32 s13, s16369; GFX11-NEXT: s_mov_b32 s12, s06370; GFX11-NEXT: s_cmp_lg_u32 s26, 06371; GFX11-NEXT: s_mov_b32 s0, 06372; GFX11-NEXT: s_cbranch_scc0 .LBB31_36373; GFX11-NEXT: ; %bb.1: ; %Flow6374; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s06375; GFX11-NEXT: s_cbranch_vccnz .LBB31_46376; GFX11-NEXT: .LBB31_2: ; %cmp.true6377; GFX11-NEXT: v_pk_add_u16 v13, s25, 3 op_sel_hi:[1,0]6378; GFX11-NEXT: v_pk_add_u16 v12, s24, 3 op_sel_hi:[1,0]6379; GFX11-NEXT: v_pk_add_u16 v11, s23, 3 op_sel_hi:[1,0]6380; GFX11-NEXT: v_pk_add_u16 v10, s22, 3 op_sel_hi:[1,0]6381; GFX11-NEXT: v_pk_add_u16 v9, s21, 3 op_sel_hi:[1,0]6382; GFX11-NEXT: v_pk_add_u16 v8, s20, 3 op_sel_hi:[1,0]6383; GFX11-NEXT: v_pk_add_u16 v7, s19, 3 op_sel_hi:[1,0]6384; GFX11-NEXT: v_pk_add_u16 v6, s18, 3 op_sel_hi:[1,0]6385; GFX11-NEXT: v_pk_add_u16 v5, s17, 3 op_sel_hi:[1,0]6386; GFX11-NEXT: v_pk_add_u16 v4, s16, 3 op_sel_hi:[1,0]6387; GFX11-NEXT: v_pk_add_u16 v3, s15, 3 op_sel_hi:[1,0]6388; GFX11-NEXT: v_pk_add_u16 v2, s14, 3 op_sel_hi:[1,0]6389; GFX11-NEXT: v_pk_add_u16 v1, s13, 3 op_sel_hi:[1,0]6390; GFX11-NEXT: v_pk_add_u16 v0, s12, 3 op_sel_hi:[1,0]6391; GFX11-NEXT: s_setpc_b64 s[30:31]6392; GFX11-NEXT: .LBB31_3:6393; GFX11-NEXT: s_branch .LBB31_26394; GFX11-NEXT: .LBB31_4:6395; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s136396; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s156397; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s176398; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s196399; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s216400; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s236401; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s256402; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s276403; GFX11-NEXT: s_setpc_b64 s[30:31]6404 %cmp = icmp eq i32 %b, 06405 br i1 %cmp, label %cmp.true, label %cmp.false6406 6407cmp.true:6408 %a1 = add <28 x i16> %a, splat (i16 3)6409 %a2 = bitcast <28 x i16> %a1 to <14 x float>6410 br label %end6411 6412cmp.false:6413 %a3 = bitcast <28 x i16> %a to <14 x float>6414 br label %end6415 6416end:6417 %phi = phi <14 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]6418 ret <14 x float> %phi6419}6420 6421define <28 x half> @bitcast_v14f32_to_v28f16(<14 x float> %a, i32 %b) {6422; SI-LABEL: bitcast_v14f32_to_v28f16:6423; SI: ; %bb.0:6424; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6425; SI-NEXT: v_mov_b32_e32 v28, v136426; SI-NEXT: v_mov_b32_e32 v29, v126427; SI-NEXT: v_mov_b32_e32 v30, v116428; SI-NEXT: v_mov_b32_e32 v31, v106429; SI-NEXT: v_mov_b32_e32 v32, v96430; SI-NEXT: v_mov_b32_e32 v33, v86431; SI-NEXT: v_mov_b32_e32 v34, v76432; SI-NEXT: v_mov_b32_e32 v35, v66433; SI-NEXT: v_mov_b32_e32 v36, v56434; SI-NEXT: v_mov_b32_e32 v37, v46435; SI-NEXT: v_mov_b32_e32 v38, v36436; SI-NEXT: v_mov_b32_e32 v39, v26437; SI-NEXT: v_mov_b32_e32 v48, v16438; SI-NEXT: v_mov_b32_e32 v49, v06439; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v146440; SI-NEXT: ; implicit-def: $vgpr06441; SI-NEXT: ; implicit-def: $vgpr16442; SI-NEXT: ; implicit-def: $vgpr26443; SI-NEXT: ; implicit-def: $vgpr36444; SI-NEXT: ; implicit-def: $vgpr46445; SI-NEXT: ; implicit-def: $vgpr56446; SI-NEXT: ; implicit-def: $vgpr66447; SI-NEXT: ; implicit-def: $vgpr76448; SI-NEXT: ; implicit-def: $vgpr86449; SI-NEXT: ; implicit-def: $vgpr96450; SI-NEXT: ; implicit-def: $vgpr106451; SI-NEXT: ; implicit-def: $vgpr116452; SI-NEXT: ; implicit-def: $vgpr126453; SI-NEXT: ; implicit-def: $vgpr136454; SI-NEXT: ; implicit-def: $vgpr146455; SI-NEXT: ; implicit-def: $vgpr156456; SI-NEXT: ; implicit-def: $vgpr166457; SI-NEXT: ; implicit-def: $vgpr176458; SI-NEXT: ; implicit-def: $vgpr186459; SI-NEXT: ; implicit-def: $vgpr196460; SI-NEXT: ; implicit-def: $vgpr206461; SI-NEXT: ; implicit-def: $vgpr216462; SI-NEXT: ; implicit-def: $vgpr226463; SI-NEXT: ; implicit-def: $vgpr236464; SI-NEXT: ; implicit-def: $vgpr246465; SI-NEXT: ; implicit-def: $vgpr256466; SI-NEXT: ; implicit-def: $vgpr266467; SI-NEXT: ; implicit-def: $vgpr276468; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc6469; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]6470; SI-NEXT: s_cbranch_execnz .LBB32_36471; SI-NEXT: ; %bb.1: ; %Flow6472; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]6473; SI-NEXT: s_cbranch_execnz .LBB32_46474; SI-NEXT: .LBB32_2: ; %end6475; SI-NEXT: s_or_b64 exec, exec, s[4:5]6476; SI-NEXT: s_setpc_b64 s[30:31]6477; SI-NEXT: .LBB32_3: ; %cmp.false6478; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v286479; SI-NEXT: v_cvt_f32_f16_e32 v27, v06480; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v296481; SI-NEXT: v_cvt_f32_f16_e32 v25, v06482; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v306483; SI-NEXT: v_cvt_f32_f16_e32 v23, v06484; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v316485; SI-NEXT: v_cvt_f32_f16_e32 v21, v06486; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v326487; SI-NEXT: v_cvt_f32_f16_e32 v19, v06488; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v336489; SI-NEXT: v_cvt_f32_f16_e32 v17, v06490; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v346491; SI-NEXT: v_cvt_f32_f16_e32 v15, v06492; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v356493; SI-NEXT: v_cvt_f32_f16_e32 v13, v06494; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v366495; SI-NEXT: v_cvt_f32_f16_e32 v11, v06496; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v376497; SI-NEXT: v_cvt_f32_f16_e32 v9, v06498; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v386499; SI-NEXT: v_cvt_f32_f16_e32 v7, v06500; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v396501; SI-NEXT: v_cvt_f32_f16_e32 v5, v06502; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v486503; SI-NEXT: v_cvt_f32_f16_e32 v3, v06504; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v496505; SI-NEXT: v_cvt_f32_f16_e32 v1, v06506; SI-NEXT: v_cvt_f32_f16_e32 v26, v286507; SI-NEXT: v_cvt_f32_f16_e32 v24, v296508; SI-NEXT: v_cvt_f32_f16_e32 v22, v306509; SI-NEXT: v_cvt_f32_f16_e32 v20, v316510; SI-NEXT: v_cvt_f32_f16_e32 v18, v326511; SI-NEXT: v_cvt_f32_f16_e32 v16, v336512; SI-NEXT: v_cvt_f32_f16_e32 v14, v346513; SI-NEXT: v_cvt_f32_f16_e32 v12, v356514; SI-NEXT: v_cvt_f32_f16_e32 v10, v366515; SI-NEXT: v_cvt_f32_f16_e32 v8, v376516; SI-NEXT: v_cvt_f32_f16_e32 v6, v386517; SI-NEXT: v_cvt_f32_f16_e32 v4, v396518; SI-NEXT: v_cvt_f32_f16_e32 v2, v486519; SI-NEXT: v_cvt_f32_f16_e32 v0, v496520; SI-NEXT: ; implicit-def: $vgpr496521; SI-NEXT: ; implicit-def: $vgpr486522; SI-NEXT: ; implicit-def: $vgpr396523; SI-NEXT: ; implicit-def: $vgpr386524; SI-NEXT: ; implicit-def: $vgpr376525; SI-NEXT: ; implicit-def: $vgpr366526; SI-NEXT: ; implicit-def: $vgpr356527; SI-NEXT: ; implicit-def: $vgpr346528; SI-NEXT: ; implicit-def: $vgpr336529; SI-NEXT: ; implicit-def: $vgpr326530; SI-NEXT: ; implicit-def: $vgpr316531; SI-NEXT: ; implicit-def: $vgpr306532; SI-NEXT: ; implicit-def: $vgpr296533; SI-NEXT: ; implicit-def: $vgpr286534; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]6535; SI-NEXT: s_cbranch_execz .LBB32_26536; SI-NEXT: .LBB32_4: ; %cmp.true6537; SI-NEXT: v_add_f32_e32 v0, 1.0, v496538; SI-NEXT: v_add_f32_e32 v2, 1.0, v486539; SI-NEXT: v_add_f32_e32 v4, 1.0, v396540; SI-NEXT: v_add_f32_e32 v6, 1.0, v386541; SI-NEXT: v_add_f32_e32 v8, 1.0, v376542; SI-NEXT: v_add_f32_e32 v10, 1.0, v366543; SI-NEXT: v_add_f32_e32 v12, 1.0, v356544; SI-NEXT: v_add_f32_e32 v14, 1.0, v346545; SI-NEXT: v_add_f32_e32 v16, 1.0, v336546; SI-NEXT: v_add_f32_e32 v18, 1.0, v326547; SI-NEXT: v_add_f32_e32 v20, 1.0, v316548; SI-NEXT: v_add_f32_e32 v22, 1.0, v306549; SI-NEXT: v_add_f32_e32 v24, 1.0, v296550; SI-NEXT: v_add_f32_e32 v26, 1.0, v286551; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v06552; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v26553; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v46554; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v66555; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v86556; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v106557; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v126558; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v146559; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v166560; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v186561; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v206562; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v226563; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v246564; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v266565; SI-NEXT: v_cvt_f32_f16_e32 v26, v266566; SI-NEXT: v_cvt_f32_f16_e32 v24, v246567; SI-NEXT: v_cvt_f32_f16_e32 v22, v226568; SI-NEXT: v_cvt_f32_f16_e32 v20, v206569; SI-NEXT: v_cvt_f32_f16_e32 v18, v186570; SI-NEXT: v_cvt_f32_f16_e32 v16, v166571; SI-NEXT: v_cvt_f32_f16_e32 v14, v146572; SI-NEXT: v_cvt_f32_f16_e32 v12, v126573; SI-NEXT: v_cvt_f32_f16_e32 v10, v106574; SI-NEXT: v_cvt_f32_f16_e32 v8, v86575; SI-NEXT: v_cvt_f32_f16_e32 v6, v66576; SI-NEXT: v_cvt_f32_f16_e32 v4, v46577; SI-NEXT: v_cvt_f32_f16_e32 v2, v26578; SI-NEXT: v_cvt_f32_f16_e32 v0, v06579; SI-NEXT: v_cvt_f32_f16_e32 v27, v276580; SI-NEXT: v_cvt_f32_f16_e32 v25, v256581; SI-NEXT: v_cvt_f32_f16_e32 v23, v236582; SI-NEXT: v_cvt_f32_f16_e32 v21, v216583; SI-NEXT: v_cvt_f32_f16_e32 v19, v196584; SI-NEXT: v_cvt_f32_f16_e32 v17, v176585; SI-NEXT: v_cvt_f32_f16_e32 v15, v156586; SI-NEXT: v_cvt_f32_f16_e32 v13, v136587; SI-NEXT: v_cvt_f32_f16_e32 v11, v116588; SI-NEXT: v_cvt_f32_f16_e32 v9, v96589; SI-NEXT: v_cvt_f32_f16_e32 v7, v76590; SI-NEXT: v_cvt_f32_f16_e32 v5, v56591; SI-NEXT: v_cvt_f32_f16_e32 v3, v36592; SI-NEXT: v_cvt_f32_f16_e32 v1, v16593; SI-NEXT: s_or_b64 exec, exec, s[4:5]6594; SI-NEXT: s_setpc_b64 s[30:31]6595;6596; VI-LABEL: bitcast_v14f32_to_v28f16:6597; VI: ; %bb.0:6598; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6599; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v146600; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc6601; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]6602; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]6603; VI-NEXT: s_cbranch_execz .LBB32_26604; VI-NEXT: ; %bb.1: ; %cmp.true6605; VI-NEXT: v_add_f32_e32 v13, 1.0, v136606; VI-NEXT: v_add_f32_e32 v12, 1.0, v126607; VI-NEXT: v_add_f32_e32 v11, 1.0, v116608; VI-NEXT: v_add_f32_e32 v10, 1.0, v106609; VI-NEXT: v_add_f32_e32 v9, 1.0, v96610; VI-NEXT: v_add_f32_e32 v8, 1.0, v86611; VI-NEXT: v_add_f32_e32 v7, 1.0, v76612; VI-NEXT: v_add_f32_e32 v6, 1.0, v66613; VI-NEXT: v_add_f32_e32 v5, 1.0, v56614; VI-NEXT: v_add_f32_e32 v4, 1.0, v46615; VI-NEXT: v_add_f32_e32 v3, 1.0, v36616; VI-NEXT: v_add_f32_e32 v2, 1.0, v26617; VI-NEXT: v_add_f32_e32 v1, 1.0, v16618; VI-NEXT: v_add_f32_e32 v0, 1.0, v06619; VI-NEXT: .LBB32_2: ; %end6620; VI-NEXT: s_or_b64 exec, exec, s[4:5]6621; VI-NEXT: s_setpc_b64 s[30:31]6622;6623; GFX9-LABEL: bitcast_v14f32_to_v28f16:6624; GFX9: ; %bb.0:6625; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6626; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v146627; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc6628; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]6629; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]6630; GFX9-NEXT: s_cbranch_execz .LBB32_26631; GFX9-NEXT: ; %bb.1: ; %cmp.true6632; GFX9-NEXT: v_add_f32_e32 v13, 1.0, v136633; GFX9-NEXT: v_add_f32_e32 v12, 1.0, v126634; GFX9-NEXT: v_add_f32_e32 v11, 1.0, v116635; GFX9-NEXT: v_add_f32_e32 v10, 1.0, v106636; GFX9-NEXT: v_add_f32_e32 v9, 1.0, v96637; GFX9-NEXT: v_add_f32_e32 v8, 1.0, v86638; GFX9-NEXT: v_add_f32_e32 v7, 1.0, v76639; GFX9-NEXT: v_add_f32_e32 v6, 1.0, v66640; GFX9-NEXT: v_add_f32_e32 v5, 1.0, v56641; GFX9-NEXT: v_add_f32_e32 v4, 1.0, v46642; GFX9-NEXT: v_add_f32_e32 v3, 1.0, v36643; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v26644; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v16645; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v06646; GFX9-NEXT: .LBB32_2: ; %end6647; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]6648; GFX9-NEXT: s_setpc_b64 s[30:31]6649;6650; GFX11-LABEL: bitcast_v14f32_to_v28f16:6651; GFX11: ; %bb.0:6652; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6653; GFX11-NEXT: s_mov_b32 s0, exec_lo6654; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v146655; GFX11-NEXT: s_xor_b32 s0, exec_lo, s06656; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)6657; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s06658; GFX11-NEXT: s_cbranch_execz .LBB32_26659; GFX11-NEXT: ; %bb.1: ; %cmp.true6660; GFX11-NEXT: v_dual_add_f32 v13, 1.0, v13 :: v_dual_add_f32 v12, 1.0, v126661; GFX11-NEXT: v_dual_add_f32 v11, 1.0, v11 :: v_dual_add_f32 v10, 1.0, v106662; GFX11-NEXT: v_dual_add_f32 v9, 1.0, v9 :: v_dual_add_f32 v8, 1.0, v86663; GFX11-NEXT: v_dual_add_f32 v7, 1.0, v7 :: v_dual_add_f32 v6, 1.0, v66664; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v46665; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v26666; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v06667; GFX11-NEXT: .LBB32_2: ; %end6668; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s06669; GFX11-NEXT: s_setpc_b64 s[30:31]6670 %cmp = icmp eq i32 %b, 06671 br i1 %cmp, label %cmp.true, label %cmp.false6672 6673cmp.true:6674 %a1 = fadd <14 x float> %a, splat (float 1.000000e+00)6675 %a2 = bitcast <14 x float> %a1 to <28 x half>6676 br label %end6677 6678cmp.false:6679 %a3 = bitcast <14 x float> %a to <28 x half>6680 br label %end6681 6682end:6683 %phi = phi <28 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]6684 ret <28 x half> %phi6685}6686 6687define inreg <28 x half> @bitcast_v14f32_to_v28f16_scalar(<14 x float> inreg %a, i32 inreg %b) {6688; SI-LABEL: bitcast_v14f32_to_v28f16_scalar:6689; SI: ; %bb.0:6690; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6691; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v06692; SI-NEXT: s_and_b64 s[4:5], vcc, exec6693; SI-NEXT: s_cbranch_scc0 .LBB33_46694; SI-NEXT: ; %bb.1: ; %cmp.false6695; SI-NEXT: s_lshr_b32 s4, s29, 166696; SI-NEXT: v_cvt_f32_f16_e32 v27, s46697; SI-NEXT: s_lshr_b32 s4, s28, 166698; SI-NEXT: v_cvt_f32_f16_e32 v25, s46699; SI-NEXT: s_lshr_b32 s4, s27, 166700; SI-NEXT: v_cvt_f32_f16_e32 v23, s46701; SI-NEXT: s_lshr_b32 s4, s26, 166702; SI-NEXT: v_cvt_f32_f16_e32 v21, s46703; SI-NEXT: s_lshr_b32 s4, s25, 166704; SI-NEXT: v_cvt_f32_f16_e32 v19, s46705; SI-NEXT: s_lshr_b32 s4, s24, 166706; SI-NEXT: v_cvt_f32_f16_e32 v17, s46707; SI-NEXT: s_lshr_b32 s4, s23, 166708; SI-NEXT: v_cvt_f32_f16_e32 v15, s46709; SI-NEXT: s_lshr_b32 s4, s22, 166710; SI-NEXT: v_cvt_f32_f16_e32 v13, s46711; SI-NEXT: s_lshr_b32 s4, s21, 166712; SI-NEXT: v_cvt_f32_f16_e32 v11, s46713; SI-NEXT: s_lshr_b32 s4, s20, 166714; SI-NEXT: v_cvt_f32_f16_e32 v9, s46715; SI-NEXT: s_lshr_b32 s4, s19, 166716; SI-NEXT: v_cvt_f32_f16_e32 v7, s46717; SI-NEXT: s_lshr_b32 s4, s18, 166718; SI-NEXT: v_cvt_f32_f16_e32 v5, s46719; SI-NEXT: s_lshr_b32 s4, s17, 166720; SI-NEXT: v_cvt_f32_f16_e32 v3, s46721; SI-NEXT: s_lshr_b32 s4, s16, 166722; SI-NEXT: v_cvt_f32_f16_e32 v1, s46723; SI-NEXT: v_cvt_f32_f16_e32 v26, s296724; SI-NEXT: v_cvt_f32_f16_e32 v24, s286725; SI-NEXT: v_cvt_f32_f16_e32 v22, s276726; SI-NEXT: v_cvt_f32_f16_e32 v20, s266727; SI-NEXT: v_cvt_f32_f16_e32 v18, s256728; SI-NEXT: v_cvt_f32_f16_e32 v16, s246729; SI-NEXT: v_cvt_f32_f16_e32 v14, s236730; SI-NEXT: v_cvt_f32_f16_e32 v12, s226731; SI-NEXT: v_cvt_f32_f16_e32 v10, s216732; SI-NEXT: v_cvt_f32_f16_e32 v8, s206733; SI-NEXT: v_cvt_f32_f16_e32 v6, s196734; SI-NEXT: v_cvt_f32_f16_e32 v4, s186735; SI-NEXT: v_cvt_f32_f16_e32 v2, s176736; SI-NEXT: v_cvt_f32_f16_e32 v0, s166737; SI-NEXT: s_cbranch_execnz .LBB33_36738; SI-NEXT: .LBB33_2: ; %cmp.true6739; SI-NEXT: v_add_f32_e64 v0, s16, 1.06740; SI-NEXT: v_add_f32_e64 v2, s17, 1.06741; SI-NEXT: v_add_f32_e64 v4, s18, 1.06742; SI-NEXT: v_add_f32_e64 v6, s19, 1.06743; SI-NEXT: v_add_f32_e64 v8, s20, 1.06744; SI-NEXT: v_add_f32_e64 v10, s21, 1.06745; SI-NEXT: v_add_f32_e64 v12, s22, 1.06746; SI-NEXT: v_add_f32_e64 v14, s23, 1.06747; SI-NEXT: v_add_f32_e64 v16, s24, 1.06748; SI-NEXT: v_add_f32_e64 v18, s25, 1.06749; SI-NEXT: v_add_f32_e64 v20, s26, 1.06750; SI-NEXT: v_add_f32_e64 v22, s27, 1.06751; SI-NEXT: v_add_f32_e64 v24, s28, 1.06752; SI-NEXT: v_add_f32_e64 v26, s29, 1.06753; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v06754; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v26755; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v46756; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v66757; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v86758; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v106759; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v126760; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v146761; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v166762; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v186763; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v206764; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v226765; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v246766; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v266767; SI-NEXT: v_cvt_f32_f16_e32 v26, v266768; SI-NEXT: v_cvt_f32_f16_e32 v24, v246769; SI-NEXT: v_cvt_f32_f16_e32 v22, v226770; SI-NEXT: v_cvt_f32_f16_e32 v20, v206771; SI-NEXT: v_cvt_f32_f16_e32 v18, v186772; SI-NEXT: v_cvt_f32_f16_e32 v16, v166773; SI-NEXT: v_cvt_f32_f16_e32 v14, v146774; SI-NEXT: v_cvt_f32_f16_e32 v12, v126775; SI-NEXT: v_cvt_f32_f16_e32 v10, v106776; SI-NEXT: v_cvt_f32_f16_e32 v8, v86777; SI-NEXT: v_cvt_f32_f16_e32 v6, v66778; SI-NEXT: v_cvt_f32_f16_e32 v4, v46779; SI-NEXT: v_cvt_f32_f16_e32 v2, v26780; SI-NEXT: v_cvt_f32_f16_e32 v0, v06781; SI-NEXT: v_cvt_f32_f16_e32 v27, v276782; SI-NEXT: v_cvt_f32_f16_e32 v25, v256783; SI-NEXT: v_cvt_f32_f16_e32 v23, v236784; SI-NEXT: v_cvt_f32_f16_e32 v21, v216785; SI-NEXT: v_cvt_f32_f16_e32 v19, v196786; SI-NEXT: v_cvt_f32_f16_e32 v17, v176787; SI-NEXT: v_cvt_f32_f16_e32 v15, v156788; SI-NEXT: v_cvt_f32_f16_e32 v13, v136789; SI-NEXT: v_cvt_f32_f16_e32 v11, v116790; SI-NEXT: v_cvt_f32_f16_e32 v9, v96791; SI-NEXT: v_cvt_f32_f16_e32 v7, v76792; SI-NEXT: v_cvt_f32_f16_e32 v5, v56793; SI-NEXT: v_cvt_f32_f16_e32 v3, v36794; SI-NEXT: v_cvt_f32_f16_e32 v1, v16795; SI-NEXT: .LBB33_3: ; %end6796; SI-NEXT: s_setpc_b64 s[30:31]6797; SI-NEXT: .LBB33_4:6798; SI-NEXT: ; implicit-def: $vgpr06799; SI-NEXT: ; implicit-def: $vgpr16800; SI-NEXT: ; implicit-def: $vgpr26801; SI-NEXT: ; implicit-def: $vgpr36802; SI-NEXT: ; implicit-def: $vgpr46803; SI-NEXT: ; implicit-def: $vgpr56804; SI-NEXT: ; implicit-def: $vgpr66805; SI-NEXT: ; implicit-def: $vgpr76806; SI-NEXT: ; implicit-def: $vgpr86807; SI-NEXT: ; implicit-def: $vgpr96808; SI-NEXT: ; implicit-def: $vgpr106809; SI-NEXT: ; implicit-def: $vgpr116810; SI-NEXT: ; implicit-def: $vgpr126811; SI-NEXT: ; implicit-def: $vgpr136812; SI-NEXT: ; implicit-def: $vgpr146813; SI-NEXT: ; implicit-def: $vgpr156814; SI-NEXT: ; implicit-def: $vgpr166815; SI-NEXT: ; implicit-def: $vgpr176816; SI-NEXT: ; implicit-def: $vgpr186817; SI-NEXT: ; implicit-def: $vgpr196818; SI-NEXT: ; implicit-def: $vgpr206819; SI-NEXT: ; implicit-def: $vgpr216820; SI-NEXT: ; implicit-def: $vgpr226821; SI-NEXT: ; implicit-def: $vgpr236822; SI-NEXT: ; implicit-def: $vgpr246823; SI-NEXT: ; implicit-def: $vgpr256824; SI-NEXT: ; implicit-def: $vgpr266825; SI-NEXT: ; implicit-def: $vgpr276826; SI-NEXT: s_branch .LBB33_26827;6828; VI-LABEL: bitcast_v14f32_to_v28f16_scalar:6829; VI: ; %bb.0:6830; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6831; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v06832; VI-NEXT: s_and_b64 s[4:5], vcc, exec6833; VI-NEXT: s_cbranch_scc0 .LBB33_36834; VI-NEXT: ; %bb.1: ; %cmp.false6835; VI-NEXT: s_cbranch_execnz .LBB33_46836; VI-NEXT: .LBB33_2: ; %cmp.true6837; VI-NEXT: v_add_f32_e64 v13, s29, 1.06838; VI-NEXT: v_add_f32_e64 v12, s28, 1.06839; VI-NEXT: v_add_f32_e64 v11, s27, 1.06840; VI-NEXT: v_add_f32_e64 v10, s26, 1.06841; VI-NEXT: v_add_f32_e64 v9, s25, 1.06842; VI-NEXT: v_add_f32_e64 v8, s24, 1.06843; VI-NEXT: v_add_f32_e64 v7, s23, 1.06844; VI-NEXT: v_add_f32_e64 v6, s22, 1.06845; VI-NEXT: v_add_f32_e64 v5, s21, 1.06846; VI-NEXT: v_add_f32_e64 v4, s20, 1.06847; VI-NEXT: v_add_f32_e64 v3, s19, 1.06848; VI-NEXT: v_add_f32_e64 v2, s18, 1.06849; VI-NEXT: v_add_f32_e64 v1, s17, 1.06850; VI-NEXT: v_add_f32_e64 v0, s16, 1.06851; VI-NEXT: s_setpc_b64 s[30:31]6852; VI-NEXT: .LBB33_3:6853; VI-NEXT: s_branch .LBB33_26854; VI-NEXT: .LBB33_4:6855; VI-NEXT: v_mov_b32_e32 v0, s166856; VI-NEXT: v_mov_b32_e32 v1, s176857; VI-NEXT: v_mov_b32_e32 v2, s186858; VI-NEXT: v_mov_b32_e32 v3, s196859; VI-NEXT: v_mov_b32_e32 v4, s206860; VI-NEXT: v_mov_b32_e32 v5, s216861; VI-NEXT: v_mov_b32_e32 v6, s226862; VI-NEXT: v_mov_b32_e32 v7, s236863; VI-NEXT: v_mov_b32_e32 v8, s246864; VI-NEXT: v_mov_b32_e32 v9, s256865; VI-NEXT: v_mov_b32_e32 v10, s266866; VI-NEXT: v_mov_b32_e32 v11, s276867; VI-NEXT: v_mov_b32_e32 v12, s286868; VI-NEXT: v_mov_b32_e32 v13, s296869; VI-NEXT: v_mov_b32_e32 v14, s306870; VI-NEXT: v_mov_b32_e32 v15, s316871; VI-NEXT: s_setpc_b64 s[30:31]6872;6873; GFX9-LABEL: bitcast_v14f32_to_v28f16_scalar:6874; GFX9: ; %bb.0:6875; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6876; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v06877; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec6878; GFX9-NEXT: s_cbranch_scc0 .LBB33_36879; GFX9-NEXT: ; %bb.1: ; %cmp.false6880; GFX9-NEXT: s_cbranch_execnz .LBB33_46881; GFX9-NEXT: .LBB33_2: ; %cmp.true6882; GFX9-NEXT: v_add_f32_e64 v13, s29, 1.06883; GFX9-NEXT: v_add_f32_e64 v12, s28, 1.06884; GFX9-NEXT: v_add_f32_e64 v11, s27, 1.06885; GFX9-NEXT: v_add_f32_e64 v10, s26, 1.06886; GFX9-NEXT: v_add_f32_e64 v9, s25, 1.06887; GFX9-NEXT: v_add_f32_e64 v8, s24, 1.06888; GFX9-NEXT: v_add_f32_e64 v7, s23, 1.06889; GFX9-NEXT: v_add_f32_e64 v6, s22, 1.06890; GFX9-NEXT: v_add_f32_e64 v5, s21, 1.06891; GFX9-NEXT: v_add_f32_e64 v4, s20, 1.06892; GFX9-NEXT: v_add_f32_e64 v3, s19, 1.06893; GFX9-NEXT: v_add_f32_e64 v2, s18, 1.06894; GFX9-NEXT: v_add_f32_e64 v1, s17, 1.06895; GFX9-NEXT: v_add_f32_e64 v0, s16, 1.06896; GFX9-NEXT: s_setpc_b64 s[30:31]6897; GFX9-NEXT: .LBB33_3:6898; GFX9-NEXT: s_branch .LBB33_26899; GFX9-NEXT: .LBB33_4:6900; GFX9-NEXT: v_mov_b32_e32 v0, s166901; GFX9-NEXT: v_mov_b32_e32 v1, s176902; GFX9-NEXT: v_mov_b32_e32 v2, s186903; GFX9-NEXT: v_mov_b32_e32 v3, s196904; GFX9-NEXT: v_mov_b32_e32 v4, s206905; GFX9-NEXT: v_mov_b32_e32 v5, s216906; GFX9-NEXT: v_mov_b32_e32 v6, s226907; GFX9-NEXT: v_mov_b32_e32 v7, s236908; GFX9-NEXT: v_mov_b32_e32 v8, s246909; GFX9-NEXT: v_mov_b32_e32 v9, s256910; GFX9-NEXT: v_mov_b32_e32 v10, s266911; GFX9-NEXT: v_mov_b32_e32 v11, s276912; GFX9-NEXT: v_mov_b32_e32 v12, s286913; GFX9-NEXT: v_mov_b32_e32 v13, s296914; GFX9-NEXT: v_mov_b32_e32 v14, s306915; GFX9-NEXT: v_mov_b32_e32 v15, s316916; GFX9-NEXT: s_setpc_b64 s[30:31]6917;6918; GFX11-LABEL: bitcast_v14f32_to_v28f16_scalar:6919; GFX11: ; %bb.0:6920; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6921; GFX11-NEXT: s_mov_b32 s15, s36922; GFX11-NEXT: s_mov_b32 s14, s26923; GFX11-NEXT: s_mov_b32 s13, s16924; GFX11-NEXT: s_mov_b32 s12, s06925; GFX11-NEXT: s_cmp_lg_u32 s26, 06926; GFX11-NEXT: s_mov_b32 s0, 06927; GFX11-NEXT: s_cbranch_scc0 .LBB33_36928; GFX11-NEXT: ; %bb.1: ; %Flow6929; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s06930; GFX11-NEXT: s_cbranch_vccnz .LBB33_46931; GFX11-NEXT: .LBB33_2: ; %cmp.true6932; GFX11-NEXT: v_add_f32_e64 v13, s25, 1.06933; GFX11-NEXT: v_add_f32_e64 v12, s24, 1.06934; GFX11-NEXT: v_add_f32_e64 v11, s23, 1.06935; GFX11-NEXT: v_add_f32_e64 v10, s22, 1.06936; GFX11-NEXT: v_add_f32_e64 v9, s21, 1.06937; GFX11-NEXT: v_add_f32_e64 v8, s20, 1.06938; GFX11-NEXT: v_add_f32_e64 v7, s19, 1.06939; GFX11-NEXT: v_add_f32_e64 v6, s18, 1.06940; GFX11-NEXT: v_add_f32_e64 v5, s17, 1.06941; GFX11-NEXT: v_add_f32_e64 v4, s16, 1.06942; GFX11-NEXT: v_add_f32_e64 v3, s15, 1.06943; GFX11-NEXT: v_add_f32_e64 v2, s14, 1.06944; GFX11-NEXT: v_add_f32_e64 v1, s13, 1.06945; GFX11-NEXT: v_add_f32_e64 v0, s12, 1.06946; GFX11-NEXT: s_setpc_b64 s[30:31]6947; GFX11-NEXT: .LBB33_3:6948; GFX11-NEXT: s_branch .LBB33_26949; GFX11-NEXT: .LBB33_4:6950; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s136951; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s156952; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s176953; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s196954; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s216955; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s236956; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s256957; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s276958; GFX11-NEXT: s_setpc_b64 s[30:31]6959 %cmp = icmp eq i32 %b, 06960 br i1 %cmp, label %cmp.true, label %cmp.false6961 6962cmp.true:6963 %a1 = fadd <14 x float> %a, splat (float 1.000000e+00)6964 %a2 = bitcast <14 x float> %a1 to <28 x half>6965 br label %end6966 6967cmp.false:6968 %a3 = bitcast <14 x float> %a to <28 x half>6969 br label %end6970 6971end:6972 %phi = phi <28 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]6973 ret <28 x half> %phi6974}6975 6976define <14 x float> @bitcast_v28f16_to_v14f32(<28 x half> %a, i32 %b) {6977; SI-LABEL: bitcast_v28f16_to_v14f32:6978; SI: ; %bb.0:6979; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6980; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill6981; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill6982; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 ; 4-byte Folded Spill6983; SI-NEXT: s_waitcnt expcnt(0)6984; SI-NEXT: v_cvt_f16_f32_e32 v42, v16985; SI-NEXT: v_cvt_f16_f32_e32 v41, v06986; SI-NEXT: v_cvt_f16_f32_e32 v40, v36987; SI-NEXT: v_cvt_f16_f32_e32 v55, v26988; SI-NEXT: v_cvt_f16_f32_e32 v54, v56989; SI-NEXT: v_cvt_f16_f32_e32 v53, v46990; SI-NEXT: v_cvt_f16_f32_e32 v52, v76991; SI-NEXT: v_cvt_f16_f32_e32 v51, v66992; SI-NEXT: v_cvt_f16_f32_e32 v50, v96993; SI-NEXT: v_cvt_f16_f32_e32 v49, v86994; SI-NEXT: v_cvt_f16_f32_e32 v48, v116995; SI-NEXT: v_cvt_f16_f32_e32 v39, v106996; SI-NEXT: v_cvt_f16_f32_e32 v38, v136997; SI-NEXT: v_cvt_f16_f32_e32 v37, v126998; SI-NEXT: v_cvt_f16_f32_e32 v36, v156999; SI-NEXT: v_cvt_f16_f32_e32 v35, v147000; SI-NEXT: v_cvt_f16_f32_e32 v34, v177001; SI-NEXT: v_cvt_f16_f32_e32 v33, v167002; SI-NEXT: v_cvt_f16_f32_e32 v32, v197003; SI-NEXT: v_cvt_f16_f32_e32 v31, v187004; SI-NEXT: v_cvt_f16_f32_e32 v30, v217005; SI-NEXT: v_cvt_f16_f32_e32 v29, v207006; SI-NEXT: v_cvt_f16_f32_e32 v21, v237007; SI-NEXT: v_cvt_f16_f32_e32 v20, v227008; SI-NEXT: v_cvt_f16_f32_e32 v19, v257009; SI-NEXT: v_cvt_f16_f32_e32 v18, v247010; SI-NEXT: v_cvt_f16_f32_e32 v17, v277011; SI-NEXT: v_cvt_f16_f32_e32 v16, v267012; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v287013; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr157014; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc7015; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]7016; SI-NEXT: s_cbranch_execz .LBB34_27017; SI-NEXT: ; %bb.1: ; %cmp.false7018; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v427019; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v407020; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v547021; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v527022; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v507023; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v487024; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v387025; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v367026; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v347027; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v327028; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v307029; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v217030; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v197031; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v177032; SI-NEXT: v_or_b32_e32 v0, v41, v07033; SI-NEXT: v_or_b32_e32 v1, v55, v17034; SI-NEXT: v_or_b32_e32 v2, v53, v27035; SI-NEXT: v_or_b32_e32 v3, v51, v37036; SI-NEXT: v_or_b32_e32 v4, v49, v47037; SI-NEXT: v_or_b32_e32 v5, v39, v57038; SI-NEXT: v_or_b32_e32 v6, v37, v67039; SI-NEXT: v_or_b32_e32 v7, v35, v77040; SI-NEXT: v_or_b32_e32 v8, v33, v87041; SI-NEXT: v_or_b32_e32 v9, v31, v97042; SI-NEXT: v_or_b32_e32 v10, v29, v107043; SI-NEXT: v_or_b32_e32 v11, v20, v117044; SI-NEXT: v_or_b32_e32 v12, v18, v127045; SI-NEXT: v_or_b32_e32 v13, v16, v137046; SI-NEXT: ; implicit-def: $vgpr427047; SI-NEXT: ; implicit-def: $vgpr417048; SI-NEXT: ; implicit-def: $vgpr407049; SI-NEXT: ; implicit-def: $vgpr557050; SI-NEXT: ; implicit-def: $vgpr547051; SI-NEXT: ; implicit-def: $vgpr537052; SI-NEXT: ; implicit-def: $vgpr527053; SI-NEXT: ; implicit-def: $vgpr517054; SI-NEXT: ; implicit-def: $vgpr507055; SI-NEXT: ; implicit-def: $vgpr497056; SI-NEXT: ; implicit-def: $vgpr487057; SI-NEXT: ; implicit-def: $vgpr397058; SI-NEXT: ; implicit-def: $vgpr387059; SI-NEXT: ; implicit-def: $vgpr377060; SI-NEXT: ; implicit-def: $vgpr367061; SI-NEXT: ; implicit-def: $vgpr357062; SI-NEXT: ; implicit-def: $vgpr347063; SI-NEXT: ; implicit-def: $vgpr337064; SI-NEXT: ; implicit-def: $vgpr327065; SI-NEXT: ; implicit-def: $vgpr317066; SI-NEXT: ; implicit-def: $vgpr307067; SI-NEXT: ; implicit-def: $vgpr297068; SI-NEXT: ; implicit-def: $vgpr217069; SI-NEXT: ; implicit-def: $vgpr207070; SI-NEXT: ; implicit-def: $vgpr197071; SI-NEXT: ; implicit-def: $vgpr187072; SI-NEXT: ; implicit-def: $vgpr177073; SI-NEXT: ; implicit-def: $vgpr167074; SI-NEXT: .LBB34_2: ; %Flow7075; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]7076; SI-NEXT: s_cbranch_execz .LBB34_47077; SI-NEXT: ; %bb.3: ; %cmp.true7078; SI-NEXT: v_cvt_f32_f16_e32 v0, v427079; SI-NEXT: v_cvt_f32_f16_e32 v1, v417080; SI-NEXT: v_cvt_f32_f16_e32 v2, v407081; SI-NEXT: v_cvt_f32_f16_e32 v3, v557082; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v07083; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v17084; SI-NEXT: v_cvt_f16_f32_e32 v0, v07085; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v27086; SI-NEXT: v_cvt_f16_f32_e32 v1, v17087; SI-NEXT: v_cvt_f16_f32_e32 v2, v27088; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v07089; SI-NEXT: v_cvt_f32_f16_e32 v4, v537090; SI-NEXT: v_or_b32_e32 v0, v1, v07091; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v27092; SI-NEXT: v_cvt_f32_f16_e32 v2, v547093; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v37094; SI-NEXT: v_cvt_f16_f32_e32 v3, v37095; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v47096; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v27097; SI-NEXT: v_cvt_f16_f32_e32 v2, v27098; SI-NEXT: v_cvt_f16_f32_e32 v4, v47099; SI-NEXT: v_or_b32_e32 v1, v3, v17100; SI-NEXT: v_cvt_f32_f16_e32 v3, v527101; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v27102; SI-NEXT: v_or_b32_e32 v2, v4, v27103; SI-NEXT: v_cvt_f32_f16_e32 v4, v517104; SI-NEXT: v_cvt_f32_f16_e32 v5, v507105; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v37106; SI-NEXT: v_cvt_f16_f32_e32 v3, v37107; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v47108; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v57109; SI-NEXT: v_cvt_f16_f32_e32 v4, v47110; SI-NEXT: v_cvt_f16_f32_e32 v5, v57111; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v37112; SI-NEXT: v_cvt_f32_f16_e32 v6, v497113; SI-NEXT: v_or_b32_e32 v3, v4, v37114; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v57115; SI-NEXT: v_cvt_f32_f16_e32 v5, v487116; SI-NEXT: v_cvt_f32_f16_e32 v7, v397117; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v67118; SI-NEXT: v_cvt_f16_f32_e32 v6, v67119; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v57120; SI-NEXT: v_cvt_f16_f32_e32 v5, v57121; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v77122; SI-NEXT: v_cvt_f16_f32_e32 v7, v77123; SI-NEXT: v_or_b32_e32 v4, v6, v47124; SI-NEXT: v_cvt_f32_f16_e32 v6, v387125; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v57126; SI-NEXT: v_or_b32_e32 v5, v7, v57127; SI-NEXT: v_cvt_f32_f16_e32 v7, v377128; SI-NEXT: v_cvt_f32_f16_e32 v8, v367129; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v67130; SI-NEXT: v_cvt_f16_f32_e32 v6, v67131; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v77132; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v87133; SI-NEXT: v_cvt_f16_f32_e32 v7, v77134; SI-NEXT: v_cvt_f16_f32_e32 v8, v87135; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v67136; SI-NEXT: v_cvt_f32_f16_e32 v9, v357137; SI-NEXT: v_or_b32_e32 v6, v7, v67138; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v87139; SI-NEXT: v_cvt_f32_f16_e32 v8, v347140; SI-NEXT: v_cvt_f32_f16_e32 v10, v337141; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v97142; SI-NEXT: v_cvt_f16_f32_e32 v9, v97143; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v87144; SI-NEXT: v_cvt_f16_f32_e32 v8, v87145; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v107146; SI-NEXT: v_cvt_f16_f32_e32 v10, v107147; SI-NEXT: v_or_b32_e32 v7, v9, v77148; SI-NEXT: v_cvt_f32_f16_e32 v9, v327149; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v87150; SI-NEXT: v_or_b32_e32 v8, v10, v87151; SI-NEXT: v_cvt_f32_f16_e32 v10, v317152; SI-NEXT: v_cvt_f32_f16_e32 v11, v307153; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v97154; SI-NEXT: v_cvt_f16_f32_e32 v9, v97155; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v107156; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v117157; SI-NEXT: v_cvt_f16_f32_e32 v10, v107158; SI-NEXT: v_cvt_f16_f32_e32 v11, v117159; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v97160; SI-NEXT: v_cvt_f32_f16_e32 v12, v297161; SI-NEXT: v_or_b32_e32 v9, v10, v97162; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v117163; SI-NEXT: v_cvt_f32_f16_e32 v11, v217164; SI-NEXT: v_cvt_f32_f16_e32 v13, v207165; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v127166; SI-NEXT: v_cvt_f16_f32_e32 v12, v127167; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v117168; SI-NEXT: v_cvt_f16_f32_e32 v11, v117169; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v137170; SI-NEXT: v_cvt_f16_f32_e32 v13, v137171; SI-NEXT: v_or_b32_e32 v10, v12, v107172; SI-NEXT: v_cvt_f32_f16_e32 v12, v197173; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v117174; SI-NEXT: v_or_b32_e32 v11, v13, v117175; SI-NEXT: v_cvt_f32_f16_e32 v13, v187176; SI-NEXT: v_cvt_f32_f16_e32 v14, v177177; SI-NEXT: v_cvt_f32_f16_e32 v15, v167178; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v127179; SI-NEXT: v_cvt_f16_f32_e32 v12, v127180; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v137181; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v147182; SI-NEXT: v_cvt_f16_f32_e32 v13, v137183; SI-NEXT: v_cvt_f16_f32_e32 v14, v147184; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v157185; SI-NEXT: v_cvt_f16_f32_e32 v15, v157186; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v127187; SI-NEXT: v_or_b32_e32 v12, v13, v127188; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v147189; SI-NEXT: v_or_b32_e32 v13, v15, v137190; SI-NEXT: .LBB34_4: ; %end7191; SI-NEXT: s_or_b64 exec, exec, s[4:5]7192; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 ; 4-byte Folded Reload7193; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload7194; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload7195; SI-NEXT: s_waitcnt vmcnt(0)7196; SI-NEXT: s_setpc_b64 s[30:31]7197;7198; VI-LABEL: bitcast_v28f16_to_v14f32:7199; VI: ; %bb.0:7200; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7201; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v147202; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc7203; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]7204; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]7205; VI-NEXT: s_cbranch_execz .LBB34_27206; VI-NEXT: ; %bb.1: ; %cmp.true7207; VI-NEXT: v_mov_b32_e32 v14, 0x2007208; VI-NEXT: v_add_f16_sdwa v15, v13, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD7209; VI-NEXT: v_add_f16_e32 v13, 0x200, v137210; VI-NEXT: v_or_b32_e32 v13, v13, v157211; VI-NEXT: v_add_f16_sdwa v15, v12, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD7212; VI-NEXT: v_add_f16_e32 v12, 0x200, v127213; VI-NEXT: v_or_b32_e32 v12, v12, v157214; VI-NEXT: v_add_f16_sdwa v15, v11, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD7215; VI-NEXT: v_add_f16_e32 v11, 0x200, v117216; VI-NEXT: v_or_b32_e32 v11, v11, v157217; VI-NEXT: v_add_f16_sdwa v15, v10, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD7218; VI-NEXT: v_add_f16_e32 v10, 0x200, v107219; VI-NEXT: v_or_b32_e32 v10, v10, v157220; VI-NEXT: v_add_f16_sdwa v15, v9, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD7221; VI-NEXT: v_add_f16_e32 v9, 0x200, v97222; VI-NEXT: v_or_b32_e32 v9, v9, v157223; VI-NEXT: v_add_f16_sdwa v15, v8, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD7224; VI-NEXT: v_add_f16_e32 v8, 0x200, v87225; VI-NEXT: v_or_b32_e32 v8, v8, v157226; VI-NEXT: v_add_f16_sdwa v15, v7, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD7227; VI-NEXT: v_add_f16_e32 v7, 0x200, v77228; VI-NEXT: v_or_b32_e32 v7, v7, v157229; VI-NEXT: v_add_f16_sdwa v15, v6, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD7230; VI-NEXT: v_add_f16_e32 v6, 0x200, v67231; VI-NEXT: v_or_b32_e32 v6, v6, v157232; VI-NEXT: v_add_f16_sdwa v15, v5, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD7233; VI-NEXT: v_add_f16_e32 v5, 0x200, v57234; VI-NEXT: v_or_b32_e32 v5, v5, v157235; VI-NEXT: v_add_f16_sdwa v15, v4, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD7236; VI-NEXT: v_add_f16_e32 v4, 0x200, v47237; VI-NEXT: v_or_b32_e32 v4, v4, v157238; VI-NEXT: v_add_f16_sdwa v15, v3, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD7239; VI-NEXT: v_add_f16_e32 v3, 0x200, v37240; VI-NEXT: v_or_b32_e32 v3, v3, v157241; VI-NEXT: v_add_f16_sdwa v15, v2, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD7242; VI-NEXT: v_add_f16_e32 v2, 0x200, v27243; VI-NEXT: v_or_b32_e32 v2, v2, v157244; VI-NEXT: v_add_f16_sdwa v15, v1, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD7245; VI-NEXT: v_add_f16_e32 v1, 0x200, v17246; VI-NEXT: v_add_f16_sdwa v14, v0, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD7247; VI-NEXT: v_add_f16_e32 v0, 0x200, v07248; VI-NEXT: v_or_b32_e32 v1, v1, v157249; VI-NEXT: v_or_b32_e32 v0, v0, v147250; VI-NEXT: .LBB34_2: ; %end7251; VI-NEXT: s_or_b64 exec, exec, s[4:5]7252; VI-NEXT: s_setpc_b64 s[30:31]7253;7254; GFX9-LABEL: bitcast_v28f16_to_v14f32:7255; GFX9: ; %bb.0:7256; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7257; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v147258; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc7259; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]7260; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]7261; GFX9-NEXT: s_cbranch_execz .LBB34_27262; GFX9-NEXT: ; %bb.1: ; %cmp.true7263; GFX9-NEXT: s_movk_i32 s6, 0x2007264; GFX9-NEXT: v_pk_add_f16 v13, v13, s6 op_sel_hi:[1,0]7265; GFX9-NEXT: v_pk_add_f16 v12, v12, s6 op_sel_hi:[1,0]7266; GFX9-NEXT: v_pk_add_f16 v11, v11, s6 op_sel_hi:[1,0]7267; GFX9-NEXT: v_pk_add_f16 v10, v10, s6 op_sel_hi:[1,0]7268; GFX9-NEXT: v_pk_add_f16 v9, v9, s6 op_sel_hi:[1,0]7269; GFX9-NEXT: v_pk_add_f16 v8, v8, s6 op_sel_hi:[1,0]7270; GFX9-NEXT: v_pk_add_f16 v7, v7, s6 op_sel_hi:[1,0]7271; GFX9-NEXT: v_pk_add_f16 v6, v6, s6 op_sel_hi:[1,0]7272; GFX9-NEXT: v_pk_add_f16 v5, v5, s6 op_sel_hi:[1,0]7273; GFX9-NEXT: v_pk_add_f16 v4, v4, s6 op_sel_hi:[1,0]7274; GFX9-NEXT: v_pk_add_f16 v3, v3, s6 op_sel_hi:[1,0]7275; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]7276; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]7277; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]7278; GFX9-NEXT: .LBB34_2: ; %end7279; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]7280; GFX9-NEXT: s_setpc_b64 s[30:31]7281;7282; GFX11-LABEL: bitcast_v28f16_to_v14f32:7283; GFX11: ; %bb.0:7284; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7285; GFX11-NEXT: s_mov_b32 s0, exec_lo7286; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v147287; GFX11-NEXT: s_xor_b32 s0, exec_lo, s07288; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)7289; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s07290; GFX11-NEXT: s_cbranch_execz .LBB34_27291; GFX11-NEXT: ; %bb.1: ; %cmp.true7292; GFX11-NEXT: v_pk_add_f16 v13, 0x200, v13 op_sel_hi:[0,1]7293; GFX11-NEXT: v_pk_add_f16 v12, 0x200, v12 op_sel_hi:[0,1]7294; GFX11-NEXT: v_pk_add_f16 v11, 0x200, v11 op_sel_hi:[0,1]7295; GFX11-NEXT: v_pk_add_f16 v10, 0x200, v10 op_sel_hi:[0,1]7296; GFX11-NEXT: v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1]7297; GFX11-NEXT: v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1]7298; GFX11-NEXT: v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]7299; GFX11-NEXT: v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]7300; GFX11-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]7301; GFX11-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]7302; GFX11-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]7303; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]7304; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]7305; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]7306; GFX11-NEXT: .LBB34_2: ; %end7307; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s07308; GFX11-NEXT: s_setpc_b64 s[30:31]7309 %cmp = icmp eq i32 %b, 07310 br i1 %cmp, label %cmp.true, label %cmp.false7311 7312cmp.true:7313 %a1 = fadd <28 x half> %a, splat (half 0xH0200)7314 %a2 = bitcast <28 x half> %a1 to <14 x float>7315 br label %end7316 7317cmp.false:7318 %a3 = bitcast <28 x half> %a to <14 x float>7319 br label %end7320 7321end:7322 %phi = phi <14 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]7323 ret <14 x float> %phi7324}7325 7326define inreg <14 x float> @bitcast_v28f16_to_v14f32_scalar(<28 x half> inreg %a, i32 inreg %b) {7327; SI-LABEL: bitcast_v28f16_to_v14f32_scalar:7328; SI: ; %bb.0:7329; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7330; SI-NEXT: v_cvt_f16_f32_e32 v51, s177331; SI-NEXT: v_cvt_f16_f32_e32 v50, s167332; SI-NEXT: v_cvt_f16_f32_e32 v49, s197333; SI-NEXT: v_cvt_f16_f32_e32 v38, s187334; SI-NEXT: v_cvt_f16_f32_e32 v36, s217335; SI-NEXT: v_cvt_f16_f32_e32 v35, s207336; SI-NEXT: v_cvt_f16_f32_e32 v29, v17337; SI-NEXT: v_cvt_f16_f32_e32 v28, v07338; SI-NEXT: v_cvt_f16_f32_e32 v27, v37339; SI-NEXT: v_cvt_f16_f32_e32 v26, v27340; SI-NEXT: v_cvt_f16_f32_e32 v25, v57341; SI-NEXT: v_cvt_f16_f32_e32 v24, v47342; SI-NEXT: v_cvt_f16_f32_e32 v23, v77343; SI-NEXT: v_cvt_f16_f32_e32 v22, v67344; SI-NEXT: v_cvt_f16_f32_e32 v21, v97345; SI-NEXT: v_cvt_f16_f32_e32 v20, v87346; SI-NEXT: v_cvt_f16_f32_e32 v19, v117347; SI-NEXT: v_cvt_f16_f32_e32 v18, v107348; SI-NEXT: v_cvt_f16_f32_e32 v17, v137349; SI-NEXT: v_cvt_f16_f32_e32 v16, v127350; SI-NEXT: v_cvt_f16_f32_e32 v48, s237351; SI-NEXT: v_cvt_f16_f32_e32 v39, s227352; SI-NEXT: v_cvt_f16_f32_e32 v37, s257353; SI-NEXT: v_cvt_f16_f32_e32 v34, s247354; SI-NEXT: v_cvt_f16_f32_e32 v33, s277355; SI-NEXT: v_cvt_f16_f32_e32 v32, s267356; SI-NEXT: v_cvt_f16_f32_e32 v31, s297357; SI-NEXT: v_cvt_f16_f32_e32 v30, s287358; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v147359; SI-NEXT: s_and_b64 s[4:5], vcc, exec7360; SI-NEXT: s_cbranch_scc0 .LBB35_47361; SI-NEXT: ; %bb.1: ; %cmp.false7362; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v517363; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v497364; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v367365; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v487366; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v377367; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v337368; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v317369; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v297370; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v277371; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v257372; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v237373; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v217374; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v197375; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v177376; SI-NEXT: v_or_b32_e32 v0, v50, v07377; SI-NEXT: v_or_b32_e32 v1, v38, v17378; SI-NEXT: v_or_b32_e32 v2, v35, v27379; SI-NEXT: v_or_b32_e32 v3, v39, v37380; SI-NEXT: v_or_b32_e32 v4, v34, v47381; SI-NEXT: v_or_b32_e32 v5, v32, v57382; SI-NEXT: v_or_b32_e32 v6, v30, v67383; SI-NEXT: v_or_b32_e32 v7, v28, v77384; SI-NEXT: v_or_b32_e32 v8, v26, v87385; SI-NEXT: v_or_b32_e32 v9, v24, v97386; SI-NEXT: v_or_b32_e32 v10, v22, v107387; SI-NEXT: v_or_b32_e32 v11, v20, v117388; SI-NEXT: v_or_b32_e32 v12, v18, v127389; SI-NEXT: v_or_b32_e32 v13, v16, v137390; SI-NEXT: s_cbranch_execnz .LBB35_37391; SI-NEXT: .LBB35_2: ; %cmp.true7392; SI-NEXT: v_cvt_f32_f16_e32 v0, v517393; SI-NEXT: v_cvt_f32_f16_e32 v1, v507394; SI-NEXT: v_cvt_f32_f16_e32 v2, v497395; SI-NEXT: v_cvt_f32_f16_e32 v3, v387396; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v07397; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v17398; SI-NEXT: v_cvt_f16_f32_e32 v0, v07399; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v27400; SI-NEXT: v_cvt_f16_f32_e32 v1, v17401; SI-NEXT: v_cvt_f16_f32_e32 v2, v27402; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v07403; SI-NEXT: v_cvt_f32_f16_e32 v4, v357404; SI-NEXT: v_or_b32_e32 v0, v1, v07405; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v27406; SI-NEXT: v_cvt_f32_f16_e32 v2, v367407; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v37408; SI-NEXT: v_cvt_f16_f32_e32 v3, v37409; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v47410; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v27411; SI-NEXT: v_cvt_f16_f32_e32 v2, v27412; SI-NEXT: v_cvt_f16_f32_e32 v4, v47413; SI-NEXT: v_or_b32_e32 v1, v3, v17414; SI-NEXT: v_cvt_f32_f16_e32 v3, v487415; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v27416; SI-NEXT: v_or_b32_e32 v2, v4, v27417; SI-NEXT: v_cvt_f32_f16_e32 v4, v397418; SI-NEXT: v_cvt_f32_f16_e32 v5, v377419; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v37420; SI-NEXT: v_cvt_f16_f32_e32 v3, v37421; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v47422; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v57423; SI-NEXT: v_cvt_f16_f32_e32 v4, v47424; SI-NEXT: v_cvt_f16_f32_e32 v5, v57425; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v37426; SI-NEXT: v_cvt_f32_f16_e32 v6, v347427; SI-NEXT: v_or_b32_e32 v3, v4, v37428; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v57429; SI-NEXT: v_cvt_f32_f16_e32 v5, v337430; SI-NEXT: v_cvt_f32_f16_e32 v7, v327431; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v67432; SI-NEXT: v_cvt_f16_f32_e32 v6, v67433; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v57434; SI-NEXT: v_cvt_f16_f32_e32 v5, v57435; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v77436; SI-NEXT: v_cvt_f16_f32_e32 v7, v77437; SI-NEXT: v_or_b32_e32 v4, v6, v47438; SI-NEXT: v_cvt_f32_f16_e32 v6, v317439; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v57440; SI-NEXT: v_or_b32_e32 v5, v7, v57441; SI-NEXT: v_cvt_f32_f16_e32 v7, v307442; SI-NEXT: v_cvt_f32_f16_e32 v8, v297443; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v67444; SI-NEXT: v_cvt_f16_f32_e32 v6, v67445; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v77446; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v87447; SI-NEXT: v_cvt_f16_f32_e32 v7, v77448; SI-NEXT: v_cvt_f16_f32_e32 v8, v87449; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v67450; SI-NEXT: v_cvt_f32_f16_e32 v9, v287451; SI-NEXT: v_or_b32_e32 v6, v7, v67452; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v87453; SI-NEXT: v_cvt_f32_f16_e32 v8, v277454; SI-NEXT: v_cvt_f32_f16_e32 v10, v267455; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v97456; SI-NEXT: v_cvt_f16_f32_e32 v9, v97457; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v87458; SI-NEXT: v_cvt_f16_f32_e32 v8, v87459; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v107460; SI-NEXT: v_cvt_f16_f32_e32 v10, v107461; SI-NEXT: v_or_b32_e32 v7, v9, v77462; SI-NEXT: v_cvt_f32_f16_e32 v9, v257463; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v87464; SI-NEXT: v_or_b32_e32 v8, v10, v87465; SI-NEXT: v_cvt_f32_f16_e32 v10, v247466; SI-NEXT: v_cvt_f32_f16_e32 v11, v237467; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v97468; SI-NEXT: v_cvt_f16_f32_e32 v9, v97469; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v107470; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v117471; SI-NEXT: v_cvt_f16_f32_e32 v10, v107472; SI-NEXT: v_cvt_f16_f32_e32 v11, v117473; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v97474; SI-NEXT: v_cvt_f32_f16_e32 v12, v227475; SI-NEXT: v_or_b32_e32 v9, v10, v97476; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v117477; SI-NEXT: v_cvt_f32_f16_e32 v11, v217478; SI-NEXT: v_cvt_f32_f16_e32 v13, v207479; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v127480; SI-NEXT: v_cvt_f16_f32_e32 v12, v127481; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v117482; SI-NEXT: v_cvt_f16_f32_e32 v11, v117483; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v137484; SI-NEXT: v_cvt_f16_f32_e32 v13, v137485; SI-NEXT: v_or_b32_e32 v10, v12, v107486; SI-NEXT: v_cvt_f32_f16_e32 v12, v197487; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v117488; SI-NEXT: v_or_b32_e32 v11, v13, v117489; SI-NEXT: v_cvt_f32_f16_e32 v13, v187490; SI-NEXT: v_cvt_f32_f16_e32 v14, v177491; SI-NEXT: v_cvt_f32_f16_e32 v15, v167492; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v127493; SI-NEXT: v_cvt_f16_f32_e32 v12, v127494; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v137495; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v147496; SI-NEXT: v_cvt_f16_f32_e32 v13, v137497; SI-NEXT: v_cvt_f16_f32_e32 v14, v147498; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v157499; SI-NEXT: v_cvt_f16_f32_e32 v15, v157500; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v127501; SI-NEXT: v_or_b32_e32 v12, v13, v127502; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v147503; SI-NEXT: v_or_b32_e32 v13, v15, v137504; SI-NEXT: .LBB35_3: ; %end7505; SI-NEXT: s_setpc_b64 s[30:31]7506; SI-NEXT: .LBB35_4:7507; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr157508; SI-NEXT: s_branch .LBB35_27509;7510; VI-LABEL: bitcast_v28f16_to_v14f32_scalar:7511; VI: ; %bb.0:7512; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7513; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v07514; VI-NEXT: s_and_b64 s[4:5], vcc, exec7515; VI-NEXT: s_cbranch_scc0 .LBB35_37516; VI-NEXT: ; %bb.1: ; %cmp.false7517; VI-NEXT: s_cbranch_execnz .LBB35_47518; VI-NEXT: .LBB35_2: ; %cmp.true7519; VI-NEXT: s_lshr_b32 s4, s29, 167520; VI-NEXT: v_mov_b32_e32 v0, 0x2007521; VI-NEXT: v_mov_b32_e32 v1, s47522; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD7523; VI-NEXT: v_add_f16_e32 v2, s29, v07524; VI-NEXT: s_lshr_b32 s4, s28, 167525; VI-NEXT: v_or_b32_e32 v13, v2, v17526; VI-NEXT: v_mov_b32_e32 v1, s47527; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD7528; VI-NEXT: v_add_f16_e32 v2, s28, v07529; VI-NEXT: s_lshr_b32 s4, s27, 167530; VI-NEXT: v_or_b32_e32 v12, v2, v17531; VI-NEXT: v_mov_b32_e32 v1, s47532; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD7533; VI-NEXT: v_add_f16_e32 v2, s27, v07534; VI-NEXT: s_lshr_b32 s4, s26, 167535; VI-NEXT: v_or_b32_e32 v11, v2, v17536; VI-NEXT: v_mov_b32_e32 v1, s47537; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD7538; VI-NEXT: v_add_f16_e32 v2, s26, v07539; VI-NEXT: s_lshr_b32 s4, s25, 167540; VI-NEXT: v_or_b32_e32 v10, v2, v17541; VI-NEXT: v_mov_b32_e32 v1, s47542; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD7543; VI-NEXT: v_add_f16_e32 v2, s25, v07544; VI-NEXT: s_lshr_b32 s4, s24, 167545; VI-NEXT: v_or_b32_e32 v9, v2, v17546; VI-NEXT: v_mov_b32_e32 v1, s47547; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD7548; VI-NEXT: v_add_f16_e32 v2, s24, v07549; VI-NEXT: s_lshr_b32 s4, s23, 167550; VI-NEXT: v_or_b32_e32 v8, v2, v17551; VI-NEXT: v_mov_b32_e32 v1, s47552; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD7553; VI-NEXT: v_add_f16_e32 v2, s23, v07554; VI-NEXT: s_lshr_b32 s4, s22, 167555; VI-NEXT: v_or_b32_e32 v7, v2, v17556; VI-NEXT: v_mov_b32_e32 v1, s47557; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD7558; VI-NEXT: v_add_f16_e32 v2, s22, v07559; VI-NEXT: s_lshr_b32 s4, s21, 167560; VI-NEXT: v_or_b32_e32 v6, v2, v17561; VI-NEXT: v_mov_b32_e32 v1, s47562; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD7563; VI-NEXT: v_add_f16_e32 v2, s21, v07564; VI-NEXT: s_lshr_b32 s4, s20, 167565; VI-NEXT: v_or_b32_e32 v5, v2, v17566; VI-NEXT: v_mov_b32_e32 v1, s47567; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD7568; VI-NEXT: v_add_f16_e32 v2, s20, v07569; VI-NEXT: s_lshr_b32 s4, s19, 167570; VI-NEXT: v_or_b32_e32 v4, v2, v17571; VI-NEXT: v_mov_b32_e32 v1, s47572; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD7573; VI-NEXT: v_add_f16_e32 v2, s19, v07574; VI-NEXT: s_lshr_b32 s4, s18, 167575; VI-NEXT: v_or_b32_e32 v3, v2, v17576; VI-NEXT: v_mov_b32_e32 v1, s47577; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD7578; VI-NEXT: v_add_f16_e32 v2, s18, v07579; VI-NEXT: s_lshr_b32 s4, s17, 167580; VI-NEXT: v_or_b32_e32 v2, v2, v17581; VI-NEXT: v_mov_b32_e32 v1, s47582; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD7583; VI-NEXT: v_add_f16_e32 v14, s17, v07584; VI-NEXT: s_lshr_b32 s4, s16, 167585; VI-NEXT: v_or_b32_e32 v1, v14, v17586; VI-NEXT: v_mov_b32_e32 v14, s47587; VI-NEXT: v_add_f16_sdwa v14, v14, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD7588; VI-NEXT: v_add_f16_e32 v0, s16, v07589; VI-NEXT: v_or_b32_e32 v0, v0, v147590; VI-NEXT: s_setpc_b64 s[30:31]7591; VI-NEXT: .LBB35_3:7592; VI-NEXT: s_branch .LBB35_27593; VI-NEXT: .LBB35_4:7594; VI-NEXT: v_mov_b32_e32 v0, s167595; VI-NEXT: v_mov_b32_e32 v1, s177596; VI-NEXT: v_mov_b32_e32 v2, s187597; VI-NEXT: v_mov_b32_e32 v3, s197598; VI-NEXT: v_mov_b32_e32 v4, s207599; VI-NEXT: v_mov_b32_e32 v5, s217600; VI-NEXT: v_mov_b32_e32 v6, s227601; VI-NEXT: v_mov_b32_e32 v7, s237602; VI-NEXT: v_mov_b32_e32 v8, s247603; VI-NEXT: v_mov_b32_e32 v9, s257604; VI-NEXT: v_mov_b32_e32 v10, s267605; VI-NEXT: v_mov_b32_e32 v11, s277606; VI-NEXT: v_mov_b32_e32 v12, s287607; VI-NEXT: v_mov_b32_e32 v13, s297608; VI-NEXT: v_mov_b32_e32 v14, s307609; VI-NEXT: v_mov_b32_e32 v15, s317610; VI-NEXT: s_setpc_b64 s[30:31]7611;7612; GFX9-LABEL: bitcast_v28f16_to_v14f32_scalar:7613; GFX9: ; %bb.0:7614; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7615; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v07616; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec7617; GFX9-NEXT: s_cbranch_scc0 .LBB35_37618; GFX9-NEXT: ; %bb.1: ; %cmp.false7619; GFX9-NEXT: s_cbranch_execnz .LBB35_47620; GFX9-NEXT: .LBB35_2: ; %cmp.true7621; GFX9-NEXT: v_mov_b32_e32 v0, 0x2007622; GFX9-NEXT: v_pk_add_f16 v13, s29, v0 op_sel_hi:[1,0]7623; GFX9-NEXT: v_pk_add_f16 v12, s28, v0 op_sel_hi:[1,0]7624; GFX9-NEXT: v_pk_add_f16 v11, s27, v0 op_sel_hi:[1,0]7625; GFX9-NEXT: v_pk_add_f16 v10, s26, v0 op_sel_hi:[1,0]7626; GFX9-NEXT: v_pk_add_f16 v9, s25, v0 op_sel_hi:[1,0]7627; GFX9-NEXT: v_pk_add_f16 v8, s24, v0 op_sel_hi:[1,0]7628; GFX9-NEXT: v_pk_add_f16 v7, s23, v0 op_sel_hi:[1,0]7629; GFX9-NEXT: v_pk_add_f16 v6, s22, v0 op_sel_hi:[1,0]7630; GFX9-NEXT: v_pk_add_f16 v5, s21, v0 op_sel_hi:[1,0]7631; GFX9-NEXT: v_pk_add_f16 v4, s20, v0 op_sel_hi:[1,0]7632; GFX9-NEXT: v_pk_add_f16 v3, s19, v0 op_sel_hi:[1,0]7633; GFX9-NEXT: v_pk_add_f16 v2, s18, v0 op_sel_hi:[1,0]7634; GFX9-NEXT: v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]7635; GFX9-NEXT: v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]7636; GFX9-NEXT: s_setpc_b64 s[30:31]7637; GFX9-NEXT: .LBB35_3:7638; GFX9-NEXT: s_branch .LBB35_27639; GFX9-NEXT: .LBB35_4:7640; GFX9-NEXT: v_mov_b32_e32 v0, s167641; GFX9-NEXT: v_mov_b32_e32 v1, s177642; GFX9-NEXT: v_mov_b32_e32 v2, s187643; GFX9-NEXT: v_mov_b32_e32 v3, s197644; GFX9-NEXT: v_mov_b32_e32 v4, s207645; GFX9-NEXT: v_mov_b32_e32 v5, s217646; GFX9-NEXT: v_mov_b32_e32 v6, s227647; GFX9-NEXT: v_mov_b32_e32 v7, s237648; GFX9-NEXT: v_mov_b32_e32 v8, s247649; GFX9-NEXT: v_mov_b32_e32 v9, s257650; GFX9-NEXT: v_mov_b32_e32 v10, s267651; GFX9-NEXT: v_mov_b32_e32 v11, s277652; GFX9-NEXT: v_mov_b32_e32 v12, s287653; GFX9-NEXT: v_mov_b32_e32 v13, s297654; GFX9-NEXT: v_mov_b32_e32 v14, s307655; GFX9-NEXT: v_mov_b32_e32 v15, s317656; GFX9-NEXT: s_setpc_b64 s[30:31]7657;7658; GFX11-LABEL: bitcast_v28f16_to_v14f32_scalar:7659; GFX11: ; %bb.0:7660; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7661; GFX11-NEXT: s_mov_b32 s15, s37662; GFX11-NEXT: s_mov_b32 s14, s27663; GFX11-NEXT: s_mov_b32 s13, s17664; GFX11-NEXT: s_mov_b32 s12, s07665; GFX11-NEXT: s_cmp_lg_u32 s26, 07666; GFX11-NEXT: s_mov_b32 s0, 07667; GFX11-NEXT: s_cbranch_scc0 .LBB35_37668; GFX11-NEXT: ; %bb.1: ; %Flow7669; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s07670; GFX11-NEXT: s_cbranch_vccnz .LBB35_47671; GFX11-NEXT: .LBB35_2: ; %cmp.true7672; GFX11-NEXT: v_pk_add_f16 v13, 0x200, s25 op_sel_hi:[0,1]7673; GFX11-NEXT: v_pk_add_f16 v12, 0x200, s24 op_sel_hi:[0,1]7674; GFX11-NEXT: v_pk_add_f16 v11, 0x200, s23 op_sel_hi:[0,1]7675; GFX11-NEXT: v_pk_add_f16 v10, 0x200, s22 op_sel_hi:[0,1]7676; GFX11-NEXT: v_pk_add_f16 v9, 0x200, s21 op_sel_hi:[0,1]7677; GFX11-NEXT: v_pk_add_f16 v8, 0x200, s20 op_sel_hi:[0,1]7678; GFX11-NEXT: v_pk_add_f16 v7, 0x200, s19 op_sel_hi:[0,1]7679; GFX11-NEXT: v_pk_add_f16 v6, 0x200, s18 op_sel_hi:[0,1]7680; GFX11-NEXT: v_pk_add_f16 v5, 0x200, s17 op_sel_hi:[0,1]7681; GFX11-NEXT: v_pk_add_f16 v4, 0x200, s16 op_sel_hi:[0,1]7682; GFX11-NEXT: v_pk_add_f16 v3, 0x200, s15 op_sel_hi:[0,1]7683; GFX11-NEXT: v_pk_add_f16 v2, 0x200, s14 op_sel_hi:[0,1]7684; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s13 op_sel_hi:[0,1]7685; GFX11-NEXT: v_pk_add_f16 v0, 0x200, s12 op_sel_hi:[0,1]7686; GFX11-NEXT: s_setpc_b64 s[30:31]7687; GFX11-NEXT: .LBB35_3:7688; GFX11-NEXT: s_branch .LBB35_27689; GFX11-NEXT: .LBB35_4:7690; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s137691; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s157692; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s177693; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s197694; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s217695; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s237696; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s257697; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s277698; GFX11-NEXT: s_setpc_b64 s[30:31]7699 %cmp = icmp eq i32 %b, 07700 br i1 %cmp, label %cmp.true, label %cmp.false7701 7702cmp.true:7703 %a1 = fadd <28 x half> %a, splat (half 0xH0200)7704 %a2 = bitcast <28 x half> %a1 to <14 x float>7705 br label %end7706 7707cmp.false:7708 %a3 = bitcast <28 x half> %a to <14 x float>7709 br label %end7710 7711end:7712 %phi = phi <14 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]7713 ret <14 x float> %phi7714}7715 7716define <7 x double> @bitcast_v7i64_to_v7f64(<7 x i64> %a, i32 %b) {7717; SI-LABEL: bitcast_v7i64_to_v7f64:7718; SI: ; %bb.0:7719; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7720; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v147721; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc7722; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]7723; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]7724; SI-NEXT: s_cbranch_execz .LBB36_27725; SI-NEXT: ; %bb.1: ; %cmp.true7726; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v07727; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc7728; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v27729; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc7730; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v47731; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc7732; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v67733; SI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc7734; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v87735; SI-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc7736; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v107737; SI-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc7738; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v127739; SI-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc7740; SI-NEXT: .LBB36_2: ; %end7741; SI-NEXT: s_or_b64 exec, exec, s[4:5]7742; SI-NEXT: s_setpc_b64 s[30:31]7743;7744; VI-LABEL: bitcast_v7i64_to_v7f64:7745; VI: ; %bb.0:7746; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7747; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v147748; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc7749; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]7750; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]7751; VI-NEXT: s_cbranch_execz .LBB36_27752; VI-NEXT: ; %bb.1: ; %cmp.true7753; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v07754; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc7755; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v27756; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc7757; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v47758; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc7759; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v67760; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc7761; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v87762; VI-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc7763; VI-NEXT: v_add_u32_e32 v10, vcc, 3, v107764; VI-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc7765; VI-NEXT: v_add_u32_e32 v12, vcc, 3, v127766; VI-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc7767; VI-NEXT: .LBB36_2: ; %end7768; VI-NEXT: s_or_b64 exec, exec, s[4:5]7769; VI-NEXT: s_setpc_b64 s[30:31]7770;7771; GFX9-LABEL: bitcast_v7i64_to_v7f64:7772; GFX9: ; %bb.0:7773; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7774; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v147775; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc7776; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]7777; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]7778; GFX9-NEXT: s_cbranch_execz .LBB36_27779; GFX9-NEXT: ; %bb.1: ; %cmp.true7780; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v07781; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc7782; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 3, v27783; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc7784; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, 3, v47785; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc7786; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, 3, v67787; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v7, vcc7788; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, 3, v87789; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v9, vcc7790; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, 3, v107791; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v11, vcc7792; GFX9-NEXT: v_add_co_u32_e32 v12, vcc, 3, v127793; GFX9-NEXT: v_addc_co_u32_e32 v13, vcc, 0, v13, vcc7794; GFX9-NEXT: .LBB36_2: ; %end7795; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]7796; GFX9-NEXT: s_setpc_b64 s[30:31]7797;7798; GFX11-LABEL: bitcast_v7i64_to_v7f64:7799; GFX11: ; %bb.0:7800; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7801; GFX11-NEXT: s_mov_b32 s0, exec_lo7802; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v147803; GFX11-NEXT: s_xor_b32 s0, exec_lo, s07804; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)7805; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s07806; GFX11-NEXT: s_cbranch_execz .LBB36_27807; GFX11-NEXT: ; %bb.1: ; %cmp.true7808; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 37809; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)7810; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo7811; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, 37812; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo7813; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v4, 37814; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)7815; GFX11-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo7816; GFX11-NEXT: v_add_co_u32 v6, vcc_lo, v6, 37817; GFX11-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v7, vcc_lo7818; GFX11-NEXT: v_add_co_u32 v8, vcc_lo, v8, 37819; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)7820; GFX11-NEXT: v_add_co_ci_u32_e64 v9, null, 0, v9, vcc_lo7821; GFX11-NEXT: v_add_co_u32 v10, vcc_lo, v10, 37822; GFX11-NEXT: v_add_co_ci_u32_e64 v11, null, 0, v11, vcc_lo7823; GFX11-NEXT: v_add_co_u32 v12, vcc_lo, v12, 37824; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)7825; GFX11-NEXT: v_add_co_ci_u32_e64 v13, null, 0, v13, vcc_lo7826; GFX11-NEXT: .LBB36_2: ; %end7827; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s07828; GFX11-NEXT: s_setpc_b64 s[30:31]7829 %cmp = icmp eq i32 %b, 07830 br i1 %cmp, label %cmp.true, label %cmp.false7831 7832cmp.true:7833 %a1 = add <7 x i64> %a, splat (i64 3)7834 %a2 = bitcast <7 x i64> %a1 to <7 x double>7835 br label %end7836 7837cmp.false:7838 %a3 = bitcast <7 x i64> %a to <7 x double>7839 br label %end7840 7841end:7842 %phi = phi <7 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]7843 ret <7 x double> %phi7844}7845 7846define inreg <7 x double> @bitcast_v7i64_to_v7f64_scalar(<7 x i64> inreg %a, i32 inreg %b) {7847; SI-LABEL: bitcast_v7i64_to_v7f64_scalar:7848; SI: ; %bb.0:7849; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7850; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v07851; SI-NEXT: s_and_b64 s[4:5], vcc, exec7852; SI-NEXT: s_cbranch_scc0 .LBB37_47853; SI-NEXT: ; %bb.1: ; %cmp.false7854; SI-NEXT: s_cbranch_execnz .LBB37_37855; SI-NEXT: .LBB37_2: ; %cmp.true7856; SI-NEXT: s_add_u32 s16, s16, 37857; SI-NEXT: s_addc_u32 s17, s17, 07858; SI-NEXT: s_add_u32 s18, s18, 37859; SI-NEXT: s_addc_u32 s19, s19, 07860; SI-NEXT: s_add_u32 s20, s20, 37861; SI-NEXT: s_addc_u32 s21, s21, 07862; SI-NEXT: s_add_u32 s22, s22, 37863; SI-NEXT: s_addc_u32 s23, s23, 07864; SI-NEXT: s_add_u32 s24, s24, 37865; SI-NEXT: s_addc_u32 s25, s25, 07866; SI-NEXT: s_add_u32 s26, s26, 37867; SI-NEXT: s_addc_u32 s27, s27, 07868; SI-NEXT: s_add_u32 s28, s28, 37869; SI-NEXT: s_addc_u32 s29, s29, 07870; SI-NEXT: .LBB37_3: ; %end7871; SI-NEXT: v_mov_b32_e32 v0, s167872; SI-NEXT: v_mov_b32_e32 v1, s177873; SI-NEXT: v_mov_b32_e32 v2, s187874; SI-NEXT: v_mov_b32_e32 v3, s197875; SI-NEXT: v_mov_b32_e32 v4, s207876; SI-NEXT: v_mov_b32_e32 v5, s217877; SI-NEXT: v_mov_b32_e32 v6, s227878; SI-NEXT: v_mov_b32_e32 v7, s237879; SI-NEXT: v_mov_b32_e32 v8, s247880; SI-NEXT: v_mov_b32_e32 v9, s257881; SI-NEXT: v_mov_b32_e32 v10, s267882; SI-NEXT: v_mov_b32_e32 v11, s277883; SI-NEXT: v_mov_b32_e32 v12, s287884; SI-NEXT: v_mov_b32_e32 v13, s297885; SI-NEXT: s_setpc_b64 s[30:31]7886; SI-NEXT: .LBB37_4:7887; SI-NEXT: s_branch .LBB37_27888;7889; VI-LABEL: bitcast_v7i64_to_v7f64_scalar:7890; VI: ; %bb.0:7891; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7892; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v07893; VI-NEXT: s_and_b64 s[4:5], vcc, exec7894; VI-NEXT: s_cbranch_scc0 .LBB37_47895; VI-NEXT: ; %bb.1: ; %cmp.false7896; VI-NEXT: s_cbranch_execnz .LBB37_37897; VI-NEXT: .LBB37_2: ; %cmp.true7898; VI-NEXT: s_add_u32 s16, s16, 37899; VI-NEXT: s_addc_u32 s17, s17, 07900; VI-NEXT: s_add_u32 s18, s18, 37901; VI-NEXT: s_addc_u32 s19, s19, 07902; VI-NEXT: s_add_u32 s20, s20, 37903; VI-NEXT: s_addc_u32 s21, s21, 07904; VI-NEXT: s_add_u32 s22, s22, 37905; VI-NEXT: s_addc_u32 s23, s23, 07906; VI-NEXT: s_add_u32 s24, s24, 37907; VI-NEXT: s_addc_u32 s25, s25, 07908; VI-NEXT: s_add_u32 s26, s26, 37909; VI-NEXT: s_addc_u32 s27, s27, 07910; VI-NEXT: s_add_u32 s28, s28, 37911; VI-NEXT: s_addc_u32 s29, s29, 07912; VI-NEXT: .LBB37_3: ; %end7913; VI-NEXT: v_mov_b32_e32 v0, s167914; VI-NEXT: v_mov_b32_e32 v1, s177915; VI-NEXT: v_mov_b32_e32 v2, s187916; VI-NEXT: v_mov_b32_e32 v3, s197917; VI-NEXT: v_mov_b32_e32 v4, s207918; VI-NEXT: v_mov_b32_e32 v5, s217919; VI-NEXT: v_mov_b32_e32 v6, s227920; VI-NEXT: v_mov_b32_e32 v7, s237921; VI-NEXT: v_mov_b32_e32 v8, s247922; VI-NEXT: v_mov_b32_e32 v9, s257923; VI-NEXT: v_mov_b32_e32 v10, s267924; VI-NEXT: v_mov_b32_e32 v11, s277925; VI-NEXT: v_mov_b32_e32 v12, s287926; VI-NEXT: v_mov_b32_e32 v13, s297927; VI-NEXT: s_setpc_b64 s[30:31]7928; VI-NEXT: .LBB37_4:7929; VI-NEXT: s_branch .LBB37_27930;7931; GFX9-LABEL: bitcast_v7i64_to_v7f64_scalar:7932; GFX9: ; %bb.0:7933; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7934; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v07935; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec7936; GFX9-NEXT: s_cbranch_scc0 .LBB37_47937; GFX9-NEXT: ; %bb.1: ; %cmp.false7938; GFX9-NEXT: s_cbranch_execnz .LBB37_37939; GFX9-NEXT: .LBB37_2: ; %cmp.true7940; GFX9-NEXT: s_add_u32 s16, s16, 37941; GFX9-NEXT: s_addc_u32 s17, s17, 07942; GFX9-NEXT: s_add_u32 s18, s18, 37943; GFX9-NEXT: s_addc_u32 s19, s19, 07944; GFX9-NEXT: s_add_u32 s20, s20, 37945; GFX9-NEXT: s_addc_u32 s21, s21, 07946; GFX9-NEXT: s_add_u32 s22, s22, 37947; GFX9-NEXT: s_addc_u32 s23, s23, 07948; GFX9-NEXT: s_add_u32 s24, s24, 37949; GFX9-NEXT: s_addc_u32 s25, s25, 07950; GFX9-NEXT: s_add_u32 s26, s26, 37951; GFX9-NEXT: s_addc_u32 s27, s27, 07952; GFX9-NEXT: s_add_u32 s28, s28, 37953; GFX9-NEXT: s_addc_u32 s29, s29, 07954; GFX9-NEXT: .LBB37_3: ; %end7955; GFX9-NEXT: v_mov_b32_e32 v0, s167956; GFX9-NEXT: v_mov_b32_e32 v1, s177957; GFX9-NEXT: v_mov_b32_e32 v2, s187958; GFX9-NEXT: v_mov_b32_e32 v3, s197959; GFX9-NEXT: v_mov_b32_e32 v4, s207960; GFX9-NEXT: v_mov_b32_e32 v5, s217961; GFX9-NEXT: v_mov_b32_e32 v6, s227962; GFX9-NEXT: v_mov_b32_e32 v7, s237963; GFX9-NEXT: v_mov_b32_e32 v8, s247964; GFX9-NEXT: v_mov_b32_e32 v9, s257965; GFX9-NEXT: v_mov_b32_e32 v10, s267966; GFX9-NEXT: v_mov_b32_e32 v11, s277967; GFX9-NEXT: v_mov_b32_e32 v12, s287968; GFX9-NEXT: v_mov_b32_e32 v13, s297969; GFX9-NEXT: s_setpc_b64 s[30:31]7970; GFX9-NEXT: .LBB37_4:7971; GFX9-NEXT: s_branch .LBB37_27972;7973; GFX11-LABEL: bitcast_v7i64_to_v7f64_scalar:7974; GFX11: ; %bb.0:7975; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7976; GFX11-NEXT: s_cmp_lg_u32 s26, 07977; GFX11-NEXT: s_mov_b32 s4, 07978; GFX11-NEXT: s_cbranch_scc0 .LBB37_47979; GFX11-NEXT: ; %bb.1: ; %Flow7980; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s47981; GFX11-NEXT: s_cbranch_vccnz .LBB37_37982; GFX11-NEXT: .LBB37_2: ; %cmp.true7983; GFX11-NEXT: s_add_u32 s0, s0, 37984; GFX11-NEXT: s_addc_u32 s1, s1, 07985; GFX11-NEXT: s_add_u32 s2, s2, 37986; GFX11-NEXT: s_addc_u32 s3, s3, 07987; GFX11-NEXT: s_add_u32 s16, s16, 37988; GFX11-NEXT: s_addc_u32 s17, s17, 07989; GFX11-NEXT: s_add_u32 s18, s18, 37990; GFX11-NEXT: s_addc_u32 s19, s19, 07991; GFX11-NEXT: s_add_u32 s20, s20, 37992; GFX11-NEXT: s_addc_u32 s21, s21, 07993; GFX11-NEXT: s_add_u32 s22, s22, 37994; GFX11-NEXT: s_addc_u32 s23, s23, 07995; GFX11-NEXT: s_add_u32 s24, s24, 37996; GFX11-NEXT: s_addc_u32 s25, s25, 07997; GFX11-NEXT: .LBB37_3: ; %end7998; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s17999; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s38000; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s178001; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s198002; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s218003; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s238004; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s258005; GFX11-NEXT: s_setpc_b64 s[30:31]8006; GFX11-NEXT: .LBB37_4:8007; GFX11-NEXT: s_branch .LBB37_28008 %cmp = icmp eq i32 %b, 08009 br i1 %cmp, label %cmp.true, label %cmp.false8010 8011cmp.true:8012 %a1 = add <7 x i64> %a, splat (i64 3)8013 %a2 = bitcast <7 x i64> %a1 to <7 x double>8014 br label %end8015 8016cmp.false:8017 %a3 = bitcast <7 x i64> %a to <7 x double>8018 br label %end8019 8020end:8021 %phi = phi <7 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]8022 ret <7 x double> %phi8023}8024 8025define <7 x i64> @bitcast_v7f64_to_v7i64(<7 x double> %a, i32 %b) {8026; SI-LABEL: bitcast_v7f64_to_v7i64:8027; SI: ; %bb.0:8028; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8029; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v148030; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc8031; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]8032; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]8033; SI-NEXT: s_cbranch_execz .LBB38_28034; SI-NEXT: ; %bb.1: ; %cmp.true8035; SI-NEXT: v_add_f64 v[0:1], v[0:1], 1.08036; SI-NEXT: v_add_f64 v[2:3], v[2:3], 1.08037; SI-NEXT: v_add_f64 v[4:5], v[4:5], 1.08038; SI-NEXT: v_add_f64 v[6:7], v[6:7], 1.08039; SI-NEXT: v_add_f64 v[8:9], v[8:9], 1.08040; SI-NEXT: v_add_f64 v[10:11], v[10:11], 1.08041; SI-NEXT: v_add_f64 v[12:13], v[12:13], 1.08042; SI-NEXT: .LBB38_2: ; %end8043; SI-NEXT: s_or_b64 exec, exec, s[4:5]8044; SI-NEXT: s_setpc_b64 s[30:31]8045;8046; VI-LABEL: bitcast_v7f64_to_v7i64:8047; VI: ; %bb.0:8048; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8049; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v148050; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc8051; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]8052; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]8053; VI-NEXT: s_cbranch_execz .LBB38_28054; VI-NEXT: ; %bb.1: ; %cmp.true8055; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.08056; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.08057; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.08058; VI-NEXT: v_add_f64 v[6:7], v[6:7], 1.08059; VI-NEXT: v_add_f64 v[8:9], v[8:9], 1.08060; VI-NEXT: v_add_f64 v[10:11], v[10:11], 1.08061; VI-NEXT: v_add_f64 v[12:13], v[12:13], 1.08062; VI-NEXT: .LBB38_2: ; %end8063; VI-NEXT: s_or_b64 exec, exec, s[4:5]8064; VI-NEXT: s_setpc_b64 s[30:31]8065;8066; GFX9-LABEL: bitcast_v7f64_to_v7i64:8067; GFX9: ; %bb.0:8068; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8069; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v148070; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc8071; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]8072; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]8073; GFX9-NEXT: s_cbranch_execz .LBB38_28074; GFX9-NEXT: ; %bb.1: ; %cmp.true8075; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.08076; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.08077; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.08078; GFX9-NEXT: v_add_f64 v[6:7], v[6:7], 1.08079; GFX9-NEXT: v_add_f64 v[8:9], v[8:9], 1.08080; GFX9-NEXT: v_add_f64 v[10:11], v[10:11], 1.08081; GFX9-NEXT: v_add_f64 v[12:13], v[12:13], 1.08082; GFX9-NEXT: .LBB38_2: ; %end8083; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]8084; GFX9-NEXT: s_setpc_b64 s[30:31]8085;8086; GFX11-LABEL: bitcast_v7f64_to_v7i64:8087; GFX11: ; %bb.0:8088; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8089; GFX11-NEXT: s_mov_b32 s0, exec_lo8090; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v148091; GFX11-NEXT: s_xor_b32 s0, exec_lo, s08092; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)8093; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s08094; GFX11-NEXT: s_cbranch_execz .LBB38_28095; GFX11-NEXT: ; %bb.1: ; %cmp.true8096; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.08097; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.08098; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.08099; GFX11-NEXT: v_add_f64 v[6:7], v[6:7], 1.08100; GFX11-NEXT: v_add_f64 v[8:9], v[8:9], 1.08101; GFX11-NEXT: v_add_f64 v[10:11], v[10:11], 1.08102; GFX11-NEXT: v_add_f64 v[12:13], v[12:13], 1.08103; GFX11-NEXT: .LBB38_2: ; %end8104; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s08105; GFX11-NEXT: s_setpc_b64 s[30:31]8106 %cmp = icmp eq i32 %b, 08107 br i1 %cmp, label %cmp.true, label %cmp.false8108 8109cmp.true:8110 %a1 = fadd <7 x double> %a, splat (double 1.000000e+00)8111 %a2 = bitcast <7 x double> %a1 to <7 x i64>8112 br label %end8113 8114cmp.false:8115 %a3 = bitcast <7 x double> %a to <7 x i64>8116 br label %end8117 8118end:8119 %phi = phi <7 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]8120 ret <7 x i64> %phi8121}8122 8123define inreg <7 x i64> @bitcast_v7f64_to_v7i64_scalar(<7 x double> inreg %a, i32 inreg %b) {8124; SI-LABEL: bitcast_v7f64_to_v7i64_scalar:8125; SI: ; %bb.0:8126; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8127; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v08128; SI-NEXT: s_and_b64 s[4:5], vcc, exec8129; SI-NEXT: s_cbranch_scc0 .LBB39_38130; SI-NEXT: ; %bb.1: ; %cmp.false8131; SI-NEXT: s_cbranch_execnz .LBB39_48132; SI-NEXT: .LBB39_2: ; %cmp.true8133; SI-NEXT: v_add_f64 v[0:1], s[16:17], 1.08134; SI-NEXT: v_add_f64 v[2:3], s[18:19], 1.08135; SI-NEXT: v_add_f64 v[4:5], s[20:21], 1.08136; SI-NEXT: v_add_f64 v[6:7], s[22:23], 1.08137; SI-NEXT: v_add_f64 v[8:9], s[24:25], 1.08138; SI-NEXT: v_add_f64 v[10:11], s[26:27], 1.08139; SI-NEXT: v_add_f64 v[12:13], s[28:29], 1.08140; SI-NEXT: s_setpc_b64 s[30:31]8141; SI-NEXT: .LBB39_3:8142; SI-NEXT: s_branch .LBB39_28143; SI-NEXT: .LBB39_4:8144; SI-NEXT: v_mov_b32_e32 v0, s168145; SI-NEXT: v_mov_b32_e32 v1, s178146; SI-NEXT: v_mov_b32_e32 v2, s188147; SI-NEXT: v_mov_b32_e32 v3, s198148; SI-NEXT: v_mov_b32_e32 v4, s208149; SI-NEXT: v_mov_b32_e32 v5, s218150; SI-NEXT: v_mov_b32_e32 v6, s228151; SI-NEXT: v_mov_b32_e32 v7, s238152; SI-NEXT: v_mov_b32_e32 v8, s248153; SI-NEXT: v_mov_b32_e32 v9, s258154; SI-NEXT: v_mov_b32_e32 v10, s268155; SI-NEXT: v_mov_b32_e32 v11, s278156; SI-NEXT: v_mov_b32_e32 v12, s288157; SI-NEXT: v_mov_b32_e32 v13, s298158; SI-NEXT: v_mov_b32_e32 v14, s308159; SI-NEXT: v_mov_b32_e32 v15, s318160; SI-NEXT: s_setpc_b64 s[30:31]8161;8162; VI-LABEL: bitcast_v7f64_to_v7i64_scalar:8163; VI: ; %bb.0:8164; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8165; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v08166; VI-NEXT: s_and_b64 s[4:5], vcc, exec8167; VI-NEXT: s_cbranch_scc0 .LBB39_38168; VI-NEXT: ; %bb.1: ; %cmp.false8169; VI-NEXT: s_cbranch_execnz .LBB39_48170; VI-NEXT: .LBB39_2: ; %cmp.true8171; VI-NEXT: v_add_f64 v[0:1], s[16:17], 1.08172; VI-NEXT: v_add_f64 v[2:3], s[18:19], 1.08173; VI-NEXT: v_add_f64 v[4:5], s[20:21], 1.08174; VI-NEXT: v_add_f64 v[6:7], s[22:23], 1.08175; VI-NEXT: v_add_f64 v[8:9], s[24:25], 1.08176; VI-NEXT: v_add_f64 v[10:11], s[26:27], 1.08177; VI-NEXT: v_add_f64 v[12:13], s[28:29], 1.08178; VI-NEXT: s_setpc_b64 s[30:31]8179; VI-NEXT: .LBB39_3:8180; VI-NEXT: s_branch .LBB39_28181; VI-NEXT: .LBB39_4:8182; VI-NEXT: v_mov_b32_e32 v0, s168183; VI-NEXT: v_mov_b32_e32 v1, s178184; VI-NEXT: v_mov_b32_e32 v2, s188185; VI-NEXT: v_mov_b32_e32 v3, s198186; VI-NEXT: v_mov_b32_e32 v4, s208187; VI-NEXT: v_mov_b32_e32 v5, s218188; VI-NEXT: v_mov_b32_e32 v6, s228189; VI-NEXT: v_mov_b32_e32 v7, s238190; VI-NEXT: v_mov_b32_e32 v8, s248191; VI-NEXT: v_mov_b32_e32 v9, s258192; VI-NEXT: v_mov_b32_e32 v10, s268193; VI-NEXT: v_mov_b32_e32 v11, s278194; VI-NEXT: v_mov_b32_e32 v12, s288195; VI-NEXT: v_mov_b32_e32 v13, s298196; VI-NEXT: v_mov_b32_e32 v14, s308197; VI-NEXT: v_mov_b32_e32 v15, s318198; VI-NEXT: s_setpc_b64 s[30:31]8199;8200; GFX9-LABEL: bitcast_v7f64_to_v7i64_scalar:8201; GFX9: ; %bb.0:8202; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8203; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v08204; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec8205; GFX9-NEXT: s_cbranch_scc0 .LBB39_38206; GFX9-NEXT: ; %bb.1: ; %cmp.false8207; GFX9-NEXT: s_cbranch_execnz .LBB39_48208; GFX9-NEXT: .LBB39_2: ; %cmp.true8209; GFX9-NEXT: v_add_f64 v[0:1], s[16:17], 1.08210; GFX9-NEXT: v_add_f64 v[2:3], s[18:19], 1.08211; GFX9-NEXT: v_add_f64 v[4:5], s[20:21], 1.08212; GFX9-NEXT: v_add_f64 v[6:7], s[22:23], 1.08213; GFX9-NEXT: v_add_f64 v[8:9], s[24:25], 1.08214; GFX9-NEXT: v_add_f64 v[10:11], s[26:27], 1.08215; GFX9-NEXT: v_add_f64 v[12:13], s[28:29], 1.08216; GFX9-NEXT: s_setpc_b64 s[30:31]8217; GFX9-NEXT: .LBB39_3:8218; GFX9-NEXT: s_branch .LBB39_28219; GFX9-NEXT: .LBB39_4:8220; GFX9-NEXT: v_mov_b32_e32 v0, s168221; GFX9-NEXT: v_mov_b32_e32 v1, s178222; GFX9-NEXT: v_mov_b32_e32 v2, s188223; GFX9-NEXT: v_mov_b32_e32 v3, s198224; GFX9-NEXT: v_mov_b32_e32 v4, s208225; GFX9-NEXT: v_mov_b32_e32 v5, s218226; GFX9-NEXT: v_mov_b32_e32 v6, s228227; GFX9-NEXT: v_mov_b32_e32 v7, s238228; GFX9-NEXT: v_mov_b32_e32 v8, s248229; GFX9-NEXT: v_mov_b32_e32 v9, s258230; GFX9-NEXT: v_mov_b32_e32 v10, s268231; GFX9-NEXT: v_mov_b32_e32 v11, s278232; GFX9-NEXT: v_mov_b32_e32 v12, s288233; GFX9-NEXT: v_mov_b32_e32 v13, s298234; GFX9-NEXT: v_mov_b32_e32 v14, s308235; GFX9-NEXT: v_mov_b32_e32 v15, s318236; GFX9-NEXT: s_setpc_b64 s[30:31]8237;8238; GFX11-LABEL: bitcast_v7f64_to_v7i64_scalar:8239; GFX11: ; %bb.0:8240; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8241; GFX11-NEXT: s_mov_b32 s15, s38242; GFX11-NEXT: s_mov_b32 s14, s28243; GFX11-NEXT: s_mov_b32 s13, s18244; GFX11-NEXT: s_mov_b32 s12, s08245; GFX11-NEXT: s_cmp_lg_u32 s26, 08246; GFX11-NEXT: s_mov_b32 s0, 08247; GFX11-NEXT: s_cbranch_scc0 .LBB39_38248; GFX11-NEXT: ; %bb.1: ; %Flow8249; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s08250; GFX11-NEXT: s_cbranch_vccnz .LBB39_48251; GFX11-NEXT: .LBB39_2: ; %cmp.true8252; GFX11-NEXT: v_add_f64 v[0:1], s[12:13], 1.08253; GFX11-NEXT: v_add_f64 v[2:3], s[14:15], 1.08254; GFX11-NEXT: v_add_f64 v[4:5], s[16:17], 1.08255; GFX11-NEXT: v_add_f64 v[6:7], s[18:19], 1.08256; GFX11-NEXT: v_add_f64 v[8:9], s[20:21], 1.08257; GFX11-NEXT: v_add_f64 v[10:11], s[22:23], 1.08258; GFX11-NEXT: v_add_f64 v[12:13], s[24:25], 1.08259; GFX11-NEXT: s_setpc_b64 s[30:31]8260; GFX11-NEXT: .LBB39_3:8261; GFX11-NEXT: s_branch .LBB39_28262; GFX11-NEXT: .LBB39_4:8263; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s138264; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s158265; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s178266; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s198267; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s218268; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s238269; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s258270; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s278271; GFX11-NEXT: s_setpc_b64 s[30:31]8272 %cmp = icmp eq i32 %b, 08273 br i1 %cmp, label %cmp.true, label %cmp.false8274 8275cmp.true:8276 %a1 = fadd <7 x double> %a, splat (double 1.000000e+00)8277 %a2 = bitcast <7 x double> %a1 to <7 x i64>8278 br label %end8279 8280cmp.false:8281 %a3 = bitcast <7 x double> %a to <7 x i64>8282 br label %end8283 8284end:8285 %phi = phi <7 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]8286 ret <7 x i64> %phi8287}8288 8289define <28 x i16> @bitcast_v7i64_to_v28i16(<7 x i64> %a, i32 %b) {8290; SI-LABEL: bitcast_v7i64_to_v28i16:8291; SI: ; %bb.0:8292; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8293; SI-NEXT: v_mov_b32_e32 v26, v138294; SI-NEXT: v_mov_b32_e32 v24, v128295; SI-NEXT: v_mov_b32_e32 v22, v118296; SI-NEXT: v_mov_b32_e32 v20, v108297; SI-NEXT: v_mov_b32_e32 v18, v98298; SI-NEXT: v_mov_b32_e32 v16, v88299; SI-NEXT: v_mov_b32_e32 v28, v78300; SI-NEXT: v_mov_b32_e32 v12, v68301; SI-NEXT: v_mov_b32_e32 v10, v58302; SI-NEXT: v_mov_b32_e32 v8, v48303; SI-NEXT: v_mov_b32_e32 v6, v38304; SI-NEXT: v_mov_b32_e32 v4, v28305; SI-NEXT: v_mov_b32_e32 v2, v18306; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v148307; SI-NEXT: ; implicit-def: $vgpr18308; SI-NEXT: ; implicit-def: $vgpr38309; SI-NEXT: ; implicit-def: $vgpr58310; SI-NEXT: ; implicit-def: $vgpr78311; SI-NEXT: ; implicit-def: $vgpr98312; SI-NEXT: ; implicit-def: $vgpr118313; SI-NEXT: ; implicit-def: $vgpr138314; SI-NEXT: ; implicit-def: $vgpr158315; SI-NEXT: ; implicit-def: $vgpr178316; SI-NEXT: ; implicit-def: $vgpr198317; SI-NEXT: ; implicit-def: $vgpr218318; SI-NEXT: ; implicit-def: $vgpr238319; SI-NEXT: ; implicit-def: $vgpr258320; SI-NEXT: ; implicit-def: $vgpr278321; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc8322; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]8323; SI-NEXT: s_cbranch_execz .LBB40_28324; SI-NEXT: ; %bb.1: ; %cmp.false8325; SI-NEXT: v_alignbit_b32 v25, v26, v24, 168326; SI-NEXT: v_alignbit_b32 v21, v22, v20, 168327; SI-NEXT: v_alignbit_b32 v17, v18, v16, 168328; SI-NEXT: v_alignbit_b32 v13, v28, v12, 168329; SI-NEXT: v_alignbit_b32 v9, v10, v8, 168330; SI-NEXT: v_alignbit_b32 v5, v6, v4, 168331; SI-NEXT: v_alignbit_b32 v1, v2, v0, 168332; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v268333; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v228334; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v188335; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v288336; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v108337; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v68338; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v28339; SI-NEXT: .LBB40_2: ; %Flow8340; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]8341; SI-NEXT: s_cbranch_execz .LBB40_48342; SI-NEXT: ; %bb.3: ; %cmp.true8343; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v08344; SI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc8345; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v48346; SI-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc8347; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v88348; SI-NEXT: v_addc_u32_e32 v10, vcc, 0, v10, vcc8349; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v128350; SI-NEXT: v_addc_u32_e32 v28, vcc, 0, v28, vcc8351; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v168352; SI-NEXT: v_addc_u32_e32 v18, vcc, 0, v18, vcc8353; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v208354; SI-NEXT: v_addc_u32_e32 v22, vcc, 0, v22, vcc8355; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v248356; SI-NEXT: v_addc_u32_e32 v26, vcc, 0, v26, vcc8357; SI-NEXT: v_alignbit_b32 v25, v26, v24, 168358; SI-NEXT: v_alignbit_b32 v21, v22, v20, 168359; SI-NEXT: v_alignbit_b32 v17, v18, v16, 168360; SI-NEXT: v_alignbit_b32 v13, v28, v12, 168361; SI-NEXT: v_alignbit_b32 v9, v10, v8, 168362; SI-NEXT: v_alignbit_b32 v5, v6, v4, 168363; SI-NEXT: v_alignbit_b32 v1, v2, v0, 168364; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v268365; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v228366; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v188367; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v288368; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v108369; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v68370; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v28371; SI-NEXT: .LBB40_4: ; %end8372; SI-NEXT: s_or_b64 exec, exec, s[4:5]8373; SI-NEXT: v_mov_b32_e32 v14, v288374; SI-NEXT: s_setpc_b64 s[30:31]8375;8376; VI-LABEL: bitcast_v7i64_to_v28i16:8377; VI: ; %bb.0:8378; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8379; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v148380; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc8381; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]8382; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]8383; VI-NEXT: s_cbranch_execz .LBB40_28384; VI-NEXT: ; %bb.1: ; %cmp.true8385; VI-NEXT: v_add_u32_e32 v12, vcc, 3, v128386; VI-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc8387; VI-NEXT: v_add_u32_e32 v10, vcc, 3, v108388; VI-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc8389; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v88390; VI-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc8391; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v68392; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc8393; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v48394; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc8395; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v28396; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc8397; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v08398; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc8399; VI-NEXT: .LBB40_2: ; %end8400; VI-NEXT: s_or_b64 exec, exec, s[4:5]8401; VI-NEXT: s_setpc_b64 s[30:31]8402;8403; GFX9-LABEL: bitcast_v7i64_to_v28i16:8404; GFX9: ; %bb.0:8405; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8406; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v148407; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc8408; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]8409; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]8410; GFX9-NEXT: s_cbranch_execz .LBB40_28411; GFX9-NEXT: ; %bb.1: ; %cmp.true8412; GFX9-NEXT: v_add_co_u32_e32 v12, vcc, 3, v128413; GFX9-NEXT: v_addc_co_u32_e32 v13, vcc, 0, v13, vcc8414; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, 3, v108415; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v11, vcc8416; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, 3, v88417; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v9, vcc8418; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, 3, v68419; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v7, vcc8420; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, 3, v48421; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc8422; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 3, v28423; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc8424; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v08425; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc8426; GFX9-NEXT: .LBB40_2: ; %end8427; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]8428; GFX9-NEXT: s_setpc_b64 s[30:31]8429;8430; GFX11-LABEL: bitcast_v7i64_to_v28i16:8431; GFX11: ; %bb.0:8432; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8433; GFX11-NEXT: s_mov_b32 s0, exec_lo8434; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v148435; GFX11-NEXT: s_xor_b32 s0, exec_lo, s08436; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)8437; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s08438; GFX11-NEXT: s_cbranch_execz .LBB40_28439; GFX11-NEXT: ; %bb.1: ; %cmp.true8440; GFX11-NEXT: v_add_co_u32 v12, vcc_lo, v12, 38441; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)8442; GFX11-NEXT: v_add_co_ci_u32_e64 v13, null, 0, v13, vcc_lo8443; GFX11-NEXT: v_add_co_u32 v10, vcc_lo, v10, 38444; GFX11-NEXT: v_add_co_ci_u32_e64 v11, null, 0, v11, vcc_lo8445; GFX11-NEXT: v_add_co_u32 v8, vcc_lo, v8, 38446; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)8447; GFX11-NEXT: v_add_co_ci_u32_e64 v9, null, 0, v9, vcc_lo8448; GFX11-NEXT: v_add_co_u32 v6, vcc_lo, v6, 38449; GFX11-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v7, vcc_lo8450; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v4, 38451; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)8452; GFX11-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo8453; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, 38454; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo8455; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 38456; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)8457; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo8458; GFX11-NEXT: .LBB40_2: ; %end8459; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s08460; GFX11-NEXT: s_setpc_b64 s[30:31]8461 %cmp = icmp eq i32 %b, 08462 br i1 %cmp, label %cmp.true, label %cmp.false8463 8464cmp.true:8465 %a1 = add <7 x i64> %a, splat (i64 3)8466 %a2 = bitcast <7 x i64> %a1 to <28 x i16>8467 br label %end8468 8469cmp.false:8470 %a3 = bitcast <7 x i64> %a to <28 x i16>8471 br label %end8472 8473end:8474 %phi = phi <28 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]8475 ret <28 x i16> %phi8476}8477 8478define inreg <28 x i16> @bitcast_v7i64_to_v28i16_scalar(<7 x i64> inreg %a, i32 inreg %b) {8479; SI-LABEL: bitcast_v7i64_to_v28i16_scalar:8480; SI: ; %bb.0:8481; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8482; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v08483; SI-NEXT: s_and_b64 s[4:5], vcc, exec8484; SI-NEXT: s_cbranch_scc0 .LBB41_48485; SI-NEXT: ; %bb.1: ; %cmp.false8486; SI-NEXT: s_lshr_b32 s44, s29, 168487; SI-NEXT: s_lshr_b32 s45, s27, 168488; SI-NEXT: s_lshr_b32 s46, s25, 168489; SI-NEXT: s_lshr_b32 s47, s23, 168490; SI-NEXT: s_lshr_b32 s56, s21, 168491; SI-NEXT: s_lshr_b32 s57, s19, 168492; SI-NEXT: s_lshr_b32 s58, s17, 168493; SI-NEXT: s_lshr_b64 s[4:5], s[28:29], 168494; SI-NEXT: s_lshr_b64 s[6:7], s[26:27], 168495; SI-NEXT: s_lshr_b64 s[8:9], s[24:25], 168496; SI-NEXT: s_lshr_b64 s[10:11], s[22:23], 168497; SI-NEXT: s_lshr_b64 s[12:13], s[20:21], 168498; SI-NEXT: s_lshr_b64 s[14:15], s[18:19], 168499; SI-NEXT: s_lshr_b64 s[40:41], s[16:17], 168500; SI-NEXT: s_cbranch_execnz .LBB41_38501; SI-NEXT: .LBB41_2: ; %cmp.true8502; SI-NEXT: s_add_u32 s28, s28, 38503; SI-NEXT: s_addc_u32 s29, s29, 08504; SI-NEXT: s_add_u32 s26, s26, 38505; SI-NEXT: s_addc_u32 s27, s27, 08506; SI-NEXT: s_add_u32 s24, s24, 38507; SI-NEXT: s_addc_u32 s25, s25, 08508; SI-NEXT: s_add_u32 s22, s22, 38509; SI-NEXT: s_addc_u32 s23, s23, 08510; SI-NEXT: s_add_u32 s20, s20, 38511; SI-NEXT: s_addc_u32 s21, s21, 08512; SI-NEXT: s_add_u32 s18, s18, 38513; SI-NEXT: s_addc_u32 s19, s19, 08514; SI-NEXT: s_add_u32 s16, s16, 38515; SI-NEXT: s_addc_u32 s17, s17, 08516; SI-NEXT: s_lshr_b32 s44, s29, 168517; SI-NEXT: s_lshr_b32 s45, s27, 168518; SI-NEXT: s_lshr_b32 s46, s25, 168519; SI-NEXT: s_lshr_b32 s47, s23, 168520; SI-NEXT: s_lshr_b32 s56, s21, 168521; SI-NEXT: s_lshr_b32 s57, s19, 168522; SI-NEXT: s_lshr_b32 s58, s17, 168523; SI-NEXT: s_lshr_b64 s[4:5], s[28:29], 168524; SI-NEXT: s_lshr_b64 s[6:7], s[26:27], 168525; SI-NEXT: s_lshr_b64 s[8:9], s[24:25], 168526; SI-NEXT: s_lshr_b64 s[10:11], s[22:23], 168527; SI-NEXT: s_lshr_b64 s[12:13], s[20:21], 168528; SI-NEXT: s_lshr_b64 s[14:15], s[18:19], 168529; SI-NEXT: s_lshr_b64 s[40:41], s[16:17], 168530; SI-NEXT: .LBB41_3: ; %end8531; SI-NEXT: v_mov_b32_e32 v0, s168532; SI-NEXT: v_mov_b32_e32 v1, s408533; SI-NEXT: v_mov_b32_e32 v2, s178534; SI-NEXT: v_mov_b32_e32 v3, s588535; SI-NEXT: v_mov_b32_e32 v4, s188536; SI-NEXT: v_mov_b32_e32 v5, s148537; SI-NEXT: v_mov_b32_e32 v6, s198538; SI-NEXT: v_mov_b32_e32 v7, s578539; SI-NEXT: v_mov_b32_e32 v8, s208540; SI-NEXT: v_mov_b32_e32 v9, s128541; SI-NEXT: v_mov_b32_e32 v10, s218542; SI-NEXT: v_mov_b32_e32 v11, s568543; SI-NEXT: v_mov_b32_e32 v12, s228544; SI-NEXT: v_mov_b32_e32 v13, s108545; SI-NEXT: v_mov_b32_e32 v14, s238546; SI-NEXT: v_mov_b32_e32 v15, s478547; SI-NEXT: v_mov_b32_e32 v16, s248548; SI-NEXT: v_mov_b32_e32 v17, s88549; SI-NEXT: v_mov_b32_e32 v18, s258550; SI-NEXT: v_mov_b32_e32 v19, s468551; SI-NEXT: v_mov_b32_e32 v20, s268552; SI-NEXT: v_mov_b32_e32 v21, s68553; SI-NEXT: v_mov_b32_e32 v22, s278554; SI-NEXT: v_mov_b32_e32 v23, s458555; SI-NEXT: v_mov_b32_e32 v24, s288556; SI-NEXT: v_mov_b32_e32 v25, s48557; SI-NEXT: v_mov_b32_e32 v26, s298558; SI-NEXT: v_mov_b32_e32 v27, s448559; SI-NEXT: s_setpc_b64 s[30:31]8560; SI-NEXT: .LBB41_4:8561; SI-NEXT: ; implicit-def: $sgpr408562; SI-NEXT: ; implicit-def: $sgpr588563; SI-NEXT: ; implicit-def: $sgpr148564; SI-NEXT: ; implicit-def: $sgpr578565; SI-NEXT: ; implicit-def: $sgpr128566; SI-NEXT: ; implicit-def: $sgpr568567; SI-NEXT: ; implicit-def: $sgpr108568; SI-NEXT: ; implicit-def: $sgpr478569; SI-NEXT: ; implicit-def: $sgpr88570; SI-NEXT: ; implicit-def: $sgpr468571; SI-NEXT: ; implicit-def: $sgpr68572; SI-NEXT: ; implicit-def: $sgpr458573; SI-NEXT: ; implicit-def: $sgpr48574; SI-NEXT: ; implicit-def: $sgpr448575; SI-NEXT: s_branch .LBB41_28576;8577; VI-LABEL: bitcast_v7i64_to_v28i16_scalar:8578; VI: ; %bb.0:8579; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8580; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v08581; VI-NEXT: s_and_b64 s[4:5], vcc, exec8582; VI-NEXT: s_cbranch_scc0 .LBB41_48583; VI-NEXT: ; %bb.1: ; %cmp.false8584; VI-NEXT: s_cbranch_execnz .LBB41_38585; VI-NEXT: .LBB41_2: ; %cmp.true8586; VI-NEXT: s_add_u32 s28, s28, 38587; VI-NEXT: s_addc_u32 s29, s29, 08588; VI-NEXT: s_add_u32 s26, s26, 38589; VI-NEXT: s_addc_u32 s27, s27, 08590; VI-NEXT: s_add_u32 s24, s24, 38591; VI-NEXT: s_addc_u32 s25, s25, 08592; VI-NEXT: s_add_u32 s22, s22, 38593; VI-NEXT: s_addc_u32 s23, s23, 08594; VI-NEXT: s_add_u32 s20, s20, 38595; VI-NEXT: s_addc_u32 s21, s21, 08596; VI-NEXT: s_add_u32 s18, s18, 38597; VI-NEXT: s_addc_u32 s19, s19, 08598; VI-NEXT: s_add_u32 s16, s16, 38599; VI-NEXT: s_addc_u32 s17, s17, 08600; VI-NEXT: .LBB41_3: ; %end8601; VI-NEXT: v_mov_b32_e32 v0, s168602; VI-NEXT: v_mov_b32_e32 v1, s178603; VI-NEXT: v_mov_b32_e32 v2, s188604; VI-NEXT: v_mov_b32_e32 v3, s198605; VI-NEXT: v_mov_b32_e32 v4, s208606; VI-NEXT: v_mov_b32_e32 v5, s218607; VI-NEXT: v_mov_b32_e32 v6, s228608; VI-NEXT: v_mov_b32_e32 v7, s238609; VI-NEXT: v_mov_b32_e32 v8, s248610; VI-NEXT: v_mov_b32_e32 v9, s258611; VI-NEXT: v_mov_b32_e32 v10, s268612; VI-NEXT: v_mov_b32_e32 v11, s278613; VI-NEXT: v_mov_b32_e32 v12, s288614; VI-NEXT: v_mov_b32_e32 v13, s298615; VI-NEXT: s_setpc_b64 s[30:31]8616; VI-NEXT: .LBB41_4:8617; VI-NEXT: s_branch .LBB41_28618;8619; GFX9-LABEL: bitcast_v7i64_to_v28i16_scalar:8620; GFX9: ; %bb.0:8621; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8622; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v08623; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec8624; GFX9-NEXT: s_cbranch_scc0 .LBB41_48625; GFX9-NEXT: ; %bb.1: ; %cmp.false8626; GFX9-NEXT: s_cbranch_execnz .LBB41_38627; GFX9-NEXT: .LBB41_2: ; %cmp.true8628; GFX9-NEXT: s_add_u32 s28, s28, 38629; GFX9-NEXT: s_addc_u32 s29, s29, 08630; GFX9-NEXT: s_add_u32 s26, s26, 38631; GFX9-NEXT: s_addc_u32 s27, s27, 08632; GFX9-NEXT: s_add_u32 s24, s24, 38633; GFX9-NEXT: s_addc_u32 s25, s25, 08634; GFX9-NEXT: s_add_u32 s22, s22, 38635; GFX9-NEXT: s_addc_u32 s23, s23, 08636; GFX9-NEXT: s_add_u32 s20, s20, 38637; GFX9-NEXT: s_addc_u32 s21, s21, 08638; GFX9-NEXT: s_add_u32 s18, s18, 38639; GFX9-NEXT: s_addc_u32 s19, s19, 08640; GFX9-NEXT: s_add_u32 s16, s16, 38641; GFX9-NEXT: s_addc_u32 s17, s17, 08642; GFX9-NEXT: .LBB41_3: ; %end8643; GFX9-NEXT: v_mov_b32_e32 v0, s168644; GFX9-NEXT: v_mov_b32_e32 v1, s178645; GFX9-NEXT: v_mov_b32_e32 v2, s188646; GFX9-NEXT: v_mov_b32_e32 v3, s198647; GFX9-NEXT: v_mov_b32_e32 v4, s208648; GFX9-NEXT: v_mov_b32_e32 v5, s218649; GFX9-NEXT: v_mov_b32_e32 v6, s228650; GFX9-NEXT: v_mov_b32_e32 v7, s238651; GFX9-NEXT: v_mov_b32_e32 v8, s248652; GFX9-NEXT: v_mov_b32_e32 v9, s258653; GFX9-NEXT: v_mov_b32_e32 v10, s268654; GFX9-NEXT: v_mov_b32_e32 v11, s278655; GFX9-NEXT: v_mov_b32_e32 v12, s288656; GFX9-NEXT: v_mov_b32_e32 v13, s298657; GFX9-NEXT: s_setpc_b64 s[30:31]8658; GFX9-NEXT: .LBB41_4:8659; GFX9-NEXT: s_branch .LBB41_28660;8661; GFX11-LABEL: bitcast_v7i64_to_v28i16_scalar:8662; GFX11: ; %bb.0:8663; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8664; GFX11-NEXT: s_cmp_lg_u32 s26, 08665; GFX11-NEXT: s_mov_b32 s4, 08666; GFX11-NEXT: s_cbranch_scc0 .LBB41_48667; GFX11-NEXT: ; %bb.1: ; %Flow8668; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s48669; GFX11-NEXT: s_cbranch_vccnz .LBB41_38670; GFX11-NEXT: .LBB41_2: ; %cmp.true8671; GFX11-NEXT: s_add_u32 s24, s24, 38672; GFX11-NEXT: s_addc_u32 s25, s25, 08673; GFX11-NEXT: s_add_u32 s22, s22, 38674; GFX11-NEXT: s_addc_u32 s23, s23, 08675; GFX11-NEXT: s_add_u32 s20, s20, 38676; GFX11-NEXT: s_addc_u32 s21, s21, 08677; GFX11-NEXT: s_add_u32 s18, s18, 38678; GFX11-NEXT: s_addc_u32 s19, s19, 08679; GFX11-NEXT: s_add_u32 s16, s16, 38680; GFX11-NEXT: s_addc_u32 s17, s17, 08681; GFX11-NEXT: s_add_u32 s2, s2, 38682; GFX11-NEXT: s_addc_u32 s3, s3, 08683; GFX11-NEXT: s_add_u32 s0, s0, 38684; GFX11-NEXT: s_addc_u32 s1, s1, 08685; GFX11-NEXT: .LBB41_3: ; %end8686; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)8687; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s18688; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s38689; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s178690; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s198691; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s218692; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s238693; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s258694; GFX11-NEXT: s_setpc_b64 s[30:31]8695; GFX11-NEXT: .LBB41_4:8696; GFX11-NEXT: s_branch .LBB41_28697 %cmp = icmp eq i32 %b, 08698 br i1 %cmp, label %cmp.true, label %cmp.false8699 8700cmp.true:8701 %a1 = add <7 x i64> %a, splat (i64 3)8702 %a2 = bitcast <7 x i64> %a1 to <28 x i16>8703 br label %end8704 8705cmp.false:8706 %a3 = bitcast <7 x i64> %a to <28 x i16>8707 br label %end8708 8709end:8710 %phi = phi <28 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]8711 ret <28 x i16> %phi8712}8713 8714define <7 x i64> @bitcast_v28i16_to_v7i64(<28 x i16> %a, i32 %b) {8715; SI-LABEL: bitcast_v28i16_to_v7i64:8716; SI: ; %bb.0:8717; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8718; SI-NEXT: v_mov_b32_e32 v36, v148719; SI-NEXT: v_mov_b32_e32 v35, v128720; SI-NEXT: v_mov_b32_e32 v34, v108721; SI-NEXT: v_mov_b32_e32 v33, v88722; SI-NEXT: v_mov_b32_e32 v32, v68723; SI-NEXT: v_mov_b32_e32 v31, v48724; SI-NEXT: v_mov_b32_e32 v30, v28725; SI-NEXT: v_mov_b32_e32 v29, v08726; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v288727; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v18728; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v38729; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v58730; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v78731; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v98732; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v118733; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v138734; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v158735; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v178736; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v198737; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v218738; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v238739; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v258740; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v278741; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr158742; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc8743; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]8744; SI-NEXT: s_cbranch_execnz .LBB42_38745; SI-NEXT: ; %bb.1: ; %Flow8746; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]8747; SI-NEXT: s_cbranch_execnz .LBB42_48748; SI-NEXT: .LBB42_2: ; %end8749; SI-NEXT: s_or_b64 exec, exec, s[4:5]8750; SI-NEXT: s_setpc_b64 s[30:31]8751; SI-NEXT: .LBB42_3: ; %cmp.false8752; SI-NEXT: v_and_b32_e32 v0, 0xffff, v298753; SI-NEXT: v_and_b32_e32 v1, 0xffff, v308754; SI-NEXT: v_and_b32_e32 v2, 0xffff, v318755; SI-NEXT: v_and_b32_e32 v3, 0xffff, v328756; SI-NEXT: v_and_b32_e32 v4, 0xffff, v338757; SI-NEXT: v_and_b32_e32 v5, 0xffff, v348758; SI-NEXT: v_and_b32_e32 v6, 0xffff, v358759; SI-NEXT: v_and_b32_e32 v7, 0xffff, v368760; SI-NEXT: v_and_b32_e32 v8, 0xffff, v168761; SI-NEXT: v_and_b32_e32 v9, 0xffff, v188762; SI-NEXT: v_and_b32_e32 v10, 0xffff, v208763; SI-NEXT: v_and_b32_e32 v11, 0xffff, v228764; SI-NEXT: v_and_b32_e32 v12, 0xffff, v248765; SI-NEXT: v_and_b32_e32 v13, 0xffff, v268766; SI-NEXT: v_or_b32_e32 v0, v0, v548767; SI-NEXT: v_or_b32_e32 v1, v1, v538768; SI-NEXT: v_or_b32_e32 v2, v2, v528769; SI-NEXT: v_or_b32_e32 v3, v3, v518770; SI-NEXT: v_or_b32_e32 v4, v4, v508771; SI-NEXT: v_or_b32_e32 v5, v5, v498772; SI-NEXT: v_or_b32_e32 v6, v6, v488773; SI-NEXT: v_or_b32_e32 v7, v7, v398774; SI-NEXT: v_or_b32_e32 v8, v8, v388775; SI-NEXT: v_or_b32_e32 v9, v9, v378776; SI-NEXT: v_or_b32_e32 v10, v10, v288777; SI-NEXT: v_or_b32_e32 v11, v11, v218778; SI-NEXT: v_or_b32_e32 v12, v12, v198779; SI-NEXT: v_or_b32_e32 v13, v13, v178780; SI-NEXT: ; implicit-def: $vgpr298781; SI-NEXT: ; implicit-def: $vgpr308782; SI-NEXT: ; implicit-def: $vgpr318783; SI-NEXT: ; implicit-def: $vgpr328784; SI-NEXT: ; implicit-def: $vgpr338785; SI-NEXT: ; implicit-def: $vgpr348786; SI-NEXT: ; implicit-def: $vgpr358787; SI-NEXT: ; implicit-def: $vgpr368788; SI-NEXT: ; implicit-def: $vgpr168789; SI-NEXT: ; implicit-def: $vgpr188790; SI-NEXT: ; implicit-def: $vgpr208791; SI-NEXT: ; implicit-def: $vgpr228792; SI-NEXT: ; implicit-def: $vgpr248793; SI-NEXT: ; implicit-def: $vgpr268794; SI-NEXT: ; implicit-def: $vgpr548795; SI-NEXT: ; implicit-def: $vgpr538796; SI-NEXT: ; implicit-def: $vgpr528797; SI-NEXT: ; implicit-def: $vgpr518798; SI-NEXT: ; implicit-def: $vgpr508799; SI-NEXT: ; implicit-def: $vgpr498800; SI-NEXT: ; implicit-def: $vgpr488801; SI-NEXT: ; implicit-def: $vgpr398802; SI-NEXT: ; implicit-def: $vgpr388803; SI-NEXT: ; implicit-def: $vgpr378804; SI-NEXT: ; implicit-def: $vgpr288805; SI-NEXT: ; implicit-def: $vgpr218806; SI-NEXT: ; implicit-def: $vgpr198807; SI-NEXT: ; implicit-def: $vgpr178808; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]8809; SI-NEXT: s_cbranch_execz .LBB42_28810; SI-NEXT: .LBB42_4: ; %cmp.true8811; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v298812; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v308813; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v318814; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v328815; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v338816; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v348817; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v358818; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v368819; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v168820; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v188821; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v208822; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v228823; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v248824; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v268825; SI-NEXT: v_and_b32_e32 v0, 0xffff, v08826; SI-NEXT: v_and_b32_e32 v1, 0xffff, v18827; SI-NEXT: v_and_b32_e32 v2, 0xffff, v28828; SI-NEXT: v_and_b32_e32 v3, 0xffff, v38829; SI-NEXT: v_and_b32_e32 v4, 0xffff, v48830; SI-NEXT: v_and_b32_e32 v5, 0xffff, v58831; SI-NEXT: v_and_b32_e32 v6, 0xffff, v68832; SI-NEXT: v_and_b32_e32 v7, 0xffff, v78833; SI-NEXT: v_and_b32_e32 v8, 0xffff, v88834; SI-NEXT: v_and_b32_e32 v9, 0xffff, v98835; SI-NEXT: v_and_b32_e32 v10, 0xffff, v108836; SI-NEXT: v_and_b32_e32 v11, 0xffff, v118837; SI-NEXT: v_and_b32_e32 v12, 0xffff, v128838; SI-NEXT: v_and_b32_e32 v13, 0xffff, v138839; SI-NEXT: v_or_b32_e32 v0, v54, v08840; SI-NEXT: s_mov_b32 s6, 0x300008841; SI-NEXT: v_or_b32_e32 v1, v53, v18842; SI-NEXT: v_or_b32_e32 v2, v52, v28843; SI-NEXT: v_or_b32_e32 v3, v51, v38844; SI-NEXT: v_or_b32_e32 v4, v50, v48845; SI-NEXT: v_or_b32_e32 v5, v49, v58846; SI-NEXT: v_or_b32_e32 v6, v48, v68847; SI-NEXT: v_or_b32_e32 v7, v39, v78848; SI-NEXT: v_or_b32_e32 v8, v38, v88849; SI-NEXT: v_or_b32_e32 v9, v37, v98850; SI-NEXT: v_or_b32_e32 v10, v28, v108851; SI-NEXT: v_or_b32_e32 v11, v21, v118852; SI-NEXT: v_or_b32_e32 v12, v19, v128853; SI-NEXT: v_or_b32_e32 v13, v17, v138854; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v08855; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v18856; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v28857; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v38858; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v48859; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v58860; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v68861; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v78862; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v88863; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v98864; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v108865; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v118866; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v128867; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v138868; SI-NEXT: s_or_b64 exec, exec, s[4:5]8869; SI-NEXT: s_setpc_b64 s[30:31]8870;8871; VI-LABEL: bitcast_v28i16_to_v7i64:8872; VI: ; %bb.0:8873; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8874; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v148875; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc8876; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]8877; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]8878; VI-NEXT: s_cbranch_execz .LBB42_28879; VI-NEXT: ; %bb.1: ; %cmp.true8880; VI-NEXT: v_mov_b32_e32 v15, 38881; VI-NEXT: v_add_u16_e32 v14, 3, v138882; VI-NEXT: v_add_u16_sdwa v13, v13, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD8883; VI-NEXT: v_or_b32_e32 v13, v14, v138884; VI-NEXT: v_add_u16_e32 v14, 3, v128885; VI-NEXT: v_add_u16_sdwa v12, v12, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD8886; VI-NEXT: v_or_b32_e32 v12, v14, v128887; VI-NEXT: v_add_u16_e32 v14, 3, v118888; VI-NEXT: v_add_u16_sdwa v11, v11, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD8889; VI-NEXT: v_or_b32_e32 v11, v14, v118890; VI-NEXT: v_add_u16_e32 v14, 3, v108891; VI-NEXT: v_add_u16_sdwa v10, v10, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD8892; VI-NEXT: v_or_b32_e32 v10, v14, v108893; VI-NEXT: v_add_u16_e32 v14, 3, v98894; VI-NEXT: v_add_u16_sdwa v9, v9, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD8895; VI-NEXT: v_or_b32_e32 v9, v14, v98896; VI-NEXT: v_add_u16_e32 v14, 3, v88897; VI-NEXT: v_add_u16_sdwa v8, v8, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD8898; VI-NEXT: v_or_b32_e32 v8, v14, v88899; VI-NEXT: v_add_u16_e32 v14, 3, v78900; VI-NEXT: v_add_u16_sdwa v7, v7, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD8901; VI-NEXT: v_or_b32_e32 v7, v14, v78902; VI-NEXT: v_add_u16_e32 v14, 3, v68903; VI-NEXT: v_add_u16_sdwa v6, v6, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD8904; VI-NEXT: v_or_b32_e32 v6, v14, v68905; VI-NEXT: v_add_u16_e32 v14, 3, v58906; VI-NEXT: v_add_u16_sdwa v5, v5, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD8907; VI-NEXT: v_or_b32_e32 v5, v14, v58908; VI-NEXT: v_add_u16_e32 v14, 3, v48909; VI-NEXT: v_add_u16_sdwa v4, v4, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD8910; VI-NEXT: v_or_b32_e32 v4, v14, v48911; VI-NEXT: v_add_u16_e32 v14, 3, v38912; VI-NEXT: v_add_u16_sdwa v3, v3, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD8913; VI-NEXT: v_or_b32_e32 v3, v14, v38914; VI-NEXT: v_add_u16_e32 v14, 3, v28915; VI-NEXT: v_add_u16_sdwa v2, v2, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD8916; VI-NEXT: v_or_b32_e32 v2, v14, v28917; VI-NEXT: v_add_u16_e32 v14, 3, v18918; VI-NEXT: v_add_u16_sdwa v1, v1, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD8919; VI-NEXT: v_or_b32_e32 v1, v14, v18920; VI-NEXT: v_add_u16_e32 v14, 3, v08921; VI-NEXT: v_add_u16_sdwa v0, v0, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD8922; VI-NEXT: v_or_b32_e32 v0, v14, v08923; VI-NEXT: .LBB42_2: ; %end8924; VI-NEXT: s_or_b64 exec, exec, s[4:5]8925; VI-NEXT: s_setpc_b64 s[30:31]8926;8927; GFX9-LABEL: bitcast_v28i16_to_v7i64:8928; GFX9: ; %bb.0:8929; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8930; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v148931; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc8932; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]8933; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]8934; GFX9-NEXT: s_cbranch_execz .LBB42_28935; GFX9-NEXT: ; %bb.1: ; %cmp.true8936; GFX9-NEXT: v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0]8937; GFX9-NEXT: v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0]8938; GFX9-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]8939; GFX9-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]8940; GFX9-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]8941; GFX9-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]8942; GFX9-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]8943; GFX9-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]8944; GFX9-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]8945; GFX9-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]8946; GFX9-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]8947; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]8948; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]8949; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]8950; GFX9-NEXT: .LBB42_2: ; %end8951; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]8952; GFX9-NEXT: s_setpc_b64 s[30:31]8953;8954; GFX11-LABEL: bitcast_v28i16_to_v7i64:8955; GFX11: ; %bb.0:8956; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8957; GFX11-NEXT: s_mov_b32 s0, exec_lo8958; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v148959; GFX11-NEXT: s_xor_b32 s0, exec_lo, s08960; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)8961; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s08962; GFX11-NEXT: s_cbranch_execz .LBB42_28963; GFX11-NEXT: ; %bb.1: ; %cmp.true8964; GFX11-NEXT: v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0]8965; GFX11-NEXT: v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0]8966; GFX11-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]8967; GFX11-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]8968; GFX11-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]8969; GFX11-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]8970; GFX11-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]8971; GFX11-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]8972; GFX11-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]8973; GFX11-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]8974; GFX11-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]8975; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]8976; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]8977; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]8978; GFX11-NEXT: .LBB42_2: ; %end8979; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s08980; GFX11-NEXT: s_setpc_b64 s[30:31]8981 %cmp = icmp eq i32 %b, 08982 br i1 %cmp, label %cmp.true, label %cmp.false8983 8984cmp.true:8985 %a1 = add <28 x i16> %a, splat (i16 3)8986 %a2 = bitcast <28 x i16> %a1 to <7 x i64>8987 br label %end8988 8989cmp.false:8990 %a3 = bitcast <28 x i16> %a to <7 x i64>8991 br label %end8992 8993end:8994 %phi = phi <7 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]8995 ret <7 x i64> %phi8996}8997 8998define inreg <7 x i64> @bitcast_v28i16_to_v7i64_scalar(<28 x i16> inreg %a, i32 inreg %b) {8999; SI-LABEL: bitcast_v28i16_to_v7i64_scalar:9000; SI: ; %bb.0:9001; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9002; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v149003; SI-NEXT: v_mov_b32_e32 v16, v129004; SI-NEXT: v_mov_b32_e32 v17, v109005; SI-NEXT: v_mov_b32_e32 v18, v89006; SI-NEXT: v_mov_b32_e32 v19, v69007; SI-NEXT: v_mov_b32_e32 v20, v49008; SI-NEXT: v_mov_b32_e32 v21, v29009; SI-NEXT: v_mov_b32_e32 v22, v09010; SI-NEXT: s_and_b64 s[4:5], vcc, exec9011; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v19012; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v39013; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v59014; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v79015; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v99016; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v119017; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v139018; SI-NEXT: s_cbranch_scc0 .LBB43_49019; SI-NEXT: ; %bb.1: ; %cmp.false9020; SI-NEXT: s_and_b32 s4, s16, 0xffff9021; SI-NEXT: s_lshl_b32 s5, s17, 169022; SI-NEXT: s_or_b32 s4, s4, s59023; SI-NEXT: s_and_b32 s5, s18, 0xffff9024; SI-NEXT: s_lshl_b32 s6, s19, 169025; SI-NEXT: v_and_b32_e32 v0, 0xffff, v229026; SI-NEXT: s_or_b32 s5, s5, s69027; SI-NEXT: s_and_b32 s6, s20, 0xffff9028; SI-NEXT: s_lshl_b32 s7, s21, 169029; SI-NEXT: v_or_b32_e32 v7, v0, v299030; SI-NEXT: v_and_b32_e32 v0, 0xffff, v209031; SI-NEXT: s_or_b32 s6, s6, s79032; SI-NEXT: s_and_b32 s7, s22, 0xffff9033; SI-NEXT: s_lshl_b32 s8, s23, 169034; SI-NEXT: v_or_b32_e32 v9, v0, v279035; SI-NEXT: v_and_b32_e32 v0, 0xffff, v199036; SI-NEXT: s_or_b32 s7, s7, s89037; SI-NEXT: s_and_b32 s8, s24, 0xffff9038; SI-NEXT: s_lshl_b32 s9, s25, 169039; SI-NEXT: v_or_b32_e32 v10, v0, v269040; SI-NEXT: v_and_b32_e32 v0, 0xffff, v189041; SI-NEXT: s_or_b32 s8, s8, s99042; SI-NEXT: s_and_b32 s9, s26, 0xffff9043; SI-NEXT: s_lshl_b32 s10, s27, 169044; SI-NEXT: v_or_b32_e32 v11, v0, v259045; SI-NEXT: v_and_b32_e32 v0, 0xffff, v179046; SI-NEXT: s_or_b32 s9, s9, s109047; SI-NEXT: s_and_b32 s10, s28, 0xffff9048; SI-NEXT: s_lshl_b32 s11, s29, 169049; SI-NEXT: v_and_b32_e32 v1, 0xffff, v219050; SI-NEXT: v_or_b32_e32 v12, v0, v249051; SI-NEXT: v_and_b32_e32 v0, 0xffff, v169052; SI-NEXT: s_or_b32 s10, s10, s119053; SI-NEXT: v_or_b32_e32 v8, v1, v289054; SI-NEXT: v_or_b32_e32 v13, v0, v239055; SI-NEXT: v_mov_b32_e32 v0, s49056; SI-NEXT: v_mov_b32_e32 v1, s59057; SI-NEXT: v_mov_b32_e32 v2, s69058; SI-NEXT: v_mov_b32_e32 v3, s79059; SI-NEXT: v_mov_b32_e32 v4, s89060; SI-NEXT: v_mov_b32_e32 v5, s99061; SI-NEXT: v_mov_b32_e32 v6, s109062; SI-NEXT: s_cbranch_execnz .LBB43_39063; SI-NEXT: .LBB43_2: ; %cmp.true9064; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v229065; SI-NEXT: v_and_b32_e32 v0, 0xffff, v09066; SI-NEXT: v_or_b32_e32 v0, v29, v09067; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v09068; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v219069; SI-NEXT: v_and_b32_e32 v0, 0xffff, v09070; SI-NEXT: v_or_b32_e32 v0, v28, v09071; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v09072; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v209073; SI-NEXT: v_and_b32_e32 v0, 0xffff, v09074; SI-NEXT: v_or_b32_e32 v0, v27, v09075; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v09076; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v199077; SI-NEXT: v_and_b32_e32 v0, 0xffff, v09078; SI-NEXT: s_add_i32 s16, s16, 39079; SI-NEXT: v_or_b32_e32 v0, v26, v09080; SI-NEXT: s_and_b32 s4, s16, 0xffff9081; SI-NEXT: s_lshl_b32 s5, s17, 169082; SI-NEXT: s_add_i32 s18, s18, 39083; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v09084; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v189085; SI-NEXT: s_or_b32 s4, s5, s49086; SI-NEXT: s_and_b32 s5, s18, 0xffff9087; SI-NEXT: s_lshl_b32 s6, s19, 169088; SI-NEXT: s_add_i32 s20, s20, 39089; SI-NEXT: v_and_b32_e32 v0, 0xffff, v09090; SI-NEXT: s_or_b32 s5, s6, s59091; SI-NEXT: s_and_b32 s6, s20, 0xffff9092; SI-NEXT: s_lshl_b32 s7, s21, 169093; SI-NEXT: s_add_i32 s22, s22, 39094; SI-NEXT: v_or_b32_e32 v0, v25, v09095; SI-NEXT: s_or_b32 s6, s7, s69096; SI-NEXT: s_and_b32 s7, s22, 0xffff9097; SI-NEXT: s_lshl_b32 s8, s23, 169098; SI-NEXT: s_add_i32 s24, s24, 39099; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v09100; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v179101; SI-NEXT: s_or_b32 s7, s8, s79102; SI-NEXT: s_and_b32 s8, s24, 0xffff9103; SI-NEXT: s_lshl_b32 s9, s25, 169104; SI-NEXT: s_add_i32 s26, s26, 39105; SI-NEXT: v_and_b32_e32 v0, 0xffff, v09106; SI-NEXT: s_or_b32 s8, s9, s89107; SI-NEXT: s_and_b32 s9, s26, 0xffff9108; SI-NEXT: s_lshl_b32 s10, s27, 169109; SI-NEXT: s_add_i32 s28, s28, 39110; SI-NEXT: v_or_b32_e32 v0, v24, v09111; SI-NEXT: s_or_b32 s9, s10, s99112; SI-NEXT: s_and_b32 s10, s28, 0xffff9113; SI-NEXT: s_lshl_b32 s11, s29, 169114; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v09115; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v169116; SI-NEXT: s_or_b32 s10, s11, s109117; SI-NEXT: v_and_b32_e32 v0, 0xffff, v09118; SI-NEXT: s_add_i32 s4, s4, 0x300009119; SI-NEXT: s_add_i32 s5, s5, 0x300009120; SI-NEXT: s_add_i32 s6, s6, 0x300009121; SI-NEXT: s_add_i32 s7, s7, 0x300009122; SI-NEXT: s_add_i32 s8, s8, 0x300009123; SI-NEXT: s_add_i32 s9, s9, 0x300009124; SI-NEXT: s_add_i32 s10, s10, 0x300009125; SI-NEXT: v_or_b32_e32 v0, v23, v09126; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v09127; SI-NEXT: v_mov_b32_e32 v0, s49128; SI-NEXT: v_mov_b32_e32 v1, s59129; SI-NEXT: v_mov_b32_e32 v2, s69130; SI-NEXT: v_mov_b32_e32 v3, s79131; SI-NEXT: v_mov_b32_e32 v4, s89132; SI-NEXT: v_mov_b32_e32 v5, s99133; SI-NEXT: v_mov_b32_e32 v6, s109134; SI-NEXT: .LBB43_3: ; %end9135; SI-NEXT: s_setpc_b64 s[30:31]9136; SI-NEXT: .LBB43_4:9137; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr159138; SI-NEXT: s_branch .LBB43_29139;9140; VI-LABEL: bitcast_v28i16_to_v7i64_scalar:9141; VI: ; %bb.0:9142; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9143; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v09144; VI-NEXT: s_and_b64 s[4:5], vcc, exec9145; VI-NEXT: s_cbranch_scc0 .LBB43_49146; VI-NEXT: ; %bb.1: ; %cmp.false9147; VI-NEXT: s_cbranch_execnz .LBB43_39148; VI-NEXT: .LBB43_2: ; %cmp.true9149; VI-NEXT: s_add_i32 s5, s29, 39150; VI-NEXT: s_and_b32 s4, s29, 0xffff00009151; VI-NEXT: s_and_b32 s5, s5, 0xffff9152; VI-NEXT: s_or_b32 s4, s4, s59153; VI-NEXT: s_add_i32 s5, s28, 39154; VI-NEXT: s_add_i32 s29, s4, 0x300009155; VI-NEXT: s_and_b32 s4, s28, 0xffff00009156; VI-NEXT: s_and_b32 s5, s5, 0xffff9157; VI-NEXT: s_or_b32 s4, s4, s59158; VI-NEXT: s_add_i32 s5, s27, 39159; VI-NEXT: s_add_i32 s28, s4, 0x300009160; VI-NEXT: s_and_b32 s4, s27, 0xffff00009161; VI-NEXT: s_and_b32 s5, s5, 0xffff9162; VI-NEXT: s_or_b32 s4, s4, s59163; VI-NEXT: s_add_i32 s5, s26, 39164; VI-NEXT: s_add_i32 s27, s4, 0x300009165; VI-NEXT: s_and_b32 s4, s26, 0xffff00009166; VI-NEXT: s_and_b32 s5, s5, 0xffff9167; VI-NEXT: s_or_b32 s4, s4, s59168; VI-NEXT: s_add_i32 s5, s25, 39169; VI-NEXT: s_add_i32 s26, s4, 0x300009170; VI-NEXT: s_and_b32 s4, s25, 0xffff00009171; VI-NEXT: s_and_b32 s5, s5, 0xffff9172; VI-NEXT: s_or_b32 s4, s4, s59173; VI-NEXT: s_add_i32 s5, s24, 39174; VI-NEXT: s_add_i32 s25, s4, 0x300009175; VI-NEXT: s_and_b32 s4, s24, 0xffff00009176; VI-NEXT: s_and_b32 s5, s5, 0xffff9177; VI-NEXT: s_or_b32 s4, s4, s59178; VI-NEXT: s_add_i32 s5, s23, 39179; VI-NEXT: s_add_i32 s24, s4, 0x300009180; VI-NEXT: s_and_b32 s4, s23, 0xffff00009181; VI-NEXT: s_and_b32 s5, s5, 0xffff9182; VI-NEXT: s_or_b32 s4, s4, s59183; VI-NEXT: s_add_i32 s5, s22, 39184; VI-NEXT: s_add_i32 s23, s4, 0x300009185; VI-NEXT: s_and_b32 s4, s22, 0xffff00009186; VI-NEXT: s_and_b32 s5, s5, 0xffff9187; VI-NEXT: s_or_b32 s4, s4, s59188; VI-NEXT: s_add_i32 s5, s21, 39189; VI-NEXT: s_add_i32 s22, s4, 0x300009190; VI-NEXT: s_and_b32 s4, s21, 0xffff00009191; VI-NEXT: s_and_b32 s5, s5, 0xffff9192; VI-NEXT: s_or_b32 s4, s4, s59193; VI-NEXT: s_add_i32 s5, s20, 39194; VI-NEXT: s_add_i32 s21, s4, 0x300009195; VI-NEXT: s_and_b32 s4, s20, 0xffff00009196; VI-NEXT: s_and_b32 s5, s5, 0xffff9197; VI-NEXT: s_or_b32 s4, s4, s59198; VI-NEXT: s_add_i32 s5, s19, 39199; VI-NEXT: s_add_i32 s20, s4, 0x300009200; VI-NEXT: s_and_b32 s4, s19, 0xffff00009201; VI-NEXT: s_and_b32 s5, s5, 0xffff9202; VI-NEXT: s_or_b32 s4, s4, s59203; VI-NEXT: s_add_i32 s5, s18, 39204; VI-NEXT: s_add_i32 s19, s4, 0x300009205; VI-NEXT: s_and_b32 s4, s18, 0xffff00009206; VI-NEXT: s_and_b32 s5, s5, 0xffff9207; VI-NEXT: s_or_b32 s4, s4, s59208; VI-NEXT: s_add_i32 s5, s17, 39209; VI-NEXT: s_add_i32 s18, s4, 0x300009210; VI-NEXT: s_and_b32 s4, s17, 0xffff00009211; VI-NEXT: s_and_b32 s5, s5, 0xffff9212; VI-NEXT: s_or_b32 s4, s4, s59213; VI-NEXT: s_add_i32 s5, s16, 39214; VI-NEXT: s_add_i32 s17, s4, 0x300009215; VI-NEXT: s_and_b32 s4, s16, 0xffff00009216; VI-NEXT: s_and_b32 s5, s5, 0xffff9217; VI-NEXT: s_or_b32 s4, s4, s59218; VI-NEXT: s_add_i32 s16, s4, 0x300009219; VI-NEXT: .LBB43_3: ; %end9220; VI-NEXT: v_mov_b32_e32 v0, s169221; VI-NEXT: v_mov_b32_e32 v1, s179222; VI-NEXT: v_mov_b32_e32 v2, s189223; VI-NEXT: v_mov_b32_e32 v3, s199224; VI-NEXT: v_mov_b32_e32 v4, s209225; VI-NEXT: v_mov_b32_e32 v5, s219226; VI-NEXT: v_mov_b32_e32 v6, s229227; VI-NEXT: v_mov_b32_e32 v7, s239228; VI-NEXT: v_mov_b32_e32 v8, s249229; VI-NEXT: v_mov_b32_e32 v9, s259230; VI-NEXT: v_mov_b32_e32 v10, s269231; VI-NEXT: v_mov_b32_e32 v11, s279232; VI-NEXT: v_mov_b32_e32 v12, s289233; VI-NEXT: v_mov_b32_e32 v13, s299234; VI-NEXT: s_setpc_b64 s[30:31]9235; VI-NEXT: .LBB43_4:9236; VI-NEXT: s_branch .LBB43_29237;9238; GFX9-LABEL: bitcast_v28i16_to_v7i64_scalar:9239; GFX9: ; %bb.0:9240; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9241; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v09242; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec9243; GFX9-NEXT: s_cbranch_scc0 .LBB43_39244; GFX9-NEXT: ; %bb.1: ; %cmp.false9245; GFX9-NEXT: s_cbranch_execnz .LBB43_49246; GFX9-NEXT: .LBB43_2: ; %cmp.true9247; GFX9-NEXT: v_pk_add_u16 v13, s29, 3 op_sel_hi:[1,0]9248; GFX9-NEXT: v_pk_add_u16 v12, s28, 3 op_sel_hi:[1,0]9249; GFX9-NEXT: v_pk_add_u16 v11, s27, 3 op_sel_hi:[1,0]9250; GFX9-NEXT: v_pk_add_u16 v10, s26, 3 op_sel_hi:[1,0]9251; GFX9-NEXT: v_pk_add_u16 v9, s25, 3 op_sel_hi:[1,0]9252; GFX9-NEXT: v_pk_add_u16 v8, s24, 3 op_sel_hi:[1,0]9253; GFX9-NEXT: v_pk_add_u16 v7, s23, 3 op_sel_hi:[1,0]9254; GFX9-NEXT: v_pk_add_u16 v6, s22, 3 op_sel_hi:[1,0]9255; GFX9-NEXT: v_pk_add_u16 v5, s21, 3 op_sel_hi:[1,0]9256; GFX9-NEXT: v_pk_add_u16 v4, s20, 3 op_sel_hi:[1,0]9257; GFX9-NEXT: v_pk_add_u16 v3, s19, 3 op_sel_hi:[1,0]9258; GFX9-NEXT: v_pk_add_u16 v2, s18, 3 op_sel_hi:[1,0]9259; GFX9-NEXT: v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]9260; GFX9-NEXT: v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]9261; GFX9-NEXT: s_setpc_b64 s[30:31]9262; GFX9-NEXT: .LBB43_3:9263; GFX9-NEXT: s_branch .LBB43_29264; GFX9-NEXT: .LBB43_4:9265; GFX9-NEXT: v_mov_b32_e32 v0, s169266; GFX9-NEXT: v_mov_b32_e32 v1, s179267; GFX9-NEXT: v_mov_b32_e32 v2, s189268; GFX9-NEXT: v_mov_b32_e32 v3, s199269; GFX9-NEXT: v_mov_b32_e32 v4, s209270; GFX9-NEXT: v_mov_b32_e32 v5, s219271; GFX9-NEXT: v_mov_b32_e32 v6, s229272; GFX9-NEXT: v_mov_b32_e32 v7, s239273; GFX9-NEXT: v_mov_b32_e32 v8, s249274; GFX9-NEXT: v_mov_b32_e32 v9, s259275; GFX9-NEXT: v_mov_b32_e32 v10, s269276; GFX9-NEXT: v_mov_b32_e32 v11, s279277; GFX9-NEXT: v_mov_b32_e32 v12, s289278; GFX9-NEXT: v_mov_b32_e32 v13, s299279; GFX9-NEXT: v_mov_b32_e32 v14, s309280; GFX9-NEXT: v_mov_b32_e32 v15, s319281; GFX9-NEXT: s_setpc_b64 s[30:31]9282;9283; GFX11-LABEL: bitcast_v28i16_to_v7i64_scalar:9284; GFX11: ; %bb.0:9285; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9286; GFX11-NEXT: s_mov_b32 s15, s39287; GFX11-NEXT: s_mov_b32 s14, s29288; GFX11-NEXT: s_mov_b32 s13, s19289; GFX11-NEXT: s_mov_b32 s12, s09290; GFX11-NEXT: s_cmp_lg_u32 s26, 09291; GFX11-NEXT: s_mov_b32 s0, 09292; GFX11-NEXT: s_cbranch_scc0 .LBB43_39293; GFX11-NEXT: ; %bb.1: ; %Flow9294; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s09295; GFX11-NEXT: s_cbranch_vccnz .LBB43_49296; GFX11-NEXT: .LBB43_2: ; %cmp.true9297; GFX11-NEXT: v_pk_add_u16 v13, s25, 3 op_sel_hi:[1,0]9298; GFX11-NEXT: v_pk_add_u16 v12, s24, 3 op_sel_hi:[1,0]9299; GFX11-NEXT: v_pk_add_u16 v11, s23, 3 op_sel_hi:[1,0]9300; GFX11-NEXT: v_pk_add_u16 v10, s22, 3 op_sel_hi:[1,0]9301; GFX11-NEXT: v_pk_add_u16 v9, s21, 3 op_sel_hi:[1,0]9302; GFX11-NEXT: v_pk_add_u16 v8, s20, 3 op_sel_hi:[1,0]9303; GFX11-NEXT: v_pk_add_u16 v7, s19, 3 op_sel_hi:[1,0]9304; GFX11-NEXT: v_pk_add_u16 v6, s18, 3 op_sel_hi:[1,0]9305; GFX11-NEXT: v_pk_add_u16 v5, s17, 3 op_sel_hi:[1,0]9306; GFX11-NEXT: v_pk_add_u16 v4, s16, 3 op_sel_hi:[1,0]9307; GFX11-NEXT: v_pk_add_u16 v3, s15, 3 op_sel_hi:[1,0]9308; GFX11-NEXT: v_pk_add_u16 v2, s14, 3 op_sel_hi:[1,0]9309; GFX11-NEXT: v_pk_add_u16 v1, s13, 3 op_sel_hi:[1,0]9310; GFX11-NEXT: v_pk_add_u16 v0, s12, 3 op_sel_hi:[1,0]9311; GFX11-NEXT: s_setpc_b64 s[30:31]9312; GFX11-NEXT: .LBB43_3:9313; GFX11-NEXT: s_branch .LBB43_29314; GFX11-NEXT: .LBB43_4:9315; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s139316; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s159317; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s179318; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s199319; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s219320; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s239321; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s259322; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s279323; GFX11-NEXT: s_setpc_b64 s[30:31]9324 %cmp = icmp eq i32 %b, 09325 br i1 %cmp, label %cmp.true, label %cmp.false9326 9327cmp.true:9328 %a1 = add <28 x i16> %a, splat (i16 3)9329 %a2 = bitcast <28 x i16> %a1 to <7 x i64>9330 br label %end9331 9332cmp.false:9333 %a3 = bitcast <28 x i16> %a to <7 x i64>9334 br label %end9335 9336end:9337 %phi = phi <7 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]9338 ret <7 x i64> %phi9339}9340 9341define <28 x half> @bitcast_v7i64_to_v28f16(<7 x i64> %a, i32 %b) {9342; SI-LABEL: bitcast_v7i64_to_v28f16:9343; SI: ; %bb.0:9344; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9345; SI-NEXT: v_mov_b32_e32 v29, v139346; SI-NEXT: v_mov_b32_e32 v28, v129347; SI-NEXT: v_mov_b32_e32 v31, v119348; SI-NEXT: v_mov_b32_e32 v30, v109349; SI-NEXT: v_mov_b32_e32 v33, v99350; SI-NEXT: v_mov_b32_e32 v32, v89351; SI-NEXT: v_mov_b32_e32 v35, v79352; SI-NEXT: v_mov_b32_e32 v34, v69353; SI-NEXT: v_mov_b32_e32 v37, v59354; SI-NEXT: v_mov_b32_e32 v36, v49355; SI-NEXT: v_mov_b32_e32 v39, v39356; SI-NEXT: v_mov_b32_e32 v38, v29357; SI-NEXT: v_mov_b32_e32 v49, v19358; SI-NEXT: v_mov_b32_e32 v48, v09359; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v149360; SI-NEXT: ; implicit-def: $vgpr09361; SI-NEXT: ; implicit-def: $vgpr19362; SI-NEXT: ; implicit-def: $vgpr29363; SI-NEXT: ; implicit-def: $vgpr39364; SI-NEXT: ; implicit-def: $vgpr49365; SI-NEXT: ; implicit-def: $vgpr59366; SI-NEXT: ; implicit-def: $vgpr69367; SI-NEXT: ; implicit-def: $vgpr79368; SI-NEXT: ; implicit-def: $vgpr89369; SI-NEXT: ; implicit-def: $vgpr99370; SI-NEXT: ; implicit-def: $vgpr109371; SI-NEXT: ; implicit-def: $vgpr119372; SI-NEXT: ; implicit-def: $vgpr129373; SI-NEXT: ; implicit-def: $vgpr139374; SI-NEXT: ; implicit-def: $vgpr149375; SI-NEXT: ; implicit-def: $vgpr159376; SI-NEXT: ; implicit-def: $vgpr169377; SI-NEXT: ; implicit-def: $vgpr179378; SI-NEXT: ; implicit-def: $vgpr189379; SI-NEXT: ; implicit-def: $vgpr199380; SI-NEXT: ; implicit-def: $vgpr209381; SI-NEXT: ; implicit-def: $vgpr219382; SI-NEXT: ; implicit-def: $vgpr229383; SI-NEXT: ; implicit-def: $vgpr239384; SI-NEXT: ; implicit-def: $vgpr249385; SI-NEXT: ; implicit-def: $vgpr259386; SI-NEXT: ; implicit-def: $vgpr269387; SI-NEXT: ; implicit-def: $vgpr279388; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc9389; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]9390; SI-NEXT: s_cbranch_execnz .LBB44_39391; SI-NEXT: ; %bb.1: ; %Flow9392; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]9393; SI-NEXT: s_cbranch_execnz .LBB44_49394; SI-NEXT: .LBB44_2: ; %end9395; SI-NEXT: s_or_b64 exec, exec, s[4:5]9396; SI-NEXT: s_setpc_b64 s[30:31]9397; SI-NEXT: .LBB44_3: ; %cmp.false9398; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v299399; SI-NEXT: v_cvt_f32_f16_e32 v27, v09400; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v289401; SI-NEXT: v_cvt_f32_f16_e32 v25, v09402; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v319403; SI-NEXT: v_cvt_f32_f16_e32 v23, v09404; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v309405; SI-NEXT: v_cvt_f32_f16_e32 v21, v09406; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v339407; SI-NEXT: v_cvt_f32_f16_e32 v19, v09408; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v329409; SI-NEXT: v_cvt_f32_f16_e32 v17, v09410; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v359411; SI-NEXT: v_cvt_f32_f16_e32 v15, v09412; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v349413; SI-NEXT: v_cvt_f32_f16_e32 v13, v09414; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v379415; SI-NEXT: v_cvt_f32_f16_e32 v11, v09416; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v369417; SI-NEXT: v_cvt_f32_f16_e32 v9, v09418; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v399419; SI-NEXT: v_cvt_f32_f16_e32 v7, v09420; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v389421; SI-NEXT: v_cvt_f32_f16_e32 v5, v09422; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v499423; SI-NEXT: v_cvt_f32_f16_e32 v3, v09424; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v489425; SI-NEXT: v_cvt_f32_f16_e32 v1, v09426; SI-NEXT: v_cvt_f32_f16_e32 v26, v299427; SI-NEXT: v_cvt_f32_f16_e32 v24, v289428; SI-NEXT: v_cvt_f32_f16_e32 v22, v319429; SI-NEXT: v_cvt_f32_f16_e32 v20, v309430; SI-NEXT: v_cvt_f32_f16_e32 v18, v339431; SI-NEXT: v_cvt_f32_f16_e32 v16, v329432; SI-NEXT: v_cvt_f32_f16_e32 v14, v359433; SI-NEXT: v_cvt_f32_f16_e32 v12, v349434; SI-NEXT: v_cvt_f32_f16_e32 v10, v379435; SI-NEXT: v_cvt_f32_f16_e32 v8, v369436; SI-NEXT: v_cvt_f32_f16_e32 v6, v399437; SI-NEXT: v_cvt_f32_f16_e32 v4, v389438; SI-NEXT: v_cvt_f32_f16_e32 v2, v499439; SI-NEXT: v_cvt_f32_f16_e32 v0, v489440; SI-NEXT: ; implicit-def: $vgpr489441; SI-NEXT: ; implicit-def: $vgpr499442; SI-NEXT: ; implicit-def: $vgpr389443; SI-NEXT: ; implicit-def: $vgpr399444; SI-NEXT: ; implicit-def: $vgpr369445; SI-NEXT: ; implicit-def: $vgpr379446; SI-NEXT: ; implicit-def: $vgpr349447; SI-NEXT: ; implicit-def: $vgpr359448; SI-NEXT: ; implicit-def: $vgpr329449; SI-NEXT: ; implicit-def: $vgpr339450; SI-NEXT: ; implicit-def: $vgpr309451; SI-NEXT: ; implicit-def: $vgpr319452; SI-NEXT: ; implicit-def: $vgpr289453; SI-NEXT: ; implicit-def: $vgpr299454; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]9455; SI-NEXT: s_cbranch_execz .LBB44_29456; SI-NEXT: .LBB44_4: ; %cmp.true9457; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v489458; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v49, vcc9459; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v389460; SI-NEXT: v_addc_u32_e32 v4, vcc, 0, v39, vcc9461; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v369462; SI-NEXT: v_addc_u32_e32 v8, vcc, 0, v37, vcc9463; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v349464; SI-NEXT: v_addc_u32_e32 v12, vcc, 0, v35, vcc9465; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v329466; SI-NEXT: v_addc_u32_e32 v16, vcc, 0, v33, vcc9467; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v309468; SI-NEXT: v_addc_u32_e32 v20, vcc, 0, v31, vcc9469; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v289470; SI-NEXT: v_addc_u32_e32 v24, vcc, 0, v29, vcc9471; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v09472; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v19473; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v29474; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v49475; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v69476; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v89477; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v109478; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v129479; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v149480; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v169481; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v189482; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v209483; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v229484; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v249485; SI-NEXT: v_cvt_f32_f16_e32 v26, v249486; SI-NEXT: v_cvt_f32_f16_e32 v24, v229487; SI-NEXT: v_cvt_f32_f16_e32 v22, v209488; SI-NEXT: v_cvt_f32_f16_e32 v20, v189489; SI-NEXT: v_cvt_f32_f16_e32 v18, v169490; SI-NEXT: v_cvt_f32_f16_e32 v16, v149491; SI-NEXT: v_cvt_f32_f16_e32 v14, v129492; SI-NEXT: v_cvt_f32_f16_e32 v12, v109493; SI-NEXT: v_cvt_f32_f16_e32 v10, v89494; SI-NEXT: v_cvt_f32_f16_e32 v8, v69495; SI-NEXT: v_cvt_f32_f16_e32 v6, v49496; SI-NEXT: v_cvt_f32_f16_e32 v4, v29497; SI-NEXT: v_cvt_f32_f16_e32 v2, v19498; SI-NEXT: v_cvt_f32_f16_e32 v0, v09499; SI-NEXT: v_cvt_f32_f16_e32 v27, v279500; SI-NEXT: v_cvt_f32_f16_e32 v25, v259501; SI-NEXT: v_cvt_f32_f16_e32 v23, v239502; SI-NEXT: v_cvt_f32_f16_e32 v21, v219503; SI-NEXT: v_cvt_f32_f16_e32 v19, v199504; SI-NEXT: v_cvt_f32_f16_e32 v17, v179505; SI-NEXT: v_cvt_f32_f16_e32 v15, v159506; SI-NEXT: v_cvt_f32_f16_e32 v13, v139507; SI-NEXT: v_cvt_f32_f16_e32 v11, v119508; SI-NEXT: v_cvt_f32_f16_e32 v9, v99509; SI-NEXT: v_cvt_f32_f16_e32 v7, v79510; SI-NEXT: v_cvt_f32_f16_e32 v5, v59511; SI-NEXT: v_cvt_f32_f16_e32 v3, v39512; SI-NEXT: v_cvt_f32_f16_e32 v1, v489513; SI-NEXT: s_or_b64 exec, exec, s[4:5]9514; SI-NEXT: s_setpc_b64 s[30:31]9515;9516; VI-LABEL: bitcast_v7i64_to_v28f16:9517; VI: ; %bb.0:9518; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9519; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v149520; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc9521; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]9522; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]9523; VI-NEXT: s_cbranch_execz .LBB44_29524; VI-NEXT: ; %bb.1: ; %cmp.true9525; VI-NEXT: v_add_u32_e32 v12, vcc, 3, v129526; VI-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc9527; VI-NEXT: v_add_u32_e32 v10, vcc, 3, v109528; VI-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc9529; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v89530; VI-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc9531; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v69532; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc9533; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v49534; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc9535; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v29536; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc9537; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v09538; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc9539; VI-NEXT: .LBB44_2: ; %end9540; VI-NEXT: s_or_b64 exec, exec, s[4:5]9541; VI-NEXT: s_setpc_b64 s[30:31]9542;9543; GFX9-LABEL: bitcast_v7i64_to_v28f16:9544; GFX9: ; %bb.0:9545; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9546; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v149547; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc9548; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]9549; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]9550; GFX9-NEXT: s_cbranch_execz .LBB44_29551; GFX9-NEXT: ; %bb.1: ; %cmp.true9552; GFX9-NEXT: v_add_co_u32_e32 v12, vcc, 3, v129553; GFX9-NEXT: v_addc_co_u32_e32 v13, vcc, 0, v13, vcc9554; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, 3, v109555; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v11, vcc9556; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, 3, v89557; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v9, vcc9558; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, 3, v69559; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v7, vcc9560; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, 3, v49561; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc9562; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 3, v29563; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc9564; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v09565; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc9566; GFX9-NEXT: .LBB44_2: ; %end9567; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]9568; GFX9-NEXT: s_setpc_b64 s[30:31]9569;9570; GFX11-LABEL: bitcast_v7i64_to_v28f16:9571; GFX11: ; %bb.0:9572; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9573; GFX11-NEXT: s_mov_b32 s0, exec_lo9574; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v149575; GFX11-NEXT: s_xor_b32 s0, exec_lo, s09576; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)9577; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s09578; GFX11-NEXT: s_cbranch_execz .LBB44_29579; GFX11-NEXT: ; %bb.1: ; %cmp.true9580; GFX11-NEXT: v_add_co_u32 v12, vcc_lo, v12, 39581; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)9582; GFX11-NEXT: v_add_co_ci_u32_e64 v13, null, 0, v13, vcc_lo9583; GFX11-NEXT: v_add_co_u32 v10, vcc_lo, v10, 39584; GFX11-NEXT: v_add_co_ci_u32_e64 v11, null, 0, v11, vcc_lo9585; GFX11-NEXT: v_add_co_u32 v8, vcc_lo, v8, 39586; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)9587; GFX11-NEXT: v_add_co_ci_u32_e64 v9, null, 0, v9, vcc_lo9588; GFX11-NEXT: v_add_co_u32 v6, vcc_lo, v6, 39589; GFX11-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v7, vcc_lo9590; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v4, 39591; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)9592; GFX11-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo9593; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, 39594; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo9595; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 39596; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)9597; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo9598; GFX11-NEXT: .LBB44_2: ; %end9599; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s09600; GFX11-NEXT: s_setpc_b64 s[30:31]9601 %cmp = icmp eq i32 %b, 09602 br i1 %cmp, label %cmp.true, label %cmp.false9603 9604cmp.true:9605 %a1 = add <7 x i64> %a, splat (i64 3)9606 %a2 = bitcast <7 x i64> %a1 to <28 x half>9607 br label %end9608 9609cmp.false:9610 %a3 = bitcast <7 x i64> %a to <28 x half>9611 br label %end9612 9613end:9614 %phi = phi <28 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]9615 ret <28 x half> %phi9616}9617 9618define inreg <28 x half> @bitcast_v7i64_to_v28f16_scalar(<7 x i64> inreg %a, i32 inreg %b) {9619; SI-LABEL: bitcast_v7i64_to_v28f16_scalar:9620; SI: ; %bb.0:9621; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9622; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v09623; SI-NEXT: s_and_b64 s[4:5], vcc, exec9624; SI-NEXT: s_cbranch_scc0 .LBB45_49625; SI-NEXT: ; %bb.1: ; %cmp.false9626; SI-NEXT: s_lshr_b32 s4, s29, 169627; SI-NEXT: v_cvt_f32_f16_e32 v27, s49628; SI-NEXT: s_lshr_b32 s4, s28, 169629; SI-NEXT: v_cvt_f32_f16_e32 v25, s49630; SI-NEXT: s_lshr_b32 s4, s27, 169631; SI-NEXT: v_cvt_f32_f16_e32 v23, s49632; SI-NEXT: s_lshr_b32 s4, s26, 169633; SI-NEXT: v_cvt_f32_f16_e32 v21, s49634; SI-NEXT: s_lshr_b32 s4, s25, 169635; SI-NEXT: v_cvt_f32_f16_e32 v19, s49636; SI-NEXT: s_lshr_b32 s4, s24, 169637; SI-NEXT: v_cvt_f32_f16_e32 v17, s49638; SI-NEXT: s_lshr_b32 s4, s23, 169639; SI-NEXT: v_cvt_f32_f16_e32 v15, s49640; SI-NEXT: s_lshr_b32 s4, s22, 169641; SI-NEXT: v_cvt_f32_f16_e32 v13, s49642; SI-NEXT: s_lshr_b32 s4, s21, 169643; SI-NEXT: v_cvt_f32_f16_e32 v11, s49644; SI-NEXT: s_lshr_b32 s4, s20, 169645; SI-NEXT: v_cvt_f32_f16_e32 v9, s49646; SI-NEXT: s_lshr_b32 s4, s19, 169647; SI-NEXT: v_cvt_f32_f16_e32 v7, s49648; SI-NEXT: s_lshr_b32 s4, s18, 169649; SI-NEXT: v_cvt_f32_f16_e32 v5, s49650; SI-NEXT: s_lshr_b32 s4, s17, 169651; SI-NEXT: v_cvt_f32_f16_e32 v3, s49652; SI-NEXT: s_lshr_b32 s4, s16, 169653; SI-NEXT: v_cvt_f32_f16_e32 v1, s49654; SI-NEXT: v_cvt_f32_f16_e32 v26, s299655; SI-NEXT: v_cvt_f32_f16_e32 v24, s289656; SI-NEXT: v_cvt_f32_f16_e32 v22, s279657; SI-NEXT: v_cvt_f32_f16_e32 v20, s269658; SI-NEXT: v_cvt_f32_f16_e32 v18, s259659; SI-NEXT: v_cvt_f32_f16_e32 v16, s249660; SI-NEXT: v_cvt_f32_f16_e32 v14, s239661; SI-NEXT: v_cvt_f32_f16_e32 v12, s229662; SI-NEXT: v_cvt_f32_f16_e32 v10, s219663; SI-NEXT: v_cvt_f32_f16_e32 v8, s209664; SI-NEXT: v_cvt_f32_f16_e32 v6, s199665; SI-NEXT: v_cvt_f32_f16_e32 v4, s189666; SI-NEXT: v_cvt_f32_f16_e32 v2, s179667; SI-NEXT: v_cvt_f32_f16_e32 v0, s169668; SI-NEXT: s_cbranch_execnz .LBB45_39669; SI-NEXT: .LBB45_2: ; %cmp.true9670; SI-NEXT: s_add_u32 s4, s16, 39671; SI-NEXT: s_addc_u32 s5, s17, 09672; SI-NEXT: s_lshr_b32 s6, s4, 169673; SI-NEXT: s_lshr_b32 s7, s5, 169674; SI-NEXT: s_add_u32 s8, s18, 39675; SI-NEXT: s_addc_u32 s9, s19, 09676; SI-NEXT: s_lshr_b32 s10, s8, 169677; SI-NEXT: s_lshr_b32 s11, s9, 169678; SI-NEXT: s_add_u32 s12, s20, 39679; SI-NEXT: s_addc_u32 s13, s21, 09680; SI-NEXT: s_lshr_b32 s14, s12, 169681; SI-NEXT: s_lshr_b32 s15, s13, 169682; SI-NEXT: s_add_u32 s16, s22, 39683; SI-NEXT: s_addc_u32 s17, s23, 09684; SI-NEXT: s_lshr_b32 s18, s16, 169685; SI-NEXT: s_lshr_b32 s19, s17, 169686; SI-NEXT: s_add_u32 s20, s24, 39687; SI-NEXT: s_addc_u32 s21, s25, 09688; SI-NEXT: s_lshr_b32 s22, s20, 169689; SI-NEXT: s_lshr_b32 s23, s21, 169690; SI-NEXT: s_add_u32 s24, s26, 39691; SI-NEXT: s_addc_u32 s25, s27, 09692; SI-NEXT: s_lshr_b32 s26, s24, 169693; SI-NEXT: s_lshr_b32 s27, s25, 169694; SI-NEXT: s_add_u32 s28, s28, 39695; SI-NEXT: s_addc_u32 s29, s29, 09696; SI-NEXT: s_lshr_b32 s40, s28, 169697; SI-NEXT: s_lshr_b32 s41, s29, 169698; SI-NEXT: v_cvt_f32_f16_e32 v26, s299699; SI-NEXT: v_cvt_f32_f16_e32 v24, s289700; SI-NEXT: v_cvt_f32_f16_e32 v22, s259701; SI-NEXT: v_cvt_f32_f16_e32 v20, s249702; SI-NEXT: v_cvt_f32_f16_e32 v18, s219703; SI-NEXT: v_cvt_f32_f16_e32 v16, s209704; SI-NEXT: v_cvt_f32_f16_e32 v14, s179705; SI-NEXT: v_cvt_f32_f16_e32 v12, s169706; SI-NEXT: v_cvt_f32_f16_e32 v10, s139707; SI-NEXT: v_cvt_f32_f16_e32 v8, s129708; SI-NEXT: v_cvt_f32_f16_e32 v6, s99709; SI-NEXT: v_cvt_f32_f16_e32 v4, s89710; SI-NEXT: v_cvt_f32_f16_e32 v2, s59711; SI-NEXT: v_cvt_f32_f16_e32 v0, s49712; SI-NEXT: v_cvt_f32_f16_e32 v27, s419713; SI-NEXT: v_cvt_f32_f16_e32 v25, s409714; SI-NEXT: v_cvt_f32_f16_e32 v23, s279715; SI-NEXT: v_cvt_f32_f16_e32 v21, s269716; SI-NEXT: v_cvt_f32_f16_e32 v19, s239717; SI-NEXT: v_cvt_f32_f16_e32 v17, s229718; SI-NEXT: v_cvt_f32_f16_e32 v15, s199719; SI-NEXT: v_cvt_f32_f16_e32 v13, s189720; SI-NEXT: v_cvt_f32_f16_e32 v11, s159721; SI-NEXT: v_cvt_f32_f16_e32 v9, s149722; SI-NEXT: v_cvt_f32_f16_e32 v7, s119723; SI-NEXT: v_cvt_f32_f16_e32 v5, s109724; SI-NEXT: v_cvt_f32_f16_e32 v3, s79725; SI-NEXT: v_cvt_f32_f16_e32 v1, s69726; SI-NEXT: .LBB45_3: ; %end9727; SI-NEXT: s_setpc_b64 s[30:31]9728; SI-NEXT: .LBB45_4:9729; SI-NEXT: ; implicit-def: $vgpr09730; SI-NEXT: ; implicit-def: $vgpr19731; SI-NEXT: ; implicit-def: $vgpr29732; SI-NEXT: ; implicit-def: $vgpr39733; SI-NEXT: ; implicit-def: $vgpr49734; SI-NEXT: ; implicit-def: $vgpr59735; SI-NEXT: ; implicit-def: $vgpr69736; SI-NEXT: ; implicit-def: $vgpr79737; SI-NEXT: ; implicit-def: $vgpr89738; SI-NEXT: ; implicit-def: $vgpr99739; SI-NEXT: ; implicit-def: $vgpr109740; SI-NEXT: ; implicit-def: $vgpr119741; SI-NEXT: ; implicit-def: $vgpr129742; SI-NEXT: ; implicit-def: $vgpr139743; SI-NEXT: ; implicit-def: $vgpr149744; SI-NEXT: ; implicit-def: $vgpr159745; SI-NEXT: ; implicit-def: $vgpr169746; SI-NEXT: ; implicit-def: $vgpr179747; SI-NEXT: ; implicit-def: $vgpr189748; SI-NEXT: ; implicit-def: $vgpr199749; SI-NEXT: ; implicit-def: $vgpr209750; SI-NEXT: ; implicit-def: $vgpr219751; SI-NEXT: ; implicit-def: $vgpr229752; SI-NEXT: ; implicit-def: $vgpr239753; SI-NEXT: ; implicit-def: $vgpr249754; SI-NEXT: ; implicit-def: $vgpr259755; SI-NEXT: ; implicit-def: $vgpr269756; SI-NEXT: ; implicit-def: $vgpr279757; SI-NEXT: s_branch .LBB45_29758;9759; VI-LABEL: bitcast_v7i64_to_v28f16_scalar:9760; VI: ; %bb.0:9761; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9762; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v09763; VI-NEXT: s_and_b64 s[4:5], vcc, exec9764; VI-NEXT: s_cbranch_scc0 .LBB45_49765; VI-NEXT: ; %bb.1: ; %cmp.false9766; VI-NEXT: s_cbranch_execnz .LBB45_39767; VI-NEXT: .LBB45_2: ; %cmp.true9768; VI-NEXT: s_add_u32 s28, s28, 39769; VI-NEXT: s_addc_u32 s29, s29, 09770; VI-NEXT: s_add_u32 s26, s26, 39771; VI-NEXT: s_addc_u32 s27, s27, 09772; VI-NEXT: s_add_u32 s24, s24, 39773; VI-NEXT: s_addc_u32 s25, s25, 09774; VI-NEXT: s_add_u32 s22, s22, 39775; VI-NEXT: s_addc_u32 s23, s23, 09776; VI-NEXT: s_add_u32 s20, s20, 39777; VI-NEXT: s_addc_u32 s21, s21, 09778; VI-NEXT: s_add_u32 s18, s18, 39779; VI-NEXT: s_addc_u32 s19, s19, 09780; VI-NEXT: s_add_u32 s16, s16, 39781; VI-NEXT: s_addc_u32 s17, s17, 09782; VI-NEXT: .LBB45_3: ; %end9783; VI-NEXT: v_mov_b32_e32 v0, s169784; VI-NEXT: v_mov_b32_e32 v1, s179785; VI-NEXT: v_mov_b32_e32 v2, s189786; VI-NEXT: v_mov_b32_e32 v3, s199787; VI-NEXT: v_mov_b32_e32 v4, s209788; VI-NEXT: v_mov_b32_e32 v5, s219789; VI-NEXT: v_mov_b32_e32 v6, s229790; VI-NEXT: v_mov_b32_e32 v7, s239791; VI-NEXT: v_mov_b32_e32 v8, s249792; VI-NEXT: v_mov_b32_e32 v9, s259793; VI-NEXT: v_mov_b32_e32 v10, s269794; VI-NEXT: v_mov_b32_e32 v11, s279795; VI-NEXT: v_mov_b32_e32 v12, s289796; VI-NEXT: v_mov_b32_e32 v13, s299797; VI-NEXT: s_setpc_b64 s[30:31]9798; VI-NEXT: .LBB45_4:9799; VI-NEXT: s_branch .LBB45_29800;9801; GFX9-LABEL: bitcast_v7i64_to_v28f16_scalar:9802; GFX9: ; %bb.0:9803; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9804; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v09805; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec9806; GFX9-NEXT: s_cbranch_scc0 .LBB45_49807; GFX9-NEXT: ; %bb.1: ; %cmp.false9808; GFX9-NEXT: s_cbranch_execnz .LBB45_39809; GFX9-NEXT: .LBB45_2: ; %cmp.true9810; GFX9-NEXT: s_add_u32 s28, s28, 39811; GFX9-NEXT: s_addc_u32 s29, s29, 09812; GFX9-NEXT: s_add_u32 s26, s26, 39813; GFX9-NEXT: s_addc_u32 s27, s27, 09814; GFX9-NEXT: s_add_u32 s24, s24, 39815; GFX9-NEXT: s_addc_u32 s25, s25, 09816; GFX9-NEXT: s_add_u32 s22, s22, 39817; GFX9-NEXT: s_addc_u32 s23, s23, 09818; GFX9-NEXT: s_add_u32 s20, s20, 39819; GFX9-NEXT: s_addc_u32 s21, s21, 09820; GFX9-NEXT: s_add_u32 s18, s18, 39821; GFX9-NEXT: s_addc_u32 s19, s19, 09822; GFX9-NEXT: s_add_u32 s16, s16, 39823; GFX9-NEXT: s_addc_u32 s17, s17, 09824; GFX9-NEXT: .LBB45_3: ; %end9825; GFX9-NEXT: v_mov_b32_e32 v0, s169826; GFX9-NEXT: v_mov_b32_e32 v1, s179827; GFX9-NEXT: v_mov_b32_e32 v2, s189828; GFX9-NEXT: v_mov_b32_e32 v3, s199829; GFX9-NEXT: v_mov_b32_e32 v4, s209830; GFX9-NEXT: v_mov_b32_e32 v5, s219831; GFX9-NEXT: v_mov_b32_e32 v6, s229832; GFX9-NEXT: v_mov_b32_e32 v7, s239833; GFX9-NEXT: v_mov_b32_e32 v8, s249834; GFX9-NEXT: v_mov_b32_e32 v9, s259835; GFX9-NEXT: v_mov_b32_e32 v10, s269836; GFX9-NEXT: v_mov_b32_e32 v11, s279837; GFX9-NEXT: v_mov_b32_e32 v12, s289838; GFX9-NEXT: v_mov_b32_e32 v13, s299839; GFX9-NEXT: s_setpc_b64 s[30:31]9840; GFX9-NEXT: .LBB45_4:9841; GFX9-NEXT: s_branch .LBB45_29842;9843; GFX11-LABEL: bitcast_v7i64_to_v28f16_scalar:9844; GFX11: ; %bb.0:9845; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9846; GFX11-NEXT: s_cmp_lg_u32 s26, 09847; GFX11-NEXT: s_mov_b32 s4, 09848; GFX11-NEXT: s_cbranch_scc0 .LBB45_49849; GFX11-NEXT: ; %bb.1: ; %Flow9850; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s49851; GFX11-NEXT: s_cbranch_vccnz .LBB45_39852; GFX11-NEXT: .LBB45_2: ; %cmp.true9853; GFX11-NEXT: s_add_u32 s24, s24, 39854; GFX11-NEXT: s_addc_u32 s25, s25, 09855; GFX11-NEXT: s_add_u32 s22, s22, 39856; GFX11-NEXT: s_addc_u32 s23, s23, 09857; GFX11-NEXT: s_add_u32 s20, s20, 39858; GFX11-NEXT: s_addc_u32 s21, s21, 09859; GFX11-NEXT: s_add_u32 s18, s18, 39860; GFX11-NEXT: s_addc_u32 s19, s19, 09861; GFX11-NEXT: s_add_u32 s16, s16, 39862; GFX11-NEXT: s_addc_u32 s17, s17, 09863; GFX11-NEXT: s_add_u32 s2, s2, 39864; GFX11-NEXT: s_addc_u32 s3, s3, 09865; GFX11-NEXT: s_add_u32 s0, s0, 39866; GFX11-NEXT: s_addc_u32 s1, s1, 09867; GFX11-NEXT: .LBB45_3: ; %end9868; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)9869; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s19870; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s39871; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s179872; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s199873; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s219874; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s239875; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s259876; GFX11-NEXT: s_setpc_b64 s[30:31]9877; GFX11-NEXT: .LBB45_4:9878; GFX11-NEXT: s_branch .LBB45_29879 %cmp = icmp eq i32 %b, 09880 br i1 %cmp, label %cmp.true, label %cmp.false9881 9882cmp.true:9883 %a1 = add <7 x i64> %a, splat (i64 3)9884 %a2 = bitcast <7 x i64> %a1 to <28 x half>9885 br label %end9886 9887cmp.false:9888 %a3 = bitcast <7 x i64> %a to <28 x half>9889 br label %end9890 9891end:9892 %phi = phi <28 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]9893 ret <28 x half> %phi9894}9895 9896define <7 x i64> @bitcast_v28f16_to_v7i64(<28 x half> %a, i32 %b) {9897; SI-LABEL: bitcast_v28f16_to_v7i64:9898; SI: ; %bb.0:9899; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9900; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill9901; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill9902; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 ; 4-byte Folded Spill9903; SI-NEXT: s_waitcnt expcnt(0)9904; SI-NEXT: v_cvt_f16_f32_e32 v42, v19905; SI-NEXT: v_cvt_f16_f32_e32 v41, v09906; SI-NEXT: v_cvt_f16_f32_e32 v40, v39907; SI-NEXT: v_cvt_f16_f32_e32 v55, v29908; SI-NEXT: v_cvt_f16_f32_e32 v54, v59909; SI-NEXT: v_cvt_f16_f32_e32 v53, v49910; SI-NEXT: v_cvt_f16_f32_e32 v52, v79911; SI-NEXT: v_cvt_f16_f32_e32 v51, v69912; SI-NEXT: v_cvt_f16_f32_e32 v50, v99913; SI-NEXT: v_cvt_f16_f32_e32 v49, v89914; SI-NEXT: v_cvt_f16_f32_e32 v48, v119915; SI-NEXT: v_cvt_f16_f32_e32 v39, v109916; SI-NEXT: v_cvt_f16_f32_e32 v38, v139917; SI-NEXT: v_cvt_f16_f32_e32 v37, v129918; SI-NEXT: v_cvt_f16_f32_e32 v36, v159919; SI-NEXT: v_cvt_f16_f32_e32 v35, v149920; SI-NEXT: v_cvt_f16_f32_e32 v34, v179921; SI-NEXT: v_cvt_f16_f32_e32 v33, v169922; SI-NEXT: v_cvt_f16_f32_e32 v32, v199923; SI-NEXT: v_cvt_f16_f32_e32 v31, v189924; SI-NEXT: v_cvt_f16_f32_e32 v30, v219925; SI-NEXT: v_cvt_f16_f32_e32 v29, v209926; SI-NEXT: v_cvt_f16_f32_e32 v21, v239927; SI-NEXT: v_cvt_f16_f32_e32 v20, v229928; SI-NEXT: v_cvt_f16_f32_e32 v19, v259929; SI-NEXT: v_cvt_f16_f32_e32 v18, v249930; SI-NEXT: v_cvt_f16_f32_e32 v17, v279931; SI-NEXT: v_cvt_f16_f32_e32 v16, v269932; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v289933; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr159934; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc9935; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]9936; SI-NEXT: s_cbranch_execz .LBB46_29937; SI-NEXT: ; %bb.1: ; %cmp.false9938; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v429939; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v409940; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v549941; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v529942; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v509943; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v489944; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v389945; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v369946; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v349947; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v329948; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v309949; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v219950; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v199951; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v179952; SI-NEXT: v_or_b32_e32 v0, v41, v09953; SI-NEXT: v_or_b32_e32 v1, v55, v19954; SI-NEXT: v_or_b32_e32 v2, v53, v29955; SI-NEXT: v_or_b32_e32 v3, v51, v39956; SI-NEXT: v_or_b32_e32 v4, v49, v49957; SI-NEXT: v_or_b32_e32 v5, v39, v59958; SI-NEXT: v_or_b32_e32 v6, v37, v69959; SI-NEXT: v_or_b32_e32 v7, v35, v79960; SI-NEXT: v_or_b32_e32 v8, v33, v89961; SI-NEXT: v_or_b32_e32 v9, v31, v99962; SI-NEXT: v_or_b32_e32 v10, v29, v109963; SI-NEXT: v_or_b32_e32 v11, v20, v119964; SI-NEXT: v_or_b32_e32 v12, v18, v129965; SI-NEXT: v_or_b32_e32 v13, v16, v139966; SI-NEXT: ; implicit-def: $vgpr429967; SI-NEXT: ; implicit-def: $vgpr419968; SI-NEXT: ; implicit-def: $vgpr409969; SI-NEXT: ; implicit-def: $vgpr559970; SI-NEXT: ; implicit-def: $vgpr549971; SI-NEXT: ; implicit-def: $vgpr539972; SI-NEXT: ; implicit-def: $vgpr529973; SI-NEXT: ; implicit-def: $vgpr519974; SI-NEXT: ; implicit-def: $vgpr509975; SI-NEXT: ; implicit-def: $vgpr499976; SI-NEXT: ; implicit-def: $vgpr489977; SI-NEXT: ; implicit-def: $vgpr399978; SI-NEXT: ; implicit-def: $vgpr389979; SI-NEXT: ; implicit-def: $vgpr379980; SI-NEXT: ; implicit-def: $vgpr369981; SI-NEXT: ; implicit-def: $vgpr359982; SI-NEXT: ; implicit-def: $vgpr349983; SI-NEXT: ; implicit-def: $vgpr339984; SI-NEXT: ; implicit-def: $vgpr329985; SI-NEXT: ; implicit-def: $vgpr319986; SI-NEXT: ; implicit-def: $vgpr309987; SI-NEXT: ; implicit-def: $vgpr299988; SI-NEXT: ; implicit-def: $vgpr219989; SI-NEXT: ; implicit-def: $vgpr209990; SI-NEXT: ; implicit-def: $vgpr199991; SI-NEXT: ; implicit-def: $vgpr189992; SI-NEXT: ; implicit-def: $vgpr179993; SI-NEXT: ; implicit-def: $vgpr169994; SI-NEXT: .LBB46_2: ; %Flow9995; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]9996; SI-NEXT: s_cbranch_execz .LBB46_49997; SI-NEXT: ; %bb.3: ; %cmp.true9998; SI-NEXT: v_cvt_f32_f16_e32 v0, v429999; SI-NEXT: v_cvt_f32_f16_e32 v1, v4110000; SI-NEXT: v_cvt_f32_f16_e32 v2, v4010001; SI-NEXT: v_cvt_f32_f16_e32 v3, v5510002; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v010003; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v110004; SI-NEXT: v_cvt_f16_f32_e32 v0, v010005; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v210006; SI-NEXT: v_cvt_f16_f32_e32 v1, v110007; SI-NEXT: v_cvt_f16_f32_e32 v2, v210008; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v010009; SI-NEXT: v_cvt_f32_f16_e32 v4, v5310010; SI-NEXT: v_or_b32_e32 v0, v1, v010011; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v210012; SI-NEXT: v_cvt_f32_f16_e32 v2, v5410013; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v310014; SI-NEXT: v_cvt_f16_f32_e32 v3, v310015; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v410016; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v210017; SI-NEXT: v_cvt_f16_f32_e32 v2, v210018; SI-NEXT: v_cvt_f16_f32_e32 v4, v410019; SI-NEXT: v_or_b32_e32 v1, v3, v110020; SI-NEXT: v_cvt_f32_f16_e32 v3, v5210021; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v210022; SI-NEXT: v_or_b32_e32 v2, v4, v210023; SI-NEXT: v_cvt_f32_f16_e32 v4, v5110024; SI-NEXT: v_cvt_f32_f16_e32 v5, v5010025; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v310026; SI-NEXT: v_cvt_f16_f32_e32 v3, v310027; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v410028; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v510029; SI-NEXT: v_cvt_f16_f32_e32 v4, v410030; SI-NEXT: v_cvt_f16_f32_e32 v5, v510031; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v310032; SI-NEXT: v_cvt_f32_f16_e32 v6, v4910033; SI-NEXT: v_or_b32_e32 v3, v4, v310034; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v510035; SI-NEXT: v_cvt_f32_f16_e32 v5, v4810036; SI-NEXT: v_cvt_f32_f16_e32 v7, v3910037; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v610038; SI-NEXT: v_cvt_f16_f32_e32 v6, v610039; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v510040; SI-NEXT: v_cvt_f16_f32_e32 v5, v510041; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v710042; SI-NEXT: v_cvt_f16_f32_e32 v7, v710043; SI-NEXT: v_or_b32_e32 v4, v6, v410044; SI-NEXT: v_cvt_f32_f16_e32 v6, v3810045; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v510046; SI-NEXT: v_or_b32_e32 v5, v7, v510047; SI-NEXT: v_cvt_f32_f16_e32 v7, v3710048; SI-NEXT: v_cvt_f32_f16_e32 v8, v3610049; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v610050; SI-NEXT: v_cvt_f16_f32_e32 v6, v610051; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v710052; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v810053; SI-NEXT: v_cvt_f16_f32_e32 v7, v710054; SI-NEXT: v_cvt_f16_f32_e32 v8, v810055; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v610056; SI-NEXT: v_cvt_f32_f16_e32 v9, v3510057; SI-NEXT: v_or_b32_e32 v6, v7, v610058; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v810059; SI-NEXT: v_cvt_f32_f16_e32 v8, v3410060; SI-NEXT: v_cvt_f32_f16_e32 v10, v3310061; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v910062; SI-NEXT: v_cvt_f16_f32_e32 v9, v910063; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v810064; SI-NEXT: v_cvt_f16_f32_e32 v8, v810065; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v1010066; SI-NEXT: v_cvt_f16_f32_e32 v10, v1010067; SI-NEXT: v_or_b32_e32 v7, v9, v710068; SI-NEXT: v_cvt_f32_f16_e32 v9, v3210069; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v810070; SI-NEXT: v_or_b32_e32 v8, v10, v810071; SI-NEXT: v_cvt_f32_f16_e32 v10, v3110072; SI-NEXT: v_cvt_f32_f16_e32 v11, v3010073; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v910074; SI-NEXT: v_cvt_f16_f32_e32 v9, v910075; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v1010076; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v1110077; SI-NEXT: v_cvt_f16_f32_e32 v10, v1010078; SI-NEXT: v_cvt_f16_f32_e32 v11, v1110079; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v910080; SI-NEXT: v_cvt_f32_f16_e32 v12, v2910081; SI-NEXT: v_or_b32_e32 v9, v10, v910082; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v1110083; SI-NEXT: v_cvt_f32_f16_e32 v11, v2110084; SI-NEXT: v_cvt_f32_f16_e32 v13, v2010085; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v1210086; SI-NEXT: v_cvt_f16_f32_e32 v12, v1210087; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v1110088; SI-NEXT: v_cvt_f16_f32_e32 v11, v1110089; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v1310090; SI-NEXT: v_cvt_f16_f32_e32 v13, v1310091; SI-NEXT: v_or_b32_e32 v10, v12, v1010092; SI-NEXT: v_cvt_f32_f16_e32 v12, v1910093; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v1110094; SI-NEXT: v_or_b32_e32 v11, v13, v1110095; SI-NEXT: v_cvt_f32_f16_e32 v13, v1810096; SI-NEXT: v_cvt_f32_f16_e32 v14, v1710097; SI-NEXT: v_cvt_f32_f16_e32 v15, v1610098; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v1210099; SI-NEXT: v_cvt_f16_f32_e32 v12, v1210100; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v1310101; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v1410102; SI-NEXT: v_cvt_f16_f32_e32 v13, v1310103; SI-NEXT: v_cvt_f16_f32_e32 v14, v1410104; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v1510105; SI-NEXT: v_cvt_f16_f32_e32 v15, v1510106; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v1210107; SI-NEXT: v_or_b32_e32 v12, v13, v1210108; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v1410109; SI-NEXT: v_or_b32_e32 v13, v15, v1310110; SI-NEXT: .LBB46_4: ; %end10111; SI-NEXT: s_or_b64 exec, exec, s[4:5]10112; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 ; 4-byte Folded Reload10113; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload10114; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload10115; SI-NEXT: s_waitcnt vmcnt(0)10116; SI-NEXT: s_setpc_b64 s[30:31]10117;10118; VI-LABEL: bitcast_v28f16_to_v7i64:10119; VI: ; %bb.0:10120; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10121; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1410122; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc10123; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]10124; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]10125; VI-NEXT: s_cbranch_execz .LBB46_210126; VI-NEXT: ; %bb.1: ; %cmp.true10127; VI-NEXT: v_mov_b32_e32 v14, 0x20010128; VI-NEXT: v_add_f16_sdwa v15, v13, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD10129; VI-NEXT: v_add_f16_e32 v13, 0x200, v1310130; VI-NEXT: v_or_b32_e32 v13, v13, v1510131; VI-NEXT: v_add_f16_sdwa v15, v12, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD10132; VI-NEXT: v_add_f16_e32 v12, 0x200, v1210133; VI-NEXT: v_or_b32_e32 v12, v12, v1510134; VI-NEXT: v_add_f16_sdwa v15, v11, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD10135; VI-NEXT: v_add_f16_e32 v11, 0x200, v1110136; VI-NEXT: v_or_b32_e32 v11, v11, v1510137; VI-NEXT: v_add_f16_sdwa v15, v10, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD10138; VI-NEXT: v_add_f16_e32 v10, 0x200, v1010139; VI-NEXT: v_or_b32_e32 v10, v10, v1510140; VI-NEXT: v_add_f16_sdwa v15, v9, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD10141; VI-NEXT: v_add_f16_e32 v9, 0x200, v910142; VI-NEXT: v_or_b32_e32 v9, v9, v1510143; VI-NEXT: v_add_f16_sdwa v15, v8, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD10144; VI-NEXT: v_add_f16_e32 v8, 0x200, v810145; VI-NEXT: v_or_b32_e32 v8, v8, v1510146; VI-NEXT: v_add_f16_sdwa v15, v7, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD10147; VI-NEXT: v_add_f16_e32 v7, 0x200, v710148; VI-NEXT: v_or_b32_e32 v7, v7, v1510149; VI-NEXT: v_add_f16_sdwa v15, v6, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD10150; VI-NEXT: v_add_f16_e32 v6, 0x200, v610151; VI-NEXT: v_or_b32_e32 v6, v6, v1510152; VI-NEXT: v_add_f16_sdwa v15, v5, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD10153; VI-NEXT: v_add_f16_e32 v5, 0x200, v510154; VI-NEXT: v_or_b32_e32 v5, v5, v1510155; VI-NEXT: v_add_f16_sdwa v15, v4, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD10156; VI-NEXT: v_add_f16_e32 v4, 0x200, v410157; VI-NEXT: v_or_b32_e32 v4, v4, v1510158; VI-NEXT: v_add_f16_sdwa v15, v3, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD10159; VI-NEXT: v_add_f16_e32 v3, 0x200, v310160; VI-NEXT: v_or_b32_e32 v3, v3, v1510161; VI-NEXT: v_add_f16_sdwa v15, v2, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD10162; VI-NEXT: v_add_f16_e32 v2, 0x200, v210163; VI-NEXT: v_or_b32_e32 v2, v2, v1510164; VI-NEXT: v_add_f16_sdwa v15, v1, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD10165; VI-NEXT: v_add_f16_e32 v1, 0x200, v110166; VI-NEXT: v_add_f16_sdwa v14, v0, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD10167; VI-NEXT: v_add_f16_e32 v0, 0x200, v010168; VI-NEXT: v_or_b32_e32 v1, v1, v1510169; VI-NEXT: v_or_b32_e32 v0, v0, v1410170; VI-NEXT: .LBB46_2: ; %end10171; VI-NEXT: s_or_b64 exec, exec, s[4:5]10172; VI-NEXT: s_setpc_b64 s[30:31]10173;10174; GFX9-LABEL: bitcast_v28f16_to_v7i64:10175; GFX9: ; %bb.0:10176; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10177; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1410178; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc10179; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]10180; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]10181; GFX9-NEXT: s_cbranch_execz .LBB46_210182; GFX9-NEXT: ; %bb.1: ; %cmp.true10183; GFX9-NEXT: s_movk_i32 s6, 0x20010184; GFX9-NEXT: v_pk_add_f16 v13, v13, s6 op_sel_hi:[1,0]10185; GFX9-NEXT: v_pk_add_f16 v12, v12, s6 op_sel_hi:[1,0]10186; GFX9-NEXT: v_pk_add_f16 v11, v11, s6 op_sel_hi:[1,0]10187; GFX9-NEXT: v_pk_add_f16 v10, v10, s6 op_sel_hi:[1,0]10188; GFX9-NEXT: v_pk_add_f16 v9, v9, s6 op_sel_hi:[1,0]10189; GFX9-NEXT: v_pk_add_f16 v8, v8, s6 op_sel_hi:[1,0]10190; GFX9-NEXT: v_pk_add_f16 v7, v7, s6 op_sel_hi:[1,0]10191; GFX9-NEXT: v_pk_add_f16 v6, v6, s6 op_sel_hi:[1,0]10192; GFX9-NEXT: v_pk_add_f16 v5, v5, s6 op_sel_hi:[1,0]10193; GFX9-NEXT: v_pk_add_f16 v4, v4, s6 op_sel_hi:[1,0]10194; GFX9-NEXT: v_pk_add_f16 v3, v3, s6 op_sel_hi:[1,0]10195; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]10196; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]10197; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]10198; GFX9-NEXT: .LBB46_2: ; %end10199; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]10200; GFX9-NEXT: s_setpc_b64 s[30:31]10201;10202; GFX11-LABEL: bitcast_v28f16_to_v7i64:10203; GFX11: ; %bb.0:10204; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10205; GFX11-NEXT: s_mov_b32 s0, exec_lo10206; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v1410207; GFX11-NEXT: s_xor_b32 s0, exec_lo, s010208; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)10209; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s010210; GFX11-NEXT: s_cbranch_execz .LBB46_210211; GFX11-NEXT: ; %bb.1: ; %cmp.true10212; GFX11-NEXT: v_pk_add_f16 v13, 0x200, v13 op_sel_hi:[0,1]10213; GFX11-NEXT: v_pk_add_f16 v12, 0x200, v12 op_sel_hi:[0,1]10214; GFX11-NEXT: v_pk_add_f16 v11, 0x200, v11 op_sel_hi:[0,1]10215; GFX11-NEXT: v_pk_add_f16 v10, 0x200, v10 op_sel_hi:[0,1]10216; GFX11-NEXT: v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1]10217; GFX11-NEXT: v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1]10218; GFX11-NEXT: v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]10219; GFX11-NEXT: v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]10220; GFX11-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]10221; GFX11-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]10222; GFX11-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]10223; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]10224; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]10225; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]10226; GFX11-NEXT: .LBB46_2: ; %end10227; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s010228; GFX11-NEXT: s_setpc_b64 s[30:31]10229 %cmp = icmp eq i32 %b, 010230 br i1 %cmp, label %cmp.true, label %cmp.false10231 10232cmp.true:10233 %a1 = fadd <28 x half> %a, splat (half 0xH0200)10234 %a2 = bitcast <28 x half> %a1 to <7 x i64>10235 br label %end10236 10237cmp.false:10238 %a3 = bitcast <28 x half> %a to <7 x i64>10239 br label %end10240 10241end:10242 %phi = phi <7 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]10243 ret <7 x i64> %phi10244}10245 10246define inreg <7 x i64> @bitcast_v28f16_to_v7i64_scalar(<28 x half> inreg %a, i32 inreg %b) {10247; SI-LABEL: bitcast_v28f16_to_v7i64_scalar:10248; SI: ; %bb.0:10249; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10250; SI-NEXT: v_cvt_f16_f32_e32 v51, s1710251; SI-NEXT: v_cvt_f16_f32_e32 v50, s1610252; SI-NEXT: v_cvt_f16_f32_e32 v49, s1910253; SI-NEXT: v_cvt_f16_f32_e32 v38, s1810254; SI-NEXT: v_cvt_f16_f32_e32 v36, s2110255; SI-NEXT: v_cvt_f16_f32_e32 v35, s2010256; SI-NEXT: v_cvt_f16_f32_e32 v29, v110257; SI-NEXT: v_cvt_f16_f32_e32 v28, v010258; SI-NEXT: v_cvt_f16_f32_e32 v27, v310259; SI-NEXT: v_cvt_f16_f32_e32 v26, v210260; SI-NEXT: v_cvt_f16_f32_e32 v25, v510261; SI-NEXT: v_cvt_f16_f32_e32 v24, v410262; SI-NEXT: v_cvt_f16_f32_e32 v23, v710263; SI-NEXT: v_cvt_f16_f32_e32 v22, v610264; SI-NEXT: v_cvt_f16_f32_e32 v21, v910265; SI-NEXT: v_cvt_f16_f32_e32 v20, v810266; SI-NEXT: v_cvt_f16_f32_e32 v19, v1110267; SI-NEXT: v_cvt_f16_f32_e32 v18, v1010268; SI-NEXT: v_cvt_f16_f32_e32 v17, v1310269; SI-NEXT: v_cvt_f16_f32_e32 v16, v1210270; SI-NEXT: v_cvt_f16_f32_e32 v48, s2310271; SI-NEXT: v_cvt_f16_f32_e32 v39, s2210272; SI-NEXT: v_cvt_f16_f32_e32 v37, s2510273; SI-NEXT: v_cvt_f16_f32_e32 v34, s2410274; SI-NEXT: v_cvt_f16_f32_e32 v33, s2710275; SI-NEXT: v_cvt_f16_f32_e32 v32, s2610276; SI-NEXT: v_cvt_f16_f32_e32 v31, s2910277; SI-NEXT: v_cvt_f16_f32_e32 v30, s2810278; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1410279; SI-NEXT: s_and_b64 s[4:5], vcc, exec10280; SI-NEXT: s_cbranch_scc0 .LBB47_410281; SI-NEXT: ; %bb.1: ; %cmp.false10282; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v5110283; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v4910284; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v3610285; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v4810286; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v3710287; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v3310288; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v3110289; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v2910290; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v2710291; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v2510292; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v2310293; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v2110294; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v1910295; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v1710296; SI-NEXT: v_or_b32_e32 v0, v50, v010297; SI-NEXT: v_or_b32_e32 v1, v38, v110298; SI-NEXT: v_or_b32_e32 v2, v35, v210299; SI-NEXT: v_or_b32_e32 v3, v39, v310300; SI-NEXT: v_or_b32_e32 v4, v34, v410301; SI-NEXT: v_or_b32_e32 v5, v32, v510302; SI-NEXT: v_or_b32_e32 v6, v30, v610303; SI-NEXT: v_or_b32_e32 v7, v28, v710304; SI-NEXT: v_or_b32_e32 v8, v26, v810305; SI-NEXT: v_or_b32_e32 v9, v24, v910306; SI-NEXT: v_or_b32_e32 v10, v22, v1010307; SI-NEXT: v_or_b32_e32 v11, v20, v1110308; SI-NEXT: v_or_b32_e32 v12, v18, v1210309; SI-NEXT: v_or_b32_e32 v13, v16, v1310310; SI-NEXT: s_cbranch_execnz .LBB47_310311; SI-NEXT: .LBB47_2: ; %cmp.true10312; SI-NEXT: v_cvt_f32_f16_e32 v0, v5110313; SI-NEXT: v_cvt_f32_f16_e32 v1, v5010314; SI-NEXT: v_cvt_f32_f16_e32 v2, v4910315; SI-NEXT: v_cvt_f32_f16_e32 v3, v3810316; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v010317; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v110318; SI-NEXT: v_cvt_f16_f32_e32 v0, v010319; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v210320; SI-NEXT: v_cvt_f16_f32_e32 v1, v110321; SI-NEXT: v_cvt_f16_f32_e32 v2, v210322; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v010323; SI-NEXT: v_cvt_f32_f16_e32 v4, v3510324; SI-NEXT: v_or_b32_e32 v0, v1, v010325; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v210326; SI-NEXT: v_cvt_f32_f16_e32 v2, v3610327; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v310328; SI-NEXT: v_cvt_f16_f32_e32 v3, v310329; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v410330; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v210331; SI-NEXT: v_cvt_f16_f32_e32 v2, v210332; SI-NEXT: v_cvt_f16_f32_e32 v4, v410333; SI-NEXT: v_or_b32_e32 v1, v3, v110334; SI-NEXT: v_cvt_f32_f16_e32 v3, v4810335; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v210336; SI-NEXT: v_or_b32_e32 v2, v4, v210337; SI-NEXT: v_cvt_f32_f16_e32 v4, v3910338; SI-NEXT: v_cvt_f32_f16_e32 v5, v3710339; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v310340; SI-NEXT: v_cvt_f16_f32_e32 v3, v310341; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v410342; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v510343; SI-NEXT: v_cvt_f16_f32_e32 v4, v410344; SI-NEXT: v_cvt_f16_f32_e32 v5, v510345; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v310346; SI-NEXT: v_cvt_f32_f16_e32 v6, v3410347; SI-NEXT: v_or_b32_e32 v3, v4, v310348; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v510349; SI-NEXT: v_cvt_f32_f16_e32 v5, v3310350; SI-NEXT: v_cvt_f32_f16_e32 v7, v3210351; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v610352; SI-NEXT: v_cvt_f16_f32_e32 v6, v610353; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v510354; SI-NEXT: v_cvt_f16_f32_e32 v5, v510355; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v710356; SI-NEXT: v_cvt_f16_f32_e32 v7, v710357; SI-NEXT: v_or_b32_e32 v4, v6, v410358; SI-NEXT: v_cvt_f32_f16_e32 v6, v3110359; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v510360; SI-NEXT: v_or_b32_e32 v5, v7, v510361; SI-NEXT: v_cvt_f32_f16_e32 v7, v3010362; SI-NEXT: v_cvt_f32_f16_e32 v8, v2910363; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v610364; SI-NEXT: v_cvt_f16_f32_e32 v6, v610365; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v710366; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v810367; SI-NEXT: v_cvt_f16_f32_e32 v7, v710368; SI-NEXT: v_cvt_f16_f32_e32 v8, v810369; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v610370; SI-NEXT: v_cvt_f32_f16_e32 v9, v2810371; SI-NEXT: v_or_b32_e32 v6, v7, v610372; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v810373; SI-NEXT: v_cvt_f32_f16_e32 v8, v2710374; SI-NEXT: v_cvt_f32_f16_e32 v10, v2610375; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v910376; SI-NEXT: v_cvt_f16_f32_e32 v9, v910377; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v810378; SI-NEXT: v_cvt_f16_f32_e32 v8, v810379; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v1010380; SI-NEXT: v_cvt_f16_f32_e32 v10, v1010381; SI-NEXT: v_or_b32_e32 v7, v9, v710382; SI-NEXT: v_cvt_f32_f16_e32 v9, v2510383; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v810384; SI-NEXT: v_or_b32_e32 v8, v10, v810385; SI-NEXT: v_cvt_f32_f16_e32 v10, v2410386; SI-NEXT: v_cvt_f32_f16_e32 v11, v2310387; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v910388; SI-NEXT: v_cvt_f16_f32_e32 v9, v910389; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v1010390; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v1110391; SI-NEXT: v_cvt_f16_f32_e32 v10, v1010392; SI-NEXT: v_cvt_f16_f32_e32 v11, v1110393; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v910394; SI-NEXT: v_cvt_f32_f16_e32 v12, v2210395; SI-NEXT: v_or_b32_e32 v9, v10, v910396; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v1110397; SI-NEXT: v_cvt_f32_f16_e32 v11, v2110398; SI-NEXT: v_cvt_f32_f16_e32 v13, v2010399; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v1210400; SI-NEXT: v_cvt_f16_f32_e32 v12, v1210401; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v1110402; SI-NEXT: v_cvt_f16_f32_e32 v11, v1110403; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v1310404; SI-NEXT: v_cvt_f16_f32_e32 v13, v1310405; SI-NEXT: v_or_b32_e32 v10, v12, v1010406; SI-NEXT: v_cvt_f32_f16_e32 v12, v1910407; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v1110408; SI-NEXT: v_or_b32_e32 v11, v13, v1110409; SI-NEXT: v_cvt_f32_f16_e32 v13, v1810410; SI-NEXT: v_cvt_f32_f16_e32 v14, v1710411; SI-NEXT: v_cvt_f32_f16_e32 v15, v1610412; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v1210413; SI-NEXT: v_cvt_f16_f32_e32 v12, v1210414; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v1310415; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v1410416; SI-NEXT: v_cvt_f16_f32_e32 v13, v1310417; SI-NEXT: v_cvt_f16_f32_e32 v14, v1410418; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v1510419; SI-NEXT: v_cvt_f16_f32_e32 v15, v1510420; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v1210421; SI-NEXT: v_or_b32_e32 v12, v13, v1210422; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v1410423; SI-NEXT: v_or_b32_e32 v13, v15, v1310424; SI-NEXT: .LBB47_3: ; %end10425; SI-NEXT: s_setpc_b64 s[30:31]10426; SI-NEXT: .LBB47_4:10427; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr1510428; SI-NEXT: s_branch .LBB47_210429;10430; VI-LABEL: bitcast_v28f16_to_v7i64_scalar:10431; VI: ; %bb.0:10432; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10433; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v010434; VI-NEXT: s_and_b64 s[4:5], vcc, exec10435; VI-NEXT: s_cbranch_scc0 .LBB47_310436; VI-NEXT: ; %bb.1: ; %cmp.false10437; VI-NEXT: s_cbranch_execnz .LBB47_410438; VI-NEXT: .LBB47_2: ; %cmp.true10439; VI-NEXT: s_lshr_b32 s4, s29, 1610440; VI-NEXT: v_mov_b32_e32 v0, 0x20010441; VI-NEXT: v_mov_b32_e32 v1, s410442; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD10443; VI-NEXT: v_add_f16_e32 v2, s29, v010444; VI-NEXT: s_lshr_b32 s4, s28, 1610445; VI-NEXT: v_or_b32_e32 v13, v2, v110446; VI-NEXT: v_mov_b32_e32 v1, s410447; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD10448; VI-NEXT: v_add_f16_e32 v2, s28, v010449; VI-NEXT: s_lshr_b32 s4, s27, 1610450; VI-NEXT: v_or_b32_e32 v12, v2, v110451; VI-NEXT: v_mov_b32_e32 v1, s410452; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD10453; VI-NEXT: v_add_f16_e32 v2, s27, v010454; VI-NEXT: s_lshr_b32 s4, s26, 1610455; VI-NEXT: v_or_b32_e32 v11, v2, v110456; VI-NEXT: v_mov_b32_e32 v1, s410457; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD10458; VI-NEXT: v_add_f16_e32 v2, s26, v010459; VI-NEXT: s_lshr_b32 s4, s25, 1610460; VI-NEXT: v_or_b32_e32 v10, v2, v110461; VI-NEXT: v_mov_b32_e32 v1, s410462; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD10463; VI-NEXT: v_add_f16_e32 v2, s25, v010464; VI-NEXT: s_lshr_b32 s4, s24, 1610465; VI-NEXT: v_or_b32_e32 v9, v2, v110466; VI-NEXT: v_mov_b32_e32 v1, s410467; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD10468; VI-NEXT: v_add_f16_e32 v2, s24, v010469; VI-NEXT: s_lshr_b32 s4, s23, 1610470; VI-NEXT: v_or_b32_e32 v8, v2, v110471; VI-NEXT: v_mov_b32_e32 v1, s410472; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD10473; VI-NEXT: v_add_f16_e32 v2, s23, v010474; VI-NEXT: s_lshr_b32 s4, s22, 1610475; VI-NEXT: v_or_b32_e32 v7, v2, v110476; VI-NEXT: v_mov_b32_e32 v1, s410477; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD10478; VI-NEXT: v_add_f16_e32 v2, s22, v010479; VI-NEXT: s_lshr_b32 s4, s21, 1610480; VI-NEXT: v_or_b32_e32 v6, v2, v110481; VI-NEXT: v_mov_b32_e32 v1, s410482; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD10483; VI-NEXT: v_add_f16_e32 v2, s21, v010484; VI-NEXT: s_lshr_b32 s4, s20, 1610485; VI-NEXT: v_or_b32_e32 v5, v2, v110486; VI-NEXT: v_mov_b32_e32 v1, s410487; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD10488; VI-NEXT: v_add_f16_e32 v2, s20, v010489; VI-NEXT: s_lshr_b32 s4, s19, 1610490; VI-NEXT: v_or_b32_e32 v4, v2, v110491; VI-NEXT: v_mov_b32_e32 v1, s410492; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD10493; VI-NEXT: v_add_f16_e32 v2, s19, v010494; VI-NEXT: s_lshr_b32 s4, s18, 1610495; VI-NEXT: v_or_b32_e32 v3, v2, v110496; VI-NEXT: v_mov_b32_e32 v1, s410497; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD10498; VI-NEXT: v_add_f16_e32 v2, s18, v010499; VI-NEXT: s_lshr_b32 s4, s17, 1610500; VI-NEXT: v_or_b32_e32 v2, v2, v110501; VI-NEXT: v_mov_b32_e32 v1, s410502; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD10503; VI-NEXT: v_add_f16_e32 v14, s17, v010504; VI-NEXT: s_lshr_b32 s4, s16, 1610505; VI-NEXT: v_or_b32_e32 v1, v14, v110506; VI-NEXT: v_mov_b32_e32 v14, s410507; VI-NEXT: v_add_f16_sdwa v14, v14, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD10508; VI-NEXT: v_add_f16_e32 v0, s16, v010509; VI-NEXT: v_or_b32_e32 v0, v0, v1410510; VI-NEXT: s_setpc_b64 s[30:31]10511; VI-NEXT: .LBB47_3:10512; VI-NEXT: s_branch .LBB47_210513; VI-NEXT: .LBB47_4:10514; VI-NEXT: v_mov_b32_e32 v0, s1610515; VI-NEXT: v_mov_b32_e32 v1, s1710516; VI-NEXT: v_mov_b32_e32 v2, s1810517; VI-NEXT: v_mov_b32_e32 v3, s1910518; VI-NEXT: v_mov_b32_e32 v4, s2010519; VI-NEXT: v_mov_b32_e32 v5, s2110520; VI-NEXT: v_mov_b32_e32 v6, s2210521; VI-NEXT: v_mov_b32_e32 v7, s2310522; VI-NEXT: v_mov_b32_e32 v8, s2410523; VI-NEXT: v_mov_b32_e32 v9, s2510524; VI-NEXT: v_mov_b32_e32 v10, s2610525; VI-NEXT: v_mov_b32_e32 v11, s2710526; VI-NEXT: v_mov_b32_e32 v12, s2810527; VI-NEXT: v_mov_b32_e32 v13, s2910528; VI-NEXT: v_mov_b32_e32 v14, s3010529; VI-NEXT: v_mov_b32_e32 v15, s3110530; VI-NEXT: s_setpc_b64 s[30:31]10531;10532; GFX9-LABEL: bitcast_v28f16_to_v7i64_scalar:10533; GFX9: ; %bb.0:10534; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10535; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v010536; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec10537; GFX9-NEXT: s_cbranch_scc0 .LBB47_310538; GFX9-NEXT: ; %bb.1: ; %cmp.false10539; GFX9-NEXT: s_cbranch_execnz .LBB47_410540; GFX9-NEXT: .LBB47_2: ; %cmp.true10541; GFX9-NEXT: v_mov_b32_e32 v0, 0x20010542; GFX9-NEXT: v_pk_add_f16 v13, s29, v0 op_sel_hi:[1,0]10543; GFX9-NEXT: v_pk_add_f16 v12, s28, v0 op_sel_hi:[1,0]10544; GFX9-NEXT: v_pk_add_f16 v11, s27, v0 op_sel_hi:[1,0]10545; GFX9-NEXT: v_pk_add_f16 v10, s26, v0 op_sel_hi:[1,0]10546; GFX9-NEXT: v_pk_add_f16 v9, s25, v0 op_sel_hi:[1,0]10547; GFX9-NEXT: v_pk_add_f16 v8, s24, v0 op_sel_hi:[1,0]10548; GFX9-NEXT: v_pk_add_f16 v7, s23, v0 op_sel_hi:[1,0]10549; GFX9-NEXT: v_pk_add_f16 v6, s22, v0 op_sel_hi:[1,0]10550; GFX9-NEXT: v_pk_add_f16 v5, s21, v0 op_sel_hi:[1,0]10551; GFX9-NEXT: v_pk_add_f16 v4, s20, v0 op_sel_hi:[1,0]10552; GFX9-NEXT: v_pk_add_f16 v3, s19, v0 op_sel_hi:[1,0]10553; GFX9-NEXT: v_pk_add_f16 v2, s18, v0 op_sel_hi:[1,0]10554; GFX9-NEXT: v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]10555; GFX9-NEXT: v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]10556; GFX9-NEXT: s_setpc_b64 s[30:31]10557; GFX9-NEXT: .LBB47_3:10558; GFX9-NEXT: s_branch .LBB47_210559; GFX9-NEXT: .LBB47_4:10560; GFX9-NEXT: v_mov_b32_e32 v0, s1610561; GFX9-NEXT: v_mov_b32_e32 v1, s1710562; GFX9-NEXT: v_mov_b32_e32 v2, s1810563; GFX9-NEXT: v_mov_b32_e32 v3, s1910564; GFX9-NEXT: v_mov_b32_e32 v4, s2010565; GFX9-NEXT: v_mov_b32_e32 v5, s2110566; GFX9-NEXT: v_mov_b32_e32 v6, s2210567; GFX9-NEXT: v_mov_b32_e32 v7, s2310568; GFX9-NEXT: v_mov_b32_e32 v8, s2410569; GFX9-NEXT: v_mov_b32_e32 v9, s2510570; GFX9-NEXT: v_mov_b32_e32 v10, s2610571; GFX9-NEXT: v_mov_b32_e32 v11, s2710572; GFX9-NEXT: v_mov_b32_e32 v12, s2810573; GFX9-NEXT: v_mov_b32_e32 v13, s2910574; GFX9-NEXT: v_mov_b32_e32 v14, s3010575; GFX9-NEXT: v_mov_b32_e32 v15, s3110576; GFX9-NEXT: s_setpc_b64 s[30:31]10577;10578; GFX11-LABEL: bitcast_v28f16_to_v7i64_scalar:10579; GFX11: ; %bb.0:10580; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10581; GFX11-NEXT: s_mov_b32 s15, s310582; GFX11-NEXT: s_mov_b32 s14, s210583; GFX11-NEXT: s_mov_b32 s13, s110584; GFX11-NEXT: s_mov_b32 s12, s010585; GFX11-NEXT: s_cmp_lg_u32 s26, 010586; GFX11-NEXT: s_mov_b32 s0, 010587; GFX11-NEXT: s_cbranch_scc0 .LBB47_310588; GFX11-NEXT: ; %bb.1: ; %Flow10589; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s010590; GFX11-NEXT: s_cbranch_vccnz .LBB47_410591; GFX11-NEXT: .LBB47_2: ; %cmp.true10592; GFX11-NEXT: v_pk_add_f16 v13, 0x200, s25 op_sel_hi:[0,1]10593; GFX11-NEXT: v_pk_add_f16 v12, 0x200, s24 op_sel_hi:[0,1]10594; GFX11-NEXT: v_pk_add_f16 v11, 0x200, s23 op_sel_hi:[0,1]10595; GFX11-NEXT: v_pk_add_f16 v10, 0x200, s22 op_sel_hi:[0,1]10596; GFX11-NEXT: v_pk_add_f16 v9, 0x200, s21 op_sel_hi:[0,1]10597; GFX11-NEXT: v_pk_add_f16 v8, 0x200, s20 op_sel_hi:[0,1]10598; GFX11-NEXT: v_pk_add_f16 v7, 0x200, s19 op_sel_hi:[0,1]10599; GFX11-NEXT: v_pk_add_f16 v6, 0x200, s18 op_sel_hi:[0,1]10600; GFX11-NEXT: v_pk_add_f16 v5, 0x200, s17 op_sel_hi:[0,1]10601; GFX11-NEXT: v_pk_add_f16 v4, 0x200, s16 op_sel_hi:[0,1]10602; GFX11-NEXT: v_pk_add_f16 v3, 0x200, s15 op_sel_hi:[0,1]10603; GFX11-NEXT: v_pk_add_f16 v2, 0x200, s14 op_sel_hi:[0,1]10604; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s13 op_sel_hi:[0,1]10605; GFX11-NEXT: v_pk_add_f16 v0, 0x200, s12 op_sel_hi:[0,1]10606; GFX11-NEXT: s_setpc_b64 s[30:31]10607; GFX11-NEXT: .LBB47_3:10608; GFX11-NEXT: s_branch .LBB47_210609; GFX11-NEXT: .LBB47_4:10610; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s1310611; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s1510612; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s1710613; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s1910614; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s2110615; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s2310616; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s2510617; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s2710618; GFX11-NEXT: s_setpc_b64 s[30:31]10619 %cmp = icmp eq i32 %b, 010620 br i1 %cmp, label %cmp.true, label %cmp.false10621 10622cmp.true:10623 %a1 = fadd <28 x half> %a, splat (half 0xH0200)10624 %a2 = bitcast <28 x half> %a1 to <7 x i64>10625 br label %end10626 10627cmp.false:10628 %a3 = bitcast <28 x half> %a to <7 x i64>10629 br label %end10630 10631end:10632 %phi = phi <7 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]10633 ret <7 x i64> %phi10634}10635 10636define <28 x i16> @bitcast_v7f64_to_v28i16(<7 x double> %a, i32 %b) {10637; SI-LABEL: bitcast_v7f64_to_v28i16:10638; SI: ; %bb.0:10639; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10640; SI-NEXT: v_mov_b32_e32 v49, v1310641; SI-NEXT: v_mov_b32_e32 v48, v1210642; SI-NEXT: v_mov_b32_e32 v38, v1110643; SI-NEXT: v_mov_b32_e32 v37, v1010644; SI-NEXT: v_mov_b32_e32 v36, v910645; SI-NEXT: v_mov_b32_e32 v35, v810646; SI-NEXT: v_mov_b32_e32 v34, v710647; SI-NEXT: v_mov_b32_e32 v33, v610648; SI-NEXT: v_mov_b32_e32 v32, v510649; SI-NEXT: v_mov_b32_e32 v31, v410650; SI-NEXT: v_mov_b32_e32 v30, v310651; SI-NEXT: v_mov_b32_e32 v29, v210652; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1410653; SI-NEXT: ; implicit-def: $vgpr2810654; SI-NEXT: ; implicit-def: $vgpr310655; SI-NEXT: ; implicit-def: $vgpr510656; SI-NEXT: ; implicit-def: $vgpr710657; SI-NEXT: ; implicit-def: $vgpr910658; SI-NEXT: ; implicit-def: $vgpr1110659; SI-NEXT: ; implicit-def: $vgpr1310660; SI-NEXT: ; implicit-def: $vgpr1510661; SI-NEXT: ; implicit-def: $vgpr1710662; SI-NEXT: ; implicit-def: $vgpr1910663; SI-NEXT: ; implicit-def: $vgpr2110664; SI-NEXT: ; implicit-def: $vgpr2310665; SI-NEXT: ; implicit-def: $vgpr2510666; SI-NEXT: ; implicit-def: $vgpr2710667; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc10668; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]10669; SI-NEXT: s_cbranch_execz .LBB48_210670; SI-NEXT: ; %bb.1: ; %cmp.false10671; SI-NEXT: v_alignbit_b32 v25, v49, v48, 1610672; SI-NEXT: v_alignbit_b32 v21, v38, v37, 1610673; SI-NEXT: v_alignbit_b32 v17, v36, v35, 1610674; SI-NEXT: v_alignbit_b32 v13, v34, v33, 1610675; SI-NEXT: v_alignbit_b32 v9, v32, v31, 1610676; SI-NEXT: v_alignbit_b32 v5, v30, v29, 1610677; SI-NEXT: v_alignbit_b32 v28, v1, v0, 1610678; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v4910679; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v3810680; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v3610681; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v3410682; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v3210683; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v3010684; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v110685; SI-NEXT: .LBB48_2: ; %Flow10686; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]10687; SI-NEXT: s_cbranch_execz .LBB48_410688; SI-NEXT: ; %bb.3: ; %cmp.true10689; SI-NEXT: v_add_f64 v[0:1], v[0:1], 1.010690; SI-NEXT: v_add_f64 v[29:30], v[29:30], 1.010691; SI-NEXT: v_add_f64 v[31:32], v[31:32], 1.010692; SI-NEXT: v_add_f64 v[33:34], v[33:34], 1.010693; SI-NEXT: v_add_f64 v[35:36], v[35:36], 1.010694; SI-NEXT: v_add_f64 v[48:49], v[48:49], 1.010695; SI-NEXT: v_add_f64 v[37:38], v[37:38], 1.010696; SI-NEXT: v_alignbit_b32 v25, v49, v48, 1610697; SI-NEXT: v_alignbit_b32 v21, v38, v37, 1610698; SI-NEXT: v_alignbit_b32 v17, v36, v35, 1610699; SI-NEXT: v_alignbit_b32 v13, v34, v33, 1610700; SI-NEXT: v_alignbit_b32 v9, v32, v31, 1610701; SI-NEXT: v_alignbit_b32 v5, v30, v29, 1610702; SI-NEXT: v_alignbit_b32 v28, v1, v0, 1610703; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v4910704; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v3810705; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v3610706; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v3410707; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v3210708; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v3010709; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v110710; SI-NEXT: .LBB48_4: ; %end10711; SI-NEXT: s_or_b64 exec, exec, s[4:5]10712; SI-NEXT: v_mov_b32_e32 v2, v110713; SI-NEXT: v_mov_b32_e32 v4, v2910714; SI-NEXT: v_mov_b32_e32 v6, v3010715; SI-NEXT: v_mov_b32_e32 v8, v3110716; SI-NEXT: v_mov_b32_e32 v10, v3210717; SI-NEXT: v_mov_b32_e32 v12, v3310718; SI-NEXT: v_mov_b32_e32 v14, v3410719; SI-NEXT: v_mov_b32_e32 v16, v3510720; SI-NEXT: v_mov_b32_e32 v18, v3610721; SI-NEXT: v_mov_b32_e32 v20, v3710722; SI-NEXT: v_mov_b32_e32 v22, v3810723; SI-NEXT: v_mov_b32_e32 v24, v4810724; SI-NEXT: v_mov_b32_e32 v26, v4910725; SI-NEXT: v_mov_b32_e32 v1, v2810726; SI-NEXT: s_setpc_b64 s[30:31]10727;10728; VI-LABEL: bitcast_v7f64_to_v28i16:10729; VI: ; %bb.0:10730; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10731; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1410732; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc10733; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]10734; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]10735; VI-NEXT: s_cbranch_execz .LBB48_210736; VI-NEXT: ; %bb.1: ; %cmp.true10737; VI-NEXT: v_add_f64 v[12:13], v[12:13], 1.010738; VI-NEXT: v_add_f64 v[10:11], v[10:11], 1.010739; VI-NEXT: v_add_f64 v[8:9], v[8:9], 1.010740; VI-NEXT: v_add_f64 v[6:7], v[6:7], 1.010741; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.010742; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.010743; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.010744; VI-NEXT: .LBB48_2: ; %end10745; VI-NEXT: s_or_b64 exec, exec, s[4:5]10746; VI-NEXT: s_setpc_b64 s[30:31]10747;10748; GFX9-LABEL: bitcast_v7f64_to_v28i16:10749; GFX9: ; %bb.0:10750; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10751; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1410752; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc10753; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]10754; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]10755; GFX9-NEXT: s_cbranch_execz .LBB48_210756; GFX9-NEXT: ; %bb.1: ; %cmp.true10757; GFX9-NEXT: v_add_f64 v[12:13], v[12:13], 1.010758; GFX9-NEXT: v_add_f64 v[10:11], v[10:11], 1.010759; GFX9-NEXT: v_add_f64 v[8:9], v[8:9], 1.010760; GFX9-NEXT: v_add_f64 v[6:7], v[6:7], 1.010761; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.010762; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.010763; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.010764; GFX9-NEXT: .LBB48_2: ; %end10765; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]10766; GFX9-NEXT: s_setpc_b64 s[30:31]10767;10768; GFX11-LABEL: bitcast_v7f64_to_v28i16:10769; GFX11: ; %bb.0:10770; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10771; GFX11-NEXT: s_mov_b32 s0, exec_lo10772; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v1410773; GFX11-NEXT: s_xor_b32 s0, exec_lo, s010774; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)10775; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s010776; GFX11-NEXT: s_cbranch_execz .LBB48_210777; GFX11-NEXT: ; %bb.1: ; %cmp.true10778; GFX11-NEXT: v_add_f64 v[12:13], v[12:13], 1.010779; GFX11-NEXT: v_add_f64 v[10:11], v[10:11], 1.010780; GFX11-NEXT: v_add_f64 v[8:9], v[8:9], 1.010781; GFX11-NEXT: v_add_f64 v[6:7], v[6:7], 1.010782; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.010783; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.010784; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.010785; GFX11-NEXT: .LBB48_2: ; %end10786; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s010787; GFX11-NEXT: s_setpc_b64 s[30:31]10788 %cmp = icmp eq i32 %b, 010789 br i1 %cmp, label %cmp.true, label %cmp.false10790 10791cmp.true:10792 %a1 = fadd <7 x double> %a, splat (double 1.000000e+00)10793 %a2 = bitcast <7 x double> %a1 to <28 x i16>10794 br label %end10795 10796cmp.false:10797 %a3 = bitcast <7 x double> %a to <28 x i16>10798 br label %end10799 10800end:10801 %phi = phi <28 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]10802 ret <28 x i16> %phi10803}10804 10805define inreg <28 x i16> @bitcast_v7f64_to_v28i16_scalar(<7 x double> inreg %a, i32 inreg %b) {10806; SI-LABEL: bitcast_v7f64_to_v28i16_scalar:10807; SI: ; %bb.0:10808; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10809; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v010810; SI-NEXT: s_and_b64 s[4:5], vcc, exec10811; SI-NEXT: s_cbranch_scc0 .LBB49_310812; SI-NEXT: ; %bb.1: ; %cmp.false10813; SI-NEXT: s_lshr_b32 s58, s29, 1610814; SI-NEXT: s_lshr_b32 s57, s27, 1610815; SI-NEXT: s_lshr_b32 s56, s25, 1610816; SI-NEXT: s_lshr_b32 s47, s23, 1610817; SI-NEXT: s_lshr_b32 s46, s21, 1610818; SI-NEXT: s_lshr_b32 s45, s19, 1610819; SI-NEXT: s_lshr_b32 s44, s17, 1610820; SI-NEXT: s_lshr_b64 s[4:5], s[28:29], 1610821; SI-NEXT: s_lshr_b64 s[6:7], s[26:27], 1610822; SI-NEXT: s_lshr_b64 s[8:9], s[24:25], 1610823; SI-NEXT: s_lshr_b64 s[10:11], s[22:23], 1610824; SI-NEXT: s_lshr_b64 s[12:13], s[20:21], 1610825; SI-NEXT: s_lshr_b64 s[14:15], s[18:19], 1610826; SI-NEXT: s_lshr_b64 s[40:41], s[16:17], 1610827; SI-NEXT: s_cbranch_execnz .LBB49_410828; SI-NEXT: .LBB49_2: ; %cmp.true10829; SI-NEXT: v_add_f64 v[28:29], s[28:29], 1.010830; SI-NEXT: v_add_f64 v[30:31], s[26:27], 1.010831; SI-NEXT: v_add_f64 v[32:33], s[24:25], 1.010832; SI-NEXT: v_add_f64 v[34:35], s[22:23], 1.010833; SI-NEXT: v_add_f64 v[36:37], s[20:21], 1.010834; SI-NEXT: v_add_f64 v[38:39], s[18:19], 1.010835; SI-NEXT: v_add_f64 v[48:49], s[16:17], 1.010836; SI-NEXT: v_lshr_b64 v[25:26], v[28:29], 1610837; SI-NEXT: v_lshr_b64 v[21:22], v[30:31], 1610838; SI-NEXT: v_lshr_b64 v[17:18], v[32:33], 1610839; SI-NEXT: v_lshr_b64 v[13:14], v[34:35], 1610840; SI-NEXT: v_lshr_b64 v[9:10], v[36:37], 1610841; SI-NEXT: v_lshr_b64 v[5:6], v[38:39], 1610842; SI-NEXT: v_lshr_b64 v[1:2], v[48:49], 1610843; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v2910844; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v3110845; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v3310846; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v3510847; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v3710848; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v3910849; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v4910850; SI-NEXT: s_branch .LBB49_510851; SI-NEXT: .LBB49_3:10852; SI-NEXT: ; implicit-def: $sgpr4010853; SI-NEXT: ; implicit-def: $sgpr4410854; SI-NEXT: ; implicit-def: $sgpr1410855; SI-NEXT: ; implicit-def: $sgpr4510856; SI-NEXT: ; implicit-def: $sgpr1210857; SI-NEXT: ; implicit-def: $sgpr4610858; SI-NEXT: ; implicit-def: $sgpr1010859; SI-NEXT: ; implicit-def: $sgpr4710860; SI-NEXT: ; implicit-def: $sgpr810861; SI-NEXT: ; implicit-def: $sgpr5610862; SI-NEXT: ; implicit-def: $sgpr610863; SI-NEXT: ; implicit-def: $sgpr5710864; SI-NEXT: ; implicit-def: $sgpr410865; SI-NEXT: ; implicit-def: $sgpr5810866; SI-NEXT: s_branch .LBB49_210867; SI-NEXT: .LBB49_4:10868; SI-NEXT: v_mov_b32_e32 v29, s2910869; SI-NEXT: v_mov_b32_e32 v31, s2710870; SI-NEXT: v_mov_b32_e32 v33, s2510871; SI-NEXT: v_mov_b32_e32 v35, s2310872; SI-NEXT: v_mov_b32_e32 v37, s2110873; SI-NEXT: v_mov_b32_e32 v39, s1910874; SI-NEXT: v_mov_b32_e32 v49, s1710875; SI-NEXT: v_mov_b32_e32 v48, s1610876; SI-NEXT: v_mov_b32_e32 v38, s1810877; SI-NEXT: v_mov_b32_e32 v36, s2010878; SI-NEXT: v_mov_b32_e32 v34, s2210879; SI-NEXT: v_mov_b32_e32 v32, s2410880; SI-NEXT: v_mov_b32_e32 v30, s2610881; SI-NEXT: v_mov_b32_e32 v28, s2810882; SI-NEXT: v_mov_b32_e32 v27, s5810883; SI-NEXT: v_mov_b32_e32 v23, s5710884; SI-NEXT: v_mov_b32_e32 v19, s5610885; SI-NEXT: v_mov_b32_e32 v15, s4710886; SI-NEXT: v_mov_b32_e32 v11, s4610887; SI-NEXT: v_mov_b32_e32 v7, s4510888; SI-NEXT: v_mov_b32_e32 v3, s4410889; SI-NEXT: v_mov_b32_e32 v1, s4010890; SI-NEXT: v_mov_b32_e32 v5, s1410891; SI-NEXT: v_mov_b32_e32 v9, s1210892; SI-NEXT: v_mov_b32_e32 v13, s1010893; SI-NEXT: v_mov_b32_e32 v17, s810894; SI-NEXT: v_mov_b32_e32 v21, s610895; SI-NEXT: v_mov_b32_e32 v25, s410896; SI-NEXT: .LBB49_5: ; %end10897; SI-NEXT: v_mov_b32_e32 v0, v4810898; SI-NEXT: v_mov_b32_e32 v2, v4910899; SI-NEXT: v_mov_b32_e32 v4, v3810900; SI-NEXT: v_mov_b32_e32 v6, v3910901; SI-NEXT: v_mov_b32_e32 v8, v3610902; SI-NEXT: v_mov_b32_e32 v10, v3710903; SI-NEXT: v_mov_b32_e32 v12, v3410904; SI-NEXT: v_mov_b32_e32 v14, v3510905; SI-NEXT: v_mov_b32_e32 v16, v3210906; SI-NEXT: v_mov_b32_e32 v18, v3310907; SI-NEXT: v_mov_b32_e32 v20, v3010908; SI-NEXT: v_mov_b32_e32 v22, v3110909; SI-NEXT: v_mov_b32_e32 v24, v2810910; SI-NEXT: v_mov_b32_e32 v26, v2910911; SI-NEXT: s_setpc_b64 s[30:31]10912;10913; VI-LABEL: bitcast_v7f64_to_v28i16_scalar:10914; VI: ; %bb.0:10915; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10916; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v010917; VI-NEXT: s_and_b64 s[4:5], vcc, exec10918; VI-NEXT: s_cbranch_scc0 .LBB49_310919; VI-NEXT: ; %bb.1: ; %cmp.false10920; VI-NEXT: s_cbranch_execnz .LBB49_410921; VI-NEXT: .LBB49_2: ; %cmp.true10922; VI-NEXT: v_add_f64 v[12:13], s[28:29], 1.010923; VI-NEXT: v_add_f64 v[10:11], s[26:27], 1.010924; VI-NEXT: v_add_f64 v[8:9], s[24:25], 1.010925; VI-NEXT: v_add_f64 v[6:7], s[22:23], 1.010926; VI-NEXT: v_add_f64 v[4:5], s[20:21], 1.010927; VI-NEXT: v_add_f64 v[2:3], s[18:19], 1.010928; VI-NEXT: v_add_f64 v[0:1], s[16:17], 1.010929; VI-NEXT: s_setpc_b64 s[30:31]10930; VI-NEXT: .LBB49_3:10931; VI-NEXT: s_branch .LBB49_210932; VI-NEXT: .LBB49_4:10933; VI-NEXT: v_mov_b32_e32 v0, s1610934; VI-NEXT: v_mov_b32_e32 v1, s1710935; VI-NEXT: v_mov_b32_e32 v2, s1810936; VI-NEXT: v_mov_b32_e32 v3, s1910937; VI-NEXT: v_mov_b32_e32 v4, s2010938; VI-NEXT: v_mov_b32_e32 v5, s2110939; VI-NEXT: v_mov_b32_e32 v6, s2210940; VI-NEXT: v_mov_b32_e32 v7, s2310941; VI-NEXT: v_mov_b32_e32 v8, s2410942; VI-NEXT: v_mov_b32_e32 v9, s2510943; VI-NEXT: v_mov_b32_e32 v10, s2610944; VI-NEXT: v_mov_b32_e32 v11, s2710945; VI-NEXT: v_mov_b32_e32 v12, s2810946; VI-NEXT: v_mov_b32_e32 v13, s2910947; VI-NEXT: v_mov_b32_e32 v14, s3010948; VI-NEXT: v_mov_b32_e32 v15, s3110949; VI-NEXT: s_setpc_b64 s[30:31]10950;10951; GFX9-LABEL: bitcast_v7f64_to_v28i16_scalar:10952; GFX9: ; %bb.0:10953; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10954; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v010955; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec10956; GFX9-NEXT: s_cbranch_scc0 .LBB49_310957; GFX9-NEXT: ; %bb.1: ; %cmp.false10958; GFX9-NEXT: s_cbranch_execnz .LBB49_410959; GFX9-NEXT: .LBB49_2: ; %cmp.true10960; GFX9-NEXT: v_add_f64 v[12:13], s[28:29], 1.010961; GFX9-NEXT: v_add_f64 v[10:11], s[26:27], 1.010962; GFX9-NEXT: v_add_f64 v[8:9], s[24:25], 1.010963; GFX9-NEXT: v_add_f64 v[6:7], s[22:23], 1.010964; GFX9-NEXT: v_add_f64 v[4:5], s[20:21], 1.010965; GFX9-NEXT: v_add_f64 v[2:3], s[18:19], 1.010966; GFX9-NEXT: v_add_f64 v[0:1], s[16:17], 1.010967; GFX9-NEXT: s_setpc_b64 s[30:31]10968; GFX9-NEXT: .LBB49_3:10969; GFX9-NEXT: s_branch .LBB49_210970; GFX9-NEXT: .LBB49_4:10971; GFX9-NEXT: v_mov_b32_e32 v0, s1610972; GFX9-NEXT: v_mov_b32_e32 v1, s1710973; GFX9-NEXT: v_mov_b32_e32 v2, s1810974; GFX9-NEXT: v_mov_b32_e32 v3, s1910975; GFX9-NEXT: v_mov_b32_e32 v4, s2010976; GFX9-NEXT: v_mov_b32_e32 v5, s2110977; GFX9-NEXT: v_mov_b32_e32 v6, s2210978; GFX9-NEXT: v_mov_b32_e32 v7, s2310979; GFX9-NEXT: v_mov_b32_e32 v8, s2410980; GFX9-NEXT: v_mov_b32_e32 v9, s2510981; GFX9-NEXT: v_mov_b32_e32 v10, s2610982; GFX9-NEXT: v_mov_b32_e32 v11, s2710983; GFX9-NEXT: v_mov_b32_e32 v12, s2810984; GFX9-NEXT: v_mov_b32_e32 v13, s2910985; GFX9-NEXT: v_mov_b32_e32 v14, s3010986; GFX9-NEXT: v_mov_b32_e32 v15, s3110987; GFX9-NEXT: s_setpc_b64 s[30:31]10988;10989; GFX11-LABEL: bitcast_v7f64_to_v28i16_scalar:10990; GFX11: ; %bb.0:10991; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10992; GFX11-NEXT: s_mov_b32 s15, s310993; GFX11-NEXT: s_mov_b32 s14, s210994; GFX11-NEXT: s_mov_b32 s13, s110995; GFX11-NEXT: s_mov_b32 s12, s010996; GFX11-NEXT: s_cmp_lg_u32 s26, 010997; GFX11-NEXT: s_mov_b32 s0, 010998; GFX11-NEXT: s_cbranch_scc0 .LBB49_310999; GFX11-NEXT: ; %bb.1: ; %Flow11000; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s011001; GFX11-NEXT: s_cbranch_vccnz .LBB49_411002; GFX11-NEXT: .LBB49_2: ; %cmp.true11003; GFX11-NEXT: v_add_f64 v[12:13], s[24:25], 1.011004; GFX11-NEXT: v_add_f64 v[10:11], s[22:23], 1.011005; GFX11-NEXT: v_add_f64 v[8:9], s[20:21], 1.011006; GFX11-NEXT: v_add_f64 v[6:7], s[18:19], 1.011007; GFX11-NEXT: v_add_f64 v[4:5], s[16:17], 1.011008; GFX11-NEXT: v_add_f64 v[2:3], s[14:15], 1.011009; GFX11-NEXT: v_add_f64 v[0:1], s[12:13], 1.011010; GFX11-NEXT: s_setpc_b64 s[30:31]11011; GFX11-NEXT: .LBB49_3:11012; GFX11-NEXT: s_branch .LBB49_211013; GFX11-NEXT: .LBB49_4:11014; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s1311015; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s1511016; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s1711017; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s1911018; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s2111019; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s2311020; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s2511021; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s2711022; GFX11-NEXT: s_setpc_b64 s[30:31]11023 %cmp = icmp eq i32 %b, 011024 br i1 %cmp, label %cmp.true, label %cmp.false11025 11026cmp.true:11027 %a1 = fadd <7 x double> %a, splat (double 1.000000e+00)11028 %a2 = bitcast <7 x double> %a1 to <28 x i16>11029 br label %end11030 11031cmp.false:11032 %a3 = bitcast <7 x double> %a to <28 x i16>11033 br label %end11034 11035end:11036 %phi = phi <28 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]11037 ret <28 x i16> %phi11038}11039 11040define <7 x double> @bitcast_v28i16_to_v7f64(<28 x i16> %a, i32 %b) {11041; SI-LABEL: bitcast_v28i16_to_v7f64:11042; SI: ; %bb.0:11043; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)11044; SI-NEXT: v_mov_b32_e32 v36, v1411045; SI-NEXT: v_mov_b32_e32 v35, v1211046; SI-NEXT: v_mov_b32_e32 v34, v1011047; SI-NEXT: v_mov_b32_e32 v33, v811048; SI-NEXT: v_mov_b32_e32 v32, v611049; SI-NEXT: v_mov_b32_e32 v31, v411050; SI-NEXT: v_mov_b32_e32 v30, v211051; SI-NEXT: v_mov_b32_e32 v29, v011052; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2811053; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v111054; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v311055; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v511056; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v711057; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v911058; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v1111059; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v1311060; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v1511061; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v1711062; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v1911063; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v2111064; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v2311065; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v2511066; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v2711067; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr1511068; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc11069; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]11070; SI-NEXT: s_cbranch_execnz .LBB50_311071; SI-NEXT: ; %bb.1: ; %Flow11072; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]11073; SI-NEXT: s_cbranch_execnz .LBB50_411074; SI-NEXT: .LBB50_2: ; %end11075; SI-NEXT: s_or_b64 exec, exec, s[4:5]11076; SI-NEXT: s_setpc_b64 s[30:31]11077; SI-NEXT: .LBB50_3: ; %cmp.false11078; SI-NEXT: v_and_b32_e32 v0, 0xffff, v2911079; SI-NEXT: v_and_b32_e32 v1, 0xffff, v3011080; SI-NEXT: v_and_b32_e32 v2, 0xffff, v3111081; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3211082; SI-NEXT: v_and_b32_e32 v4, 0xffff, v3311083; SI-NEXT: v_and_b32_e32 v5, 0xffff, v3411084; SI-NEXT: v_and_b32_e32 v6, 0xffff, v3511085; SI-NEXT: v_and_b32_e32 v7, 0xffff, v3611086; SI-NEXT: v_and_b32_e32 v8, 0xffff, v1611087; SI-NEXT: v_and_b32_e32 v9, 0xffff, v1811088; SI-NEXT: v_and_b32_e32 v10, 0xffff, v2011089; SI-NEXT: v_and_b32_e32 v11, 0xffff, v2211090; SI-NEXT: v_and_b32_e32 v12, 0xffff, v2411091; SI-NEXT: v_and_b32_e32 v13, 0xffff, v2611092; SI-NEXT: v_or_b32_e32 v0, v0, v5411093; SI-NEXT: v_or_b32_e32 v1, v1, v5311094; SI-NEXT: v_or_b32_e32 v2, v2, v5211095; SI-NEXT: v_or_b32_e32 v3, v3, v5111096; SI-NEXT: v_or_b32_e32 v4, v4, v5011097; SI-NEXT: v_or_b32_e32 v5, v5, v4911098; SI-NEXT: v_or_b32_e32 v6, v6, v4811099; SI-NEXT: v_or_b32_e32 v7, v7, v3911100; SI-NEXT: v_or_b32_e32 v8, v8, v3811101; SI-NEXT: v_or_b32_e32 v9, v9, v3711102; SI-NEXT: v_or_b32_e32 v10, v10, v2811103; SI-NEXT: v_or_b32_e32 v11, v11, v2111104; SI-NEXT: v_or_b32_e32 v12, v12, v1911105; SI-NEXT: v_or_b32_e32 v13, v13, v1711106; SI-NEXT: ; implicit-def: $vgpr2911107; SI-NEXT: ; implicit-def: $vgpr3011108; SI-NEXT: ; implicit-def: $vgpr3111109; SI-NEXT: ; implicit-def: $vgpr3211110; SI-NEXT: ; implicit-def: $vgpr3311111; SI-NEXT: ; implicit-def: $vgpr3411112; SI-NEXT: ; implicit-def: $vgpr3511113; SI-NEXT: ; implicit-def: $vgpr3611114; SI-NEXT: ; implicit-def: $vgpr1611115; SI-NEXT: ; implicit-def: $vgpr1811116; SI-NEXT: ; implicit-def: $vgpr2011117; SI-NEXT: ; implicit-def: $vgpr2211118; SI-NEXT: ; implicit-def: $vgpr2411119; SI-NEXT: ; implicit-def: $vgpr2611120; SI-NEXT: ; implicit-def: $vgpr5411121; SI-NEXT: ; implicit-def: $vgpr5311122; SI-NEXT: ; implicit-def: $vgpr5211123; SI-NEXT: ; implicit-def: $vgpr5111124; SI-NEXT: ; implicit-def: $vgpr5011125; SI-NEXT: ; implicit-def: $vgpr4911126; SI-NEXT: ; implicit-def: $vgpr4811127; SI-NEXT: ; implicit-def: $vgpr3911128; SI-NEXT: ; implicit-def: $vgpr3811129; SI-NEXT: ; implicit-def: $vgpr3711130; SI-NEXT: ; implicit-def: $vgpr2811131; SI-NEXT: ; implicit-def: $vgpr2111132; SI-NEXT: ; implicit-def: $vgpr1911133; SI-NEXT: ; implicit-def: $vgpr1711134; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]11135; SI-NEXT: s_cbranch_execz .LBB50_211136; SI-NEXT: .LBB50_4: ; %cmp.true11137; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v2911138; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v3011139; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v3111140; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3211141; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v3311142; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v3411143; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v3511144; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v3611145; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v1611146; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v1811147; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v2011148; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v2211149; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v2411150; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v2611151; SI-NEXT: v_and_b32_e32 v0, 0xffff, v011152; SI-NEXT: v_and_b32_e32 v1, 0xffff, v111153; SI-NEXT: v_and_b32_e32 v2, 0xffff, v211154; SI-NEXT: v_and_b32_e32 v3, 0xffff, v311155; SI-NEXT: v_and_b32_e32 v4, 0xffff, v411156; SI-NEXT: v_and_b32_e32 v5, 0xffff, v511157; SI-NEXT: v_and_b32_e32 v6, 0xffff, v611158; SI-NEXT: v_and_b32_e32 v7, 0xffff, v711159; SI-NEXT: v_and_b32_e32 v8, 0xffff, v811160; SI-NEXT: v_and_b32_e32 v9, 0xffff, v911161; SI-NEXT: v_and_b32_e32 v10, 0xffff, v1011162; SI-NEXT: v_and_b32_e32 v11, 0xffff, v1111163; SI-NEXT: v_and_b32_e32 v12, 0xffff, v1211164; SI-NEXT: v_and_b32_e32 v13, 0xffff, v1311165; SI-NEXT: v_or_b32_e32 v0, v54, v011166; SI-NEXT: s_mov_b32 s6, 0x3000011167; SI-NEXT: v_or_b32_e32 v1, v53, v111168; SI-NEXT: v_or_b32_e32 v2, v52, v211169; SI-NEXT: v_or_b32_e32 v3, v51, v311170; SI-NEXT: v_or_b32_e32 v4, v50, v411171; SI-NEXT: v_or_b32_e32 v5, v49, v511172; SI-NEXT: v_or_b32_e32 v6, v48, v611173; SI-NEXT: v_or_b32_e32 v7, v39, v711174; SI-NEXT: v_or_b32_e32 v8, v38, v811175; SI-NEXT: v_or_b32_e32 v9, v37, v911176; SI-NEXT: v_or_b32_e32 v10, v28, v1011177; SI-NEXT: v_or_b32_e32 v11, v21, v1111178; SI-NEXT: v_or_b32_e32 v12, v19, v1211179; SI-NEXT: v_or_b32_e32 v13, v17, v1311180; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v011181; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v111182; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v211183; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v311184; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v411185; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v511186; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v611187; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v711188; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v811189; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v911190; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v1011191; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v1111192; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v1211193; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v1311194; SI-NEXT: s_or_b64 exec, exec, s[4:5]11195; SI-NEXT: s_setpc_b64 s[30:31]11196;11197; VI-LABEL: bitcast_v28i16_to_v7f64:11198; VI: ; %bb.0:11199; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)11200; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1411201; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc11202; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]11203; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]11204; VI-NEXT: s_cbranch_execz .LBB50_211205; VI-NEXT: ; %bb.1: ; %cmp.true11206; VI-NEXT: v_mov_b32_e32 v15, 311207; VI-NEXT: v_add_u16_e32 v14, 3, v1311208; VI-NEXT: v_add_u16_sdwa v13, v13, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD11209; VI-NEXT: v_or_b32_e32 v13, v14, v1311210; VI-NEXT: v_add_u16_e32 v14, 3, v1211211; VI-NEXT: v_add_u16_sdwa v12, v12, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD11212; VI-NEXT: v_or_b32_e32 v12, v14, v1211213; VI-NEXT: v_add_u16_e32 v14, 3, v1111214; VI-NEXT: v_add_u16_sdwa v11, v11, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD11215; VI-NEXT: v_or_b32_e32 v11, v14, v1111216; VI-NEXT: v_add_u16_e32 v14, 3, v1011217; VI-NEXT: v_add_u16_sdwa v10, v10, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD11218; VI-NEXT: v_or_b32_e32 v10, v14, v1011219; VI-NEXT: v_add_u16_e32 v14, 3, v911220; VI-NEXT: v_add_u16_sdwa v9, v9, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD11221; VI-NEXT: v_or_b32_e32 v9, v14, v911222; VI-NEXT: v_add_u16_e32 v14, 3, v811223; VI-NEXT: v_add_u16_sdwa v8, v8, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD11224; VI-NEXT: v_or_b32_e32 v8, v14, v811225; VI-NEXT: v_add_u16_e32 v14, 3, v711226; VI-NEXT: v_add_u16_sdwa v7, v7, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD11227; VI-NEXT: v_or_b32_e32 v7, v14, v711228; VI-NEXT: v_add_u16_e32 v14, 3, v611229; VI-NEXT: v_add_u16_sdwa v6, v6, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD11230; VI-NEXT: v_or_b32_e32 v6, v14, v611231; VI-NEXT: v_add_u16_e32 v14, 3, v511232; VI-NEXT: v_add_u16_sdwa v5, v5, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD11233; VI-NEXT: v_or_b32_e32 v5, v14, v511234; VI-NEXT: v_add_u16_e32 v14, 3, v411235; VI-NEXT: v_add_u16_sdwa v4, v4, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD11236; VI-NEXT: v_or_b32_e32 v4, v14, v411237; VI-NEXT: v_add_u16_e32 v14, 3, v311238; VI-NEXT: v_add_u16_sdwa v3, v3, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD11239; VI-NEXT: v_or_b32_e32 v3, v14, v311240; VI-NEXT: v_add_u16_e32 v14, 3, v211241; VI-NEXT: v_add_u16_sdwa v2, v2, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD11242; VI-NEXT: v_or_b32_e32 v2, v14, v211243; VI-NEXT: v_add_u16_e32 v14, 3, v111244; VI-NEXT: v_add_u16_sdwa v1, v1, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD11245; VI-NEXT: v_or_b32_e32 v1, v14, v111246; VI-NEXT: v_add_u16_e32 v14, 3, v011247; VI-NEXT: v_add_u16_sdwa v0, v0, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD11248; VI-NEXT: v_or_b32_e32 v0, v14, v011249; VI-NEXT: .LBB50_2: ; %end11250; VI-NEXT: s_or_b64 exec, exec, s[4:5]11251; VI-NEXT: s_setpc_b64 s[30:31]11252;11253; GFX9-LABEL: bitcast_v28i16_to_v7f64:11254; GFX9: ; %bb.0:11255; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)11256; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1411257; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc11258; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]11259; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]11260; GFX9-NEXT: s_cbranch_execz .LBB50_211261; GFX9-NEXT: ; %bb.1: ; %cmp.true11262; GFX9-NEXT: v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0]11263; GFX9-NEXT: v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0]11264; GFX9-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]11265; GFX9-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]11266; GFX9-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]11267; GFX9-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]11268; GFX9-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]11269; GFX9-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]11270; GFX9-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]11271; GFX9-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]11272; GFX9-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]11273; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]11274; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]11275; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]11276; GFX9-NEXT: .LBB50_2: ; %end11277; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]11278; GFX9-NEXT: s_setpc_b64 s[30:31]11279;11280; GFX11-LABEL: bitcast_v28i16_to_v7f64:11281; GFX11: ; %bb.0:11282; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)11283; GFX11-NEXT: s_mov_b32 s0, exec_lo11284; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v1411285; GFX11-NEXT: s_xor_b32 s0, exec_lo, s011286; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)11287; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s011288; GFX11-NEXT: s_cbranch_execz .LBB50_211289; GFX11-NEXT: ; %bb.1: ; %cmp.true11290; GFX11-NEXT: v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0]11291; GFX11-NEXT: v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0]11292; GFX11-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]11293; GFX11-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]11294; GFX11-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]11295; GFX11-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]11296; GFX11-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]11297; GFX11-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]11298; GFX11-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]11299; GFX11-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]11300; GFX11-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]11301; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]11302; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]11303; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]11304; GFX11-NEXT: .LBB50_2: ; %end11305; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s011306; GFX11-NEXT: s_setpc_b64 s[30:31]11307 %cmp = icmp eq i32 %b, 011308 br i1 %cmp, label %cmp.true, label %cmp.false11309 11310cmp.true:11311 %a1 = add <28 x i16> %a, splat (i16 3)11312 %a2 = bitcast <28 x i16> %a1 to <7 x double>11313 br label %end11314 11315cmp.false:11316 %a3 = bitcast <28 x i16> %a to <7 x double>11317 br label %end11318 11319end:11320 %phi = phi <7 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]11321 ret <7 x double> %phi11322}11323 11324define inreg <7 x double> @bitcast_v28i16_to_v7f64_scalar(<28 x i16> inreg %a, i32 inreg %b) {11325; SI-LABEL: bitcast_v28i16_to_v7f64_scalar:11326; SI: ; %bb.0:11327; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)11328; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1411329; SI-NEXT: v_mov_b32_e32 v16, v1211330; SI-NEXT: v_mov_b32_e32 v17, v1011331; SI-NEXT: v_mov_b32_e32 v18, v811332; SI-NEXT: v_mov_b32_e32 v19, v611333; SI-NEXT: v_mov_b32_e32 v20, v411334; SI-NEXT: v_mov_b32_e32 v21, v211335; SI-NEXT: v_mov_b32_e32 v22, v011336; SI-NEXT: s_and_b64 s[4:5], vcc, exec11337; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v111338; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v311339; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v511340; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v711341; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v911342; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v1111343; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v1311344; SI-NEXT: s_cbranch_scc0 .LBB51_411345; SI-NEXT: ; %bb.1: ; %cmp.false11346; SI-NEXT: s_and_b32 s4, s16, 0xffff11347; SI-NEXT: s_lshl_b32 s5, s17, 1611348; SI-NEXT: s_or_b32 s4, s4, s511349; SI-NEXT: s_and_b32 s5, s18, 0xffff11350; SI-NEXT: s_lshl_b32 s6, s19, 1611351; SI-NEXT: v_and_b32_e32 v0, 0xffff, v2211352; SI-NEXT: s_or_b32 s5, s5, s611353; SI-NEXT: s_and_b32 s6, s20, 0xffff11354; SI-NEXT: s_lshl_b32 s7, s21, 1611355; SI-NEXT: v_or_b32_e32 v7, v0, v2911356; SI-NEXT: v_and_b32_e32 v0, 0xffff, v2011357; SI-NEXT: s_or_b32 s6, s6, s711358; SI-NEXT: s_and_b32 s7, s22, 0xffff11359; SI-NEXT: s_lshl_b32 s8, s23, 1611360; SI-NEXT: v_or_b32_e32 v9, v0, v2711361; SI-NEXT: v_and_b32_e32 v0, 0xffff, v1911362; SI-NEXT: s_or_b32 s7, s7, s811363; SI-NEXT: s_and_b32 s8, s24, 0xffff11364; SI-NEXT: s_lshl_b32 s9, s25, 1611365; SI-NEXT: v_or_b32_e32 v10, v0, v2611366; SI-NEXT: v_and_b32_e32 v0, 0xffff, v1811367; SI-NEXT: s_or_b32 s8, s8, s911368; SI-NEXT: s_and_b32 s9, s26, 0xffff11369; SI-NEXT: s_lshl_b32 s10, s27, 1611370; SI-NEXT: v_or_b32_e32 v11, v0, v2511371; SI-NEXT: v_and_b32_e32 v0, 0xffff, v1711372; SI-NEXT: s_or_b32 s9, s9, s1011373; SI-NEXT: s_and_b32 s10, s28, 0xffff11374; SI-NEXT: s_lshl_b32 s11, s29, 1611375; SI-NEXT: v_and_b32_e32 v1, 0xffff, v2111376; SI-NEXT: v_or_b32_e32 v12, v0, v2411377; SI-NEXT: v_and_b32_e32 v0, 0xffff, v1611378; SI-NEXT: s_or_b32 s10, s10, s1111379; SI-NEXT: v_or_b32_e32 v8, v1, v2811380; SI-NEXT: v_or_b32_e32 v13, v0, v2311381; SI-NEXT: v_mov_b32_e32 v0, s411382; SI-NEXT: v_mov_b32_e32 v1, s511383; SI-NEXT: v_mov_b32_e32 v2, s611384; SI-NEXT: v_mov_b32_e32 v3, s711385; SI-NEXT: v_mov_b32_e32 v4, s811386; SI-NEXT: v_mov_b32_e32 v5, s911387; SI-NEXT: v_mov_b32_e32 v6, s1011388; SI-NEXT: s_cbranch_execnz .LBB51_311389; SI-NEXT: .LBB51_2: ; %cmp.true11390; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v2211391; SI-NEXT: v_and_b32_e32 v0, 0xffff, v011392; SI-NEXT: v_or_b32_e32 v0, v29, v011393; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v011394; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v2111395; SI-NEXT: v_and_b32_e32 v0, 0xffff, v011396; SI-NEXT: v_or_b32_e32 v0, v28, v011397; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v011398; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v2011399; SI-NEXT: v_and_b32_e32 v0, 0xffff, v011400; SI-NEXT: v_or_b32_e32 v0, v27, v011401; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v011402; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v1911403; SI-NEXT: v_and_b32_e32 v0, 0xffff, v011404; SI-NEXT: s_add_i32 s16, s16, 311405; SI-NEXT: v_or_b32_e32 v0, v26, v011406; SI-NEXT: s_and_b32 s4, s16, 0xffff11407; SI-NEXT: s_lshl_b32 s5, s17, 1611408; SI-NEXT: s_add_i32 s18, s18, 311409; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v011410; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v1811411; SI-NEXT: s_or_b32 s4, s5, s411412; SI-NEXT: s_and_b32 s5, s18, 0xffff11413; SI-NEXT: s_lshl_b32 s6, s19, 1611414; SI-NEXT: s_add_i32 s20, s20, 311415; SI-NEXT: v_and_b32_e32 v0, 0xffff, v011416; SI-NEXT: s_or_b32 s5, s6, s511417; SI-NEXT: s_and_b32 s6, s20, 0xffff11418; SI-NEXT: s_lshl_b32 s7, s21, 1611419; SI-NEXT: s_add_i32 s22, s22, 311420; SI-NEXT: v_or_b32_e32 v0, v25, v011421; SI-NEXT: s_or_b32 s6, s7, s611422; SI-NEXT: s_and_b32 s7, s22, 0xffff11423; SI-NEXT: s_lshl_b32 s8, s23, 1611424; SI-NEXT: s_add_i32 s24, s24, 311425; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v011426; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v1711427; SI-NEXT: s_or_b32 s7, s8, s711428; SI-NEXT: s_and_b32 s8, s24, 0xffff11429; SI-NEXT: s_lshl_b32 s9, s25, 1611430; SI-NEXT: s_add_i32 s26, s26, 311431; SI-NEXT: v_and_b32_e32 v0, 0xffff, v011432; SI-NEXT: s_or_b32 s8, s9, s811433; SI-NEXT: s_and_b32 s9, s26, 0xffff11434; SI-NEXT: s_lshl_b32 s10, s27, 1611435; SI-NEXT: s_add_i32 s28, s28, 311436; SI-NEXT: v_or_b32_e32 v0, v24, v011437; SI-NEXT: s_or_b32 s9, s10, s911438; SI-NEXT: s_and_b32 s10, s28, 0xffff11439; SI-NEXT: s_lshl_b32 s11, s29, 1611440; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v011441; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v1611442; SI-NEXT: s_or_b32 s10, s11, s1011443; SI-NEXT: v_and_b32_e32 v0, 0xffff, v011444; SI-NEXT: s_add_i32 s4, s4, 0x3000011445; SI-NEXT: s_add_i32 s5, s5, 0x3000011446; SI-NEXT: s_add_i32 s6, s6, 0x3000011447; SI-NEXT: s_add_i32 s7, s7, 0x3000011448; SI-NEXT: s_add_i32 s8, s8, 0x3000011449; SI-NEXT: s_add_i32 s9, s9, 0x3000011450; SI-NEXT: s_add_i32 s10, s10, 0x3000011451; SI-NEXT: v_or_b32_e32 v0, v23, v011452; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v011453; SI-NEXT: v_mov_b32_e32 v0, s411454; SI-NEXT: v_mov_b32_e32 v1, s511455; SI-NEXT: v_mov_b32_e32 v2, s611456; SI-NEXT: v_mov_b32_e32 v3, s711457; SI-NEXT: v_mov_b32_e32 v4, s811458; SI-NEXT: v_mov_b32_e32 v5, s911459; SI-NEXT: v_mov_b32_e32 v6, s1011460; SI-NEXT: .LBB51_3: ; %end11461; SI-NEXT: s_setpc_b64 s[30:31]11462; SI-NEXT: .LBB51_4:11463; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr1511464; SI-NEXT: s_branch .LBB51_211465;11466; VI-LABEL: bitcast_v28i16_to_v7f64_scalar:11467; VI: ; %bb.0:11468; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)11469; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v011470; VI-NEXT: s_and_b64 s[4:5], vcc, exec11471; VI-NEXT: s_cbranch_scc0 .LBB51_411472; VI-NEXT: ; %bb.1: ; %cmp.false11473; VI-NEXT: s_cbranch_execnz .LBB51_311474; VI-NEXT: .LBB51_2: ; %cmp.true11475; VI-NEXT: s_add_i32 s5, s29, 311476; VI-NEXT: s_and_b32 s4, s29, 0xffff000011477; VI-NEXT: s_and_b32 s5, s5, 0xffff11478; VI-NEXT: s_or_b32 s4, s4, s511479; VI-NEXT: s_add_i32 s5, s28, 311480; VI-NEXT: s_add_i32 s29, s4, 0x3000011481; VI-NEXT: s_and_b32 s4, s28, 0xffff000011482; VI-NEXT: s_and_b32 s5, s5, 0xffff11483; VI-NEXT: s_or_b32 s4, s4, s511484; VI-NEXT: s_add_i32 s5, s27, 311485; VI-NEXT: s_add_i32 s28, s4, 0x3000011486; VI-NEXT: s_and_b32 s4, s27, 0xffff000011487; VI-NEXT: s_and_b32 s5, s5, 0xffff11488; VI-NEXT: s_or_b32 s4, s4, s511489; VI-NEXT: s_add_i32 s5, s26, 311490; VI-NEXT: s_add_i32 s27, s4, 0x3000011491; VI-NEXT: s_and_b32 s4, s26, 0xffff000011492; VI-NEXT: s_and_b32 s5, s5, 0xffff11493; VI-NEXT: s_or_b32 s4, s4, s511494; VI-NEXT: s_add_i32 s5, s25, 311495; VI-NEXT: s_add_i32 s26, s4, 0x3000011496; VI-NEXT: s_and_b32 s4, s25, 0xffff000011497; VI-NEXT: s_and_b32 s5, s5, 0xffff11498; VI-NEXT: s_or_b32 s4, s4, s511499; VI-NEXT: s_add_i32 s5, s24, 311500; VI-NEXT: s_add_i32 s25, s4, 0x3000011501; VI-NEXT: s_and_b32 s4, s24, 0xffff000011502; VI-NEXT: s_and_b32 s5, s5, 0xffff11503; VI-NEXT: s_or_b32 s4, s4, s511504; VI-NEXT: s_add_i32 s5, s23, 311505; VI-NEXT: s_add_i32 s24, s4, 0x3000011506; VI-NEXT: s_and_b32 s4, s23, 0xffff000011507; VI-NEXT: s_and_b32 s5, s5, 0xffff11508; VI-NEXT: s_or_b32 s4, s4, s511509; VI-NEXT: s_add_i32 s5, s22, 311510; VI-NEXT: s_add_i32 s23, s4, 0x3000011511; VI-NEXT: s_and_b32 s4, s22, 0xffff000011512; VI-NEXT: s_and_b32 s5, s5, 0xffff11513; VI-NEXT: s_or_b32 s4, s4, s511514; VI-NEXT: s_add_i32 s5, s21, 311515; VI-NEXT: s_add_i32 s22, s4, 0x3000011516; VI-NEXT: s_and_b32 s4, s21, 0xffff000011517; VI-NEXT: s_and_b32 s5, s5, 0xffff11518; VI-NEXT: s_or_b32 s4, s4, s511519; VI-NEXT: s_add_i32 s5, s20, 311520; VI-NEXT: s_add_i32 s21, s4, 0x3000011521; VI-NEXT: s_and_b32 s4, s20, 0xffff000011522; VI-NEXT: s_and_b32 s5, s5, 0xffff11523; VI-NEXT: s_or_b32 s4, s4, s511524; VI-NEXT: s_add_i32 s5, s19, 311525; VI-NEXT: s_add_i32 s20, s4, 0x3000011526; VI-NEXT: s_and_b32 s4, s19, 0xffff000011527; VI-NEXT: s_and_b32 s5, s5, 0xffff11528; VI-NEXT: s_or_b32 s4, s4, s511529; VI-NEXT: s_add_i32 s5, s18, 311530; VI-NEXT: s_add_i32 s19, s4, 0x3000011531; VI-NEXT: s_and_b32 s4, s18, 0xffff000011532; VI-NEXT: s_and_b32 s5, s5, 0xffff11533; VI-NEXT: s_or_b32 s4, s4, s511534; VI-NEXT: s_add_i32 s5, s17, 311535; VI-NEXT: s_add_i32 s18, s4, 0x3000011536; VI-NEXT: s_and_b32 s4, s17, 0xffff000011537; VI-NEXT: s_and_b32 s5, s5, 0xffff11538; VI-NEXT: s_or_b32 s4, s4, s511539; VI-NEXT: s_add_i32 s5, s16, 311540; VI-NEXT: s_add_i32 s17, s4, 0x3000011541; VI-NEXT: s_and_b32 s4, s16, 0xffff000011542; VI-NEXT: s_and_b32 s5, s5, 0xffff11543; VI-NEXT: s_or_b32 s4, s4, s511544; VI-NEXT: s_add_i32 s16, s4, 0x3000011545; VI-NEXT: .LBB51_3: ; %end11546; VI-NEXT: v_mov_b32_e32 v0, s1611547; VI-NEXT: v_mov_b32_e32 v1, s1711548; VI-NEXT: v_mov_b32_e32 v2, s1811549; VI-NEXT: v_mov_b32_e32 v3, s1911550; VI-NEXT: v_mov_b32_e32 v4, s2011551; VI-NEXT: v_mov_b32_e32 v5, s2111552; VI-NEXT: v_mov_b32_e32 v6, s2211553; VI-NEXT: v_mov_b32_e32 v7, s2311554; VI-NEXT: v_mov_b32_e32 v8, s2411555; VI-NEXT: v_mov_b32_e32 v9, s2511556; VI-NEXT: v_mov_b32_e32 v10, s2611557; VI-NEXT: v_mov_b32_e32 v11, s2711558; VI-NEXT: v_mov_b32_e32 v12, s2811559; VI-NEXT: v_mov_b32_e32 v13, s2911560; VI-NEXT: s_setpc_b64 s[30:31]11561; VI-NEXT: .LBB51_4:11562; VI-NEXT: s_branch .LBB51_211563;11564; GFX9-LABEL: bitcast_v28i16_to_v7f64_scalar:11565; GFX9: ; %bb.0:11566; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)11567; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v011568; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec11569; GFX9-NEXT: s_cbranch_scc0 .LBB51_311570; GFX9-NEXT: ; %bb.1: ; %cmp.false11571; GFX9-NEXT: s_cbranch_execnz .LBB51_411572; GFX9-NEXT: .LBB51_2: ; %cmp.true11573; GFX9-NEXT: v_pk_add_u16 v13, s29, 3 op_sel_hi:[1,0]11574; GFX9-NEXT: v_pk_add_u16 v12, s28, 3 op_sel_hi:[1,0]11575; GFX9-NEXT: v_pk_add_u16 v11, s27, 3 op_sel_hi:[1,0]11576; GFX9-NEXT: v_pk_add_u16 v10, s26, 3 op_sel_hi:[1,0]11577; GFX9-NEXT: v_pk_add_u16 v9, s25, 3 op_sel_hi:[1,0]11578; GFX9-NEXT: v_pk_add_u16 v8, s24, 3 op_sel_hi:[1,0]11579; GFX9-NEXT: v_pk_add_u16 v7, s23, 3 op_sel_hi:[1,0]11580; GFX9-NEXT: v_pk_add_u16 v6, s22, 3 op_sel_hi:[1,0]11581; GFX9-NEXT: v_pk_add_u16 v5, s21, 3 op_sel_hi:[1,0]11582; GFX9-NEXT: v_pk_add_u16 v4, s20, 3 op_sel_hi:[1,0]11583; GFX9-NEXT: v_pk_add_u16 v3, s19, 3 op_sel_hi:[1,0]11584; GFX9-NEXT: v_pk_add_u16 v2, s18, 3 op_sel_hi:[1,0]11585; GFX9-NEXT: v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]11586; GFX9-NEXT: v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]11587; GFX9-NEXT: s_setpc_b64 s[30:31]11588; GFX9-NEXT: .LBB51_3:11589; GFX9-NEXT: s_branch .LBB51_211590; GFX9-NEXT: .LBB51_4:11591; GFX9-NEXT: v_mov_b32_e32 v0, s1611592; GFX9-NEXT: v_mov_b32_e32 v1, s1711593; GFX9-NEXT: v_mov_b32_e32 v2, s1811594; GFX9-NEXT: v_mov_b32_e32 v3, s1911595; GFX9-NEXT: v_mov_b32_e32 v4, s2011596; GFX9-NEXT: v_mov_b32_e32 v5, s2111597; GFX9-NEXT: v_mov_b32_e32 v6, s2211598; GFX9-NEXT: v_mov_b32_e32 v7, s2311599; GFX9-NEXT: v_mov_b32_e32 v8, s2411600; GFX9-NEXT: v_mov_b32_e32 v9, s2511601; GFX9-NEXT: v_mov_b32_e32 v10, s2611602; GFX9-NEXT: v_mov_b32_e32 v11, s2711603; GFX9-NEXT: v_mov_b32_e32 v12, s2811604; GFX9-NEXT: v_mov_b32_e32 v13, s2911605; GFX9-NEXT: v_mov_b32_e32 v14, s3011606; GFX9-NEXT: v_mov_b32_e32 v15, s3111607; GFX9-NEXT: s_setpc_b64 s[30:31]11608;11609; GFX11-LABEL: bitcast_v28i16_to_v7f64_scalar:11610; GFX11: ; %bb.0:11611; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)11612; GFX11-NEXT: s_mov_b32 s15, s311613; GFX11-NEXT: s_mov_b32 s14, s211614; GFX11-NEXT: s_mov_b32 s13, s111615; GFX11-NEXT: s_mov_b32 s12, s011616; GFX11-NEXT: s_cmp_lg_u32 s26, 011617; GFX11-NEXT: s_mov_b32 s0, 011618; GFX11-NEXT: s_cbranch_scc0 .LBB51_311619; GFX11-NEXT: ; %bb.1: ; %Flow11620; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s011621; GFX11-NEXT: s_cbranch_vccnz .LBB51_411622; GFX11-NEXT: .LBB51_2: ; %cmp.true11623; GFX11-NEXT: v_pk_add_u16 v13, s25, 3 op_sel_hi:[1,0]11624; GFX11-NEXT: v_pk_add_u16 v12, s24, 3 op_sel_hi:[1,0]11625; GFX11-NEXT: v_pk_add_u16 v11, s23, 3 op_sel_hi:[1,0]11626; GFX11-NEXT: v_pk_add_u16 v10, s22, 3 op_sel_hi:[1,0]11627; GFX11-NEXT: v_pk_add_u16 v9, s21, 3 op_sel_hi:[1,0]11628; GFX11-NEXT: v_pk_add_u16 v8, s20, 3 op_sel_hi:[1,0]11629; GFX11-NEXT: v_pk_add_u16 v7, s19, 3 op_sel_hi:[1,0]11630; GFX11-NEXT: v_pk_add_u16 v6, s18, 3 op_sel_hi:[1,0]11631; GFX11-NEXT: v_pk_add_u16 v5, s17, 3 op_sel_hi:[1,0]11632; GFX11-NEXT: v_pk_add_u16 v4, s16, 3 op_sel_hi:[1,0]11633; GFX11-NEXT: v_pk_add_u16 v3, s15, 3 op_sel_hi:[1,0]11634; GFX11-NEXT: v_pk_add_u16 v2, s14, 3 op_sel_hi:[1,0]11635; GFX11-NEXT: v_pk_add_u16 v1, s13, 3 op_sel_hi:[1,0]11636; GFX11-NEXT: v_pk_add_u16 v0, s12, 3 op_sel_hi:[1,0]11637; GFX11-NEXT: s_setpc_b64 s[30:31]11638; GFX11-NEXT: .LBB51_3:11639; GFX11-NEXT: s_branch .LBB51_211640; GFX11-NEXT: .LBB51_4:11641; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s1311642; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s1511643; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s1711644; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s1911645; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s2111646; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s2311647; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s2511648; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s2711649; GFX11-NEXT: s_setpc_b64 s[30:31]11650 %cmp = icmp eq i32 %b, 011651 br i1 %cmp, label %cmp.true, label %cmp.false11652 11653cmp.true:11654 %a1 = add <28 x i16> %a, splat (i16 3)11655 %a2 = bitcast <28 x i16> %a1 to <7 x double>11656 br label %end11657 11658cmp.false:11659 %a3 = bitcast <28 x i16> %a to <7 x double>11660 br label %end11661 11662end:11663 %phi = phi <7 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]11664 ret <7 x double> %phi11665}11666 11667define <28 x half> @bitcast_v7f64_to_v28f16(<7 x double> %a, i32 %b) {11668; SI-LABEL: bitcast_v7f64_to_v28f16:11669; SI: ; %bb.0:11670; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)11671; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1411672; SI-NEXT: ; implicit-def: $vgpr4811673; SI-NEXT: ; implicit-def: $vgpr4911674; SI-NEXT: ; implicit-def: $vgpr3911675; SI-NEXT: ; implicit-def: $vgpr3811676; SI-NEXT: ; implicit-def: $vgpr3711677; SI-NEXT: ; implicit-def: $vgpr3511678; SI-NEXT: ; implicit-def: $vgpr3611679; SI-NEXT: ; implicit-def: $vgpr3311680; SI-NEXT: ; implicit-def: $vgpr3411681; SI-NEXT: ; implicit-def: $vgpr3011682; SI-NEXT: ; implicit-def: $vgpr3211683; SI-NEXT: ; implicit-def: $vgpr2811684; SI-NEXT: ; implicit-def: $vgpr3111685; SI-NEXT: ; implicit-def: $vgpr2911686; SI-NEXT: ; implicit-def: $vgpr1411687; SI-NEXT: ; implicit-def: $vgpr1511688; SI-NEXT: ; implicit-def: $vgpr1611689; SI-NEXT: ; implicit-def: $vgpr1711690; SI-NEXT: ; implicit-def: $vgpr1811691; SI-NEXT: ; implicit-def: $vgpr1911692; SI-NEXT: ; implicit-def: $vgpr2011693; SI-NEXT: ; implicit-def: $vgpr2111694; SI-NEXT: ; implicit-def: $vgpr2211695; SI-NEXT: ; implicit-def: $vgpr2311696; SI-NEXT: ; implicit-def: $vgpr2411697; SI-NEXT: ; implicit-def: $vgpr2511698; SI-NEXT: ; implicit-def: $vgpr2611699; SI-NEXT: ; implicit-def: $vgpr2711700; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc11701; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]11702; SI-NEXT: s_cbranch_execz .LBB52_211703; SI-NEXT: ; %bb.1: ; %cmp.false11704; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v1311705; SI-NEXT: v_cvt_f32_f16_e32 v27, v1411706; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v1211707; SI-NEXT: v_cvt_f32_f16_e32 v25, v1411708; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v1111709; SI-NEXT: v_cvt_f32_f16_e32 v23, v1411710; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v1011711; SI-NEXT: v_cvt_f32_f16_e32 v21, v1411712; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v911713; SI-NEXT: v_cvt_f32_f16_e32 v19, v1411714; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v811715; SI-NEXT: v_cvt_f32_f16_e32 v17, v1411716; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v711717; SI-NEXT: v_cvt_f32_f16_e32 v15, v1411718; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v611719; SI-NEXT: v_cvt_f32_f16_e32 v29, v1411720; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v511721; SI-NEXT: v_cvt_f32_f16_e32 v28, v1411722; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v411723; SI-NEXT: v_cvt_f32_f16_e32 v30, v1411724; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v311725; SI-NEXT: v_cvt_f32_f16_e32 v33, v1411726; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v211727; SI-NEXT: v_cvt_f32_f16_e32 v35, v1411728; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v111729; SI-NEXT: v_cvt_f32_f16_e32 v38, v1411730; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v011731; SI-NEXT: v_cvt_f32_f16_e32 v49, v1411732; SI-NEXT: v_cvt_f32_f16_e32 v26, v1311733; SI-NEXT: v_cvt_f32_f16_e32 v24, v1211734; SI-NEXT: v_cvt_f32_f16_e32 v22, v1111735; SI-NEXT: v_cvt_f32_f16_e32 v20, v1011736; SI-NEXT: v_cvt_f32_f16_e32 v18, v911737; SI-NEXT: v_cvt_f32_f16_e32 v16, v811738; SI-NEXT: v_cvt_f32_f16_e32 v14, v711739; SI-NEXT: v_cvt_f32_f16_e32 v31, v611740; SI-NEXT: v_cvt_f32_f16_e32 v32, v511741; SI-NEXT: v_cvt_f32_f16_e32 v34, v411742; SI-NEXT: v_cvt_f32_f16_e32 v36, v311743; SI-NEXT: v_cvt_f32_f16_e32 v37, v211744; SI-NEXT: v_cvt_f32_f16_e32 v39, v111745; SI-NEXT: v_cvt_f32_f16_e32 v48, v011746; SI-NEXT: ; implicit-def: $vgpr011747; SI-NEXT: ; implicit-def: $vgpr211748; SI-NEXT: ; implicit-def: $vgpr411749; SI-NEXT: ; implicit-def: $vgpr611750; SI-NEXT: ; implicit-def: $vgpr811751; SI-NEXT: ; implicit-def: $vgpr1011752; SI-NEXT: ; implicit-def: $vgpr1211753; SI-NEXT: .LBB52_2: ; %Flow11754; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]11755; SI-NEXT: s_cbranch_execz .LBB52_411756; SI-NEXT: ; %bb.3: ; %cmp.true11757; SI-NEXT: v_add_f64 v[0:1], v[0:1], 1.011758; SI-NEXT: v_add_f64 v[2:3], v[2:3], 1.011759; SI-NEXT: v_add_f64 v[4:5], v[4:5], 1.011760; SI-NEXT: v_add_f64 v[6:7], v[6:7], 1.011761; SI-NEXT: v_add_f64 v[8:9], v[8:9], 1.011762; SI-NEXT: v_add_f64 v[10:11], v[10:11], 1.011763; SI-NEXT: v_add_f64 v[12:13], v[12:13], 1.011764; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v011765; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v111766; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v211767; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v311768; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v411769; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v511770; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v611771; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v711772; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v811773; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v911774; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v1011775; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v1111776; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v1211777; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v1311778; SI-NEXT: v_cvt_f32_f16_e32 v26, v1311779; SI-NEXT: v_cvt_f32_f16_e32 v24, v1211780; SI-NEXT: v_cvt_f32_f16_e32 v22, v1111781; SI-NEXT: v_cvt_f32_f16_e32 v20, v1011782; SI-NEXT: v_cvt_f32_f16_e32 v18, v911783; SI-NEXT: v_cvt_f32_f16_e32 v16, v811784; SI-NEXT: v_cvt_f32_f16_e32 v14, v711785; SI-NEXT: v_cvt_f32_f16_e32 v31, v611786; SI-NEXT: v_cvt_f32_f16_e32 v32, v511787; SI-NEXT: v_cvt_f32_f16_e32 v34, v411788; SI-NEXT: v_cvt_f32_f16_e32 v36, v311789; SI-NEXT: v_cvt_f32_f16_e32 v37, v211790; SI-NEXT: v_cvt_f32_f16_e32 v39, v111791; SI-NEXT: v_cvt_f32_f16_e32 v48, v011792; SI-NEXT: v_cvt_f32_f16_e32 v27, v2711793; SI-NEXT: v_cvt_f32_f16_e32 v25, v2511794; SI-NEXT: v_cvt_f32_f16_e32 v23, v2311795; SI-NEXT: v_cvt_f32_f16_e32 v21, v2111796; SI-NEXT: v_cvt_f32_f16_e32 v19, v1911797; SI-NEXT: v_cvt_f32_f16_e32 v17, v1711798; SI-NEXT: v_cvt_f32_f16_e32 v15, v1511799; SI-NEXT: v_cvt_f32_f16_e32 v29, v2911800; SI-NEXT: v_cvt_f32_f16_e32 v28, v2811801; SI-NEXT: v_cvt_f32_f16_e32 v30, v3011802; SI-NEXT: v_cvt_f32_f16_e32 v33, v3311803; SI-NEXT: v_cvt_f32_f16_e32 v35, v3511804; SI-NEXT: v_cvt_f32_f16_e32 v38, v3811805; SI-NEXT: v_cvt_f32_f16_e32 v49, v4911806; SI-NEXT: .LBB52_4: ; %end11807; SI-NEXT: s_or_b64 exec, exec, s[4:5]11808; SI-NEXT: v_mov_b32_e32 v0, v4811809; SI-NEXT: v_mov_b32_e32 v1, v4911810; SI-NEXT: v_mov_b32_e32 v2, v3911811; SI-NEXT: v_mov_b32_e32 v3, v3811812; SI-NEXT: v_mov_b32_e32 v4, v3711813; SI-NEXT: v_mov_b32_e32 v5, v3511814; SI-NEXT: v_mov_b32_e32 v6, v3611815; SI-NEXT: v_mov_b32_e32 v7, v3311816; SI-NEXT: v_mov_b32_e32 v8, v3411817; SI-NEXT: v_mov_b32_e32 v9, v3011818; SI-NEXT: v_mov_b32_e32 v10, v3211819; SI-NEXT: v_mov_b32_e32 v11, v2811820; SI-NEXT: v_mov_b32_e32 v12, v3111821; SI-NEXT: v_mov_b32_e32 v13, v2911822; SI-NEXT: s_setpc_b64 s[30:31]11823;11824; VI-LABEL: bitcast_v7f64_to_v28f16:11825; VI: ; %bb.0:11826; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)11827; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1411828; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc11829; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]11830; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]11831; VI-NEXT: s_cbranch_execz .LBB52_211832; VI-NEXT: ; %bb.1: ; %cmp.true11833; VI-NEXT: v_add_f64 v[12:13], v[12:13], 1.011834; VI-NEXT: v_add_f64 v[10:11], v[10:11], 1.011835; VI-NEXT: v_add_f64 v[8:9], v[8:9], 1.011836; VI-NEXT: v_add_f64 v[6:7], v[6:7], 1.011837; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.011838; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.011839; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.011840; VI-NEXT: .LBB52_2: ; %end11841; VI-NEXT: s_or_b64 exec, exec, s[4:5]11842; VI-NEXT: s_setpc_b64 s[30:31]11843;11844; GFX9-LABEL: bitcast_v7f64_to_v28f16:11845; GFX9: ; %bb.0:11846; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)11847; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1411848; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc11849; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]11850; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]11851; GFX9-NEXT: s_cbranch_execz .LBB52_211852; GFX9-NEXT: ; %bb.1: ; %cmp.true11853; GFX9-NEXT: v_add_f64 v[12:13], v[12:13], 1.011854; GFX9-NEXT: v_add_f64 v[10:11], v[10:11], 1.011855; GFX9-NEXT: v_add_f64 v[8:9], v[8:9], 1.011856; GFX9-NEXT: v_add_f64 v[6:7], v[6:7], 1.011857; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.011858; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.011859; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.011860; GFX9-NEXT: .LBB52_2: ; %end11861; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]11862; GFX9-NEXT: s_setpc_b64 s[30:31]11863;11864; GFX11-LABEL: bitcast_v7f64_to_v28f16:11865; GFX11: ; %bb.0:11866; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)11867; GFX11-NEXT: s_mov_b32 s0, exec_lo11868; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v1411869; GFX11-NEXT: s_xor_b32 s0, exec_lo, s011870; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)11871; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s011872; GFX11-NEXT: s_cbranch_execz .LBB52_211873; GFX11-NEXT: ; %bb.1: ; %cmp.true11874; GFX11-NEXT: v_add_f64 v[12:13], v[12:13], 1.011875; GFX11-NEXT: v_add_f64 v[10:11], v[10:11], 1.011876; GFX11-NEXT: v_add_f64 v[8:9], v[8:9], 1.011877; GFX11-NEXT: v_add_f64 v[6:7], v[6:7], 1.011878; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.011879; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.011880; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.011881; GFX11-NEXT: .LBB52_2: ; %end11882; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s011883; GFX11-NEXT: s_setpc_b64 s[30:31]11884 %cmp = icmp eq i32 %b, 011885 br i1 %cmp, label %cmp.true, label %cmp.false11886 11887cmp.true:11888 %a1 = fadd <7 x double> %a, splat (double 1.000000e+00)11889 %a2 = bitcast <7 x double> %a1 to <28 x half>11890 br label %end11891 11892cmp.false:11893 %a3 = bitcast <7 x double> %a to <28 x half>11894 br label %end11895 11896end:11897 %phi = phi <28 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]11898 ret <28 x half> %phi11899}11900 11901define inreg <28 x half> @bitcast_v7f64_to_v28f16_scalar(<7 x double> inreg %a, i32 inreg %b) {11902; SI-LABEL: bitcast_v7f64_to_v28f16_scalar:11903; SI: ; %bb.0:11904; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)11905; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v011906; SI-NEXT: s_and_b64 s[4:5], vcc, exec11907; SI-NEXT: s_cbranch_scc0 .LBB53_411908; SI-NEXT: ; %bb.1: ; %cmp.false11909; SI-NEXT: s_lshr_b32 s4, s29, 1611910; SI-NEXT: v_cvt_f32_f16_e32 v27, s411911; SI-NEXT: s_lshr_b32 s4, s28, 1611912; SI-NEXT: v_cvt_f32_f16_e32 v25, s411913; SI-NEXT: s_lshr_b32 s4, s27, 1611914; SI-NEXT: v_cvt_f32_f16_e32 v23, s411915; SI-NEXT: s_lshr_b32 s4, s26, 1611916; SI-NEXT: v_cvt_f32_f16_e32 v21, s411917; SI-NEXT: s_lshr_b32 s4, s25, 1611918; SI-NEXT: v_cvt_f32_f16_e32 v19, s411919; SI-NEXT: s_lshr_b32 s4, s24, 1611920; SI-NEXT: v_cvt_f32_f16_e32 v17, s411921; SI-NEXT: s_lshr_b32 s4, s23, 1611922; SI-NEXT: v_cvt_f32_f16_e32 v15, s411923; SI-NEXT: s_lshr_b32 s4, s22, 1611924; SI-NEXT: v_cvt_f32_f16_e32 v13, s411925; SI-NEXT: s_lshr_b32 s4, s21, 1611926; SI-NEXT: v_cvt_f32_f16_e32 v11, s411927; SI-NEXT: s_lshr_b32 s4, s20, 1611928; SI-NEXT: v_cvt_f32_f16_e32 v9, s411929; SI-NEXT: s_lshr_b32 s4, s19, 1611930; SI-NEXT: v_cvt_f32_f16_e32 v7, s411931; SI-NEXT: s_lshr_b32 s4, s18, 1611932; SI-NEXT: v_cvt_f32_f16_e32 v5, s411933; SI-NEXT: s_lshr_b32 s4, s17, 1611934; SI-NEXT: v_cvt_f32_f16_e32 v3, s411935; SI-NEXT: s_lshr_b32 s4, s16, 1611936; SI-NEXT: v_cvt_f32_f16_e32 v1, s411937; SI-NEXT: v_cvt_f32_f16_e32 v26, s2911938; SI-NEXT: v_cvt_f32_f16_e32 v24, s2811939; SI-NEXT: v_cvt_f32_f16_e32 v22, s2711940; SI-NEXT: v_cvt_f32_f16_e32 v20, s2611941; SI-NEXT: v_cvt_f32_f16_e32 v18, s2511942; SI-NEXT: v_cvt_f32_f16_e32 v16, s2411943; SI-NEXT: v_cvt_f32_f16_e32 v14, s2311944; SI-NEXT: v_cvt_f32_f16_e32 v12, s2211945; SI-NEXT: v_cvt_f32_f16_e32 v10, s2111946; SI-NEXT: v_cvt_f32_f16_e32 v8, s2011947; SI-NEXT: v_cvt_f32_f16_e32 v6, s1911948; SI-NEXT: v_cvt_f32_f16_e32 v4, s1811949; SI-NEXT: v_cvt_f32_f16_e32 v2, s1711950; SI-NEXT: v_cvt_f32_f16_e32 v0, s1611951; SI-NEXT: s_cbranch_execnz .LBB53_311952; SI-NEXT: .LBB53_2: ; %cmp.true11953; SI-NEXT: v_add_f64 v[0:1], s[16:17], 1.011954; SI-NEXT: v_add_f64 v[2:3], s[18:19], 1.011955; SI-NEXT: v_add_f64 v[4:5], s[20:21], 1.011956; SI-NEXT: v_add_f64 v[6:7], s[22:23], 1.011957; SI-NEXT: v_add_f64 v[8:9], s[24:25], 1.011958; SI-NEXT: v_add_f64 v[10:11], s[26:27], 1.011959; SI-NEXT: v_add_f64 v[12:13], s[28:29], 1.011960; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v011961; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v211962; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v311963; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v411964; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v511965; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v611966; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v711967; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v811968; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v911969; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v1011970; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v1111971; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v1211972; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v1311973; SI-NEXT: v_cvt_f32_f16_e32 v24, v1211974; SI-NEXT: v_cvt_f32_f16_e32 v12, v611975; SI-NEXT: v_cvt_f32_f16_e32 v6, v311976; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v111977; SI-NEXT: v_cvt_f32_f16_e32 v26, v1311978; SI-NEXT: v_cvt_f32_f16_e32 v22, v1111979; SI-NEXT: v_cvt_f32_f16_e32 v20, v1011980; SI-NEXT: v_cvt_f32_f16_e32 v18, v911981; SI-NEXT: v_cvt_f32_f16_e32 v16, v811982; SI-NEXT: v_cvt_f32_f16_e32 v14, v711983; SI-NEXT: v_cvt_f32_f16_e32 v10, v511984; SI-NEXT: v_cvt_f32_f16_e32 v8, v411985; SI-NEXT: v_cvt_f32_f16_e32 v4, v211986; SI-NEXT: v_cvt_f32_f16_e32 v2, v111987; SI-NEXT: v_cvt_f32_f16_e32 v0, v011988; SI-NEXT: v_cvt_f32_f16_e32 v27, v2711989; SI-NEXT: v_cvt_f32_f16_e32 v25, v2511990; SI-NEXT: v_cvt_f32_f16_e32 v23, v2311991; SI-NEXT: v_cvt_f32_f16_e32 v21, v2111992; SI-NEXT: v_cvt_f32_f16_e32 v19, v1911993; SI-NEXT: v_cvt_f32_f16_e32 v17, v1711994; SI-NEXT: v_cvt_f32_f16_e32 v15, v1511995; SI-NEXT: v_cvt_f32_f16_e32 v13, v3311996; SI-NEXT: v_cvt_f32_f16_e32 v11, v3211997; SI-NEXT: v_cvt_f32_f16_e32 v9, v3111998; SI-NEXT: v_cvt_f32_f16_e32 v7, v3011999; SI-NEXT: v_cvt_f32_f16_e32 v5, v2912000; SI-NEXT: v_cvt_f32_f16_e32 v3, v312001; SI-NEXT: v_cvt_f32_f16_e32 v1, v2812002; SI-NEXT: .LBB53_3: ; %end12003; SI-NEXT: s_setpc_b64 s[30:31]12004; SI-NEXT: .LBB53_4:12005; SI-NEXT: ; implicit-def: $vgpr012006; SI-NEXT: ; implicit-def: $vgpr112007; SI-NEXT: ; implicit-def: $vgpr212008; SI-NEXT: ; implicit-def: $vgpr312009; SI-NEXT: ; implicit-def: $vgpr412010; SI-NEXT: ; implicit-def: $vgpr512011; SI-NEXT: ; implicit-def: $vgpr612012; SI-NEXT: ; implicit-def: $vgpr712013; SI-NEXT: ; implicit-def: $vgpr812014; SI-NEXT: ; implicit-def: $vgpr912015; SI-NEXT: ; implicit-def: $vgpr1012016; SI-NEXT: ; implicit-def: $vgpr1112017; SI-NEXT: ; implicit-def: $vgpr1212018; SI-NEXT: ; implicit-def: $vgpr1312019; SI-NEXT: ; implicit-def: $vgpr1412020; SI-NEXT: ; implicit-def: $vgpr1512021; SI-NEXT: ; implicit-def: $vgpr1612022; SI-NEXT: ; implicit-def: $vgpr1712023; SI-NEXT: ; implicit-def: $vgpr1812024; SI-NEXT: ; implicit-def: $vgpr1912025; SI-NEXT: ; implicit-def: $vgpr2012026; SI-NEXT: ; implicit-def: $vgpr2112027; SI-NEXT: ; implicit-def: $vgpr2212028; SI-NEXT: ; implicit-def: $vgpr2312029; SI-NEXT: ; implicit-def: $vgpr2412030; SI-NEXT: ; implicit-def: $vgpr2512031; SI-NEXT: ; implicit-def: $vgpr2612032; SI-NEXT: ; implicit-def: $vgpr2712033; SI-NEXT: s_branch .LBB53_212034;12035; VI-LABEL: bitcast_v7f64_to_v28f16_scalar:12036; VI: ; %bb.0:12037; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12038; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v012039; VI-NEXT: s_and_b64 s[4:5], vcc, exec12040; VI-NEXT: s_cbranch_scc0 .LBB53_312041; VI-NEXT: ; %bb.1: ; %cmp.false12042; VI-NEXT: s_cbranch_execnz .LBB53_412043; VI-NEXT: .LBB53_2: ; %cmp.true12044; VI-NEXT: v_add_f64 v[12:13], s[28:29], 1.012045; VI-NEXT: v_add_f64 v[10:11], s[26:27], 1.012046; VI-NEXT: v_add_f64 v[8:9], s[24:25], 1.012047; VI-NEXT: v_add_f64 v[6:7], s[22:23], 1.012048; VI-NEXT: v_add_f64 v[4:5], s[20:21], 1.012049; VI-NEXT: v_add_f64 v[2:3], s[18:19], 1.012050; VI-NEXT: v_add_f64 v[0:1], s[16:17], 1.012051; VI-NEXT: s_setpc_b64 s[30:31]12052; VI-NEXT: .LBB53_3:12053; VI-NEXT: s_branch .LBB53_212054; VI-NEXT: .LBB53_4:12055; VI-NEXT: v_mov_b32_e32 v0, s1612056; VI-NEXT: v_mov_b32_e32 v1, s1712057; VI-NEXT: v_mov_b32_e32 v2, s1812058; VI-NEXT: v_mov_b32_e32 v3, s1912059; VI-NEXT: v_mov_b32_e32 v4, s2012060; VI-NEXT: v_mov_b32_e32 v5, s2112061; VI-NEXT: v_mov_b32_e32 v6, s2212062; VI-NEXT: v_mov_b32_e32 v7, s2312063; VI-NEXT: v_mov_b32_e32 v8, s2412064; VI-NEXT: v_mov_b32_e32 v9, s2512065; VI-NEXT: v_mov_b32_e32 v10, s2612066; VI-NEXT: v_mov_b32_e32 v11, s2712067; VI-NEXT: v_mov_b32_e32 v12, s2812068; VI-NEXT: v_mov_b32_e32 v13, s2912069; VI-NEXT: v_mov_b32_e32 v14, s3012070; VI-NEXT: v_mov_b32_e32 v15, s3112071; VI-NEXT: s_setpc_b64 s[30:31]12072;12073; GFX9-LABEL: bitcast_v7f64_to_v28f16_scalar:12074; GFX9: ; %bb.0:12075; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12076; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v012077; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec12078; GFX9-NEXT: s_cbranch_scc0 .LBB53_312079; GFX9-NEXT: ; %bb.1: ; %cmp.false12080; GFX9-NEXT: s_cbranch_execnz .LBB53_412081; GFX9-NEXT: .LBB53_2: ; %cmp.true12082; GFX9-NEXT: v_add_f64 v[12:13], s[28:29], 1.012083; GFX9-NEXT: v_add_f64 v[10:11], s[26:27], 1.012084; GFX9-NEXT: v_add_f64 v[8:9], s[24:25], 1.012085; GFX9-NEXT: v_add_f64 v[6:7], s[22:23], 1.012086; GFX9-NEXT: v_add_f64 v[4:5], s[20:21], 1.012087; GFX9-NEXT: v_add_f64 v[2:3], s[18:19], 1.012088; GFX9-NEXT: v_add_f64 v[0:1], s[16:17], 1.012089; GFX9-NEXT: s_setpc_b64 s[30:31]12090; GFX9-NEXT: .LBB53_3:12091; GFX9-NEXT: s_branch .LBB53_212092; GFX9-NEXT: .LBB53_4:12093; GFX9-NEXT: v_mov_b32_e32 v0, s1612094; GFX9-NEXT: v_mov_b32_e32 v1, s1712095; GFX9-NEXT: v_mov_b32_e32 v2, s1812096; GFX9-NEXT: v_mov_b32_e32 v3, s1912097; GFX9-NEXT: v_mov_b32_e32 v4, s2012098; GFX9-NEXT: v_mov_b32_e32 v5, s2112099; GFX9-NEXT: v_mov_b32_e32 v6, s2212100; GFX9-NEXT: v_mov_b32_e32 v7, s2312101; GFX9-NEXT: v_mov_b32_e32 v8, s2412102; GFX9-NEXT: v_mov_b32_e32 v9, s2512103; GFX9-NEXT: v_mov_b32_e32 v10, s2612104; GFX9-NEXT: v_mov_b32_e32 v11, s2712105; GFX9-NEXT: v_mov_b32_e32 v12, s2812106; GFX9-NEXT: v_mov_b32_e32 v13, s2912107; GFX9-NEXT: v_mov_b32_e32 v14, s3012108; GFX9-NEXT: v_mov_b32_e32 v15, s3112109; GFX9-NEXT: s_setpc_b64 s[30:31]12110;12111; GFX11-LABEL: bitcast_v7f64_to_v28f16_scalar:12112; GFX11: ; %bb.0:12113; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12114; GFX11-NEXT: s_mov_b32 s15, s312115; GFX11-NEXT: s_mov_b32 s14, s212116; GFX11-NEXT: s_mov_b32 s13, s112117; GFX11-NEXT: s_mov_b32 s12, s012118; GFX11-NEXT: s_cmp_lg_u32 s26, 012119; GFX11-NEXT: s_mov_b32 s0, 012120; GFX11-NEXT: s_cbranch_scc0 .LBB53_312121; GFX11-NEXT: ; %bb.1: ; %Flow12122; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s012123; GFX11-NEXT: s_cbranch_vccnz .LBB53_412124; GFX11-NEXT: .LBB53_2: ; %cmp.true12125; GFX11-NEXT: v_add_f64 v[12:13], s[24:25], 1.012126; GFX11-NEXT: v_add_f64 v[10:11], s[22:23], 1.012127; GFX11-NEXT: v_add_f64 v[8:9], s[20:21], 1.012128; GFX11-NEXT: v_add_f64 v[6:7], s[18:19], 1.012129; GFX11-NEXT: v_add_f64 v[4:5], s[16:17], 1.012130; GFX11-NEXT: v_add_f64 v[2:3], s[14:15], 1.012131; GFX11-NEXT: v_add_f64 v[0:1], s[12:13], 1.012132; GFX11-NEXT: s_setpc_b64 s[30:31]12133; GFX11-NEXT: .LBB53_3:12134; GFX11-NEXT: s_branch .LBB53_212135; GFX11-NEXT: .LBB53_4:12136; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s1312137; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s1512138; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s1712139; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s1912140; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s2112141; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s2312142; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s2512143; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s2712144; GFX11-NEXT: s_setpc_b64 s[30:31]12145 %cmp = icmp eq i32 %b, 012146 br i1 %cmp, label %cmp.true, label %cmp.false12147 12148cmp.true:12149 %a1 = fadd <7 x double> %a, splat (double 1.000000e+00)12150 %a2 = bitcast <7 x double> %a1 to <28 x half>12151 br label %end12152 12153cmp.false:12154 %a3 = bitcast <7 x double> %a to <28 x half>12155 br label %end12156 12157end:12158 %phi = phi <28 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]12159 ret <28 x half> %phi12160}12161 12162define <7 x double> @bitcast_v28f16_to_v7f64(<28 x half> %a, i32 %b) {12163; SI-LABEL: bitcast_v28f16_to_v7f64:12164; SI: ; %bb.0:12165; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12166; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill12167; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill12168; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 ; 4-byte Folded Spill12169; SI-NEXT: s_waitcnt expcnt(0)12170; SI-NEXT: v_cvt_f16_f32_e32 v42, v112171; SI-NEXT: v_cvt_f16_f32_e32 v41, v012172; SI-NEXT: v_cvt_f16_f32_e32 v40, v312173; SI-NEXT: v_cvt_f16_f32_e32 v55, v212174; SI-NEXT: v_cvt_f16_f32_e32 v54, v512175; SI-NEXT: v_cvt_f16_f32_e32 v53, v412176; SI-NEXT: v_cvt_f16_f32_e32 v52, v712177; SI-NEXT: v_cvt_f16_f32_e32 v51, v612178; SI-NEXT: v_cvt_f16_f32_e32 v50, v912179; SI-NEXT: v_cvt_f16_f32_e32 v49, v812180; SI-NEXT: v_cvt_f16_f32_e32 v48, v1112181; SI-NEXT: v_cvt_f16_f32_e32 v39, v1012182; SI-NEXT: v_cvt_f16_f32_e32 v38, v1312183; SI-NEXT: v_cvt_f16_f32_e32 v37, v1212184; SI-NEXT: v_cvt_f16_f32_e32 v36, v1512185; SI-NEXT: v_cvt_f16_f32_e32 v35, v1412186; SI-NEXT: v_cvt_f16_f32_e32 v34, v1712187; SI-NEXT: v_cvt_f16_f32_e32 v33, v1612188; SI-NEXT: v_cvt_f16_f32_e32 v32, v1912189; SI-NEXT: v_cvt_f16_f32_e32 v31, v1812190; SI-NEXT: v_cvt_f16_f32_e32 v30, v2112191; SI-NEXT: v_cvt_f16_f32_e32 v29, v2012192; SI-NEXT: v_cvt_f16_f32_e32 v21, v2312193; SI-NEXT: v_cvt_f16_f32_e32 v20, v2212194; SI-NEXT: v_cvt_f16_f32_e32 v19, v2512195; SI-NEXT: v_cvt_f16_f32_e32 v18, v2412196; SI-NEXT: v_cvt_f16_f32_e32 v17, v2712197; SI-NEXT: v_cvt_f16_f32_e32 v16, v2612198; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2812199; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr1512200; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc12201; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]12202; SI-NEXT: s_cbranch_execz .LBB54_212203; SI-NEXT: ; %bb.1: ; %cmp.false12204; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v4212205; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v4012206; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v5412207; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v5212208; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v5012209; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v4812210; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v3812211; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v3612212; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v3412213; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v3212214; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v3012215; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v2112216; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v1912217; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v1712218; SI-NEXT: v_or_b32_e32 v0, v41, v012219; SI-NEXT: v_or_b32_e32 v1, v55, v112220; SI-NEXT: v_or_b32_e32 v2, v53, v212221; SI-NEXT: v_or_b32_e32 v3, v51, v312222; SI-NEXT: v_or_b32_e32 v4, v49, v412223; SI-NEXT: v_or_b32_e32 v5, v39, v512224; SI-NEXT: v_or_b32_e32 v6, v37, v612225; SI-NEXT: v_or_b32_e32 v7, v35, v712226; SI-NEXT: v_or_b32_e32 v8, v33, v812227; SI-NEXT: v_or_b32_e32 v9, v31, v912228; SI-NEXT: v_or_b32_e32 v10, v29, v1012229; SI-NEXT: v_or_b32_e32 v11, v20, v1112230; SI-NEXT: v_or_b32_e32 v12, v18, v1212231; SI-NEXT: v_or_b32_e32 v13, v16, v1312232; SI-NEXT: ; implicit-def: $vgpr4212233; SI-NEXT: ; implicit-def: $vgpr4112234; SI-NEXT: ; implicit-def: $vgpr4012235; SI-NEXT: ; implicit-def: $vgpr5512236; SI-NEXT: ; implicit-def: $vgpr5412237; SI-NEXT: ; implicit-def: $vgpr5312238; SI-NEXT: ; implicit-def: $vgpr5212239; SI-NEXT: ; implicit-def: $vgpr5112240; SI-NEXT: ; implicit-def: $vgpr5012241; SI-NEXT: ; implicit-def: $vgpr4912242; SI-NEXT: ; implicit-def: $vgpr4812243; SI-NEXT: ; implicit-def: $vgpr3912244; SI-NEXT: ; implicit-def: $vgpr3812245; SI-NEXT: ; implicit-def: $vgpr3712246; SI-NEXT: ; implicit-def: $vgpr3612247; SI-NEXT: ; implicit-def: $vgpr3512248; SI-NEXT: ; implicit-def: $vgpr3412249; SI-NEXT: ; implicit-def: $vgpr3312250; SI-NEXT: ; implicit-def: $vgpr3212251; SI-NEXT: ; implicit-def: $vgpr3112252; SI-NEXT: ; implicit-def: $vgpr3012253; SI-NEXT: ; implicit-def: $vgpr2912254; SI-NEXT: ; implicit-def: $vgpr2112255; SI-NEXT: ; implicit-def: $vgpr2012256; SI-NEXT: ; implicit-def: $vgpr1912257; SI-NEXT: ; implicit-def: $vgpr1812258; SI-NEXT: ; implicit-def: $vgpr1712259; SI-NEXT: ; implicit-def: $vgpr1612260; SI-NEXT: .LBB54_2: ; %Flow12261; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]12262; SI-NEXT: s_cbranch_execz .LBB54_412263; SI-NEXT: ; %bb.3: ; %cmp.true12264; SI-NEXT: v_cvt_f32_f16_e32 v0, v4212265; SI-NEXT: v_cvt_f32_f16_e32 v1, v4112266; SI-NEXT: v_cvt_f32_f16_e32 v2, v4012267; SI-NEXT: v_cvt_f32_f16_e32 v3, v5512268; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v012269; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v112270; SI-NEXT: v_cvt_f16_f32_e32 v0, v012271; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v212272; SI-NEXT: v_cvt_f16_f32_e32 v1, v112273; SI-NEXT: v_cvt_f16_f32_e32 v2, v212274; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v012275; SI-NEXT: v_cvt_f32_f16_e32 v4, v5312276; SI-NEXT: v_or_b32_e32 v0, v1, v012277; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v212278; SI-NEXT: v_cvt_f32_f16_e32 v2, v5412279; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v312280; SI-NEXT: v_cvt_f16_f32_e32 v3, v312281; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v412282; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v212283; SI-NEXT: v_cvt_f16_f32_e32 v2, v212284; SI-NEXT: v_cvt_f16_f32_e32 v4, v412285; SI-NEXT: v_or_b32_e32 v1, v3, v112286; SI-NEXT: v_cvt_f32_f16_e32 v3, v5212287; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v212288; SI-NEXT: v_or_b32_e32 v2, v4, v212289; SI-NEXT: v_cvt_f32_f16_e32 v4, v5112290; SI-NEXT: v_cvt_f32_f16_e32 v5, v5012291; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v312292; SI-NEXT: v_cvt_f16_f32_e32 v3, v312293; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v412294; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v512295; SI-NEXT: v_cvt_f16_f32_e32 v4, v412296; SI-NEXT: v_cvt_f16_f32_e32 v5, v512297; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v312298; SI-NEXT: v_cvt_f32_f16_e32 v6, v4912299; SI-NEXT: v_or_b32_e32 v3, v4, v312300; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v512301; SI-NEXT: v_cvt_f32_f16_e32 v5, v4812302; SI-NEXT: v_cvt_f32_f16_e32 v7, v3912303; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v612304; SI-NEXT: v_cvt_f16_f32_e32 v6, v612305; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v512306; SI-NEXT: v_cvt_f16_f32_e32 v5, v512307; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v712308; SI-NEXT: v_cvt_f16_f32_e32 v7, v712309; SI-NEXT: v_or_b32_e32 v4, v6, v412310; SI-NEXT: v_cvt_f32_f16_e32 v6, v3812311; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v512312; SI-NEXT: v_or_b32_e32 v5, v7, v512313; SI-NEXT: v_cvt_f32_f16_e32 v7, v3712314; SI-NEXT: v_cvt_f32_f16_e32 v8, v3612315; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v612316; SI-NEXT: v_cvt_f16_f32_e32 v6, v612317; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v712318; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v812319; SI-NEXT: v_cvt_f16_f32_e32 v7, v712320; SI-NEXT: v_cvt_f16_f32_e32 v8, v812321; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v612322; SI-NEXT: v_cvt_f32_f16_e32 v9, v3512323; SI-NEXT: v_or_b32_e32 v6, v7, v612324; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v812325; SI-NEXT: v_cvt_f32_f16_e32 v8, v3412326; SI-NEXT: v_cvt_f32_f16_e32 v10, v3312327; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v912328; SI-NEXT: v_cvt_f16_f32_e32 v9, v912329; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v812330; SI-NEXT: v_cvt_f16_f32_e32 v8, v812331; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v1012332; SI-NEXT: v_cvt_f16_f32_e32 v10, v1012333; SI-NEXT: v_or_b32_e32 v7, v9, v712334; SI-NEXT: v_cvt_f32_f16_e32 v9, v3212335; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v812336; SI-NEXT: v_or_b32_e32 v8, v10, v812337; SI-NEXT: v_cvt_f32_f16_e32 v10, v3112338; SI-NEXT: v_cvt_f32_f16_e32 v11, v3012339; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v912340; SI-NEXT: v_cvt_f16_f32_e32 v9, v912341; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v1012342; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v1112343; SI-NEXT: v_cvt_f16_f32_e32 v10, v1012344; SI-NEXT: v_cvt_f16_f32_e32 v11, v1112345; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v912346; SI-NEXT: v_cvt_f32_f16_e32 v12, v2912347; SI-NEXT: v_or_b32_e32 v9, v10, v912348; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v1112349; SI-NEXT: v_cvt_f32_f16_e32 v11, v2112350; SI-NEXT: v_cvt_f32_f16_e32 v13, v2012351; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v1212352; SI-NEXT: v_cvt_f16_f32_e32 v12, v1212353; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v1112354; SI-NEXT: v_cvt_f16_f32_e32 v11, v1112355; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v1312356; SI-NEXT: v_cvt_f16_f32_e32 v13, v1312357; SI-NEXT: v_or_b32_e32 v10, v12, v1012358; SI-NEXT: v_cvt_f32_f16_e32 v12, v1912359; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v1112360; SI-NEXT: v_or_b32_e32 v11, v13, v1112361; SI-NEXT: v_cvt_f32_f16_e32 v13, v1812362; SI-NEXT: v_cvt_f32_f16_e32 v14, v1712363; SI-NEXT: v_cvt_f32_f16_e32 v15, v1612364; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v1212365; SI-NEXT: v_cvt_f16_f32_e32 v12, v1212366; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v1312367; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v1412368; SI-NEXT: v_cvt_f16_f32_e32 v13, v1312369; SI-NEXT: v_cvt_f16_f32_e32 v14, v1412370; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v1512371; SI-NEXT: v_cvt_f16_f32_e32 v15, v1512372; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v1212373; SI-NEXT: v_or_b32_e32 v12, v13, v1212374; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v1412375; SI-NEXT: v_or_b32_e32 v13, v15, v1312376; SI-NEXT: .LBB54_4: ; %end12377; SI-NEXT: s_or_b64 exec, exec, s[4:5]12378; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 ; 4-byte Folded Reload12379; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload12380; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload12381; SI-NEXT: s_waitcnt vmcnt(0)12382; SI-NEXT: s_setpc_b64 s[30:31]12383;12384; VI-LABEL: bitcast_v28f16_to_v7f64:12385; VI: ; %bb.0:12386; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12387; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1412388; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc12389; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]12390; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]12391; VI-NEXT: s_cbranch_execz .LBB54_212392; VI-NEXT: ; %bb.1: ; %cmp.true12393; VI-NEXT: v_mov_b32_e32 v14, 0x20012394; VI-NEXT: v_add_f16_sdwa v15, v13, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD12395; VI-NEXT: v_add_f16_e32 v13, 0x200, v1312396; VI-NEXT: v_or_b32_e32 v13, v13, v1512397; VI-NEXT: v_add_f16_sdwa v15, v12, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD12398; VI-NEXT: v_add_f16_e32 v12, 0x200, v1212399; VI-NEXT: v_or_b32_e32 v12, v12, v1512400; VI-NEXT: v_add_f16_sdwa v15, v11, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD12401; VI-NEXT: v_add_f16_e32 v11, 0x200, v1112402; VI-NEXT: v_or_b32_e32 v11, v11, v1512403; VI-NEXT: v_add_f16_sdwa v15, v10, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD12404; VI-NEXT: v_add_f16_e32 v10, 0x200, v1012405; VI-NEXT: v_or_b32_e32 v10, v10, v1512406; VI-NEXT: v_add_f16_sdwa v15, v9, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD12407; VI-NEXT: v_add_f16_e32 v9, 0x200, v912408; VI-NEXT: v_or_b32_e32 v9, v9, v1512409; VI-NEXT: v_add_f16_sdwa v15, v8, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD12410; VI-NEXT: v_add_f16_e32 v8, 0x200, v812411; VI-NEXT: v_or_b32_e32 v8, v8, v1512412; VI-NEXT: v_add_f16_sdwa v15, v7, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD12413; VI-NEXT: v_add_f16_e32 v7, 0x200, v712414; VI-NEXT: v_or_b32_e32 v7, v7, v1512415; VI-NEXT: v_add_f16_sdwa v15, v6, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD12416; VI-NEXT: v_add_f16_e32 v6, 0x200, v612417; VI-NEXT: v_or_b32_e32 v6, v6, v1512418; VI-NEXT: v_add_f16_sdwa v15, v5, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD12419; VI-NEXT: v_add_f16_e32 v5, 0x200, v512420; VI-NEXT: v_or_b32_e32 v5, v5, v1512421; VI-NEXT: v_add_f16_sdwa v15, v4, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD12422; VI-NEXT: v_add_f16_e32 v4, 0x200, v412423; VI-NEXT: v_or_b32_e32 v4, v4, v1512424; VI-NEXT: v_add_f16_sdwa v15, v3, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD12425; VI-NEXT: v_add_f16_e32 v3, 0x200, v312426; VI-NEXT: v_or_b32_e32 v3, v3, v1512427; VI-NEXT: v_add_f16_sdwa v15, v2, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD12428; VI-NEXT: v_add_f16_e32 v2, 0x200, v212429; VI-NEXT: v_or_b32_e32 v2, v2, v1512430; VI-NEXT: v_add_f16_sdwa v15, v1, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD12431; VI-NEXT: v_add_f16_e32 v1, 0x200, v112432; VI-NEXT: v_add_f16_sdwa v14, v0, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD12433; VI-NEXT: v_add_f16_e32 v0, 0x200, v012434; VI-NEXT: v_or_b32_e32 v1, v1, v1512435; VI-NEXT: v_or_b32_e32 v0, v0, v1412436; VI-NEXT: .LBB54_2: ; %end12437; VI-NEXT: s_or_b64 exec, exec, s[4:5]12438; VI-NEXT: s_setpc_b64 s[30:31]12439;12440; GFX9-LABEL: bitcast_v28f16_to_v7f64:12441; GFX9: ; %bb.0:12442; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12443; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1412444; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc12445; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]12446; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]12447; GFX9-NEXT: s_cbranch_execz .LBB54_212448; GFX9-NEXT: ; %bb.1: ; %cmp.true12449; GFX9-NEXT: s_movk_i32 s6, 0x20012450; GFX9-NEXT: v_pk_add_f16 v13, v13, s6 op_sel_hi:[1,0]12451; GFX9-NEXT: v_pk_add_f16 v12, v12, s6 op_sel_hi:[1,0]12452; GFX9-NEXT: v_pk_add_f16 v11, v11, s6 op_sel_hi:[1,0]12453; GFX9-NEXT: v_pk_add_f16 v10, v10, s6 op_sel_hi:[1,0]12454; GFX9-NEXT: v_pk_add_f16 v9, v9, s6 op_sel_hi:[1,0]12455; GFX9-NEXT: v_pk_add_f16 v8, v8, s6 op_sel_hi:[1,0]12456; GFX9-NEXT: v_pk_add_f16 v7, v7, s6 op_sel_hi:[1,0]12457; GFX9-NEXT: v_pk_add_f16 v6, v6, s6 op_sel_hi:[1,0]12458; GFX9-NEXT: v_pk_add_f16 v5, v5, s6 op_sel_hi:[1,0]12459; GFX9-NEXT: v_pk_add_f16 v4, v4, s6 op_sel_hi:[1,0]12460; GFX9-NEXT: v_pk_add_f16 v3, v3, s6 op_sel_hi:[1,0]12461; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]12462; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]12463; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]12464; GFX9-NEXT: .LBB54_2: ; %end12465; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]12466; GFX9-NEXT: s_setpc_b64 s[30:31]12467;12468; GFX11-LABEL: bitcast_v28f16_to_v7f64:12469; GFX11: ; %bb.0:12470; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12471; GFX11-NEXT: s_mov_b32 s0, exec_lo12472; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v1412473; GFX11-NEXT: s_xor_b32 s0, exec_lo, s012474; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)12475; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s012476; GFX11-NEXT: s_cbranch_execz .LBB54_212477; GFX11-NEXT: ; %bb.1: ; %cmp.true12478; GFX11-NEXT: v_pk_add_f16 v13, 0x200, v13 op_sel_hi:[0,1]12479; GFX11-NEXT: v_pk_add_f16 v12, 0x200, v12 op_sel_hi:[0,1]12480; GFX11-NEXT: v_pk_add_f16 v11, 0x200, v11 op_sel_hi:[0,1]12481; GFX11-NEXT: v_pk_add_f16 v10, 0x200, v10 op_sel_hi:[0,1]12482; GFX11-NEXT: v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1]12483; GFX11-NEXT: v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1]12484; GFX11-NEXT: v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]12485; GFX11-NEXT: v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]12486; GFX11-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]12487; GFX11-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]12488; GFX11-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]12489; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]12490; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]12491; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]12492; GFX11-NEXT: .LBB54_2: ; %end12493; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s012494; GFX11-NEXT: s_setpc_b64 s[30:31]12495 %cmp = icmp eq i32 %b, 012496 br i1 %cmp, label %cmp.true, label %cmp.false12497 12498cmp.true:12499 %a1 = fadd <28 x half> %a, splat (half 0xH0200)12500 %a2 = bitcast <28 x half> %a1 to <7 x double>12501 br label %end12502 12503cmp.false:12504 %a3 = bitcast <28 x half> %a to <7 x double>12505 br label %end12506 12507end:12508 %phi = phi <7 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]12509 ret <7 x double> %phi12510}12511 12512define inreg <7 x double> @bitcast_v28f16_to_v7f64_scalar(<28 x half> inreg %a, i32 inreg %b) {12513; SI-LABEL: bitcast_v28f16_to_v7f64_scalar:12514; SI: ; %bb.0:12515; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12516; SI-NEXT: v_cvt_f16_f32_e32 v51, s1712517; SI-NEXT: v_cvt_f16_f32_e32 v50, s1612518; SI-NEXT: v_cvt_f16_f32_e32 v49, s1912519; SI-NEXT: v_cvt_f16_f32_e32 v38, s1812520; SI-NEXT: v_cvt_f16_f32_e32 v36, s2112521; SI-NEXT: v_cvt_f16_f32_e32 v35, s2012522; SI-NEXT: v_cvt_f16_f32_e32 v29, v112523; SI-NEXT: v_cvt_f16_f32_e32 v28, v012524; SI-NEXT: v_cvt_f16_f32_e32 v27, v312525; SI-NEXT: v_cvt_f16_f32_e32 v26, v212526; SI-NEXT: v_cvt_f16_f32_e32 v25, v512527; SI-NEXT: v_cvt_f16_f32_e32 v24, v412528; SI-NEXT: v_cvt_f16_f32_e32 v23, v712529; SI-NEXT: v_cvt_f16_f32_e32 v22, v612530; SI-NEXT: v_cvt_f16_f32_e32 v21, v912531; SI-NEXT: v_cvt_f16_f32_e32 v20, v812532; SI-NEXT: v_cvt_f16_f32_e32 v19, v1112533; SI-NEXT: v_cvt_f16_f32_e32 v18, v1012534; SI-NEXT: v_cvt_f16_f32_e32 v17, v1312535; SI-NEXT: v_cvt_f16_f32_e32 v16, v1212536; SI-NEXT: v_cvt_f16_f32_e32 v48, s2312537; SI-NEXT: v_cvt_f16_f32_e32 v39, s2212538; SI-NEXT: v_cvt_f16_f32_e32 v37, s2512539; SI-NEXT: v_cvt_f16_f32_e32 v34, s2412540; SI-NEXT: v_cvt_f16_f32_e32 v33, s2712541; SI-NEXT: v_cvt_f16_f32_e32 v32, s2612542; SI-NEXT: v_cvt_f16_f32_e32 v31, s2912543; SI-NEXT: v_cvt_f16_f32_e32 v30, s2812544; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1412545; SI-NEXT: s_and_b64 s[4:5], vcc, exec12546; SI-NEXT: s_cbranch_scc0 .LBB55_412547; SI-NEXT: ; %bb.1: ; %cmp.false12548; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v5112549; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v4912550; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v3612551; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v4812552; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v3712553; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v3312554; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v3112555; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v2912556; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v2712557; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v2512558; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v2312559; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v2112560; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v1912561; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v1712562; SI-NEXT: v_or_b32_e32 v0, v50, v012563; SI-NEXT: v_or_b32_e32 v1, v38, v112564; SI-NEXT: v_or_b32_e32 v2, v35, v212565; SI-NEXT: v_or_b32_e32 v3, v39, v312566; SI-NEXT: v_or_b32_e32 v4, v34, v412567; SI-NEXT: v_or_b32_e32 v5, v32, v512568; SI-NEXT: v_or_b32_e32 v6, v30, v612569; SI-NEXT: v_or_b32_e32 v7, v28, v712570; SI-NEXT: v_or_b32_e32 v8, v26, v812571; SI-NEXT: v_or_b32_e32 v9, v24, v912572; SI-NEXT: v_or_b32_e32 v10, v22, v1012573; SI-NEXT: v_or_b32_e32 v11, v20, v1112574; SI-NEXT: v_or_b32_e32 v12, v18, v1212575; SI-NEXT: v_or_b32_e32 v13, v16, v1312576; SI-NEXT: s_cbranch_execnz .LBB55_312577; SI-NEXT: .LBB55_2: ; %cmp.true12578; SI-NEXT: v_cvt_f32_f16_e32 v0, v5112579; SI-NEXT: v_cvt_f32_f16_e32 v1, v5012580; SI-NEXT: v_cvt_f32_f16_e32 v2, v4912581; SI-NEXT: v_cvt_f32_f16_e32 v3, v3812582; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v012583; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v112584; SI-NEXT: v_cvt_f16_f32_e32 v0, v012585; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v212586; SI-NEXT: v_cvt_f16_f32_e32 v1, v112587; SI-NEXT: v_cvt_f16_f32_e32 v2, v212588; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v012589; SI-NEXT: v_cvt_f32_f16_e32 v4, v3512590; SI-NEXT: v_or_b32_e32 v0, v1, v012591; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v212592; SI-NEXT: v_cvt_f32_f16_e32 v2, v3612593; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v312594; SI-NEXT: v_cvt_f16_f32_e32 v3, v312595; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v412596; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v212597; SI-NEXT: v_cvt_f16_f32_e32 v2, v212598; SI-NEXT: v_cvt_f16_f32_e32 v4, v412599; SI-NEXT: v_or_b32_e32 v1, v3, v112600; SI-NEXT: v_cvt_f32_f16_e32 v3, v4812601; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v212602; SI-NEXT: v_or_b32_e32 v2, v4, v212603; SI-NEXT: v_cvt_f32_f16_e32 v4, v3912604; SI-NEXT: v_cvt_f32_f16_e32 v5, v3712605; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v312606; SI-NEXT: v_cvt_f16_f32_e32 v3, v312607; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v412608; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v512609; SI-NEXT: v_cvt_f16_f32_e32 v4, v412610; SI-NEXT: v_cvt_f16_f32_e32 v5, v512611; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v312612; SI-NEXT: v_cvt_f32_f16_e32 v6, v3412613; SI-NEXT: v_or_b32_e32 v3, v4, v312614; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v512615; SI-NEXT: v_cvt_f32_f16_e32 v5, v3312616; SI-NEXT: v_cvt_f32_f16_e32 v7, v3212617; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v612618; SI-NEXT: v_cvt_f16_f32_e32 v6, v612619; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v512620; SI-NEXT: v_cvt_f16_f32_e32 v5, v512621; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v712622; SI-NEXT: v_cvt_f16_f32_e32 v7, v712623; SI-NEXT: v_or_b32_e32 v4, v6, v412624; SI-NEXT: v_cvt_f32_f16_e32 v6, v3112625; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v512626; SI-NEXT: v_or_b32_e32 v5, v7, v512627; SI-NEXT: v_cvt_f32_f16_e32 v7, v3012628; SI-NEXT: v_cvt_f32_f16_e32 v8, v2912629; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v612630; SI-NEXT: v_cvt_f16_f32_e32 v6, v612631; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v712632; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v812633; SI-NEXT: v_cvt_f16_f32_e32 v7, v712634; SI-NEXT: v_cvt_f16_f32_e32 v8, v812635; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v612636; SI-NEXT: v_cvt_f32_f16_e32 v9, v2812637; SI-NEXT: v_or_b32_e32 v6, v7, v612638; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v812639; SI-NEXT: v_cvt_f32_f16_e32 v8, v2712640; SI-NEXT: v_cvt_f32_f16_e32 v10, v2612641; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v912642; SI-NEXT: v_cvt_f16_f32_e32 v9, v912643; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v812644; SI-NEXT: v_cvt_f16_f32_e32 v8, v812645; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v1012646; SI-NEXT: v_cvt_f16_f32_e32 v10, v1012647; SI-NEXT: v_or_b32_e32 v7, v9, v712648; SI-NEXT: v_cvt_f32_f16_e32 v9, v2512649; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v812650; SI-NEXT: v_or_b32_e32 v8, v10, v812651; SI-NEXT: v_cvt_f32_f16_e32 v10, v2412652; SI-NEXT: v_cvt_f32_f16_e32 v11, v2312653; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v912654; SI-NEXT: v_cvt_f16_f32_e32 v9, v912655; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v1012656; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v1112657; SI-NEXT: v_cvt_f16_f32_e32 v10, v1012658; SI-NEXT: v_cvt_f16_f32_e32 v11, v1112659; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v912660; SI-NEXT: v_cvt_f32_f16_e32 v12, v2212661; SI-NEXT: v_or_b32_e32 v9, v10, v912662; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v1112663; SI-NEXT: v_cvt_f32_f16_e32 v11, v2112664; SI-NEXT: v_cvt_f32_f16_e32 v13, v2012665; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v1212666; SI-NEXT: v_cvt_f16_f32_e32 v12, v1212667; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v1112668; SI-NEXT: v_cvt_f16_f32_e32 v11, v1112669; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v1312670; SI-NEXT: v_cvt_f16_f32_e32 v13, v1312671; SI-NEXT: v_or_b32_e32 v10, v12, v1012672; SI-NEXT: v_cvt_f32_f16_e32 v12, v1912673; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v1112674; SI-NEXT: v_or_b32_e32 v11, v13, v1112675; SI-NEXT: v_cvt_f32_f16_e32 v13, v1812676; SI-NEXT: v_cvt_f32_f16_e32 v14, v1712677; SI-NEXT: v_cvt_f32_f16_e32 v15, v1612678; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v1212679; SI-NEXT: v_cvt_f16_f32_e32 v12, v1212680; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v1312681; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v1412682; SI-NEXT: v_cvt_f16_f32_e32 v13, v1312683; SI-NEXT: v_cvt_f16_f32_e32 v14, v1412684; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v1512685; SI-NEXT: v_cvt_f16_f32_e32 v15, v1512686; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v1212687; SI-NEXT: v_or_b32_e32 v12, v13, v1212688; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v1412689; SI-NEXT: v_or_b32_e32 v13, v15, v1312690; SI-NEXT: .LBB55_3: ; %end12691; SI-NEXT: s_setpc_b64 s[30:31]12692; SI-NEXT: .LBB55_4:12693; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr1512694; SI-NEXT: s_branch .LBB55_212695;12696; VI-LABEL: bitcast_v28f16_to_v7f64_scalar:12697; VI: ; %bb.0:12698; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12699; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v012700; VI-NEXT: s_and_b64 s[4:5], vcc, exec12701; VI-NEXT: s_cbranch_scc0 .LBB55_312702; VI-NEXT: ; %bb.1: ; %cmp.false12703; VI-NEXT: s_cbranch_execnz .LBB55_412704; VI-NEXT: .LBB55_2: ; %cmp.true12705; VI-NEXT: s_lshr_b32 s4, s29, 1612706; VI-NEXT: v_mov_b32_e32 v0, 0x20012707; VI-NEXT: v_mov_b32_e32 v1, s412708; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD12709; VI-NEXT: v_add_f16_e32 v2, s29, v012710; VI-NEXT: s_lshr_b32 s4, s28, 1612711; VI-NEXT: v_or_b32_e32 v13, v2, v112712; VI-NEXT: v_mov_b32_e32 v1, s412713; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD12714; VI-NEXT: v_add_f16_e32 v2, s28, v012715; VI-NEXT: s_lshr_b32 s4, s27, 1612716; VI-NEXT: v_or_b32_e32 v12, v2, v112717; VI-NEXT: v_mov_b32_e32 v1, s412718; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD12719; VI-NEXT: v_add_f16_e32 v2, s27, v012720; VI-NEXT: s_lshr_b32 s4, s26, 1612721; VI-NEXT: v_or_b32_e32 v11, v2, v112722; VI-NEXT: v_mov_b32_e32 v1, s412723; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD12724; VI-NEXT: v_add_f16_e32 v2, s26, v012725; VI-NEXT: s_lshr_b32 s4, s25, 1612726; VI-NEXT: v_or_b32_e32 v10, v2, v112727; VI-NEXT: v_mov_b32_e32 v1, s412728; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD12729; VI-NEXT: v_add_f16_e32 v2, s25, v012730; VI-NEXT: s_lshr_b32 s4, s24, 1612731; VI-NEXT: v_or_b32_e32 v9, v2, v112732; VI-NEXT: v_mov_b32_e32 v1, s412733; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD12734; VI-NEXT: v_add_f16_e32 v2, s24, v012735; VI-NEXT: s_lshr_b32 s4, s23, 1612736; VI-NEXT: v_or_b32_e32 v8, v2, v112737; VI-NEXT: v_mov_b32_e32 v1, s412738; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD12739; VI-NEXT: v_add_f16_e32 v2, s23, v012740; VI-NEXT: s_lshr_b32 s4, s22, 1612741; VI-NEXT: v_or_b32_e32 v7, v2, v112742; VI-NEXT: v_mov_b32_e32 v1, s412743; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD12744; VI-NEXT: v_add_f16_e32 v2, s22, v012745; VI-NEXT: s_lshr_b32 s4, s21, 1612746; VI-NEXT: v_or_b32_e32 v6, v2, v112747; VI-NEXT: v_mov_b32_e32 v1, s412748; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD12749; VI-NEXT: v_add_f16_e32 v2, s21, v012750; VI-NEXT: s_lshr_b32 s4, s20, 1612751; VI-NEXT: v_or_b32_e32 v5, v2, v112752; VI-NEXT: v_mov_b32_e32 v1, s412753; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD12754; VI-NEXT: v_add_f16_e32 v2, s20, v012755; VI-NEXT: s_lshr_b32 s4, s19, 1612756; VI-NEXT: v_or_b32_e32 v4, v2, v112757; VI-NEXT: v_mov_b32_e32 v1, s412758; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD12759; VI-NEXT: v_add_f16_e32 v2, s19, v012760; VI-NEXT: s_lshr_b32 s4, s18, 1612761; VI-NEXT: v_or_b32_e32 v3, v2, v112762; VI-NEXT: v_mov_b32_e32 v1, s412763; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD12764; VI-NEXT: v_add_f16_e32 v2, s18, v012765; VI-NEXT: s_lshr_b32 s4, s17, 1612766; VI-NEXT: v_or_b32_e32 v2, v2, v112767; VI-NEXT: v_mov_b32_e32 v1, s412768; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD12769; VI-NEXT: v_add_f16_e32 v14, s17, v012770; VI-NEXT: s_lshr_b32 s4, s16, 1612771; VI-NEXT: v_or_b32_e32 v1, v14, v112772; VI-NEXT: v_mov_b32_e32 v14, s412773; VI-NEXT: v_add_f16_sdwa v14, v14, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD12774; VI-NEXT: v_add_f16_e32 v0, s16, v012775; VI-NEXT: v_or_b32_e32 v0, v0, v1412776; VI-NEXT: s_setpc_b64 s[30:31]12777; VI-NEXT: .LBB55_3:12778; VI-NEXT: s_branch .LBB55_212779; VI-NEXT: .LBB55_4:12780; VI-NEXT: v_mov_b32_e32 v0, s1612781; VI-NEXT: v_mov_b32_e32 v1, s1712782; VI-NEXT: v_mov_b32_e32 v2, s1812783; VI-NEXT: v_mov_b32_e32 v3, s1912784; VI-NEXT: v_mov_b32_e32 v4, s2012785; VI-NEXT: v_mov_b32_e32 v5, s2112786; VI-NEXT: v_mov_b32_e32 v6, s2212787; VI-NEXT: v_mov_b32_e32 v7, s2312788; VI-NEXT: v_mov_b32_e32 v8, s2412789; VI-NEXT: v_mov_b32_e32 v9, s2512790; VI-NEXT: v_mov_b32_e32 v10, s2612791; VI-NEXT: v_mov_b32_e32 v11, s2712792; VI-NEXT: v_mov_b32_e32 v12, s2812793; VI-NEXT: v_mov_b32_e32 v13, s2912794; VI-NEXT: v_mov_b32_e32 v14, s3012795; VI-NEXT: v_mov_b32_e32 v15, s3112796; VI-NEXT: s_setpc_b64 s[30:31]12797;12798; GFX9-LABEL: bitcast_v28f16_to_v7f64_scalar:12799; GFX9: ; %bb.0:12800; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12801; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v012802; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec12803; GFX9-NEXT: s_cbranch_scc0 .LBB55_312804; GFX9-NEXT: ; %bb.1: ; %cmp.false12805; GFX9-NEXT: s_cbranch_execnz .LBB55_412806; GFX9-NEXT: .LBB55_2: ; %cmp.true12807; GFX9-NEXT: v_mov_b32_e32 v0, 0x20012808; GFX9-NEXT: v_pk_add_f16 v13, s29, v0 op_sel_hi:[1,0]12809; GFX9-NEXT: v_pk_add_f16 v12, s28, v0 op_sel_hi:[1,0]12810; GFX9-NEXT: v_pk_add_f16 v11, s27, v0 op_sel_hi:[1,0]12811; GFX9-NEXT: v_pk_add_f16 v10, s26, v0 op_sel_hi:[1,0]12812; GFX9-NEXT: v_pk_add_f16 v9, s25, v0 op_sel_hi:[1,0]12813; GFX9-NEXT: v_pk_add_f16 v8, s24, v0 op_sel_hi:[1,0]12814; GFX9-NEXT: v_pk_add_f16 v7, s23, v0 op_sel_hi:[1,0]12815; GFX9-NEXT: v_pk_add_f16 v6, s22, v0 op_sel_hi:[1,0]12816; GFX9-NEXT: v_pk_add_f16 v5, s21, v0 op_sel_hi:[1,0]12817; GFX9-NEXT: v_pk_add_f16 v4, s20, v0 op_sel_hi:[1,0]12818; GFX9-NEXT: v_pk_add_f16 v3, s19, v0 op_sel_hi:[1,0]12819; GFX9-NEXT: v_pk_add_f16 v2, s18, v0 op_sel_hi:[1,0]12820; GFX9-NEXT: v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]12821; GFX9-NEXT: v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]12822; GFX9-NEXT: s_setpc_b64 s[30:31]12823; GFX9-NEXT: .LBB55_3:12824; GFX9-NEXT: s_branch .LBB55_212825; GFX9-NEXT: .LBB55_4:12826; GFX9-NEXT: v_mov_b32_e32 v0, s1612827; GFX9-NEXT: v_mov_b32_e32 v1, s1712828; GFX9-NEXT: v_mov_b32_e32 v2, s1812829; GFX9-NEXT: v_mov_b32_e32 v3, s1912830; GFX9-NEXT: v_mov_b32_e32 v4, s2012831; GFX9-NEXT: v_mov_b32_e32 v5, s2112832; GFX9-NEXT: v_mov_b32_e32 v6, s2212833; GFX9-NEXT: v_mov_b32_e32 v7, s2312834; GFX9-NEXT: v_mov_b32_e32 v8, s2412835; GFX9-NEXT: v_mov_b32_e32 v9, s2512836; GFX9-NEXT: v_mov_b32_e32 v10, s2612837; GFX9-NEXT: v_mov_b32_e32 v11, s2712838; GFX9-NEXT: v_mov_b32_e32 v12, s2812839; GFX9-NEXT: v_mov_b32_e32 v13, s2912840; GFX9-NEXT: v_mov_b32_e32 v14, s3012841; GFX9-NEXT: v_mov_b32_e32 v15, s3112842; GFX9-NEXT: s_setpc_b64 s[30:31]12843;12844; GFX11-LABEL: bitcast_v28f16_to_v7f64_scalar:12845; GFX11: ; %bb.0:12846; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12847; GFX11-NEXT: s_mov_b32 s15, s312848; GFX11-NEXT: s_mov_b32 s14, s212849; GFX11-NEXT: s_mov_b32 s13, s112850; GFX11-NEXT: s_mov_b32 s12, s012851; GFX11-NEXT: s_cmp_lg_u32 s26, 012852; GFX11-NEXT: s_mov_b32 s0, 012853; GFX11-NEXT: s_cbranch_scc0 .LBB55_312854; GFX11-NEXT: ; %bb.1: ; %Flow12855; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s012856; GFX11-NEXT: s_cbranch_vccnz .LBB55_412857; GFX11-NEXT: .LBB55_2: ; %cmp.true12858; GFX11-NEXT: v_pk_add_f16 v13, 0x200, s25 op_sel_hi:[0,1]12859; GFX11-NEXT: v_pk_add_f16 v12, 0x200, s24 op_sel_hi:[0,1]12860; GFX11-NEXT: v_pk_add_f16 v11, 0x200, s23 op_sel_hi:[0,1]12861; GFX11-NEXT: v_pk_add_f16 v10, 0x200, s22 op_sel_hi:[0,1]12862; GFX11-NEXT: v_pk_add_f16 v9, 0x200, s21 op_sel_hi:[0,1]12863; GFX11-NEXT: v_pk_add_f16 v8, 0x200, s20 op_sel_hi:[0,1]12864; GFX11-NEXT: v_pk_add_f16 v7, 0x200, s19 op_sel_hi:[0,1]12865; GFX11-NEXT: v_pk_add_f16 v6, 0x200, s18 op_sel_hi:[0,1]12866; GFX11-NEXT: v_pk_add_f16 v5, 0x200, s17 op_sel_hi:[0,1]12867; GFX11-NEXT: v_pk_add_f16 v4, 0x200, s16 op_sel_hi:[0,1]12868; GFX11-NEXT: v_pk_add_f16 v3, 0x200, s15 op_sel_hi:[0,1]12869; GFX11-NEXT: v_pk_add_f16 v2, 0x200, s14 op_sel_hi:[0,1]12870; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s13 op_sel_hi:[0,1]12871; GFX11-NEXT: v_pk_add_f16 v0, 0x200, s12 op_sel_hi:[0,1]12872; GFX11-NEXT: s_setpc_b64 s[30:31]12873; GFX11-NEXT: .LBB55_3:12874; GFX11-NEXT: s_branch .LBB55_212875; GFX11-NEXT: .LBB55_4:12876; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s1312877; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s1512878; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s1712879; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s1912880; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s2112881; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s2312882; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s2512883; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s2712884; GFX11-NEXT: s_setpc_b64 s[30:31]12885 %cmp = icmp eq i32 %b, 012886 br i1 %cmp, label %cmp.true, label %cmp.false12887 12888cmp.true:12889 %a1 = fadd <28 x half> %a, splat (half 0xH0200)12890 %a2 = bitcast <28 x half> %a1 to <7 x double>12891 br label %end12892 12893cmp.false:12894 %a3 = bitcast <28 x half> %a to <7 x double>12895 br label %end12896 12897end:12898 %phi = phi <7 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]12899 ret <7 x double> %phi12900}12901 12902define <28 x half> @bitcast_v28i16_to_v28f16(<28 x i16> %a, i32 %b) {12903; SI-LABEL: bitcast_v28i16_to_v28f16:12904; SI: ; %bb.0:12905; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12906; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill12907; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill12908; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill12909; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill12910; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill12911; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill12912; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill12913; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill12914; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 ; 4-byte Folded Spill12915; SI-NEXT: s_waitcnt expcnt(1)12916; SI-NEXT: v_mov_b32_e32 v47, v2712917; SI-NEXT: v_mov_b32_e32 v46, v2612918; SI-NEXT: v_mov_b32_e32 v45, v2512919; SI-NEXT: v_mov_b32_e32 v44, v2412920; SI-NEXT: v_mov_b32_e32 v43, v2312921; SI-NEXT: v_mov_b32_e32 v42, v2212922; SI-NEXT: v_mov_b32_e32 v41, v2112923; SI-NEXT: v_mov_b32_e32 v40, v2012924; SI-NEXT: v_mov_b32_e32 v55, v1912925; SI-NEXT: v_mov_b32_e32 v54, v1812926; SI-NEXT: v_mov_b32_e32 v53, v1712927; SI-NEXT: v_mov_b32_e32 v52, v1612928; SI-NEXT: v_mov_b32_e32 v51, v1512929; SI-NEXT: v_mov_b32_e32 v50, v1412930; SI-NEXT: v_mov_b32_e32 v49, v1312931; SI-NEXT: v_mov_b32_e32 v48, v1212932; SI-NEXT: v_mov_b32_e32 v39, v1112933; SI-NEXT: v_mov_b32_e32 v38, v1012934; SI-NEXT: v_mov_b32_e32 v37, v912935; SI-NEXT: v_mov_b32_e32 v36, v812936; SI-NEXT: v_mov_b32_e32 v35, v712937; SI-NEXT: v_mov_b32_e32 v34, v612938; SI-NEXT: v_mov_b32_e32 v33, v512939; SI-NEXT: v_mov_b32_e32 v32, v412940; SI-NEXT: v_mov_b32_e32 v31, v312941; SI-NEXT: v_mov_b32_e32 v30, v212942; SI-NEXT: v_mov_b32_e32 v29, v112943; SI-NEXT: s_waitcnt expcnt(0)12944; SI-NEXT: v_mov_b32_e32 v56, v012945; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2812946; SI-NEXT: ; implicit-def: $vgpr012947; SI-NEXT: ; implicit-def: $vgpr112948; SI-NEXT: ; implicit-def: $vgpr212949; SI-NEXT: ; implicit-def: $vgpr312950; SI-NEXT: ; implicit-def: $vgpr412951; SI-NEXT: ; implicit-def: $vgpr512952; SI-NEXT: ; implicit-def: $vgpr612953; SI-NEXT: ; implicit-def: $vgpr712954; SI-NEXT: ; implicit-def: $vgpr812955; SI-NEXT: ; implicit-def: $vgpr912956; SI-NEXT: ; implicit-def: $vgpr1012957; SI-NEXT: ; implicit-def: $vgpr1112958; SI-NEXT: ; implicit-def: $vgpr1212959; SI-NEXT: ; implicit-def: $vgpr1312960; SI-NEXT: ; implicit-def: $vgpr1412961; SI-NEXT: ; implicit-def: $vgpr1512962; SI-NEXT: ; implicit-def: $vgpr1612963; SI-NEXT: ; implicit-def: $vgpr1712964; SI-NEXT: ; implicit-def: $vgpr1812965; SI-NEXT: ; implicit-def: $vgpr1912966; SI-NEXT: ; implicit-def: $vgpr2012967; SI-NEXT: ; implicit-def: $vgpr2112968; SI-NEXT: ; implicit-def: $vgpr2212969; SI-NEXT: ; implicit-def: $vgpr2312970; SI-NEXT: ; implicit-def: $vgpr2412971; SI-NEXT: ; implicit-def: $vgpr2512972; SI-NEXT: ; implicit-def: $vgpr2612973; SI-NEXT: ; implicit-def: $vgpr2712974; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc12975; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]12976; SI-NEXT: s_cbranch_execz .LBB56_212977; SI-NEXT: ; %bb.1: ; %cmp.false12978; SI-NEXT: v_cvt_f32_f16_e32 v0, v5612979; SI-NEXT: v_cvt_f32_f16_e32 v1, v2912980; SI-NEXT: v_cvt_f32_f16_e32 v2, v3012981; SI-NEXT: v_cvt_f32_f16_e32 v3, v3112982; SI-NEXT: v_cvt_f32_f16_e32 v4, v3212983; SI-NEXT: v_cvt_f32_f16_e32 v5, v3312984; SI-NEXT: v_cvt_f32_f16_e32 v6, v3412985; SI-NEXT: v_cvt_f32_f16_e32 v7, v3512986; SI-NEXT: v_cvt_f32_f16_e32 v8, v3612987; SI-NEXT: v_cvt_f32_f16_e32 v9, v3712988; SI-NEXT: v_cvt_f32_f16_e32 v10, v3812989; SI-NEXT: v_cvt_f32_f16_e32 v11, v3912990; SI-NEXT: v_cvt_f32_f16_e32 v12, v4812991; SI-NEXT: v_cvt_f32_f16_e32 v13, v4912992; SI-NEXT: v_cvt_f32_f16_e32 v14, v5012993; SI-NEXT: v_cvt_f32_f16_e32 v15, v5112994; SI-NEXT: v_cvt_f32_f16_e32 v16, v5212995; SI-NEXT: v_cvt_f32_f16_e32 v17, v5312996; SI-NEXT: v_cvt_f32_f16_e32 v18, v5412997; SI-NEXT: v_cvt_f32_f16_e32 v19, v5512998; SI-NEXT: v_cvt_f32_f16_e32 v20, v4012999; SI-NEXT: v_cvt_f32_f16_e32 v21, v4113000; SI-NEXT: v_cvt_f32_f16_e32 v22, v4213001; SI-NEXT: v_cvt_f32_f16_e32 v23, v4313002; SI-NEXT: v_cvt_f32_f16_e32 v24, v4413003; SI-NEXT: v_cvt_f32_f16_e32 v25, v4513004; SI-NEXT: v_cvt_f32_f16_e32 v26, v4613005; SI-NEXT: v_cvt_f32_f16_e32 v27, v4713006; SI-NEXT: ; implicit-def: $vgpr5613007; SI-NEXT: ; implicit-def: $vgpr2913008; SI-NEXT: ; implicit-def: $vgpr3013009; SI-NEXT: ; implicit-def: $vgpr3113010; SI-NEXT: ; implicit-def: $vgpr3213011; SI-NEXT: ; implicit-def: $vgpr3313012; SI-NEXT: ; implicit-def: $vgpr3413013; SI-NEXT: ; implicit-def: $vgpr3513014; SI-NEXT: ; implicit-def: $vgpr3613015; SI-NEXT: ; implicit-def: $vgpr3713016; SI-NEXT: ; implicit-def: $vgpr3813017; SI-NEXT: ; implicit-def: $vgpr3913018; SI-NEXT: ; implicit-def: $vgpr4813019; SI-NEXT: ; implicit-def: $vgpr4913020; SI-NEXT: ; implicit-def: $vgpr5013021; SI-NEXT: ; implicit-def: $vgpr5113022; SI-NEXT: ; implicit-def: $vgpr5213023; SI-NEXT: ; implicit-def: $vgpr5313024; SI-NEXT: ; implicit-def: $vgpr5413025; SI-NEXT: ; implicit-def: $vgpr5513026; SI-NEXT: ; implicit-def: $vgpr4013027; SI-NEXT: ; implicit-def: $vgpr4113028; SI-NEXT: ; implicit-def: $vgpr4213029; SI-NEXT: ; implicit-def: $vgpr4313030; SI-NEXT: ; implicit-def: $vgpr4413031; SI-NEXT: ; implicit-def: $vgpr4513032; SI-NEXT: ; implicit-def: $vgpr4613033; SI-NEXT: ; implicit-def: $vgpr4713034; SI-NEXT: .LBB56_2: ; %Flow13035; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]13036; SI-NEXT: s_cbranch_execz .LBB56_413037; SI-NEXT: ; %bb.3: ; %cmp.true13038; SI-NEXT: v_add_i32_e32 v27, vcc, 3, v4713039; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v4613040; SI-NEXT: v_add_i32_e32 v25, vcc, 3, v4513041; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v4413042; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v4313043; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v4213044; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v4113045; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v4013046; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v5513047; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v5413048; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v5313049; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v5213050; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v5113051; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v5013052; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v4913053; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v4813054; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v3913055; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v3813056; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v3713057; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v3613058; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v3513059; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v3413060; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v3313061; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v3213062; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3113063; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v3013064; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v2913065; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v5613066; SI-NEXT: v_cvt_f32_f16_e32 v0, v013067; SI-NEXT: v_cvt_f32_f16_e32 v1, v113068; SI-NEXT: v_cvt_f32_f16_e32 v2, v213069; SI-NEXT: v_cvt_f32_f16_e32 v3, v313070; SI-NEXT: v_cvt_f32_f16_e32 v4, v413071; SI-NEXT: v_cvt_f32_f16_e32 v5, v513072; SI-NEXT: v_cvt_f32_f16_e32 v6, v613073; SI-NEXT: v_cvt_f32_f16_e32 v7, v713074; SI-NEXT: v_cvt_f32_f16_e32 v8, v813075; SI-NEXT: v_cvt_f32_f16_e32 v9, v913076; SI-NEXT: v_cvt_f32_f16_e32 v10, v1013077; SI-NEXT: v_cvt_f32_f16_e32 v11, v1113078; SI-NEXT: v_cvt_f32_f16_e32 v12, v1213079; SI-NEXT: v_cvt_f32_f16_e32 v13, v1313080; SI-NEXT: v_cvt_f32_f16_e32 v14, v1413081; SI-NEXT: v_cvt_f32_f16_e32 v15, v1513082; SI-NEXT: v_cvt_f32_f16_e32 v16, v1613083; SI-NEXT: v_cvt_f32_f16_e32 v17, v1713084; SI-NEXT: v_cvt_f32_f16_e32 v18, v1813085; SI-NEXT: v_cvt_f32_f16_e32 v19, v1913086; SI-NEXT: v_cvt_f32_f16_e32 v20, v2013087; SI-NEXT: v_cvt_f32_f16_e32 v21, v2113088; SI-NEXT: v_cvt_f32_f16_e32 v22, v2213089; SI-NEXT: v_cvt_f32_f16_e32 v23, v2313090; SI-NEXT: v_cvt_f32_f16_e32 v24, v2413091; SI-NEXT: v_cvt_f32_f16_e32 v25, v2513092; SI-NEXT: v_cvt_f32_f16_e32 v26, v2613093; SI-NEXT: v_cvt_f32_f16_e32 v27, v2713094; SI-NEXT: .LBB56_4: ; %end13095; SI-NEXT: s_or_b64 exec, exec, s[4:5]13096; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 ; 4-byte Folded Reload13097; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload13098; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload13099; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload13100; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload13101; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload13102; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload13103; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload13104; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload13105; SI-NEXT: s_waitcnt vmcnt(0)13106; SI-NEXT: s_setpc_b64 s[30:31]13107;13108; VI-LABEL: bitcast_v28i16_to_v28f16:13109; VI: ; %bb.0:13110; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)13111; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1413112; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc13113; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]13114; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]13115; VI-NEXT: s_cbranch_execz .LBB56_213116; VI-NEXT: ; %bb.1: ; %cmp.true13117; VI-NEXT: v_mov_b32_e32 v14, 313118; VI-NEXT: v_add_u16_sdwa v19, v13, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD13119; VI-NEXT: v_add_u16_e32 v13, 3, v1313120; VI-NEXT: v_or_b32_e32 v13, v13, v1913121; VI-NEXT: v_add_u16_sdwa v19, v12, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD13122; VI-NEXT: v_add_u16_e32 v12, 3, v1213123; VI-NEXT: v_or_b32_e32 v12, v12, v1913124; VI-NEXT: v_add_u16_sdwa v19, v11, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD13125; VI-NEXT: v_add_u16_e32 v11, 3, v1113126; VI-NEXT: v_or_b32_e32 v11, v11, v1913127; VI-NEXT: v_add_u16_sdwa v19, v10, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD13128; VI-NEXT: v_add_u16_e32 v10, 3, v1013129; VI-NEXT: v_or_b32_e32 v10, v10, v1913130; VI-NEXT: v_add_u16_sdwa v19, v9, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD13131; VI-NEXT: v_add_u16_e32 v9, 3, v913132; VI-NEXT: v_or_b32_e32 v9, v9, v1913133; VI-NEXT: v_add_u16_sdwa v19, v8, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD13134; VI-NEXT: v_add_u16_e32 v8, 3, v813135; VI-NEXT: v_or_b32_e32 v8, v8, v1913136; VI-NEXT: v_add_u16_sdwa v19, v7, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD13137; VI-NEXT: v_add_u16_e32 v7, 3, v713138; VI-NEXT: v_or_b32_e32 v7, v7, v1913139; VI-NEXT: v_add_u16_sdwa v19, v6, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD13140; VI-NEXT: v_add_u16_e32 v6, 3, v613141; VI-NEXT: v_add_u16_sdwa v15, v0, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD13142; VI-NEXT: v_add_u16_sdwa v16, v1, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD13143; VI-NEXT: v_add_u16_sdwa v17, v2, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD13144; VI-NEXT: v_add_u16_sdwa v18, v3, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD13145; VI-NEXT: v_or_b32_e32 v6, v6, v1913146; VI-NEXT: v_add_u16_sdwa v19, v4, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD13147; VI-NEXT: v_add_u16_sdwa v14, v5, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD13148; VI-NEXT: v_add_u16_e32 v5, 3, v513149; VI-NEXT: v_add_u16_e32 v4, 3, v413150; VI-NEXT: v_add_u16_e32 v3, 3, v313151; VI-NEXT: v_add_u16_e32 v2, 3, v213152; VI-NEXT: v_add_u16_e32 v1, 3, v113153; VI-NEXT: v_add_u16_e32 v0, 3, v013154; VI-NEXT: v_or_b32_e32 v5, v5, v1413155; VI-NEXT: v_or_b32_e32 v4, v4, v1913156; VI-NEXT: v_or_b32_e32 v3, v3, v1813157; VI-NEXT: v_or_b32_e32 v2, v2, v1713158; VI-NEXT: v_or_b32_e32 v1, v1, v1613159; VI-NEXT: v_or_b32_e32 v0, v0, v1513160; VI-NEXT: .LBB56_2: ; %end13161; VI-NEXT: s_or_b64 exec, exec, s[4:5]13162; VI-NEXT: s_setpc_b64 s[30:31]13163;13164; GFX9-LABEL: bitcast_v28i16_to_v28f16:13165; GFX9: ; %bb.0:13166; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)13167; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1413168; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc13169; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]13170; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]13171; GFX9-NEXT: s_cbranch_execz .LBB56_213172; GFX9-NEXT: ; %bb.1: ; %cmp.true13173; GFX9-NEXT: v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0]13174; GFX9-NEXT: v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0]13175; GFX9-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]13176; GFX9-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]13177; GFX9-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]13178; GFX9-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]13179; GFX9-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]13180; GFX9-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]13181; GFX9-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]13182; GFX9-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]13183; GFX9-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]13184; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]13185; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]13186; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]13187; GFX9-NEXT: .LBB56_2: ; %end13188; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]13189; GFX9-NEXT: s_setpc_b64 s[30:31]13190;13191; GFX11-LABEL: bitcast_v28i16_to_v28f16:13192; GFX11: ; %bb.0:13193; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)13194; GFX11-NEXT: s_mov_b32 s0, exec_lo13195; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v1413196; GFX11-NEXT: s_xor_b32 s0, exec_lo, s013197; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)13198; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s013199; GFX11-NEXT: s_cbranch_execz .LBB56_213200; GFX11-NEXT: ; %bb.1: ; %cmp.true13201; GFX11-NEXT: v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0]13202; GFX11-NEXT: v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0]13203; GFX11-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]13204; GFX11-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]13205; GFX11-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]13206; GFX11-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]13207; GFX11-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]13208; GFX11-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]13209; GFX11-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]13210; GFX11-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]13211; GFX11-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]13212; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]13213; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]13214; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]13215; GFX11-NEXT: .LBB56_2: ; %end13216; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s013217; GFX11-NEXT: s_setpc_b64 s[30:31]13218 %cmp = icmp eq i32 %b, 013219 br i1 %cmp, label %cmp.true, label %cmp.false13220 13221cmp.true:13222 %a1 = add <28 x i16> %a, splat (i16 3)13223 %a2 = bitcast <28 x i16> %a1 to <28 x half>13224 br label %end13225 13226cmp.false:13227 %a3 = bitcast <28 x i16> %a to <28 x half>13228 br label %end13229 13230end:13231 %phi = phi <28 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]13232 ret <28 x half> %phi13233}13234 13235define inreg <28 x half> @bitcast_v28i16_to_v28f16_scalar(<28 x i16> inreg %a, i32 inreg %b) {13236; SI-LABEL: bitcast_v28i16_to_v28f16_scalar:13237; SI: ; %bb.0:13238; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)13239; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1413240; SI-NEXT: v_mov_b32_e32 v38, v1313241; SI-NEXT: v_mov_b32_e32 v37, v1213242; SI-NEXT: v_mov_b32_e32 v36, v1113243; SI-NEXT: v_mov_b32_e32 v35, v1013244; SI-NEXT: v_mov_b32_e32 v34, v913245; SI-NEXT: v_mov_b32_e32 v33, v813246; SI-NEXT: v_mov_b32_e32 v32, v713247; SI-NEXT: v_mov_b32_e32 v31, v613248; SI-NEXT: v_mov_b32_e32 v30, v513249; SI-NEXT: v_mov_b32_e32 v29, v413250; SI-NEXT: v_mov_b32_e32 v28, v313251; SI-NEXT: v_mov_b32_e32 v49, v213252; SI-NEXT: v_mov_b32_e32 v48, v113253; SI-NEXT: v_mov_b32_e32 v39, v013254; SI-NEXT: s_and_b64 s[4:5], vcc, exec13255; SI-NEXT: s_cbranch_scc0 .LBB57_413256; SI-NEXT: ; %bb.1: ; %cmp.false13257; SI-NEXT: v_cvt_f32_f16_e32 v0, s1613258; SI-NEXT: v_cvt_f32_f16_e32 v1, s1713259; SI-NEXT: v_cvt_f32_f16_e32 v2, s1813260; SI-NEXT: v_cvt_f32_f16_e32 v3, s1913261; SI-NEXT: v_cvt_f32_f16_e32 v4, s2013262; SI-NEXT: v_cvt_f32_f16_e32 v5, s2113263; SI-NEXT: v_cvt_f32_f16_e32 v6, s2213264; SI-NEXT: v_cvt_f32_f16_e32 v7, s2313265; SI-NEXT: v_cvt_f32_f16_e32 v8, s2413266; SI-NEXT: v_cvt_f32_f16_e32 v9, s2513267; SI-NEXT: v_cvt_f32_f16_e32 v10, s2613268; SI-NEXT: v_cvt_f32_f16_e32 v11, s2713269; SI-NEXT: v_cvt_f32_f16_e32 v12, s2813270; SI-NEXT: v_cvt_f32_f16_e32 v13, s2913271; SI-NEXT: v_cvt_f32_f16_e32 v14, v3913272; SI-NEXT: v_cvt_f32_f16_e32 v15, v4813273; SI-NEXT: v_cvt_f32_f16_e32 v16, v4913274; SI-NEXT: v_cvt_f32_f16_e32 v17, v2813275; SI-NEXT: v_cvt_f32_f16_e32 v18, v2913276; SI-NEXT: v_cvt_f32_f16_e32 v19, v3013277; SI-NEXT: v_cvt_f32_f16_e32 v20, v3113278; SI-NEXT: v_cvt_f32_f16_e32 v21, v3213279; SI-NEXT: v_cvt_f32_f16_e32 v22, v3313280; SI-NEXT: v_cvt_f32_f16_e32 v23, v3413281; SI-NEXT: v_cvt_f32_f16_e32 v24, v3513282; SI-NEXT: v_cvt_f32_f16_e32 v25, v3613283; SI-NEXT: v_cvt_f32_f16_e32 v26, v3713284; SI-NEXT: v_cvt_f32_f16_e32 v27, v3813285; SI-NEXT: s_cbranch_execnz .LBB57_313286; SI-NEXT: .LBB57_2: ; %cmp.true13287; SI-NEXT: v_add_i32_e32 v27, vcc, 3, v3813288; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v3713289; SI-NEXT: v_add_i32_e32 v25, vcc, 3, v3613290; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v3513291; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v3413292; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v3313293; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v3213294; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v3113295; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v3013296; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v2913297; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v2813298; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v4913299; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v4813300; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v3913301; SI-NEXT: s_add_i32 s29, s29, 313302; SI-NEXT: s_add_i32 s28, s28, 313303; SI-NEXT: s_add_i32 s27, s27, 313304; SI-NEXT: s_add_i32 s26, s26, 313305; SI-NEXT: s_add_i32 s25, s25, 313306; SI-NEXT: s_add_i32 s24, s24, 313307; SI-NEXT: s_add_i32 s23, s23, 313308; SI-NEXT: s_add_i32 s22, s22, 313309; SI-NEXT: s_add_i32 s21, s21, 313310; SI-NEXT: s_add_i32 s20, s20, 313311; SI-NEXT: s_add_i32 s19, s19, 313312; SI-NEXT: s_add_i32 s18, s18, 313313; SI-NEXT: s_add_i32 s17, s17, 313314; SI-NEXT: s_add_i32 s16, s16, 313315; SI-NEXT: v_cvt_f32_f16_e32 v0, s1613316; SI-NEXT: v_cvt_f32_f16_e32 v1, s1713317; SI-NEXT: v_cvt_f32_f16_e32 v2, s1813318; SI-NEXT: v_cvt_f32_f16_e32 v3, s1913319; SI-NEXT: v_cvt_f32_f16_e32 v4, s2013320; SI-NEXT: v_cvt_f32_f16_e32 v5, s2113321; SI-NEXT: v_cvt_f32_f16_e32 v6, s2213322; SI-NEXT: v_cvt_f32_f16_e32 v7, s2313323; SI-NEXT: v_cvt_f32_f16_e32 v8, s2413324; SI-NEXT: v_cvt_f32_f16_e32 v9, s2513325; SI-NEXT: v_cvt_f32_f16_e32 v10, s2613326; SI-NEXT: v_cvt_f32_f16_e32 v11, s2713327; SI-NEXT: v_cvt_f32_f16_e32 v12, s2813328; SI-NEXT: v_cvt_f32_f16_e32 v13, s2913329; SI-NEXT: v_cvt_f32_f16_e32 v14, v1413330; SI-NEXT: v_cvt_f32_f16_e32 v15, v1513331; SI-NEXT: v_cvt_f32_f16_e32 v16, v1613332; SI-NEXT: v_cvt_f32_f16_e32 v17, v1713333; SI-NEXT: v_cvt_f32_f16_e32 v18, v1813334; SI-NEXT: v_cvt_f32_f16_e32 v19, v1913335; SI-NEXT: v_cvt_f32_f16_e32 v20, v2013336; SI-NEXT: v_cvt_f32_f16_e32 v21, v2113337; SI-NEXT: v_cvt_f32_f16_e32 v22, v2213338; SI-NEXT: v_cvt_f32_f16_e32 v23, v2313339; SI-NEXT: v_cvt_f32_f16_e32 v24, v2413340; SI-NEXT: v_cvt_f32_f16_e32 v25, v2513341; SI-NEXT: v_cvt_f32_f16_e32 v26, v2613342; SI-NEXT: v_cvt_f32_f16_e32 v27, v2713343; SI-NEXT: .LBB57_3: ; %end13344; SI-NEXT: s_setpc_b64 s[30:31]13345; SI-NEXT: .LBB57_4:13346; SI-NEXT: ; implicit-def: $vgpr013347; SI-NEXT: ; implicit-def: $vgpr113348; SI-NEXT: ; implicit-def: $vgpr213349; SI-NEXT: ; implicit-def: $vgpr313350; SI-NEXT: ; implicit-def: $vgpr413351; SI-NEXT: ; implicit-def: $vgpr513352; SI-NEXT: ; implicit-def: $vgpr613353; SI-NEXT: ; implicit-def: $vgpr713354; SI-NEXT: ; implicit-def: $vgpr813355; SI-NEXT: ; implicit-def: $vgpr913356; SI-NEXT: ; implicit-def: $vgpr1013357; SI-NEXT: ; implicit-def: $vgpr1113358; SI-NEXT: ; implicit-def: $vgpr1213359; SI-NEXT: ; implicit-def: $vgpr1313360; SI-NEXT: ; implicit-def: $vgpr1413361; SI-NEXT: ; implicit-def: $vgpr1513362; SI-NEXT: ; implicit-def: $vgpr1613363; SI-NEXT: ; implicit-def: $vgpr1713364; SI-NEXT: ; implicit-def: $vgpr1813365; SI-NEXT: ; implicit-def: $vgpr1913366; SI-NEXT: ; implicit-def: $vgpr2013367; SI-NEXT: ; implicit-def: $vgpr2113368; SI-NEXT: ; implicit-def: $vgpr2213369; SI-NEXT: ; implicit-def: $vgpr2313370; SI-NEXT: ; implicit-def: $vgpr2413371; SI-NEXT: ; implicit-def: $vgpr2513372; SI-NEXT: ; implicit-def: $vgpr2613373; SI-NEXT: ; implicit-def: $vgpr2713374; SI-NEXT: s_branch .LBB57_213375;13376; VI-LABEL: bitcast_v28i16_to_v28f16_scalar:13377; VI: ; %bb.0:13378; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)13379; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v013380; VI-NEXT: s_and_b64 s[4:5], vcc, exec13381; VI-NEXT: s_cbranch_scc0 .LBB57_413382; VI-NEXT: ; %bb.1: ; %cmp.false13383; VI-NEXT: s_cbranch_execnz .LBB57_313384; VI-NEXT: .LBB57_2: ; %cmp.true13385; VI-NEXT: s_and_b32 s4, s16, 0xffff000013386; VI-NEXT: s_add_i32 s5, s16, 313387; VI-NEXT: s_and_b32 s6, s17, 0xffff000013388; VI-NEXT: s_add_i32 s7, s17, 313389; VI-NEXT: s_and_b32 s8, s18, 0xffff000013390; VI-NEXT: s_add_i32 s9, s18, 313391; VI-NEXT: s_and_b32 s10, s19, 0xffff000013392; VI-NEXT: s_add_i32 s11, s19, 313393; VI-NEXT: s_and_b32 s12, s20, 0xffff000013394; VI-NEXT: s_add_i32 s13, s20, 313395; VI-NEXT: s_and_b32 s14, s21, 0xffff000013396; VI-NEXT: s_add_i32 s15, s21, 313397; VI-NEXT: s_and_b32 s16, s22, 0xffff000013398; VI-NEXT: s_add_i32 s17, s22, 313399; VI-NEXT: s_and_b32 s18, s23, 0xffff000013400; VI-NEXT: s_add_i32 s19, s23, 313401; VI-NEXT: s_and_b32 s20, s24, 0xffff000013402; VI-NEXT: s_add_i32 s21, s24, 313403; VI-NEXT: s_and_b32 s22, s25, 0xffff000013404; VI-NEXT: s_add_i32 s23, s25, 313405; VI-NEXT: s_and_b32 s24, s26, 0xffff000013406; VI-NEXT: s_add_i32 s25, s26, 313407; VI-NEXT: s_and_b32 s26, s27, 0xffff000013408; VI-NEXT: s_add_i32 s27, s27, 313409; VI-NEXT: s_and_b32 s40, s28, 0xffff000013410; VI-NEXT: s_add_i32 s28, s28, 313411; VI-NEXT: s_and_b32 s41, s29, 0xffff000013412; VI-NEXT: s_add_i32 s29, s29, 313413; VI-NEXT: s_and_b32 s29, s29, 0xffff13414; VI-NEXT: s_and_b32 s28, s28, 0xffff13415; VI-NEXT: s_and_b32 s27, s27, 0xffff13416; VI-NEXT: s_and_b32 s25, s25, 0xffff13417; VI-NEXT: s_and_b32 s23, s23, 0xffff13418; VI-NEXT: s_and_b32 s21, s21, 0xffff13419; VI-NEXT: s_and_b32 s19, s19, 0xffff13420; VI-NEXT: s_and_b32 s17, s17, 0xffff13421; VI-NEXT: s_and_b32 s15, s15, 0xffff13422; VI-NEXT: s_and_b32 s13, s13, 0xffff13423; VI-NEXT: s_and_b32 s11, s11, 0xffff13424; VI-NEXT: s_and_b32 s9, s9, 0xffff13425; VI-NEXT: s_and_b32 s7, s7, 0xffff13426; VI-NEXT: s_and_b32 s5, s5, 0xffff13427; VI-NEXT: s_or_b32 s29, s41, s2913428; VI-NEXT: s_or_b32 s28, s40, s2813429; VI-NEXT: s_or_b32 s26, s26, s2713430; VI-NEXT: s_or_b32 s24, s24, s2513431; VI-NEXT: s_or_b32 s22, s22, s2313432; VI-NEXT: s_or_b32 s20, s20, s2113433; VI-NEXT: s_or_b32 s18, s18, s1913434; VI-NEXT: s_or_b32 s16, s16, s1713435; VI-NEXT: s_or_b32 s14, s14, s1513436; VI-NEXT: s_or_b32 s12, s12, s1313437; VI-NEXT: s_or_b32 s10, s10, s1113438; VI-NEXT: s_or_b32 s8, s8, s913439; VI-NEXT: s_or_b32 s6, s6, s713440; VI-NEXT: s_or_b32 s4, s4, s513441; VI-NEXT: s_add_i32 s29, s29, 0x3000013442; VI-NEXT: s_add_i32 s28, s28, 0x3000013443; VI-NEXT: s_add_i32 s27, s26, 0x3000013444; VI-NEXT: s_add_i32 s26, s24, 0x3000013445; VI-NEXT: s_add_i32 s25, s22, 0x3000013446; VI-NEXT: s_add_i32 s24, s20, 0x3000013447; VI-NEXT: s_add_i32 s23, s18, 0x3000013448; VI-NEXT: s_add_i32 s22, s16, 0x3000013449; VI-NEXT: s_add_i32 s21, s14, 0x3000013450; VI-NEXT: s_add_i32 s20, s12, 0x3000013451; VI-NEXT: s_add_i32 s19, s10, 0x3000013452; VI-NEXT: s_add_i32 s18, s8, 0x3000013453; VI-NEXT: s_add_i32 s17, s6, 0x3000013454; VI-NEXT: s_add_i32 s16, s4, 0x3000013455; VI-NEXT: .LBB57_3: ; %end13456; VI-NEXT: v_mov_b32_e32 v0, s1613457; VI-NEXT: v_mov_b32_e32 v1, s1713458; VI-NEXT: v_mov_b32_e32 v2, s1813459; VI-NEXT: v_mov_b32_e32 v3, s1913460; VI-NEXT: v_mov_b32_e32 v4, s2013461; VI-NEXT: v_mov_b32_e32 v5, s2113462; VI-NEXT: v_mov_b32_e32 v6, s2213463; VI-NEXT: v_mov_b32_e32 v7, s2313464; VI-NEXT: v_mov_b32_e32 v8, s2413465; VI-NEXT: v_mov_b32_e32 v9, s2513466; VI-NEXT: v_mov_b32_e32 v10, s2613467; VI-NEXT: v_mov_b32_e32 v11, s2713468; VI-NEXT: v_mov_b32_e32 v12, s2813469; VI-NEXT: v_mov_b32_e32 v13, s2913470; VI-NEXT: s_setpc_b64 s[30:31]13471; VI-NEXT: .LBB57_4:13472; VI-NEXT: s_branch .LBB57_213473;13474; GFX9-LABEL: bitcast_v28i16_to_v28f16_scalar:13475; GFX9: ; %bb.0:13476; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)13477; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v013478; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec13479; GFX9-NEXT: s_cbranch_scc0 .LBB57_313480; GFX9-NEXT: ; %bb.1: ; %cmp.false13481; GFX9-NEXT: s_cbranch_execnz .LBB57_413482; GFX9-NEXT: .LBB57_2: ; %cmp.true13483; GFX9-NEXT: v_pk_add_u16 v13, s29, 3 op_sel_hi:[1,0]13484; GFX9-NEXT: v_pk_add_u16 v12, s28, 3 op_sel_hi:[1,0]13485; GFX9-NEXT: v_pk_add_u16 v11, s27, 3 op_sel_hi:[1,0]13486; GFX9-NEXT: v_pk_add_u16 v10, s26, 3 op_sel_hi:[1,0]13487; GFX9-NEXT: v_pk_add_u16 v9, s25, 3 op_sel_hi:[1,0]13488; GFX9-NEXT: v_pk_add_u16 v8, s24, 3 op_sel_hi:[1,0]13489; GFX9-NEXT: v_pk_add_u16 v7, s23, 3 op_sel_hi:[1,0]13490; GFX9-NEXT: v_pk_add_u16 v6, s22, 3 op_sel_hi:[1,0]13491; GFX9-NEXT: v_pk_add_u16 v5, s21, 3 op_sel_hi:[1,0]13492; GFX9-NEXT: v_pk_add_u16 v4, s20, 3 op_sel_hi:[1,0]13493; GFX9-NEXT: v_pk_add_u16 v3, s19, 3 op_sel_hi:[1,0]13494; GFX9-NEXT: v_pk_add_u16 v2, s18, 3 op_sel_hi:[1,0]13495; GFX9-NEXT: v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]13496; GFX9-NEXT: v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]13497; GFX9-NEXT: s_setpc_b64 s[30:31]13498; GFX9-NEXT: .LBB57_3:13499; GFX9-NEXT: s_branch .LBB57_213500; GFX9-NEXT: .LBB57_4:13501; GFX9-NEXT: v_mov_b32_e32 v0, s1613502; GFX9-NEXT: v_mov_b32_e32 v1, s1713503; GFX9-NEXT: v_mov_b32_e32 v2, s1813504; GFX9-NEXT: v_mov_b32_e32 v3, s1913505; GFX9-NEXT: v_mov_b32_e32 v4, s2013506; GFX9-NEXT: v_mov_b32_e32 v5, s2113507; GFX9-NEXT: v_mov_b32_e32 v6, s2213508; GFX9-NEXT: v_mov_b32_e32 v7, s2313509; GFX9-NEXT: v_mov_b32_e32 v8, s2413510; GFX9-NEXT: v_mov_b32_e32 v9, s2513511; GFX9-NEXT: v_mov_b32_e32 v10, s2613512; GFX9-NEXT: v_mov_b32_e32 v11, s2713513; GFX9-NEXT: v_mov_b32_e32 v12, s2813514; GFX9-NEXT: v_mov_b32_e32 v13, s2913515; GFX9-NEXT: v_mov_b32_e32 v14, s3013516; GFX9-NEXT: v_mov_b32_e32 v15, s3113517; GFX9-NEXT: s_setpc_b64 s[30:31]13518;13519; GFX11-LABEL: bitcast_v28i16_to_v28f16_scalar:13520; GFX11: ; %bb.0:13521; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)13522; GFX11-NEXT: s_mov_b32 s15, s313523; GFX11-NEXT: s_mov_b32 s14, s213524; GFX11-NEXT: s_mov_b32 s13, s113525; GFX11-NEXT: s_mov_b32 s12, s013526; GFX11-NEXT: s_cmp_lg_u32 s26, 013527; GFX11-NEXT: s_mov_b32 s0, 013528; GFX11-NEXT: s_cbranch_scc0 .LBB57_313529; GFX11-NEXT: ; %bb.1: ; %Flow13530; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s013531; GFX11-NEXT: s_cbranch_vccnz .LBB57_413532; GFX11-NEXT: .LBB57_2: ; %cmp.true13533; GFX11-NEXT: v_pk_add_u16 v13, s25, 3 op_sel_hi:[1,0]13534; GFX11-NEXT: v_pk_add_u16 v12, s24, 3 op_sel_hi:[1,0]13535; GFX11-NEXT: v_pk_add_u16 v11, s23, 3 op_sel_hi:[1,0]13536; GFX11-NEXT: v_pk_add_u16 v10, s22, 3 op_sel_hi:[1,0]13537; GFX11-NEXT: v_pk_add_u16 v9, s21, 3 op_sel_hi:[1,0]13538; GFX11-NEXT: v_pk_add_u16 v8, s20, 3 op_sel_hi:[1,0]13539; GFX11-NEXT: v_pk_add_u16 v7, s19, 3 op_sel_hi:[1,0]13540; GFX11-NEXT: v_pk_add_u16 v6, s18, 3 op_sel_hi:[1,0]13541; GFX11-NEXT: v_pk_add_u16 v5, s17, 3 op_sel_hi:[1,0]13542; GFX11-NEXT: v_pk_add_u16 v4, s16, 3 op_sel_hi:[1,0]13543; GFX11-NEXT: v_pk_add_u16 v3, s15, 3 op_sel_hi:[1,0]13544; GFX11-NEXT: v_pk_add_u16 v2, s14, 3 op_sel_hi:[1,0]13545; GFX11-NEXT: v_pk_add_u16 v1, s13, 3 op_sel_hi:[1,0]13546; GFX11-NEXT: v_pk_add_u16 v0, s12, 3 op_sel_hi:[1,0]13547; GFX11-NEXT: s_setpc_b64 s[30:31]13548; GFX11-NEXT: .LBB57_3:13549; GFX11-NEXT: s_branch .LBB57_213550; GFX11-NEXT: .LBB57_4:13551; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s1313552; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s1513553; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s1713554; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s1913555; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s2113556; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s2313557; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s2513558; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s2713559; GFX11-NEXT: s_setpc_b64 s[30:31]13560 %cmp = icmp eq i32 %b, 013561 br i1 %cmp, label %cmp.true, label %cmp.false13562 13563cmp.true:13564 %a1 = add <28 x i16> %a, splat (i16 3)13565 %a2 = bitcast <28 x i16> %a1 to <28 x half>13566 br label %end13567 13568cmp.false:13569 %a3 = bitcast <28 x i16> %a to <28 x half>13570 br label %end13571 13572end:13573 %phi = phi <28 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]13574 ret <28 x half> %phi13575}13576 13577define <28 x i16> @bitcast_v28f16_to_v28i16(<28 x half> %a, i32 %b) {13578; SI-LABEL: bitcast_v28f16_to_v28i16:13579; SI: ; %bb.0:13580; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)13581; SI-NEXT: v_cvt_f16_f32_e32 v0, v013582; SI-NEXT: v_cvt_f16_f32_e32 v1, v113583; SI-NEXT: v_cvt_f16_f32_e32 v2, v213584; SI-NEXT: v_cvt_f16_f32_e32 v3, v313585; SI-NEXT: v_cvt_f16_f32_e32 v4, v413586; SI-NEXT: v_cvt_f16_f32_e32 v5, v513587; SI-NEXT: v_cvt_f16_f32_e32 v6, v613588; SI-NEXT: v_cvt_f16_f32_e32 v7, v713589; SI-NEXT: v_cvt_f16_f32_e32 v8, v813590; SI-NEXT: v_cvt_f16_f32_e32 v9, v913591; SI-NEXT: v_cvt_f16_f32_e32 v10, v1013592; SI-NEXT: v_cvt_f16_f32_e32 v11, v1113593; SI-NEXT: v_cvt_f16_f32_e32 v12, v1213594; SI-NEXT: v_cvt_f16_f32_e32 v13, v1313595; SI-NEXT: v_cvt_f16_f32_e32 v14, v1413596; SI-NEXT: v_cvt_f16_f32_e32 v15, v1513597; SI-NEXT: v_cvt_f16_f32_e32 v16, v1613598; SI-NEXT: v_cvt_f16_f32_e32 v17, v1713599; SI-NEXT: v_cvt_f16_f32_e32 v18, v1813600; SI-NEXT: v_cvt_f16_f32_e32 v19, v1913601; SI-NEXT: v_cvt_f16_f32_e32 v20, v2013602; SI-NEXT: v_cvt_f16_f32_e32 v21, v2113603; SI-NEXT: v_cvt_f16_f32_e32 v22, v2213604; SI-NEXT: v_cvt_f16_f32_e32 v23, v2313605; SI-NEXT: v_cvt_f16_f32_e32 v24, v2413606; SI-NEXT: v_cvt_f16_f32_e32 v25, v2513607; SI-NEXT: v_cvt_f16_f32_e32 v26, v2613608; SI-NEXT: v_cvt_f16_f32_e32 v27, v2713609; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2813610; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc13611; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]13612; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]13613; SI-NEXT: s_cbranch_execz .LBB58_213614; SI-NEXT: ; %bb.1: ; %cmp.true13615; SI-NEXT: v_cvt_f32_f16_e32 v27, v2713616; SI-NEXT: v_cvt_f32_f16_e32 v26, v2613617; SI-NEXT: v_cvt_f32_f16_e32 v23, v2313618; SI-NEXT: v_cvt_f32_f16_e32 v22, v2213619; SI-NEXT: v_cvt_f32_f16_e32 v19, v1913620; SI-NEXT: v_cvt_f32_f16_e32 v18, v1813621; SI-NEXT: v_cvt_f32_f16_e32 v15, v1513622; SI-NEXT: v_add_f32_e32 v27, 0x38000000, v2713623; SI-NEXT: v_cvt_f32_f16_e32 v14, v1413624; SI-NEXT: v_cvt_f32_f16_e32 v11, v1113625; SI-NEXT: v_add_f32_e32 v26, 0x38000000, v2613626; SI-NEXT: v_cvt_f16_f32_e32 v27, v2713627; SI-NEXT: v_add_f32_e32 v23, 0x38000000, v2313628; SI-NEXT: v_cvt_f32_f16_e32 v10, v1013629; SI-NEXT: v_cvt_f32_f16_e32 v7, v713630; SI-NEXT: v_cvt_f16_f32_e32 v26, v2613631; SI-NEXT: v_cvt_f16_f32_e32 v23, v2313632; SI-NEXT: v_add_f32_e32 v22, 0x38000000, v2213633; SI-NEXT: v_add_f32_e32 v19, 0x38000000, v1913634; SI-NEXT: v_cvt_f32_f16_e32 v6, v613635; SI-NEXT: v_cvt_f32_f16_e32 v3, v313636; SI-NEXT: v_cvt_f16_f32_e32 v22, v2213637; SI-NEXT: v_cvt_f16_f32_e32 v19, v1913638; SI-NEXT: v_add_f32_e32 v18, 0x38000000, v1813639; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v1513640; SI-NEXT: v_cvt_f32_f16_e32 v2, v213641; SI-NEXT: v_cvt_f32_f16_e32 v1, v113642; SI-NEXT: v_cvt_f32_f16_e32 v5, v513643; SI-NEXT: v_cvt_f32_f16_e32 v9, v913644; SI-NEXT: v_cvt_f32_f16_e32 v13, v1313645; SI-NEXT: v_cvt_f32_f16_e32 v17, v1713646; SI-NEXT: v_cvt_f32_f16_e32 v21, v2113647; SI-NEXT: v_cvt_f32_f16_e32 v25, v2513648; SI-NEXT: v_cvt_f16_f32_e32 v18, v1813649; SI-NEXT: v_cvt_f16_f32_e32 v15, v1513650; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v1413651; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v1113652; SI-NEXT: v_cvt_f32_f16_e32 v0, v013653; SI-NEXT: v_cvt_f32_f16_e32 v4, v413654; SI-NEXT: v_cvt_f32_f16_e32 v8, v813655; SI-NEXT: v_cvt_f32_f16_e32 v12, v1213656; SI-NEXT: v_cvt_f32_f16_e32 v16, v1613657; SI-NEXT: v_cvt_f32_f16_e32 v20, v2013658; SI-NEXT: v_cvt_f32_f16_e32 v24, v2413659; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v2713660; SI-NEXT: v_cvt_f16_f32_e32 v14, v1413661; SI-NEXT: v_cvt_f16_f32_e32 v11, v1113662; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v1013663; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v713664; SI-NEXT: v_or_b32_e32 v26, v26, v2813665; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v2313666; SI-NEXT: v_cvt_f16_f32_e32 v10, v1013667; SI-NEXT: v_cvt_f16_f32_e32 v7, v713668; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v613669; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v313670; SI-NEXT: v_or_b32_e32 v22, v22, v2813671; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v1913672; SI-NEXT: v_cvt_f16_f32_e32 v6, v613673; SI-NEXT: v_cvt_f16_f32_e32 v3, v313674; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v213675; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v113676; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v513677; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v913678; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v1313679; SI-NEXT: v_add_f32_e32 v17, 0x38000000, v1713680; SI-NEXT: v_add_f32_e32 v21, 0x38000000, v2113681; SI-NEXT: v_add_f32_e32 v25, 0x38000000, v2513682; SI-NEXT: v_or_b32_e32 v18, v18, v2813683; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v1513684; SI-NEXT: v_cvt_f16_f32_e32 v2, v213685; SI-NEXT: v_cvt_f16_f32_e32 v1, v113686; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v013687; SI-NEXT: v_cvt_f16_f32_e32 v5, v513688; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v413689; SI-NEXT: v_cvt_f16_f32_e32 v9, v913690; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v813691; SI-NEXT: v_cvt_f16_f32_e32 v13, v1313692; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v1213693; SI-NEXT: v_cvt_f16_f32_e32 v17, v1713694; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v1613695; SI-NEXT: v_cvt_f16_f32_e32 v21, v2113696; SI-NEXT: v_add_f32_e32 v20, 0x38000000, v2013697; SI-NEXT: v_cvt_f16_f32_e32 v25, v2513698; SI-NEXT: v_add_f32_e32 v24, 0x38000000, v2413699; SI-NEXT: v_or_b32_e32 v14, v14, v2813700; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v1113701; SI-NEXT: v_cvt_f16_f32_e32 v0, v013702; SI-NEXT: v_cvt_f16_f32_e32 v4, v413703; SI-NEXT: v_cvt_f16_f32_e32 v8, v813704; SI-NEXT: v_cvt_f16_f32_e32 v12, v1213705; SI-NEXT: v_cvt_f16_f32_e32 v16, v1613706; SI-NEXT: v_cvt_f16_f32_e32 v20, v2013707; SI-NEXT: v_cvt_f16_f32_e32 v24, v2413708; SI-NEXT: v_or_b32_e32 v10, v10, v2813709; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v713710; SI-NEXT: v_or_b32_e32 v6, v6, v2813711; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v313712; SI-NEXT: v_or_b32_e32 v2, v2, v2813713; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v113714; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v513715; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v913716; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v1313717; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v1713718; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v2113719; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v2513720; SI-NEXT: v_or_b32_e32 v0, v0, v113721; SI-NEXT: v_or_b32_e32 v4, v4, v513722; SI-NEXT: v_or_b32_e32 v8, v8, v913723; SI-NEXT: v_or_b32_e32 v12, v12, v1313724; SI-NEXT: v_or_b32_e32 v16, v16, v1713725; SI-NEXT: v_or_b32_e32 v20, v20, v2113726; SI-NEXT: v_or_b32_e32 v24, v24, v2513727; SI-NEXT: v_alignbit_b32 v1, v2, v1, 1613728; SI-NEXT: v_alignbit_b32 v5, v6, v5, 1613729; SI-NEXT: v_alignbit_b32 v9, v10, v9, 1613730; SI-NEXT: v_alignbit_b32 v13, v14, v13, 1613731; SI-NEXT: v_alignbit_b32 v17, v18, v17, 1613732; SI-NEXT: v_alignbit_b32 v21, v22, v21, 1613733; SI-NEXT: v_alignbit_b32 v25, v26, v25, 1613734; SI-NEXT: .LBB58_2: ; %end13735; SI-NEXT: s_or_b64 exec, exec, s[4:5]13736; SI-NEXT: s_setpc_b64 s[30:31]13737;13738; VI-LABEL: bitcast_v28f16_to_v28i16:13739; VI: ; %bb.0:13740; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)13741; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1413742; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc13743; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]13744; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]13745; VI-NEXT: s_cbranch_execz .LBB58_213746; VI-NEXT: ; %bb.1: ; %cmp.true13747; VI-NEXT: v_mov_b32_e32 v15, 0x20013748; VI-NEXT: v_add_f16_e32 v19, 0x200, v1313749; VI-NEXT: v_add_f16_sdwa v13, v13, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD13750; VI-NEXT: v_or_b32_e32 v13, v19, v1313751; VI-NEXT: v_add_f16_e32 v19, 0x200, v1213752; VI-NEXT: v_add_f16_sdwa v12, v12, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD13753; VI-NEXT: v_or_b32_e32 v12, v19, v1213754; VI-NEXT: v_add_f16_e32 v19, 0x200, v1113755; VI-NEXT: v_add_f16_sdwa v11, v11, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD13756; VI-NEXT: v_or_b32_e32 v11, v19, v1113757; VI-NEXT: v_add_f16_e32 v19, 0x200, v1013758; VI-NEXT: v_add_f16_sdwa v10, v10, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD13759; VI-NEXT: v_or_b32_e32 v10, v19, v1013760; VI-NEXT: v_add_f16_e32 v19, 0x200, v913761; VI-NEXT: v_add_f16_sdwa v9, v9, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD13762; VI-NEXT: v_or_b32_e32 v9, v19, v913763; VI-NEXT: v_add_f16_e32 v19, 0x200, v813764; VI-NEXT: v_add_f16_sdwa v8, v8, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD13765; VI-NEXT: v_or_b32_e32 v8, v19, v813766; VI-NEXT: v_add_f16_e32 v19, 0x200, v713767; VI-NEXT: v_add_f16_sdwa v7, v7, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD13768; VI-NEXT: v_or_b32_e32 v7, v19, v713769; VI-NEXT: v_add_f16_e32 v19, 0x200, v613770; VI-NEXT: v_add_f16_sdwa v6, v6, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD13771; VI-NEXT: v_add_f16_e32 v14, 0x200, v013772; VI-NEXT: v_add_f16_sdwa v0, v0, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD13773; VI-NEXT: v_add_f16_e32 v16, 0x200, v113774; VI-NEXT: v_add_f16_sdwa v1, v1, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD13775; VI-NEXT: v_add_f16_e32 v17, 0x200, v213776; VI-NEXT: v_add_f16_sdwa v2, v2, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD13777; VI-NEXT: v_add_f16_e32 v18, 0x200, v313778; VI-NEXT: v_add_f16_sdwa v3, v3, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD13779; VI-NEXT: v_or_b32_e32 v6, v19, v613780; VI-NEXT: v_add_f16_e32 v19, 0x200, v413781; VI-NEXT: v_add_f16_sdwa v4, v4, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD13782; VI-NEXT: v_add_f16_sdwa v15, v5, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD13783; VI-NEXT: v_add_f16_e32 v5, 0x200, v513784; VI-NEXT: v_or_b32_e32 v5, v5, v1513785; VI-NEXT: v_or_b32_e32 v4, v19, v413786; VI-NEXT: v_or_b32_e32 v3, v18, v313787; VI-NEXT: v_or_b32_e32 v2, v17, v213788; VI-NEXT: v_or_b32_e32 v1, v16, v113789; VI-NEXT: v_or_b32_e32 v0, v14, v013790; VI-NEXT: .LBB58_2: ; %end13791; VI-NEXT: s_or_b64 exec, exec, s[4:5]13792; VI-NEXT: s_setpc_b64 s[30:31]13793;13794; GFX9-LABEL: bitcast_v28f16_to_v28i16:13795; GFX9: ; %bb.0:13796; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)13797; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1413798; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc13799; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]13800; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]13801; GFX9-NEXT: s_cbranch_execz .LBB58_213802; GFX9-NEXT: ; %bb.1: ; %cmp.true13803; GFX9-NEXT: s_movk_i32 s6, 0x20013804; GFX9-NEXT: v_pk_add_f16 v13, v13, s6 op_sel_hi:[1,0]13805; GFX9-NEXT: v_pk_add_f16 v12, v12, s6 op_sel_hi:[1,0]13806; GFX9-NEXT: v_pk_add_f16 v11, v11, s6 op_sel_hi:[1,0]13807; GFX9-NEXT: v_pk_add_f16 v10, v10, s6 op_sel_hi:[1,0]13808; GFX9-NEXT: v_pk_add_f16 v9, v9, s6 op_sel_hi:[1,0]13809; GFX9-NEXT: v_pk_add_f16 v8, v8, s6 op_sel_hi:[1,0]13810; GFX9-NEXT: v_pk_add_f16 v7, v7, s6 op_sel_hi:[1,0]13811; GFX9-NEXT: v_pk_add_f16 v6, v6, s6 op_sel_hi:[1,0]13812; GFX9-NEXT: v_pk_add_f16 v5, v5, s6 op_sel_hi:[1,0]13813; GFX9-NEXT: v_pk_add_f16 v4, v4, s6 op_sel_hi:[1,0]13814; GFX9-NEXT: v_pk_add_f16 v3, v3, s6 op_sel_hi:[1,0]13815; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]13816; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]13817; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]13818; GFX9-NEXT: .LBB58_2: ; %end13819; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]13820; GFX9-NEXT: s_setpc_b64 s[30:31]13821;13822; GFX11-LABEL: bitcast_v28f16_to_v28i16:13823; GFX11: ; %bb.0:13824; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)13825; GFX11-NEXT: s_mov_b32 s0, exec_lo13826; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v1413827; GFX11-NEXT: s_xor_b32 s0, exec_lo, s013828; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)13829; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s013830; GFX11-NEXT: s_cbranch_execz .LBB58_213831; GFX11-NEXT: ; %bb.1: ; %cmp.true13832; GFX11-NEXT: v_pk_add_f16 v13, 0x200, v13 op_sel_hi:[0,1]13833; GFX11-NEXT: v_pk_add_f16 v12, 0x200, v12 op_sel_hi:[0,1]13834; GFX11-NEXT: v_pk_add_f16 v11, 0x200, v11 op_sel_hi:[0,1]13835; GFX11-NEXT: v_pk_add_f16 v10, 0x200, v10 op_sel_hi:[0,1]13836; GFX11-NEXT: v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1]13837; GFX11-NEXT: v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1]13838; GFX11-NEXT: v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]13839; GFX11-NEXT: v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]13840; GFX11-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]13841; GFX11-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]13842; GFX11-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]13843; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]13844; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]13845; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]13846; GFX11-NEXT: .LBB58_2: ; %end13847; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s013848; GFX11-NEXT: s_setpc_b64 s[30:31]13849 %cmp = icmp eq i32 %b, 013850 br i1 %cmp, label %cmp.true, label %cmp.false13851 13852cmp.true:13853 %a1 = fadd <28 x half> %a, splat (half 0xH0200)13854 %a2 = bitcast <28 x half> %a1 to <28 x i16>13855 br label %end13856 13857cmp.false:13858 %a3 = bitcast <28 x half> %a to <28 x i16>13859 br label %end13860 13861end:13862 %phi = phi <28 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]13863 ret <28 x i16> %phi13864}13865 13866define inreg <28 x i16> @bitcast_v28f16_to_v28i16_scalar(<28 x half> inreg %a, i32 inreg %b) {13867; SI-LABEL: bitcast_v28f16_to_v28i16_scalar:13868; SI: ; %bb.0:13869; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)13870; SI-NEXT: v_mov_b32_e32 v17, v1213871; SI-NEXT: v_mov_b32_e32 v21, v1113872; SI-NEXT: v_mov_b32_e32 v22, v813873; SI-NEXT: v_mov_b32_e32 v25, v713874; SI-NEXT: v_mov_b32_e32 v18, v413875; SI-NEXT: v_mov_b32_e32 v26, v313876; SI-NEXT: v_mov_b32_e32 v28, v013877; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1413878; SI-NEXT: v_cvt_f16_f32_e32 v0, s1613879; SI-NEXT: v_cvt_f16_f32_e32 v3, s1913880; SI-NEXT: v_cvt_f16_f32_e32 v4, s2013881; SI-NEXT: v_cvt_f16_f32_e32 v7, s2313882; SI-NEXT: v_cvt_f16_f32_e32 v8, s2413883; SI-NEXT: v_cvt_f16_f32_e32 v11, s2713884; SI-NEXT: v_cvt_f16_f32_e32 v15, v113885; SI-NEXT: v_cvt_f16_f32_e32 v16, v213886; SI-NEXT: v_cvt_f16_f32_e32 v19, v513887; SI-NEXT: v_cvt_f16_f32_e32 v20, v613888; SI-NEXT: v_cvt_f16_f32_e32 v23, v913889; SI-NEXT: v_cvt_f16_f32_e32 v24, v1013890; SI-NEXT: v_cvt_f16_f32_e32 v27, v1313891; SI-NEXT: v_cvt_f16_f32_e32 v12, s2813892; SI-NEXT: v_cvt_f16_f32_e32 v14, v2813893; SI-NEXT: v_cvt_f16_f32_e32 v30, v2613894; SI-NEXT: v_cvt_f16_f32_e32 v18, v1813895; SI-NEXT: v_cvt_f16_f32_e32 v36, v2513896; SI-NEXT: v_cvt_f16_f32_e32 v22, v2213897; SI-NEXT: v_cvt_f16_f32_e32 v37, v2113898; SI-NEXT: v_cvt_f16_f32_e32 v26, v1713899; SI-NEXT: v_cvt_f16_f32_e32 v34, s1713900; SI-NEXT: v_cvt_f16_f32_e32 v2, s1813901; SI-NEXT: v_cvt_f16_f32_e32 v32, s2113902; SI-NEXT: v_cvt_f16_f32_e32 v6, s2213903; SI-NEXT: v_cvt_f16_f32_e32 v29, s2513904; SI-NEXT: v_cvt_f16_f32_e32 v10, s2613905; SI-NEXT: v_cvt_f16_f32_e32 v35, s2913906; SI-NEXT: s_and_b64 s[4:5], vcc, exec13907; SI-NEXT: s_cbranch_scc0 .LBB59_413908; SI-NEXT: ; %bb.1: ; %cmp.false13909; SI-NEXT: s_cbranch_execnz .LBB59_313910; SI-NEXT: .LBB59_2: ; %cmp.true13911; SI-NEXT: v_cvt_f32_f16_e32 v11, v1113912; SI-NEXT: v_cvt_f32_f16_e32 v7, v713913; SI-NEXT: v_cvt_f32_f16_e32 v10, v1013914; SI-NEXT: v_cvt_f32_f16_e32 v19, v1913915; SI-NEXT: v_cvt_f32_f16_e32 v3, v313916; SI-NEXT: v_cvt_f32_f16_e32 v6, v613917; SI-NEXT: v_cvt_f32_f16_e32 v15, v1513918; SI-NEXT: v_cvt_f32_f16_e32 v18, v1813919; SI-NEXT: v_cvt_f32_f16_e32 v23, v2313920; SI-NEXT: v_cvt_f32_f16_e32 v2, v213921; SI-NEXT: v_cvt_f32_f16_e32 v14, v1413922; SI-NEXT: v_cvt_f32_f16_e32 v22, v2213923; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v1113924; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v713925; SI-NEXT: v_cvt_f16_f32_e32 v11, v1113926; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v1013927; SI-NEXT: v_add_f32_e32 v19, 0x38000000, v1913928; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v313929; SI-NEXT: v_cvt_f16_f32_e32 v7, v713930; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v613931; SI-NEXT: v_cvt_f16_f32_e32 v10, v1013932; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v1513933; SI-NEXT: v_cvt_f16_f32_e32 v19, v1913934; SI-NEXT: v_add_f32_e32 v18, 0x38000000, v1813935; SI-NEXT: v_add_f32_e32 v23, 0x38000000, v2313936; SI-NEXT: v_cvt_f16_f32_e32 v3, v313937; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v213938; SI-NEXT: v_cvt_f16_f32_e32 v6, v613939; SI-NEXT: v_cvt_f16_f32_e32 v15, v1513940; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v1413941; SI-NEXT: v_cvt_f16_f32_e32 v18, v1813942; SI-NEXT: v_cvt_f16_f32_e32 v23, v2313943; SI-NEXT: v_add_f32_e32 v22, 0x38000000, v2213944; SI-NEXT: v_cvt_f16_f32_e32 v2, v213945; SI-NEXT: v_cvt_f16_f32_e32 v14, v1413946; SI-NEXT: v_cvt_f16_f32_e32 v22, v2213947; SI-NEXT: v_cvt_f32_f16_e32 v1, v3413948; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v1113949; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v713950; SI-NEXT: v_or_b32_e32 v10, v10, v1313951; SI-NEXT: v_cvt_f32_f16_e32 v13, v3513952; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v1913953; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v313954; SI-NEXT: v_or_b32_e32 v6, v6, v913955; SI-NEXT: v_cvt_f32_f16_e32 v9, v2913956; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v1513957; SI-NEXT: v_or_b32_e32 v18, v18, v2113958; SI-NEXT: v_cvt_f32_f16_e32 v21, v3613959; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v2313960; SI-NEXT: v_cvt_f32_f16_e32 v27, v2713961; SI-NEXT: v_or_b32_e32 v2, v2, v513962; SI-NEXT: v_cvt_f32_f16_e32 v5, v3213963; SI-NEXT: v_or_b32_e32 v14, v14, v1713964; SI-NEXT: v_cvt_f32_f16_e32 v17, v3013965; SI-NEXT: v_or_b32_e32 v22, v22, v2513966; SI-NEXT: v_cvt_f32_f16_e32 v25, v3713967; SI-NEXT: v_cvt_f32_f16_e32 v26, v2613968; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v113969; SI-NEXT: v_cvt_f16_f32_e32 v1, v113970; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v1313971; SI-NEXT: v_cvt_f32_f16_e32 v0, v013972; SI-NEXT: v_cvt_f32_f16_e32 v4, v413973; SI-NEXT: v_cvt_f32_f16_e32 v8, v813974; SI-NEXT: v_cvt_f32_f16_e32 v12, v1213975; SI-NEXT: v_cvt_f32_f16_e32 v16, v1613976; SI-NEXT: v_cvt_f32_f16_e32 v20, v2013977; SI-NEXT: v_cvt_f32_f16_e32 v24, v2413978; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v913979; SI-NEXT: v_cvt_f16_f32_e32 v13, v1313980; SI-NEXT: v_add_f32_e32 v21, 0x38000000, v2113981; SI-NEXT: v_add_f32_e32 v27, 0x38000000, v2713982; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v513983; SI-NEXT: v_cvt_f16_f32_e32 v9, v913984; SI-NEXT: v_add_f32_e32 v17, 0x38000000, v1713985; SI-NEXT: v_cvt_f16_f32_e32 v21, v2113986; SI-NEXT: v_add_f32_e32 v25, 0x38000000, v2513987; SI-NEXT: v_cvt_f16_f32_e32 v27, v2713988; SI-NEXT: v_add_f32_e32 v26, 0x38000000, v2613989; SI-NEXT: v_cvt_f16_f32_e32 v5, v513990; SI-NEXT: v_cvt_f16_f32_e32 v17, v1713991; SI-NEXT: v_cvt_f16_f32_e32 v26, v2613992; SI-NEXT: v_cvt_f16_f32_e32 v25, v2513993; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v113994; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v013995; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v413996; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v813997; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v1213998; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v1613999; SI-NEXT: v_add_f32_e32 v20, 0x38000000, v2014000; SI-NEXT: v_add_f32_e32 v24, 0x38000000, v2414001; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v1314002; SI-NEXT: v_cvt_f16_f32_e32 v0, v014003; SI-NEXT: v_cvt_f16_f32_e32 v4, v414004; SI-NEXT: v_cvt_f16_f32_e32 v8, v814005; SI-NEXT: v_cvt_f16_f32_e32 v12, v1214006; SI-NEXT: v_cvt_f16_f32_e32 v16, v1614007; SI-NEXT: v_cvt_f16_f32_e32 v20, v2014008; SI-NEXT: v_cvt_f16_f32_e32 v24, v2414009; SI-NEXT: v_lshr_b64 v[34:35], v[1:2], 1614010; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v914011; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v2114012; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v2714013; SI-NEXT: v_lshr_b64 v[35:36], v[13:14], 1614014; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v514015; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v1714016; SI-NEXT: v_or_b32_e32 v26, v26, v2814017; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v2514018; SI-NEXT: v_lshr_b64 v[29:30], v[9:10], 1614019; SI-NEXT: v_lshr_b64 v[36:37], v[21:22], 1614020; SI-NEXT: v_lshr_b64 v[32:33], v[5:6], 1614021; SI-NEXT: v_lshr_b64 v[30:31], v[17:18], 1614022; SI-NEXT: v_lshr_b64 v[37:38], v[25:26], 1614023; SI-NEXT: v_or_b32_e32 v0, v0, v114024; SI-NEXT: v_or_b32_e32 v4, v4, v514025; SI-NEXT: v_or_b32_e32 v8, v8, v914026; SI-NEXT: v_or_b32_e32 v12, v12, v1314027; SI-NEXT: v_or_b32_e32 v16, v16, v1714028; SI-NEXT: v_or_b32_e32 v20, v20, v2114029; SI-NEXT: v_or_b32_e32 v24, v24, v2514030; SI-NEXT: .LBB59_3: ; %end14031; SI-NEXT: v_mov_b32_e32 v1, v3414032; SI-NEXT: v_mov_b32_e32 v5, v3214033; SI-NEXT: v_mov_b32_e32 v9, v2914034; SI-NEXT: v_mov_b32_e32 v13, v3514035; SI-NEXT: v_mov_b32_e32 v17, v3014036; SI-NEXT: v_mov_b32_e32 v21, v3614037; SI-NEXT: v_mov_b32_e32 v25, v3714038; SI-NEXT: s_setpc_b64 s[30:31]14039; SI-NEXT: .LBB59_4:14040; SI-NEXT: s_branch .LBB59_214041;14042; VI-LABEL: bitcast_v28f16_to_v28i16_scalar:14043; VI: ; %bb.0:14044; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14045; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v014046; VI-NEXT: s_and_b64 s[4:5], vcc, exec14047; VI-NEXT: s_cbranch_scc0 .LBB59_314048; VI-NEXT: ; %bb.1: ; %cmp.false14049; VI-NEXT: s_cbranch_execnz .LBB59_414050; VI-NEXT: .LBB59_2: ; %cmp.true14051; VI-NEXT: s_lshr_b32 s5, s28, 1614052; VI-NEXT: v_mov_b32_e32 v0, 0x20014053; VI-NEXT: v_mov_b32_e32 v2, s514054; VI-NEXT: s_lshr_b32 s5, s29, 1614055; VI-NEXT: v_add_f16_e32 v1, s28, v014056; VI-NEXT: v_add_f16_sdwa v2, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD14057; VI-NEXT: v_mov_b32_e32 v4, s514058; VI-NEXT: s_lshr_b32 s5, s27, 1614059; VI-NEXT: v_or_b32_e32 v12, v1, v214060; VI-NEXT: v_mov_b32_e32 v2, s514061; VI-NEXT: v_add_f16_e32 v1, s27, v014062; VI-NEXT: v_add_f16_sdwa v2, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD14063; VI-NEXT: s_lshr_b32 s5, s26, 1614064; VI-NEXT: v_or_b32_e32 v11, v1, v214065; VI-NEXT: v_mov_b32_e32 v2, s514066; VI-NEXT: v_add_f16_e32 v1, s26, v014067; VI-NEXT: v_add_f16_sdwa v2, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD14068; VI-NEXT: s_lshr_b32 s5, s25, 1614069; VI-NEXT: v_or_b32_e32 v10, v1, v214070; VI-NEXT: v_mov_b32_e32 v2, s514071; VI-NEXT: v_add_f16_e32 v1, s25, v014072; VI-NEXT: v_add_f16_sdwa v2, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD14073; VI-NEXT: s_lshr_b32 s5, s24, 1614074; VI-NEXT: v_or_b32_e32 v9, v1, v214075; VI-NEXT: v_mov_b32_e32 v2, s514076; VI-NEXT: v_add_f16_e32 v1, s24, v014077; VI-NEXT: v_add_f16_sdwa v2, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD14078; VI-NEXT: s_lshr_b32 s5, s23, 1614079; VI-NEXT: v_or_b32_e32 v8, v1, v214080; VI-NEXT: v_mov_b32_e32 v2, s514081; VI-NEXT: v_add_f16_e32 v1, s23, v014082; VI-NEXT: v_add_f16_sdwa v2, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD14083; VI-NEXT: s_lshr_b32 s5, s22, 1614084; VI-NEXT: v_or_b32_e32 v7, v1, v214085; VI-NEXT: v_mov_b32_e32 v2, s514086; VI-NEXT: v_add_f16_e32 v1, s22, v014087; VI-NEXT: v_add_f16_sdwa v2, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD14088; VI-NEXT: s_lshr_b32 s5, s21, 1614089; VI-NEXT: v_or_b32_e32 v6, v1, v214090; VI-NEXT: v_mov_b32_e32 v2, s514091; VI-NEXT: v_add_f16_e32 v1, s21, v014092; VI-NEXT: v_add_f16_sdwa v2, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD14093; VI-NEXT: s_lshr_b32 s5, s20, 1614094; VI-NEXT: v_or_b32_e32 v5, v1, v214095; VI-NEXT: v_mov_b32_e32 v2, s514096; VI-NEXT: v_add_f16_e32 v3, s29, v014097; VI-NEXT: v_add_f16_sdwa v4, v4, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD14098; VI-NEXT: v_add_f16_e32 v1, s20, v014099; VI-NEXT: v_add_f16_sdwa v2, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD14100; VI-NEXT: s_lshr_b32 s5, s19, 1614101; VI-NEXT: v_or_b32_e32 v13, v3, v414102; VI-NEXT: v_or_b32_e32 v4, v1, v214103; VI-NEXT: v_mov_b32_e32 v2, s514104; VI-NEXT: v_add_f16_e32 v1, s19, v014105; VI-NEXT: v_add_f16_sdwa v2, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD14106; VI-NEXT: s_lshr_b32 s5, s18, 1614107; VI-NEXT: v_or_b32_e32 v3, v1, v214108; VI-NEXT: v_mov_b32_e32 v2, s514109; VI-NEXT: s_lshr_b32 s4, s16, 1614110; VI-NEXT: v_add_f16_e32 v1, s18, v014111; VI-NEXT: v_add_f16_sdwa v2, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD14112; VI-NEXT: v_or_b32_e32 v2, v1, v214113; VI-NEXT: v_mov_b32_e32 v1, s414114; VI-NEXT: s_lshr_b32 s4, s17, 1614115; VI-NEXT: v_add_f16_sdwa v15, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD14116; VI-NEXT: v_mov_b32_e32 v1, s414117; VI-NEXT: v_add_f16_e32 v14, s16, v014118; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD14119; VI-NEXT: v_add_f16_e32 v0, s17, v014120; VI-NEXT: v_or_b32_e32 v1, v0, v114121; VI-NEXT: v_or_b32_e32 v0, v14, v1514122; VI-NEXT: s_setpc_b64 s[30:31]14123; VI-NEXT: .LBB59_3:14124; VI-NEXT: s_branch .LBB59_214125; VI-NEXT: .LBB59_4:14126; VI-NEXT: v_mov_b32_e32 v0, s1614127; VI-NEXT: v_mov_b32_e32 v1, s1714128; VI-NEXT: v_mov_b32_e32 v2, s1814129; VI-NEXT: v_mov_b32_e32 v3, s1914130; VI-NEXT: v_mov_b32_e32 v4, s2014131; VI-NEXT: v_mov_b32_e32 v5, s2114132; VI-NEXT: v_mov_b32_e32 v6, s2214133; VI-NEXT: v_mov_b32_e32 v7, s2314134; VI-NEXT: v_mov_b32_e32 v8, s2414135; VI-NEXT: v_mov_b32_e32 v9, s2514136; VI-NEXT: v_mov_b32_e32 v10, s2614137; VI-NEXT: v_mov_b32_e32 v11, s2714138; VI-NEXT: v_mov_b32_e32 v12, s2814139; VI-NEXT: v_mov_b32_e32 v13, s2914140; VI-NEXT: v_mov_b32_e32 v14, s3014141; VI-NEXT: v_mov_b32_e32 v15, s3114142; VI-NEXT: s_setpc_b64 s[30:31]14143;14144; GFX9-LABEL: bitcast_v28f16_to_v28i16_scalar:14145; GFX9: ; %bb.0:14146; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14147; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v014148; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec14149; GFX9-NEXT: s_cbranch_scc0 .LBB59_314150; GFX9-NEXT: ; %bb.1: ; %cmp.false14151; GFX9-NEXT: s_cbranch_execnz .LBB59_414152; GFX9-NEXT: .LBB59_2: ; %cmp.true14153; GFX9-NEXT: v_mov_b32_e32 v0, 0x20014154; GFX9-NEXT: v_pk_add_f16 v13, s29, v0 op_sel_hi:[1,0]14155; GFX9-NEXT: v_pk_add_f16 v12, s28, v0 op_sel_hi:[1,0]14156; GFX9-NEXT: v_pk_add_f16 v11, s27, v0 op_sel_hi:[1,0]14157; GFX9-NEXT: v_pk_add_f16 v10, s26, v0 op_sel_hi:[1,0]14158; GFX9-NEXT: v_pk_add_f16 v9, s25, v0 op_sel_hi:[1,0]14159; GFX9-NEXT: v_pk_add_f16 v8, s24, v0 op_sel_hi:[1,0]14160; GFX9-NEXT: v_pk_add_f16 v7, s23, v0 op_sel_hi:[1,0]14161; GFX9-NEXT: v_pk_add_f16 v6, s22, v0 op_sel_hi:[1,0]14162; GFX9-NEXT: v_pk_add_f16 v5, s21, v0 op_sel_hi:[1,0]14163; GFX9-NEXT: v_pk_add_f16 v4, s20, v0 op_sel_hi:[1,0]14164; GFX9-NEXT: v_pk_add_f16 v3, s19, v0 op_sel_hi:[1,0]14165; GFX9-NEXT: v_pk_add_f16 v2, s18, v0 op_sel_hi:[1,0]14166; GFX9-NEXT: v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]14167; GFX9-NEXT: v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]14168; GFX9-NEXT: s_setpc_b64 s[30:31]14169; GFX9-NEXT: .LBB59_3:14170; GFX9-NEXT: s_branch .LBB59_214171; GFX9-NEXT: .LBB59_4:14172; GFX9-NEXT: v_mov_b32_e32 v0, s1614173; GFX9-NEXT: v_mov_b32_e32 v1, s1714174; GFX9-NEXT: v_mov_b32_e32 v2, s1814175; GFX9-NEXT: v_mov_b32_e32 v3, s1914176; GFX9-NEXT: v_mov_b32_e32 v4, s2014177; GFX9-NEXT: v_mov_b32_e32 v5, s2114178; GFX9-NEXT: v_mov_b32_e32 v6, s2214179; GFX9-NEXT: v_mov_b32_e32 v7, s2314180; GFX9-NEXT: v_mov_b32_e32 v8, s2414181; GFX9-NEXT: v_mov_b32_e32 v9, s2514182; GFX9-NEXT: v_mov_b32_e32 v10, s2614183; GFX9-NEXT: v_mov_b32_e32 v11, s2714184; GFX9-NEXT: v_mov_b32_e32 v12, s2814185; GFX9-NEXT: v_mov_b32_e32 v13, s2914186; GFX9-NEXT: v_mov_b32_e32 v14, s3014187; GFX9-NEXT: v_mov_b32_e32 v15, s3114188; GFX9-NEXT: s_setpc_b64 s[30:31]14189;14190; GFX11-LABEL: bitcast_v28f16_to_v28i16_scalar:14191; GFX11: ; %bb.0:14192; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14193; GFX11-NEXT: s_mov_b32 s15, s314194; GFX11-NEXT: s_mov_b32 s14, s214195; GFX11-NEXT: s_mov_b32 s13, s114196; GFX11-NEXT: s_mov_b32 s12, s014197; GFX11-NEXT: s_cmp_lg_u32 s26, 014198; GFX11-NEXT: s_mov_b32 s0, 014199; GFX11-NEXT: s_cbranch_scc0 .LBB59_314200; GFX11-NEXT: ; %bb.1: ; %Flow14201; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s014202; GFX11-NEXT: s_cbranch_vccnz .LBB59_414203; GFX11-NEXT: .LBB59_2: ; %cmp.true14204; GFX11-NEXT: v_pk_add_f16 v13, 0x200, s25 op_sel_hi:[0,1]14205; GFX11-NEXT: v_pk_add_f16 v12, 0x200, s24 op_sel_hi:[0,1]14206; GFX11-NEXT: v_pk_add_f16 v11, 0x200, s23 op_sel_hi:[0,1]14207; GFX11-NEXT: v_pk_add_f16 v10, 0x200, s22 op_sel_hi:[0,1]14208; GFX11-NEXT: v_pk_add_f16 v9, 0x200, s21 op_sel_hi:[0,1]14209; GFX11-NEXT: v_pk_add_f16 v8, 0x200, s20 op_sel_hi:[0,1]14210; GFX11-NEXT: v_pk_add_f16 v7, 0x200, s19 op_sel_hi:[0,1]14211; GFX11-NEXT: v_pk_add_f16 v6, 0x200, s18 op_sel_hi:[0,1]14212; GFX11-NEXT: v_pk_add_f16 v5, 0x200, s17 op_sel_hi:[0,1]14213; GFX11-NEXT: v_pk_add_f16 v4, 0x200, s16 op_sel_hi:[0,1]14214; GFX11-NEXT: v_pk_add_f16 v3, 0x200, s15 op_sel_hi:[0,1]14215; GFX11-NEXT: v_pk_add_f16 v2, 0x200, s14 op_sel_hi:[0,1]14216; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s13 op_sel_hi:[0,1]14217; GFX11-NEXT: v_pk_add_f16 v0, 0x200, s12 op_sel_hi:[0,1]14218; GFX11-NEXT: s_setpc_b64 s[30:31]14219; GFX11-NEXT: .LBB59_3:14220; GFX11-NEXT: s_branch .LBB59_214221; GFX11-NEXT: .LBB59_4:14222; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s1314223; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s1514224; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s1714225; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s1914226; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s2114227; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s2314228; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s2514229; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s2714230; GFX11-NEXT: s_setpc_b64 s[30:31]14231 %cmp = icmp eq i32 %b, 014232 br i1 %cmp, label %cmp.true, label %cmp.false14233 14234cmp.true:14235 %a1 = fadd <28 x half> %a, splat (half 0xH0200)14236 %a2 = bitcast <28 x half> %a1 to <28 x i16>14237 br label %end14238 14239cmp.false:14240 %a3 = bitcast <28 x half> %a to <28 x i16>14241 br label %end14242 14243end:14244 %phi = phi <28 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]14245 ret <28 x i16> %phi14246}14247;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:14248; GFX11-FAKE16: {{.*}}14249; GFX11-TRUE16: {{.*}}14250