1798 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52 3; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=SI %s4; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=VI %s5; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s6; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s7; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s8 9define <3 x half> @bitcast_v3bf16_to_v3f16(<3 x bfloat> %a, i32 %b) {10; SI-LABEL: bitcast_v3bf16_to_v3f16:11; SI: ; %bb.0:12; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)13; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v314; SI-NEXT: v_mul_f32_e32 v3, 1.0, v015; SI-NEXT: v_mul_f32_e32 v4, 1.0, v116; SI-NEXT: v_mul_f32_e32 v5, 1.0, v217; SI-NEXT: ; implicit-def: $vgpr018; SI-NEXT: ; implicit-def: $vgpr119; SI-NEXT: ; implicit-def: $vgpr220; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc21; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]22; SI-NEXT: s_cbranch_execnz .LBB0_323; SI-NEXT: ; %bb.1: ; %Flow24; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]25; SI-NEXT: s_cbranch_execnz .LBB0_426; SI-NEXT: .LBB0_2: ; %end27; SI-NEXT: s_or_b64 exec, exec, s[4:5]28; SI-NEXT: s_setpc_b64 s[30:31]29; SI-NEXT: .LBB0_3: ; %cmp.false30; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v331; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v432; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v533; SI-NEXT: v_cvt_f32_f16_e32 v0, v034; SI-NEXT: v_cvt_f32_f16_e32 v1, v135; SI-NEXT: v_cvt_f32_f16_e32 v2, v236; SI-NEXT: ; implicit-def: $vgpr537; SI-NEXT: ; implicit-def: $vgpr438; SI-NEXT: ; implicit-def: $vgpr339; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]40; SI-NEXT: s_cbranch_execz .LBB0_241; SI-NEXT: .LBB0_4: ; %cmp.true42; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v543; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v044; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v045; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v446; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v047; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v048; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v349; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v050; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v051; SI-NEXT: v_cvt_f32_f16_e32 v0, v052; SI-NEXT: v_cvt_f32_f16_e32 v1, v153; SI-NEXT: v_cvt_f32_f16_e32 v2, v254; SI-NEXT: s_or_b64 exec, exec, s[4:5]55; SI-NEXT: s_setpc_b64 s[30:31]56;57; VI-LABEL: bitcast_v3bf16_to_v3f16:58; VI: ; %bb.0:59; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)60; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v261; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc62; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]63; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]64; VI-NEXT: s_cbranch_execz .LBB0_265; VI-NEXT: ; %bb.1: ; %cmp.true66; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v167; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v168; VI-NEXT: v_bfe_u32 v2, v1, 16, 169; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v170; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v271; VI-NEXT: v_or_b32_e32 v3, 0x400000, v172; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v173; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc74; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v075; VI-NEXT: v_add_f32_e32 v2, 0x40c00000, v276; VI-NEXT: v_bfe_u32 v3, v2, 16, 177; VI-NEXT: s_movk_i32 s6, 0x7fff78; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v279; VI-NEXT: v_add_u32_e32 v3, vcc, s6, v380; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v081; VI-NEXT: v_or_b32_e32 v4, 0x400000, v282; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v283; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v084; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc85; VI-NEXT: v_bfe_u32 v3, v0, 16, 186; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v087; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v388; VI-NEXT: v_or_b32_e32 v4, 0x400000, v089; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v090; VI-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc91; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v092; VI-NEXT: v_alignbit_b32 v0, v0, v2, 1693; VI-NEXT: v_mov_b32_e32 v2, 0x7fc0000094; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD95; VI-NEXT: .LBB0_2: ; %end96; VI-NEXT: s_or_b64 exec, exec, s[4:5]97; VI-NEXT: s_setpc_b64 s[30:31]98;99; GFX9-LABEL: bitcast_v3bf16_to_v3f16:100; GFX9: ; %bb.0:101; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)102; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2103; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc104; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]105; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]106; GFX9-NEXT: s_cbranch_execz .LBB0_2107; GFX9-NEXT: ; %bb.1: ; %cmp.true108; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1109; GFX9-NEXT: v_add_f32_e32 v1, 0x40c00000, v1110; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1111; GFX9-NEXT: s_movk_i32 s6, 0x7fff112; GFX9-NEXT: v_add3_u32 v2, v2, v1, s6113; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1114; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1115; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc116; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v0117; GFX9-NEXT: v_add_f32_e32 v2, 0x40c00000, v2118; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1119; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0120; GFX9-NEXT: v_add3_u32 v3, v3, v2, s6121; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2122; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2123; GFX9-NEXT: v_add_f32_e32 v0, 0x40c00000, v0124; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc125; GFX9-NEXT: v_bfe_u32 v3, v0, 16, 1126; GFX9-NEXT: v_add3_u32 v3, v3, v0, s6127; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v0128; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0129; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc130; GFX9-NEXT: s_mov_b32 s6, 0x7060302131; GFX9-NEXT: v_perm_b32 v0, v0, v2, s6132; GFX9-NEXT: s_movk_i32 s6, 0x7fc0133; GFX9-NEXT: v_alignbit_b32 v1, s6, v1, 16134; GFX9-NEXT: .LBB0_2: ; %end135; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]136; GFX9-NEXT: s_setpc_b64 s[30:31]137;138; GFX11-TRUE16-LABEL: bitcast_v3bf16_to_v3f16:139; GFX11-TRUE16: ; %bb.0:140; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)141; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2142; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_vgpr3143; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo144; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)145; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0146; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false147; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0148; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1149; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow150; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0151; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB0_4152; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true153; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, 0154; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l155; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)156; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v2157; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v0.l158; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2159; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)160; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v2, 16, 1161; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2162; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2163; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff164; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)165; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v3, v7 :: v_dual_and_b32 v0, 0xffff0000, v0166; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0167; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1168; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1169; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1170; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0x7fc0171; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v0, 16, 1172; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v1, 0x7fff173; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0174; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)175; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff176; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v5, vcc_lo177; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0178; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)179; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.h180; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v6, v8, vcc_lo181; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h182; GFX11-TRUE16-NEXT: .LBB0_4: ; %end183; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0184; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)185; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3186; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]187;188; GFX11-FAKE16-LABEL: bitcast_v3bf16_to_v3f16:189; GFX11-FAKE16: ; %bb.0:190; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)191; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo192; GFX11-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v2193; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0194; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)195; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0196; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB0_2197; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true198; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1199; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)200; GFX11-FAKE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v2, 16, v0201; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2202; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)203; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1204; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v1205; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v2, 16, 1206; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v2207; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2208; GFX11-FAKE16-NEXT: v_add3_u32 v4, v4, v1, 0x7fff209; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0210; GFX11-FAKE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff211; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)212; GFX11-FAKE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0213; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v3, v7, vcc_lo214; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)215; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v0, 16, 1216; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0217; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0218; GFX11-FAKE16-NEXT: v_add3_u32 v5, v5, v0, 0x7fff219; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)220; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v8, vcc_lo221; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1222; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v2, 0x7060302223; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc_lo224; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)225; GFX11-FAKE16-NEXT: v_alignbit_b32 v1, 0x7fc0, v1, 16226; GFX11-FAKE16-NEXT: .LBB0_2: ; %end227; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0228; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]229 %cmp = icmp eq i32 %b, 0230 br i1 %cmp, label %cmp.true, label %cmp.false231 232cmp.true:233 %a1 = fadd <3 x bfloat> %a, splat (bfloat 0xR40C0)234 %a2 = bitcast <3 x bfloat> %a1 to <3 x half>235 br label %end236 237cmp.false:238 %a3 = bitcast <3 x bfloat> %a to <3 x half>239 br label %end240 241end:242 %phi = phi <3 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]243 ret <3 x half> %phi244}245 246define inreg <3 x half> @bitcast_v3bf16_to_v3f16_scalar(<3 x bfloat> inreg %a, i32 inreg %b) {247; SI-LABEL: bitcast_v3bf16_to_v3f16_scalar:248; SI: ; %bb.0:249; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)250; SI-NEXT: s_cmp_lg_u32 s19, 0251; SI-NEXT: v_mul_f32_e64 v3, 1.0, s16252; SI-NEXT: v_mul_f32_e64 v4, 1.0, s17253; SI-NEXT: v_mul_f32_e64 v5, 1.0, s18254; SI-NEXT: s_cbranch_scc0 .LBB1_4255; SI-NEXT: ; %bb.1: ; %cmp.false256; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v3257; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v4258; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v5259; SI-NEXT: v_cvt_f32_f16_e32 v0, v0260; SI-NEXT: v_cvt_f32_f16_e32 v1, v1261; SI-NEXT: v_cvt_f32_f16_e32 v2, v2262; SI-NEXT: s_cbranch_execnz .LBB1_3263; SI-NEXT: .LBB1_2: ; %cmp.true264; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v5265; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0266; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v0267; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v4268; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0269; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v0270; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v3271; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0272; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0273; SI-NEXT: v_cvt_f32_f16_e32 v0, v0274; SI-NEXT: v_cvt_f32_f16_e32 v1, v1275; SI-NEXT: v_cvt_f32_f16_e32 v2, v2276; SI-NEXT: .LBB1_3: ; %end277; SI-NEXT: s_setpc_b64 s[30:31]278; SI-NEXT: .LBB1_4:279; SI-NEXT: ; implicit-def: $vgpr0280; SI-NEXT: ; implicit-def: $vgpr1281; SI-NEXT: ; implicit-def: $vgpr2282; SI-NEXT: s_branch .LBB1_2283;284; VI-LABEL: bitcast_v3bf16_to_v3f16_scalar:285; VI: ; %bb.0:286; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)287; VI-NEXT: s_cmp_lg_u32 s18, 0288; VI-NEXT: s_cbranch_scc0 .LBB1_3289; VI-NEXT: ; %bb.1: ; %cmp.false290; VI-NEXT: s_cbranch_execnz .LBB1_4291; VI-NEXT: .LBB1_2: ; %cmp.true292; VI-NEXT: s_lshl_b32 s4, s17, 16293; VI-NEXT: v_mov_b32_e32 v1, 0x40c00000294; VI-NEXT: v_add_f32_e32 v0, s4, v1295; VI-NEXT: v_bfe_u32 v2, v0, 16, 1296; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0297; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2298; VI-NEXT: s_lshl_b32 s4, s16, 16299; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0300; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0301; VI-NEXT: v_add_f32_e32 v0, s4, v1302; VI-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc303; VI-NEXT: v_bfe_u32 v3, v0, 16, 1304; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v0305; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3306; VI-NEXT: s_and_b32 s4, s16, 0xffff0000307; VI-NEXT: v_or_b32_e32 v4, 0x400000, v0308; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0309; VI-NEXT: v_add_f32_e32 v1, s4, v1310; VI-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc311; VI-NEXT: v_bfe_u32 v3, v1, 16, 1312; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1313; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3314; VI-NEXT: v_or_b32_e32 v4, 0x400000, v1315; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1316; VI-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc317; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1318; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]319; VI-NEXT: v_mov_b32_e32 v1, 0x7fc00000320; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD321; VI-NEXT: s_setpc_b64 s[30:31]322; VI-NEXT: .LBB1_3:323; VI-NEXT: s_branch .LBB1_2324; VI-NEXT: .LBB1_4:325; VI-NEXT: v_mov_b32_e32 v0, s16326; VI-NEXT: v_mov_b32_e32 v1, s17327; VI-NEXT: s_setpc_b64 s[30:31]328;329; GFX9-LABEL: bitcast_v3bf16_to_v3f16_scalar:330; GFX9: ; %bb.0:331; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)332; GFX9-NEXT: s_cmp_lg_u32 s18, 0333; GFX9-NEXT: s_cbranch_scc0 .LBB1_3334; GFX9-NEXT: ; %bb.1: ; %cmp.false335; GFX9-NEXT: s_cbranch_execnz .LBB1_4336; GFX9-NEXT: .LBB1_2: ; %cmp.true337; GFX9-NEXT: s_lshl_b32 s4, s17, 16338; GFX9-NEXT: v_mov_b32_e32 v0, 0x40c00000339; GFX9-NEXT: v_add_f32_e32 v1, s4, v0340; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1341; GFX9-NEXT: v_add_u32_e32 v2, v2, v1342; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2343; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1344; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1345; GFX9-NEXT: s_pack_lh_b32_b16 s4, 0, s16346; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc347; GFX9-NEXT: v_add_f32_e32 v2, s4, v0348; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1349; GFX9-NEXT: v_add_u32_e32 v3, v3, v2350; GFX9-NEXT: s_lshl_b32 s4, s16, 16351; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3352; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2353; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2354; GFX9-NEXT: v_add_f32_e32 v0, s4, v0355; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc356; GFX9-NEXT: v_bfe_u32 v3, v0, 16, 1357; GFX9-NEXT: v_add_u32_e32 v3, v3, v0358; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3359; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v0360; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0361; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc362; GFX9-NEXT: v_mov_b32_e32 v3, 0xffff363; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2364; GFX9-NEXT: v_and_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1365; GFX9-NEXT: s_movk_i32 s4, 0x7fc0366; GFX9-NEXT: v_and_b32_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1367; GFX9-NEXT: v_lshl_or_b32 v0, v2, 16, v0368; GFX9-NEXT: v_lshl_or_b32 v1, s4, 16, v1369; GFX9-NEXT: s_setpc_b64 s[30:31]370; GFX9-NEXT: .LBB1_3:371; GFX9-NEXT: s_branch .LBB1_2372; GFX9-NEXT: .LBB1_4:373; GFX9-NEXT: v_mov_b32_e32 v0, s16374; GFX9-NEXT: v_mov_b32_e32 v1, s17375; GFX9-NEXT: s_setpc_b64 s[30:31]376;377; GFX11-TRUE16-LABEL: bitcast_v3bf16_to_v3f16_scalar:378; GFX11-TRUE16: ; %bb.0:379; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)380; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s2, 0381; GFX11-TRUE16-NEXT: s_mov_b32 s2, 0382; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB1_3383; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow384; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s2385; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB1_4386; GFX11-TRUE16-NEXT: .LBB1_2: ; %cmp.true387; GFX11-TRUE16-NEXT: s_pack_lh_b32_b16 s2, 0, s0388; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 16389; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s2390; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s1391; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, 16392; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)393; GFX11-TRUE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s0394; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1395; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)396; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1397; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0398; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0399; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v2, 16, 1400; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v0401; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v1402; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v2403; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v1404; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)405; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3406; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v2407; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4408; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v7, vcc_lo409; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1410; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)411; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5412; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0413; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc_lo414; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2415; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, 0x7fc0416; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)417; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1418; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v5, v8, vcc_lo419; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l420; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)421; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2422; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l423; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]424; GFX11-TRUE16-NEXT: .LBB1_3:425; GFX11-TRUE16-NEXT: s_branch .LBB1_2426; GFX11-TRUE16-NEXT: .LBB1_4:427; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1428; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]429;430; GFX11-FAKE16-LABEL: bitcast_v3bf16_to_v3f16_scalar:431; GFX11-FAKE16: ; %bb.0:432; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)433; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s2, 0434; GFX11-FAKE16-NEXT: s_mov_b32 s2, 0435; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB1_3436; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow437; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s2438; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB1_4439; GFX11-FAKE16-NEXT: .LBB1_2: ; %cmp.true440; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s0, 16441; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s1, 16442; GFX11-FAKE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s2443; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s1444; GFX11-FAKE16-NEXT: s_pack_lh_b32_b16 s0, 0, s0445; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)446; GFX11-FAKE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s0447; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v0, 16, 1448; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)449; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1450; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v0451; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0452; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v2, 16, 1453; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v0454; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1455; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v2456; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v1457; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)458; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3459; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v5, v2460; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4461; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v7, vcc_lo462; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1463; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)464; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5465; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0466; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc_lo467; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2468; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)469; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0470; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1471; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)472; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v5, v8 :: v_dual_and_b32 v1, 0xffff, v1473; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2474; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)475; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, 0x7fc0, 16, v1476; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v2, 16, v0477; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]478; GFX11-FAKE16-NEXT: .LBB1_3:479; GFX11-FAKE16-NEXT: s_branch .LBB1_2480; GFX11-FAKE16-NEXT: .LBB1_4:481; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1482; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]483 %cmp = icmp eq i32 %b, 0484 br i1 %cmp, label %cmp.true, label %cmp.false485 486cmp.true:487 %a1 = fadd <3 x bfloat> %a, splat (bfloat 0xR40C0)488 %a2 = bitcast <3 x bfloat> %a1 to <3 x half>489 br label %end490 491cmp.false:492 %a3 = bitcast <3 x bfloat> %a to <3 x half>493 br label %end494 495end:496 %phi = phi <3 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]497 ret <3 x half> %phi498}499 500define <3 x bfloat> @bitcast_v3f16_to_v3bf16(<3 x half> %a, i32 %b) {501; SI-LABEL: bitcast_v3f16_to_v3bf16:502; SI: ; %bb.0:503; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)504; SI-NEXT: v_cvt_f16_f32_e32 v4, v0505; SI-NEXT: v_cvt_f16_f32_e32 v5, v1506; SI-NEXT: v_cvt_f16_f32_e32 v6, v2507; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3508; SI-NEXT: ; implicit-def: $vgpr0509; SI-NEXT: ; implicit-def: $vgpr1510; SI-NEXT: ; implicit-def: $vgpr2511; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc512; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]513; SI-NEXT: s_cbranch_execnz .LBB2_3514; SI-NEXT: ; %bb.1: ; %Flow515; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]516; SI-NEXT: s_cbranch_execnz .LBB2_4517; SI-NEXT: .LBB2_2: ; %end518; SI-NEXT: s_or_b64 exec, exec, s[4:5]519; SI-NEXT: s_setpc_b64 s[30:31]520; SI-NEXT: .LBB2_3: ; %cmp.false521; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v4522; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v5523; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v6524; SI-NEXT: ; implicit-def: $vgpr6525; SI-NEXT: ; implicit-def: $vgpr5526; SI-NEXT: ; implicit-def: $vgpr4527; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]528; SI-NEXT: s_cbranch_execz .LBB2_2529; SI-NEXT: .LBB2_4: ; %cmp.true530; SI-NEXT: v_cvt_f32_f16_e32 v0, v6531; SI-NEXT: v_cvt_f32_f16_e32 v1, v5532; SI-NEXT: v_cvt_f32_f16_e32 v2, v4533; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0534; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1535; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v2536; SI-NEXT: v_cvt_f16_f32_e32 v2, v2537; SI-NEXT: v_cvt_f16_f32_e32 v1, v1538; SI-NEXT: v_cvt_f16_f32_e32 v3, v0539; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v2540; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1541; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v3542; SI-NEXT: s_or_b64 exec, exec, s[4:5]543; SI-NEXT: s_setpc_b64 s[30:31]544;545; VI-LABEL: bitcast_v3f16_to_v3bf16:546; VI: ; %bb.0:547; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)548; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2549; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc550; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]551; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]552; VI-NEXT: ; %bb.1: ; %cmp.true553; VI-NEXT: v_mov_b32_e32 v3, 0x200554; VI-NEXT: v_add_f16_e32 v1, 0x200, v1555; VI-NEXT: v_add_f16_e32 v2, 0x200, v0556; VI-NEXT: v_add_f16_sdwa v0, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD557; VI-NEXT: v_or_b32_e32 v0, v2, v0558; VI-NEXT: v_or_b32_e32 v1, 0x7e000000, v1559; VI-NEXT: ; %bb.2: ; %end560; VI-NEXT: s_or_b64 exec, exec, s[4:5]561; VI-NEXT: s_setpc_b64 s[30:31]562;563; GFX9-LABEL: bitcast_v3f16_to_v3bf16:564; GFX9: ; %bb.0:565; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)566; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2567; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc568; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]569; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]570; GFX9-NEXT: ; %bb.1: ; %cmp.true571; GFX9-NEXT: s_movk_i32 s6, 0x200572; GFX9-NEXT: v_pk_add_f16 v1, v1, s6573; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]574; GFX9-NEXT: ; %bb.2: ; %end575; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]576; GFX9-NEXT: s_setpc_b64 s[30:31]577;578; GFX11-LABEL: bitcast_v3f16_to_v3bf16:579; GFX11: ; %bb.0:580; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)581; GFX11-NEXT: s_mov_b32 s0, exec_lo582; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v2583; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0584; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)585; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0586; GFX11-NEXT: ; %bb.1: ; %cmp.true587; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1588; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]589; GFX11-NEXT: ; %bb.2: ; %end590; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0591; GFX11-NEXT: s_setpc_b64 s[30:31]592 %cmp = icmp eq i32 %b, 0593 br i1 %cmp, label %cmp.true, label %cmp.false594 595cmp.true:596 %a1 = fadd <3 x half> %a, splat (half 0xH0200)597 %a2 = bitcast <3 x half> %a1 to <3 x bfloat>598 br label %end599 600cmp.false:601 %a3 = bitcast <3 x half> %a to <3 x bfloat>602 br label %end603 604end:605 %phi = phi <3 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ]606 ret <3 x bfloat> %phi607}608 609define inreg <3 x bfloat> @bitcast_v3f16_to_v3bf16_scalar(<3 x half> inreg %a, i32 inreg %b) {610; SI-LABEL: bitcast_v3f16_to_v3bf16_scalar:611; SI: ; %bb.0:612; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)613; SI-NEXT: v_cvt_f16_f32_e32 v3, s16614; SI-NEXT: v_cvt_f16_f32_e32 v4, s17615; SI-NEXT: v_cvt_f16_f32_e32 v5, s18616; SI-NEXT: s_cmp_lg_u32 s19, 0617; SI-NEXT: s_cbranch_scc0 .LBB3_4618; SI-NEXT: ; %bb.1: ; %cmp.false619; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v3620; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v4621; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v5622; SI-NEXT: s_cbranch_execnz .LBB3_3623; SI-NEXT: .LBB3_2: ; %cmp.true624; SI-NEXT: v_cvt_f32_f16_e32 v0, v5625; SI-NEXT: v_cvt_f32_f16_e32 v1, v4626; SI-NEXT: v_cvt_f32_f16_e32 v2, v3627; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0628; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1629; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v2630; SI-NEXT: v_cvt_f16_f32_e32 v2, v2631; SI-NEXT: v_cvt_f16_f32_e32 v1, v1632; SI-NEXT: v_cvt_f16_f32_e32 v3, v0633; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v2634; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1635; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v3636; SI-NEXT: .LBB3_3: ; %end637; SI-NEXT: s_setpc_b64 s[30:31]638; SI-NEXT: .LBB3_4:639; SI-NEXT: ; implicit-def: $vgpr0640; SI-NEXT: ; implicit-def: $vgpr1641; SI-NEXT: ; implicit-def: $vgpr2642; SI-NEXT: s_branch .LBB3_2643;644; VI-LABEL: bitcast_v3f16_to_v3bf16_scalar:645; VI: ; %bb.0:646; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)647; VI-NEXT: s_cmp_lg_u32 s18, 0648; VI-NEXT: s_cbranch_scc0 .LBB3_3649; VI-NEXT: ; %bb.1: ; %cmp.false650; VI-NEXT: s_cbranch_execnz .LBB3_4651; VI-NEXT: .LBB3_2: ; %cmp.true652; VI-NEXT: s_lshr_b32 s4, s16, 16653; VI-NEXT: v_mov_b32_e32 v0, 0x200654; VI-NEXT: v_mov_b32_e32 v3, s4655; VI-NEXT: v_add_f16_e32 v1, s17, v0656; VI-NEXT: v_add_f16_e32 v2, s16, v0657; VI-NEXT: v_add_f16_sdwa v0, v3, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD658; VI-NEXT: v_or_b32_e32 v0, v2, v0659; VI-NEXT: v_or_b32_e32 v1, 0x7e000000, v1660; VI-NEXT: s_setpc_b64 s[30:31]661; VI-NEXT: .LBB3_3:662; VI-NEXT: s_branch .LBB3_2663; VI-NEXT: .LBB3_4:664; VI-NEXT: v_mov_b32_e32 v0, s16665; VI-NEXT: v_mov_b32_e32 v1, s17666; VI-NEXT: s_setpc_b64 s[30:31]667;668; GFX9-LABEL: bitcast_v3f16_to_v3bf16_scalar:669; GFX9: ; %bb.0:670; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)671; GFX9-NEXT: s_cmp_lg_u32 s18, 0672; GFX9-NEXT: s_cbranch_scc0 .LBB3_3673; GFX9-NEXT: ; %bb.1: ; %cmp.false674; GFX9-NEXT: s_cbranch_execnz .LBB3_4675; GFX9-NEXT: .LBB3_2: ; %cmp.true676; GFX9-NEXT: v_mov_b32_e32 v0, 0x200677; GFX9-NEXT: v_pk_add_f16 v1, s17, v0678; GFX9-NEXT: v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]679; GFX9-NEXT: s_setpc_b64 s[30:31]680; GFX9-NEXT: .LBB3_3:681; GFX9-NEXT: s_branch .LBB3_2682; GFX9-NEXT: .LBB3_4:683; GFX9-NEXT: v_mov_b32_e32 v0, s16684; GFX9-NEXT: v_mov_b32_e32 v1, s17685; GFX9-NEXT: s_setpc_b64 s[30:31]686;687; GFX11-LABEL: bitcast_v3f16_to_v3bf16_scalar:688; GFX11: ; %bb.0:689; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)690; GFX11-NEXT: s_cmp_lg_u32 s2, 0691; GFX11-NEXT: s_mov_b32 s2, 0692; GFX11-NEXT: s_cbranch_scc0 .LBB3_3693; GFX11-NEXT: ; %bb.1: ; %Flow694; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s2695; GFX11-NEXT: s_cbranch_vccnz .LBB3_4696; GFX11-NEXT: .LBB3_2: ; %cmp.true697; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s1698; GFX11-NEXT: v_pk_add_f16 v0, 0x200, s0 op_sel_hi:[0,1]699; GFX11-NEXT: s_setpc_b64 s[30:31]700; GFX11-NEXT: .LBB3_3:701; GFX11-NEXT: s_branch .LBB3_2702; GFX11-NEXT: .LBB3_4:703; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1704; GFX11-NEXT: s_setpc_b64 s[30:31]705 %cmp = icmp eq i32 %b, 0706 br i1 %cmp, label %cmp.true, label %cmp.false707 708cmp.true:709 %a1 = fadd <3 x half> %a, splat (half 0xH0200)710 %a2 = bitcast <3 x half> %a1 to <3 x bfloat>711 br label %end712 713cmp.false:714 %a3 = bitcast <3 x half> %a to <3 x bfloat>715 br label %end716 717end:718 %phi = phi <3 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ]719 ret <3 x bfloat> %phi720}721 722define <3 x i16> @bitcast_v3bf16_to_v3i16(<3 x bfloat> %a, i32 %b) {723; SI-LABEL: bitcast_v3bf16_to_v3i16:724; SI: ; %bb.0:725; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)726; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3727; SI-NEXT: v_mul_f32_e32 v5, 1.0, v0728; SI-NEXT: v_mul_f32_e32 v4, 1.0, v1729; SI-NEXT: v_mul_f32_e32 v3, 1.0, v2730; SI-NEXT: ; implicit-def: $vgpr0731; SI-NEXT: ; implicit-def: $vgpr1732; SI-NEXT: ; implicit-def: $vgpr2733; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc734; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]735; SI-NEXT: s_cbranch_execnz .LBB4_3736; SI-NEXT: ; %bb.1: ; %Flow737; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]738; SI-NEXT: s_cbranch_execnz .LBB4_4739; SI-NEXT: .LBB4_2: ; %end740; SI-NEXT: s_or_b64 exec, exec, s[4:5]741; SI-NEXT: s_setpc_b64 s[30:31]742; SI-NEXT: .LBB4_3: ; %cmp.false743; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v5744; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v4745; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v3746; SI-NEXT: ; implicit-def: $vgpr5747; SI-NEXT: ; implicit-def: $vgpr4748; SI-NEXT: ; implicit-def: $vgpr3749; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]750; SI-NEXT: s_cbranch_execz .LBB4_2751; SI-NEXT: .LBB4_4: ; %cmp.true752; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v4753; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v5754; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1755; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0756; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1757; SI-NEXT: v_alignbit_b32 v0, v2, v0, 16758; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v3759; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2760; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1761; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2762; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16763; SI-NEXT: s_or_b64 exec, exec, s[4:5]764; SI-NEXT: s_setpc_b64 s[30:31]765;766; VI-LABEL: bitcast_v3bf16_to_v3i16:767; VI: ; %bb.0:768; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)769; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2770; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc771; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]772; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]773; VI-NEXT: s_cbranch_execz .LBB4_2774; VI-NEXT: ; %bb.1: ; %cmp.true775; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1776; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1777; VI-NEXT: v_bfe_u32 v2, v1, 16, 1778; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1779; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2780; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1781; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1782; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc783; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v0784; VI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2785; VI-NEXT: v_bfe_u32 v3, v2, 16, 1786; VI-NEXT: s_movk_i32 s6, 0x7fff787; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2788; VI-NEXT: v_add_u32_e32 v3, vcc, s6, v3789; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0790; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2791; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2792; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0793; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc794; VI-NEXT: v_bfe_u32 v3, v0, 16, 1795; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v0796; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3797; VI-NEXT: v_or_b32_e32 v4, 0x400000, v0798; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0799; VI-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc800; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0801; VI-NEXT: v_alignbit_b32 v0, v0, v2, 16802; VI-NEXT: v_mov_b32_e32 v2, 0x7fc00000803; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD804; VI-NEXT: .LBB4_2: ; %end805; VI-NEXT: s_or_b64 exec, exec, s[4:5]806; VI-NEXT: s_setpc_b64 s[30:31]807;808; GFX9-LABEL: bitcast_v3bf16_to_v3i16:809; GFX9: ; %bb.0:810; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)811; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2812; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc813; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]814; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]815; GFX9-NEXT: s_cbranch_execz .LBB4_2816; GFX9-NEXT: ; %bb.1: ; %cmp.true817; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1818; GFX9-NEXT: v_add_f32_e32 v1, 0x40c00000, v1819; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1820; GFX9-NEXT: s_movk_i32 s6, 0x7fff821; GFX9-NEXT: v_add3_u32 v2, v2, v1, s6822; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1823; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1824; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc825; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v0826; GFX9-NEXT: v_add_f32_e32 v2, 0x40c00000, v2827; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1828; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0829; GFX9-NEXT: v_add3_u32 v3, v3, v2, s6830; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2831; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2832; GFX9-NEXT: v_add_f32_e32 v0, 0x40c00000, v0833; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc834; GFX9-NEXT: v_bfe_u32 v3, v0, 16, 1835; GFX9-NEXT: v_add3_u32 v3, v3, v0, s6836; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v0837; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0838; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc839; GFX9-NEXT: s_mov_b32 s6, 0x7060302840; GFX9-NEXT: v_perm_b32 v0, v0, v2, s6841; GFX9-NEXT: s_movk_i32 s6, 0x7fc0842; GFX9-NEXT: v_alignbit_b32 v1, s6, v1, 16843; GFX9-NEXT: .LBB4_2: ; %end844; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]845; GFX9-NEXT: s_setpc_b64 s[30:31]846;847; GFX11-TRUE16-LABEL: bitcast_v3bf16_to_v3i16:848; GFX11-TRUE16: ; %bb.0:849; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)850; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo851; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v2852; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0853; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)854; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0855; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB4_2856; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true857; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, 0858; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l859; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)860; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v2861; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v0.l862; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0863; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0864; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)865; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1866; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1867; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1868; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v0, 16, 1869; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)870; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff871; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2872; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0873; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff874; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)875; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc_lo876; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v2, 16, 1877; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v2878; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2879; GFX11-TRUE16-NEXT: v_mov_b32_e32 v3, 0x7fc0880; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v1.h881; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v2, 0x7fff882; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)883; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l884; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v5, v8, vcc_lo885; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0886; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v7, vcc_lo887; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)888; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.h889; GFX11-TRUE16-NEXT: .LBB4_2: ; %end890; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0891; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]892;893; GFX11-FAKE16-LABEL: bitcast_v3bf16_to_v3i16:894; GFX11-FAKE16: ; %bb.0:895; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)896; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo897; GFX11-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v2898; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0899; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)900; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0901; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB4_2902; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true903; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1904; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)905; GFX11-FAKE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v2, 16, v0906; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2907; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)908; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1909; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v1910; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v2, 16, 1911; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v2912; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2913; GFX11-FAKE16-NEXT: v_add3_u32 v4, v4, v1, 0x7fff914; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0915; GFX11-FAKE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff916; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)917; GFX11-FAKE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0918; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v3, v7, vcc_lo919; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)920; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v0, 16, 1921; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0922; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0923; GFX11-FAKE16-NEXT: v_add3_u32 v5, v5, v0, 0x7fff924; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)925; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v8, vcc_lo926; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1927; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v2, 0x7060302928; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc_lo929; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)930; GFX11-FAKE16-NEXT: v_alignbit_b32 v1, 0x7fc0, v1, 16931; GFX11-FAKE16-NEXT: .LBB4_2: ; %end932; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0933; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]934 %cmp = icmp eq i32 %b, 0935 br i1 %cmp, label %cmp.true, label %cmp.false936 937cmp.true:938 %a1 = fadd <3 x bfloat> %a, splat (bfloat 0xR40C0)939 %a2 = bitcast <3 x bfloat> %a1 to <3 x i16>940 br label %end941 942cmp.false:943 %a3 = bitcast <3 x bfloat> %a to <3 x i16>944 br label %end945 946end:947 %phi = phi <3 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]948 ret <3 x i16> %phi949}950 951define inreg <3 x i16> @bitcast_v3bf16_to_v3i16_scalar(<3 x bfloat> inreg %a, i32 inreg %b) {952; SI-LABEL: bitcast_v3bf16_to_v3i16_scalar:953; SI: ; %bb.0:954; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)955; SI-NEXT: s_cmp_lg_u32 s19, 0956; SI-NEXT: v_mul_f32_e64 v5, 1.0, s16957; SI-NEXT: v_mul_f32_e64 v1, 1.0, s17958; SI-NEXT: v_mul_f32_e64 v4, 1.0, s18959; SI-NEXT: s_cbranch_scc0 .LBB5_4960; SI-NEXT: ; %bb.1: ; %cmp.false961; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v5962; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v1963; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v4964; SI-NEXT: s_cbranch_execnz .LBB5_3965; SI-NEXT: .LBB5_2: ; %cmp.true966; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1967; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v5968; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v1969; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0970; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v2971; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16972; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v2973; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v4974; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2975; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2976; SI-NEXT: v_lshr_b64 v[3:4], v[1:2], 16977; SI-NEXT: .LBB5_3: ; %end978; SI-NEXT: v_mov_b32_e32 v1, v3979; SI-NEXT: s_setpc_b64 s[30:31]980; SI-NEXT: .LBB5_4:981; SI-NEXT: ; implicit-def: $vgpr0982; SI-NEXT: ; implicit-def: $vgpr3983; SI-NEXT: ; implicit-def: $vgpr2984; SI-NEXT: s_branch .LBB5_2985;986; VI-LABEL: bitcast_v3bf16_to_v3i16_scalar:987; VI: ; %bb.0:988; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)989; VI-NEXT: s_cmp_lg_u32 s18, 0990; VI-NEXT: s_cbranch_scc0 .LBB5_3991; VI-NEXT: ; %bb.1: ; %cmp.false992; VI-NEXT: s_cbranch_execnz .LBB5_4993; VI-NEXT: .LBB5_2: ; %cmp.true994; VI-NEXT: s_lshl_b32 s4, s17, 16995; VI-NEXT: v_mov_b32_e32 v1, 0x40c00000996; VI-NEXT: v_add_f32_e32 v0, s4, v1997; VI-NEXT: v_bfe_u32 v2, v0, 16, 1998; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0999; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v21000; VI-NEXT: s_lshl_b32 s4, s16, 161001; VI-NEXT: v_or_b32_e32 v3, 0x400000, v01002; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v01003; VI-NEXT: v_add_f32_e32 v0, s4, v11004; VI-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc1005; VI-NEXT: v_bfe_u32 v3, v0, 16, 11006; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v01007; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v31008; VI-NEXT: s_and_b32 s4, s16, 0xffff00001009; VI-NEXT: v_or_b32_e32 v4, 0x400000, v01010; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v01011; VI-NEXT: v_add_f32_e32 v1, s4, v11012; VI-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc1013; VI-NEXT: v_bfe_u32 v3, v1, 16, 11014; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v11015; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v31016; VI-NEXT: v_or_b32_e32 v4, 0x400000, v11017; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v11018; VI-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc1019; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v11020; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]1021; VI-NEXT: v_mov_b32_e32 v1, 0x7fc000001022; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1023; VI-NEXT: s_setpc_b64 s[30:31]1024; VI-NEXT: .LBB5_3:1025; VI-NEXT: s_branch .LBB5_21026; VI-NEXT: .LBB5_4:1027; VI-NEXT: v_mov_b32_e32 v0, s161028; VI-NEXT: v_mov_b32_e32 v1, s171029; VI-NEXT: s_setpc_b64 s[30:31]1030;1031; GFX9-LABEL: bitcast_v3bf16_to_v3i16_scalar:1032; GFX9: ; %bb.0:1033; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1034; GFX9-NEXT: s_cmp_lg_u32 s18, 01035; GFX9-NEXT: s_cbranch_scc0 .LBB5_31036; GFX9-NEXT: ; %bb.1: ; %cmp.false1037; GFX9-NEXT: s_cbranch_execnz .LBB5_41038; GFX9-NEXT: .LBB5_2: ; %cmp.true1039; GFX9-NEXT: s_lshl_b32 s4, s17, 161040; GFX9-NEXT: v_mov_b32_e32 v0, 0x40c000001041; GFX9-NEXT: v_add_f32_e32 v1, s4, v01042; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 11043; GFX9-NEXT: v_add_u32_e32 v2, v2, v11044; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v21045; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v11046; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v11047; GFX9-NEXT: s_pack_lh_b32_b16 s4, 0, s161048; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc1049; GFX9-NEXT: v_add_f32_e32 v2, s4, v01050; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 11051; GFX9-NEXT: v_add_u32_e32 v3, v3, v21052; GFX9-NEXT: s_lshl_b32 s4, s16, 161053; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v31054; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v21055; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v21056; GFX9-NEXT: v_add_f32_e32 v0, s4, v01057; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc1058; GFX9-NEXT: v_bfe_u32 v3, v0, 16, 11059; GFX9-NEXT: v_add_u32_e32 v3, v3, v01060; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v31061; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v01062; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v01063; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc1064; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v01065; GFX9-NEXT: v_mov_b32_e32 v3, 0xffff00001066; GFX9-NEXT: v_and_or_b32 v0, v2, v3, v01067; GFX9-NEXT: v_mov_b32_e32 v2, 0xffff1068; GFX9-NEXT: s_movk_i32 s4, 0x7fc01069; GFX9-NEXT: v_and_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_11070; GFX9-NEXT: v_lshl_or_b32 v1, s4, 16, v11071; GFX9-NEXT: s_setpc_b64 s[30:31]1072; GFX9-NEXT: .LBB5_3:1073; GFX9-NEXT: s_branch .LBB5_21074; GFX9-NEXT: .LBB5_4:1075; GFX9-NEXT: v_mov_b32_e32 v0, s161076; GFX9-NEXT: v_mov_b32_e32 v1, s171077; GFX9-NEXT: s_setpc_b64 s[30:31]1078;1079; GFX11-TRUE16-LABEL: bitcast_v3bf16_to_v3i16_scalar:1080; GFX11-TRUE16: ; %bb.0:1081; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1082; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s2, 01083; GFX11-TRUE16-NEXT: s_mov_b32 s2, 01084; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB5_31085; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow1086; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s21087; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB5_41088; GFX11-TRUE16-NEXT: .LBB5_2: ; %cmp.true1089; GFX11-TRUE16-NEXT: s_lshl_b32 s2, s0, 161090; GFX11-TRUE16-NEXT: s_pack_lh_b32_b16 s0, 0, s01091; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s21092; GFX11-TRUE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s01093; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 161094; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)1095; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s11096; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 11097; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)1098; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v2, 16, 11099; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v01100; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v21101; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 11102; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v01103; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v21104; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v01105; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v11106; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)1107; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v51108; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v31109; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v3, v7 :: v_dual_add_nc_u32 v4, v4, v11110; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)1111; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v41112; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v11113; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc_lo1114; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v21115; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, 0x7fc01116; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)1117; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v1.h1118; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v5, v8, vcc_lo1119; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.h1120; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l1121; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]1122; GFX11-TRUE16-NEXT: .LBB5_3:1123; GFX11-TRUE16-NEXT: s_branch .LBB5_21124; GFX11-TRUE16-NEXT: .LBB5_4:1125; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s11126; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]1127;1128; GFX11-FAKE16-LABEL: bitcast_v3bf16_to_v3i16_scalar:1129; GFX11-FAKE16: ; %bb.0:1130; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1131; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s2, 01132; GFX11-FAKE16-NEXT: s_mov_b32 s2, 01133; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB5_31134; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow1135; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s21136; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB5_41137; GFX11-FAKE16-NEXT: .LBB5_2: ; %cmp.true1138; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s0, 161139; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s1, 161140; GFX11-FAKE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s21141; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s11142; GFX11-FAKE16-NEXT: s_pack_lh_b32_b16 s0, 0, s01143; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)1144; GFX11-FAKE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s01145; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v0, 16, 11146; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)1147; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 11148; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v01149; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v01150; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v2, 16, 11151; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v01152; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v11153; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v21154; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v11155; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)1156; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v31157; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v5, v21158; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v41159; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v7, vcc_lo1160; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v11161; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)1162; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v51163; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v01164; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc_lo1165; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v21166; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)1167; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v11168; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v5, v8, vcc_lo1169; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, 0x7fc0, 16, v11170; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)1171; GFX11-FAKE16-NEXT: v_and_or_b32 v0, 0xffff0000, v2, v01172; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]1173; GFX11-FAKE16-NEXT: .LBB5_3:1174; GFX11-FAKE16-NEXT: s_branch .LBB5_21175; GFX11-FAKE16-NEXT: .LBB5_4:1176; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s11177; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]1178 %cmp = icmp eq i32 %b, 01179 br i1 %cmp, label %cmp.true, label %cmp.false1180 1181cmp.true:1182 %a1 = fadd <3 x bfloat> %a, splat (bfloat 0xR40C0)1183 %a2 = bitcast <3 x bfloat> %a1 to <3 x i16>1184 br label %end1185 1186cmp.false:1187 %a3 = bitcast <3 x bfloat> %a to <3 x i16>1188 br label %end1189 1190end:1191 %phi = phi <3 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]1192 ret <3 x i16> %phi1193}1194 1195define <3 x bfloat> @bitcast_v3i16_to_v3bf16(<3 x i16> %a, i32 %b) {1196; SI-LABEL: bitcast_v3i16_to_v3bf16:1197; SI: ; %bb.0:1198; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1199; SI-NEXT: v_mov_b32_e32 v4, v01200; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31201; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v11202; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v21203; SI-NEXT: ; implicit-def: $vgpr01204; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc1205; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]1206; SI-NEXT: s_cbranch_execnz .LBB6_31207; SI-NEXT: ; %bb.1: ; %Flow1208; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1209; SI-NEXT: s_cbranch_execnz .LBB6_41210; SI-NEXT: .LBB6_2: ; %end1211; SI-NEXT: s_or_b64 exec, exec, s[4:5]1212; SI-NEXT: s_setpc_b64 s[30:31]1213; SI-NEXT: .LBB6_3: ; %cmp.false1214; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v41215; SI-NEXT: ; implicit-def: $vgpr41216; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1217; SI-NEXT: s_cbranch_execz .LBB6_21218; SI-NEXT: .LBB6_4: ; %cmp.true1219; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v41220; SI-NEXT: v_and_b32_e32 v0, 0xffff, v01221; SI-NEXT: v_or_b32_e32 v0, v1, v01222; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v01223; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v01224; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v01225; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v21226; SI-NEXT: s_or_b64 exec, exec, s[4:5]1227; SI-NEXT: s_setpc_b64 s[30:31]1228;1229; VI-LABEL: bitcast_v3i16_to_v3bf16:1230; VI: ; %bb.0:1231; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1232; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v21233; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc1234; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]1235; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1236; VI-NEXT: ; %bb.1: ; %cmp.true1237; VI-NEXT: v_mov_b32_e32 v2, 31238; VI-NEXT: v_add_u16_sdwa v2, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1239; VI-NEXT: v_add_u16_e32 v0, 3, v01240; VI-NEXT: v_add_u16_e32 v1, 3, v11241; VI-NEXT: v_or_b32_e32 v0, v0, v21242; VI-NEXT: ; %bb.2: ; %end1243; VI-NEXT: s_or_b64 exec, exec, s[4:5]1244; VI-NEXT: s_setpc_b64 s[30:31]1245;1246; GFX9-LABEL: bitcast_v3i16_to_v3bf16:1247; GFX9: ; %bb.0:1248; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1249; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v21250; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc1251; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]1252; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1253; GFX9-NEXT: ; %bb.1: ; %cmp.true1254; GFX9-NEXT: v_pk_add_u16 v1, v1, 31255; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]1256; GFX9-NEXT: ; %bb.2: ; %end1257; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]1258; GFX9-NEXT: s_setpc_b64 s[30:31]1259;1260; GFX11-LABEL: bitcast_v3i16_to_v3bf16:1261; GFX11: ; %bb.0:1262; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1263; GFX11-NEXT: s_mov_b32 s0, exec_lo1264; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v21265; GFX11-NEXT: s_xor_b32 s0, exec_lo, s01266; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)1267; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s01268; GFX11-NEXT: ; %bb.1: ; %cmp.true1269; GFX11-NEXT: v_pk_add_u16 v1, v1, 31270; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]1271; GFX11-NEXT: ; %bb.2: ; %end1272; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s01273; GFX11-NEXT: s_setpc_b64 s[30:31]1274 %cmp = icmp eq i32 %b, 01275 br i1 %cmp, label %cmp.true, label %cmp.false1276 1277cmp.true:1278 %a1 = add <3 x i16> %a, splat (i16 3)1279 %a2 = bitcast <3 x i16> %a1 to <3 x bfloat>1280 br label %end1281 1282cmp.false:1283 %a3 = bitcast <3 x i16> %a to <3 x bfloat>1284 br label %end1285 1286end:1287 %phi = phi <3 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ]1288 ret <3 x bfloat> %phi1289}1290 1291define inreg <3 x bfloat> @bitcast_v3i16_to_v3bf16_scalar(<3 x i16> inreg %a, i32 inreg %b) {1292; SI-LABEL: bitcast_v3i16_to_v3bf16_scalar:1293; SI: ; %bb.0:1294; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1295; SI-NEXT: s_cmp_lg_u32 s19, 01296; SI-NEXT: s_cbranch_scc0 .LBB7_41297; SI-NEXT: ; %bb.1: ; %cmp.false1298; SI-NEXT: s_lshl_b32 s6, s16, 161299; SI-NEXT: s_lshl_b32 s7, s17, 161300; SI-NEXT: s_lshl_b32 s8, s18, 161301; SI-NEXT: s_cbranch_execnz .LBB7_31302; SI-NEXT: .LBB7_2: ; %cmp.true1303; SI-NEXT: s_add_i32 s16, s16, 31304; SI-NEXT: s_and_b32 s4, s16, 0xffff1305; SI-NEXT: s_lshl_b32 s5, s17, 161306; SI-NEXT: s_or_b32 s4, s5, s41307; SI-NEXT: s_add_i32 s4, s4, 0x300001308; SI-NEXT: s_lshl_b32 s5, s18, 161309; SI-NEXT: s_and_b32 s7, s4, 0xffff00001310; SI-NEXT: s_lshl_b32 s6, s4, 161311; SI-NEXT: s_add_i32 s8, s5, 0x300001312; SI-NEXT: .LBB7_3: ; %end1313; SI-NEXT: v_mov_b32_e32 v0, s61314; SI-NEXT: v_mov_b32_e32 v1, s71315; SI-NEXT: v_mov_b32_e32 v2, s81316; SI-NEXT: s_setpc_b64 s[30:31]1317; SI-NEXT: .LBB7_4:1318; SI-NEXT: ; implicit-def: $sgpr61319; SI-NEXT: ; implicit-def: $sgpr71320; SI-NEXT: ; implicit-def: $sgpr81321; SI-NEXT: s_branch .LBB7_21322;1323; VI-LABEL: bitcast_v3i16_to_v3bf16_scalar:1324; VI: ; %bb.0:1325; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1326; VI-NEXT: s_cmp_lg_u32 s18, 01327; VI-NEXT: s_cbranch_scc0 .LBB7_41328; VI-NEXT: ; %bb.1: ; %cmp.false1329; VI-NEXT: s_cbranch_execnz .LBB7_31330; VI-NEXT: .LBB7_2: ; %cmp.true1331; VI-NEXT: s_add_i32 s5, s16, 31332; VI-NEXT: s_and_b32 s4, s16, 0xffff00001333; VI-NEXT: s_and_b32 s5, s5, 0xffff1334; VI-NEXT: s_or_b32 s4, s4, s51335; VI-NEXT: s_add_i32 s17, s17, 31336; VI-NEXT: s_add_i32 s16, s4, 0x300001337; VI-NEXT: .LBB7_3: ; %end1338; VI-NEXT: v_mov_b32_e32 v0, s161339; VI-NEXT: v_mov_b32_e32 v1, s171340; VI-NEXT: s_setpc_b64 s[30:31]1341; VI-NEXT: .LBB7_4:1342; VI-NEXT: s_branch .LBB7_21343;1344; GFX9-LABEL: bitcast_v3i16_to_v3bf16_scalar:1345; GFX9: ; %bb.0:1346; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1347; GFX9-NEXT: s_cmp_lg_u32 s18, 01348; GFX9-NEXT: s_cbranch_scc0 .LBB7_31349; GFX9-NEXT: ; %bb.1: ; %cmp.false1350; GFX9-NEXT: s_cbranch_execnz .LBB7_41351; GFX9-NEXT: .LBB7_2: ; %cmp.true1352; GFX9-NEXT: v_pk_add_u16 v1, s17, 31353; GFX9-NEXT: v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]1354; GFX9-NEXT: s_setpc_b64 s[30:31]1355; GFX9-NEXT: .LBB7_3:1356; GFX9-NEXT: s_branch .LBB7_21357; GFX9-NEXT: .LBB7_4:1358; GFX9-NEXT: v_mov_b32_e32 v0, s161359; GFX9-NEXT: v_mov_b32_e32 v1, s171360; GFX9-NEXT: s_setpc_b64 s[30:31]1361;1362; GFX11-LABEL: bitcast_v3i16_to_v3bf16_scalar:1363; GFX11: ; %bb.0:1364; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1365; GFX11-NEXT: s_cmp_lg_u32 s2, 01366; GFX11-NEXT: s_mov_b32 s2, 01367; GFX11-NEXT: s_cbranch_scc0 .LBB7_31368; GFX11-NEXT: ; %bb.1: ; %Flow1369; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s21370; GFX11-NEXT: s_cbranch_vccnz .LBB7_41371; GFX11-NEXT: .LBB7_2: ; %cmp.true1372; GFX11-NEXT: v_pk_add_u16 v1, s1, 31373; GFX11-NEXT: v_pk_add_u16 v0, s0, 3 op_sel_hi:[1,0]1374; GFX11-NEXT: s_setpc_b64 s[30:31]1375; GFX11-NEXT: .LBB7_3:1376; GFX11-NEXT: s_branch .LBB7_21377; GFX11-NEXT: .LBB7_4:1378; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s11379; GFX11-NEXT: s_setpc_b64 s[30:31]1380 %cmp = icmp eq i32 %b, 01381 br i1 %cmp, label %cmp.true, label %cmp.false1382 1383cmp.true:1384 %a1 = add <3 x i16> %a, splat (i16 3)1385 %a2 = bitcast <3 x i16> %a1 to <3 x bfloat>1386 br label %end1387 1388cmp.false:1389 %a3 = bitcast <3 x i16> %a to <3 x bfloat>1390 br label %end1391 1392end:1393 %phi = phi <3 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ]1394 ret <3 x bfloat> %phi1395}1396 1397define <3 x i16> @bitcast_v3f16_to_v3i16(<3 x half> %a, i32 %b) {1398; SI-LABEL: bitcast_v3f16_to_v3i16:1399; SI: ; %bb.0:1400; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1401; SI-NEXT: v_cvt_f16_f32_e32 v0, v01402; SI-NEXT: v_cvt_f16_f32_e32 v1, v11403; SI-NEXT: v_cvt_f16_f32_e32 v2, v21404; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31405; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc1406; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]1407; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1408; SI-NEXT: s_cbranch_execz .LBB8_21409; SI-NEXT: ; %bb.1: ; %cmp.true1410; SI-NEXT: v_cvt_f32_f16_e32 v1, v11411; SI-NEXT: v_cvt_f32_f16_e32 v0, v01412; SI-NEXT: v_cvt_f32_f16_e32 v2, v21413; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v11414; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v01415; SI-NEXT: v_cvt_f16_f32_e32 v1, v11416; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v21417; SI-NEXT: v_cvt_f16_f32_e32 v0, v01418; SI-NEXT: v_cvt_f16_f32_e32 v2, v21419; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v11420; SI-NEXT: v_or_b32_e32 v0, v0, v11421; SI-NEXT: v_alignbit_b32 v1, v2, v1, 161422; SI-NEXT: .LBB8_2: ; %end1423; SI-NEXT: s_or_b64 exec, exec, s[4:5]1424; SI-NEXT: s_setpc_b64 s[30:31]1425;1426; VI-LABEL: bitcast_v3f16_to_v3i16:1427; VI: ; %bb.0:1428; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1429; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v21430; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc1431; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]1432; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1433; VI-NEXT: ; %bb.1: ; %cmp.true1434; VI-NEXT: v_mov_b32_e32 v3, 0x2001435; VI-NEXT: v_add_f16_e32 v1, 0x200, v11436; VI-NEXT: v_add_f16_e32 v2, 0x200, v01437; VI-NEXT: v_add_f16_sdwa v0, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1438; VI-NEXT: v_or_b32_e32 v0, v2, v01439; VI-NEXT: v_or_b32_e32 v1, 0x7e000000, v11440; VI-NEXT: ; %bb.2: ; %end1441; VI-NEXT: s_or_b64 exec, exec, s[4:5]1442; VI-NEXT: s_setpc_b64 s[30:31]1443;1444; GFX9-LABEL: bitcast_v3f16_to_v3i16:1445; GFX9: ; %bb.0:1446; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1447; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v21448; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc1449; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]1450; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1451; GFX9-NEXT: ; %bb.1: ; %cmp.true1452; GFX9-NEXT: s_movk_i32 s6, 0x2001453; GFX9-NEXT: v_pk_add_f16 v1, v1, s61454; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]1455; GFX9-NEXT: ; %bb.2: ; %end1456; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]1457; GFX9-NEXT: s_setpc_b64 s[30:31]1458;1459; GFX11-LABEL: bitcast_v3f16_to_v3i16:1460; GFX11: ; %bb.0:1461; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1462; GFX11-NEXT: s_mov_b32 s0, exec_lo1463; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v21464; GFX11-NEXT: s_xor_b32 s0, exec_lo, s01465; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)1466; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s01467; GFX11-NEXT: ; %bb.1: ; %cmp.true1468; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v11469; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]1470; GFX11-NEXT: ; %bb.2: ; %end1471; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s01472; GFX11-NEXT: s_setpc_b64 s[30:31]1473 %cmp = icmp eq i32 %b, 01474 br i1 %cmp, label %cmp.true, label %cmp.false1475 1476cmp.true:1477 %a1 = fadd <3 x half> %a, splat (half 0xH0200)1478 %a2 = bitcast <3 x half> %a1 to <3 x i16>1479 br label %end1480 1481cmp.false:1482 %a3 = bitcast <3 x half> %a to <3 x i16>1483 br label %end1484 1485end:1486 %phi = phi <3 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]1487 ret <3 x i16> %phi1488}1489 1490define inreg <3 x i16> @bitcast_v3f16_to_v3i16_scalar(<3 x half> inreg %a, i32 inreg %b) {1491; SI-LABEL: bitcast_v3f16_to_v3i16_scalar:1492; SI: ; %bb.0:1493; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1494; SI-NEXT: v_cvt_f16_f32_e32 v0, s161495; SI-NEXT: v_cvt_f16_f32_e32 v3, s171496; SI-NEXT: v_cvt_f16_f32_e32 v2, s181497; SI-NEXT: s_cmp_lg_u32 s19, 01498; SI-NEXT: s_cbranch_scc0 .LBB9_41499; SI-NEXT: ; %bb.1: ; %cmp.false1500; SI-NEXT: s_cbranch_execnz .LBB9_31501; SI-NEXT: .LBB9_2: ; %cmp.true1502; SI-NEXT: v_cvt_f32_f16_e32 v1, v31503; SI-NEXT: v_cvt_f32_f16_e32 v2, v21504; SI-NEXT: v_cvt_f32_f16_e32 v0, v01505; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v11506; SI-NEXT: v_cvt_f16_f32_e32 v1, v11507; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v21508; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v01509; SI-NEXT: v_cvt_f16_f32_e32 v2, v21510; SI-NEXT: v_cvt_f16_f32_e32 v0, v01511; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v11512; SI-NEXT: v_lshr_b64 v[3:4], v[1:2], 161513; SI-NEXT: v_or_b32_e32 v0, v0, v11514; SI-NEXT: .LBB9_3: ; %end1515; SI-NEXT: v_mov_b32_e32 v1, v31516; SI-NEXT: s_setpc_b64 s[30:31]1517; SI-NEXT: .LBB9_4:1518; SI-NEXT: s_branch .LBB9_21519;1520; VI-LABEL: bitcast_v3f16_to_v3i16_scalar:1521; VI: ; %bb.0:1522; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1523; VI-NEXT: s_cmp_lg_u32 s18, 01524; VI-NEXT: s_cbranch_scc0 .LBB9_31525; VI-NEXT: ; %bb.1: ; %cmp.false1526; VI-NEXT: s_cbranch_execnz .LBB9_41527; VI-NEXT: .LBB9_2: ; %cmp.true1528; VI-NEXT: s_lshr_b32 s4, s16, 161529; VI-NEXT: v_mov_b32_e32 v0, 0x2001530; VI-NEXT: v_mov_b32_e32 v3, s41531; VI-NEXT: v_add_f16_e32 v1, s17, v01532; VI-NEXT: v_add_f16_e32 v2, s16, v01533; VI-NEXT: v_add_f16_sdwa v0, v3, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD1534; VI-NEXT: v_or_b32_e32 v0, v2, v01535; VI-NEXT: v_or_b32_e32 v1, 0x7e000000, v11536; VI-NEXT: s_setpc_b64 s[30:31]1537; VI-NEXT: .LBB9_3:1538; VI-NEXT: s_branch .LBB9_21539; VI-NEXT: .LBB9_4:1540; VI-NEXT: v_mov_b32_e32 v0, s161541; VI-NEXT: v_mov_b32_e32 v1, s171542; VI-NEXT: s_setpc_b64 s[30:31]1543;1544; GFX9-LABEL: bitcast_v3f16_to_v3i16_scalar:1545; GFX9: ; %bb.0:1546; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1547; GFX9-NEXT: s_cmp_lg_u32 s18, 01548; GFX9-NEXT: s_cbranch_scc0 .LBB9_31549; GFX9-NEXT: ; %bb.1: ; %cmp.false1550; GFX9-NEXT: s_cbranch_execnz .LBB9_41551; GFX9-NEXT: .LBB9_2: ; %cmp.true1552; GFX9-NEXT: v_mov_b32_e32 v0, 0x2001553; GFX9-NEXT: v_pk_add_f16 v1, s17, v01554; GFX9-NEXT: v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]1555; GFX9-NEXT: s_setpc_b64 s[30:31]1556; GFX9-NEXT: .LBB9_3:1557; GFX9-NEXT: s_branch .LBB9_21558; GFX9-NEXT: .LBB9_4:1559; GFX9-NEXT: v_mov_b32_e32 v0, s161560; GFX9-NEXT: v_mov_b32_e32 v1, s171561; GFX9-NEXT: s_setpc_b64 s[30:31]1562;1563; GFX11-LABEL: bitcast_v3f16_to_v3i16_scalar:1564; GFX11: ; %bb.0:1565; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1566; GFX11-NEXT: s_cmp_lg_u32 s2, 01567; GFX11-NEXT: s_mov_b32 s2, 01568; GFX11-NEXT: s_cbranch_scc0 .LBB9_31569; GFX11-NEXT: ; %bb.1: ; %Flow1570; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s21571; GFX11-NEXT: s_cbranch_vccnz .LBB9_41572; GFX11-NEXT: .LBB9_2: ; %cmp.true1573; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s11574; GFX11-NEXT: v_pk_add_f16 v0, 0x200, s0 op_sel_hi:[0,1]1575; GFX11-NEXT: s_setpc_b64 s[30:31]1576; GFX11-NEXT: .LBB9_3:1577; GFX11-NEXT: s_branch .LBB9_21578; GFX11-NEXT: .LBB9_4:1579; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s11580; GFX11-NEXT: s_setpc_b64 s[30:31]1581 %cmp = icmp eq i32 %b, 01582 br i1 %cmp, label %cmp.true, label %cmp.false1583 1584cmp.true:1585 %a1 = fadd <3 x half> %a, splat (half 0xH0200)1586 %a2 = bitcast <3 x half> %a1 to <3 x i16>1587 br label %end1588 1589cmp.false:1590 %a3 = bitcast <3 x half> %a to <3 x i16>1591 br label %end1592 1593end:1594 %phi = phi <3 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]1595 ret <3 x i16> %phi1596}1597 1598define <3 x half> @bitcast_v3i16_to_v3f16(<3 x i16> %a, i32 %b) {1599; SI-LABEL: bitcast_v3i16_to_v3f16:1600; SI: ; %bb.0:1601; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1602; SI-NEXT: v_mov_b32_e32 v6, v21603; SI-NEXT: v_mov_b32_e32 v4, v11604; SI-NEXT: v_mov_b32_e32 v5, v01605; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31606; SI-NEXT: ; implicit-def: $vgpr01607; SI-NEXT: ; implicit-def: $vgpr11608; SI-NEXT: ; implicit-def: $vgpr21609; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc1610; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]1611; SI-NEXT: s_cbranch_execnz .LBB10_31612; SI-NEXT: ; %bb.1: ; %Flow1613; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1614; SI-NEXT: s_cbranch_execnz .LBB10_41615; SI-NEXT: .LBB10_2: ; %end1616; SI-NEXT: s_or_b64 exec, exec, s[4:5]1617; SI-NEXT: s_setpc_b64 s[30:31]1618; SI-NEXT: .LBB10_3: ; %cmp.false1619; SI-NEXT: v_cvt_f32_f16_e32 v0, v51620; SI-NEXT: v_cvt_f32_f16_e32 v1, v41621; SI-NEXT: v_cvt_f32_f16_e32 v2, v61622; SI-NEXT: ; implicit-def: $vgpr61623; SI-NEXT: ; implicit-def: $vgpr41624; SI-NEXT: ; implicit-def: $vgpr51625; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1626; SI-NEXT: s_cbranch_execz .LBB10_21627; SI-NEXT: .LBB10_4: ; %cmp.true1628; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v61629; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v41630; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v51631; SI-NEXT: v_cvt_f32_f16_e32 v0, v01632; SI-NEXT: v_cvt_f32_f16_e32 v1, v11633; SI-NEXT: v_cvt_f32_f16_e32 v2, v21634; SI-NEXT: s_or_b64 exec, exec, s[4:5]1635; SI-NEXT: s_setpc_b64 s[30:31]1636;1637; VI-LABEL: bitcast_v3i16_to_v3f16:1638; VI: ; %bb.0:1639; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1640; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v21641; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc1642; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]1643; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1644; VI-NEXT: ; %bb.1: ; %cmp.true1645; VI-NEXT: v_mov_b32_e32 v2, 31646; VI-NEXT: v_add_u16_sdwa v2, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1647; VI-NEXT: v_add_u16_e32 v0, 3, v01648; VI-NEXT: v_add_u16_e32 v1, 3, v11649; VI-NEXT: v_or_b32_e32 v0, v0, v21650; VI-NEXT: ; %bb.2: ; %end1651; VI-NEXT: s_or_b64 exec, exec, s[4:5]1652; VI-NEXT: s_setpc_b64 s[30:31]1653;1654; GFX9-LABEL: bitcast_v3i16_to_v3f16:1655; GFX9: ; %bb.0:1656; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1657; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v21658; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc1659; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]1660; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1661; GFX9-NEXT: ; %bb.1: ; %cmp.true1662; GFX9-NEXT: v_pk_add_u16 v1, v1, 31663; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]1664; GFX9-NEXT: ; %bb.2: ; %end1665; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]1666; GFX9-NEXT: s_setpc_b64 s[30:31]1667;1668; GFX11-LABEL: bitcast_v3i16_to_v3f16:1669; GFX11: ; %bb.0:1670; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1671; GFX11-NEXT: s_mov_b32 s0, exec_lo1672; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v21673; GFX11-NEXT: s_xor_b32 s0, exec_lo, s01674; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)1675; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s01676; GFX11-NEXT: ; %bb.1: ; %cmp.true1677; GFX11-NEXT: v_pk_add_u16 v1, v1, 31678; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]1679; GFX11-NEXT: ; %bb.2: ; %end1680; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s01681; GFX11-NEXT: s_setpc_b64 s[30:31]1682 %cmp = icmp eq i32 %b, 01683 br i1 %cmp, label %cmp.true, label %cmp.false1684 1685cmp.true:1686 %a1 = add <3 x i16> %a, splat (i16 3)1687 %a2 = bitcast <3 x i16> %a1 to <3 x half>1688 br label %end1689 1690cmp.false:1691 %a3 = bitcast <3 x i16> %a to <3 x half>1692 br label %end1693 1694end:1695 %phi = phi <3 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]1696 ret <3 x half> %phi1697}1698 1699define inreg <3 x half> @bitcast_v3i16_to_v3f16_scalar(<3 x i16> inreg %a, i32 inreg %b) {1700; SI-LABEL: bitcast_v3i16_to_v3f16_scalar:1701; SI: ; %bb.0:1702; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1703; SI-NEXT: s_cmp_lg_u32 s19, 01704; SI-NEXT: s_cbranch_scc0 .LBB11_41705; SI-NEXT: ; %bb.1: ; %cmp.false1706; SI-NEXT: v_cvt_f32_f16_e32 v0, s161707; SI-NEXT: v_cvt_f32_f16_e32 v1, s171708; SI-NEXT: v_cvt_f32_f16_e32 v2, s181709; SI-NEXT: s_cbranch_execnz .LBB11_31710; SI-NEXT: .LBB11_2: ; %cmp.true1711; SI-NEXT: s_add_i32 s18, s18, 31712; SI-NEXT: s_add_i32 s17, s17, 31713; SI-NEXT: s_add_i32 s16, s16, 31714; SI-NEXT: v_cvt_f32_f16_e32 v0, s161715; SI-NEXT: v_cvt_f32_f16_e32 v1, s171716; SI-NEXT: v_cvt_f32_f16_e32 v2, s181717; SI-NEXT: .LBB11_3: ; %end1718; SI-NEXT: s_setpc_b64 s[30:31]1719; SI-NEXT: .LBB11_4:1720; SI-NEXT: ; implicit-def: $vgpr01721; SI-NEXT: ; implicit-def: $vgpr11722; SI-NEXT: ; implicit-def: $vgpr21723; SI-NEXT: s_branch .LBB11_21724;1725; VI-LABEL: bitcast_v3i16_to_v3f16_scalar:1726; VI: ; %bb.0:1727; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1728; VI-NEXT: s_cmp_lg_u32 s18, 01729; VI-NEXT: s_cbranch_scc0 .LBB11_41730; VI-NEXT: ; %bb.1: ; %cmp.false1731; VI-NEXT: s_cbranch_execnz .LBB11_31732; VI-NEXT: .LBB11_2: ; %cmp.true1733; VI-NEXT: s_add_i32 s5, s16, 31734; VI-NEXT: s_and_b32 s4, s16, 0xffff00001735; VI-NEXT: s_and_b32 s5, s5, 0xffff1736; VI-NEXT: s_or_b32 s4, s4, s51737; VI-NEXT: s_add_i32 s17, s17, 31738; VI-NEXT: s_add_i32 s16, s4, 0x300001739; VI-NEXT: .LBB11_3: ; %end1740; VI-NEXT: v_mov_b32_e32 v0, s161741; VI-NEXT: v_mov_b32_e32 v1, s171742; VI-NEXT: s_setpc_b64 s[30:31]1743; VI-NEXT: .LBB11_4:1744; VI-NEXT: s_branch .LBB11_21745;1746; GFX9-LABEL: bitcast_v3i16_to_v3f16_scalar:1747; GFX9: ; %bb.0:1748; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1749; GFX9-NEXT: s_cmp_lg_u32 s18, 01750; GFX9-NEXT: s_cbranch_scc0 .LBB11_31751; GFX9-NEXT: ; %bb.1: ; %cmp.false1752; GFX9-NEXT: s_cbranch_execnz .LBB11_41753; GFX9-NEXT: .LBB11_2: ; %cmp.true1754; GFX9-NEXT: v_pk_add_u16 v1, s17, 31755; GFX9-NEXT: v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]1756; GFX9-NEXT: s_setpc_b64 s[30:31]1757; GFX9-NEXT: .LBB11_3:1758; GFX9-NEXT: s_branch .LBB11_21759; GFX9-NEXT: .LBB11_4:1760; GFX9-NEXT: v_mov_b32_e32 v0, s161761; GFX9-NEXT: v_mov_b32_e32 v1, s171762; GFX9-NEXT: s_setpc_b64 s[30:31]1763;1764; GFX11-LABEL: bitcast_v3i16_to_v3f16_scalar:1765; GFX11: ; %bb.0:1766; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1767; GFX11-NEXT: s_cmp_lg_u32 s2, 01768; GFX11-NEXT: s_mov_b32 s2, 01769; GFX11-NEXT: s_cbranch_scc0 .LBB11_31770; GFX11-NEXT: ; %bb.1: ; %Flow1771; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s21772; GFX11-NEXT: s_cbranch_vccnz .LBB11_41773; GFX11-NEXT: .LBB11_2: ; %cmp.true1774; GFX11-NEXT: v_pk_add_u16 v1, s1, 31775; GFX11-NEXT: v_pk_add_u16 v0, s0, 3 op_sel_hi:[1,0]1776; GFX11-NEXT: s_setpc_b64 s[30:31]1777; GFX11-NEXT: .LBB11_3:1778; GFX11-NEXT: s_branch .LBB11_21779; GFX11-NEXT: .LBB11_4:1780; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s11781; GFX11-NEXT: s_setpc_b64 s[30:31]1782 %cmp = icmp eq i32 %b, 01783 br i1 %cmp, label %cmp.true, label %cmp.false1784 1785cmp.true:1786 %a1 = add <3 x i16> %a, splat (i16 3)1787 %a2 = bitcast <3 x i16> %a1 to <3 x half>1788 br label %end1789 1790cmp.false:1791 %a3 = bitcast <3 x i16> %a to <3 x half>1792 br label %end1793 1794end:1795 %phi = phi <3 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]1796 ret <3 x half> %phi1797}1798