brintos / llvm-project-archived public Read only

1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52 3; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=SI %s4; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=VI %s5; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s6; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s7; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s8 9define double @bitcast_i64_to_f64(i64 %a, i32 %b) {10; SI-LABEL: bitcast_i64_to_f64:11; SI:       ; %bb.0:12; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)13; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v214; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc15; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]16; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]17; SI-NEXT:  ; %bb.1: ; %cmp.true18; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v019; SI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc20; SI-NEXT:  ; %bb.2: ; %end21; SI-NEXT:    s_or_b64 exec, exec, s[4:5]22; SI-NEXT:    s_setpc_b64 s[30:31]23;24; VI-LABEL: bitcast_i64_to_f64:25; VI:       ; %bb.0:26; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)27; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v228; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc29; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]30; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]31; VI-NEXT:  ; %bb.1: ; %cmp.true32; VI-NEXT:    v_add_u32_e32 v0, vcc, 3, v033; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc34; VI-NEXT:  ; %bb.2: ; %end35; VI-NEXT:    s_or_b64 exec, exec, s[4:5]36; VI-NEXT:    s_setpc_b64 s[30:31]37;38; GFX9-LABEL: bitcast_i64_to_f64:39; GFX9:       ; %bb.0:40; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)41; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v242; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc43; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]44; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]45; GFX9-NEXT:  ; %bb.1: ; %cmp.true46; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, 3, v047; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc48; GFX9-NEXT:  ; %bb.2: ; %end49; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]50; GFX9-NEXT:    s_setpc_b64 s[30:31]51;52; GFX11-LABEL: bitcast_i64_to_f64:53; GFX11:       ; %bb.0:54; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)55; GFX11-NEXT:    s_mov_b32 s0, exec_lo56; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v257; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s058; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)59; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s060; GFX11-NEXT:  ; %bb.1: ; %cmp.true61; GFX11-NEXT:    v_add_co_u32 v0, vcc_lo, v0, 362; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)63; GFX11-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo64; GFX11-NEXT:  ; %bb.2: ; %end65; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s066; GFX11-NEXT:    s_setpc_b64 s[30:31]67  %cmp = icmp eq i32 %b, 068  br i1 %cmp, label %cmp.true, label %cmp.false69 70cmp.true:71  %a1 = add i64 %a, 372  %a2 = bitcast i64 %a1 to double73  br label %end74 75cmp.false:76  %a3 = bitcast i64 %a to double77  br label %end78 79end:80  %phi = phi double [ %a2, %cmp.true ], [ %a3, %cmp.false ]81  ret double %phi82}83 84define inreg double @bitcast_i64_to_f64_scalar(i64 inreg %a, i32 inreg %b) {85; SI-LABEL: bitcast_i64_to_f64_scalar:86; SI:       ; %bb.0:87; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)88; SI-NEXT:    s_cmp_lg_u32 s18, 089; SI-NEXT:    s_cbranch_scc0 .LBB1_490; SI-NEXT:  ; %bb.1: ; %cmp.false91; SI-NEXT:    s_cbranch_execnz .LBB1_392; SI-NEXT:  .LBB1_2: ; %cmp.true93; SI-NEXT:    s_add_u32 s16, s16, 394; SI-NEXT:    s_addc_u32 s17, s17, 095; SI-NEXT:  .LBB1_3: ; %end96; SI-NEXT:    v_mov_b32_e32 v0, s1697; SI-NEXT:    v_mov_b32_e32 v1, s1798; SI-NEXT:    s_setpc_b64 s[30:31]99; SI-NEXT:  .LBB1_4:100; SI-NEXT:    s_branch .LBB1_2101;102; VI-LABEL: bitcast_i64_to_f64_scalar:103; VI:       ; %bb.0:104; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)105; VI-NEXT:    s_cmp_lg_u32 s18, 0106; VI-NEXT:    s_cbranch_scc0 .LBB1_4107; VI-NEXT:  ; %bb.1: ; %cmp.false108; VI-NEXT:    s_cbranch_execnz .LBB1_3109; VI-NEXT:  .LBB1_2: ; %cmp.true110; VI-NEXT:    s_add_u32 s16, s16, 3111; VI-NEXT:    s_addc_u32 s17, s17, 0112; VI-NEXT:  .LBB1_3: ; %end113; VI-NEXT:    v_mov_b32_e32 v0, s16114; VI-NEXT:    v_mov_b32_e32 v1, s17115; VI-NEXT:    s_setpc_b64 s[30:31]116; VI-NEXT:  .LBB1_4:117; VI-NEXT:    s_branch .LBB1_2118;119; GFX9-LABEL: bitcast_i64_to_f64_scalar:120; GFX9:       ; %bb.0:121; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)122; GFX9-NEXT:    s_cmp_lg_u32 s18, 0123; GFX9-NEXT:    s_cbranch_scc0 .LBB1_4124; GFX9-NEXT:  ; %bb.1: ; %cmp.false125; GFX9-NEXT:    s_cbranch_execnz .LBB1_3126; GFX9-NEXT:  .LBB1_2: ; %cmp.true127; GFX9-NEXT:    s_add_u32 s16, s16, 3128; GFX9-NEXT:    s_addc_u32 s17, s17, 0129; GFX9-NEXT:  .LBB1_3: ; %end130; GFX9-NEXT:    v_mov_b32_e32 v0, s16131; GFX9-NEXT:    v_mov_b32_e32 v1, s17132; GFX9-NEXT:    s_setpc_b64 s[30:31]133; GFX9-NEXT:  .LBB1_4:134; GFX9-NEXT:    s_branch .LBB1_2135;136; GFX11-LABEL: bitcast_i64_to_f64_scalar:137; GFX11:       ; %bb.0:138; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)139; GFX11-NEXT:    s_cmp_lg_u32 s2, 0140; GFX11-NEXT:    s_mov_b32 s2, 0141; GFX11-NEXT:    s_cbranch_scc0 .LBB1_4142; GFX11-NEXT:  ; %bb.1: ; %Flow143; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s2144; GFX11-NEXT:    s_cbranch_vccnz .LBB1_3145; GFX11-NEXT:  .LBB1_2: ; %cmp.true146; GFX11-NEXT:    s_add_u32 s0, s0, 3147; GFX11-NEXT:    s_addc_u32 s1, s1, 0148; GFX11-NEXT:  .LBB1_3: ; %end149; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)150; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1151; GFX11-NEXT:    s_setpc_b64 s[30:31]152; GFX11-NEXT:  .LBB1_4:153; GFX11-NEXT:    s_branch .LBB1_2154  %cmp = icmp eq i32 %b, 0155  br i1 %cmp, label %cmp.true, label %cmp.false156 157cmp.true:158  %a1 = add i64 %a, 3159  %a2 = bitcast i64 %a1 to double160  br label %end161 162cmp.false:163  %a3 = bitcast i64 %a to double164  br label %end165 166end:167  %phi = phi double [ %a2, %cmp.true ], [ %a3, %cmp.false ]168  ret double %phi169}170 171define i64 @bitcast_f64_to_i64(double %a, i32 %b) {172; SI-LABEL: bitcast_f64_to_i64:173; SI:       ; %bb.0:174; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)175; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2176; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc177; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]178; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]179; SI-NEXT:  ; %bb.1: ; %cmp.true180; SI-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0181; SI-NEXT:  ; %bb.2: ; %end182; SI-NEXT:    s_or_b64 exec, exec, s[4:5]183; SI-NEXT:    s_setpc_b64 s[30:31]184;185; VI-LABEL: bitcast_f64_to_i64:186; VI:       ; %bb.0:187; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)188; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2189; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc190; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]191; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]192; VI-NEXT:  ; %bb.1: ; %cmp.true193; VI-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0194; VI-NEXT:  ; %bb.2: ; %end195; VI-NEXT:    s_or_b64 exec, exec, s[4:5]196; VI-NEXT:    s_setpc_b64 s[30:31]197;198; GFX9-LABEL: bitcast_f64_to_i64:199; GFX9:       ; %bb.0:200; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)201; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2202; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc203; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]204; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]205; GFX9-NEXT:  ; %bb.1: ; %cmp.true206; GFX9-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0207; GFX9-NEXT:  ; %bb.2: ; %end208; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]209; GFX9-NEXT:    s_setpc_b64 s[30:31]210;211; GFX11-LABEL: bitcast_f64_to_i64:212; GFX11:       ; %bb.0:213; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)214; GFX11-NEXT:    s_mov_b32 s0, exec_lo215; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v2216; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0217; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)218; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0219; GFX11-NEXT:    s_cbranch_execz .LBB2_2220; GFX11-NEXT:  ; %bb.1: ; %cmp.true221; GFX11-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0222; GFX11-NEXT:  .LBB2_2: ; %end223; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0224; GFX11-NEXT:    s_setpc_b64 s[30:31]225  %cmp = icmp eq i32 %b, 0226  br i1 %cmp, label %cmp.true, label %cmp.false227 228cmp.true:229  %a1 = fadd double %a, 1.000000e+00230  %a2 = bitcast double %a1 to i64231  br label %end232 233cmp.false:234  %a3 = bitcast double %a to i64235  br label %end236 237end:238  %phi = phi i64 [ %a2, %cmp.true ], [ %a3, %cmp.false ]239  ret i64 %phi240}241 242define inreg i64 @bitcast_f64_to_i64_scalar(double inreg %a, i32 inreg %b) {243; SI-LABEL: bitcast_f64_to_i64_scalar:244; SI:       ; %bb.0:245; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)246; SI-NEXT:    s_cmp_lg_u32 s18, 0247; SI-NEXT:    s_cbranch_scc0 .LBB3_3248; SI-NEXT:  ; %bb.1: ; %cmp.false249; SI-NEXT:    s_cbranch_execnz .LBB3_4250; SI-NEXT:  .LBB3_2: ; %cmp.true251; SI-NEXT:    v_add_f64 v[0:1], s[16:17], 1.0252; SI-NEXT:    s_setpc_b64 s[30:31]253; SI-NEXT:  .LBB3_3:254; SI-NEXT:    s_branch .LBB3_2255; SI-NEXT:  .LBB3_4:256; SI-NEXT:    v_mov_b32_e32 v0, s16257; SI-NEXT:    v_mov_b32_e32 v1, s17258; SI-NEXT:    s_setpc_b64 s[30:31]259;260; VI-LABEL: bitcast_f64_to_i64_scalar:261; VI:       ; %bb.0:262; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)263; VI-NEXT:    s_cmp_lg_u32 s18, 0264; VI-NEXT:    s_cbranch_scc0 .LBB3_3265; VI-NEXT:  ; %bb.1: ; %cmp.false266; VI-NEXT:    s_cbranch_execnz .LBB3_4267; VI-NEXT:  .LBB3_2: ; %cmp.true268; VI-NEXT:    v_add_f64 v[0:1], s[16:17], 1.0269; VI-NEXT:    s_setpc_b64 s[30:31]270; VI-NEXT:  .LBB3_3:271; VI-NEXT:    s_branch .LBB3_2272; VI-NEXT:  .LBB3_4:273; VI-NEXT:    v_mov_b32_e32 v0, s16274; VI-NEXT:    v_mov_b32_e32 v1, s17275; VI-NEXT:    s_setpc_b64 s[30:31]276;277; GFX9-LABEL: bitcast_f64_to_i64_scalar:278; GFX9:       ; %bb.0:279; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)280; GFX9-NEXT:    s_cmp_lg_u32 s18, 0281; GFX9-NEXT:    s_cbranch_scc0 .LBB3_3282; GFX9-NEXT:  ; %bb.1: ; %cmp.false283; GFX9-NEXT:    s_cbranch_execnz .LBB3_4284; GFX9-NEXT:  .LBB3_2: ; %cmp.true285; GFX9-NEXT:    v_add_f64 v[0:1], s[16:17], 1.0286; GFX9-NEXT:    s_setpc_b64 s[30:31]287; GFX9-NEXT:  .LBB3_3:288; GFX9-NEXT:    s_branch .LBB3_2289; GFX9-NEXT:  .LBB3_4:290; GFX9-NEXT:    v_mov_b32_e32 v0, s16291; GFX9-NEXT:    v_mov_b32_e32 v1, s17292; GFX9-NEXT:    s_setpc_b64 s[30:31]293;294; GFX11-LABEL: bitcast_f64_to_i64_scalar:295; GFX11:       ; %bb.0:296; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)297; GFX11-NEXT:    s_cmp_lg_u32 s2, 0298; GFX11-NEXT:    s_mov_b32 s2, 0299; GFX11-NEXT:    s_cbranch_scc0 .LBB3_3300; GFX11-NEXT:  ; %bb.1: ; %Flow301; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s2302; GFX11-NEXT:    s_cbranch_vccnz .LBB3_4303; GFX11-NEXT:  .LBB3_2: ; %cmp.true304; GFX11-NEXT:    v_add_f64 v[0:1], s[0:1], 1.0305; GFX11-NEXT:    s_setpc_b64 s[30:31]306; GFX11-NEXT:  .LBB3_3:307; GFX11-NEXT:    s_branch .LBB3_2308; GFX11-NEXT:  .LBB3_4:309; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1310; GFX11-NEXT:    s_setpc_b64 s[30:31]311  %cmp = icmp eq i32 %b, 0312  br i1 %cmp, label %cmp.true, label %cmp.false313 314cmp.true:315  %a1 = fadd double %a, 1.000000e+00316  %a2 = bitcast double %a1 to i64317  br label %end318 319cmp.false:320  %a3 = bitcast double %a to i64321  br label %end322 323end:324  %phi = phi i64 [ %a2, %cmp.true ], [ %a3, %cmp.false ]325  ret i64 %phi326}327 328define <2 x i32> @bitcast_i64_to_v2i32(i64 %a, i32 %b) {329; SI-LABEL: bitcast_i64_to_v2i32:330; SI:       ; %bb.0:331; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)332; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2333; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc334; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]335; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]336; SI-NEXT:  ; %bb.1: ; %cmp.true337; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v0338; SI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc339; SI-NEXT:  ; %bb.2: ; %end340; SI-NEXT:    s_or_b64 exec, exec, s[4:5]341; SI-NEXT:    s_setpc_b64 s[30:31]342;343; VI-LABEL: bitcast_i64_to_v2i32:344; VI:       ; %bb.0:345; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)346; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2347; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc348; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]349; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]350; VI-NEXT:  ; %bb.1: ; %cmp.true351; VI-NEXT:    v_add_u32_e32 v0, vcc, 3, v0352; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc353; VI-NEXT:  ; %bb.2: ; %end354; VI-NEXT:    s_or_b64 exec, exec, s[4:5]355; VI-NEXT:    s_setpc_b64 s[30:31]356;357; GFX9-LABEL: bitcast_i64_to_v2i32:358; GFX9:       ; %bb.0:359; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)360; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2361; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc362; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]363; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]364; GFX9-NEXT:  ; %bb.1: ; %cmp.true365; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, 3, v0366; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc367; GFX9-NEXT:  ; %bb.2: ; %end368; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]369; GFX9-NEXT:    s_setpc_b64 s[30:31]370;371; GFX11-LABEL: bitcast_i64_to_v2i32:372; GFX11:       ; %bb.0:373; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)374; GFX11-NEXT:    s_mov_b32 s0, exec_lo375; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v2376; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0377; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)378; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0379; GFX11-NEXT:  ; %bb.1: ; %cmp.true380; GFX11-NEXT:    v_add_co_u32 v0, vcc_lo, v0, 3381; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)382; GFX11-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo383; GFX11-NEXT:  ; %bb.2: ; %end384; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0385; GFX11-NEXT:    s_setpc_b64 s[30:31]386  %cmp = icmp eq i32 %b, 0387  br i1 %cmp, label %cmp.true, label %cmp.false388 389cmp.true:390  %a1 = add i64 %a, 3391  %a2 = bitcast i64 %a1 to <2 x i32>392  br label %end393 394cmp.false:395  %a3 = bitcast i64 %a to <2 x i32>396  br label %end397 398end:399  %phi = phi <2 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]400  ret <2 x i32> %phi401}402 403define inreg <2 x i32> @bitcast_i64_to_v2i32_scalar(i64 inreg %a, i32 inreg %b) {404; SI-LABEL: bitcast_i64_to_v2i32_scalar:405; SI:       ; %bb.0:406; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)407; SI-NEXT:    s_cmp_lg_u32 s18, 0408; SI-NEXT:    s_cbranch_scc0 .LBB5_4409; SI-NEXT:  ; %bb.1: ; %cmp.false410; SI-NEXT:    s_cbranch_execnz .LBB5_3411; SI-NEXT:  .LBB5_2: ; %cmp.true412; SI-NEXT:    s_add_u32 s16, s16, 3413; SI-NEXT:    s_addc_u32 s17, s17, 0414; SI-NEXT:  .LBB5_3: ; %end415; SI-NEXT:    v_mov_b32_e32 v0, s16416; SI-NEXT:    v_mov_b32_e32 v1, s17417; SI-NEXT:    s_setpc_b64 s[30:31]418; SI-NEXT:  .LBB5_4:419; SI-NEXT:    s_branch .LBB5_2420;421; VI-LABEL: bitcast_i64_to_v2i32_scalar:422; VI:       ; %bb.0:423; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)424; VI-NEXT:    s_cmp_lg_u32 s18, 0425; VI-NEXT:    s_cbranch_scc0 .LBB5_4426; VI-NEXT:  ; %bb.1: ; %cmp.false427; VI-NEXT:    s_cbranch_execnz .LBB5_3428; VI-NEXT:  .LBB5_2: ; %cmp.true429; VI-NEXT:    s_add_u32 s16, s16, 3430; VI-NEXT:    s_addc_u32 s17, s17, 0431; VI-NEXT:  .LBB5_3: ; %end432; VI-NEXT:    v_mov_b32_e32 v0, s16433; VI-NEXT:    v_mov_b32_e32 v1, s17434; VI-NEXT:    s_setpc_b64 s[30:31]435; VI-NEXT:  .LBB5_4:436; VI-NEXT:    s_branch .LBB5_2437;438; GFX9-LABEL: bitcast_i64_to_v2i32_scalar:439; GFX9:       ; %bb.0:440; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)441; GFX9-NEXT:    s_cmp_lg_u32 s18, 0442; GFX9-NEXT:    s_cbranch_scc0 .LBB5_4443; GFX9-NEXT:  ; %bb.1: ; %cmp.false444; GFX9-NEXT:    s_cbranch_execnz .LBB5_3445; GFX9-NEXT:  .LBB5_2: ; %cmp.true446; GFX9-NEXT:    s_add_u32 s16, s16, 3447; GFX9-NEXT:    s_addc_u32 s17, s17, 0448; GFX9-NEXT:  .LBB5_3: ; %end449; GFX9-NEXT:    v_mov_b32_e32 v0, s16450; GFX9-NEXT:    v_mov_b32_e32 v1, s17451; GFX9-NEXT:    s_setpc_b64 s[30:31]452; GFX9-NEXT:  .LBB5_4:453; GFX9-NEXT:    s_branch .LBB5_2454;455; GFX11-LABEL: bitcast_i64_to_v2i32_scalar:456; GFX11:       ; %bb.0:457; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)458; GFX11-NEXT:    s_cmp_lg_u32 s2, 0459; GFX11-NEXT:    s_mov_b32 s2, 0460; GFX11-NEXT:    s_cbranch_scc0 .LBB5_4461; GFX11-NEXT:  ; %bb.1: ; %Flow462; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s2463; GFX11-NEXT:    s_cbranch_vccnz .LBB5_3464; GFX11-NEXT:  .LBB5_2: ; %cmp.true465; GFX11-NEXT:    s_add_u32 s0, s0, 3466; GFX11-NEXT:    s_addc_u32 s1, s1, 0467; GFX11-NEXT:  .LBB5_3: ; %end468; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)469; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1470; GFX11-NEXT:    s_setpc_b64 s[30:31]471; GFX11-NEXT:  .LBB5_4:472; GFX11-NEXT:    s_branch .LBB5_2473  %cmp = icmp eq i32 %b, 0474  br i1 %cmp, label %cmp.true, label %cmp.false475 476cmp.true:477  %a1 = add i64 %a, 3478  %a2 = bitcast i64 %a1 to <2 x i32>479  br label %end480 481cmp.false:482  %a3 = bitcast i64 %a to <2 x i32>483  br label %end484 485end:486  %phi = phi <2 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]487  ret <2 x i32> %phi488}489 490define i64 @bitcast_v2i32_to_i64(<2 x i32> %a, i32 %b) {491; SI-LABEL: bitcast_v2i32_to_i64:492; SI:       ; %bb.0:493; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)494; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2495; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc496; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]497; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]498; SI-NEXT:  ; %bb.1: ; %cmp.true499; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v1500; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v0501; SI-NEXT:  ; %bb.2: ; %end502; SI-NEXT:    s_or_b64 exec, exec, s[4:5]503; SI-NEXT:    s_setpc_b64 s[30:31]504;505; VI-LABEL: bitcast_v2i32_to_i64:506; VI:       ; %bb.0:507; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)508; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2509; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc510; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]511; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]512; VI-NEXT:  ; %bb.1: ; %cmp.true513; VI-NEXT:    v_add_u32_e32 v1, vcc, 3, v1514; VI-NEXT:    v_add_u32_e32 v0, vcc, 3, v0515; VI-NEXT:  ; %bb.2: ; %end516; VI-NEXT:    s_or_b64 exec, exec, s[4:5]517; VI-NEXT:    s_setpc_b64 s[30:31]518;519; GFX9-LABEL: bitcast_v2i32_to_i64:520; GFX9:       ; %bb.0:521; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)522; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2523; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc524; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]525; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]526; GFX9-NEXT:  ; %bb.1: ; %cmp.true527; GFX9-NEXT:    v_add_u32_e32 v1, 3, v1528; GFX9-NEXT:    v_add_u32_e32 v0, 3, v0529; GFX9-NEXT:  ; %bb.2: ; %end530; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]531; GFX9-NEXT:    s_setpc_b64 s[30:31]532;533; GFX11-LABEL: bitcast_v2i32_to_i64:534; GFX11:       ; %bb.0:535; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)536; GFX11-NEXT:    s_mov_b32 s0, exec_lo537; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v2538; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0539; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)540; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0541; GFX11-NEXT:  ; %bb.1: ; %cmp.true542; GFX11-NEXT:    v_add_nc_u32_e32 v1, 3, v1543; GFX11-NEXT:    v_add_nc_u32_e32 v0, 3, v0544; GFX11-NEXT:  ; %bb.2: ; %end545; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0546; GFX11-NEXT:    s_setpc_b64 s[30:31]547  %cmp = icmp eq i32 %b, 0548  br i1 %cmp, label %cmp.true, label %cmp.false549 550cmp.true:551  %a1 = add <2 x i32> %a, splat (i32 3)552  %a2 = bitcast <2 x i32> %a1 to i64553  br label %end554 555cmp.false:556  %a3 = bitcast <2 x i32> %a to i64557  br label %end558 559end:560  %phi = phi i64 [ %a2, %cmp.true ], [ %a3, %cmp.false ]561  ret i64 %phi562}563 564define inreg i64 @bitcast_v2i32_to_i64_scalar(<2 x i32> inreg %a, i32 inreg %b) {565; SI-LABEL: bitcast_v2i32_to_i64_scalar:566; SI:       ; %bb.0:567; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)568; SI-NEXT:    s_cmp_lg_u32 s18, 0569; SI-NEXT:    s_cbranch_scc0 .LBB7_4570; SI-NEXT:  ; %bb.1: ; %cmp.false571; SI-NEXT:    s_cbranch_execnz .LBB7_3572; SI-NEXT:  .LBB7_2: ; %cmp.true573; SI-NEXT:    s_add_i32 s17, s17, 3574; SI-NEXT:    s_add_i32 s16, s16, 3575; SI-NEXT:  .LBB7_3: ; %end576; SI-NEXT:    v_mov_b32_e32 v0, s16577; SI-NEXT:    v_mov_b32_e32 v1, s17578; SI-NEXT:    s_setpc_b64 s[30:31]579; SI-NEXT:  .LBB7_4:580; SI-NEXT:    s_branch .LBB7_2581;582; VI-LABEL: bitcast_v2i32_to_i64_scalar:583; VI:       ; %bb.0:584; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)585; VI-NEXT:    s_cmp_lg_u32 s18, 0586; VI-NEXT:    s_cbranch_scc0 .LBB7_4587; VI-NEXT:  ; %bb.1: ; %cmp.false588; VI-NEXT:    s_cbranch_execnz .LBB7_3589; VI-NEXT:  .LBB7_2: ; %cmp.true590; VI-NEXT:    s_add_i32 s17, s17, 3591; VI-NEXT:    s_add_i32 s16, s16, 3592; VI-NEXT:  .LBB7_3: ; %end593; VI-NEXT:    v_mov_b32_e32 v0, s16594; VI-NEXT:    v_mov_b32_e32 v1, s17595; VI-NEXT:    s_setpc_b64 s[30:31]596; VI-NEXT:  .LBB7_4:597; VI-NEXT:    s_branch .LBB7_2598;599; GFX9-LABEL: bitcast_v2i32_to_i64_scalar:600; GFX9:       ; %bb.0:601; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)602; GFX9-NEXT:    s_cmp_lg_u32 s18, 0603; GFX9-NEXT:    s_cbranch_scc0 .LBB7_4604; GFX9-NEXT:  ; %bb.1: ; %cmp.false605; GFX9-NEXT:    s_cbranch_execnz .LBB7_3606; GFX9-NEXT:  .LBB7_2: ; %cmp.true607; GFX9-NEXT:    s_add_i32 s17, s17, 3608; GFX9-NEXT:    s_add_i32 s16, s16, 3609; GFX9-NEXT:  .LBB7_3: ; %end610; GFX9-NEXT:    v_mov_b32_e32 v0, s16611; GFX9-NEXT:    v_mov_b32_e32 v1, s17612; GFX9-NEXT:    s_setpc_b64 s[30:31]613; GFX9-NEXT:  .LBB7_4:614; GFX9-NEXT:    s_branch .LBB7_2615;616; GFX11-LABEL: bitcast_v2i32_to_i64_scalar:617; GFX11:       ; %bb.0:618; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)619; GFX11-NEXT:    s_cmp_lg_u32 s2, 0620; GFX11-NEXT:    s_mov_b32 s2, 0621; GFX11-NEXT:    s_cbranch_scc0 .LBB7_4622; GFX11-NEXT:  ; %bb.1: ; %Flow623; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s2624; GFX11-NEXT:    s_cbranch_vccnz .LBB7_3625; GFX11-NEXT:  .LBB7_2: ; %cmp.true626; GFX11-NEXT:    s_add_i32 s1, s1, 3627; GFX11-NEXT:    s_add_i32 s0, s0, 3628; GFX11-NEXT:  .LBB7_3: ; %end629; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)630; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1631; GFX11-NEXT:    s_setpc_b64 s[30:31]632; GFX11-NEXT:  .LBB7_4:633; GFX11-NEXT:    s_branch .LBB7_2634  %cmp = icmp eq i32 %b, 0635  br i1 %cmp, label %cmp.true, label %cmp.false636 637cmp.true:638  %a1 = add <2 x i32> %a, splat (i32 3)639  %a2 = bitcast <2 x i32> %a1 to i64640  br label %end641 642cmp.false:643  %a3 = bitcast <2 x i32> %a to i64644  br label %end645 646end:647  %phi = phi i64 [ %a2, %cmp.true ], [ %a3, %cmp.false ]648  ret i64 %phi649}650 651define <2 x float> @bitcast_i64_to_v2f32(i64 %a, i32 %b) {652; SI-LABEL: bitcast_i64_to_v2f32:653; SI:       ; %bb.0:654; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)655; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2656; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc657; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]658; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]659; SI-NEXT:  ; %bb.1: ; %cmp.true660; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v0661; SI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc662; SI-NEXT:  ; %bb.2: ; %end663; SI-NEXT:    s_or_b64 exec, exec, s[4:5]664; SI-NEXT:    s_setpc_b64 s[30:31]665;666; VI-LABEL: bitcast_i64_to_v2f32:667; VI:       ; %bb.0:668; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)669; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2670; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc671; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]672; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]673; VI-NEXT:  ; %bb.1: ; %cmp.true674; VI-NEXT:    v_add_u32_e32 v0, vcc, 3, v0675; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc676; VI-NEXT:  ; %bb.2: ; %end677; VI-NEXT:    s_or_b64 exec, exec, s[4:5]678; VI-NEXT:    s_setpc_b64 s[30:31]679;680; GFX9-LABEL: bitcast_i64_to_v2f32:681; GFX9:       ; %bb.0:682; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)683; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2684; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc685; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]686; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]687; GFX9-NEXT:  ; %bb.1: ; %cmp.true688; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, 3, v0689; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc690; GFX9-NEXT:  ; %bb.2: ; %end691; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]692; GFX9-NEXT:    s_setpc_b64 s[30:31]693;694; GFX11-LABEL: bitcast_i64_to_v2f32:695; GFX11:       ; %bb.0:696; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)697; GFX11-NEXT:    s_mov_b32 s0, exec_lo698; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v2699; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0700; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)701; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0702; GFX11-NEXT:  ; %bb.1: ; %cmp.true703; GFX11-NEXT:    v_add_co_u32 v0, vcc_lo, v0, 3704; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)705; GFX11-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo706; GFX11-NEXT:  ; %bb.2: ; %end707; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0708; GFX11-NEXT:    s_setpc_b64 s[30:31]709  %cmp = icmp eq i32 %b, 0710  br i1 %cmp, label %cmp.true, label %cmp.false711 712cmp.true:713  %a1 = add i64 %a, 3714  %a2 = bitcast i64 %a1 to <2 x float>715  br label %end716 717cmp.false:718  %a3 = bitcast i64 %a to <2 x float>719  br label %end720 721end:722  %phi = phi <2 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]723  ret <2 x float> %phi724}725 726define inreg <2 x float> @bitcast_i64_to_v2f32_scalar(i64 inreg %a, i32 inreg %b) {727; SI-LABEL: bitcast_i64_to_v2f32_scalar:728; SI:       ; %bb.0:729; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)730; SI-NEXT:    s_cmp_lg_u32 s18, 0731; SI-NEXT:    s_cbranch_scc0 .LBB9_4732; SI-NEXT:  ; %bb.1: ; %cmp.false733; SI-NEXT:    s_cbranch_execnz .LBB9_3734; SI-NEXT:  .LBB9_2: ; %cmp.true735; SI-NEXT:    s_add_u32 s16, s16, 3736; SI-NEXT:    s_addc_u32 s17, s17, 0737; SI-NEXT:  .LBB9_3: ; %end738; SI-NEXT:    v_mov_b32_e32 v0, s16739; SI-NEXT:    v_mov_b32_e32 v1, s17740; SI-NEXT:    s_setpc_b64 s[30:31]741; SI-NEXT:  .LBB9_4:742; SI-NEXT:    s_branch .LBB9_2743;744; VI-LABEL: bitcast_i64_to_v2f32_scalar:745; VI:       ; %bb.0:746; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)747; VI-NEXT:    s_cmp_lg_u32 s18, 0748; VI-NEXT:    s_cbranch_scc0 .LBB9_4749; VI-NEXT:  ; %bb.1: ; %cmp.false750; VI-NEXT:    s_cbranch_execnz .LBB9_3751; VI-NEXT:  .LBB9_2: ; %cmp.true752; VI-NEXT:    s_add_u32 s16, s16, 3753; VI-NEXT:    s_addc_u32 s17, s17, 0754; VI-NEXT:  .LBB9_3: ; %end755; VI-NEXT:    v_mov_b32_e32 v0, s16756; VI-NEXT:    v_mov_b32_e32 v1, s17757; VI-NEXT:    s_setpc_b64 s[30:31]758; VI-NEXT:  .LBB9_4:759; VI-NEXT:    s_branch .LBB9_2760;761; GFX9-LABEL: bitcast_i64_to_v2f32_scalar:762; GFX9:       ; %bb.0:763; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)764; GFX9-NEXT:    s_cmp_lg_u32 s18, 0765; GFX9-NEXT:    s_cbranch_scc0 .LBB9_4766; GFX9-NEXT:  ; %bb.1: ; %cmp.false767; GFX9-NEXT:    s_cbranch_execnz .LBB9_3768; GFX9-NEXT:  .LBB9_2: ; %cmp.true769; GFX9-NEXT:    s_add_u32 s16, s16, 3770; GFX9-NEXT:    s_addc_u32 s17, s17, 0771; GFX9-NEXT:  .LBB9_3: ; %end772; GFX9-NEXT:    v_mov_b32_e32 v0, s16773; GFX9-NEXT:    v_mov_b32_e32 v1, s17774; GFX9-NEXT:    s_setpc_b64 s[30:31]775; GFX9-NEXT:  .LBB9_4:776; GFX9-NEXT:    s_branch .LBB9_2777;778; GFX11-LABEL: bitcast_i64_to_v2f32_scalar:779; GFX11:       ; %bb.0:780; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)781; GFX11-NEXT:    s_cmp_lg_u32 s2, 0782; GFX11-NEXT:    s_mov_b32 s2, 0783; GFX11-NEXT:    s_cbranch_scc0 .LBB9_4784; GFX11-NEXT:  ; %bb.1: ; %Flow785; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s2786; GFX11-NEXT:    s_cbranch_vccnz .LBB9_3787; GFX11-NEXT:  .LBB9_2: ; %cmp.true788; GFX11-NEXT:    s_add_u32 s0, s0, 3789; GFX11-NEXT:    s_addc_u32 s1, s1, 0790; GFX11-NEXT:  .LBB9_3: ; %end791; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)792; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1793; GFX11-NEXT:    s_setpc_b64 s[30:31]794; GFX11-NEXT:  .LBB9_4:795; GFX11-NEXT:    s_branch .LBB9_2796  %cmp = icmp eq i32 %b, 0797  br i1 %cmp, label %cmp.true, label %cmp.false798 799cmp.true:800  %a1 = add i64 %a, 3801  %a2 = bitcast i64 %a1 to <2 x float>802  br label %end803 804cmp.false:805  %a3 = bitcast i64 %a to <2 x float>806  br label %end807 808end:809  %phi = phi <2 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]810  ret <2 x float> %phi811}812 813define i64 @bitcast_v2f32_to_i64(<2 x float> %a, i32 %b) {814; SI-LABEL: bitcast_v2f32_to_i64:815; SI:       ; %bb.0:816; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)817; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2818; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc819; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]820; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]821; SI-NEXT:  ; %bb.1: ; %cmp.true822; SI-NEXT:    v_add_f32_e32 v1, 1.0, v1823; SI-NEXT:    v_add_f32_e32 v0, 1.0, v0824; SI-NEXT:  ; %bb.2: ; %end825; SI-NEXT:    s_or_b64 exec, exec, s[4:5]826; SI-NEXT:    s_setpc_b64 s[30:31]827;828; VI-LABEL: bitcast_v2f32_to_i64:829; VI:       ; %bb.0:830; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)831; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2832; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc833; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]834; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]835; VI-NEXT:  ; %bb.1: ; %cmp.true836; VI-NEXT:    v_add_f32_e32 v1, 1.0, v1837; VI-NEXT:    v_add_f32_e32 v0, 1.0, v0838; VI-NEXT:  ; %bb.2: ; %end839; VI-NEXT:    s_or_b64 exec, exec, s[4:5]840; VI-NEXT:    s_setpc_b64 s[30:31]841;842; GFX9-LABEL: bitcast_v2f32_to_i64:843; GFX9:       ; %bb.0:844; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)845; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2846; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc847; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]848; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]849; GFX9-NEXT:  ; %bb.1: ; %cmp.true850; GFX9-NEXT:    v_add_f32_e32 v1, 1.0, v1851; GFX9-NEXT:    v_add_f32_e32 v0, 1.0, v0852; GFX9-NEXT:  ; %bb.2: ; %end853; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]854; GFX9-NEXT:    s_setpc_b64 s[30:31]855;856; GFX11-LABEL: bitcast_v2f32_to_i64:857; GFX11:       ; %bb.0:858; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)859; GFX11-NEXT:    s_mov_b32 s0, exec_lo860; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v2861; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0862; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)863; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0864; GFX11-NEXT:  ; %bb.1: ; %cmp.true865; GFX11-NEXT:    v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0866; GFX11-NEXT:  ; %bb.2: ; %end867; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0868; GFX11-NEXT:    s_setpc_b64 s[30:31]869  %cmp = icmp eq i32 %b, 0870  br i1 %cmp, label %cmp.true, label %cmp.false871 872cmp.true:873  %a1 = fadd <2 x float> %a, splat (float 1.000000e+00)874  %a2 = bitcast <2 x float> %a1 to i64875  br label %end876 877cmp.false:878  %a3 = bitcast <2 x float> %a to i64879  br label %end880 881end:882  %phi = phi i64 [ %a2, %cmp.true ], [ %a3, %cmp.false ]883  ret i64 %phi884}885 886define inreg i64 @bitcast_v2f32_to_i64_scalar(<2 x float> inreg %a, i32 inreg %b) {887; SI-LABEL: bitcast_v2f32_to_i64_scalar:888; SI:       ; %bb.0:889; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)890; SI-NEXT:    s_cmp_lg_u32 s18, 0891; SI-NEXT:    s_cbranch_scc0 .LBB11_3892; SI-NEXT:  ; %bb.1: ; %cmp.false893; SI-NEXT:    s_cbranch_execnz .LBB11_4894; SI-NEXT:  .LBB11_2: ; %cmp.true895; SI-NEXT:    v_add_f32_e64 v1, s17, 1.0896; SI-NEXT:    v_add_f32_e64 v0, s16, 1.0897; SI-NEXT:    s_setpc_b64 s[30:31]898; SI-NEXT:  .LBB11_3:899; SI-NEXT:    s_branch .LBB11_2900; SI-NEXT:  .LBB11_4:901; SI-NEXT:    v_mov_b32_e32 v0, s16902; SI-NEXT:    v_mov_b32_e32 v1, s17903; SI-NEXT:    s_setpc_b64 s[30:31]904;905; VI-LABEL: bitcast_v2f32_to_i64_scalar:906; VI:       ; %bb.0:907; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)908; VI-NEXT:    s_cmp_lg_u32 s18, 0909; VI-NEXT:    s_cbranch_scc0 .LBB11_3910; VI-NEXT:  ; %bb.1: ; %cmp.false911; VI-NEXT:    s_cbranch_execnz .LBB11_4912; VI-NEXT:  .LBB11_2: ; %cmp.true913; VI-NEXT:    v_add_f32_e64 v1, s17, 1.0914; VI-NEXT:    v_add_f32_e64 v0, s16, 1.0915; VI-NEXT:    s_setpc_b64 s[30:31]916; VI-NEXT:  .LBB11_3:917; VI-NEXT:    s_branch .LBB11_2918; VI-NEXT:  .LBB11_4:919; VI-NEXT:    v_mov_b32_e32 v0, s16920; VI-NEXT:    v_mov_b32_e32 v1, s17921; VI-NEXT:    s_setpc_b64 s[30:31]922;923; GFX9-LABEL: bitcast_v2f32_to_i64_scalar:924; GFX9:       ; %bb.0:925; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)926; GFX9-NEXT:    s_cmp_lg_u32 s18, 0927; GFX9-NEXT:    s_cbranch_scc0 .LBB11_3928; GFX9-NEXT:  ; %bb.1: ; %cmp.false929; GFX9-NEXT:    s_cbranch_execnz .LBB11_4930; GFX9-NEXT:  .LBB11_2: ; %cmp.true931; GFX9-NEXT:    v_add_f32_e64 v1, s17, 1.0932; GFX9-NEXT:    v_add_f32_e64 v0, s16, 1.0933; GFX9-NEXT:    s_setpc_b64 s[30:31]934; GFX9-NEXT:  .LBB11_3:935; GFX9-NEXT:    s_branch .LBB11_2936; GFX9-NEXT:  .LBB11_4:937; GFX9-NEXT:    v_mov_b32_e32 v0, s16938; GFX9-NEXT:    v_mov_b32_e32 v1, s17939; GFX9-NEXT:    s_setpc_b64 s[30:31]940;941; GFX11-LABEL: bitcast_v2f32_to_i64_scalar:942; GFX11:       ; %bb.0:943; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)944; GFX11-NEXT:    s_cmp_lg_u32 s2, 0945; GFX11-NEXT:    s_mov_b32 s2, 0946; GFX11-NEXT:    s_cbranch_scc0 .LBB11_3947; GFX11-NEXT:  ; %bb.1: ; %Flow948; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s2949; GFX11-NEXT:    s_cbranch_vccnz .LBB11_4950; GFX11-NEXT:  .LBB11_2: ; %cmp.true951; GFX11-NEXT:    v_add_f32_e64 v1, s1, 1.0952; GFX11-NEXT:    v_add_f32_e64 v0, s0, 1.0953; GFX11-NEXT:    s_setpc_b64 s[30:31]954; GFX11-NEXT:  .LBB11_3:955; GFX11-NEXT:    s_branch .LBB11_2956; GFX11-NEXT:  .LBB11_4:957; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1958; GFX11-NEXT:    s_setpc_b64 s[30:31]959  %cmp = icmp eq i32 %b, 0960  br i1 %cmp, label %cmp.true, label %cmp.false961 962cmp.true:963  %a1 = fadd <2 x float> %a, splat (float 1.000000e+00)964  %a2 = bitcast <2 x float> %a1 to i64965  br label %end966 967cmp.false:968  %a3 = bitcast <2 x float> %a to i64969  br label %end970 971end:972  %phi = phi i64 [ %a2, %cmp.true ], [ %a3, %cmp.false ]973  ret i64 %phi974}975 976define <4 x i16> @bitcast_i64_to_v4i16(i64 %a, i32 %b) {977; SI-LABEL: bitcast_i64_to_v4i16:978; SI:       ; %bb.0:979; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)980; SI-NEXT:    v_mov_b32_e32 v4, v1981; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2982; SI-NEXT:    ; implicit-def: $vgpr1983; SI-NEXT:    ; implicit-def: $vgpr3984; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc985; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]986; SI-NEXT:  ; %bb.1: ; %cmp.false987; SI-NEXT:    v_alignbit_b32 v1, v4, v0, 16988; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v4989; SI-NEXT:  ; %bb.2: ; %Flow990; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]991; SI-NEXT:  ; %bb.3: ; %cmp.true992; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v0993; SI-NEXT:    v_addc_u32_e32 v4, vcc, 0, v4, vcc994; SI-NEXT:    v_alignbit_b32 v1, v4, v0, 16995; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v4996; SI-NEXT:  ; %bb.4: ; %end997; SI-NEXT:    s_or_b64 exec, exec, s[4:5]998; SI-NEXT:    v_mov_b32_e32 v2, v4999; SI-NEXT:    s_setpc_b64 s[30:31]1000;1001; VI-LABEL: bitcast_i64_to_v4i16:1002; VI:       ; %bb.0:1003; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1004; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v21005; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc1006; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]1007; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1008; VI-NEXT:  ; %bb.1: ; %cmp.true1009; VI-NEXT:    v_add_u32_e32 v0, vcc, 3, v01010; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc1011; VI-NEXT:  ; %bb.2: ; %end1012; VI-NEXT:    s_or_b64 exec, exec, s[4:5]1013; VI-NEXT:    s_setpc_b64 s[30:31]1014;1015; GFX9-LABEL: bitcast_i64_to_v4i16:1016; GFX9:       ; %bb.0:1017; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1018; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v21019; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc1020; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]1021; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1022; GFX9-NEXT:  ; %bb.1: ; %cmp.true1023; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, 3, v01024; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc1025; GFX9-NEXT:  ; %bb.2: ; %end1026; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]1027; GFX9-NEXT:    s_setpc_b64 s[30:31]1028;1029; GFX11-LABEL: bitcast_i64_to_v4i16:1030; GFX11:       ; %bb.0:1031; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1032; GFX11-NEXT:    s_mov_b32 s0, exec_lo1033; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v21034; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s01035; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)1036; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s01037; GFX11-NEXT:  ; %bb.1: ; %cmp.true1038; GFX11-NEXT:    v_add_co_u32 v0, vcc_lo, v0, 31039; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)1040; GFX11-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo1041; GFX11-NEXT:  ; %bb.2: ; %end1042; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s01043; GFX11-NEXT:    s_setpc_b64 s[30:31]1044  %cmp = icmp eq i32 %b, 01045  br i1 %cmp, label %cmp.true, label %cmp.false1046 1047cmp.true:1048  %a1 = add i64 %a, 31049  %a2 = bitcast i64 %a1 to <4 x i16>1050  br label %end1051 1052cmp.false:1053  %a3 = bitcast i64 %a to <4 x i16>1054  br label %end1055 1056end:1057  %phi = phi <4 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]1058  ret <4 x i16> %phi1059}1060 1061define inreg <4 x i16> @bitcast_i64_to_v4i16_scalar(i64 inreg %a, i32 inreg %b) {1062; SI-LABEL: bitcast_i64_to_v4i16_scalar:1063; SI:       ; %bb.0:1064; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1065; SI-NEXT:    s_cmp_lg_u32 s18, 01066; SI-NEXT:    s_cbranch_scc0 .LBB13_41067; SI-NEXT:  ; %bb.1: ; %cmp.false1068; SI-NEXT:    s_lshr_b32 s8, s17, 161069; SI-NEXT:    s_lshr_b64 s[4:5], s[16:17], 161070; SI-NEXT:    s_cbranch_execnz .LBB13_31071; SI-NEXT:  .LBB13_2: ; %cmp.true1072; SI-NEXT:    s_add_u32 s16, s16, 31073; SI-NEXT:    s_addc_u32 s17, s17, 01074; SI-NEXT:    s_lshr_b32 s8, s17, 161075; SI-NEXT:    s_lshr_b64 s[4:5], s[16:17], 161076; SI-NEXT:  .LBB13_3: ; %end1077; SI-NEXT:    v_mov_b32_e32 v0, s161078; SI-NEXT:    v_mov_b32_e32 v1, s41079; SI-NEXT:    v_mov_b32_e32 v2, s171080; SI-NEXT:    v_mov_b32_e32 v3, s81081; SI-NEXT:    s_setpc_b64 s[30:31]1082; SI-NEXT:  .LBB13_4:1083; SI-NEXT:    ; implicit-def: $sgpr41084; SI-NEXT:    ; implicit-def: $sgpr81085; SI-NEXT:    s_branch .LBB13_21086;1087; VI-LABEL: bitcast_i64_to_v4i16_scalar:1088; VI:       ; %bb.0:1089; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1090; VI-NEXT:    s_cmp_lg_u32 s18, 01091; VI-NEXT:    s_cbranch_scc0 .LBB13_41092; VI-NEXT:  ; %bb.1: ; %cmp.false1093; VI-NEXT:    s_cbranch_execnz .LBB13_31094; VI-NEXT:  .LBB13_2: ; %cmp.true1095; VI-NEXT:    s_add_u32 s16, s16, 31096; VI-NEXT:    s_addc_u32 s17, s17, 01097; VI-NEXT:  .LBB13_3: ; %end1098; VI-NEXT:    v_mov_b32_e32 v0, s161099; VI-NEXT:    v_mov_b32_e32 v1, s171100; VI-NEXT:    s_setpc_b64 s[30:31]1101; VI-NEXT:  .LBB13_4:1102; VI-NEXT:    s_branch .LBB13_21103;1104; GFX9-LABEL: bitcast_i64_to_v4i16_scalar:1105; GFX9:       ; %bb.0:1106; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1107; GFX9-NEXT:    s_cmp_lg_u32 s18, 01108; GFX9-NEXT:    s_cbranch_scc0 .LBB13_41109; GFX9-NEXT:  ; %bb.1: ; %cmp.false1110; GFX9-NEXT:    s_cbranch_execnz .LBB13_31111; GFX9-NEXT:  .LBB13_2: ; %cmp.true1112; GFX9-NEXT:    s_add_u32 s16, s16, 31113; GFX9-NEXT:    s_addc_u32 s17, s17, 01114; GFX9-NEXT:  .LBB13_3: ; %end1115; GFX9-NEXT:    v_mov_b32_e32 v0, s161116; GFX9-NEXT:    v_mov_b32_e32 v1, s171117; GFX9-NEXT:    s_setpc_b64 s[30:31]1118; GFX9-NEXT:  .LBB13_4:1119; GFX9-NEXT:    s_branch .LBB13_21120;1121; GFX11-LABEL: bitcast_i64_to_v4i16_scalar:1122; GFX11:       ; %bb.0:1123; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1124; GFX11-NEXT:    s_cmp_lg_u32 s2, 01125; GFX11-NEXT:    s_mov_b32 s2, 01126; GFX11-NEXT:    s_cbranch_scc0 .LBB13_41127; GFX11-NEXT:  ; %bb.1: ; %Flow1128; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s21129; GFX11-NEXT:    s_cbranch_vccnz .LBB13_31130; GFX11-NEXT:  .LBB13_2: ; %cmp.true1131; GFX11-NEXT:    s_add_u32 s0, s0, 31132; GFX11-NEXT:    s_addc_u32 s1, s1, 01133; GFX11-NEXT:  .LBB13_3: ; %end1134; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)1135; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s11136; GFX11-NEXT:    s_setpc_b64 s[30:31]1137; GFX11-NEXT:  .LBB13_4:1138; GFX11-NEXT:    s_branch .LBB13_21139  %cmp = icmp eq i32 %b, 01140  br i1 %cmp, label %cmp.true, label %cmp.false1141 1142cmp.true:1143  %a1 = add i64 %a, 31144  %a2 = bitcast i64 %a1 to <4 x i16>1145  br label %end1146 1147cmp.false:1148  %a3 = bitcast i64 %a to <4 x i16>1149  br label %end1150 1151end:1152  %phi = phi <4 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]1153  ret <4 x i16> %phi1154}1155 1156define i64 @bitcast_v4i16_to_i64(<4 x i16> %a, i32 %b) {1157; SI-LABEL: bitcast_v4i16_to_i64:1158; SI:       ; %bb.0:1159; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1160; SI-NEXT:    v_mov_b32_e32 v5, v01161; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v41162; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v11163; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v31164; SI-NEXT:    ; implicit-def: $vgpr0_vgpr11165; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc1166; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]1167; SI-NEXT:    s_cbranch_execnz .LBB14_31168; SI-NEXT:  ; %bb.1: ; %Flow1169; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1170; SI-NEXT:    s_cbranch_execnz .LBB14_41171; SI-NEXT:  .LBB14_2: ; %end1172; SI-NEXT:    s_or_b64 exec, exec, s[4:5]1173; SI-NEXT:    s_setpc_b64 s[30:31]1174; SI-NEXT:  .LBB14_3: ; %cmp.false1175; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v51176; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v21177; SI-NEXT:    v_or_b32_e32 v0, v0, v41178; SI-NEXT:    v_or_b32_e32 v1, v1, v31179; SI-NEXT:    ; implicit-def: $vgpr51180; SI-NEXT:    ; implicit-def: $vgpr41181; SI-NEXT:    ; implicit-def: $vgpr21182; SI-NEXT:    ; implicit-def: $vgpr31183; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1184; SI-NEXT:    s_cbranch_execz .LBB14_21185; SI-NEXT:  .LBB14_4: ; %cmp.true1186; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v51187; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v21188; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v01189; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v11190; SI-NEXT:    v_or_b32_e32 v0, v4, v01191; SI-NEXT:    v_or_b32_e32 v1, v3, v11192; SI-NEXT:    v_add_i32_e32 v0, vcc, 0x30000, v01193; SI-NEXT:    v_add_i32_e32 v1, vcc, 0x30000, v11194; SI-NEXT:    s_or_b64 exec, exec, s[4:5]1195; SI-NEXT:    s_setpc_b64 s[30:31]1196;1197; VI-LABEL: bitcast_v4i16_to_i64:1198; VI:       ; %bb.0:1199; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1200; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v21201; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc1202; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]1203; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1204; VI-NEXT:  ; %bb.1: ; %cmp.true1205; VI-NEXT:    v_mov_b32_e32 v3, 31206; VI-NEXT:    v_add_u16_e32 v2, 3, v11207; VI-NEXT:    v_add_u16_sdwa v1, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1208; VI-NEXT:    v_or_b32_e32 v1, v2, v11209; VI-NEXT:    v_add_u16_e32 v2, 3, v01210; VI-NEXT:    v_add_u16_sdwa v0, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1211; VI-NEXT:    v_or_b32_e32 v0, v2, v01212; VI-NEXT:  ; %bb.2: ; %end1213; VI-NEXT:    s_or_b64 exec, exec, s[4:5]1214; VI-NEXT:    s_setpc_b64 s[30:31]1215;1216; GFX9-LABEL: bitcast_v4i16_to_i64:1217; GFX9:       ; %bb.0:1218; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1219; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v21220; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc1221; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]1222; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1223; GFX9-NEXT:  ; %bb.1: ; %cmp.true1224; GFX9-NEXT:    v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]1225; GFX9-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]1226; GFX9-NEXT:  ; %bb.2: ; %end1227; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]1228; GFX9-NEXT:    s_setpc_b64 s[30:31]1229;1230; GFX11-LABEL: bitcast_v4i16_to_i64:1231; GFX11:       ; %bb.0:1232; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1233; GFX11-NEXT:    s_mov_b32 s0, exec_lo1234; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v21235; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s01236; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)1237; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s01238; GFX11-NEXT:  ; %bb.1: ; %cmp.true1239; GFX11-NEXT:    v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]1240; GFX11-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]1241; GFX11-NEXT:  ; %bb.2: ; %end1242; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s01243; GFX11-NEXT:    s_setpc_b64 s[30:31]1244  %cmp = icmp eq i32 %b, 01245  br i1 %cmp, label %cmp.true, label %cmp.false1246 1247cmp.true:1248  %a1 = add <4 x i16> %a, splat (i16 3)1249  %a2 = bitcast <4 x i16> %a1 to i641250  br label %end1251 1252cmp.false:1253  %a3 = bitcast <4 x i16> %a to i641254  br label %end1255 1256end:1257  %phi = phi i64 [ %a2, %cmp.true ], [ %a3, %cmp.false ]1258  ret i64 %phi1259}1260 1261define inreg i64 @bitcast_v4i16_to_i64_scalar(<4 x i16> inreg %a, i32 inreg %b) {1262; SI-LABEL: bitcast_v4i16_to_i64_scalar:1263; SI:       ; %bb.0:1264; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1265; SI-NEXT:    s_cmp_lg_u32 s20, 01266; SI-NEXT:    s_cbranch_scc0 .LBB15_41267; SI-NEXT:  ; %bb.1: ; %cmp.false1268; SI-NEXT:    s_and_b32 s4, s16, 0xffff1269; SI-NEXT:    s_lshl_b32 s5, s17, 161270; SI-NEXT:    s_or_b32 s4, s4, s51271; SI-NEXT:    s_and_b32 s5, s18, 0xffff1272; SI-NEXT:    s_lshl_b32 s6, s19, 161273; SI-NEXT:    s_or_b32 s5, s5, s61274; SI-NEXT:    s_cbranch_execnz .LBB15_31275; SI-NEXT:  .LBB15_2: ; %cmp.true1276; SI-NEXT:    s_add_i32 s16, s16, 31277; SI-NEXT:    s_and_b32 s4, s16, 0xffff1278; SI-NEXT:    s_lshl_b32 s5, s17, 161279; SI-NEXT:    s_add_i32 s18, s18, 31280; SI-NEXT:    s_or_b32 s4, s5, s41281; SI-NEXT:    s_and_b32 s5, s18, 0xffff1282; SI-NEXT:    s_lshl_b32 s6, s19, 161283; SI-NEXT:    s_or_b32 s5, s6, s51284; SI-NEXT:    s_add_i32 s4, s4, 0x300001285; SI-NEXT:    s_add_i32 s5, s5, 0x300001286; SI-NEXT:  .LBB15_3: ; %end1287; SI-NEXT:    v_mov_b32_e32 v0, s41288; SI-NEXT:    v_mov_b32_e32 v1, s51289; SI-NEXT:    s_setpc_b64 s[30:31]1290; SI-NEXT:  .LBB15_4:1291; SI-NEXT:    ; implicit-def: $sgpr4_sgpr51292; SI-NEXT:    s_branch .LBB15_21293;1294; VI-LABEL: bitcast_v4i16_to_i64_scalar:1295; VI:       ; %bb.0:1296; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1297; VI-NEXT:    s_cmp_lg_u32 s18, 01298; VI-NEXT:    s_cbranch_scc0 .LBB15_41299; VI-NEXT:  ; %bb.1: ; %cmp.false1300; VI-NEXT:    s_cbranch_execnz .LBB15_31301; VI-NEXT:  .LBB15_2: ; %cmp.true1302; VI-NEXT:    s_add_i32 s5, s17, 31303; VI-NEXT:    s_and_b32 s4, s17, 0xffff00001304; VI-NEXT:    s_and_b32 s5, s5, 0xffff1305; VI-NEXT:    s_or_b32 s4, s4, s51306; VI-NEXT:    s_add_i32 s5, s16, 31307; VI-NEXT:    s_add_i32 s17, s4, 0x300001308; VI-NEXT:    s_and_b32 s4, s16, 0xffff00001309; VI-NEXT:    s_and_b32 s5, s5, 0xffff1310; VI-NEXT:    s_or_b32 s4, s4, s51311; VI-NEXT:    s_add_i32 s16, s4, 0x300001312; VI-NEXT:  .LBB15_3: ; %end1313; VI-NEXT:    v_mov_b32_e32 v0, s161314; VI-NEXT:    v_mov_b32_e32 v1, s171315; VI-NEXT:    s_setpc_b64 s[30:31]1316; VI-NEXT:  .LBB15_4:1317; VI-NEXT:    s_branch .LBB15_21318;1319; GFX9-LABEL: bitcast_v4i16_to_i64_scalar:1320; GFX9:       ; %bb.0:1321; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1322; GFX9-NEXT:    s_cmp_lg_u32 s18, 01323; GFX9-NEXT:    s_cbranch_scc0 .LBB15_31324; GFX9-NEXT:  ; %bb.1: ; %cmp.false1325; GFX9-NEXT:    s_cbranch_execnz .LBB15_41326; GFX9-NEXT:  .LBB15_2: ; %cmp.true1327; GFX9-NEXT:    v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]1328; GFX9-NEXT:    v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]1329; GFX9-NEXT:    s_setpc_b64 s[30:31]1330; GFX9-NEXT:  .LBB15_3:1331; GFX9-NEXT:    s_branch .LBB15_21332; GFX9-NEXT:  .LBB15_4:1333; GFX9-NEXT:    v_mov_b32_e32 v0, s161334; GFX9-NEXT:    v_mov_b32_e32 v1, s171335; GFX9-NEXT:    s_setpc_b64 s[30:31]1336;1337; GFX11-LABEL: bitcast_v4i16_to_i64_scalar:1338; GFX11:       ; %bb.0:1339; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1340; GFX11-NEXT:    s_cmp_lg_u32 s2, 01341; GFX11-NEXT:    s_mov_b32 s2, 01342; GFX11-NEXT:    s_cbranch_scc0 .LBB15_31343; GFX11-NEXT:  ; %bb.1: ; %Flow1344; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s21345; GFX11-NEXT:    s_cbranch_vccnz .LBB15_41346; GFX11-NEXT:  .LBB15_2: ; %cmp.true1347; GFX11-NEXT:    v_pk_add_u16 v1, s1, 3 op_sel_hi:[1,0]1348; GFX11-NEXT:    v_pk_add_u16 v0, s0, 3 op_sel_hi:[1,0]1349; GFX11-NEXT:    s_setpc_b64 s[30:31]1350; GFX11-NEXT:  .LBB15_3:1351; GFX11-NEXT:    s_branch .LBB15_21352; GFX11-NEXT:  .LBB15_4:1353; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s11354; GFX11-NEXT:    s_setpc_b64 s[30:31]1355  %cmp = icmp eq i32 %b, 01356  br i1 %cmp, label %cmp.true, label %cmp.false1357 1358cmp.true:1359  %a1 = add <4 x i16> %a, splat (i16 3)1360  %a2 = bitcast <4 x i16> %a1 to i641361  br label %end1362 1363cmp.false:1364  %a3 = bitcast <4 x i16> %a to i641365  br label %end1366 1367end:1368  %phi = phi i64 [ %a2, %cmp.true ], [ %a3, %cmp.false ]1369  ret i64 %phi1370}1371 1372define <4 x half> @bitcast_i64_to_v4f16(i64 %a, i32 %b) {1373; SI-LABEL: bitcast_i64_to_v4f16:1374; SI:       ; %bb.0:1375; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1376; SI-NEXT:    v_mov_b32_e32 v5, v11377; SI-NEXT:    v_mov_b32_e32 v4, v01378; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v21379; SI-NEXT:    ; implicit-def: $vgpr01380; SI-NEXT:    ; implicit-def: $vgpr11381; SI-NEXT:    ; implicit-def: $vgpr21382; SI-NEXT:    ; implicit-def: $vgpr31383; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc1384; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]1385; SI-NEXT:    s_cbranch_execnz .LBB16_31386; SI-NEXT:  ; %bb.1: ; %Flow1387; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1388; SI-NEXT:    s_cbranch_execnz .LBB16_41389; SI-NEXT:  .LBB16_2: ; %end1390; SI-NEXT:    s_or_b64 exec, exec, s[4:5]1391; SI-NEXT:    s_setpc_b64 s[30:31]1392; SI-NEXT:  .LBB16_3: ; %cmp.false1393; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v51394; SI-NEXT:    v_cvt_f32_f16_e32 v3, v01395; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v41396; SI-NEXT:    v_cvt_f32_f16_e32 v1, v01397; SI-NEXT:    v_cvt_f32_f16_e32 v2, v51398; SI-NEXT:    v_cvt_f32_f16_e32 v0, v41399; SI-NEXT:    ; implicit-def: $vgpr41400; SI-NEXT:    ; implicit-def: $vgpr51401; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1402; SI-NEXT:    s_cbranch_execz .LBB16_21403; SI-NEXT:  .LBB16_4: ; %cmp.true1404; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v41405; SI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v5, vcc1406; SI-NEXT:    v_lshrrev_b32_e32 v4, 16, v01407; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v11408; SI-NEXT:    v_cvt_f32_f16_e32 v2, v11409; SI-NEXT:    v_cvt_f32_f16_e32 v0, v01410; SI-NEXT:    v_cvt_f32_f16_e32 v3, v31411; SI-NEXT:    v_cvt_f32_f16_e32 v1, v41412; SI-NEXT:    s_or_b64 exec, exec, s[4:5]1413; SI-NEXT:    s_setpc_b64 s[30:31]1414;1415; VI-LABEL: bitcast_i64_to_v4f16:1416; VI:       ; %bb.0:1417; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1418; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v21419; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc1420; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]1421; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1422; VI-NEXT:  ; %bb.1: ; %cmp.true1423; VI-NEXT:    v_add_u32_e32 v0, vcc, 3, v01424; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc1425; VI-NEXT:  ; %bb.2: ; %end1426; VI-NEXT:    s_or_b64 exec, exec, s[4:5]1427; VI-NEXT:    s_setpc_b64 s[30:31]1428;1429; GFX9-LABEL: bitcast_i64_to_v4f16:1430; GFX9:       ; %bb.0:1431; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1432; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v21433; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc1434; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]1435; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1436; GFX9-NEXT:  ; %bb.1: ; %cmp.true1437; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, 3, v01438; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc1439; GFX9-NEXT:  ; %bb.2: ; %end1440; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]1441; GFX9-NEXT:    s_setpc_b64 s[30:31]1442;1443; GFX11-LABEL: bitcast_i64_to_v4f16:1444; GFX11:       ; %bb.0:1445; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1446; GFX11-NEXT:    s_mov_b32 s0, exec_lo1447; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v21448; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s01449; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)1450; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s01451; GFX11-NEXT:  ; %bb.1: ; %cmp.true1452; GFX11-NEXT:    v_add_co_u32 v0, vcc_lo, v0, 31453; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)1454; GFX11-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo1455; GFX11-NEXT:  ; %bb.2: ; %end1456; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s01457; GFX11-NEXT:    s_setpc_b64 s[30:31]1458  %cmp = icmp eq i32 %b, 01459  br i1 %cmp, label %cmp.true, label %cmp.false1460 1461cmp.true:1462  %a1 = add i64 %a, 31463  %a2 = bitcast i64 %a1 to <4 x half>1464  br label %end1465 1466cmp.false:1467  %a3 = bitcast i64 %a to <4 x half>1468  br label %end1469 1470end:1471  %phi = phi <4 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]1472  ret <4 x half> %phi1473}1474 1475define inreg <4 x half> @bitcast_i64_to_v4f16_scalar(i64 inreg %a, i32 inreg %b) {1476; SI-LABEL: bitcast_i64_to_v4f16_scalar:1477; SI:       ; %bb.0:1478; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1479; SI-NEXT:    s_cmp_lg_u32 s18, 01480; SI-NEXT:    s_cbranch_scc0 .LBB17_41481; SI-NEXT:  ; %bb.1: ; %cmp.false1482; SI-NEXT:    s_lshr_b32 s4, s17, 161483; SI-NEXT:    v_cvt_f32_f16_e32 v3, s41484; SI-NEXT:    s_lshr_b32 s4, s16, 161485; SI-NEXT:    v_cvt_f32_f16_e32 v1, s41486; SI-NEXT:    v_cvt_f32_f16_e32 v2, s171487; SI-NEXT:    v_cvt_f32_f16_e32 v0, s161488; SI-NEXT:    s_cbranch_execnz .LBB17_31489; SI-NEXT:  .LBB17_2: ; %cmp.true1490; SI-NEXT:    s_add_u32 s4, s16, 31491; SI-NEXT:    s_addc_u32 s5, s17, 01492; SI-NEXT:    s_lshr_b32 s6, s4, 161493; SI-NEXT:    s_lshr_b32 s7, s5, 161494; SI-NEXT:    v_cvt_f32_f16_e32 v2, s51495; SI-NEXT:    v_cvt_f32_f16_e32 v0, s41496; SI-NEXT:    v_cvt_f32_f16_e32 v3, s71497; SI-NEXT:    v_cvt_f32_f16_e32 v1, s61498; SI-NEXT:  .LBB17_3: ; %end1499; SI-NEXT:    s_setpc_b64 s[30:31]1500; SI-NEXT:  .LBB17_4:1501; SI-NEXT:    ; implicit-def: $vgpr01502; SI-NEXT:    ; implicit-def: $vgpr11503; SI-NEXT:    ; implicit-def: $vgpr21504; SI-NEXT:    ; implicit-def: $vgpr31505; SI-NEXT:    s_branch .LBB17_21506;1507; VI-LABEL: bitcast_i64_to_v4f16_scalar:1508; VI:       ; %bb.0:1509; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1510; VI-NEXT:    s_cmp_lg_u32 s18, 01511; VI-NEXT:    s_cbranch_scc0 .LBB17_41512; VI-NEXT:  ; %bb.1: ; %cmp.false1513; VI-NEXT:    s_cbranch_execnz .LBB17_31514; VI-NEXT:  .LBB17_2: ; %cmp.true1515; VI-NEXT:    s_add_u32 s16, s16, 31516; VI-NEXT:    s_addc_u32 s17, s17, 01517; VI-NEXT:  .LBB17_3: ; %end1518; VI-NEXT:    v_mov_b32_e32 v0, s161519; VI-NEXT:    v_mov_b32_e32 v1, s171520; VI-NEXT:    s_setpc_b64 s[30:31]1521; VI-NEXT:  .LBB17_4:1522; VI-NEXT:    s_branch .LBB17_21523;1524; GFX9-LABEL: bitcast_i64_to_v4f16_scalar:1525; GFX9:       ; %bb.0:1526; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1527; GFX9-NEXT:    s_cmp_lg_u32 s18, 01528; GFX9-NEXT:    s_cbranch_scc0 .LBB17_41529; GFX9-NEXT:  ; %bb.1: ; %cmp.false1530; GFX9-NEXT:    s_cbranch_execnz .LBB17_31531; GFX9-NEXT:  .LBB17_2: ; %cmp.true1532; GFX9-NEXT:    s_add_u32 s16, s16, 31533; GFX9-NEXT:    s_addc_u32 s17, s17, 01534; GFX9-NEXT:  .LBB17_3: ; %end1535; GFX9-NEXT:    v_mov_b32_e32 v0, s161536; GFX9-NEXT:    v_mov_b32_e32 v1, s171537; GFX9-NEXT:    s_setpc_b64 s[30:31]1538; GFX9-NEXT:  .LBB17_4:1539; GFX9-NEXT:    s_branch .LBB17_21540;1541; GFX11-LABEL: bitcast_i64_to_v4f16_scalar:1542; GFX11:       ; %bb.0:1543; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1544; GFX11-NEXT:    s_cmp_lg_u32 s2, 01545; GFX11-NEXT:    s_mov_b32 s2, 01546; GFX11-NEXT:    s_cbranch_scc0 .LBB17_41547; GFX11-NEXT:  ; %bb.1: ; %Flow1548; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s21549; GFX11-NEXT:    s_cbranch_vccnz .LBB17_31550; GFX11-NEXT:  .LBB17_2: ; %cmp.true1551; GFX11-NEXT:    s_add_u32 s0, s0, 31552; GFX11-NEXT:    s_addc_u32 s1, s1, 01553; GFX11-NEXT:  .LBB17_3: ; %end1554; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)1555; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s11556; GFX11-NEXT:    s_setpc_b64 s[30:31]1557; GFX11-NEXT:  .LBB17_4:1558; GFX11-NEXT:    s_branch .LBB17_21559  %cmp = icmp eq i32 %b, 01560  br i1 %cmp, label %cmp.true, label %cmp.false1561 1562cmp.true:1563  %a1 = add i64 %a, 31564  %a2 = bitcast i64 %a1 to <4 x half>1565  br label %end1566 1567cmp.false:1568  %a3 = bitcast i64 %a to <4 x half>1569  br label %end1570 1571end:1572  %phi = phi <4 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]1573  ret <4 x half> %phi1574}1575 1576define i64 @bitcast_v4f16_to_i64(<4 x half> %a, i32 %b) {1577; SI-LABEL: bitcast_v4f16_to_i64:1578; SI:       ; %bb.0:1579; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1580; SI-NEXT:    v_cvt_f16_f32_e32 v6, v11581; SI-NEXT:    v_cvt_f16_f32_e32 v5, v01582; SI-NEXT:    v_cvt_f16_f32_e32 v3, v31583; SI-NEXT:    v_cvt_f16_f32_e32 v2, v21584; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v41585; SI-NEXT:    ; implicit-def: $vgpr0_vgpr11586; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc1587; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]1588; SI-NEXT:    s_cbranch_execnz .LBB18_31589; SI-NEXT:  ; %bb.1: ; %Flow1590; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1591; SI-NEXT:    s_cbranch_execnz .LBB18_41592; SI-NEXT:  .LBB18_2: ; %end1593; SI-NEXT:    s_or_b64 exec, exec, s[4:5]1594; SI-NEXT:    s_setpc_b64 s[30:31]1595; SI-NEXT:  .LBB18_3: ; %cmp.false1596; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v61597; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v31598; SI-NEXT:    v_or_b32_e32 v0, v5, v01599; SI-NEXT:    v_or_b32_e32 v1, v2, v11600; SI-NEXT:    ; implicit-def: $vgpr61601; SI-NEXT:    ; implicit-def: $vgpr51602; SI-NEXT:    ; implicit-def: $vgpr31603; SI-NEXT:    ; implicit-def: $vgpr21604; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1605; SI-NEXT:    s_cbranch_execz .LBB18_21606; SI-NEXT:  .LBB18_4: ; %cmp.true1607; SI-NEXT:    v_cvt_f32_f16_e32 v0, v61608; SI-NEXT:    v_cvt_f32_f16_e32 v1, v51609; SI-NEXT:    v_cvt_f32_f16_e32 v3, v31610; SI-NEXT:    v_cvt_f32_f16_e32 v2, v21611; SI-NEXT:    v_add_f32_e32 v0, 0x38000000, v01612; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v11613; SI-NEXT:    v_cvt_f16_f32_e32 v0, v01614; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v31615; SI-NEXT:    v_cvt_f16_f32_e32 v1, v11616; SI-NEXT:    v_cvt_f16_f32_e32 v3, v31617; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v21618; SI-NEXT:    v_cvt_f16_f32_e32 v2, v21619; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v01620; SI-NEXT:    v_or_b32_e32 v0, v1, v01621; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v31622; SI-NEXT:    v_or_b32_e32 v1, v2, v11623; SI-NEXT:    s_or_b64 exec, exec, s[4:5]1624; SI-NEXT:    s_setpc_b64 s[30:31]1625;1626; VI-LABEL: bitcast_v4f16_to_i64:1627; VI:       ; %bb.0:1628; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1629; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v21630; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc1631; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]1632; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1633; VI-NEXT:  ; %bb.1: ; %cmp.true1634; VI-NEXT:    v_mov_b32_e32 v2, 0x2001635; VI-NEXT:    v_add_f16_sdwa v3, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1636; VI-NEXT:    v_add_f16_e32 v1, 0x200, v11637; VI-NEXT:    v_add_f16_sdwa v2, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1638; VI-NEXT:    v_add_f16_e32 v0, 0x200, v01639; VI-NEXT:    v_or_b32_e32 v1, v1, v31640; VI-NEXT:    v_or_b32_e32 v0, v0, v21641; VI-NEXT:  ; %bb.2: ; %end1642; VI-NEXT:    s_or_b64 exec, exec, s[4:5]1643; VI-NEXT:    s_setpc_b64 s[30:31]1644;1645; GFX9-LABEL: bitcast_v4f16_to_i64:1646; GFX9:       ; %bb.0:1647; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1648; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v21649; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc1650; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]1651; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1652; GFX9-NEXT:  ; %bb.1: ; %cmp.true1653; GFX9-NEXT:    s_movk_i32 s6, 0x2001654; GFX9-NEXT:    v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]1655; GFX9-NEXT:    v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]1656; GFX9-NEXT:  ; %bb.2: ; %end1657; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]1658; GFX9-NEXT:    s_setpc_b64 s[30:31]1659;1660; GFX11-LABEL: bitcast_v4f16_to_i64:1661; GFX11:       ; %bb.0:1662; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1663; GFX11-NEXT:    s_mov_b32 s0, exec_lo1664; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v21665; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s01666; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)1667; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s01668; GFX11-NEXT:  ; %bb.1: ; %cmp.true1669; GFX11-NEXT:    v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]1670; GFX11-NEXT:    v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]1671; GFX11-NEXT:  ; %bb.2: ; %end1672; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s01673; GFX11-NEXT:    s_setpc_b64 s[30:31]1674  %cmp = icmp eq i32 %b, 01675  br i1 %cmp, label %cmp.true, label %cmp.false1676 1677cmp.true:1678  %a1 = fadd <4 x half> %a, splat (half 0xH0200)1679  %a2 = bitcast <4 x half> %a1 to i641680  br label %end1681 1682cmp.false:1683  %a3 = bitcast <4 x half> %a to i641684  br label %end1685 1686end:1687  %phi = phi i64 [ %a2, %cmp.true ], [ %a3, %cmp.false ]1688  ret i64 %phi1689}1690 1691define inreg i64 @bitcast_v4f16_to_i64_scalar(<4 x half> inreg %a, i32 inreg %b) {1692; SI-LABEL: bitcast_v4f16_to_i64_scalar:1693; SI:       ; %bb.0:1694; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1695; SI-NEXT:    v_cvt_f16_f32_e32 v5, s171696; SI-NEXT:    v_cvt_f16_f32_e32 v4, s161697; SI-NEXT:    v_cvt_f16_f32_e32 v3, s191698; SI-NEXT:    v_cvt_f16_f32_e32 v2, s181699; SI-NEXT:    s_cmp_lg_u32 s20, 01700; SI-NEXT:    s_cbranch_scc0 .LBB19_41701; SI-NEXT:  ; %bb.1: ; %cmp.false1702; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v51703; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v31704; SI-NEXT:    v_or_b32_e32 v0, v4, v01705; SI-NEXT:    v_or_b32_e32 v1, v2, v11706; SI-NEXT:    s_cbranch_execnz .LBB19_31707; SI-NEXT:  .LBB19_2: ; %cmp.true1708; SI-NEXT:    v_cvt_f32_f16_e32 v0, v51709; SI-NEXT:    v_cvt_f32_f16_e32 v1, v41710; SI-NEXT:    v_cvt_f32_f16_e32 v3, v31711; SI-NEXT:    v_cvt_f32_f16_e32 v2, v21712; SI-NEXT:    v_add_f32_e32 v0, 0x38000000, v01713; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v11714; SI-NEXT:    v_cvt_f16_f32_e32 v0, v01715; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v31716; SI-NEXT:    v_cvt_f16_f32_e32 v1, v11717; SI-NEXT:    v_cvt_f16_f32_e32 v3, v31718; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v21719; SI-NEXT:    v_cvt_f16_f32_e32 v2, v21720; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v01721; SI-NEXT:    v_or_b32_e32 v0, v1, v01722; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v31723; SI-NEXT:    v_or_b32_e32 v1, v2, v11724; SI-NEXT:  .LBB19_3: ; %end1725; SI-NEXT:    s_setpc_b64 s[30:31]1726; SI-NEXT:  .LBB19_4:1727; SI-NEXT:    ; implicit-def: $vgpr0_vgpr11728; SI-NEXT:    s_branch .LBB19_21729;1730; VI-LABEL: bitcast_v4f16_to_i64_scalar:1731; VI:       ; %bb.0:1732; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1733; VI-NEXT:    s_cmp_lg_u32 s18, 01734; VI-NEXT:    s_cbranch_scc0 .LBB19_31735; VI-NEXT:  ; %bb.1: ; %cmp.false1736; VI-NEXT:    s_cbranch_execnz .LBB19_41737; VI-NEXT:  .LBB19_2: ; %cmp.true1738; VI-NEXT:    s_lshr_b32 s4, s17, 161739; VI-NEXT:    v_mov_b32_e32 v0, 0x2001740; VI-NEXT:    v_mov_b32_e32 v1, s41741; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD1742; VI-NEXT:    v_add_f16_e32 v2, s17, v01743; VI-NEXT:    s_lshr_b32 s4, s16, 161744; VI-NEXT:    v_or_b32_e32 v1, v2, v11745; VI-NEXT:    v_mov_b32_e32 v2, s41746; VI-NEXT:    v_add_f16_sdwa v2, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD1747; VI-NEXT:    v_add_f16_e32 v0, s16, v01748; VI-NEXT:    v_or_b32_e32 v0, v0, v21749; VI-NEXT:    s_setpc_b64 s[30:31]1750; VI-NEXT:  .LBB19_3:1751; VI-NEXT:    s_branch .LBB19_21752; VI-NEXT:  .LBB19_4:1753; VI-NEXT:    v_mov_b32_e32 v0, s161754; VI-NEXT:    v_mov_b32_e32 v1, s171755; VI-NEXT:    s_setpc_b64 s[30:31]1756;1757; GFX9-LABEL: bitcast_v4f16_to_i64_scalar:1758; GFX9:       ; %bb.0:1759; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1760; GFX9-NEXT:    s_cmp_lg_u32 s18, 01761; GFX9-NEXT:    s_cbranch_scc0 .LBB19_31762; GFX9-NEXT:  ; %bb.1: ; %cmp.false1763; GFX9-NEXT:    s_cbranch_execnz .LBB19_41764; GFX9-NEXT:  .LBB19_2: ; %cmp.true1765; GFX9-NEXT:    v_mov_b32_e32 v0, 0x2001766; GFX9-NEXT:    v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]1767; GFX9-NEXT:    v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]1768; GFX9-NEXT:    s_setpc_b64 s[30:31]1769; GFX9-NEXT:  .LBB19_3:1770; GFX9-NEXT:    s_branch .LBB19_21771; GFX9-NEXT:  .LBB19_4:1772; GFX9-NEXT:    v_mov_b32_e32 v0, s161773; GFX9-NEXT:    v_mov_b32_e32 v1, s171774; GFX9-NEXT:    s_setpc_b64 s[30:31]1775;1776; GFX11-LABEL: bitcast_v4f16_to_i64_scalar:1777; GFX11:       ; %bb.0:1778; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1779; GFX11-NEXT:    s_cmp_lg_u32 s2, 01780; GFX11-NEXT:    s_mov_b32 s2, 01781; GFX11-NEXT:    s_cbranch_scc0 .LBB19_31782; GFX11-NEXT:  ; %bb.1: ; %Flow1783; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s21784; GFX11-NEXT:    s_cbranch_vccnz .LBB19_41785; GFX11-NEXT:  .LBB19_2: ; %cmp.true1786; GFX11-NEXT:    v_pk_add_f16 v1, 0x200, s1 op_sel_hi:[0,1]1787; GFX11-NEXT:    v_pk_add_f16 v0, 0x200, s0 op_sel_hi:[0,1]1788; GFX11-NEXT:    s_setpc_b64 s[30:31]1789; GFX11-NEXT:  .LBB19_3:1790; GFX11-NEXT:    s_branch .LBB19_21791; GFX11-NEXT:  .LBB19_4:1792; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s11793; GFX11-NEXT:    s_setpc_b64 s[30:31]1794  %cmp = icmp eq i32 %b, 01795  br i1 %cmp, label %cmp.true, label %cmp.false1796 1797cmp.true:1798  %a1 = fadd <4 x half> %a, splat (half 0xH0200)1799  %a2 = bitcast <4 x half> %a1 to i641800  br label %end1801 1802cmp.false:1803  %a3 = bitcast <4 x half> %a to i641804  br label %end1805 1806end:1807  %phi = phi i64 [ %a2, %cmp.true ], [ %a3, %cmp.false ]1808  ret i64 %phi1809}1810 1811define <4 x bfloat> @bitcast_i64_to_v4bf16(i64 %a, i32 %b) {1812; SI-LABEL: bitcast_i64_to_v4bf16:1813; SI:       ; %bb.0:1814; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1815; SI-NEXT:    v_mov_b32_e32 v5, v11816; SI-NEXT:    v_mov_b32_e32 v4, v01817; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v21818; SI-NEXT:    ; implicit-def: $vgpr01819; SI-NEXT:    ; implicit-def: $vgpr11820; SI-NEXT:    ; implicit-def: $vgpr21821; SI-NEXT:    ; implicit-def: $vgpr31822; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc1823; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]1824; SI-NEXT:    s_cbranch_execnz .LBB20_31825; SI-NEXT:  ; %bb.1: ; %Flow1826; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1827; SI-NEXT:    s_cbranch_execnz .LBB20_41828; SI-NEXT:  .LBB20_2: ; %end1829; SI-NEXT:    s_or_b64 exec, exec, s[4:5]1830; SI-NEXT:    s_setpc_b64 s[30:31]1831; SI-NEXT:  .LBB20_3: ; %cmp.false1832; SI-NEXT:    v_and_b32_e32 v3, 0xffff0000, v51833; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v51834; SI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v41835; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v41836; SI-NEXT:    ; implicit-def: $vgpr41837; SI-NEXT:    ; implicit-def: $vgpr51838; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1839; SI-NEXT:    s_cbranch_execz .LBB20_21840; SI-NEXT:  .LBB20_4: ; %cmp.true1841; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v41842; SI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v5, vcc1843; SI-NEXT:    v_and_b32_e32 v3, 0xffff0000, v11844; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v11845; SI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v01846; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v01847; SI-NEXT:    s_or_b64 exec, exec, s[4:5]1848; SI-NEXT:    s_setpc_b64 s[30:31]1849;1850; VI-LABEL: bitcast_i64_to_v4bf16:1851; VI:       ; %bb.0:1852; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1853; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v21854; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc1855; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]1856; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1857; VI-NEXT:  ; %bb.1: ; %cmp.true1858; VI-NEXT:    v_add_u32_e32 v0, vcc, 3, v01859; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc1860; VI-NEXT:  ; %bb.2: ; %end1861; VI-NEXT:    s_or_b64 exec, exec, s[4:5]1862; VI-NEXT:    s_setpc_b64 s[30:31]1863;1864; GFX9-LABEL: bitcast_i64_to_v4bf16:1865; GFX9:       ; %bb.0:1866; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1867; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v21868; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc1869; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]1870; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1871; GFX9-NEXT:  ; %bb.1: ; %cmp.true1872; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, 3, v01873; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc1874; GFX9-NEXT:  ; %bb.2: ; %end1875; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]1876; GFX9-NEXT:    s_setpc_b64 s[30:31]1877;1878; GFX11-LABEL: bitcast_i64_to_v4bf16:1879; GFX11:       ; %bb.0:1880; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1881; GFX11-NEXT:    s_mov_b32 s0, exec_lo1882; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v21883; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s01884; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)1885; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s01886; GFX11-NEXT:  ; %bb.1: ; %cmp.true1887; GFX11-NEXT:    v_add_co_u32 v0, vcc_lo, v0, 31888; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)1889; GFX11-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo1890; GFX11-NEXT:  ; %bb.2: ; %end1891; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s01892; GFX11-NEXT:    s_setpc_b64 s[30:31]1893  %cmp = icmp eq i32 %b, 01894  br i1 %cmp, label %cmp.true, label %cmp.false1895 1896cmp.true:1897  %a1 = add i64 %a, 31898  %a2 = bitcast i64 %a1 to <4 x bfloat>1899  br label %end1900 1901cmp.false:1902  %a3 = bitcast i64 %a to <4 x bfloat>1903  br label %end1904 1905end:1906  %phi = phi <4 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ]1907  ret <4 x bfloat> %phi1908}1909 1910define inreg <4 x bfloat> @bitcast_i64_to_v4bf16_scalar(i64 inreg %a, i32 inreg %b) {1911; SI-LABEL: bitcast_i64_to_v4bf16_scalar:1912; SI:       ; %bb.0:1913; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1914; SI-NEXT:    s_cmp_lg_u32 s18, 01915; SI-NEXT:    s_cbranch_scc0 .LBB21_41916; SI-NEXT:  ; %bb.1: ; %cmp.false1917; SI-NEXT:    s_and_b32 s6, s17, 0xffff00001918; SI-NEXT:    s_lshl_b32 s7, s17, 161919; SI-NEXT:    s_and_b32 s8, s16, 0xffff00001920; SI-NEXT:    s_lshl_b32 s9, s16, 161921; SI-NEXT:    s_cbranch_execnz .LBB21_31922; SI-NEXT:  .LBB21_2: ; %cmp.true1923; SI-NEXT:    s_add_u32 s4, s16, 31924; SI-NEXT:    s_addc_u32 s5, s17, 01925; SI-NEXT:    s_and_b32 s6, s5, 0xffff00001926; SI-NEXT:    s_lshl_b32 s7, s5, 161927; SI-NEXT:    s_and_b32 s8, s4, 0xffff00001928; SI-NEXT:    s_lshl_b32 s9, s4, 161929; SI-NEXT:  .LBB21_3: ; %end1930; SI-NEXT:    v_mov_b32_e32 v0, s91931; SI-NEXT:    v_mov_b32_e32 v1, s81932; SI-NEXT:    v_mov_b32_e32 v2, s71933; SI-NEXT:    v_mov_b32_e32 v3, s61934; SI-NEXT:    s_setpc_b64 s[30:31]1935; SI-NEXT:  .LBB21_4:1936; SI-NEXT:    ; implicit-def: $sgpr91937; SI-NEXT:    ; implicit-def: $sgpr81938; SI-NEXT:    ; implicit-def: $sgpr71939; SI-NEXT:    ; implicit-def: $sgpr61940; SI-NEXT:    s_branch .LBB21_21941;1942; VI-LABEL: bitcast_i64_to_v4bf16_scalar:1943; VI:       ; %bb.0:1944; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1945; VI-NEXT:    s_cmp_lg_u32 s18, 01946; VI-NEXT:    s_cbranch_scc0 .LBB21_41947; VI-NEXT:  ; %bb.1: ; %cmp.false1948; VI-NEXT:    s_cbranch_execnz .LBB21_31949; VI-NEXT:  .LBB21_2: ; %cmp.true1950; VI-NEXT:    s_add_u32 s16, s16, 31951; VI-NEXT:    s_addc_u32 s17, s17, 01952; VI-NEXT:  .LBB21_3: ; %end1953; VI-NEXT:    v_mov_b32_e32 v0, s161954; VI-NEXT:    v_mov_b32_e32 v1, s171955; VI-NEXT:    s_setpc_b64 s[30:31]1956; VI-NEXT:  .LBB21_4:1957; VI-NEXT:    s_branch .LBB21_21958;1959; GFX9-LABEL: bitcast_i64_to_v4bf16_scalar:1960; GFX9:       ; %bb.0:1961; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1962; GFX9-NEXT:    s_cmp_lg_u32 s18, 01963; GFX9-NEXT:    s_cbranch_scc0 .LBB21_41964; GFX9-NEXT:  ; %bb.1: ; %cmp.false1965; GFX9-NEXT:    s_cbranch_execnz .LBB21_31966; GFX9-NEXT:  .LBB21_2: ; %cmp.true1967; GFX9-NEXT:    s_add_u32 s16, s16, 31968; GFX9-NEXT:    s_addc_u32 s17, s17, 01969; GFX9-NEXT:  .LBB21_3: ; %end1970; GFX9-NEXT:    v_mov_b32_e32 v0, s161971; GFX9-NEXT:    v_mov_b32_e32 v1, s171972; GFX9-NEXT:    s_setpc_b64 s[30:31]1973; GFX9-NEXT:  .LBB21_4:1974; GFX9-NEXT:    s_branch .LBB21_21975;1976; GFX11-LABEL: bitcast_i64_to_v4bf16_scalar:1977; GFX11:       ; %bb.0:1978; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1979; GFX11-NEXT:    s_cmp_lg_u32 s2, 01980; GFX11-NEXT:    s_mov_b32 s2, 01981; GFX11-NEXT:    s_cbranch_scc0 .LBB21_41982; GFX11-NEXT:  ; %bb.1: ; %Flow1983; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s21984; GFX11-NEXT:    s_cbranch_vccnz .LBB21_31985; GFX11-NEXT:  .LBB21_2: ; %cmp.true1986; GFX11-NEXT:    s_add_u32 s0, s0, 31987; GFX11-NEXT:    s_addc_u32 s1, s1, 01988; GFX11-NEXT:  .LBB21_3: ; %end1989; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)1990; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s11991; GFX11-NEXT:    s_setpc_b64 s[30:31]1992; GFX11-NEXT:  .LBB21_4:1993; GFX11-NEXT:    s_branch .LBB21_21994  %cmp = icmp eq i32 %b, 01995  br i1 %cmp, label %cmp.true, label %cmp.false1996 1997cmp.true:1998  %a1 = add i64 %a, 31999  %a2 = bitcast i64 %a1 to <4 x bfloat>2000  br label %end2001 2002cmp.false:2003  %a3 = bitcast i64 %a to <4 x bfloat>2004  br label %end2005 2006end:2007  %phi = phi <4 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ]2008  ret <4 x bfloat> %phi2009}2010 2011define i64 @bitcast_v4bf16_to_i64(<4 x bfloat> %a, i32 %b) {2012; SI-LABEL: bitcast_v4bf16_to_i64:2013; SI:       ; %bb.0:2014; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2015; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v42016; SI-NEXT:    v_mul_f32_e32 v4, 1.0, v12017; SI-NEXT:    v_mul_f32_e32 v5, 1.0, v02018; SI-NEXT:    v_mul_f32_e32 v3, 1.0, v32019; SI-NEXT:    v_mul_f32_e32 v2, 1.0, v22020; SI-NEXT:    ; implicit-def: $vgpr0_vgpr12021; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc2022; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]2023; SI-NEXT:    s_cbranch_execnz .LBB22_32024; SI-NEXT:  ; %bb.1: ; %Flow2025; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]2026; SI-NEXT:    s_cbranch_execnz .LBB22_42027; SI-NEXT:  .LBB22_2: ; %end2028; SI-NEXT:    s_or_b64 exec, exec, s[4:5]2029; SI-NEXT:    s_setpc_b64 s[30:31]2030; SI-NEXT:  .LBB22_3: ; %cmp.false2031; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v42032; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v32033; SI-NEXT:    v_alignbit_b32 v0, v0, v5, 162034; SI-NEXT:    v_alignbit_b32 v1, v1, v2, 162035; SI-NEXT:    ; implicit-def: $vgpr52036; SI-NEXT:    ; implicit-def: $vgpr42037; SI-NEXT:    ; implicit-def: $vgpr22038; SI-NEXT:    ; implicit-def: $vgpr32039; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]2040; SI-NEXT:    s_cbranch_execz .LBB22_22041; SI-NEXT:  .LBB22_4: ; %cmp.true2042; SI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v42043; SI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v52044; SI-NEXT:    v_add_f32_e32 v1, 0x40c00000, v12045; SI-NEXT:    v_add_f32_e32 v0, 0x40c00000, v02046; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v12047; SI-NEXT:    v_alignbit_b32 v0, v1, v0, 162048; SI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v22049; SI-NEXT:    v_and_b32_e32 v2, 0xffff0000, v32050; SI-NEXT:    v_add_f32_e32 v2, 0x40c00000, v22051; SI-NEXT:    v_add_f32_e32 v1, 0x40c00000, v12052; SI-NEXT:    v_lshrrev_b32_e32 v2, 16, v22053; SI-NEXT:    v_alignbit_b32 v1, v2, v1, 162054; SI-NEXT:    s_or_b64 exec, exec, s[4:5]2055; SI-NEXT:    s_setpc_b64 s[30:31]2056;2057; VI-LABEL: bitcast_v4bf16_to_i64:2058; VI:       ; %bb.0:2059; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2060; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v22061; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc2062; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]2063; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]2064; VI-NEXT:    s_cbranch_execz .LBB22_22065; VI-NEXT:  ; %bb.1: ; %cmp.true2066; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v12067; VI-NEXT:    v_add_f32_e32 v2, 0x40c00000, v22068; VI-NEXT:    v_bfe_u32 v3, v2, 16, 12069; VI-NEXT:    v_add_u32_e32 v3, vcc, v3, v22070; VI-NEXT:    v_add_u32_e32 v3, vcc, 0x7fff, v32071; VI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v12072; VI-NEXT:    v_or_b32_e32 v4, 0x400000, v22073; VI-NEXT:    v_cmp_u_f32_e32 vcc, v2, v22074; VI-NEXT:    v_add_f32_e32 v1, 0x40c00000, v12075; VI-NEXT:    v_cndmask_b32_e32 v2, v3, v4, vcc2076; VI-NEXT:    v_bfe_u32 v3, v1, 16, 12077; VI-NEXT:    s_movk_i32 s6, 0x7fff2078; VI-NEXT:    v_add_u32_e32 v3, vcc, v3, v12079; VI-NEXT:    v_add_u32_e32 v3, vcc, s6, v32080; VI-NEXT:    v_or_b32_e32 v4, 0x400000, v12081; VI-NEXT:    v_cmp_u_f32_e32 vcc, v1, v12082; VI-NEXT:    v_cndmask_b32_e32 v1, v3, v4, vcc2083; VI-NEXT:    v_lshrrev_b32_e32 v1, 16, v12084; VI-NEXT:    v_alignbit_b32 v1, v1, v2, 162085; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v02086; VI-NEXT:    v_add_f32_e32 v2, 0x40c00000, v22087; VI-NEXT:    v_bfe_u32 v3, v2, 16, 12088; VI-NEXT:    v_add_u32_e32 v3, vcc, v3, v22089; VI-NEXT:    v_add_u32_e32 v3, vcc, s6, v32090; VI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v02091; VI-NEXT:    v_or_b32_e32 v4, 0x400000, v22092; VI-NEXT:    v_cmp_u_f32_e32 vcc, v2, v22093; VI-NEXT:    v_add_f32_e32 v0, 0x40c00000, v02094; VI-NEXT:    v_cndmask_b32_e32 v2, v3, v4, vcc2095; VI-NEXT:    v_bfe_u32 v3, v0, 16, 12096; VI-NEXT:    v_add_u32_e32 v3, vcc, v3, v02097; VI-NEXT:    v_add_u32_e32 v3, vcc, 0x7fff, v32098; VI-NEXT:    v_or_b32_e32 v4, 0x400000, v02099; VI-NEXT:    v_cmp_u_f32_e32 vcc, v0, v02100; VI-NEXT:    v_cndmask_b32_e32 v0, v3, v4, vcc2101; VI-NEXT:    v_lshrrev_b32_e32 v0, 16, v02102; VI-NEXT:    v_alignbit_b32 v0, v0, v2, 162103; VI-NEXT:  .LBB22_2: ; %end2104; VI-NEXT:    s_or_b64 exec, exec, s[4:5]2105; VI-NEXT:    s_setpc_b64 s[30:31]2106;2107; GFX9-LABEL: bitcast_v4bf16_to_i64:2108; GFX9:       ; %bb.0:2109; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2110; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v22111; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc2112; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]2113; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]2114; GFX9-NEXT:    s_cbranch_execz .LBB22_22115; GFX9-NEXT:  ; %bb.1: ; %cmp.true2116; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 16, v02117; GFX9-NEXT:    v_add_f32_e32 v2, 0x40c00000, v22118; GFX9-NEXT:    v_bfe_u32 v3, v2, 16, 12119; GFX9-NEXT:    s_movk_i32 s6, 0x7fff2120; GFX9-NEXT:    v_and_b32_e32 v0, 0xffff0000, v02121; GFX9-NEXT:    v_add3_u32 v3, v3, v2, s62122; GFX9-NEXT:    v_or_b32_e32 v4, 0x400000, v22123; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v2, v22124; GFX9-NEXT:    v_add_f32_e32 v0, 0x40c00000, v02125; GFX9-NEXT:    v_cndmask_b32_e32 v2, v3, v4, vcc2126; GFX9-NEXT:    v_bfe_u32 v3, v0, 16, 12127; GFX9-NEXT:    v_add3_u32 v3, v3, v0, s62128; GFX9-NEXT:    v_or_b32_e32 v4, 0x400000, v02129; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v0, v02130; GFX9-NEXT:    v_cndmask_b32_e32 v0, v3, v4, vcc2131; GFX9-NEXT:    s_mov_b32 s7, 0x70603022132; GFX9-NEXT:    v_perm_b32 v0, v0, v2, s72133; GFX9-NEXT:    v_and_b32_e32 v2, 0xffff0000, v12134; GFX9-NEXT:    v_add_f32_e32 v2, 0x40c00000, v22135; GFX9-NEXT:    v_bfe_u32 v3, v2, 16, 12136; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 16, v12137; GFX9-NEXT:    v_add3_u32 v3, v3, v2, s62138; GFX9-NEXT:    v_or_b32_e32 v4, 0x400000, v22139; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v2, v22140; GFX9-NEXT:    v_add_f32_e32 v1, 0x40c00000, v12141; GFX9-NEXT:    v_cndmask_b32_e32 v2, v3, v4, vcc2142; GFX9-NEXT:    v_bfe_u32 v3, v1, 16, 12143; GFX9-NEXT:    v_add3_u32 v3, v3, v1, s62144; GFX9-NEXT:    v_or_b32_e32 v4, 0x400000, v12145; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v1, v12146; GFX9-NEXT:    v_cndmask_b32_e32 v1, v3, v4, vcc2147; GFX9-NEXT:    v_perm_b32 v1, v2, v1, s72148; GFX9-NEXT:  .LBB22_2: ; %end2149; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]2150; GFX9-NEXT:    s_setpc_b64 s[30:31]2151;2152; GFX11-TRUE16-LABEL: bitcast_v4bf16_to_i64:2153; GFX11-TRUE16:       ; %bb.0:2154; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2155; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v22156; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_vgpr32157; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo2158; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)2159; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s02160; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false2161; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v02162; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr02163; GFX11-TRUE16-NEXT:  ; %bb.2: ; %Flow2164; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s02165; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB22_42166; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true2167; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, 02168; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.h, v0.l2169; GFX11-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v02170; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v12171; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)2172; GFX11-TRUE16-NEXT:    v_add_f32_e32 v4, 0x40c00000, v32173; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.h, v1.l2174; GFX11-TRUE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v22175; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)2176; GFX11-TRUE16-NEXT:    v_add_f32_e32 v0, 0x40c00000, v02177; GFX11-TRUE16-NEXT:    v_bfe_u32 v6, v4, 16, 12178; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)2179; GFX11-TRUE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v32180; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, 0x400000, v42181; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v42182; GFX11-TRUE16-NEXT:    v_bfe_u32 v1, v2, 16, 12183; GFX11-TRUE16-NEXT:    v_add3_u32 v6, v6, v4, 0x7fff2184; GFX11-TRUE16-NEXT:    v_bfe_u32 v9, v3, 16, 12185; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, 0x400000, v32186; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, 0x400000, v22187; GFX11-TRUE16-NEXT:    v_bfe_u32 v8, v0, 16, 12188; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v4, v6, v7, vcc_lo2189; GFX11-TRUE16-NEXT:    v_add3_u32 v9, v9, v3, 0x7fff2190; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v32191; GFX11-TRUE16-NEXT:    v_add3_u32 v1, v1, v2, 0x7fff2192; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, 0x400000, v02193; GFX11-TRUE16-NEXT:    v_add3_u32 v8, v8, v0, 0x7fff2194; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v6, v9, v11, vcc_lo2195; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v22196; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v1, v5, vcc_lo2197; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v02198; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v4.h2199; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v8, v10, vcc_lo2200; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v6.h2201; GFX11-TRUE16-NEXT:  .LBB22_4: ; %end2202; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s02203; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)2204; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v32205; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]2206;2207; GFX11-FAKE16-LABEL: bitcast_v4bf16_to_i64:2208; GFX11-FAKE16:       ; %bb.0:2209; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2210; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo2211; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v22212; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s02213; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)2214; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s02215; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB22_22216; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true2217; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff0000, v12218; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)2219; GFX11-FAKE16-NEXT:    v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v2, 16, v02220; GFX11-FAKE16-NEXT:    v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v1, 16, v12221; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)2222; GFX11-FAKE16-NEXT:    v_bfe_u32 v8, v3, 16, 12223; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, 0x400000, v32224; GFX11-FAKE16-NEXT:    v_bfe_u32 v4, v2, 16, 12225; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, 0x400000, v22226; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v22227; GFX11-FAKE16-NEXT:    v_add3_u32 v8, v8, v3, 0x7fff2228; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v02229; GFX11-FAKE16-NEXT:    v_add3_u32 v4, v4, v2, 0x7fff2230; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)2231; GFX11-FAKE16-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v02232; GFX11-FAKE16-NEXT:    v_bfe_u32 v9, v1, 16, 12233; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)2234; GFX11-FAKE16-NEXT:    v_bfe_u32 v6, v0, 16, 12235; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, 0x400000, v02236; GFX11-FAKE16-NEXT:    v_add3_u32 v9, v9, v1, 0x7fff2237; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v4, v5, vcc_lo2238; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v02239; GFX11-FAKE16-NEXT:    v_add3_u32 v6, v6, v0, 0x7fff2240; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, 0x400000, v12241; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)2242; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v6, v7, vcc_lo2243; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v32244; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v8, v10, vcc_lo2245; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v12246; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v9, v4, vcc_lo2247; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v2, 0x70603022248; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)2249; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v3, v1, 0x70603022250; GFX11-FAKE16-NEXT:  .LBB22_2: ; %end2251; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s02252; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]2253  %cmp = icmp eq i32 %b, 02254  br i1 %cmp, label %cmp.true, label %cmp.false2255 2256cmp.true:2257  %a1 = fadd <4 x bfloat> %a, splat (bfloat 0xR40C0)2258  %a2 = bitcast <4 x bfloat> %a1 to i642259  br label %end2260 2261cmp.false:2262  %a3 = bitcast <4 x bfloat> %a to i642263  br label %end2264 2265end:2266  %phi = phi i64 [ %a2, %cmp.true ], [ %a3, %cmp.false ]2267  ret i64 %phi2268}2269 2270define inreg i64 @bitcast_v4bf16_to_i64_scalar(<4 x bfloat> inreg %a, i32 inreg %b) {2271; SI-LABEL: bitcast_v4bf16_to_i64_scalar:2272; SI:       ; %bb.0:2273; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2274; SI-NEXT:    s_cmp_lg_u32 s20, 02275; SI-NEXT:    v_mul_f32_e64 v8, 1.0, s172276; SI-NEXT:    v_mul_f32_e64 v5, 1.0, s162277; SI-NEXT:    v_mul_f32_e64 v7, 1.0, s192278; SI-NEXT:    v_mul_f32_e64 v3, 1.0, s182279; SI-NEXT:    s_cbranch_scc0 .LBB23_42280; SI-NEXT:  ; %bb.1: ; %cmp.false2281; SI-NEXT:    v_lshrrev_b32_e32 v6, 16, v82282; SI-NEXT:    v_lshr_b64 v[0:1], v[5:6], 162283; SI-NEXT:    v_lshrrev_b32_e32 v4, 16, v72284; SI-NEXT:    v_lshr_b64 v[1:2], v[3:4], 162285; SI-NEXT:    s_cbranch_execnz .LBB23_32286; SI-NEXT:  .LBB23_2: ; %cmp.true2287; SI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v82288; SI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v52289; SI-NEXT:    v_add_f32_e32 v1, 0x40c00000, v12290; SI-NEXT:    v_add_f32_e32 v0, 0x40c00000, v02291; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v12292; SI-NEXT:    v_lshr_b64 v[0:1], v[0:1], 162293; SI-NEXT:    v_and_b32_e32 v2, 0xffff0000, v72294; SI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v32295; SI-NEXT:    v_add_f32_e32 v2, 0x40c00000, v22296; SI-NEXT:    v_add_f32_e32 v1, 0x40c00000, v12297; SI-NEXT:    v_lshrrev_b32_e32 v2, 16, v22298; SI-NEXT:    v_lshr_b64 v[1:2], v[1:2], 162299; SI-NEXT:  .LBB23_3: ; %end2300; SI-NEXT:    s_setpc_b64 s[30:31]2301; SI-NEXT:  .LBB23_4:2302; SI-NEXT:    ; implicit-def: $vgpr0_vgpr12303; SI-NEXT:    s_branch .LBB23_22304;2305; VI-LABEL: bitcast_v4bf16_to_i64_scalar:2306; VI:       ; %bb.0:2307; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2308; VI-NEXT:    s_cmp_lg_u32 s18, 02309; VI-NEXT:    s_cbranch_scc0 .LBB23_32310; VI-NEXT:  ; %bb.1: ; %cmp.false2311; VI-NEXT:    s_cbranch_execnz .LBB23_42312; VI-NEXT:  .LBB23_2: ; %cmp.true2313; VI-NEXT:    s_lshl_b32 s4, s17, 162314; VI-NEXT:    v_mov_b32_e32 v4, 0x40c000002315; VI-NEXT:    v_add_f32_e32 v0, s4, v42316; VI-NEXT:    v_bfe_u32 v1, v0, 16, 12317; VI-NEXT:    v_add_u32_e32 v1, vcc, v1, v02318; VI-NEXT:    v_add_u32_e32 v1, vcc, 0x7fff, v12319; VI-NEXT:    v_or_b32_e32 v2, 0x400000, v02320; VI-NEXT:    v_cmp_u_f32_e32 vcc, v0, v02321; VI-NEXT:    s_and_b32 s4, s17, 0xffff00002322; VI-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc2323; VI-NEXT:    v_add_f32_e32 v1, s4, v42324; VI-NEXT:    v_bfe_u32 v2, v1, 16, 12325; VI-NEXT:    v_add_u32_e32 v2, vcc, v2, v12326; VI-NEXT:    v_add_u32_e32 v2, vcc, 0x7fff, v22327; VI-NEXT:    v_or_b32_e32 v3, 0x400000, v12328; VI-NEXT:    v_cmp_u_f32_e32 vcc, v1, v12329; VI-NEXT:    v_cndmask_b32_e32 v1, v2, v3, vcc2330; VI-NEXT:    v_lshrrev_b32_e32 v1, 16, v12331; VI-NEXT:    s_lshl_b32 s4, s16, 162332; VI-NEXT:    v_lshrrev_b64 v[2:3], 16, v[0:1]2333; VI-NEXT:    v_add_f32_e32 v0, s4, v42334; VI-NEXT:    v_bfe_u32 v1, v0, 16, 12335; VI-NEXT:    v_add_u32_e32 v1, vcc, v1, v02336; VI-NEXT:    v_add_u32_e32 v1, vcc, 0x7fff, v12337; VI-NEXT:    v_or_b32_e32 v3, 0x400000, v02338; VI-NEXT:    v_cmp_u_f32_e32 vcc, v0, v02339; VI-NEXT:    s_and_b32 s4, s16, 0xffff00002340; VI-NEXT:    v_cndmask_b32_e32 v0, v1, v3, vcc2341; VI-NEXT:    v_add_f32_e32 v1, s4, v42342; VI-NEXT:    v_bfe_u32 v3, v1, 16, 12343; VI-NEXT:    v_add_u32_e32 v3, vcc, v3, v12344; VI-NEXT:    v_add_u32_e32 v3, vcc, 0x7fff, v32345; VI-NEXT:    v_or_b32_e32 v4, 0x400000, v12346; VI-NEXT:    v_cmp_u_f32_e32 vcc, v1, v12347; VI-NEXT:    v_cndmask_b32_e32 v1, v3, v4, vcc2348; VI-NEXT:    v_lshrrev_b32_e32 v1, 16, v12349; VI-NEXT:    v_lshrrev_b64 v[0:1], 16, v[0:1]2350; VI-NEXT:    v_mov_b32_e32 v1, v22351; VI-NEXT:    s_setpc_b64 s[30:31]2352; VI-NEXT:  .LBB23_3:2353; VI-NEXT:    s_branch .LBB23_22354; VI-NEXT:  .LBB23_4:2355; VI-NEXT:    v_mov_b32_e32 v0, s162356; VI-NEXT:    v_mov_b32_e32 v1, s172357; VI-NEXT:    s_setpc_b64 s[30:31]2358;2359; GFX9-LABEL: bitcast_v4bf16_to_i64_scalar:2360; GFX9:       ; %bb.0:2361; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2362; GFX9-NEXT:    s_cmp_lg_u32 s18, 02363; GFX9-NEXT:    s_cbranch_scc0 .LBB23_32364; GFX9-NEXT:  ; %bb.1: ; %cmp.false2365; GFX9-NEXT:    s_cbranch_execnz .LBB23_42366; GFX9-NEXT:  .LBB23_2: ; %cmp.true2367; GFX9-NEXT:    s_pack_lh_b32_b16 s4, 0, s162368; GFX9-NEXT:    v_mov_b32_e32 v1, 0x40c000002369; GFX9-NEXT:    v_add_f32_e32 v0, s4, v12370; GFX9-NEXT:    v_bfe_u32 v2, v0, 16, 12371; GFX9-NEXT:    v_add_u32_e32 v2, v2, v02372; GFX9-NEXT:    v_add_u32_e32 v2, 0x7fff, v22373; GFX9-NEXT:    v_or_b32_e32 v3, 0x400000, v02374; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v0, v02375; GFX9-NEXT:    s_lshl_b32 s4, s16, 162376; GFX9-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc2377; GFX9-NEXT:    v_add_f32_e32 v2, s4, v12378; GFX9-NEXT:    v_bfe_u32 v3, v2, 16, 12379; GFX9-NEXT:    v_add_u32_e32 v3, v3, v22380; GFX9-NEXT:    v_add_u32_e32 v3, 0x7fff, v32381; GFX9-NEXT:    v_or_b32_e32 v4, 0x400000, v22382; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v2, v22383; GFX9-NEXT:    v_cndmask_b32_e32 v2, v3, v4, vcc2384; GFX9-NEXT:    v_mov_b32_e32 v3, 0xffff2385; GFX9-NEXT:    v_lshrrev_b32_e32 v0, 16, v02386; GFX9-NEXT:    v_and_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_12387; GFX9-NEXT:    s_pack_lh_b32_b16 s4, 0, s172388; GFX9-NEXT:    v_lshl_or_b32 v0, v0, 16, v22389; GFX9-NEXT:    v_add_f32_e32 v2, s4, v12390; GFX9-NEXT:    v_bfe_u32 v4, v2, 16, 12391; GFX9-NEXT:    v_add_u32_e32 v4, v4, v22392; GFX9-NEXT:    s_lshl_b32 s4, s17, 162393; GFX9-NEXT:    v_add_u32_e32 v4, 0x7fff, v42394; GFX9-NEXT:    v_or_b32_e32 v5, 0x400000, v22395; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v2, v22396; GFX9-NEXT:    v_add_f32_e32 v1, s4, v12397; GFX9-NEXT:    v_cndmask_b32_e32 v2, v4, v5, vcc2398; GFX9-NEXT:    v_bfe_u32 v4, v1, 16, 12399; GFX9-NEXT:    v_add_u32_e32 v4, v4, v12400; GFX9-NEXT:    v_add_u32_e32 v4, 0x7fff, v42401; GFX9-NEXT:    v_or_b32_e32 v5, 0x400000, v12402; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v1, v12403; GFX9-NEXT:    v_cndmask_b32_e32 v1, v4, v5, vcc2404; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 16, v22405; GFX9-NEXT:    v_and_b32_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_12406; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v12407; GFX9-NEXT:    s_setpc_b64 s[30:31]2408; GFX9-NEXT:  .LBB23_3:2409; GFX9-NEXT:    s_branch .LBB23_22410; GFX9-NEXT:  .LBB23_4:2411; GFX9-NEXT:    v_mov_b32_e32 v0, s162412; GFX9-NEXT:    v_mov_b32_e32 v1, s172413; GFX9-NEXT:    s_setpc_b64 s[30:31]2414;2415; GFX11-TRUE16-LABEL: bitcast_v4bf16_to_i64_scalar:2416; GFX11-TRUE16:       ; %bb.0:2417; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2418; GFX11-TRUE16-NEXT:    s_cmp_lg_u32 s2, 02419; GFX11-TRUE16-NEXT:    s_mov_b32 s2, 02420; GFX11-TRUE16-NEXT:    s_cbranch_scc0 .LBB23_32421; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow2422; GFX11-TRUE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s22423; GFX11-TRUE16-NEXT:    s_cbranch_vccnz .LBB23_42424; GFX11-TRUE16-NEXT:  .LBB23_2: ; %cmp.true2425; GFX11-TRUE16-NEXT:    s_pack_lh_b32_b16 s2, 0, s02426; GFX11-TRUE16-NEXT:    s_lshl_b32 s0, s0, 162427; GFX11-TRUE16-NEXT:    v_add_f32_e64 v0, 0x40c00000, s22428; GFX11-TRUE16-NEXT:    v_add_f32_e64 v1, 0x40c00000, s02429; GFX11-TRUE16-NEXT:    s_pack_lh_b32_b16 s2, 0, s12430; GFX11-TRUE16-NEXT:    s_lshl_b32 s1, s1, 162431; GFX11-TRUE16-NEXT:    v_add_f32_e64 v3, 0x40c00000, s22432; GFX11-TRUE16-NEXT:    v_bfe_u32 v2, v0, 16, 12433; GFX11-TRUE16-NEXT:    v_bfe_u32 v6, v1, 16, 12434; GFX11-TRUE16-NEXT:    v_add_f32_e64 v4, 0x40c00000, s12435; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, 0x400000, v02436; GFX11-TRUE16-NEXT:    v_bfe_u32 v8, v3, 16, 12437; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v2, v2, v02438; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v6, v6, v12439; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, 0x400000, v12440; GFX11-TRUE16-NEXT:    v_bfe_u32 v9, v4, 16, 12441; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v8, v8, v32442; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v02443; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v6, 0x7fff, v62444; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v2, 0x7fff, v22445; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, 0x400000, v32446; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)2447; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v0, v2, v5 :: v_dual_add_nc_u32 v9, v9, v42448; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, 0x400000, v42449; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v5, 0x7fff, v82450; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v32451; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v8, 0x7fff, v92452; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v9, 16, v02453; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)2454; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v5, v10, vcc_lo2455; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v12456; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v02457; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v6, v7, vcc_lo2458; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v42459; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)2460; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v12461; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v8, v2, vcc_lo2462; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v9.l2463; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v22464; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v3.l2465; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]2466; GFX11-TRUE16-NEXT:  .LBB23_3:2467; GFX11-TRUE16-NEXT:    s_branch .LBB23_22468; GFX11-TRUE16-NEXT:  .LBB23_4:2469; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s12470; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]2471;2472; GFX11-FAKE16-LABEL: bitcast_v4bf16_to_i64_scalar:2473; GFX11-FAKE16:       ; %bb.0:2474; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2475; GFX11-FAKE16-NEXT:    s_cmp_lg_u32 s2, 02476; GFX11-FAKE16-NEXT:    s_mov_b32 s2, 02477; GFX11-FAKE16-NEXT:    s_cbranch_scc0 .LBB23_32478; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow2479; GFX11-FAKE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s22480; GFX11-FAKE16-NEXT:    s_cbranch_vccnz .LBB23_42481; GFX11-FAKE16-NEXT:  .LBB23_2: ; %cmp.true2482; GFX11-FAKE16-NEXT:    s_pack_lh_b32_b16 s2, 0, s02483; GFX11-FAKE16-NEXT:    s_lshl_b32 s0, s0, 162484; GFX11-FAKE16-NEXT:    v_add_f32_e64 v0, 0x40c00000, s22485; GFX11-FAKE16-NEXT:    v_add_f32_e64 v1, 0x40c00000, s02486; GFX11-FAKE16-NEXT:    s_lshl_b32 s0, s1, 162487; GFX11-FAKE16-NEXT:    s_pack_lh_b32_b16 s1, 0, s12488; GFX11-FAKE16-NEXT:    v_add_f32_e64 v2, 0x40c00000, s02489; GFX11-FAKE16-NEXT:    v_add_f32_e64 v5, 0x40c00000, s12490; GFX11-FAKE16-NEXT:    v_bfe_u32 v4, v1, 16, 12491; GFX11-FAKE16-NEXT:    v_bfe_u32 v3, v0, 16, 12492; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, 0x400000, v12493; GFX11-FAKE16-NEXT:    v_bfe_u32 v6, v2, 16, 12494; GFX11-FAKE16-NEXT:    v_bfe_u32 v8, v5, 16, 12495; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v4, v4, v12496; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v12497; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, 0x400000, v22498; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, 0x400000, v02499; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v8, v8, v52500; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v4, 0x7fff, v42501; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)2502; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v1, v4, v9 :: v_dual_add_nc_u32 v6, v6, v22503; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v4, 0x7fff, v82504; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, 0x400000, v52505; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)2506; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v6, 0x7fff, v62507; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v22508; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v3, v3, v02509; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v12510; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v2, v6, v10 :: v_dual_add_nc_u32 v3, 0x7fff, v32511; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v02512; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)2513; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v12514; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v22515; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)2516; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v3, v7, vcc_lo2517; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v52518; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v22519; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)2520; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v02521; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v4, v8, vcc_lo2522; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v0, v0, 16, v12523; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)2524; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v32525; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, v3, 16, v22526; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]2527; GFX11-FAKE16-NEXT:  .LBB23_3:2528; GFX11-FAKE16-NEXT:    s_branch .LBB23_22529; GFX11-FAKE16-NEXT:  .LBB23_4:2530; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s12531; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]2532  %cmp = icmp eq i32 %b, 02533  br i1 %cmp, label %cmp.true, label %cmp.false2534 2535cmp.true:2536  %a1 = fadd <4 x bfloat> %a, splat (bfloat 0xR40C0)2537  %a2 = bitcast <4 x bfloat> %a1 to i642538  br label %end2539 2540cmp.false:2541  %a3 = bitcast <4 x bfloat> %a to i642542  br label %end2543 2544end:2545  %phi = phi i64 [ %a2, %cmp.true ], [ %a3, %cmp.false ]2546  ret i64 %phi2547}2548 2549define <8 x i8> @bitcast_i64_to_v8i8(i64 %a, i32 %b) {2550; SI-LABEL: bitcast_i64_to_v8i8:2551; SI:       ; %bb.0:2552; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2553; SI-NEXT:    v_mov_b32_e32 v4, v12554; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v22555; SI-NEXT:    ; implicit-def: $vgpr12556; SI-NEXT:    ; implicit-def: $vgpr22557; SI-NEXT:    ; implicit-def: $vgpr32558; SI-NEXT:    ; implicit-def: $vgpr52559; SI-NEXT:    ; implicit-def: $vgpr62560; SI-NEXT:    ; implicit-def: $vgpr72561; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc2562; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]2563; SI-NEXT:    s_cbranch_execnz .LBB24_32564; SI-NEXT:  ; %bb.1: ; %Flow2565; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]2566; SI-NEXT:    s_cbranch_execnz .LBB24_42567; SI-NEXT:  .LBB24_2: ; %end2568; SI-NEXT:    s_or_b64 exec, exec, s[4:5]2569; SI-NEXT:    s_setpc_b64 s[30:31]2570; SI-NEXT:  .LBB24_3: ; %cmp.false2571; SI-NEXT:    v_alignbit_b32 v3, v4, v0, 242572; SI-NEXT:    v_alignbit_b32 v2, v4, v0, 162573; SI-NEXT:    v_alignbit_b32 v1, v4, v0, 82574; SI-NEXT:    v_lshrrev_b32_e32 v7, 24, v42575; SI-NEXT:    v_lshrrev_b32_e32 v6, 16, v42576; SI-NEXT:    v_lshrrev_b32_e32 v5, 8, v42577; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]2578; SI-NEXT:    s_cbranch_execz .LBB24_22579; SI-NEXT:  .LBB24_4: ; %cmp.true2580; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v02581; SI-NEXT:    v_addc_u32_e32 v4, vcc, 0, v4, vcc2582; SI-NEXT:    v_alignbit_b32 v3, v4, v0, 242583; SI-NEXT:    v_alignbit_b32 v2, v4, v0, 162584; SI-NEXT:    v_alignbit_b32 v1, v4, v0, 82585; SI-NEXT:    v_lshrrev_b32_e32 v7, 24, v42586; SI-NEXT:    v_lshrrev_b32_e32 v6, 16, v42587; SI-NEXT:    v_lshrrev_b32_e32 v5, 8, v42588; SI-NEXT:    s_or_b64 exec, exec, s[4:5]2589; SI-NEXT:    s_setpc_b64 s[30:31]2590;2591; VI-LABEL: bitcast_i64_to_v8i8:2592; VI:       ; %bb.0:2593; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2594; VI-NEXT:    v_mov_b32_e32 v9, v12595; VI-NEXT:    v_mov_b32_e32 v8, v02596; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v22597; VI-NEXT:    ; implicit-def: $vgpr12598; VI-NEXT:    ; implicit-def: $vgpr22599; VI-NEXT:    ; implicit-def: $vgpr32600; VI-NEXT:    ; implicit-def: $vgpr52601; VI-NEXT:    ; implicit-def: $vgpr62602; VI-NEXT:    ; implicit-def: $vgpr72603; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc2604; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]2605; VI-NEXT:  ; %bb.1: ; %cmp.false2606; VI-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]2607; VI-NEXT:    v_lshrrev_b32_e32 v7, 24, v92608; VI-NEXT:    v_lshrrev_b32_e32 v6, 16, v92609; VI-NEXT:    v_lshrrev_b32_e32 v5, 8, v92610; VI-NEXT:    v_lshrrev_b32_e32 v2, 16, v82611; VI-NEXT:    v_lshrrev_b32_e32 v1, 8, v82612; VI-NEXT:  ; %bb.2: ; %Flow2613; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]2614; VI-NEXT:  ; %bb.3: ; %cmp.true2615; VI-NEXT:    v_add_u32_e32 v8, vcc, 3, v82616; VI-NEXT:    v_addc_u32_e32 v9, vcc, 0, v9, vcc2617; VI-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]2618; VI-NEXT:    v_lshrrev_b32_e32 v7, 24, v92619; VI-NEXT:    v_lshrrev_b32_e32 v6, 16, v92620; VI-NEXT:    v_lshrrev_b32_e32 v5, 8, v92621; VI-NEXT:    v_lshrrev_b32_e32 v2, 16, v82622; VI-NEXT:    v_lshrrev_b32_e32 v1, 8, v82623; VI-NEXT:  ; %bb.4: ; %end2624; VI-NEXT:    s_or_b64 exec, exec, s[4:5]2625; VI-NEXT:    v_mov_b32_e32 v0, v82626; VI-NEXT:    v_mov_b32_e32 v4, v92627; VI-NEXT:    s_setpc_b64 s[30:31]2628;2629; GFX9-LABEL: bitcast_i64_to_v8i8:2630; GFX9:       ; %bb.0:2631; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2632; GFX9-NEXT:    v_mov_b32_e32 v9, v12633; GFX9-NEXT:    v_mov_b32_e32 v8, v02634; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v22635; GFX9-NEXT:    ; implicit-def: $vgpr12636; GFX9-NEXT:    ; implicit-def: $vgpr22637; GFX9-NEXT:    ; implicit-def: $vgpr32638; GFX9-NEXT:    ; implicit-def: $vgpr52639; GFX9-NEXT:    ; implicit-def: $vgpr62640; GFX9-NEXT:    ; implicit-def: $vgpr72641; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc2642; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]2643; GFX9-NEXT:  ; %bb.1: ; %cmp.false2644; GFX9-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]2645; GFX9-NEXT:    v_lshrrev_b32_e32 v7, 24, v92646; GFX9-NEXT:    v_lshrrev_b32_e32 v6, 16, v92647; GFX9-NEXT:    v_lshrrev_b32_e32 v5, 8, v92648; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 16, v82649; GFX9-NEXT:    v_lshrrev_b32_e32 v1, 8, v82650; GFX9-NEXT:  ; %bb.2: ; %Flow2651; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]2652; GFX9-NEXT:  ; %bb.3: ; %cmp.true2653; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, 3, v82654; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, 0, v9, vcc2655; GFX9-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]2656; GFX9-NEXT:    v_lshrrev_b32_e32 v7, 24, v92657; GFX9-NEXT:    v_lshrrev_b32_e32 v6, 16, v92658; GFX9-NEXT:    v_lshrrev_b32_e32 v5, 8, v92659; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 16, v82660; GFX9-NEXT:    v_lshrrev_b32_e32 v1, 8, v82661; GFX9-NEXT:  ; %bb.4: ; %end2662; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]2663; GFX9-NEXT:    v_mov_b32_e32 v0, v82664; GFX9-NEXT:    v_mov_b32_e32 v4, v92665; GFX9-NEXT:    s_setpc_b64 s[30:31]2666;2667; GFX11-TRUE16-LABEL: bitcast_i64_to_v8i8:2668; GFX11-TRUE16:       ; %bb.0:2669; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2670; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v02671; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo2672; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo162673; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo162674; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo162675; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_lo162676; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v22677; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s02678; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false2679; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)2680; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]2681; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v92682; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v92683; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v82684; GFX11-TRUE16-NEXT:  ; %bb.2: ; %Flow2685; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s02686; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true2687; GFX11-TRUE16-NEXT:    v_add_co_u32 v8, vcc_lo, v8, 32688; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)2689; GFX11-TRUE16-NEXT:    v_add_co_ci_u32_e64 v9, null, 0, v9, vcc_lo2690; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v82691; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)2692; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]2693; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v92694; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v92695; GFX11-TRUE16-NEXT:  ; %bb.4: ; %end2696; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s02697; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v8.l2698; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v8.h2699; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v9.l2700; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v9.h2701; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]2702;2703; GFX11-FAKE16-LABEL: bitcast_i64_to_v8i8:2704; GFX11-FAKE16:       ; %bb.0:2705; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2706; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v02707; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v22708; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr12709; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr22710; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr32711; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr52712; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr62713; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr72714; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo2715; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)2716; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s02717; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false2718; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)2719; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]2720; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v92721; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v92722; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v92723; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v82724; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v82725; GFX11-FAKE16-NEXT:  ; %bb.2: ; %Flow2726; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s02727; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB24_42728; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true2729; GFX11-FAKE16-NEXT:    v_add_co_u32 v8, vcc_lo, v8, 32730; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)2731; GFX11-FAKE16-NEXT:    v_add_co_ci_u32_e64 v9, null, 0, v9, vcc_lo2732; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v82733; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v82734; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)2735; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]2736; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v92737; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v92738; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v92739; GFX11-FAKE16-NEXT:  .LBB24_4: ; %end2740; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s02741; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, v82742; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, v92743; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]2744  %cmp = icmp eq i32 %b, 02745  br i1 %cmp, label %cmp.true, label %cmp.false2746 2747cmp.true:2748  %a1 = add i64 %a, 32749  %a2 = bitcast i64 %a1 to <8 x i8>2750  br label %end2751 2752cmp.false:2753  %a3 = bitcast i64 %a to <8 x i8>2754  br label %end2755 2756end:2757  %phi = phi <8 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]2758  ret <8 x i8> %phi2759}2760 2761define inreg <8 x i8> @bitcast_i64_to_v8i8_scalar(i64 inreg %a, i32 inreg %b) {2762; SI-LABEL: bitcast_i64_to_v8i8_scalar:2763; SI:       ; %bb.0:2764; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2765; SI-NEXT:    s_cmp_lg_u32 s18, 02766; SI-NEXT:    s_cbranch_scc0 .LBB25_42767; SI-NEXT:  ; %bb.1: ; %cmp.false2768; SI-NEXT:    s_lshr_b32 s12, s17, 242769; SI-NEXT:    s_lshr_b32 s13, s17, 162770; SI-NEXT:    s_lshr_b32 s14, s17, 82771; SI-NEXT:    s_lshr_b64 s[4:5], s[16:17], 242772; SI-NEXT:    s_lshr_b64 s[6:7], s[16:17], 162773; SI-NEXT:    s_lshr_b64 s[8:9], s[16:17], 82774; SI-NEXT:    s_cbranch_execnz .LBB25_32775; SI-NEXT:  .LBB25_2: ; %cmp.true2776; SI-NEXT:    s_add_u32 s16, s16, 32777; SI-NEXT:    s_addc_u32 s17, s17, 02778; SI-NEXT:    s_lshr_b32 s12, s17, 242779; SI-NEXT:    s_lshr_b32 s13, s17, 162780; SI-NEXT:    s_lshr_b32 s14, s17, 82781; SI-NEXT:    s_lshr_b64 s[4:5], s[16:17], 242782; SI-NEXT:    s_lshr_b64 s[6:7], s[16:17], 162783; SI-NEXT:    s_lshr_b64 s[8:9], s[16:17], 82784; SI-NEXT:  .LBB25_3: ; %end2785; SI-NEXT:    v_mov_b32_e32 v0, s162786; SI-NEXT:    v_mov_b32_e32 v1, s82787; SI-NEXT:    v_mov_b32_e32 v2, s62788; SI-NEXT:    v_mov_b32_e32 v3, s42789; SI-NEXT:    v_mov_b32_e32 v4, s172790; SI-NEXT:    v_mov_b32_e32 v5, s142791; SI-NEXT:    v_mov_b32_e32 v6, s132792; SI-NEXT:    v_mov_b32_e32 v7, s122793; SI-NEXT:    s_setpc_b64 s[30:31]2794; SI-NEXT:  .LBB25_4:2795; SI-NEXT:    ; implicit-def: $sgpr82796; SI-NEXT:    ; implicit-def: $sgpr62797; SI-NEXT:    ; implicit-def: $sgpr42798; SI-NEXT:    ; implicit-def: $sgpr142799; SI-NEXT:    ; implicit-def: $sgpr132800; SI-NEXT:    ; implicit-def: $sgpr122801; SI-NEXT:    s_branch .LBB25_22802;2803; VI-LABEL: bitcast_i64_to_v8i8_scalar:2804; VI:       ; %bb.0:2805; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2806; VI-NEXT:    s_cmp_lg_u32 s18, 02807; VI-NEXT:    s_cbranch_scc0 .LBB25_42808; VI-NEXT:  ; %bb.1: ; %cmp.false2809; VI-NEXT:    s_lshr_b64 s[4:5], s[16:17], 242810; VI-NEXT:    s_lshr_b32 s5, s17, 242811; VI-NEXT:    s_lshr_b32 s8, s17, 162812; VI-NEXT:    s_lshr_b32 s9, s17, 82813; VI-NEXT:    s_lshr_b32 s10, s16, 162814; VI-NEXT:    s_lshr_b32 s11, s16, 82815; VI-NEXT:    s_cbranch_execnz .LBB25_32816; VI-NEXT:  .LBB25_2: ; %cmp.true2817; VI-NEXT:    s_add_u32 s16, s16, 32818; VI-NEXT:    s_addc_u32 s17, s17, 02819; VI-NEXT:    s_lshr_b64 s[4:5], s[16:17], 242820; VI-NEXT:    s_lshr_b32 s5, s17, 242821; VI-NEXT:    s_lshr_b32 s8, s17, 162822; VI-NEXT:    s_lshr_b32 s9, s17, 82823; VI-NEXT:    s_lshr_b32 s10, s16, 162824; VI-NEXT:    s_lshr_b32 s11, s16, 82825; VI-NEXT:  .LBB25_3: ; %end2826; VI-NEXT:    v_mov_b32_e32 v0, s162827; VI-NEXT:    v_mov_b32_e32 v1, s112828; VI-NEXT:    v_mov_b32_e32 v2, s102829; VI-NEXT:    v_mov_b32_e32 v3, s42830; VI-NEXT:    v_mov_b32_e32 v4, s172831; VI-NEXT:    v_mov_b32_e32 v5, s92832; VI-NEXT:    v_mov_b32_e32 v6, s82833; VI-NEXT:    v_mov_b32_e32 v7, s52834; VI-NEXT:    s_setpc_b64 s[30:31]2835; VI-NEXT:  .LBB25_4:2836; VI-NEXT:    ; implicit-def: $sgpr112837; VI-NEXT:    ; implicit-def: $sgpr102838; VI-NEXT:    ; implicit-def: $sgpr42839; VI-NEXT:    ; implicit-def: $sgpr92840; VI-NEXT:    ; implicit-def: $sgpr82841; VI-NEXT:    ; implicit-def: $sgpr52842; VI-NEXT:    s_branch .LBB25_22843;2844; GFX9-LABEL: bitcast_i64_to_v8i8_scalar:2845; GFX9:       ; %bb.0:2846; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2847; GFX9-NEXT:    s_cmp_lg_u32 s18, 02848; GFX9-NEXT:    s_cbranch_scc0 .LBB25_42849; GFX9-NEXT:  ; %bb.1: ; %cmp.false2850; GFX9-NEXT:    s_lshr_b64 s[4:5], s[16:17], 242851; GFX9-NEXT:    s_lshr_b32 s5, s17, 242852; GFX9-NEXT:    s_lshr_b32 s8, s17, 162853; GFX9-NEXT:    s_lshr_b32 s9, s17, 82854; GFX9-NEXT:    s_lshr_b32 s10, s16, 162855; GFX9-NEXT:    s_lshr_b32 s11, s16, 82856; GFX9-NEXT:    s_cbranch_execnz .LBB25_32857; GFX9-NEXT:  .LBB25_2: ; %cmp.true2858; GFX9-NEXT:    s_add_u32 s16, s16, 32859; GFX9-NEXT:    s_addc_u32 s17, s17, 02860; GFX9-NEXT:    s_lshr_b64 s[4:5], s[16:17], 242861; GFX9-NEXT:    s_lshr_b32 s5, s17, 242862; GFX9-NEXT:    s_lshr_b32 s8, s17, 162863; GFX9-NEXT:    s_lshr_b32 s9, s17, 82864; GFX9-NEXT:    s_lshr_b32 s10, s16, 162865; GFX9-NEXT:    s_lshr_b32 s11, s16, 82866; GFX9-NEXT:  .LBB25_3: ; %end2867; GFX9-NEXT:    v_mov_b32_e32 v0, s162868; GFX9-NEXT:    v_mov_b32_e32 v1, s112869; GFX9-NEXT:    v_mov_b32_e32 v2, s102870; GFX9-NEXT:    v_mov_b32_e32 v3, s42871; GFX9-NEXT:    v_mov_b32_e32 v4, s172872; GFX9-NEXT:    v_mov_b32_e32 v5, s92873; GFX9-NEXT:    v_mov_b32_e32 v6, s82874; GFX9-NEXT:    v_mov_b32_e32 v7, s52875; GFX9-NEXT:    s_setpc_b64 s[30:31]2876; GFX9-NEXT:  .LBB25_4:2877; GFX9-NEXT:    ; implicit-def: $sgpr112878; GFX9-NEXT:    ; implicit-def: $sgpr102879; GFX9-NEXT:    ; implicit-def: $sgpr42880; GFX9-NEXT:    ; implicit-def: $sgpr92881; GFX9-NEXT:    ; implicit-def: $sgpr82882; GFX9-NEXT:    ; implicit-def: $sgpr52883; GFX9-NEXT:    s_branch .LBB25_22884;2885; GFX11-LABEL: bitcast_i64_to_v8i8_scalar:2886; GFX11:       ; %bb.0:2887; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2888; GFX11-NEXT:    s_cmp_lg_u32 s2, 02889; GFX11-NEXT:    s_mov_b32 s8, 02890; GFX11-NEXT:    s_cbranch_scc0 .LBB25_42891; GFX11-NEXT:  ; %bb.1: ; %cmp.false2892; GFX11-NEXT:    s_lshr_b64 s[2:3], s[0:1], 242893; GFX11-NEXT:    s_lshr_b32 s3, s1, 242894; GFX11-NEXT:    s_lshr_b32 s4, s1, 162895; GFX11-NEXT:    s_lshr_b32 s5, s1, 82896; GFX11-NEXT:    s_lshr_b32 s6, s0, 162897; GFX11-NEXT:    s_lshr_b32 s7, s0, 82898; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s82899; GFX11-NEXT:    s_cbranch_vccnz .LBB25_32900; GFX11-NEXT:  .LBB25_2: ; %cmp.true2901; GFX11-NEXT:    s_add_u32 s0, s0, 32902; GFX11-NEXT:    s_addc_u32 s1, s1, 02903; GFX11-NEXT:    s_lshr_b32 s6, s0, 162904; GFX11-NEXT:    s_lshr_b64 s[2:3], s[0:1], 242905; GFX11-NEXT:    s_lshr_b32 s3, s1, 242906; GFX11-NEXT:    s_lshr_b32 s4, s1, 162907; GFX11-NEXT:    s_lshr_b32 s5, s1, 82908; GFX11-NEXT:    s_lshr_b32 s7, s0, 82909; GFX11-NEXT:  .LBB25_3: ; %end2910; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)2911; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s72912; GFX11-NEXT:    v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s22913; GFX11-NEXT:    v_dual_mov_b32 v4, s1 :: v_dual_mov_b32 v5, s52914; GFX11-NEXT:    v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s32915; GFX11-NEXT:    s_setpc_b64 s[30:31]2916; GFX11-NEXT:  .LBB25_4:2917; GFX11-NEXT:    ; implicit-def: $sgpr72918; GFX11-NEXT:    ; implicit-def: $sgpr62919; GFX11-NEXT:    ; implicit-def: $sgpr22920; GFX11-NEXT:    ; implicit-def: $sgpr52921; GFX11-NEXT:    ; implicit-def: $sgpr42922; GFX11-NEXT:    ; implicit-def: $sgpr32923; GFX11-NEXT:    s_branch .LBB25_22924  %cmp = icmp eq i32 %b, 02925  br i1 %cmp, label %cmp.true, label %cmp.false2926 2927cmp.true:2928  %a1 = add i64 %a, 32929  %a2 = bitcast i64 %a1 to <8 x i8>2930  br label %end2931 2932cmp.false:2933  %a3 = bitcast i64 %a to <8 x i8>2934  br label %end2935 2936end:2937  %phi = phi <8 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]2938  ret <8 x i8> %phi2939}2940 2941define i64 @bitcast_v8i8_to_i64(<8 x i8> %a, i32 %b) {2942; SI-LABEL: bitcast_v8i8_to_i64:2943; SI:       ; %bb.0:2944; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2945; SI-NEXT:    v_mov_b32_e32 v9, v02946; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v82947; SI-NEXT:    v_lshlrev_b32_e32 v10, 8, v12948; SI-NEXT:    v_lshlrev_b32_e32 v8, 24, v32949; SI-NEXT:    v_lshlrev_b32_e32 v5, 8, v52950; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v72951; SI-NEXT:    ; implicit-def: $vgpr0_vgpr12952; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc2953; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]2954; SI-NEXT:    s_cbranch_execnz .LBB26_32955; SI-NEXT:  ; %bb.1: ; %Flow2956; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]2957; SI-NEXT:    s_cbranch_execnz .LBB26_42958; SI-NEXT:  .LBB26_2: ; %end2959; SI-NEXT:    s_or_b64 exec, exec, s[4:5]2960; SI-NEXT:    s_setpc_b64 s[30:31]2961; SI-NEXT:  .LBB26_3: ; %cmp.false2962; SI-NEXT:    v_and_b32_e32 v0, 0xff, v92963; SI-NEXT:    v_and_b32_e32 v1, 0xff, v22964; SI-NEXT:    v_or_b32_e32 v0, v0, v102965; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v12966; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v02967; SI-NEXT:    v_or_b32_e32 v1, v8, v12968; SI-NEXT:    v_or_b32_e32 v0, v0, v12969; SI-NEXT:    v_and_b32_e32 v1, 0xff, v42970; SI-NEXT:    v_and_b32_e32 v2, 0xff, v62971; SI-NEXT:    v_or_b32_e32 v1, v1, v52972; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v22973; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v12974; SI-NEXT:    v_or_b32_e32 v2, v3, v22975; SI-NEXT:    v_or_b32_e32 v1, v1, v22976; SI-NEXT:    ; implicit-def: $vgpr92977; SI-NEXT:    ; implicit-def: $vgpr102978; SI-NEXT:    ; implicit-def: $vgpr22979; SI-NEXT:    ; implicit-def: $vgpr82980; SI-NEXT:    ; implicit-def: $vgpr42981; SI-NEXT:    ; implicit-def: $vgpr52982; SI-NEXT:    ; implicit-def: $vgpr62983; SI-NEXT:    ; implicit-def: $vgpr32984; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]2985; SI-NEXT:    s_cbranch_execz .LBB26_22986; SI-NEXT:  .LBB26_4: ; %cmp.true2987; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v92988; SI-NEXT:    v_and_b32_e32 v0, 0xff, v02989; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v22990; SI-NEXT:    v_or_b32_e32 v0, v10, v02991; SI-NEXT:    v_and_b32_e32 v1, 0xff, v12992; SI-NEXT:    v_add_i32_e32 v0, vcc, 0x300, v02993; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v12994; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v02995; SI-NEXT:    v_or_b32_e32 v1, v8, v12996; SI-NEXT:    v_or_b32_e32 v0, v1, v02997; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v42998; SI-NEXT:    v_and_b32_e32 v1, 0xff, v12999; SI-NEXT:    v_add_i32_e32 v2, vcc, 3, v63000; SI-NEXT:    v_or_b32_e32 v1, v5, v13001; SI-NEXT:    v_and_b32_e32 v2, 0xff, v23002; SI-NEXT:    v_add_i32_e32 v1, vcc, 0x300, v13003; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v23004; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v13005; SI-NEXT:    v_or_b32_e32 v2, v3, v23006; SI-NEXT:    v_or_b32_e32 v1, v2, v13007; SI-NEXT:    v_add_i32_e32 v0, vcc, 0x3000000, v03008; SI-NEXT:    v_add_i32_e32 v1, vcc, 0x3000000, v13009; SI-NEXT:    s_or_b64 exec, exec, s[4:5]3010; SI-NEXT:    s_setpc_b64 s[30:31]3011;3012; VI-LABEL: bitcast_v8i8_to_i64:3013; VI:       ; %bb.0:3014; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3015; VI-NEXT:    v_mov_b32_e32 v9, v03016; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v83017; VI-NEXT:    v_lshlrev_b16_e32 v10, 8, v13018; VI-NEXT:    v_lshlrev_b16_e32 v8, 8, v33019; VI-NEXT:    v_lshlrev_b16_e32 v5, 8, v53020; VI-NEXT:    v_lshlrev_b16_e32 v3, 8, v73021; VI-NEXT:    ; implicit-def: $vgpr0_vgpr13022; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc3023; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]3024; VI-NEXT:    s_cbranch_execnz .LBB26_33025; VI-NEXT:  ; %bb.1: ; %Flow3026; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]3027; VI-NEXT:    s_cbranch_execnz .LBB26_43028; VI-NEXT:  .LBB26_2: ; %end3029; VI-NEXT:    s_or_b64 exec, exec, s[4:5]3030; VI-NEXT:    s_setpc_b64 s[30:31]3031; VI-NEXT:  .LBB26_3: ; %cmp.false3032; VI-NEXT:    v_or_b32_sdwa v0, v9, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD3033; VI-NEXT:    v_or_b32_sdwa v1, v2, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD3034; VI-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD3035; VI-NEXT:    v_or_b32_sdwa v1, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD3036; VI-NEXT:    v_or_b32_sdwa v2, v6, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD3037; VI-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD3038; VI-NEXT:    ; implicit-def: $vgpr93039; VI-NEXT:    ; implicit-def: $vgpr103040; VI-NEXT:    ; implicit-def: $vgpr23041; VI-NEXT:    ; implicit-def: $vgpr83042; VI-NEXT:    ; implicit-def: $vgpr43043; VI-NEXT:    ; implicit-def: $vgpr53044; VI-NEXT:    ; implicit-def: $vgpr63045; VI-NEXT:    ; implicit-def: $vgpr33046; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]3047; VI-NEXT:    s_cbranch_execz .LBB26_23048; VI-NEXT:  .LBB26_4: ; %cmp.true3049; VI-NEXT:    v_add_u16_e32 v0, 3, v93050; VI-NEXT:    v_add_u16_e32 v1, 3, v23051; VI-NEXT:    v_or_b32_sdwa v0, v10, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_03052; VI-NEXT:    v_or_b32_sdwa v1, v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_03053; VI-NEXT:    v_mov_b32_e32 v2, 0x3003054; VI-NEXT:    v_add_u16_e32 v0, 0x300, v03055; VI-NEXT:    v_add_u16_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD3056; VI-NEXT:    v_or_b32_e32 v0, v0, v13057; VI-NEXT:    v_add_u16_e32 v1, 3, v43058; VI-NEXT:    v_add_u16_e32 v4, 3, v63059; VI-NEXT:    v_or_b32_sdwa v1, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_03060; VI-NEXT:    v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_03061; VI-NEXT:    v_add_u16_e32 v1, 0x300, v13062; VI-NEXT:    v_add_u16_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD3063; VI-NEXT:    v_or_b32_e32 v1, v1, v23064; VI-NEXT:    s_or_b64 exec, exec, s[4:5]3065; VI-NEXT:    s_setpc_b64 s[30:31]3066;3067; GFX9-LABEL: bitcast_v8i8_to_i64:3068; GFX9:       ; %bb.0:3069; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3070; GFX9-NEXT:    v_mov_b32_e32 v9, v03071; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v83072; GFX9-NEXT:    v_lshlrev_b16_e32 v10, 8, v13073; GFX9-NEXT:    v_lshlrev_b16_e32 v8, 8, v33074; GFX9-NEXT:    v_lshlrev_b16_e32 v5, 8, v53075; GFX9-NEXT:    v_lshlrev_b16_e32 v3, 8, v73076; GFX9-NEXT:    ; implicit-def: $vgpr0_vgpr13077; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc3078; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]3079; GFX9-NEXT:    s_cbranch_execnz .LBB26_33080; GFX9-NEXT:  ; %bb.1: ; %Flow3081; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]3082; GFX9-NEXT:    s_cbranch_execnz .LBB26_43083; GFX9-NEXT:  .LBB26_2: ; %end3084; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]3085; GFX9-NEXT:    s_setpc_b64 s[30:31]3086; GFX9-NEXT:  .LBB26_3: ; %cmp.false3087; GFX9-NEXT:    v_or_b32_sdwa v0, v9, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD3088; GFX9-NEXT:    v_or_b32_sdwa v1, v2, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD3089; GFX9-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD3090; GFX9-NEXT:    v_or_b32_sdwa v1, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD3091; GFX9-NEXT:    v_or_b32_sdwa v2, v6, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD3092; GFX9-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD3093; GFX9-NEXT:    ; implicit-def: $vgpr93094; GFX9-NEXT:    ; implicit-def: $vgpr103095; GFX9-NEXT:    ; implicit-def: $vgpr23096; GFX9-NEXT:    ; implicit-def: $vgpr83097; GFX9-NEXT:    ; implicit-def: $vgpr43098; GFX9-NEXT:    ; implicit-def: $vgpr53099; GFX9-NEXT:    ; implicit-def: $vgpr63100; GFX9-NEXT:    ; implicit-def: $vgpr33101; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]3102; GFX9-NEXT:    s_cbranch_execz .LBB26_23103; GFX9-NEXT:  .LBB26_4: ; %cmp.true3104; GFX9-NEXT:    v_add_u16_e32 v0, 3, v93105; GFX9-NEXT:    v_add_u16_e32 v1, 3, v23106; GFX9-NEXT:    v_or_b32_sdwa v0, v10, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_03107; GFX9-NEXT:    s_movk_i32 s6, 0x3003108; GFX9-NEXT:    v_or_b32_sdwa v1, v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_03109; GFX9-NEXT:    v_add_u16_e32 v0, 0x300, v03110; GFX9-NEXT:    v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD3111; GFX9-NEXT:    v_or_b32_e32 v0, v0, v13112; GFX9-NEXT:    v_add_u16_e32 v1, 3, v43113; GFX9-NEXT:    v_add_u16_e32 v2, 3, v63114; GFX9-NEXT:    v_or_b32_sdwa v1, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_03115; GFX9-NEXT:    v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_03116; GFX9-NEXT:    v_add_u16_e32 v1, 0x300, v13117; GFX9-NEXT:    v_add_u16_sdwa v2, v2, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD3118; GFX9-NEXT:    v_or_b32_e32 v1, v1, v23119; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]3120; GFX9-NEXT:    s_setpc_b64 s[30:31]3121;3122; GFX11-TRUE16-LABEL: bitcast_v8i8_to_i64:3123; GFX11-TRUE16:       ; %bb.0:3124; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3125; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.h, v5.l3126; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.h, v2.l3127; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v0.l3128; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.l, 8, v1.l3129; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.h, 8, v3.l3130; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.l, 8, v5.h3131; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.h, 8, v7.l3132; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo3133; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr13134; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v83135; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s03136; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB26_33137; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow3138; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s03139; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB26_43140; GFX11-TRUE16-NEXT:  .LBB26_2: ; %end3141; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s03142; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]3143; GFX11-TRUE16-NEXT:  .LBB26_3: ; %cmp.false3144; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v5.l3145; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v4.h3146; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v4.l3147; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v6.l3148; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo163149; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_hi163150; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_lo163151; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr6_lo163152; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)3153; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v2.l3154; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v0.h, v2.h3155; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)3156; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v3.l3157; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v1.h, v3.h3158; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_lo163159; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_hi163160; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo163161; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_hi163162; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s03163; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB26_23164; GFX11-TRUE16-NEXT:  .LBB26_4: ; %cmp.true3165; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v5.l, 33166; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v4.h, 33167; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v4.l, 33168; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v6.l, 33169; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)3170; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l3171; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h3172; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)3173; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l3174; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h3175; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)3176; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v2.l, v0.l3177; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v2.h, v0.h3178; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)3179; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v3.l, v1.l3180; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v3.h, v1.h3181; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)3182; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l3183; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, 0x300, v0.h3184; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)3185; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.l3186; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, 0x300, v1.h3187; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s03188; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]3189;3190; GFX11-FAKE16-LABEL: bitcast_v8i8_to_i64:3191; GFX11-FAKE16:       ; %bb.0:3192; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3193; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v9, v03194; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v83195; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v8, 8, v13196; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v3, 8, v33197; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v5, 8, v53198; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v7, 8, v73199; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr13200; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo3201; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)3202; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s03203; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB26_33204; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow3205; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s03206; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB26_43207; GFX11-FAKE16-NEXT:  .LBB26_2: ; %end3208; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s03209; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]3210; GFX11-FAKE16-NEXT:  .LBB26_3: ; %cmp.false3211; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v93212; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v23213; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v43214; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v63215; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr93216; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr63217; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)3218; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v83219; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v33220; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)3221; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v53222; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v4, v73223; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr83224; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr43225; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr53226; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr73227; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)3228; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v03229; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v13230; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)3231; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v23232; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v33233; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)3234; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v13235; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v33236; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr23237; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33238; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s03239; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB26_23240; GFX11-FAKE16-NEXT:  .LBB26_4: ; %cmp.true3241; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v9, 33242; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v2, 33243; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v4, 33244; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v6, 33245; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)3246; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v03247; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v13248; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)3249; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v23250; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v43251; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)3252; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v8, v03253; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v3, v13254; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)3255; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v5, v23256; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v7, v43257; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)3258; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v03259; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v13260; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)3261; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x300, v23262; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v33263; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)3264; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v03265; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v13266; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)3267; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v23268; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v33269; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)3270; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v13271; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v33272; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s03273; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]3274  %cmp = icmp eq i32 %b, 03275  br i1 %cmp, label %cmp.true, label %cmp.false3276 3277cmp.true:3278  %a1 = add <8 x i8> %a, splat (i8 3)3279  %a2 = bitcast <8 x i8> %a1 to i643280  br label %end3281 3282cmp.false:3283  %a3 = bitcast <8 x i8> %a to i643284  br label %end3285 3286end:3287  %phi = phi i64 [ %a2, %cmp.true ], [ %a3, %cmp.false ]3288  ret i64 %phi3289}3290 3291define inreg i64 @bitcast_v8i8_to_i64_scalar(<8 x i8> inreg %a, i32 inreg %b) {3292; SI-LABEL: bitcast_v8i8_to_i64_scalar:3293; SI:       ; %bb.0:3294; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3295; SI-NEXT:    s_cmp_lg_u32 s24, 03296; SI-NEXT:    s_cbranch_scc0 .LBB27_43297; SI-NEXT:  ; %bb.1: ; %cmp.false3298; SI-NEXT:    s_and_b32 s4, s16, 0xff3299; SI-NEXT:    s_lshl_b32 s5, s17, 83300; SI-NEXT:    s_or_b32 s4, s4, s53301; SI-NEXT:    s_and_b32 s5, s18, 0xff3302; SI-NEXT:    s_lshl_b32 s5, s5, 163303; SI-NEXT:    s_lshl_b32 s6, s19, 243304; SI-NEXT:    s_and_b32 s4, s4, 0xffff3305; SI-NEXT:    s_or_b32 s5, s6, s53306; SI-NEXT:    s_or_b32 s4, s4, s53307; SI-NEXT:    s_and_b32 s5, s20, 0xff3308; SI-NEXT:    s_lshl_b32 s6, s21, 83309; SI-NEXT:    s_or_b32 s5, s5, s63310; SI-NEXT:    s_and_b32 s6, s22, 0xff3311; SI-NEXT:    s_lshl_b32 s6, s6, 163312; SI-NEXT:    s_lshl_b32 s7, s23, 243313; SI-NEXT:    s_and_b32 s5, s5, 0xffff3314; SI-NEXT:    s_or_b32 s6, s7, s63315; SI-NEXT:    s_or_b32 s5, s5, s63316; SI-NEXT:    s_cbranch_execnz .LBB27_33317; SI-NEXT:  .LBB27_2: ; %cmp.true3318; SI-NEXT:    s_add_i32 s16, s16, 33319; SI-NEXT:    s_and_b32 s4, s16, 0xff3320; SI-NEXT:    s_lshl_b32 s5, s17, 83321; SI-NEXT:    s_add_i32 s18, s18, 33322; SI-NEXT:    s_or_b32 s4, s5, s43323; SI-NEXT:    s_and_b32 s6, s18, 0xff3324; SI-NEXT:    s_addk_i32 s4, 0x3003325; SI-NEXT:    s_lshl_b32 s5, s19, 243326; SI-NEXT:    s_lshl_b32 s6, s6, 163327; SI-NEXT:    s_and_b32 s4, s4, 0xffff3328; SI-NEXT:    s_or_b32 s5, s5, s63329; SI-NEXT:    s_add_i32 s20, s20, 33330; SI-NEXT:    s_or_b32 s4, s5, s43331; SI-NEXT:    s_and_b32 s5, s20, 0xff3332; SI-NEXT:    s_lshl_b32 s6, s21, 83333; SI-NEXT:    s_add_i32 s22, s22, 33334; SI-NEXT:    s_or_b32 s5, s6, s53335; SI-NEXT:    s_and_b32 s7, s22, 0xff3336; SI-NEXT:    s_addk_i32 s5, 0x3003337; SI-NEXT:    s_lshl_b32 s6, s23, 243338; SI-NEXT:    s_lshl_b32 s7, s7, 163339; SI-NEXT:    s_and_b32 s5, s5, 0xffff3340; SI-NEXT:    s_or_b32 s6, s6, s73341; SI-NEXT:    s_or_b32 s5, s6, s53342; SI-NEXT:    s_add_i32 s4, s4, 0x30000003343; SI-NEXT:    s_add_i32 s5, s5, 0x30000003344; SI-NEXT:  .LBB27_3: ; %end3345; SI-NEXT:    v_mov_b32_e32 v0, s43346; SI-NEXT:    v_mov_b32_e32 v1, s53347; SI-NEXT:    s_setpc_b64 s[30:31]3348; SI-NEXT:  .LBB27_4:3349; SI-NEXT:    ; implicit-def: $sgpr4_sgpr53350; SI-NEXT:    s_branch .LBB27_23351;3352; VI-LABEL: bitcast_v8i8_to_i64_scalar:3353; VI:       ; %bb.0:3354; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3355; VI-NEXT:    s_cmp_lg_u32 s24, 03356; VI-NEXT:    s_cbranch_scc0 .LBB27_43357; VI-NEXT:  ; %bb.1: ; %cmp.false3358; VI-NEXT:    s_and_b32 s4, s16, 0xff3359; VI-NEXT:    s_lshl_b32 s5, s17, 83360; VI-NEXT:    s_or_b32 s4, s4, s53361; VI-NEXT:    s_and_b32 s5, s18, 0xff3362; VI-NEXT:    s_lshl_b32 s6, s19, 83363; VI-NEXT:    s_or_b32 s5, s5, s63364; VI-NEXT:    s_and_b32 s4, s4, 0xffff3365; VI-NEXT:    s_lshl_b32 s5, s5, 163366; VI-NEXT:    s_or_b32 s4, s4, s53367; VI-NEXT:    s_and_b32 s5, s20, 0xff3368; VI-NEXT:    s_lshl_b32 s6, s21, 83369; VI-NEXT:    s_or_b32 s5, s5, s63370; VI-NEXT:    s_and_b32 s6, s22, 0xff3371; VI-NEXT:    s_lshl_b32 s7, s23, 83372; VI-NEXT:    s_or_b32 s6, s6, s73373; VI-NEXT:    s_and_b32 s5, s5, 0xffff3374; VI-NEXT:    s_lshl_b32 s6, s6, 163375; VI-NEXT:    s_or_b32 s5, s5, s63376; VI-NEXT:    s_cbranch_execnz .LBB27_33377; VI-NEXT:  .LBB27_2: ; %cmp.true3378; VI-NEXT:    s_add_i32 s16, s16, 33379; VI-NEXT:    s_and_b32 s4, s16, 0xff3380; VI-NEXT:    s_lshl_b32 s5, s17, 83381; VI-NEXT:    s_add_i32 s18, s18, 33382; VI-NEXT:    s_or_b32 s4, s5, s43383; VI-NEXT:    s_and_b32 s5, s18, 0xff3384; VI-NEXT:    s_lshl_b32 s6, s19, 83385; VI-NEXT:    s_addk_i32 s4, 0x3003386; VI-NEXT:    s_or_b32 s5, s6, s53387; VI-NEXT:    s_and_b32 s4, s4, 0xffff3388; VI-NEXT:    s_lshl_b32 s5, s5, 163389; VI-NEXT:    s_add_i32 s20, s20, 33390; VI-NEXT:    s_or_b32 s4, s5, s43391; VI-NEXT:    s_and_b32 s5, s20, 0xff3392; VI-NEXT:    s_lshl_b32 s6, s21, 83393; VI-NEXT:    s_add_i32 s22, s22, 33394; VI-NEXT:    s_or_b32 s5, s6, s53395; VI-NEXT:    s_and_b32 s6, s22, 0xff3396; VI-NEXT:    s_lshl_b32 s7, s23, 83397; VI-NEXT:    s_addk_i32 s5, 0x3003398; VI-NEXT:    s_or_b32 s6, s7, s63399; VI-NEXT:    s_and_b32 s5, s5, 0xffff3400; VI-NEXT:    s_lshl_b32 s6, s6, 163401; VI-NEXT:    s_or_b32 s5, s6, s53402; VI-NEXT:    s_add_i32 s4, s4, 0x30000003403; VI-NEXT:    s_add_i32 s5, s5, 0x30000003404; VI-NEXT:  .LBB27_3: ; %end3405; VI-NEXT:    v_mov_b32_e32 v0, s43406; VI-NEXT:    v_mov_b32_e32 v1, s53407; VI-NEXT:    s_setpc_b64 s[30:31]3408; VI-NEXT:  .LBB27_4:3409; VI-NEXT:    ; implicit-def: $sgpr4_sgpr53410; VI-NEXT:    s_branch .LBB27_23411;3412; GFX9-LABEL: bitcast_v8i8_to_i64_scalar:3413; GFX9:       ; %bb.0:3414; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3415; GFX9-NEXT:    s_cmp_lg_u32 s24, 03416; GFX9-NEXT:    s_cbranch_scc0 .LBB27_43417; GFX9-NEXT:  ; %bb.1: ; %cmp.false3418; GFX9-NEXT:    s_and_b32 s4, s16, 0xff3419; GFX9-NEXT:    s_lshl_b32 s5, s17, 83420; GFX9-NEXT:    s_or_b32 s4, s4, s53421; GFX9-NEXT:    s_and_b32 s5, s18, 0xff3422; GFX9-NEXT:    s_lshl_b32 s6, s19, 83423; GFX9-NEXT:    s_or_b32 s5, s5, s63424; GFX9-NEXT:    s_and_b32 s4, s4, 0xffff3425; GFX9-NEXT:    s_lshl_b32 s5, s5, 163426; GFX9-NEXT:    s_or_b32 s4, s4, s53427; GFX9-NEXT:    s_and_b32 s5, s20, 0xff3428; GFX9-NEXT:    s_lshl_b32 s6, s21, 83429; GFX9-NEXT:    s_or_b32 s5, s5, s63430; GFX9-NEXT:    s_and_b32 s6, s22, 0xff3431; GFX9-NEXT:    s_lshl_b32 s7, s23, 83432; GFX9-NEXT:    s_or_b32 s6, s6, s73433; GFX9-NEXT:    s_and_b32 s5, s5, 0xffff3434; GFX9-NEXT:    s_lshl_b32 s6, s6, 163435; GFX9-NEXT:    s_or_b32 s5, s5, s63436; GFX9-NEXT:    s_cbranch_execnz .LBB27_33437; GFX9-NEXT:  .LBB27_2: ; %cmp.true3438; GFX9-NEXT:    s_add_i32 s16, s16, 33439; GFX9-NEXT:    s_and_b32 s4, s16, 0xff3440; GFX9-NEXT:    s_lshl_b32 s5, s17, 83441; GFX9-NEXT:    s_add_i32 s18, s18, 33442; GFX9-NEXT:    s_or_b32 s4, s5, s43443; GFX9-NEXT:    s_and_b32 s5, s18, 0xff3444; GFX9-NEXT:    s_lshl_b32 s6, s19, 83445; GFX9-NEXT:    s_or_b32 s5, s6, s53446; GFX9-NEXT:    s_addk_i32 s4, 0x3003447; GFX9-NEXT:    s_addk_i32 s5, 0x3003448; GFX9-NEXT:    s_and_b32 s4, s4, 0xffff3449; GFX9-NEXT:    s_lshl_b32 s5, s5, 163450; GFX9-NEXT:    s_add_i32 s20, s20, 33451; GFX9-NEXT:    s_or_b32 s4, s4, s53452; GFX9-NEXT:    s_and_b32 s5, s20, 0xff3453; GFX9-NEXT:    s_lshl_b32 s6, s21, 83454; GFX9-NEXT:    s_add_i32 s22, s22, 33455; GFX9-NEXT:    s_or_b32 s5, s6, s53456; GFX9-NEXT:    s_and_b32 s6, s22, 0xff3457; GFX9-NEXT:    s_lshl_b32 s7, s23, 83458; GFX9-NEXT:    s_or_b32 s6, s7, s63459; GFX9-NEXT:    s_addk_i32 s5, 0x3003460; GFX9-NEXT:    s_addk_i32 s6, 0x3003461; GFX9-NEXT:    s_and_b32 s5, s5, 0xffff3462; GFX9-NEXT:    s_lshl_b32 s6, s6, 163463; GFX9-NEXT:    s_or_b32 s5, s5, s63464; GFX9-NEXT:  .LBB27_3: ; %end3465; GFX9-NEXT:    v_mov_b32_e32 v0, s43466; GFX9-NEXT:    v_mov_b32_e32 v1, s53467; GFX9-NEXT:    s_setpc_b64 s[30:31]3468; GFX9-NEXT:  .LBB27_4:3469; GFX9-NEXT:    ; implicit-def: $sgpr4_sgpr53470; GFX9-NEXT:    s_branch .LBB27_23471;3472; GFX11-LABEL: bitcast_v8i8_to_i64_scalar:3473; GFX11:       ; %bb.0:3474; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3475; GFX11-NEXT:    s_cmp_lg_u32 s20, 03476; GFX11-NEXT:    s_mov_b32 s6, 03477; GFX11-NEXT:    s_cbranch_scc0 .LBB27_43478; GFX11-NEXT:  ; %bb.1: ; %cmp.false3479; GFX11-NEXT:    s_and_b32 s4, s0, 0xff3480; GFX11-NEXT:    s_lshl_b32 s5, s1, 83481; GFX11-NEXT:    s_and_b32 s7, s2, 0xff3482; GFX11-NEXT:    s_lshl_b32 s8, s3, 83483; GFX11-NEXT:    s_or_b32 s4, s4, s53484; GFX11-NEXT:    s_or_b32 s5, s7, s83485; GFX11-NEXT:    s_and_b32 s7, s16, 0xff3486; GFX11-NEXT:    s_lshl_b32 s8, s17, 83487; GFX11-NEXT:    s_and_b32 s9, s18, 0xff3488; GFX11-NEXT:    s_lshl_b32 s10, s19, 83489; GFX11-NEXT:    s_or_b32 s7, s7, s83490; GFX11-NEXT:    s_or_b32 s8, s9, s103491; GFX11-NEXT:    s_and_b32 s4, s4, 0xffff3492; GFX11-NEXT:    s_lshl_b32 s5, s5, 163493; GFX11-NEXT:    s_and_b32 s7, s7, 0xffff3494; GFX11-NEXT:    s_lshl_b32 s8, s8, 163495; GFX11-NEXT:    s_or_b32 s4, s4, s53496; GFX11-NEXT:    s_or_b32 s5, s7, s83497; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s63498; GFX11-NEXT:    s_cbranch_vccnz .LBB27_33499; GFX11-NEXT:  .LBB27_2: ; %cmp.true3500; GFX11-NEXT:    s_add_i32 s0, s0, 33501; GFX11-NEXT:    s_lshl_b32 s1, s1, 83502; GFX11-NEXT:    s_and_b32 s0, s0, 0xff3503; GFX11-NEXT:    s_add_i32 s2, s2, 33504; GFX11-NEXT:    s_or_b32 s0, s1, s03505; GFX11-NEXT:    s_and_b32 s1, s2, 0xff3506; GFX11-NEXT:    s_lshl_b32 s2, s3, 83507; GFX11-NEXT:    s_add_i32 s16, s16, 33508; GFX11-NEXT:    s_add_i32 s18, s18, 33509; GFX11-NEXT:    s_or_b32 s1, s2, s13510; GFX11-NEXT:    s_and_b32 s2, s16, 0xff3511; GFX11-NEXT:    s_lshl_b32 s3, s17, 83512; GFX11-NEXT:    s_and_b32 s4, s18, 0xff3513; GFX11-NEXT:    s_lshl_b32 s5, s19, 83514; GFX11-NEXT:    s_or_b32 s2, s3, s23515; GFX11-NEXT:    s_or_b32 s3, s5, s43516; GFX11-NEXT:    s_addk_i32 s0, 0x3003517; GFX11-NEXT:    s_addk_i32 s1, 0x3003518; GFX11-NEXT:    s_addk_i32 s2, 0x3003519; GFX11-NEXT:    s_addk_i32 s3, 0x3003520; GFX11-NEXT:    s_and_b32 s0, s0, 0xffff3521; GFX11-NEXT:    s_lshl_b32 s1, s1, 163522; GFX11-NEXT:    s_and_b32 s2, s2, 0xffff3523; GFX11-NEXT:    s_lshl_b32 s3, s3, 163524; GFX11-NEXT:    s_or_b32 s4, s0, s13525; GFX11-NEXT:    s_or_b32 s5, s2, s33526; GFX11-NEXT:  .LBB27_3: ; %end3527; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)3528; GFX11-NEXT:    v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s53529; GFX11-NEXT:    s_setpc_b64 s[30:31]3530; GFX11-NEXT:  .LBB27_4:3531; GFX11-NEXT:    ; implicit-def: $sgpr4_sgpr53532; GFX11-NEXT:    s_branch .LBB27_23533  %cmp = icmp eq i32 %b, 03534  br i1 %cmp, label %cmp.true, label %cmp.false3535 3536cmp.true:3537  %a1 = add <8 x i8> %a, splat (i8 3)3538  %a2 = bitcast <8 x i8> %a1 to i643539  br label %end3540 3541cmp.false:3542  %a3 = bitcast <8 x i8> %a to i643543  br label %end3544 3545end:3546  %phi = phi i64 [ %a2, %cmp.true ], [ %a3, %cmp.false ]3547  ret i64 %phi3548}3549 3550define <2 x i32> @bitcast_f64_to_v2i32(double %a, i32 %b) {3551; SI-LABEL: bitcast_f64_to_v2i32:3552; SI:       ; %bb.0:3553; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3554; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v23555; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc3556; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]3557; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]3558; SI-NEXT:  ; %bb.1: ; %cmp.true3559; SI-NEXT:    v_add_f64 v[0:1], v[0:1], 1.03560; SI-NEXT:  ; %bb.2: ; %end3561; SI-NEXT:    s_or_b64 exec, exec, s[4:5]3562; SI-NEXT:    s_setpc_b64 s[30:31]3563;3564; VI-LABEL: bitcast_f64_to_v2i32:3565; VI:       ; %bb.0:3566; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3567; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v23568; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc3569; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]3570; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]3571; VI-NEXT:  ; %bb.1: ; %cmp.true3572; VI-NEXT:    v_add_f64 v[0:1], v[0:1], 1.03573; VI-NEXT:  ; %bb.2: ; %end3574; VI-NEXT:    s_or_b64 exec, exec, s[4:5]3575; VI-NEXT:    s_setpc_b64 s[30:31]3576;3577; GFX9-LABEL: bitcast_f64_to_v2i32:3578; GFX9:       ; %bb.0:3579; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3580; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v23581; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc3582; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]3583; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]3584; GFX9-NEXT:  ; %bb.1: ; %cmp.true3585; GFX9-NEXT:    v_add_f64 v[0:1], v[0:1], 1.03586; GFX9-NEXT:  ; %bb.2: ; %end3587; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]3588; GFX9-NEXT:    s_setpc_b64 s[30:31]3589;3590; GFX11-LABEL: bitcast_f64_to_v2i32:3591; GFX11:       ; %bb.0:3592; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3593; GFX11-NEXT:    s_mov_b32 s0, exec_lo3594; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v23595; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s03596; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)3597; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s03598; GFX11-NEXT:    s_cbranch_execz .LBB28_23599; GFX11-NEXT:  ; %bb.1: ; %cmp.true3600; GFX11-NEXT:    v_add_f64 v[0:1], v[0:1], 1.03601; GFX11-NEXT:  .LBB28_2: ; %end3602; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s03603; GFX11-NEXT:    s_setpc_b64 s[30:31]3604  %cmp = icmp eq i32 %b, 03605  br i1 %cmp, label %cmp.true, label %cmp.false3606 3607cmp.true:3608  %a1 = fadd double %a, 1.000000e+003609  %a2 = bitcast double %a1 to <2 x i32>3610  br label %end3611 3612cmp.false:3613  %a3 = bitcast double %a to <2 x i32>3614  br label %end3615 3616end:3617  %phi = phi <2 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]3618  ret <2 x i32> %phi3619}3620 3621define inreg <2 x i32> @bitcast_f64_to_v2i32_scalar(double inreg %a, i32 inreg %b) {3622; SI-LABEL: bitcast_f64_to_v2i32_scalar:3623; SI:       ; %bb.0:3624; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3625; SI-NEXT:    s_cmp_lg_u32 s18, 03626; SI-NEXT:    s_cbranch_scc0 .LBB29_33627; SI-NEXT:  ; %bb.1: ; %cmp.false3628; SI-NEXT:    s_cbranch_execnz .LBB29_43629; SI-NEXT:  .LBB29_2: ; %cmp.true3630; SI-NEXT:    v_add_f64 v[0:1], s[16:17], 1.03631; SI-NEXT:    s_setpc_b64 s[30:31]3632; SI-NEXT:  .LBB29_3:3633; SI-NEXT:    s_branch .LBB29_23634; SI-NEXT:  .LBB29_4:3635; SI-NEXT:    v_mov_b32_e32 v0, s163636; SI-NEXT:    v_mov_b32_e32 v1, s173637; SI-NEXT:    s_setpc_b64 s[30:31]3638;3639; VI-LABEL: bitcast_f64_to_v2i32_scalar:3640; VI:       ; %bb.0:3641; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3642; VI-NEXT:    s_cmp_lg_u32 s18, 03643; VI-NEXT:    s_cbranch_scc0 .LBB29_33644; VI-NEXT:  ; %bb.1: ; %cmp.false3645; VI-NEXT:    s_cbranch_execnz .LBB29_43646; VI-NEXT:  .LBB29_2: ; %cmp.true3647; VI-NEXT:    v_add_f64 v[0:1], s[16:17], 1.03648; VI-NEXT:    s_setpc_b64 s[30:31]3649; VI-NEXT:  .LBB29_3:3650; VI-NEXT:    s_branch .LBB29_23651; VI-NEXT:  .LBB29_4:3652; VI-NEXT:    v_mov_b32_e32 v0, s163653; VI-NEXT:    v_mov_b32_e32 v1, s173654; VI-NEXT:    s_setpc_b64 s[30:31]3655;3656; GFX9-LABEL: bitcast_f64_to_v2i32_scalar:3657; GFX9:       ; %bb.0:3658; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3659; GFX9-NEXT:    s_cmp_lg_u32 s18, 03660; GFX9-NEXT:    s_cbranch_scc0 .LBB29_33661; GFX9-NEXT:  ; %bb.1: ; %cmp.false3662; GFX9-NEXT:    s_cbranch_execnz .LBB29_43663; GFX9-NEXT:  .LBB29_2: ; %cmp.true3664; GFX9-NEXT:    v_add_f64 v[0:1], s[16:17], 1.03665; GFX9-NEXT:    s_setpc_b64 s[30:31]3666; GFX9-NEXT:  .LBB29_3:3667; GFX9-NEXT:    s_branch .LBB29_23668; GFX9-NEXT:  .LBB29_4:3669; GFX9-NEXT:    v_mov_b32_e32 v0, s163670; GFX9-NEXT:    v_mov_b32_e32 v1, s173671; GFX9-NEXT:    s_setpc_b64 s[30:31]3672;3673; GFX11-LABEL: bitcast_f64_to_v2i32_scalar:3674; GFX11:       ; %bb.0:3675; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3676; GFX11-NEXT:    s_cmp_lg_u32 s2, 03677; GFX11-NEXT:    s_mov_b32 s2, 03678; GFX11-NEXT:    s_cbranch_scc0 .LBB29_33679; GFX11-NEXT:  ; %bb.1: ; %Flow3680; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s23681; GFX11-NEXT:    s_cbranch_vccnz .LBB29_43682; GFX11-NEXT:  .LBB29_2: ; %cmp.true3683; GFX11-NEXT:    v_add_f64 v[0:1], s[0:1], 1.03684; GFX11-NEXT:    s_setpc_b64 s[30:31]3685; GFX11-NEXT:  .LBB29_3:3686; GFX11-NEXT:    s_branch .LBB29_23687; GFX11-NEXT:  .LBB29_4:3688; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s13689; GFX11-NEXT:    s_setpc_b64 s[30:31]3690  %cmp = icmp eq i32 %b, 03691  br i1 %cmp, label %cmp.true, label %cmp.false3692 3693cmp.true:3694  %a1 = fadd double %a, 1.000000e+003695  %a2 = bitcast double %a1 to <2 x i32>3696  br label %end3697 3698cmp.false:3699  %a3 = bitcast double %a to <2 x i32>3700  br label %end3701 3702end:3703  %phi = phi <2 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]3704  ret <2 x i32> %phi3705}3706 3707define double @bitcast_v2i32_to_f64(<2 x i32> %a, i32 %b) {3708; SI-LABEL: bitcast_v2i32_to_f64:3709; SI:       ; %bb.0:3710; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3711; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v23712; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc3713; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]3714; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]3715; SI-NEXT:  ; %bb.1: ; %cmp.true3716; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v13717; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v03718; SI-NEXT:  ; %bb.2: ; %end3719; SI-NEXT:    s_or_b64 exec, exec, s[4:5]3720; SI-NEXT:    s_setpc_b64 s[30:31]3721;3722; VI-LABEL: bitcast_v2i32_to_f64:3723; VI:       ; %bb.0:3724; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3725; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v23726; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc3727; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]3728; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]3729; VI-NEXT:  ; %bb.1: ; %cmp.true3730; VI-NEXT:    v_add_u32_e32 v1, vcc, 3, v13731; VI-NEXT:    v_add_u32_e32 v0, vcc, 3, v03732; VI-NEXT:  ; %bb.2: ; %end3733; VI-NEXT:    s_or_b64 exec, exec, s[4:5]3734; VI-NEXT:    s_setpc_b64 s[30:31]3735;3736; GFX9-LABEL: bitcast_v2i32_to_f64:3737; GFX9:       ; %bb.0:3738; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3739; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v23740; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc3741; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]3742; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]3743; GFX9-NEXT:  ; %bb.1: ; %cmp.true3744; GFX9-NEXT:    v_add_u32_e32 v1, 3, v13745; GFX9-NEXT:    v_add_u32_e32 v0, 3, v03746; GFX9-NEXT:  ; %bb.2: ; %end3747; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]3748; GFX9-NEXT:    s_setpc_b64 s[30:31]3749;3750; GFX11-LABEL: bitcast_v2i32_to_f64:3751; GFX11:       ; %bb.0:3752; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3753; GFX11-NEXT:    s_mov_b32 s0, exec_lo3754; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v23755; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s03756; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)3757; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s03758; GFX11-NEXT:  ; %bb.1: ; %cmp.true3759; GFX11-NEXT:    v_add_nc_u32_e32 v1, 3, v13760; GFX11-NEXT:    v_add_nc_u32_e32 v0, 3, v03761; GFX11-NEXT:  ; %bb.2: ; %end3762; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s03763; GFX11-NEXT:    s_setpc_b64 s[30:31]3764  %cmp = icmp eq i32 %b, 03765  br i1 %cmp, label %cmp.true, label %cmp.false3766 3767cmp.true:3768  %a1 = add <2 x i32> %a, splat (i32 3)3769  %a2 = bitcast <2 x i32> %a1 to double3770  br label %end3771 3772cmp.false:3773  %a3 = bitcast <2 x i32> %a to double3774  br label %end3775 3776end:3777  %phi = phi double [ %a2, %cmp.true ], [ %a3, %cmp.false ]3778  ret double %phi3779}3780 3781define inreg double @bitcast_v2i32_to_f64_scalar(<2 x i32> inreg %a, i32 inreg %b) {3782; SI-LABEL: bitcast_v2i32_to_f64_scalar:3783; SI:       ; %bb.0:3784; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3785; SI-NEXT:    s_cmp_lg_u32 s18, 03786; SI-NEXT:    s_cbranch_scc0 .LBB31_43787; SI-NEXT:  ; %bb.1: ; %cmp.false3788; SI-NEXT:    s_cbranch_execnz .LBB31_33789; SI-NEXT:  .LBB31_2: ; %cmp.true3790; SI-NEXT:    s_add_i32 s17, s17, 33791; SI-NEXT:    s_add_i32 s16, s16, 33792; SI-NEXT:  .LBB31_3: ; %end3793; SI-NEXT:    v_mov_b32_e32 v0, s163794; SI-NEXT:    v_mov_b32_e32 v1, s173795; SI-NEXT:    s_setpc_b64 s[30:31]3796; SI-NEXT:  .LBB31_4:3797; SI-NEXT:    s_branch .LBB31_23798;3799; VI-LABEL: bitcast_v2i32_to_f64_scalar:3800; VI:       ; %bb.0:3801; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3802; VI-NEXT:    s_cmp_lg_u32 s18, 03803; VI-NEXT:    s_cbranch_scc0 .LBB31_43804; VI-NEXT:  ; %bb.1: ; %cmp.false3805; VI-NEXT:    s_cbranch_execnz .LBB31_33806; VI-NEXT:  .LBB31_2: ; %cmp.true3807; VI-NEXT:    s_add_i32 s17, s17, 33808; VI-NEXT:    s_add_i32 s16, s16, 33809; VI-NEXT:  .LBB31_3: ; %end3810; VI-NEXT:    v_mov_b32_e32 v0, s163811; VI-NEXT:    v_mov_b32_e32 v1, s173812; VI-NEXT:    s_setpc_b64 s[30:31]3813; VI-NEXT:  .LBB31_4:3814; VI-NEXT:    s_branch .LBB31_23815;3816; GFX9-LABEL: bitcast_v2i32_to_f64_scalar:3817; GFX9:       ; %bb.0:3818; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3819; GFX9-NEXT:    s_cmp_lg_u32 s18, 03820; GFX9-NEXT:    s_cbranch_scc0 .LBB31_43821; GFX9-NEXT:  ; %bb.1: ; %cmp.false3822; GFX9-NEXT:    s_cbranch_execnz .LBB31_33823; GFX9-NEXT:  .LBB31_2: ; %cmp.true3824; GFX9-NEXT:    s_add_i32 s17, s17, 33825; GFX9-NEXT:    s_add_i32 s16, s16, 33826; GFX9-NEXT:  .LBB31_3: ; %end3827; GFX9-NEXT:    v_mov_b32_e32 v0, s163828; GFX9-NEXT:    v_mov_b32_e32 v1, s173829; GFX9-NEXT:    s_setpc_b64 s[30:31]3830; GFX9-NEXT:  .LBB31_4:3831; GFX9-NEXT:    s_branch .LBB31_23832;3833; GFX11-LABEL: bitcast_v2i32_to_f64_scalar:3834; GFX11:       ; %bb.0:3835; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3836; GFX11-NEXT:    s_cmp_lg_u32 s2, 03837; GFX11-NEXT:    s_mov_b32 s2, 03838; GFX11-NEXT:    s_cbranch_scc0 .LBB31_43839; GFX11-NEXT:  ; %bb.1: ; %Flow3840; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s23841; GFX11-NEXT:    s_cbranch_vccnz .LBB31_33842; GFX11-NEXT:  .LBB31_2: ; %cmp.true3843; GFX11-NEXT:    s_add_i32 s1, s1, 33844; GFX11-NEXT:    s_add_i32 s0, s0, 33845; GFX11-NEXT:  .LBB31_3: ; %end3846; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)3847; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s13848; GFX11-NEXT:    s_setpc_b64 s[30:31]3849; GFX11-NEXT:  .LBB31_4:3850; GFX11-NEXT:    s_branch .LBB31_23851  %cmp = icmp eq i32 %b, 03852  br i1 %cmp, label %cmp.true, label %cmp.false3853 3854cmp.true:3855  %a1 = add <2 x i32> %a, splat (i32 3)3856  %a2 = bitcast <2 x i32> %a1 to double3857  br label %end3858 3859cmp.false:3860  %a3 = bitcast <2 x i32> %a to double3861  br label %end3862 3863end:3864  %phi = phi double [ %a2, %cmp.true ], [ %a3, %cmp.false ]3865  ret double %phi3866}3867 3868define <2 x float> @bitcast_f64_to_v2f32(double %a, i32 %b) {3869; SI-LABEL: bitcast_f64_to_v2f32:3870; SI:       ; %bb.0:3871; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3872; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v23873; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc3874; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]3875; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]3876; SI-NEXT:  ; %bb.1: ; %cmp.true3877; SI-NEXT:    v_add_f64 v[0:1], v[0:1], 1.03878; SI-NEXT:  ; %bb.2: ; %end3879; SI-NEXT:    s_or_b64 exec, exec, s[4:5]3880; SI-NEXT:    s_setpc_b64 s[30:31]3881;3882; VI-LABEL: bitcast_f64_to_v2f32:3883; VI:       ; %bb.0:3884; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3885; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v23886; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc3887; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]3888; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]3889; VI-NEXT:  ; %bb.1: ; %cmp.true3890; VI-NEXT:    v_add_f64 v[0:1], v[0:1], 1.03891; VI-NEXT:  ; %bb.2: ; %end3892; VI-NEXT:    s_or_b64 exec, exec, s[4:5]3893; VI-NEXT:    s_setpc_b64 s[30:31]3894;3895; GFX9-LABEL: bitcast_f64_to_v2f32:3896; GFX9:       ; %bb.0:3897; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3898; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v23899; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc3900; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]3901; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]3902; GFX9-NEXT:  ; %bb.1: ; %cmp.true3903; GFX9-NEXT:    v_add_f64 v[0:1], v[0:1], 1.03904; GFX9-NEXT:  ; %bb.2: ; %end3905; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]3906; GFX9-NEXT:    s_setpc_b64 s[30:31]3907;3908; GFX11-LABEL: bitcast_f64_to_v2f32:3909; GFX11:       ; %bb.0:3910; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3911; GFX11-NEXT:    s_mov_b32 s0, exec_lo3912; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v23913; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s03914; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)3915; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s03916; GFX11-NEXT:    s_cbranch_execz .LBB32_23917; GFX11-NEXT:  ; %bb.1: ; %cmp.true3918; GFX11-NEXT:    v_add_f64 v[0:1], v[0:1], 1.03919; GFX11-NEXT:  .LBB32_2: ; %end3920; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s03921; GFX11-NEXT:    s_setpc_b64 s[30:31]3922  %cmp = icmp eq i32 %b, 03923  br i1 %cmp, label %cmp.true, label %cmp.false3924 3925cmp.true:3926  %a1 = fadd double %a, 1.000000e+003927  %a2 = bitcast double %a1 to <2 x float>3928  br label %end3929 3930cmp.false:3931  %a3 = bitcast double %a to <2 x float>3932  br label %end3933 3934end:3935  %phi = phi <2 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]3936  ret <2 x float> %phi3937}3938 3939define inreg <2 x float> @bitcast_f64_to_v2f32_scalar(double inreg %a, i32 inreg %b) {3940; SI-LABEL: bitcast_f64_to_v2f32_scalar:3941; SI:       ; %bb.0:3942; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3943; SI-NEXT:    s_cmp_lg_u32 s18, 03944; SI-NEXT:    s_cbranch_scc0 .LBB33_33945; SI-NEXT:  ; %bb.1: ; %cmp.false3946; SI-NEXT:    s_cbranch_execnz .LBB33_43947; SI-NEXT:  .LBB33_2: ; %cmp.true3948; SI-NEXT:    v_add_f64 v[0:1], s[16:17], 1.03949; SI-NEXT:    s_setpc_b64 s[30:31]3950; SI-NEXT:  .LBB33_3:3951; SI-NEXT:    s_branch .LBB33_23952; SI-NEXT:  .LBB33_4:3953; SI-NEXT:    v_mov_b32_e32 v0, s163954; SI-NEXT:    v_mov_b32_e32 v1, s173955; SI-NEXT:    s_setpc_b64 s[30:31]3956;3957; VI-LABEL: bitcast_f64_to_v2f32_scalar:3958; VI:       ; %bb.0:3959; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3960; VI-NEXT:    s_cmp_lg_u32 s18, 03961; VI-NEXT:    s_cbranch_scc0 .LBB33_33962; VI-NEXT:  ; %bb.1: ; %cmp.false3963; VI-NEXT:    s_cbranch_execnz .LBB33_43964; VI-NEXT:  .LBB33_2: ; %cmp.true3965; VI-NEXT:    v_add_f64 v[0:1], s[16:17], 1.03966; VI-NEXT:    s_setpc_b64 s[30:31]3967; VI-NEXT:  .LBB33_3:3968; VI-NEXT:    s_branch .LBB33_23969; VI-NEXT:  .LBB33_4:3970; VI-NEXT:    v_mov_b32_e32 v0, s163971; VI-NEXT:    v_mov_b32_e32 v1, s173972; VI-NEXT:    s_setpc_b64 s[30:31]3973;3974; GFX9-LABEL: bitcast_f64_to_v2f32_scalar:3975; GFX9:       ; %bb.0:3976; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3977; GFX9-NEXT:    s_cmp_lg_u32 s18, 03978; GFX9-NEXT:    s_cbranch_scc0 .LBB33_33979; GFX9-NEXT:  ; %bb.1: ; %cmp.false3980; GFX9-NEXT:    s_cbranch_execnz .LBB33_43981; GFX9-NEXT:  .LBB33_2: ; %cmp.true3982; GFX9-NEXT:    v_add_f64 v[0:1], s[16:17], 1.03983; GFX9-NEXT:    s_setpc_b64 s[30:31]3984; GFX9-NEXT:  .LBB33_3:3985; GFX9-NEXT:    s_branch .LBB33_23986; GFX9-NEXT:  .LBB33_4:3987; GFX9-NEXT:    v_mov_b32_e32 v0, s163988; GFX9-NEXT:    v_mov_b32_e32 v1, s173989; GFX9-NEXT:    s_setpc_b64 s[30:31]3990;3991; GFX11-LABEL: bitcast_f64_to_v2f32_scalar:3992; GFX11:       ; %bb.0:3993; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3994; GFX11-NEXT:    s_cmp_lg_u32 s2, 03995; GFX11-NEXT:    s_mov_b32 s2, 03996; GFX11-NEXT:    s_cbranch_scc0 .LBB33_33997; GFX11-NEXT:  ; %bb.1: ; %Flow3998; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s23999; GFX11-NEXT:    s_cbranch_vccnz .LBB33_44000; GFX11-NEXT:  .LBB33_2: ; %cmp.true4001; GFX11-NEXT:    v_add_f64 v[0:1], s[0:1], 1.04002; GFX11-NEXT:    s_setpc_b64 s[30:31]4003; GFX11-NEXT:  .LBB33_3:4004; GFX11-NEXT:    s_branch .LBB33_24005; GFX11-NEXT:  .LBB33_4:4006; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s14007; GFX11-NEXT:    s_setpc_b64 s[30:31]4008  %cmp = icmp eq i32 %b, 04009  br i1 %cmp, label %cmp.true, label %cmp.false4010 4011cmp.true:4012  %a1 = fadd double %a, 1.000000e+004013  %a2 = bitcast double %a1 to <2 x float>4014  br label %end4015 4016cmp.false:4017  %a3 = bitcast double %a to <2 x float>4018  br label %end4019 4020end:4021  %phi = phi <2 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]4022  ret <2 x float> %phi4023}4024 4025define double @bitcast_v2f32_to_f64(<2 x float> %a, i32 %b) {4026; SI-LABEL: bitcast_v2f32_to_f64:4027; SI:       ; %bb.0:4028; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4029; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v24030; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc4031; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]4032; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]4033; SI-NEXT:  ; %bb.1: ; %cmp.true4034; SI-NEXT:    v_add_f32_e32 v1, 1.0, v14035; SI-NEXT:    v_add_f32_e32 v0, 1.0, v04036; SI-NEXT:  ; %bb.2: ; %end4037; SI-NEXT:    s_or_b64 exec, exec, s[4:5]4038; SI-NEXT:    s_setpc_b64 s[30:31]4039;4040; VI-LABEL: bitcast_v2f32_to_f64:4041; VI:       ; %bb.0:4042; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4043; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v24044; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc4045; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]4046; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]4047; VI-NEXT:  ; %bb.1: ; %cmp.true4048; VI-NEXT:    v_add_f32_e32 v1, 1.0, v14049; VI-NEXT:    v_add_f32_e32 v0, 1.0, v04050; VI-NEXT:  ; %bb.2: ; %end4051; VI-NEXT:    s_or_b64 exec, exec, s[4:5]4052; VI-NEXT:    s_setpc_b64 s[30:31]4053;4054; GFX9-LABEL: bitcast_v2f32_to_f64:4055; GFX9:       ; %bb.0:4056; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4057; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v24058; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc4059; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]4060; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]4061; GFX9-NEXT:  ; %bb.1: ; %cmp.true4062; GFX9-NEXT:    v_add_f32_e32 v1, 1.0, v14063; GFX9-NEXT:    v_add_f32_e32 v0, 1.0, v04064; GFX9-NEXT:  ; %bb.2: ; %end4065; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]4066; GFX9-NEXT:    s_setpc_b64 s[30:31]4067;4068; GFX11-LABEL: bitcast_v2f32_to_f64:4069; GFX11:       ; %bb.0:4070; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4071; GFX11-NEXT:    s_mov_b32 s0, exec_lo4072; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v24073; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s04074; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)4075; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s04076; GFX11-NEXT:  ; %bb.1: ; %cmp.true4077; GFX11-NEXT:    v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v04078; GFX11-NEXT:  ; %bb.2: ; %end4079; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s04080; GFX11-NEXT:    s_setpc_b64 s[30:31]4081  %cmp = icmp eq i32 %b, 04082  br i1 %cmp, label %cmp.true, label %cmp.false4083 4084cmp.true:4085  %a1 = fadd <2 x float> %a, splat (float 1.000000e+00)4086  %a2 = bitcast <2 x float> %a1 to double4087  br label %end4088 4089cmp.false:4090  %a3 = bitcast <2 x float> %a to double4091  br label %end4092 4093end:4094  %phi = phi double [ %a2, %cmp.true ], [ %a3, %cmp.false ]4095  ret double %phi4096}4097 4098define inreg double @bitcast_v2f32_to_f64_scalar(<2 x float> inreg %a, i32 inreg %b) {4099; SI-LABEL: bitcast_v2f32_to_f64_scalar:4100; SI:       ; %bb.0:4101; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4102; SI-NEXT:    s_cmp_lg_u32 s18, 04103; SI-NEXT:    s_cbranch_scc0 .LBB35_34104; SI-NEXT:  ; %bb.1: ; %cmp.false4105; SI-NEXT:    s_cbranch_execnz .LBB35_44106; SI-NEXT:  .LBB35_2: ; %cmp.true4107; SI-NEXT:    v_add_f32_e64 v1, s17, 1.04108; SI-NEXT:    v_add_f32_e64 v0, s16, 1.04109; SI-NEXT:    s_setpc_b64 s[30:31]4110; SI-NEXT:  .LBB35_3:4111; SI-NEXT:    s_branch .LBB35_24112; SI-NEXT:  .LBB35_4:4113; SI-NEXT:    v_mov_b32_e32 v0, s164114; SI-NEXT:    v_mov_b32_e32 v1, s174115; SI-NEXT:    s_setpc_b64 s[30:31]4116;4117; VI-LABEL: bitcast_v2f32_to_f64_scalar:4118; VI:       ; %bb.0:4119; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4120; VI-NEXT:    s_cmp_lg_u32 s18, 04121; VI-NEXT:    s_cbranch_scc0 .LBB35_34122; VI-NEXT:  ; %bb.1: ; %cmp.false4123; VI-NEXT:    s_cbranch_execnz .LBB35_44124; VI-NEXT:  .LBB35_2: ; %cmp.true4125; VI-NEXT:    v_add_f32_e64 v1, s17, 1.04126; VI-NEXT:    v_add_f32_e64 v0, s16, 1.04127; VI-NEXT:    s_setpc_b64 s[30:31]4128; VI-NEXT:  .LBB35_3:4129; VI-NEXT:    s_branch .LBB35_24130; VI-NEXT:  .LBB35_4:4131; VI-NEXT:    v_mov_b32_e32 v0, s164132; VI-NEXT:    v_mov_b32_e32 v1, s174133; VI-NEXT:    s_setpc_b64 s[30:31]4134;4135; GFX9-LABEL: bitcast_v2f32_to_f64_scalar:4136; GFX9:       ; %bb.0:4137; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4138; GFX9-NEXT:    s_cmp_lg_u32 s18, 04139; GFX9-NEXT:    s_cbranch_scc0 .LBB35_34140; GFX9-NEXT:  ; %bb.1: ; %cmp.false4141; GFX9-NEXT:    s_cbranch_execnz .LBB35_44142; GFX9-NEXT:  .LBB35_2: ; %cmp.true4143; GFX9-NEXT:    v_add_f32_e64 v1, s17, 1.04144; GFX9-NEXT:    v_add_f32_e64 v0, s16, 1.04145; GFX9-NEXT:    s_setpc_b64 s[30:31]4146; GFX9-NEXT:  .LBB35_3:4147; GFX9-NEXT:    s_branch .LBB35_24148; GFX9-NEXT:  .LBB35_4:4149; GFX9-NEXT:    v_mov_b32_e32 v0, s164150; GFX9-NEXT:    v_mov_b32_e32 v1, s174151; GFX9-NEXT:    s_setpc_b64 s[30:31]4152;4153; GFX11-LABEL: bitcast_v2f32_to_f64_scalar:4154; GFX11:       ; %bb.0:4155; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4156; GFX11-NEXT:    s_cmp_lg_u32 s2, 04157; GFX11-NEXT:    s_mov_b32 s2, 04158; GFX11-NEXT:    s_cbranch_scc0 .LBB35_34159; GFX11-NEXT:  ; %bb.1: ; %Flow4160; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s24161; GFX11-NEXT:    s_cbranch_vccnz .LBB35_44162; GFX11-NEXT:  .LBB35_2: ; %cmp.true4163; GFX11-NEXT:    v_add_f32_e64 v1, s1, 1.04164; GFX11-NEXT:    v_add_f32_e64 v0, s0, 1.04165; GFX11-NEXT:    s_setpc_b64 s[30:31]4166; GFX11-NEXT:  .LBB35_3:4167; GFX11-NEXT:    s_branch .LBB35_24168; GFX11-NEXT:  .LBB35_4:4169; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s14170; GFX11-NEXT:    s_setpc_b64 s[30:31]4171  %cmp = icmp eq i32 %b, 04172  br i1 %cmp, label %cmp.true, label %cmp.false4173 4174cmp.true:4175  %a1 = fadd <2 x float> %a, splat (float 1.000000e+00)4176  %a2 = bitcast <2 x float> %a1 to double4177  br label %end4178 4179cmp.false:4180  %a3 = bitcast <2 x float> %a to double4181  br label %end4182 4183end:4184  %phi = phi double [ %a2, %cmp.true ], [ %a3, %cmp.false ]4185  ret double %phi4186}4187 4188define <4 x i16> @bitcast_f64_to_v4i16(double %a, i32 %b) {4189; SI-LABEL: bitcast_f64_to_v4i16:4190; SI:       ; %bb.0:4191; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4192; SI-NEXT:    v_mov_b32_e32 v5, v14193; SI-NEXT:    v_mov_b32_e32 v4, v04194; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v24195; SI-NEXT:    ; implicit-def: $vgpr14196; SI-NEXT:    ; implicit-def: $vgpr34197; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc4198; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]4199; SI-NEXT:  ; %bb.1: ; %cmp.false4200; SI-NEXT:    v_alignbit_b32 v1, v5, v4, 164201; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v54202; SI-NEXT:  ; %bb.2: ; %Flow4203; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]4204; SI-NEXT:  ; %bb.3: ; %cmp.true4205; SI-NEXT:    v_add_f64 v[4:5], v[4:5], 1.04206; SI-NEXT:    v_alignbit_b32 v1, v5, v4, 164207; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v54208; SI-NEXT:  ; %bb.4: ; %end4209; SI-NEXT:    s_or_b64 exec, exec, s[4:5]4210; SI-NEXT:    v_mov_b32_e32 v0, v44211; SI-NEXT:    v_mov_b32_e32 v2, v54212; SI-NEXT:    s_setpc_b64 s[30:31]4213;4214; VI-LABEL: bitcast_f64_to_v4i16:4215; VI:       ; %bb.0:4216; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4217; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v24218; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc4219; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]4220; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]4221; VI-NEXT:  ; %bb.1: ; %cmp.true4222; VI-NEXT:    v_add_f64 v[0:1], v[0:1], 1.04223; VI-NEXT:  ; %bb.2: ; %end4224; VI-NEXT:    s_or_b64 exec, exec, s[4:5]4225; VI-NEXT:    s_setpc_b64 s[30:31]4226;4227; GFX9-LABEL: bitcast_f64_to_v4i16:4228; GFX9:       ; %bb.0:4229; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4230; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v24231; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc4232; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]4233; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]4234; GFX9-NEXT:  ; %bb.1: ; %cmp.true4235; GFX9-NEXT:    v_add_f64 v[0:1], v[0:1], 1.04236; GFX9-NEXT:  ; %bb.2: ; %end4237; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]4238; GFX9-NEXT:    s_setpc_b64 s[30:31]4239;4240; GFX11-LABEL: bitcast_f64_to_v4i16:4241; GFX11:       ; %bb.0:4242; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4243; GFX11-NEXT:    s_mov_b32 s0, exec_lo4244; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v24245; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s04246; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)4247; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s04248; GFX11-NEXT:    s_cbranch_execz .LBB36_24249; GFX11-NEXT:  ; %bb.1: ; %cmp.true4250; GFX11-NEXT:    v_add_f64 v[0:1], v[0:1], 1.04251; GFX11-NEXT:  .LBB36_2: ; %end4252; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s04253; GFX11-NEXT:    s_setpc_b64 s[30:31]4254  %cmp = icmp eq i32 %b, 04255  br i1 %cmp, label %cmp.true, label %cmp.false4256 4257cmp.true:4258  %a1 = fadd double %a, 1.000000e+004259  %a2 = bitcast double %a1 to <4 x i16>4260  br label %end4261 4262cmp.false:4263  %a3 = bitcast double %a to <4 x i16>4264  br label %end4265 4266end:4267  %phi = phi <4 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]4268  ret <4 x i16> %phi4269}4270 4271define inreg <4 x i16> @bitcast_f64_to_v4i16_scalar(double inreg %a, i32 inreg %b) {4272; SI-LABEL: bitcast_f64_to_v4i16_scalar:4273; SI:       ; %bb.0:4274; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4275; SI-NEXT:    s_cmp_lg_u32 s18, 04276; SI-NEXT:    s_cbranch_scc0 .LBB37_34277; SI-NEXT:  ; %bb.1: ; %cmp.false4278; SI-NEXT:    s_lshr_b32 s8, s17, 164279; SI-NEXT:    s_lshr_b64 s[4:5], s[16:17], 164280; SI-NEXT:    s_cbranch_execnz .LBB37_44281; SI-NEXT:  .LBB37_2: ; %cmp.true4282; SI-NEXT:    v_add_f64 v[4:5], s[16:17], 1.04283; SI-NEXT:    v_lshr_b64 v[1:2], v[4:5], 164284; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v54285; SI-NEXT:    s_branch .LBB37_54286; SI-NEXT:  .LBB37_3:4287; SI-NEXT:    ; implicit-def: $sgpr44288; SI-NEXT:    ; implicit-def: $sgpr84289; SI-NEXT:    s_branch .LBB37_24290; SI-NEXT:  .LBB37_4:4291; SI-NEXT:    v_mov_b32_e32 v5, s174292; SI-NEXT:    v_mov_b32_e32 v4, s164293; SI-NEXT:    v_mov_b32_e32 v3, s84294; SI-NEXT:    v_mov_b32_e32 v1, s44295; SI-NEXT:  .LBB37_5: ; %end4296; SI-NEXT:    v_mov_b32_e32 v0, v44297; SI-NEXT:    v_mov_b32_e32 v2, v54298; SI-NEXT:    s_setpc_b64 s[30:31]4299;4300; VI-LABEL: bitcast_f64_to_v4i16_scalar:4301; VI:       ; %bb.0:4302; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4303; VI-NEXT:    s_cmp_lg_u32 s18, 04304; VI-NEXT:    s_cbranch_scc0 .LBB37_34305; VI-NEXT:  ; %bb.1: ; %cmp.false4306; VI-NEXT:    s_cbranch_execnz .LBB37_44307; VI-NEXT:  .LBB37_2: ; %cmp.true4308; VI-NEXT:    v_add_f64 v[0:1], s[16:17], 1.04309; VI-NEXT:    s_setpc_b64 s[30:31]4310; VI-NEXT:  .LBB37_3:4311; VI-NEXT:    s_branch .LBB37_24312; VI-NEXT:  .LBB37_4:4313; VI-NEXT:    v_mov_b32_e32 v0, s164314; VI-NEXT:    v_mov_b32_e32 v1, s174315; VI-NEXT:    s_setpc_b64 s[30:31]4316;4317; GFX9-LABEL: bitcast_f64_to_v4i16_scalar:4318; GFX9:       ; %bb.0:4319; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4320; GFX9-NEXT:    s_cmp_lg_u32 s18, 04321; GFX9-NEXT:    s_cbranch_scc0 .LBB37_34322; GFX9-NEXT:  ; %bb.1: ; %cmp.false4323; GFX9-NEXT:    s_cbranch_execnz .LBB37_44324; GFX9-NEXT:  .LBB37_2: ; %cmp.true4325; GFX9-NEXT:    v_add_f64 v[0:1], s[16:17], 1.04326; GFX9-NEXT:    s_setpc_b64 s[30:31]4327; GFX9-NEXT:  .LBB37_3:4328; GFX9-NEXT:    s_branch .LBB37_24329; GFX9-NEXT:  .LBB37_4:4330; GFX9-NEXT:    v_mov_b32_e32 v0, s164331; GFX9-NEXT:    v_mov_b32_e32 v1, s174332; GFX9-NEXT:    s_setpc_b64 s[30:31]4333;4334; GFX11-LABEL: bitcast_f64_to_v4i16_scalar:4335; GFX11:       ; %bb.0:4336; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4337; GFX11-NEXT:    s_cmp_lg_u32 s2, 04338; GFX11-NEXT:    s_mov_b32 s2, 04339; GFX11-NEXT:    s_cbranch_scc0 .LBB37_34340; GFX11-NEXT:  ; %bb.1: ; %Flow4341; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s24342; GFX11-NEXT:    s_cbranch_vccnz .LBB37_44343; GFX11-NEXT:  .LBB37_2: ; %cmp.true4344; GFX11-NEXT:    v_add_f64 v[0:1], s[0:1], 1.04345; GFX11-NEXT:    s_setpc_b64 s[30:31]4346; GFX11-NEXT:  .LBB37_3:4347; GFX11-NEXT:    s_branch .LBB37_24348; GFX11-NEXT:  .LBB37_4:4349; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s14350; GFX11-NEXT:    s_setpc_b64 s[30:31]4351  %cmp = icmp eq i32 %b, 04352  br i1 %cmp, label %cmp.true, label %cmp.false4353 4354cmp.true:4355  %a1 = fadd double %a, 1.000000e+004356  %a2 = bitcast double %a1 to <4 x i16>4357  br label %end4358 4359cmp.false:4360  %a3 = bitcast double %a to <4 x i16>4361  br label %end4362 4363end:4364  %phi = phi <4 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]4365  ret <4 x i16> %phi4366}4367 4368define double @bitcast_v4i16_to_f64(<4 x i16> %a, i32 %b) {4369; SI-LABEL: bitcast_v4i16_to_f64:4370; SI:       ; %bb.0:4371; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4372; SI-NEXT:    v_mov_b32_e32 v5, v04373; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v44374; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v14375; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v34376; SI-NEXT:    ; implicit-def: $vgpr0_vgpr14377; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc4378; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]4379; SI-NEXT:    s_cbranch_execnz .LBB38_34380; SI-NEXT:  ; %bb.1: ; %Flow4381; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]4382; SI-NEXT:    s_cbranch_execnz .LBB38_44383; SI-NEXT:  .LBB38_2: ; %end4384; SI-NEXT:    s_or_b64 exec, exec, s[4:5]4385; SI-NEXT:    s_setpc_b64 s[30:31]4386; SI-NEXT:  .LBB38_3: ; %cmp.false4387; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v54388; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v24389; SI-NEXT:    v_or_b32_e32 v0, v0, v44390; SI-NEXT:    v_or_b32_e32 v1, v1, v34391; SI-NEXT:    ; implicit-def: $vgpr54392; SI-NEXT:    ; implicit-def: $vgpr44393; SI-NEXT:    ; implicit-def: $vgpr24394; SI-NEXT:    ; implicit-def: $vgpr34395; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]4396; SI-NEXT:    s_cbranch_execz .LBB38_24397; SI-NEXT:  .LBB38_4: ; %cmp.true4398; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v54399; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v24400; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v04401; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v14402; SI-NEXT:    v_or_b32_e32 v0, v4, v04403; SI-NEXT:    v_or_b32_e32 v1, v3, v14404; SI-NEXT:    v_add_i32_e32 v0, vcc, 0x30000, v04405; SI-NEXT:    v_add_i32_e32 v1, vcc, 0x30000, v14406; SI-NEXT:    s_or_b64 exec, exec, s[4:5]4407; SI-NEXT:    s_setpc_b64 s[30:31]4408;4409; VI-LABEL: bitcast_v4i16_to_f64:4410; VI:       ; %bb.0:4411; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4412; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v24413; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc4414; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]4415; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]4416; VI-NEXT:  ; %bb.1: ; %cmp.true4417; VI-NEXT:    v_mov_b32_e32 v3, 34418; VI-NEXT:    v_add_u16_e32 v2, 3, v14419; VI-NEXT:    v_add_u16_sdwa v1, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4420; VI-NEXT:    v_or_b32_e32 v1, v2, v14421; VI-NEXT:    v_add_u16_e32 v2, 3, v04422; VI-NEXT:    v_add_u16_sdwa v0, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4423; VI-NEXT:    v_or_b32_e32 v0, v2, v04424; VI-NEXT:  ; %bb.2: ; %end4425; VI-NEXT:    s_or_b64 exec, exec, s[4:5]4426; VI-NEXT:    s_setpc_b64 s[30:31]4427;4428; GFX9-LABEL: bitcast_v4i16_to_f64:4429; GFX9:       ; %bb.0:4430; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4431; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v24432; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc4433; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]4434; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]4435; GFX9-NEXT:  ; %bb.1: ; %cmp.true4436; GFX9-NEXT:    v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]4437; GFX9-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]4438; GFX9-NEXT:  ; %bb.2: ; %end4439; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]4440; GFX9-NEXT:    s_setpc_b64 s[30:31]4441;4442; GFX11-LABEL: bitcast_v4i16_to_f64:4443; GFX11:       ; %bb.0:4444; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4445; GFX11-NEXT:    s_mov_b32 s0, exec_lo4446; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v24447; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s04448; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)4449; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s04450; GFX11-NEXT:  ; %bb.1: ; %cmp.true4451; GFX11-NEXT:    v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]4452; GFX11-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]4453; GFX11-NEXT:  ; %bb.2: ; %end4454; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s04455; GFX11-NEXT:    s_setpc_b64 s[30:31]4456  %cmp = icmp eq i32 %b, 04457  br i1 %cmp, label %cmp.true, label %cmp.false4458 4459cmp.true:4460  %a1 = add <4 x i16> %a, splat (i16 3)4461  %a2 = bitcast <4 x i16> %a1 to double4462  br label %end4463 4464cmp.false:4465  %a3 = bitcast <4 x i16> %a to double4466  br label %end4467 4468end:4469  %phi = phi double [ %a2, %cmp.true ], [ %a3, %cmp.false ]4470  ret double %phi4471}4472 4473define inreg double @bitcast_v4i16_to_f64_scalar(<4 x i16> inreg %a, i32 inreg %b) {4474; SI-LABEL: bitcast_v4i16_to_f64_scalar:4475; SI:       ; %bb.0:4476; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4477; SI-NEXT:    s_cmp_lg_u32 s20, 04478; SI-NEXT:    s_cbranch_scc0 .LBB39_44479; SI-NEXT:  ; %bb.1: ; %cmp.false4480; SI-NEXT:    s_and_b32 s4, s16, 0xffff4481; SI-NEXT:    s_lshl_b32 s5, s17, 164482; SI-NEXT:    s_or_b32 s4, s4, s54483; SI-NEXT:    s_and_b32 s5, s18, 0xffff4484; SI-NEXT:    s_lshl_b32 s6, s19, 164485; SI-NEXT:    s_or_b32 s5, s5, s64486; SI-NEXT:    s_cbranch_execnz .LBB39_34487; SI-NEXT:  .LBB39_2: ; %cmp.true4488; SI-NEXT:    s_add_i32 s16, s16, 34489; SI-NEXT:    s_and_b32 s4, s16, 0xffff4490; SI-NEXT:    s_lshl_b32 s5, s17, 164491; SI-NEXT:    s_add_i32 s18, s18, 34492; SI-NEXT:    s_or_b32 s4, s5, s44493; SI-NEXT:    s_and_b32 s5, s18, 0xffff4494; SI-NEXT:    s_lshl_b32 s6, s19, 164495; SI-NEXT:    s_or_b32 s5, s6, s54496; SI-NEXT:    s_add_i32 s4, s4, 0x300004497; SI-NEXT:    s_add_i32 s5, s5, 0x300004498; SI-NEXT:  .LBB39_3: ; %end4499; SI-NEXT:    v_mov_b32_e32 v0, s44500; SI-NEXT:    v_mov_b32_e32 v1, s54501; SI-NEXT:    s_setpc_b64 s[30:31]4502; SI-NEXT:  .LBB39_4:4503; SI-NEXT:    ; implicit-def: $sgpr4_sgpr54504; SI-NEXT:    s_branch .LBB39_24505;4506; VI-LABEL: bitcast_v4i16_to_f64_scalar:4507; VI:       ; %bb.0:4508; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4509; VI-NEXT:    s_cmp_lg_u32 s18, 04510; VI-NEXT:    s_cbranch_scc0 .LBB39_44511; VI-NEXT:  ; %bb.1: ; %cmp.false4512; VI-NEXT:    s_cbranch_execnz .LBB39_34513; VI-NEXT:  .LBB39_2: ; %cmp.true4514; VI-NEXT:    s_add_i32 s5, s17, 34515; VI-NEXT:    s_and_b32 s4, s17, 0xffff00004516; VI-NEXT:    s_and_b32 s5, s5, 0xffff4517; VI-NEXT:    s_or_b32 s4, s4, s54518; VI-NEXT:    s_add_i32 s5, s16, 34519; VI-NEXT:    s_add_i32 s17, s4, 0x300004520; VI-NEXT:    s_and_b32 s4, s16, 0xffff00004521; VI-NEXT:    s_and_b32 s5, s5, 0xffff4522; VI-NEXT:    s_or_b32 s4, s4, s54523; VI-NEXT:    s_add_i32 s16, s4, 0x300004524; VI-NEXT:  .LBB39_3: ; %end4525; VI-NEXT:    v_mov_b32_e32 v0, s164526; VI-NEXT:    v_mov_b32_e32 v1, s174527; VI-NEXT:    s_setpc_b64 s[30:31]4528; VI-NEXT:  .LBB39_4:4529; VI-NEXT:    s_branch .LBB39_24530;4531; GFX9-LABEL: bitcast_v4i16_to_f64_scalar:4532; GFX9:       ; %bb.0:4533; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4534; GFX9-NEXT:    s_cmp_lg_u32 s18, 04535; GFX9-NEXT:    s_cbranch_scc0 .LBB39_34536; GFX9-NEXT:  ; %bb.1: ; %cmp.false4537; GFX9-NEXT:    s_cbranch_execnz .LBB39_44538; GFX9-NEXT:  .LBB39_2: ; %cmp.true4539; GFX9-NEXT:    v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]4540; GFX9-NEXT:    v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]4541; GFX9-NEXT:    s_setpc_b64 s[30:31]4542; GFX9-NEXT:  .LBB39_3:4543; GFX9-NEXT:    s_branch .LBB39_24544; GFX9-NEXT:  .LBB39_4:4545; GFX9-NEXT:    v_mov_b32_e32 v0, s164546; GFX9-NEXT:    v_mov_b32_e32 v1, s174547; GFX9-NEXT:    s_setpc_b64 s[30:31]4548;4549; GFX11-LABEL: bitcast_v4i16_to_f64_scalar:4550; GFX11:       ; %bb.0:4551; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4552; GFX11-NEXT:    s_cmp_lg_u32 s2, 04553; GFX11-NEXT:    s_mov_b32 s2, 04554; GFX11-NEXT:    s_cbranch_scc0 .LBB39_34555; GFX11-NEXT:  ; %bb.1: ; %Flow4556; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s24557; GFX11-NEXT:    s_cbranch_vccnz .LBB39_44558; GFX11-NEXT:  .LBB39_2: ; %cmp.true4559; GFX11-NEXT:    v_pk_add_u16 v1, s1, 3 op_sel_hi:[1,0]4560; GFX11-NEXT:    v_pk_add_u16 v0, s0, 3 op_sel_hi:[1,0]4561; GFX11-NEXT:    s_setpc_b64 s[30:31]4562; GFX11-NEXT:  .LBB39_3:4563; GFX11-NEXT:    s_branch .LBB39_24564; GFX11-NEXT:  .LBB39_4:4565; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s14566; GFX11-NEXT:    s_setpc_b64 s[30:31]4567  %cmp = icmp eq i32 %b, 04568  br i1 %cmp, label %cmp.true, label %cmp.false4569 4570cmp.true:4571  %a1 = add <4 x i16> %a, splat (i16 3)4572  %a2 = bitcast <4 x i16> %a1 to double4573  br label %end4574 4575cmp.false:4576  %a3 = bitcast <4 x i16> %a to double4577  br label %end4578 4579end:4580  %phi = phi double [ %a2, %cmp.true ], [ %a3, %cmp.false ]4581  ret double %phi4582}4583 4584define <4 x half> @bitcast_f64_to_v4f16(double %a, i32 %b) {4585; SI-LABEL: bitcast_f64_to_v4f16:4586; SI:       ; %bb.0:4587; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4588; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v24589; SI-NEXT:    ; implicit-def: $vgpr44590; SI-NEXT:    ; implicit-def: $vgpr54591; SI-NEXT:    ; implicit-def: $vgpr24592; SI-NEXT:    ; implicit-def: $vgpr34593; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc4594; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]4595; SI-NEXT:    s_cbranch_execz .LBB40_24596; SI-NEXT:  ; %bb.1: ; %cmp.false4597; SI-NEXT:    v_lshrrev_b32_e32 v2, 16, v14598; SI-NEXT:    v_cvt_f32_f16_e32 v3, v24599; SI-NEXT:    v_lshrrev_b32_e32 v2, 16, v04600; SI-NEXT:    v_cvt_f32_f16_e32 v5, v24601; SI-NEXT:    v_cvt_f32_f16_e32 v2, v14602; SI-NEXT:    v_cvt_f32_f16_e32 v4, v04603; SI-NEXT:    ; implicit-def: $vgpr0_vgpr14604; SI-NEXT:  .LBB40_2: ; %Flow4605; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]4606; SI-NEXT:    s_cbranch_execz .LBB40_44607; SI-NEXT:  ; %bb.3: ; %cmp.true4608; SI-NEXT:    v_add_f64 v[0:1], v[0:1], 1.04609; SI-NEXT:    v_lshrrev_b32_e32 v5, 16, v04610; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v14611; SI-NEXT:    v_cvt_f32_f16_e32 v2, v14612; SI-NEXT:    v_cvt_f32_f16_e32 v4, v04613; SI-NEXT:    v_cvt_f32_f16_e32 v3, v34614; SI-NEXT:    v_cvt_f32_f16_e32 v5, v54615; SI-NEXT:  .LBB40_4: ; %end4616; SI-NEXT:    s_or_b64 exec, exec, s[4:5]4617; SI-NEXT:    v_mov_b32_e32 v0, v44618; SI-NEXT:    v_mov_b32_e32 v1, v54619; SI-NEXT:    s_setpc_b64 s[30:31]4620;4621; VI-LABEL: bitcast_f64_to_v4f16:4622; VI:       ; %bb.0:4623; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4624; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v24625; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc4626; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]4627; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]4628; VI-NEXT:  ; %bb.1: ; %cmp.true4629; VI-NEXT:    v_add_f64 v[0:1], v[0:1], 1.04630; VI-NEXT:  ; %bb.2: ; %end4631; VI-NEXT:    s_or_b64 exec, exec, s[4:5]4632; VI-NEXT:    s_setpc_b64 s[30:31]4633;4634; GFX9-LABEL: bitcast_f64_to_v4f16:4635; GFX9:       ; %bb.0:4636; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4637; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v24638; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc4639; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]4640; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]4641; GFX9-NEXT:  ; %bb.1: ; %cmp.true4642; GFX9-NEXT:    v_add_f64 v[0:1], v[0:1], 1.04643; GFX9-NEXT:  ; %bb.2: ; %end4644; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]4645; GFX9-NEXT:    s_setpc_b64 s[30:31]4646;4647; GFX11-LABEL: bitcast_f64_to_v4f16:4648; GFX11:       ; %bb.0:4649; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4650; GFX11-NEXT:    s_mov_b32 s0, exec_lo4651; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v24652; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s04653; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)4654; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s04655; GFX11-NEXT:    s_cbranch_execz .LBB40_24656; GFX11-NEXT:  ; %bb.1: ; %cmp.true4657; GFX11-NEXT:    v_add_f64 v[0:1], v[0:1], 1.04658; GFX11-NEXT:  .LBB40_2: ; %end4659; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s04660; GFX11-NEXT:    s_setpc_b64 s[30:31]4661  %cmp = icmp eq i32 %b, 04662  br i1 %cmp, label %cmp.true, label %cmp.false4663 4664cmp.true:4665  %a1 = fadd double %a, 1.000000e+004666  %a2 = bitcast double %a1 to <4 x half>4667  br label %end4668 4669cmp.false:4670  %a3 = bitcast double %a to <4 x half>4671  br label %end4672 4673end:4674  %phi = phi <4 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]4675  ret <4 x half> %phi4676}4677 4678define inreg <4 x half> @bitcast_f64_to_v4f16_scalar(double inreg %a, i32 inreg %b) {4679; SI-LABEL: bitcast_f64_to_v4f16_scalar:4680; SI:       ; %bb.0:4681; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4682; SI-NEXT:    s_cmp_lg_u32 s18, 04683; SI-NEXT:    s_cbranch_scc0 .LBB41_44684; SI-NEXT:  ; %bb.1: ; %cmp.false4685; SI-NEXT:    s_lshr_b32 s4, s17, 164686; SI-NEXT:    v_cvt_f32_f16_e32 v3, s44687; SI-NEXT:    s_lshr_b32 s4, s16, 164688; SI-NEXT:    v_cvt_f32_f16_e32 v1, s44689; SI-NEXT:    v_cvt_f32_f16_e32 v2, s174690; SI-NEXT:    v_cvt_f32_f16_e32 v0, s164691; SI-NEXT:    s_cbranch_execnz .LBB41_34692; SI-NEXT:  .LBB41_2: ; %cmp.true4693; SI-NEXT:    v_add_f64 v[0:1], s[16:17], 1.04694; SI-NEXT:    v_lshrrev_b32_e32 v4, 16, v04695; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v14696; SI-NEXT:    v_cvt_f32_f16_e32 v2, v14697; SI-NEXT:    v_cvt_f32_f16_e32 v0, v04698; SI-NEXT:    v_cvt_f32_f16_e32 v3, v34699; SI-NEXT:    v_cvt_f32_f16_e32 v1, v44700; SI-NEXT:  .LBB41_3: ; %end4701; SI-NEXT:    s_setpc_b64 s[30:31]4702; SI-NEXT:  .LBB41_4:4703; SI-NEXT:    ; implicit-def: $vgpr04704; SI-NEXT:    ; implicit-def: $vgpr14705; SI-NEXT:    ; implicit-def: $vgpr24706; SI-NEXT:    ; implicit-def: $vgpr34707; SI-NEXT:    s_branch .LBB41_24708;4709; VI-LABEL: bitcast_f64_to_v4f16_scalar:4710; VI:       ; %bb.0:4711; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4712; VI-NEXT:    s_cmp_lg_u32 s18, 04713; VI-NEXT:    s_cbranch_scc0 .LBB41_34714; VI-NEXT:  ; %bb.1: ; %cmp.false4715; VI-NEXT:    s_cbranch_execnz .LBB41_44716; VI-NEXT:  .LBB41_2: ; %cmp.true4717; VI-NEXT:    v_add_f64 v[0:1], s[16:17], 1.04718; VI-NEXT:    s_setpc_b64 s[30:31]4719; VI-NEXT:  .LBB41_3:4720; VI-NEXT:    s_branch .LBB41_24721; VI-NEXT:  .LBB41_4:4722; VI-NEXT:    v_mov_b32_e32 v0, s164723; VI-NEXT:    v_mov_b32_e32 v1, s174724; VI-NEXT:    s_setpc_b64 s[30:31]4725;4726; GFX9-LABEL: bitcast_f64_to_v4f16_scalar:4727; GFX9:       ; %bb.0:4728; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4729; GFX9-NEXT:    s_cmp_lg_u32 s18, 04730; GFX9-NEXT:    s_cbranch_scc0 .LBB41_34731; GFX9-NEXT:  ; %bb.1: ; %cmp.false4732; GFX9-NEXT:    s_cbranch_execnz .LBB41_44733; GFX9-NEXT:  .LBB41_2: ; %cmp.true4734; GFX9-NEXT:    v_add_f64 v[0:1], s[16:17], 1.04735; GFX9-NEXT:    s_setpc_b64 s[30:31]4736; GFX9-NEXT:  .LBB41_3:4737; GFX9-NEXT:    s_branch .LBB41_24738; GFX9-NEXT:  .LBB41_4:4739; GFX9-NEXT:    v_mov_b32_e32 v0, s164740; GFX9-NEXT:    v_mov_b32_e32 v1, s174741; GFX9-NEXT:    s_setpc_b64 s[30:31]4742;4743; GFX11-LABEL: bitcast_f64_to_v4f16_scalar:4744; GFX11:       ; %bb.0:4745; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4746; GFX11-NEXT:    s_cmp_lg_u32 s2, 04747; GFX11-NEXT:    s_mov_b32 s2, 04748; GFX11-NEXT:    s_cbranch_scc0 .LBB41_34749; GFX11-NEXT:  ; %bb.1: ; %Flow4750; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s24751; GFX11-NEXT:    s_cbranch_vccnz .LBB41_44752; GFX11-NEXT:  .LBB41_2: ; %cmp.true4753; GFX11-NEXT:    v_add_f64 v[0:1], s[0:1], 1.04754; GFX11-NEXT:    s_setpc_b64 s[30:31]4755; GFX11-NEXT:  .LBB41_3:4756; GFX11-NEXT:    s_branch .LBB41_24757; GFX11-NEXT:  .LBB41_4:4758; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s14759; GFX11-NEXT:    s_setpc_b64 s[30:31]4760  %cmp = icmp eq i32 %b, 04761  br i1 %cmp, label %cmp.true, label %cmp.false4762 4763cmp.true:4764  %a1 = fadd double %a, 1.000000e+004765  %a2 = bitcast double %a1 to <4 x half>4766  br label %end4767 4768cmp.false:4769  %a3 = bitcast double %a to <4 x half>4770  br label %end4771 4772end:4773  %phi = phi <4 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]4774  ret <4 x half> %phi4775}4776 4777define double @bitcast_v4f16_to_f64(<4 x half> %a, i32 %b) {4778; SI-LABEL: bitcast_v4f16_to_f64:4779; SI:       ; %bb.0:4780; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4781; SI-NEXT:    v_cvt_f16_f32_e32 v6, v14782; SI-NEXT:    v_cvt_f16_f32_e32 v5, v04783; SI-NEXT:    v_cvt_f16_f32_e32 v3, v34784; SI-NEXT:    v_cvt_f16_f32_e32 v2, v24785; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v44786; SI-NEXT:    ; implicit-def: $vgpr0_vgpr14787; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc4788; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]4789; SI-NEXT:    s_cbranch_execnz .LBB42_34790; SI-NEXT:  ; %bb.1: ; %Flow4791; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]4792; SI-NEXT:    s_cbranch_execnz .LBB42_44793; SI-NEXT:  .LBB42_2: ; %end4794; SI-NEXT:    s_or_b64 exec, exec, s[4:5]4795; SI-NEXT:    s_setpc_b64 s[30:31]4796; SI-NEXT:  .LBB42_3: ; %cmp.false4797; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v64798; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v34799; SI-NEXT:    v_or_b32_e32 v0, v5, v04800; SI-NEXT:    v_or_b32_e32 v1, v2, v14801; SI-NEXT:    ; implicit-def: $vgpr64802; SI-NEXT:    ; implicit-def: $vgpr54803; SI-NEXT:    ; implicit-def: $vgpr34804; SI-NEXT:    ; implicit-def: $vgpr24805; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]4806; SI-NEXT:    s_cbranch_execz .LBB42_24807; SI-NEXT:  .LBB42_4: ; %cmp.true4808; SI-NEXT:    v_cvt_f32_f16_e32 v0, v64809; SI-NEXT:    v_cvt_f32_f16_e32 v1, v54810; SI-NEXT:    v_cvt_f32_f16_e32 v3, v34811; SI-NEXT:    v_cvt_f32_f16_e32 v2, v24812; SI-NEXT:    v_add_f32_e32 v0, 0x38000000, v04813; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v14814; SI-NEXT:    v_cvt_f16_f32_e32 v0, v04815; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v34816; SI-NEXT:    v_cvt_f16_f32_e32 v1, v14817; SI-NEXT:    v_cvt_f16_f32_e32 v3, v34818; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v24819; SI-NEXT:    v_cvt_f16_f32_e32 v2, v24820; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v04821; SI-NEXT:    v_or_b32_e32 v0, v1, v04822; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v34823; SI-NEXT:    v_or_b32_e32 v1, v2, v14824; SI-NEXT:    s_or_b64 exec, exec, s[4:5]4825; SI-NEXT:    s_setpc_b64 s[30:31]4826;4827; VI-LABEL: bitcast_v4f16_to_f64:4828; VI:       ; %bb.0:4829; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4830; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v24831; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc4832; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]4833; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]4834; VI-NEXT:  ; %bb.1: ; %cmp.true4835; VI-NEXT:    v_mov_b32_e32 v2, 0x2004836; VI-NEXT:    v_add_f16_sdwa v3, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4837; VI-NEXT:    v_add_f16_e32 v1, 0x200, v14838; VI-NEXT:    v_add_f16_sdwa v2, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4839; VI-NEXT:    v_add_f16_e32 v0, 0x200, v04840; VI-NEXT:    v_or_b32_e32 v1, v1, v34841; VI-NEXT:    v_or_b32_e32 v0, v0, v24842; VI-NEXT:  ; %bb.2: ; %end4843; VI-NEXT:    s_or_b64 exec, exec, s[4:5]4844; VI-NEXT:    s_setpc_b64 s[30:31]4845;4846; GFX9-LABEL: bitcast_v4f16_to_f64:4847; GFX9:       ; %bb.0:4848; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4849; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v24850; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc4851; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]4852; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]4853; GFX9-NEXT:  ; %bb.1: ; %cmp.true4854; GFX9-NEXT:    s_movk_i32 s6, 0x2004855; GFX9-NEXT:    v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]4856; GFX9-NEXT:    v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]4857; GFX9-NEXT:  ; %bb.2: ; %end4858; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]4859; GFX9-NEXT:    s_setpc_b64 s[30:31]4860;4861; GFX11-LABEL: bitcast_v4f16_to_f64:4862; GFX11:       ; %bb.0:4863; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4864; GFX11-NEXT:    s_mov_b32 s0, exec_lo4865; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v24866; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s04867; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)4868; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s04869; GFX11-NEXT:  ; %bb.1: ; %cmp.true4870; GFX11-NEXT:    v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]4871; GFX11-NEXT:    v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]4872; GFX11-NEXT:  ; %bb.2: ; %end4873; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s04874; GFX11-NEXT:    s_setpc_b64 s[30:31]4875  %cmp = icmp eq i32 %b, 04876  br i1 %cmp, label %cmp.true, label %cmp.false4877 4878cmp.true:4879  %a1 = fadd <4 x half> %a, splat (half 0xH0200)4880  %a2 = bitcast <4 x half> %a1 to double4881  br label %end4882 4883cmp.false:4884  %a3 = bitcast <4 x half> %a to double4885  br label %end4886 4887end:4888  %phi = phi double [ %a2, %cmp.true ], [ %a3, %cmp.false ]4889  ret double %phi4890}4891 4892define inreg double @bitcast_v4f16_to_f64_scalar(<4 x half> inreg %a, i32 inreg %b) {4893; SI-LABEL: bitcast_v4f16_to_f64_scalar:4894; SI:       ; %bb.0:4895; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4896; SI-NEXT:    v_cvt_f16_f32_e32 v5, s174897; SI-NEXT:    v_cvt_f16_f32_e32 v4, s164898; SI-NEXT:    v_cvt_f16_f32_e32 v3, s194899; SI-NEXT:    v_cvt_f16_f32_e32 v2, s184900; SI-NEXT:    s_cmp_lg_u32 s20, 04901; SI-NEXT:    s_cbranch_scc0 .LBB43_44902; SI-NEXT:  ; %bb.1: ; %cmp.false4903; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v54904; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v34905; SI-NEXT:    v_or_b32_e32 v0, v4, v04906; SI-NEXT:    v_or_b32_e32 v1, v2, v14907; SI-NEXT:    s_cbranch_execnz .LBB43_34908; SI-NEXT:  .LBB43_2: ; %cmp.true4909; SI-NEXT:    v_cvt_f32_f16_e32 v0, v54910; SI-NEXT:    v_cvt_f32_f16_e32 v1, v44911; SI-NEXT:    v_cvt_f32_f16_e32 v3, v34912; SI-NEXT:    v_cvt_f32_f16_e32 v2, v24913; SI-NEXT:    v_add_f32_e32 v0, 0x38000000, v04914; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v14915; SI-NEXT:    v_cvt_f16_f32_e32 v0, v04916; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v34917; SI-NEXT:    v_cvt_f16_f32_e32 v1, v14918; SI-NEXT:    v_cvt_f16_f32_e32 v3, v34919; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v24920; SI-NEXT:    v_cvt_f16_f32_e32 v2, v24921; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v04922; SI-NEXT:    v_or_b32_e32 v0, v1, v04923; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v34924; SI-NEXT:    v_or_b32_e32 v1, v2, v14925; SI-NEXT:  .LBB43_3: ; %end4926; SI-NEXT:    s_setpc_b64 s[30:31]4927; SI-NEXT:  .LBB43_4:4928; SI-NEXT:    ; implicit-def: $vgpr0_vgpr14929; SI-NEXT:    s_branch .LBB43_24930;4931; VI-LABEL: bitcast_v4f16_to_f64_scalar:4932; VI:       ; %bb.0:4933; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4934; VI-NEXT:    s_cmp_lg_u32 s18, 04935; VI-NEXT:    s_cbranch_scc0 .LBB43_34936; VI-NEXT:  ; %bb.1: ; %cmp.false4937; VI-NEXT:    s_cbranch_execnz .LBB43_44938; VI-NEXT:  .LBB43_2: ; %cmp.true4939; VI-NEXT:    s_lshr_b32 s4, s17, 164940; VI-NEXT:    v_mov_b32_e32 v0, 0x2004941; VI-NEXT:    v_mov_b32_e32 v1, s44942; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD4943; VI-NEXT:    v_add_f16_e32 v2, s17, v04944; VI-NEXT:    s_lshr_b32 s4, s16, 164945; VI-NEXT:    v_or_b32_e32 v1, v2, v14946; VI-NEXT:    v_mov_b32_e32 v2, s44947; VI-NEXT:    v_add_f16_sdwa v2, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD4948; VI-NEXT:    v_add_f16_e32 v0, s16, v04949; VI-NEXT:    v_or_b32_e32 v0, v0, v24950; VI-NEXT:    s_setpc_b64 s[30:31]4951; VI-NEXT:  .LBB43_3:4952; VI-NEXT:    s_branch .LBB43_24953; VI-NEXT:  .LBB43_4:4954; VI-NEXT:    v_mov_b32_e32 v0, s164955; VI-NEXT:    v_mov_b32_e32 v1, s174956; VI-NEXT:    s_setpc_b64 s[30:31]4957;4958; GFX9-LABEL: bitcast_v4f16_to_f64_scalar:4959; GFX9:       ; %bb.0:4960; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4961; GFX9-NEXT:    s_cmp_lg_u32 s18, 04962; GFX9-NEXT:    s_cbranch_scc0 .LBB43_34963; GFX9-NEXT:  ; %bb.1: ; %cmp.false4964; GFX9-NEXT:    s_cbranch_execnz .LBB43_44965; GFX9-NEXT:  .LBB43_2: ; %cmp.true4966; GFX9-NEXT:    v_mov_b32_e32 v0, 0x2004967; GFX9-NEXT:    v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]4968; GFX9-NEXT:    v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]4969; GFX9-NEXT:    s_setpc_b64 s[30:31]4970; GFX9-NEXT:  .LBB43_3:4971; GFX9-NEXT:    s_branch .LBB43_24972; GFX9-NEXT:  .LBB43_4:4973; GFX9-NEXT:    v_mov_b32_e32 v0, s164974; GFX9-NEXT:    v_mov_b32_e32 v1, s174975; GFX9-NEXT:    s_setpc_b64 s[30:31]4976;4977; GFX11-LABEL: bitcast_v4f16_to_f64_scalar:4978; GFX11:       ; %bb.0:4979; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4980; GFX11-NEXT:    s_cmp_lg_u32 s2, 04981; GFX11-NEXT:    s_mov_b32 s2, 04982; GFX11-NEXT:    s_cbranch_scc0 .LBB43_34983; GFX11-NEXT:  ; %bb.1: ; %Flow4984; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s24985; GFX11-NEXT:    s_cbranch_vccnz .LBB43_44986; GFX11-NEXT:  .LBB43_2: ; %cmp.true4987; GFX11-NEXT:    v_pk_add_f16 v1, 0x200, s1 op_sel_hi:[0,1]4988; GFX11-NEXT:    v_pk_add_f16 v0, 0x200, s0 op_sel_hi:[0,1]4989; GFX11-NEXT:    s_setpc_b64 s[30:31]4990; GFX11-NEXT:  .LBB43_3:4991; GFX11-NEXT:    s_branch .LBB43_24992; GFX11-NEXT:  .LBB43_4:4993; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s14994; GFX11-NEXT:    s_setpc_b64 s[30:31]4995  %cmp = icmp eq i32 %b, 04996  br i1 %cmp, label %cmp.true, label %cmp.false4997 4998cmp.true:4999  %a1 = fadd <4 x half> %a, splat (half 0xH0200)5000  %a2 = bitcast <4 x half> %a1 to double5001  br label %end5002 5003cmp.false:5004  %a3 = bitcast <4 x half> %a to double5005  br label %end5006 5007end:5008  %phi = phi double [ %a2, %cmp.true ], [ %a3, %cmp.false ]5009  ret double %phi5010}5011 5012define <4 x bfloat> @bitcast_f64_to_v4bf16(double %a, i32 %b) {5013; SI-LABEL: bitcast_f64_to_v4bf16:5014; SI:       ; %bb.0:5015; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5016; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v25017; SI-NEXT:    ; implicit-def: $vgpr55018; SI-NEXT:    ; implicit-def: $vgpr45019; SI-NEXT:    ; implicit-def: $vgpr25020; SI-NEXT:    ; implicit-def: $vgpr35021; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc5022; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]5023; SI-NEXT:  ; %bb.1: ; %cmp.false5024; SI-NEXT:    v_and_b32_e32 v3, 0xffff0000, v15025; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v15026; SI-NEXT:    v_and_b32_e32 v4, 0xffff0000, v05027; SI-NEXT:    v_lshlrev_b32_e32 v5, 16, v05028; SI-NEXT:    ; implicit-def: $vgpr0_vgpr15029; SI-NEXT:  ; %bb.2: ; %Flow5030; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]5031; SI-NEXT:  ; %bb.3: ; %cmp.true5032; SI-NEXT:    v_add_f64 v[0:1], v[0:1], 1.05033; SI-NEXT:    v_and_b32_e32 v3, 0xffff0000, v15034; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v15035; SI-NEXT:    v_and_b32_e32 v4, 0xffff0000, v05036; SI-NEXT:    v_lshlrev_b32_e32 v5, 16, v05037; SI-NEXT:  ; %bb.4: ; %end5038; SI-NEXT:    s_or_b64 exec, exec, s[4:5]5039; SI-NEXT:    v_mov_b32_e32 v0, v55040; SI-NEXT:    v_mov_b32_e32 v1, v45041; SI-NEXT:    s_setpc_b64 s[30:31]5042;5043; VI-LABEL: bitcast_f64_to_v4bf16:5044; VI:       ; %bb.0:5045; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5046; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v25047; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc5048; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]5049; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]5050; VI-NEXT:  ; %bb.1: ; %cmp.true5051; VI-NEXT:    v_add_f64 v[0:1], v[0:1], 1.05052; VI-NEXT:  ; %bb.2: ; %end5053; VI-NEXT:    s_or_b64 exec, exec, s[4:5]5054; VI-NEXT:    s_setpc_b64 s[30:31]5055;5056; GFX9-LABEL: bitcast_f64_to_v4bf16:5057; GFX9:       ; %bb.0:5058; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5059; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v25060; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc5061; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]5062; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]5063; GFX9-NEXT:  ; %bb.1: ; %cmp.true5064; GFX9-NEXT:    v_add_f64 v[0:1], v[0:1], 1.05065; GFX9-NEXT:  ; %bb.2: ; %end5066; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]5067; GFX9-NEXT:    s_setpc_b64 s[30:31]5068;5069; GFX11-LABEL: bitcast_f64_to_v4bf16:5070; GFX11:       ; %bb.0:5071; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5072; GFX11-NEXT:    s_mov_b32 s0, exec_lo5073; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v25074; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s05075; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)5076; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s05077; GFX11-NEXT:    s_cbranch_execz .LBB44_25078; GFX11-NEXT:  ; %bb.1: ; %cmp.true5079; GFX11-NEXT:    v_add_f64 v[0:1], v[0:1], 1.05080; GFX11-NEXT:  .LBB44_2: ; %end5081; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s05082; GFX11-NEXT:    s_setpc_b64 s[30:31]5083  %cmp = icmp eq i32 %b, 05084  br i1 %cmp, label %cmp.true, label %cmp.false5085 5086cmp.true:5087  %a1 = fadd double %a, 1.000000e+005088  %a2 = bitcast double %a1 to <4 x bfloat>5089  br label %end5090 5091cmp.false:5092  %a3 = bitcast double %a to <4 x bfloat>5093  br label %end5094 5095end:5096  %phi = phi <4 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ]5097  ret <4 x bfloat> %phi5098}5099 5100define inreg <4 x bfloat> @bitcast_f64_to_v4bf16_scalar(double inreg %a, i32 inreg %b) {5101; SI-LABEL: bitcast_f64_to_v4bf16_scalar:5102; SI:       ; %bb.0:5103; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5104; SI-NEXT:    s_cmp_lg_u32 s18, 05105; SI-NEXT:    s_cbranch_scc0 .LBB45_35106; SI-NEXT:  ; %bb.1: ; %cmp.false5107; SI-NEXT:    s_and_b32 s9, s17, 0xffff00005108; SI-NEXT:    s_lshl_b32 s8, s17, 165109; SI-NEXT:    s_and_b32 s7, s16, 0xffff00005110; SI-NEXT:    s_lshl_b32 s6, s16, 165111; SI-NEXT:    s_cbranch_execnz .LBB45_45112; SI-NEXT:  .LBB45_2: ; %cmp.true5113; SI-NEXT:    v_add_f64 v[0:1], s[16:17], 1.05114; SI-NEXT:    v_and_b32_e32 v3, 0xffff0000, v15115; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v15116; SI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v05117; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v05118; SI-NEXT:    s_setpc_b64 s[30:31]5119; SI-NEXT:  .LBB45_3:5120; SI-NEXT:    ; implicit-def: $sgpr65121; SI-NEXT:    ; implicit-def: $sgpr75122; SI-NEXT:    ; implicit-def: $sgpr85123; SI-NEXT:    ; implicit-def: $sgpr95124; SI-NEXT:    s_branch .LBB45_25125; SI-NEXT:  .LBB45_4:5126; SI-NEXT:    v_mov_b32_e32 v3, s95127; SI-NEXT:    v_mov_b32_e32 v2, s85128; SI-NEXT:    v_mov_b32_e32 v1, s75129; SI-NEXT:    v_mov_b32_e32 v0, s65130; SI-NEXT:    s_setpc_b64 s[30:31]5131;5132; VI-LABEL: bitcast_f64_to_v4bf16_scalar:5133; VI:       ; %bb.0:5134; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5135; VI-NEXT:    s_cmp_lg_u32 s18, 05136; VI-NEXT:    s_cbranch_scc0 .LBB45_35137; VI-NEXT:  ; %bb.1: ; %cmp.false5138; VI-NEXT:    s_cbranch_execnz .LBB45_45139; VI-NEXT:  .LBB45_2: ; %cmp.true5140; VI-NEXT:    v_add_f64 v[0:1], s[16:17], 1.05141; VI-NEXT:    s_setpc_b64 s[30:31]5142; VI-NEXT:  .LBB45_3:5143; VI-NEXT:    s_branch .LBB45_25144; VI-NEXT:  .LBB45_4:5145; VI-NEXT:    v_mov_b32_e32 v0, s165146; VI-NEXT:    v_mov_b32_e32 v1, s175147; VI-NEXT:    s_setpc_b64 s[30:31]5148;5149; GFX9-LABEL: bitcast_f64_to_v4bf16_scalar:5150; GFX9:       ; %bb.0:5151; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5152; GFX9-NEXT:    s_cmp_lg_u32 s18, 05153; GFX9-NEXT:    s_cbranch_scc0 .LBB45_35154; GFX9-NEXT:  ; %bb.1: ; %cmp.false5155; GFX9-NEXT:    s_cbranch_execnz .LBB45_45156; GFX9-NEXT:  .LBB45_2: ; %cmp.true5157; GFX9-NEXT:    v_add_f64 v[0:1], s[16:17], 1.05158; GFX9-NEXT:    s_setpc_b64 s[30:31]5159; GFX9-NEXT:  .LBB45_3:5160; GFX9-NEXT:    s_branch .LBB45_25161; GFX9-NEXT:  .LBB45_4:5162; GFX9-NEXT:    v_mov_b32_e32 v0, s165163; GFX9-NEXT:    v_mov_b32_e32 v1, s175164; GFX9-NEXT:    s_setpc_b64 s[30:31]5165;5166; GFX11-LABEL: bitcast_f64_to_v4bf16_scalar:5167; GFX11:       ; %bb.0:5168; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5169; GFX11-NEXT:    s_cmp_lg_u32 s2, 05170; GFX11-NEXT:    s_mov_b32 s2, 05171; GFX11-NEXT:    s_cbranch_scc0 .LBB45_35172; GFX11-NEXT:  ; %bb.1: ; %Flow5173; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s25174; GFX11-NEXT:    s_cbranch_vccnz .LBB45_45175; GFX11-NEXT:  .LBB45_2: ; %cmp.true5176; GFX11-NEXT:    v_add_f64 v[0:1], s[0:1], 1.05177; GFX11-NEXT:    s_setpc_b64 s[30:31]5178; GFX11-NEXT:  .LBB45_3:5179; GFX11-NEXT:    s_branch .LBB45_25180; GFX11-NEXT:  .LBB45_4:5181; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s15182; GFX11-NEXT:    s_setpc_b64 s[30:31]5183  %cmp = icmp eq i32 %b, 05184  br i1 %cmp, label %cmp.true, label %cmp.false5185 5186cmp.true:5187  %a1 = fadd double %a, 1.000000e+005188  %a2 = bitcast double %a1 to <4 x bfloat>5189  br label %end5190 5191cmp.false:5192  %a3 = bitcast double %a to <4 x bfloat>5193  br label %end5194 5195end:5196  %phi = phi <4 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ]5197  ret <4 x bfloat> %phi5198}5199 5200define double @bitcast_v4bf16_to_f64(<4 x bfloat> %a, i32 %b) {5201; SI-LABEL: bitcast_v4bf16_to_f64:5202; SI:       ; %bb.0:5203; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5204; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v45205; SI-NEXT:    v_mul_f32_e32 v4, 1.0, v15206; SI-NEXT:    v_mul_f32_e32 v5, 1.0, v05207; SI-NEXT:    v_mul_f32_e32 v3, 1.0, v35208; SI-NEXT:    v_mul_f32_e32 v2, 1.0, v25209; SI-NEXT:    ; implicit-def: $vgpr0_vgpr15210; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc5211; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]5212; SI-NEXT:    s_cbranch_execnz .LBB46_35213; SI-NEXT:  ; %bb.1: ; %Flow5214; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]5215; SI-NEXT:    s_cbranch_execnz .LBB46_45216; SI-NEXT:  .LBB46_2: ; %end5217; SI-NEXT:    s_or_b64 exec, exec, s[4:5]5218; SI-NEXT:    s_setpc_b64 s[30:31]5219; SI-NEXT:  .LBB46_3: ; %cmp.false5220; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v45221; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v35222; SI-NEXT:    v_alignbit_b32 v0, v0, v5, 165223; SI-NEXT:    v_alignbit_b32 v1, v1, v2, 165224; SI-NEXT:    ; implicit-def: $vgpr55225; SI-NEXT:    ; implicit-def: $vgpr45226; SI-NEXT:    ; implicit-def: $vgpr25227; SI-NEXT:    ; implicit-def: $vgpr35228; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]5229; SI-NEXT:    s_cbranch_execz .LBB46_25230; SI-NEXT:  .LBB46_4: ; %cmp.true5231; SI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v45232; SI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v55233; SI-NEXT:    v_add_f32_e32 v1, 0x40c00000, v15234; SI-NEXT:    v_add_f32_e32 v0, 0x40c00000, v05235; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v15236; SI-NEXT:    v_alignbit_b32 v0, v1, v0, 165237; SI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v25238; SI-NEXT:    v_and_b32_e32 v2, 0xffff0000, v35239; SI-NEXT:    v_add_f32_e32 v2, 0x40c00000, v25240; SI-NEXT:    v_add_f32_e32 v1, 0x40c00000, v15241; SI-NEXT:    v_lshrrev_b32_e32 v2, 16, v25242; SI-NEXT:    v_alignbit_b32 v1, v2, v1, 165243; SI-NEXT:    s_or_b64 exec, exec, s[4:5]5244; SI-NEXT:    s_setpc_b64 s[30:31]5245;5246; VI-LABEL: bitcast_v4bf16_to_f64:5247; VI:       ; %bb.0:5248; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5249; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v25250; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc5251; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]5252; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]5253; VI-NEXT:    s_cbranch_execz .LBB46_25254; VI-NEXT:  ; %bb.1: ; %cmp.true5255; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v15256; VI-NEXT:    v_add_f32_e32 v2, 0x40c00000, v25257; VI-NEXT:    v_bfe_u32 v3, v2, 16, 15258; VI-NEXT:    v_add_u32_e32 v3, vcc, v3, v25259; VI-NEXT:    v_add_u32_e32 v3, vcc, 0x7fff, v35260; VI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v15261; VI-NEXT:    v_or_b32_e32 v4, 0x400000, v25262; VI-NEXT:    v_cmp_u_f32_e32 vcc, v2, v25263; VI-NEXT:    v_add_f32_e32 v1, 0x40c00000, v15264; VI-NEXT:    v_cndmask_b32_e32 v2, v3, v4, vcc5265; VI-NEXT:    v_bfe_u32 v3, v1, 16, 15266; VI-NEXT:    s_movk_i32 s6, 0x7fff5267; VI-NEXT:    v_add_u32_e32 v3, vcc, v3, v15268; VI-NEXT:    v_add_u32_e32 v3, vcc, s6, v35269; VI-NEXT:    v_or_b32_e32 v4, 0x400000, v15270; VI-NEXT:    v_cmp_u_f32_e32 vcc, v1, v15271; VI-NEXT:    v_cndmask_b32_e32 v1, v3, v4, vcc5272; VI-NEXT:    v_lshrrev_b32_e32 v1, 16, v15273; VI-NEXT:    v_alignbit_b32 v1, v1, v2, 165274; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v05275; VI-NEXT:    v_add_f32_e32 v2, 0x40c00000, v25276; VI-NEXT:    v_bfe_u32 v3, v2, 16, 15277; VI-NEXT:    v_add_u32_e32 v3, vcc, v3, v25278; VI-NEXT:    v_add_u32_e32 v3, vcc, s6, v35279; VI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v05280; VI-NEXT:    v_or_b32_e32 v4, 0x400000, v25281; VI-NEXT:    v_cmp_u_f32_e32 vcc, v2, v25282; VI-NEXT:    v_add_f32_e32 v0, 0x40c00000, v05283; VI-NEXT:    v_cndmask_b32_e32 v2, v3, v4, vcc5284; VI-NEXT:    v_bfe_u32 v3, v0, 16, 15285; VI-NEXT:    v_add_u32_e32 v3, vcc, v3, v05286; VI-NEXT:    v_add_u32_e32 v3, vcc, 0x7fff, v35287; VI-NEXT:    v_or_b32_e32 v4, 0x400000, v05288; VI-NEXT:    v_cmp_u_f32_e32 vcc, v0, v05289; VI-NEXT:    v_cndmask_b32_e32 v0, v3, v4, vcc5290; VI-NEXT:    v_lshrrev_b32_e32 v0, 16, v05291; VI-NEXT:    v_alignbit_b32 v0, v0, v2, 165292; VI-NEXT:  .LBB46_2: ; %end5293; VI-NEXT:    s_or_b64 exec, exec, s[4:5]5294; VI-NEXT:    s_setpc_b64 s[30:31]5295;5296; GFX9-LABEL: bitcast_v4bf16_to_f64:5297; GFX9:       ; %bb.0:5298; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5299; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v25300; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc5301; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]5302; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]5303; GFX9-NEXT:    s_cbranch_execz .LBB46_25304; GFX9-NEXT:  ; %bb.1: ; %cmp.true5305; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 16, v05306; GFX9-NEXT:    v_add_f32_e32 v2, 0x40c00000, v25307; GFX9-NEXT:    v_bfe_u32 v3, v2, 16, 15308; GFX9-NEXT:    s_movk_i32 s6, 0x7fff5309; GFX9-NEXT:    v_and_b32_e32 v0, 0xffff0000, v05310; GFX9-NEXT:    v_add3_u32 v3, v3, v2, s65311; GFX9-NEXT:    v_or_b32_e32 v4, 0x400000, v25312; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v2, v25313; GFX9-NEXT:    v_add_f32_e32 v0, 0x40c00000, v05314; GFX9-NEXT:    v_cndmask_b32_e32 v2, v3, v4, vcc5315; GFX9-NEXT:    v_bfe_u32 v3, v0, 16, 15316; GFX9-NEXT:    v_add3_u32 v3, v3, v0, s65317; GFX9-NEXT:    v_or_b32_e32 v4, 0x400000, v05318; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v0, v05319; GFX9-NEXT:    v_cndmask_b32_e32 v0, v3, v4, vcc5320; GFX9-NEXT:    s_mov_b32 s7, 0x70603025321; GFX9-NEXT:    v_perm_b32 v0, v0, v2, s75322; GFX9-NEXT:    v_and_b32_e32 v2, 0xffff0000, v15323; GFX9-NEXT:    v_add_f32_e32 v2, 0x40c00000, v25324; GFX9-NEXT:    v_bfe_u32 v3, v2, 16, 15325; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 16, v15326; GFX9-NEXT:    v_add3_u32 v3, v3, v2, s65327; GFX9-NEXT:    v_or_b32_e32 v4, 0x400000, v25328; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v2, v25329; GFX9-NEXT:    v_add_f32_e32 v1, 0x40c00000, v15330; GFX9-NEXT:    v_cndmask_b32_e32 v2, v3, v4, vcc5331; GFX9-NEXT:    v_bfe_u32 v3, v1, 16, 15332; GFX9-NEXT:    v_add3_u32 v3, v3, v1, s65333; GFX9-NEXT:    v_or_b32_e32 v4, 0x400000, v15334; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v1, v15335; GFX9-NEXT:    v_cndmask_b32_e32 v1, v3, v4, vcc5336; GFX9-NEXT:    v_perm_b32 v1, v2, v1, s75337; GFX9-NEXT:  .LBB46_2: ; %end5338; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]5339; GFX9-NEXT:    s_setpc_b64 s[30:31]5340;5341; GFX11-TRUE16-LABEL: bitcast_v4bf16_to_f64:5342; GFX11-TRUE16:       ; %bb.0:5343; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5344; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v25345; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_vgpr35346; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo5347; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)5348; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s05349; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false5350; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v05351; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr05352; GFX11-TRUE16-NEXT:  ; %bb.2: ; %Flow5353; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s05354; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB46_45355; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true5356; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, 05357; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.h, v0.l5358; GFX11-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v05359; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v15360; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)5361; GFX11-TRUE16-NEXT:    v_add_f32_e32 v4, 0x40c00000, v35362; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.h, v1.l5363; GFX11-TRUE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v25364; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)5365; GFX11-TRUE16-NEXT:    v_add_f32_e32 v0, 0x40c00000, v05366; GFX11-TRUE16-NEXT:    v_bfe_u32 v6, v4, 16, 15367; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)5368; GFX11-TRUE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v35369; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, 0x400000, v45370; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v45371; GFX11-TRUE16-NEXT:    v_bfe_u32 v1, v2, 16, 15372; GFX11-TRUE16-NEXT:    v_add3_u32 v6, v6, v4, 0x7fff5373; GFX11-TRUE16-NEXT:    v_bfe_u32 v9, v3, 16, 15374; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, 0x400000, v35375; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, 0x400000, v25376; GFX11-TRUE16-NEXT:    v_bfe_u32 v8, v0, 16, 15377; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v4, v6, v7, vcc_lo5378; GFX11-TRUE16-NEXT:    v_add3_u32 v9, v9, v3, 0x7fff5379; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v35380; GFX11-TRUE16-NEXT:    v_add3_u32 v1, v1, v2, 0x7fff5381; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, 0x400000, v05382; GFX11-TRUE16-NEXT:    v_add3_u32 v8, v8, v0, 0x7fff5383; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v6, v9, v11, vcc_lo5384; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v25385; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v1, v5, vcc_lo5386; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v05387; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v4.h5388; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v8, v10, vcc_lo5389; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v6.h5390; GFX11-TRUE16-NEXT:  .LBB46_4: ; %end5391; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s05392; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)5393; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v35394; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]5395;5396; GFX11-FAKE16-LABEL: bitcast_v4bf16_to_f64:5397; GFX11-FAKE16:       ; %bb.0:5398; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5399; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo5400; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v25401; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s05402; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)5403; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s05404; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB46_25405; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true5406; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff0000, v15407; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)5408; GFX11-FAKE16-NEXT:    v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v2, 16, v05409; GFX11-FAKE16-NEXT:    v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v1, 16, v15410; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)5411; GFX11-FAKE16-NEXT:    v_bfe_u32 v8, v3, 16, 15412; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, 0x400000, v35413; GFX11-FAKE16-NEXT:    v_bfe_u32 v4, v2, 16, 15414; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, 0x400000, v25415; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v25416; GFX11-FAKE16-NEXT:    v_add3_u32 v8, v8, v3, 0x7fff5417; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v05418; GFX11-FAKE16-NEXT:    v_add3_u32 v4, v4, v2, 0x7fff5419; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)5420; GFX11-FAKE16-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v05421; GFX11-FAKE16-NEXT:    v_bfe_u32 v9, v1, 16, 15422; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)5423; GFX11-FAKE16-NEXT:    v_bfe_u32 v6, v0, 16, 15424; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, 0x400000, v05425; GFX11-FAKE16-NEXT:    v_add3_u32 v9, v9, v1, 0x7fff5426; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v4, v5, vcc_lo5427; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v05428; GFX11-FAKE16-NEXT:    v_add3_u32 v6, v6, v0, 0x7fff5429; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, 0x400000, v15430; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)5431; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v6, v7, vcc_lo5432; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v35433; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v8, v10, vcc_lo5434; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v15435; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v9, v4, vcc_lo5436; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v2, 0x70603025437; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)5438; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v3, v1, 0x70603025439; GFX11-FAKE16-NEXT:  .LBB46_2: ; %end5440; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s05441; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]5442  %cmp = icmp eq i32 %b, 05443  br i1 %cmp, label %cmp.true, label %cmp.false5444 5445cmp.true:5446  %a1 = fadd <4 x bfloat> %a, splat (bfloat 0xR40C0)5447  %a2 = bitcast <4 x bfloat> %a1 to double5448  br label %end5449 5450cmp.false:5451  %a3 = bitcast <4 x bfloat> %a to double5452  br label %end5453 5454end:5455  %phi = phi double [ %a2, %cmp.true ], [ %a3, %cmp.false ]5456  ret double %phi5457}5458 5459define inreg double @bitcast_v4bf16_to_f64_scalar(<4 x bfloat> inreg %a, i32 inreg %b) {5460; SI-LABEL: bitcast_v4bf16_to_f64_scalar:5461; SI:       ; %bb.0:5462; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5463; SI-NEXT:    s_cmp_lg_u32 s20, 05464; SI-NEXT:    v_mul_f32_e64 v8, 1.0, s175465; SI-NEXT:    v_mul_f32_e64 v5, 1.0, s165466; SI-NEXT:    v_mul_f32_e64 v7, 1.0, s195467; SI-NEXT:    v_mul_f32_e64 v3, 1.0, s185468; SI-NEXT:    s_cbranch_scc0 .LBB47_45469; SI-NEXT:  ; %bb.1: ; %cmp.false5470; SI-NEXT:    v_lshrrev_b32_e32 v6, 16, v85471; SI-NEXT:    v_lshr_b64 v[0:1], v[5:6], 165472; SI-NEXT:    v_lshrrev_b32_e32 v4, 16, v75473; SI-NEXT:    v_lshr_b64 v[1:2], v[3:4], 165474; SI-NEXT:    s_cbranch_execnz .LBB47_35475; SI-NEXT:  .LBB47_2: ; %cmp.true5476; SI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v85477; SI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v55478; SI-NEXT:    v_add_f32_e32 v1, 0x40c00000, v15479; SI-NEXT:    v_add_f32_e32 v0, 0x40c00000, v05480; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v15481; SI-NEXT:    v_lshr_b64 v[0:1], v[0:1], 165482; SI-NEXT:    v_and_b32_e32 v2, 0xffff0000, v75483; SI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v35484; SI-NEXT:    v_add_f32_e32 v2, 0x40c00000, v25485; SI-NEXT:    v_add_f32_e32 v1, 0x40c00000, v15486; SI-NEXT:    v_lshrrev_b32_e32 v2, 16, v25487; SI-NEXT:    v_lshr_b64 v[1:2], v[1:2], 165488; SI-NEXT:  .LBB47_3: ; %end5489; SI-NEXT:    s_setpc_b64 s[30:31]5490; SI-NEXT:  .LBB47_4:5491; SI-NEXT:    ; implicit-def: $vgpr0_vgpr15492; SI-NEXT:    s_branch .LBB47_25493;5494; VI-LABEL: bitcast_v4bf16_to_f64_scalar:5495; VI:       ; %bb.0:5496; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5497; VI-NEXT:    s_cmp_lg_u32 s18, 05498; VI-NEXT:    s_cbranch_scc0 .LBB47_35499; VI-NEXT:  ; %bb.1: ; %cmp.false5500; VI-NEXT:    s_cbranch_execnz .LBB47_45501; VI-NEXT:  .LBB47_2: ; %cmp.true5502; VI-NEXT:    s_lshl_b32 s4, s17, 165503; VI-NEXT:    v_mov_b32_e32 v4, 0x40c000005504; VI-NEXT:    v_add_f32_e32 v0, s4, v45505; VI-NEXT:    v_bfe_u32 v1, v0, 16, 15506; VI-NEXT:    v_add_u32_e32 v1, vcc, v1, v05507; VI-NEXT:    v_add_u32_e32 v1, vcc, 0x7fff, v15508; VI-NEXT:    v_or_b32_e32 v2, 0x400000, v05509; VI-NEXT:    v_cmp_u_f32_e32 vcc, v0, v05510; VI-NEXT:    s_and_b32 s4, s17, 0xffff00005511; VI-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc5512; VI-NEXT:    v_add_f32_e32 v1, s4, v45513; VI-NEXT:    v_bfe_u32 v2, v1, 16, 15514; VI-NEXT:    v_add_u32_e32 v2, vcc, v2, v15515; VI-NEXT:    v_add_u32_e32 v2, vcc, 0x7fff, v25516; VI-NEXT:    v_or_b32_e32 v3, 0x400000, v15517; VI-NEXT:    v_cmp_u_f32_e32 vcc, v1, v15518; VI-NEXT:    v_cndmask_b32_e32 v1, v2, v3, vcc5519; VI-NEXT:    v_lshrrev_b32_e32 v1, 16, v15520; VI-NEXT:    s_lshl_b32 s4, s16, 165521; VI-NEXT:    v_lshrrev_b64 v[2:3], 16, v[0:1]5522; VI-NEXT:    v_add_f32_e32 v0, s4, v45523; VI-NEXT:    v_bfe_u32 v1, v0, 16, 15524; VI-NEXT:    v_add_u32_e32 v1, vcc, v1, v05525; VI-NEXT:    v_add_u32_e32 v1, vcc, 0x7fff, v15526; VI-NEXT:    v_or_b32_e32 v3, 0x400000, v05527; VI-NEXT:    v_cmp_u_f32_e32 vcc, v0, v05528; VI-NEXT:    s_and_b32 s4, s16, 0xffff00005529; VI-NEXT:    v_cndmask_b32_e32 v0, v1, v3, vcc5530; VI-NEXT:    v_add_f32_e32 v1, s4, v45531; VI-NEXT:    v_bfe_u32 v3, v1, 16, 15532; VI-NEXT:    v_add_u32_e32 v3, vcc, v3, v15533; VI-NEXT:    v_add_u32_e32 v3, vcc, 0x7fff, v35534; VI-NEXT:    v_or_b32_e32 v4, 0x400000, v15535; VI-NEXT:    v_cmp_u_f32_e32 vcc, v1, v15536; VI-NEXT:    v_cndmask_b32_e32 v1, v3, v4, vcc5537; VI-NEXT:    v_lshrrev_b32_e32 v1, 16, v15538; VI-NEXT:    v_lshrrev_b64 v[0:1], 16, v[0:1]5539; VI-NEXT:    v_mov_b32_e32 v1, v25540; VI-NEXT:    s_setpc_b64 s[30:31]5541; VI-NEXT:  .LBB47_3:5542; VI-NEXT:    s_branch .LBB47_25543; VI-NEXT:  .LBB47_4:5544; VI-NEXT:    v_mov_b32_e32 v0, s165545; VI-NEXT:    v_mov_b32_e32 v1, s175546; VI-NEXT:    s_setpc_b64 s[30:31]5547;5548; GFX9-LABEL: bitcast_v4bf16_to_f64_scalar:5549; GFX9:       ; %bb.0:5550; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5551; GFX9-NEXT:    s_cmp_lg_u32 s18, 05552; GFX9-NEXT:    s_cbranch_scc0 .LBB47_35553; GFX9-NEXT:  ; %bb.1: ; %cmp.false5554; GFX9-NEXT:    s_cbranch_execnz .LBB47_45555; GFX9-NEXT:  .LBB47_2: ; %cmp.true5556; GFX9-NEXT:    s_pack_lh_b32_b16 s4, 0, s165557; GFX9-NEXT:    v_mov_b32_e32 v1, 0x40c000005558; GFX9-NEXT:    v_add_f32_e32 v0, s4, v15559; GFX9-NEXT:    v_bfe_u32 v2, v0, 16, 15560; GFX9-NEXT:    v_add_u32_e32 v2, v2, v05561; GFX9-NEXT:    v_add_u32_e32 v2, 0x7fff, v25562; GFX9-NEXT:    v_or_b32_e32 v3, 0x400000, v05563; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v0, v05564; GFX9-NEXT:    s_lshl_b32 s4, s16, 165565; GFX9-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc5566; GFX9-NEXT:    v_add_f32_e32 v2, s4, v15567; GFX9-NEXT:    v_bfe_u32 v3, v2, 16, 15568; GFX9-NEXT:    v_add_u32_e32 v3, v3, v25569; GFX9-NEXT:    v_add_u32_e32 v3, 0x7fff, v35570; GFX9-NEXT:    v_or_b32_e32 v4, 0x400000, v25571; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v2, v25572; GFX9-NEXT:    v_cndmask_b32_e32 v2, v3, v4, vcc5573; GFX9-NEXT:    v_mov_b32_e32 v3, 0xffff5574; GFX9-NEXT:    v_lshrrev_b32_e32 v0, 16, v05575; GFX9-NEXT:    v_and_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_15576; GFX9-NEXT:    s_pack_lh_b32_b16 s4, 0, s175577; GFX9-NEXT:    v_lshl_or_b32 v0, v0, 16, v25578; GFX9-NEXT:    v_add_f32_e32 v2, s4, v15579; GFX9-NEXT:    v_bfe_u32 v4, v2, 16, 15580; GFX9-NEXT:    v_add_u32_e32 v4, v4, v25581; GFX9-NEXT:    s_lshl_b32 s4, s17, 165582; GFX9-NEXT:    v_add_u32_e32 v4, 0x7fff, v45583; GFX9-NEXT:    v_or_b32_e32 v5, 0x400000, v25584; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v2, v25585; GFX9-NEXT:    v_add_f32_e32 v1, s4, v15586; GFX9-NEXT:    v_cndmask_b32_e32 v2, v4, v5, vcc5587; GFX9-NEXT:    v_bfe_u32 v4, v1, 16, 15588; GFX9-NEXT:    v_add_u32_e32 v4, v4, v15589; GFX9-NEXT:    v_add_u32_e32 v4, 0x7fff, v45590; GFX9-NEXT:    v_or_b32_e32 v5, 0x400000, v15591; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v1, v15592; GFX9-NEXT:    v_cndmask_b32_e32 v1, v4, v5, vcc5593; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 16, v25594; GFX9-NEXT:    v_and_b32_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_15595; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v15596; GFX9-NEXT:    s_setpc_b64 s[30:31]5597; GFX9-NEXT:  .LBB47_3:5598; GFX9-NEXT:    s_branch .LBB47_25599; GFX9-NEXT:  .LBB47_4:5600; GFX9-NEXT:    v_mov_b32_e32 v0, s165601; GFX9-NEXT:    v_mov_b32_e32 v1, s175602; GFX9-NEXT:    s_setpc_b64 s[30:31]5603;5604; GFX11-TRUE16-LABEL: bitcast_v4bf16_to_f64_scalar:5605; GFX11-TRUE16:       ; %bb.0:5606; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5607; GFX11-TRUE16-NEXT:    s_cmp_lg_u32 s2, 05608; GFX11-TRUE16-NEXT:    s_mov_b32 s2, 05609; GFX11-TRUE16-NEXT:    s_cbranch_scc0 .LBB47_35610; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow5611; GFX11-TRUE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s25612; GFX11-TRUE16-NEXT:    s_cbranch_vccnz .LBB47_45613; GFX11-TRUE16-NEXT:  .LBB47_2: ; %cmp.true5614; GFX11-TRUE16-NEXT:    s_pack_lh_b32_b16 s2, 0, s05615; GFX11-TRUE16-NEXT:    s_lshl_b32 s0, s0, 165616; GFX11-TRUE16-NEXT:    v_add_f32_e64 v0, 0x40c00000, s25617; GFX11-TRUE16-NEXT:    v_add_f32_e64 v1, 0x40c00000, s05618; GFX11-TRUE16-NEXT:    s_pack_lh_b32_b16 s2, 0, s15619; GFX11-TRUE16-NEXT:    s_lshl_b32 s1, s1, 165620; GFX11-TRUE16-NEXT:    v_add_f32_e64 v3, 0x40c00000, s25621; GFX11-TRUE16-NEXT:    v_bfe_u32 v2, v0, 16, 15622; GFX11-TRUE16-NEXT:    v_bfe_u32 v6, v1, 16, 15623; GFX11-TRUE16-NEXT:    v_add_f32_e64 v4, 0x40c00000, s15624; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, 0x400000, v05625; GFX11-TRUE16-NEXT:    v_bfe_u32 v8, v3, 16, 15626; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v2, v2, v05627; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v6, v6, v15628; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, 0x400000, v15629; GFX11-TRUE16-NEXT:    v_bfe_u32 v9, v4, 16, 15630; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v8, v8, v35631; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v05632; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v6, 0x7fff, v65633; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v2, 0x7fff, v25634; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, 0x400000, v35635; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)5636; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v0, v2, v5 :: v_dual_add_nc_u32 v9, v9, v45637; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, 0x400000, v45638; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v5, 0x7fff, v85639; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v35640; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v8, 0x7fff, v95641; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v9, 16, v05642; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)5643; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v5, v10, vcc_lo5644; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v15645; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v05646; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v6, v7, vcc_lo5647; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v45648; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)5649; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v15650; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v8, v2, vcc_lo5651; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v9.l5652; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v25653; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v3.l5654; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]5655; GFX11-TRUE16-NEXT:  .LBB47_3:5656; GFX11-TRUE16-NEXT:    s_branch .LBB47_25657; GFX11-TRUE16-NEXT:  .LBB47_4:5658; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s15659; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]5660;5661; GFX11-FAKE16-LABEL: bitcast_v4bf16_to_f64_scalar:5662; GFX11-FAKE16:       ; %bb.0:5663; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5664; GFX11-FAKE16-NEXT:    s_cmp_lg_u32 s2, 05665; GFX11-FAKE16-NEXT:    s_mov_b32 s2, 05666; GFX11-FAKE16-NEXT:    s_cbranch_scc0 .LBB47_35667; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow5668; GFX11-FAKE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s25669; GFX11-FAKE16-NEXT:    s_cbranch_vccnz .LBB47_45670; GFX11-FAKE16-NEXT:  .LBB47_2: ; %cmp.true5671; GFX11-FAKE16-NEXT:    s_pack_lh_b32_b16 s2, 0, s05672; GFX11-FAKE16-NEXT:    s_lshl_b32 s0, s0, 165673; GFX11-FAKE16-NEXT:    v_add_f32_e64 v0, 0x40c00000, s25674; GFX11-FAKE16-NEXT:    v_add_f32_e64 v1, 0x40c00000, s05675; GFX11-FAKE16-NEXT:    s_lshl_b32 s0, s1, 165676; GFX11-FAKE16-NEXT:    s_pack_lh_b32_b16 s1, 0, s15677; GFX11-FAKE16-NEXT:    v_add_f32_e64 v2, 0x40c00000, s05678; GFX11-FAKE16-NEXT:    v_add_f32_e64 v5, 0x40c00000, s15679; GFX11-FAKE16-NEXT:    v_bfe_u32 v4, v1, 16, 15680; GFX11-FAKE16-NEXT:    v_bfe_u32 v3, v0, 16, 15681; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, 0x400000, v15682; GFX11-FAKE16-NEXT:    v_bfe_u32 v6, v2, 16, 15683; GFX11-FAKE16-NEXT:    v_bfe_u32 v8, v5, 16, 15684; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v4, v4, v15685; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v15686; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, 0x400000, v25687; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, 0x400000, v05688; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v8, v8, v55689; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v4, 0x7fff, v45690; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)5691; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v1, v4, v9 :: v_dual_add_nc_u32 v6, v6, v25692; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v4, 0x7fff, v85693; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, 0x400000, v55694; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)5695; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v6, 0x7fff, v65696; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v25697; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v3, v3, v05698; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v15699; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v2, v6, v10 :: v_dual_add_nc_u32 v3, 0x7fff, v35700; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v05701; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)5702; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v15703; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v25704; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)5705; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v3, v7, vcc_lo5706; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v55707; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v25708; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)5709; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v05710; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v4, v8, vcc_lo5711; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v0, v0, 16, v15712; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)5713; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v35714; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, v3, 16, v25715; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]5716; GFX11-FAKE16-NEXT:  .LBB47_3:5717; GFX11-FAKE16-NEXT:    s_branch .LBB47_25718; GFX11-FAKE16-NEXT:  .LBB47_4:5719; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s15720; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]5721  %cmp = icmp eq i32 %b, 05722  br i1 %cmp, label %cmp.true, label %cmp.false5723 5724cmp.true:5725  %a1 = fadd <4 x bfloat> %a, splat (bfloat 0xR40C0)5726  %a2 = bitcast <4 x bfloat> %a1 to double5727  br label %end5728 5729cmp.false:5730  %a3 = bitcast <4 x bfloat> %a to double5731  br label %end5732 5733end:5734  %phi = phi double [ %a2, %cmp.true ], [ %a3, %cmp.false ]5735  ret double %phi5736}5737 5738define <8 x i8> @bitcast_f64_to_v8i8(double %a, i32 %b) {5739; SI-LABEL: bitcast_f64_to_v8i8:5740; SI:       ; %bb.0:5741; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5742; SI-NEXT:    v_mov_b32_e32 v9, v15743; SI-NEXT:    v_mov_b32_e32 v8, v05744; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v25745; SI-NEXT:    ; implicit-def: $vgpr15746; SI-NEXT:    ; implicit-def: $vgpr25747; SI-NEXT:    ; implicit-def: $vgpr35748; SI-NEXT:    ; implicit-def: $vgpr55749; SI-NEXT:    ; implicit-def: $vgpr65750; SI-NEXT:    ; implicit-def: $vgpr75751; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc5752; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]5753; SI-NEXT:  ; %bb.1: ; %cmp.false5754; SI-NEXT:    v_alignbit_b32 v3, v9, v8, 245755; SI-NEXT:    v_alignbit_b32 v2, v9, v8, 165756; SI-NEXT:    v_alignbit_b32 v1, v9, v8, 85757; SI-NEXT:    v_lshrrev_b32_e32 v7, 24, v95758; SI-NEXT:    v_lshrrev_b32_e32 v6, 16, v95759; SI-NEXT:    v_lshrrev_b32_e32 v5, 8, v95760; SI-NEXT:  ; %bb.2: ; %Flow5761; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]5762; SI-NEXT:  ; %bb.3: ; %cmp.true5763; SI-NEXT:    v_add_f64 v[8:9], v[8:9], 1.05764; SI-NEXT:    v_alignbit_b32 v3, v9, v8, 245765; SI-NEXT:    v_alignbit_b32 v2, v9, v8, 165766; SI-NEXT:    v_alignbit_b32 v1, v9, v8, 85767; SI-NEXT:    v_lshrrev_b32_e32 v7, 24, v95768; SI-NEXT:    v_lshrrev_b32_e32 v6, 16, v95769; SI-NEXT:    v_lshrrev_b32_e32 v5, 8, v95770; SI-NEXT:  ; %bb.4: ; %end5771; SI-NEXT:    s_or_b64 exec, exec, s[4:5]5772; SI-NEXT:    v_mov_b32_e32 v0, v85773; SI-NEXT:    v_mov_b32_e32 v4, v95774; SI-NEXT:    s_setpc_b64 s[30:31]5775;5776; VI-LABEL: bitcast_f64_to_v8i8:5777; VI:       ; %bb.0:5778; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5779; VI-NEXT:    v_mov_b32_e32 v9, v15780; VI-NEXT:    v_mov_b32_e32 v8, v05781; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v25782; VI-NEXT:    ; implicit-def: $vgpr15783; VI-NEXT:    ; implicit-def: $vgpr25784; VI-NEXT:    ; implicit-def: $vgpr35785; VI-NEXT:    ; implicit-def: $vgpr55786; VI-NEXT:    ; implicit-def: $vgpr65787; VI-NEXT:    ; implicit-def: $vgpr75788; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc5789; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]5790; VI-NEXT:  ; %bb.1: ; %cmp.false5791; VI-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]5792; VI-NEXT:    v_lshrrev_b32_e32 v7, 24, v95793; VI-NEXT:    v_lshrrev_b32_e32 v6, 16, v95794; VI-NEXT:    v_lshrrev_b32_e32 v5, 8, v95795; VI-NEXT:    v_lshrrev_b32_e32 v2, 16, v85796; VI-NEXT:    v_lshrrev_b32_e32 v1, 8, v85797; VI-NEXT:  ; %bb.2: ; %Flow5798; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]5799; VI-NEXT:    s_cbranch_execz .LBB48_45800; VI-NEXT:  ; %bb.3: ; %cmp.true5801; VI-NEXT:    v_add_f64 v[8:9], v[8:9], 1.05802; VI-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]5803; VI-NEXT:    v_lshrrev_b32_e32 v7, 24, v95804; VI-NEXT:    v_lshrrev_b32_e32 v6, 16, v95805; VI-NEXT:    v_lshrrev_b32_e32 v5, 8, v95806; VI-NEXT:    v_lshrrev_b32_e32 v2, 16, v85807; VI-NEXT:    v_lshrrev_b32_e32 v1, 8, v85808; VI-NEXT:  .LBB48_4: ; %end5809; VI-NEXT:    s_or_b64 exec, exec, s[4:5]5810; VI-NEXT:    v_mov_b32_e32 v0, v85811; VI-NEXT:    v_mov_b32_e32 v4, v95812; VI-NEXT:    s_setpc_b64 s[30:31]5813;5814; GFX9-LABEL: bitcast_f64_to_v8i8:5815; GFX9:       ; %bb.0:5816; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5817; GFX9-NEXT:    v_mov_b32_e32 v9, v15818; GFX9-NEXT:    v_mov_b32_e32 v8, v05819; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v25820; GFX9-NEXT:    ; implicit-def: $vgpr15821; GFX9-NEXT:    ; implicit-def: $vgpr25822; GFX9-NEXT:    ; implicit-def: $vgpr35823; GFX9-NEXT:    ; implicit-def: $vgpr55824; GFX9-NEXT:    ; implicit-def: $vgpr65825; GFX9-NEXT:    ; implicit-def: $vgpr75826; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc5827; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]5828; GFX9-NEXT:  ; %bb.1: ; %cmp.false5829; GFX9-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]5830; GFX9-NEXT:    v_lshrrev_b32_e32 v7, 24, v95831; GFX9-NEXT:    v_lshrrev_b32_e32 v6, 16, v95832; GFX9-NEXT:    v_lshrrev_b32_e32 v5, 8, v95833; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 16, v85834; GFX9-NEXT:    v_lshrrev_b32_e32 v1, 8, v85835; GFX9-NEXT:  ; %bb.2: ; %Flow5836; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]5837; GFX9-NEXT:    s_cbranch_execz .LBB48_45838; GFX9-NEXT:  ; %bb.3: ; %cmp.true5839; GFX9-NEXT:    v_add_f64 v[8:9], v[8:9], 1.05840; GFX9-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]5841; GFX9-NEXT:    v_lshrrev_b32_e32 v7, 24, v95842; GFX9-NEXT:    v_lshrrev_b32_e32 v6, 16, v95843; GFX9-NEXT:    v_lshrrev_b32_e32 v5, 8, v95844; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 16, v85845; GFX9-NEXT:    v_lshrrev_b32_e32 v1, 8, v85846; GFX9-NEXT:  .LBB48_4: ; %end5847; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]5848; GFX9-NEXT:    v_mov_b32_e32 v0, v85849; GFX9-NEXT:    v_mov_b32_e32 v4, v95850; GFX9-NEXT:    s_setpc_b64 s[30:31]5851;5852; GFX11-TRUE16-LABEL: bitcast_f64_to_v8i8:5853; GFX11-TRUE16:       ; %bb.0:5854; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5855; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v05856; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo5857; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo165858; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo165859; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo165860; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_lo165861; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v25862; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s05863; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false5864; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)5865; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]5866; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v95867; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v95868; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v85869; GFX11-TRUE16-NEXT:  ; %bb.2: ; %Flow5870; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s05871; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB48_45872; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true5873; GFX11-TRUE16-NEXT:    v_add_f64 v[8:9], v[8:9], 1.05874; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)5875; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]5876; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v95877; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v95878; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v85879; GFX11-TRUE16-NEXT:  .LBB48_4: ; %end5880; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s05881; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v8.l5882; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v8.h5883; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v9.l5884; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v9.h5885; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]5886;5887; GFX11-FAKE16-LABEL: bitcast_f64_to_v8i8:5888; GFX11-FAKE16:       ; %bb.0:5889; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5890; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v05891; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v25892; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr15893; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr25894; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35895; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr55896; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr65897; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr75898; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo5899; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)5900; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s05901; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false5902; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)5903; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]5904; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v95905; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v95906; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v95907; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v85908; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v85909; GFX11-FAKE16-NEXT:  ; %bb.2: ; %Flow5910; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s05911; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB48_45912; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true5913; GFX11-FAKE16-NEXT:    v_add_f64 v[8:9], v[8:9], 1.05914; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)5915; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]5916; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v95917; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v95918; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v95919; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v85920; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v85921; GFX11-FAKE16-NEXT:  .LBB48_4: ; %end5922; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s05923; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, v85924; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, v95925; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]5926  %cmp = icmp eq i32 %b, 05927  br i1 %cmp, label %cmp.true, label %cmp.false5928 5929cmp.true:5930  %a1 = fadd double %a, 1.000000e+005931  %a2 = bitcast double %a1 to <8 x i8>5932  br label %end5933 5934cmp.false:5935  %a3 = bitcast double %a to <8 x i8>5936  br label %end5937 5938end:5939  %phi = phi <8 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]5940  ret <8 x i8> %phi5941}5942 5943define inreg <8 x i8> @bitcast_f64_to_v8i8_scalar(double inreg %a, i32 inreg %b) {5944; SI-LABEL: bitcast_f64_to_v8i8_scalar:5945; SI:       ; %bb.0:5946; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5947; SI-NEXT:    s_cmp_lg_u32 s18, 05948; SI-NEXT:    s_cbranch_scc0 .LBB49_35949; SI-NEXT:  ; %bb.1: ; %cmp.false5950; SI-NEXT:    s_lshr_b32 s14, s17, 245951; SI-NEXT:    s_lshr_b32 s13, s17, 165952; SI-NEXT:    s_lshr_b32 s12, s17, 85953; SI-NEXT:    s_lshr_b64 s[4:5], s[16:17], 245954; SI-NEXT:    s_lshr_b64 s[6:7], s[16:17], 165955; SI-NEXT:    s_lshr_b64 s[8:9], s[16:17], 85956; SI-NEXT:    s_cbranch_execnz .LBB49_45957; SI-NEXT:  .LBB49_2: ; %cmp.true5958; SI-NEXT:    v_add_f64 v[10:11], s[16:17], 1.05959; SI-NEXT:    v_lshr_b64 v[3:4], v[10:11], 245960; SI-NEXT:    v_lshr_b64 v[8:9], v[10:11], 165961; SI-NEXT:    v_lshr_b64 v[1:2], v[10:11], 85962; SI-NEXT:    v_lshrrev_b32_e32 v7, 24, v115963; SI-NEXT:    v_lshrrev_b32_e32 v6, 16, v115964; SI-NEXT:    v_lshrrev_b32_e32 v5, 8, v115965; SI-NEXT:    s_branch .LBB49_55966; SI-NEXT:  .LBB49_3:5967; SI-NEXT:    ; implicit-def: $sgpr85968; SI-NEXT:    ; implicit-def: $sgpr65969; SI-NEXT:    ; implicit-def: $sgpr45970; SI-NEXT:    ; implicit-def: $sgpr125971; SI-NEXT:    ; implicit-def: $sgpr135972; SI-NEXT:    ; implicit-def: $sgpr145973; SI-NEXT:    s_branch .LBB49_25974; SI-NEXT:  .LBB49_4:5975; SI-NEXT:    v_mov_b32_e32 v11, s175976; SI-NEXT:    v_mov_b32_e32 v10, s165977; SI-NEXT:    v_mov_b32_e32 v7, s145978; SI-NEXT:    v_mov_b32_e32 v6, s135979; SI-NEXT:    v_mov_b32_e32 v5, s125980; SI-NEXT:    v_mov_b32_e32 v1, s85981; SI-NEXT:    v_mov_b32_e32 v8, s65982; SI-NEXT:    v_mov_b32_e32 v3, s45983; SI-NEXT:  .LBB49_5: ; %end5984; SI-NEXT:    v_mov_b32_e32 v0, v105985; SI-NEXT:    v_mov_b32_e32 v2, v85986; SI-NEXT:    v_mov_b32_e32 v4, v115987; SI-NEXT:    s_setpc_b64 s[30:31]5988;5989; VI-LABEL: bitcast_f64_to_v8i8_scalar:5990; VI:       ; %bb.0:5991; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5992; VI-NEXT:    s_cmp_lg_u32 s18, 05993; VI-NEXT:    s_cbranch_scc0 .LBB49_35994; VI-NEXT:  ; %bb.1: ; %cmp.false5995; VI-NEXT:    s_lshr_b64 s[4:5], s[16:17], 245996; VI-NEXT:    s_lshr_b32 s9, s17, 245997; VI-NEXT:    s_lshr_b32 s8, s17, 165998; VI-NEXT:    s_lshr_b32 s5, s17, 85999; VI-NEXT:    s_lshr_b32 s11, s16, 166000; VI-NEXT:    s_lshr_b32 s10, s16, 86001; VI-NEXT:    s_cbranch_execnz .LBB49_46002; VI-NEXT:  .LBB49_2: ; %cmp.true6003; VI-NEXT:    v_add_f64 v[8:9], s[16:17], 1.06004; VI-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]6005; VI-NEXT:    v_lshrrev_b32_e32 v7, 24, v96006; VI-NEXT:    v_lshrrev_b32_e32 v6, 16, v96007; VI-NEXT:    v_lshrrev_b32_e32 v5, 8, v96008; VI-NEXT:    v_lshrrev_b32_e32 v2, 16, v86009; VI-NEXT:    v_lshrrev_b32_e32 v1, 8, v86010; VI-NEXT:    s_branch .LBB49_56011; VI-NEXT:  .LBB49_3:6012; VI-NEXT:    ; implicit-def: $sgpr106013; VI-NEXT:    ; implicit-def: $sgpr116014; VI-NEXT:    ; implicit-def: $sgpr46015; VI-NEXT:    ; implicit-def: $sgpr56016; VI-NEXT:    ; implicit-def: $sgpr86017; VI-NEXT:    ; implicit-def: $sgpr96018; VI-NEXT:    s_branch .LBB49_26019; VI-NEXT:  .LBB49_4:6020; VI-NEXT:    v_mov_b32_e32 v8, s166021; VI-NEXT:    v_mov_b32_e32 v9, s176022; VI-NEXT:    v_mov_b32_e32 v2, s116023; VI-NEXT:    v_mov_b32_e32 v1, s106024; VI-NEXT:    v_mov_b32_e32 v3, s46025; VI-NEXT:    v_mov_b32_e32 v7, s96026; VI-NEXT:    v_mov_b32_e32 v6, s86027; VI-NEXT:    v_mov_b32_e32 v5, s56028; VI-NEXT:  .LBB49_5: ; %end6029; VI-NEXT:    v_mov_b32_e32 v0, v86030; VI-NEXT:    v_mov_b32_e32 v4, v96031; VI-NEXT:    s_setpc_b64 s[30:31]6032;6033; GFX9-LABEL: bitcast_f64_to_v8i8_scalar:6034; GFX9:       ; %bb.0:6035; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6036; GFX9-NEXT:    s_cmp_lg_u32 s18, 06037; GFX9-NEXT:    s_cbranch_scc0 .LBB49_36038; GFX9-NEXT:  ; %bb.1: ; %cmp.false6039; GFX9-NEXT:    s_lshr_b64 s[4:5], s[16:17], 246040; GFX9-NEXT:    s_lshr_b32 s9, s17, 246041; GFX9-NEXT:    s_lshr_b32 s8, s17, 166042; GFX9-NEXT:    s_lshr_b32 s5, s17, 86043; GFX9-NEXT:    s_lshr_b32 s11, s16, 166044; GFX9-NEXT:    s_lshr_b32 s10, s16, 86045; GFX9-NEXT:    s_cbranch_execnz .LBB49_46046; GFX9-NEXT:  .LBB49_2: ; %cmp.true6047; GFX9-NEXT:    v_add_f64 v[8:9], s[16:17], 1.06048; GFX9-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]6049; GFX9-NEXT:    v_lshrrev_b32_e32 v7, 24, v96050; GFX9-NEXT:    v_lshrrev_b32_e32 v6, 16, v96051; GFX9-NEXT:    v_lshrrev_b32_e32 v5, 8, v96052; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 16, v86053; GFX9-NEXT:    v_lshrrev_b32_e32 v1, 8, v86054; GFX9-NEXT:    s_branch .LBB49_56055; GFX9-NEXT:  .LBB49_3:6056; GFX9-NEXT:    ; implicit-def: $sgpr106057; GFX9-NEXT:    ; implicit-def: $sgpr116058; GFX9-NEXT:    ; implicit-def: $sgpr46059; GFX9-NEXT:    ; implicit-def: $sgpr56060; GFX9-NEXT:    ; implicit-def: $sgpr86061; GFX9-NEXT:    ; implicit-def: $sgpr96062; GFX9-NEXT:    s_branch .LBB49_26063; GFX9-NEXT:  .LBB49_4:6064; GFX9-NEXT:    v_mov_b32_e32 v8, s166065; GFX9-NEXT:    v_mov_b32_e32 v9, s176066; GFX9-NEXT:    v_mov_b32_e32 v2, s116067; GFX9-NEXT:    v_mov_b32_e32 v1, s106068; GFX9-NEXT:    v_mov_b32_e32 v3, s46069; GFX9-NEXT:    v_mov_b32_e32 v7, s96070; GFX9-NEXT:    v_mov_b32_e32 v6, s86071; GFX9-NEXT:    v_mov_b32_e32 v5, s56072; GFX9-NEXT:  .LBB49_5: ; %end6073; GFX9-NEXT:    v_mov_b32_e32 v0, v86074; GFX9-NEXT:    v_mov_b32_e32 v4, v96075; GFX9-NEXT:    s_setpc_b64 s[30:31]6076;6077; GFX11-LABEL: bitcast_f64_to_v8i8_scalar:6078; GFX11:       ; %bb.0:6079; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6080; GFX11-NEXT:    s_cmp_lg_u32 s2, 06081; GFX11-NEXT:    s_mov_b32 s4, 06082; GFX11-NEXT:    s_cbranch_scc0 .LBB49_36083; GFX11-NEXT:  ; %bb.1: ; %cmp.false6084; GFX11-NEXT:    s_lshr_b64 s[2:3], s[0:1], 246085; GFX11-NEXT:    s_lshr_b32 s6, s1, 246086; GFX11-NEXT:    s_lshr_b32 s5, s1, 166087; GFX11-NEXT:    s_lshr_b32 s3, s1, 86088; GFX11-NEXT:    s_lshr_b32 s8, s0, 166089; GFX11-NEXT:    s_lshr_b32 s7, s0, 86090; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s46091; GFX11-NEXT:    s_cbranch_vccnz .LBB49_46092; GFX11-NEXT:  .LBB49_2: ; %cmp.true6093; GFX11-NEXT:    v_add_f64 v[8:9], s[0:1], 1.06094; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)6095; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]6096; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v96097; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v96098; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v96099; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v86100; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v86101; GFX11-NEXT:    s_branch .LBB49_56102; GFX11-NEXT:  .LBB49_3:6103; GFX11-NEXT:    ; implicit-def: $sgpr76104; GFX11-NEXT:    ; implicit-def: $sgpr86105; GFX11-NEXT:    ; implicit-def: $sgpr26106; GFX11-NEXT:    ; implicit-def: $sgpr36107; GFX11-NEXT:    ; implicit-def: $sgpr56108; GFX11-NEXT:    ; implicit-def: $sgpr66109; GFX11-NEXT:    s_branch .LBB49_26110; GFX11-NEXT:  .LBB49_4:6111; GFX11-NEXT:    v_dual_mov_b32 v8, s0 :: v_dual_mov_b32 v9, s16112; GFX11-NEXT:    v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v1, s76113; GFX11-NEXT:    v_dual_mov_b32 v3, s2 :: v_dual_mov_b32 v6, s56114; GFX11-NEXT:    v_mov_b32_e32 v7, s66115; GFX11-NEXT:    v_mov_b32_e32 v5, s36116; GFX11-NEXT:  .LBB49_5: ; %end6117; GFX11-NEXT:    v_mov_b32_e32 v0, v86118; GFX11-NEXT:    v_mov_b32_e32 v4, v96119; GFX11-NEXT:    s_setpc_b64 s[30:31]6120  %cmp = icmp eq i32 %b, 06121  br i1 %cmp, label %cmp.true, label %cmp.false6122 6123cmp.true:6124  %a1 = fadd double %a, 1.000000e+006125  %a2 = bitcast double %a1 to <8 x i8>6126  br label %end6127 6128cmp.false:6129  %a3 = bitcast double %a to <8 x i8>6130  br label %end6131 6132end:6133  %phi = phi <8 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]6134  ret <8 x i8> %phi6135}6136 6137define double @bitcast_v8i8_to_f64(<8 x i8> %a, i32 %b) {6138; SI-LABEL: bitcast_v8i8_to_f64:6139; SI:       ; %bb.0:6140; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6141; SI-NEXT:    v_mov_b32_e32 v9, v06142; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v86143; SI-NEXT:    v_lshlrev_b32_e32 v10, 8, v16144; SI-NEXT:    v_lshlrev_b32_e32 v8, 24, v36145; SI-NEXT:    v_lshlrev_b32_e32 v5, 8, v56146; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v76147; SI-NEXT:    ; implicit-def: $vgpr0_vgpr16148; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc6149; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]6150; SI-NEXT:    s_cbranch_execnz .LBB50_36151; SI-NEXT:  ; %bb.1: ; %Flow6152; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]6153; SI-NEXT:    s_cbranch_execnz .LBB50_46154; SI-NEXT:  .LBB50_2: ; %end6155; SI-NEXT:    s_or_b64 exec, exec, s[4:5]6156; SI-NEXT:    s_setpc_b64 s[30:31]6157; SI-NEXT:  .LBB50_3: ; %cmp.false6158; SI-NEXT:    v_and_b32_e32 v0, 0xff, v96159; SI-NEXT:    v_and_b32_e32 v1, 0xff, v26160; SI-NEXT:    v_or_b32_e32 v0, v0, v106161; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v16162; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v06163; SI-NEXT:    v_or_b32_e32 v1, v8, v16164; SI-NEXT:    v_or_b32_e32 v0, v0, v16165; SI-NEXT:    v_and_b32_e32 v1, 0xff, v46166; SI-NEXT:    v_and_b32_e32 v2, 0xff, v66167; SI-NEXT:    v_or_b32_e32 v1, v1, v56168; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v26169; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v16170; SI-NEXT:    v_or_b32_e32 v2, v3, v26171; SI-NEXT:    v_or_b32_e32 v1, v1, v26172; SI-NEXT:    ; implicit-def: $vgpr96173; SI-NEXT:    ; implicit-def: $vgpr106174; SI-NEXT:    ; implicit-def: $vgpr26175; SI-NEXT:    ; implicit-def: $vgpr86176; SI-NEXT:    ; implicit-def: $vgpr46177; SI-NEXT:    ; implicit-def: $vgpr56178; SI-NEXT:    ; implicit-def: $vgpr66179; SI-NEXT:    ; implicit-def: $vgpr36180; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]6181; SI-NEXT:    s_cbranch_execz .LBB50_26182; SI-NEXT:  .LBB50_4: ; %cmp.true6183; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v96184; SI-NEXT:    v_and_b32_e32 v0, 0xff, v06185; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v26186; SI-NEXT:    v_or_b32_e32 v0, v10, v06187; SI-NEXT:    v_and_b32_e32 v1, 0xff, v16188; SI-NEXT:    v_add_i32_e32 v0, vcc, 0x300, v06189; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v16190; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v06191; SI-NEXT:    v_or_b32_e32 v1, v8, v16192; SI-NEXT:    v_or_b32_e32 v0, v1, v06193; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v46194; SI-NEXT:    v_and_b32_e32 v1, 0xff, v16195; SI-NEXT:    v_add_i32_e32 v2, vcc, 3, v66196; SI-NEXT:    v_or_b32_e32 v1, v5, v16197; SI-NEXT:    v_and_b32_e32 v2, 0xff, v26198; SI-NEXT:    v_add_i32_e32 v1, vcc, 0x300, v16199; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v26200; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v16201; SI-NEXT:    v_or_b32_e32 v2, v3, v26202; SI-NEXT:    v_or_b32_e32 v1, v2, v16203; SI-NEXT:    v_add_i32_e32 v0, vcc, 0x3000000, v06204; SI-NEXT:    v_add_i32_e32 v1, vcc, 0x3000000, v16205; SI-NEXT:    s_or_b64 exec, exec, s[4:5]6206; SI-NEXT:    s_setpc_b64 s[30:31]6207;6208; VI-LABEL: bitcast_v8i8_to_f64:6209; VI:       ; %bb.0:6210; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6211; VI-NEXT:    v_mov_b32_e32 v9, v06212; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v86213; VI-NEXT:    v_lshlrev_b16_e32 v10, 8, v16214; VI-NEXT:    v_lshlrev_b16_e32 v8, 8, v36215; VI-NEXT:    v_lshlrev_b16_e32 v5, 8, v56216; VI-NEXT:    v_lshlrev_b16_e32 v3, 8, v76217; VI-NEXT:    ; implicit-def: $vgpr0_vgpr16218; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc6219; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]6220; VI-NEXT:    s_cbranch_execnz .LBB50_36221; VI-NEXT:  ; %bb.1: ; %Flow6222; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]6223; VI-NEXT:    s_cbranch_execnz .LBB50_46224; VI-NEXT:  .LBB50_2: ; %end6225; VI-NEXT:    s_or_b64 exec, exec, s[4:5]6226; VI-NEXT:    s_setpc_b64 s[30:31]6227; VI-NEXT:  .LBB50_3: ; %cmp.false6228; VI-NEXT:    v_or_b32_sdwa v0, v9, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD6229; VI-NEXT:    v_or_b32_sdwa v1, v2, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD6230; VI-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD6231; VI-NEXT:    v_or_b32_sdwa v1, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD6232; VI-NEXT:    v_or_b32_sdwa v2, v6, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD6233; VI-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD6234; VI-NEXT:    ; implicit-def: $vgpr96235; VI-NEXT:    ; implicit-def: $vgpr106236; VI-NEXT:    ; implicit-def: $vgpr26237; VI-NEXT:    ; implicit-def: $vgpr86238; VI-NEXT:    ; implicit-def: $vgpr46239; VI-NEXT:    ; implicit-def: $vgpr56240; VI-NEXT:    ; implicit-def: $vgpr66241; VI-NEXT:    ; implicit-def: $vgpr36242; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]6243; VI-NEXT:    s_cbranch_execz .LBB50_26244; VI-NEXT:  .LBB50_4: ; %cmp.true6245; VI-NEXT:    v_add_u16_e32 v0, 3, v96246; VI-NEXT:    v_add_u16_e32 v1, 3, v26247; VI-NEXT:    v_or_b32_sdwa v0, v10, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_06248; VI-NEXT:    v_or_b32_sdwa v1, v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_06249; VI-NEXT:    v_mov_b32_e32 v2, 0x3006250; VI-NEXT:    v_add_u16_e32 v0, 0x300, v06251; VI-NEXT:    v_add_u16_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD6252; VI-NEXT:    v_or_b32_e32 v0, v0, v16253; VI-NEXT:    v_add_u16_e32 v1, 3, v46254; VI-NEXT:    v_add_u16_e32 v4, 3, v66255; VI-NEXT:    v_or_b32_sdwa v1, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_06256; VI-NEXT:    v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_06257; VI-NEXT:    v_add_u16_e32 v1, 0x300, v16258; VI-NEXT:    v_add_u16_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD6259; VI-NEXT:    v_or_b32_e32 v1, v1, v26260; VI-NEXT:    s_or_b64 exec, exec, s[4:5]6261; VI-NEXT:    s_setpc_b64 s[30:31]6262;6263; GFX9-LABEL: bitcast_v8i8_to_f64:6264; GFX9:       ; %bb.0:6265; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6266; GFX9-NEXT:    v_mov_b32_e32 v9, v06267; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v86268; GFX9-NEXT:    v_lshlrev_b16_e32 v10, 8, v16269; GFX9-NEXT:    v_lshlrev_b16_e32 v8, 8, v36270; GFX9-NEXT:    v_lshlrev_b16_e32 v5, 8, v56271; GFX9-NEXT:    v_lshlrev_b16_e32 v3, 8, v76272; GFX9-NEXT:    ; implicit-def: $vgpr0_vgpr16273; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc6274; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]6275; GFX9-NEXT:    s_cbranch_execnz .LBB50_36276; GFX9-NEXT:  ; %bb.1: ; %Flow6277; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]6278; GFX9-NEXT:    s_cbranch_execnz .LBB50_46279; GFX9-NEXT:  .LBB50_2: ; %end6280; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]6281; GFX9-NEXT:    s_setpc_b64 s[30:31]6282; GFX9-NEXT:  .LBB50_3: ; %cmp.false6283; GFX9-NEXT:    v_or_b32_sdwa v0, v9, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD6284; GFX9-NEXT:    v_or_b32_sdwa v1, v2, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD6285; GFX9-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD6286; GFX9-NEXT:    v_or_b32_sdwa v1, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD6287; GFX9-NEXT:    v_or_b32_sdwa v2, v6, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD6288; GFX9-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD6289; GFX9-NEXT:    ; implicit-def: $vgpr96290; GFX9-NEXT:    ; implicit-def: $vgpr106291; GFX9-NEXT:    ; implicit-def: $vgpr26292; GFX9-NEXT:    ; implicit-def: $vgpr86293; GFX9-NEXT:    ; implicit-def: $vgpr46294; GFX9-NEXT:    ; implicit-def: $vgpr56295; GFX9-NEXT:    ; implicit-def: $vgpr66296; GFX9-NEXT:    ; implicit-def: $vgpr36297; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]6298; GFX9-NEXT:    s_cbranch_execz .LBB50_26299; GFX9-NEXT:  .LBB50_4: ; %cmp.true6300; GFX9-NEXT:    v_add_u16_e32 v0, 3, v96301; GFX9-NEXT:    v_add_u16_e32 v1, 3, v26302; GFX9-NEXT:    v_or_b32_sdwa v0, v10, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_06303; GFX9-NEXT:    s_movk_i32 s6, 0x3006304; GFX9-NEXT:    v_or_b32_sdwa v1, v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_06305; GFX9-NEXT:    v_add_u16_e32 v0, 0x300, v06306; GFX9-NEXT:    v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD6307; GFX9-NEXT:    v_or_b32_e32 v0, v0, v16308; GFX9-NEXT:    v_add_u16_e32 v1, 3, v46309; GFX9-NEXT:    v_add_u16_e32 v2, 3, v66310; GFX9-NEXT:    v_or_b32_sdwa v1, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_06311; GFX9-NEXT:    v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_06312; GFX9-NEXT:    v_add_u16_e32 v1, 0x300, v16313; GFX9-NEXT:    v_add_u16_sdwa v2, v2, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD6314; GFX9-NEXT:    v_or_b32_e32 v1, v1, v26315; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]6316; GFX9-NEXT:    s_setpc_b64 s[30:31]6317;6318; GFX11-TRUE16-LABEL: bitcast_v8i8_to_f64:6319; GFX11-TRUE16:       ; %bb.0:6320; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6321; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.h, v5.l6322; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.h, v2.l6323; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v0.l6324; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.l, 8, v1.l6325; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.h, 8, v3.l6326; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.l, 8, v5.h6327; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.h, 8, v7.l6328; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo6329; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr16330; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v86331; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s06332; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB50_36333; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow6334; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s06335; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB50_46336; GFX11-TRUE16-NEXT:  .LBB50_2: ; %end6337; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s06338; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]6339; GFX11-TRUE16-NEXT:  .LBB50_3: ; %cmp.false6340; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v5.l6341; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v4.h6342; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v4.l6343; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v6.l6344; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo166345; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_hi166346; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_lo166347; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr6_lo166348; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)6349; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v2.l6350; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v0.h, v2.h6351; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)6352; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v3.l6353; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v1.h, v3.h6354; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_lo166355; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_hi166356; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo166357; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_hi166358; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s06359; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB50_26360; GFX11-TRUE16-NEXT:  .LBB50_4: ; %cmp.true6361; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v5.l, 36362; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v4.h, 36363; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v4.l, 36364; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v6.l, 36365; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)6366; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l6367; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h6368; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)6369; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l6370; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h6371; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)6372; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v2.l, v0.l6373; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v2.h, v0.h6374; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)6375; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v3.l, v1.l6376; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v3.h, v1.h6377; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)6378; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l6379; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, 0x300, v0.h6380; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)6381; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.l6382; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, 0x300, v1.h6383; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s06384; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]6385;6386; GFX11-FAKE16-LABEL: bitcast_v8i8_to_f64:6387; GFX11-FAKE16:       ; %bb.0:6388; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6389; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v9, v06390; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v86391; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v8, 8, v16392; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v3, 8, v36393; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v5, 8, v56394; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v7, 8, v76395; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr16396; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo6397; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)6398; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s06399; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB50_36400; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow6401; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s06402; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB50_46403; GFX11-FAKE16-NEXT:  .LBB50_2: ; %end6404; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s06405; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]6406; GFX11-FAKE16-NEXT:  .LBB50_3: ; %cmp.false6407; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v96408; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v26409; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v46410; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v66411; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr96412; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr66413; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)6414; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v86415; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v36416; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)6417; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v56418; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v4, v76419; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr86420; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr46421; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr56422; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr76423; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)6424; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v06425; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v16426; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)6427; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v26428; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v36429; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)6430; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v16431; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v36432; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr26433; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36434; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s06435; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB50_26436; GFX11-FAKE16-NEXT:  .LBB50_4: ; %cmp.true6437; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v9, 36438; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v2, 36439; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v4, 36440; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v6, 36441; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)6442; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v06443; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v16444; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)6445; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v26446; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v46447; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)6448; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v8, v06449; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v3, v16450; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)6451; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v5, v26452; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v7, v46453; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)6454; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v06455; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v16456; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)6457; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x300, v26458; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v36459; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)6460; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v06461; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v16462; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)6463; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v26464; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v36465; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)6466; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v16467; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v36468; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s06469; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]6470  %cmp = icmp eq i32 %b, 06471  br i1 %cmp, label %cmp.true, label %cmp.false6472 6473cmp.true:6474  %a1 = add <8 x i8> %a, splat (i8 3)6475  %a2 = bitcast <8 x i8> %a1 to double6476  br label %end6477 6478cmp.false:6479  %a3 = bitcast <8 x i8> %a to double6480  br label %end6481 6482end:6483  %phi = phi double [ %a2, %cmp.true ], [ %a3, %cmp.false ]6484  ret double %phi6485}6486 6487define inreg double @bitcast_v8i8_to_f64_scalar(<8 x i8> inreg %a, i32 inreg %b) {6488; SI-LABEL: bitcast_v8i8_to_f64_scalar:6489; SI:       ; %bb.0:6490; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6491; SI-NEXT:    s_cmp_lg_u32 s24, 06492; SI-NEXT:    s_cbranch_scc0 .LBB51_46493; SI-NEXT:  ; %bb.1: ; %cmp.false6494; SI-NEXT:    s_and_b32 s4, s16, 0xff6495; SI-NEXT:    s_lshl_b32 s5, s17, 86496; SI-NEXT:    s_or_b32 s4, s4, s56497; SI-NEXT:    s_and_b32 s5, s18, 0xff6498; SI-NEXT:    s_lshl_b32 s5, s5, 166499; SI-NEXT:    s_lshl_b32 s6, s19, 246500; SI-NEXT:    s_and_b32 s4, s4, 0xffff6501; SI-NEXT:    s_or_b32 s5, s6, s56502; SI-NEXT:    s_or_b32 s4, s4, s56503; SI-NEXT:    s_and_b32 s5, s20, 0xff6504; SI-NEXT:    s_lshl_b32 s6, s21, 86505; SI-NEXT:    s_or_b32 s5, s5, s66506; SI-NEXT:    s_and_b32 s6, s22, 0xff6507; SI-NEXT:    s_lshl_b32 s6, s6, 166508; SI-NEXT:    s_lshl_b32 s7, s23, 246509; SI-NEXT:    s_and_b32 s5, s5, 0xffff6510; SI-NEXT:    s_or_b32 s6, s7, s66511; SI-NEXT:    s_or_b32 s5, s5, s66512; SI-NEXT:    s_cbranch_execnz .LBB51_36513; SI-NEXT:  .LBB51_2: ; %cmp.true6514; SI-NEXT:    s_add_i32 s16, s16, 36515; SI-NEXT:    s_and_b32 s4, s16, 0xff6516; SI-NEXT:    s_lshl_b32 s5, s17, 86517; SI-NEXT:    s_add_i32 s18, s18, 36518; SI-NEXT:    s_or_b32 s4, s5, s46519; SI-NEXT:    s_and_b32 s6, s18, 0xff6520; SI-NEXT:    s_addk_i32 s4, 0x3006521; SI-NEXT:    s_lshl_b32 s5, s19, 246522; SI-NEXT:    s_lshl_b32 s6, s6, 166523; SI-NEXT:    s_and_b32 s4, s4, 0xffff6524; SI-NEXT:    s_or_b32 s5, s5, s66525; SI-NEXT:    s_add_i32 s20, s20, 36526; SI-NEXT:    s_or_b32 s4, s5, s46527; SI-NEXT:    s_and_b32 s5, s20, 0xff6528; SI-NEXT:    s_lshl_b32 s6, s21, 86529; SI-NEXT:    s_add_i32 s22, s22, 36530; SI-NEXT:    s_or_b32 s5, s6, s56531; SI-NEXT:    s_and_b32 s7, s22, 0xff6532; SI-NEXT:    s_addk_i32 s5, 0x3006533; SI-NEXT:    s_lshl_b32 s6, s23, 246534; SI-NEXT:    s_lshl_b32 s7, s7, 166535; SI-NEXT:    s_and_b32 s5, s5, 0xffff6536; SI-NEXT:    s_or_b32 s6, s6, s76537; SI-NEXT:    s_or_b32 s5, s6, s56538; SI-NEXT:    s_add_i32 s4, s4, 0x30000006539; SI-NEXT:    s_add_i32 s5, s5, 0x30000006540; SI-NEXT:  .LBB51_3: ; %end6541; SI-NEXT:    v_mov_b32_e32 v0, s46542; SI-NEXT:    v_mov_b32_e32 v1, s56543; SI-NEXT:    s_setpc_b64 s[30:31]6544; SI-NEXT:  .LBB51_4:6545; SI-NEXT:    ; implicit-def: $sgpr4_sgpr56546; SI-NEXT:    s_branch .LBB51_26547;6548; VI-LABEL: bitcast_v8i8_to_f64_scalar:6549; VI:       ; %bb.0:6550; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6551; VI-NEXT:    s_cmp_lg_u32 s24, 06552; VI-NEXT:    s_cbranch_scc0 .LBB51_46553; VI-NEXT:  ; %bb.1: ; %cmp.false6554; VI-NEXT:    s_and_b32 s4, s16, 0xff6555; VI-NEXT:    s_lshl_b32 s5, s17, 86556; VI-NEXT:    s_or_b32 s4, s4, s56557; VI-NEXT:    s_and_b32 s5, s18, 0xff6558; VI-NEXT:    s_lshl_b32 s6, s19, 86559; VI-NEXT:    s_or_b32 s5, s5, s66560; VI-NEXT:    s_and_b32 s4, s4, 0xffff6561; VI-NEXT:    s_lshl_b32 s5, s5, 166562; VI-NEXT:    s_or_b32 s4, s4, s56563; VI-NEXT:    s_and_b32 s5, s20, 0xff6564; VI-NEXT:    s_lshl_b32 s6, s21, 86565; VI-NEXT:    s_or_b32 s5, s5, s66566; VI-NEXT:    s_and_b32 s6, s22, 0xff6567; VI-NEXT:    s_lshl_b32 s7, s23, 86568; VI-NEXT:    s_or_b32 s6, s6, s76569; VI-NEXT:    s_and_b32 s5, s5, 0xffff6570; VI-NEXT:    s_lshl_b32 s6, s6, 166571; VI-NEXT:    s_or_b32 s5, s5, s66572; VI-NEXT:    s_cbranch_execnz .LBB51_36573; VI-NEXT:  .LBB51_2: ; %cmp.true6574; VI-NEXT:    s_add_i32 s16, s16, 36575; VI-NEXT:    s_and_b32 s4, s16, 0xff6576; VI-NEXT:    s_lshl_b32 s5, s17, 86577; VI-NEXT:    s_add_i32 s18, s18, 36578; VI-NEXT:    s_or_b32 s4, s5, s46579; VI-NEXT:    s_and_b32 s5, s18, 0xff6580; VI-NEXT:    s_lshl_b32 s6, s19, 86581; VI-NEXT:    s_addk_i32 s4, 0x3006582; VI-NEXT:    s_or_b32 s5, s6, s56583; VI-NEXT:    s_and_b32 s4, s4, 0xffff6584; VI-NEXT:    s_lshl_b32 s5, s5, 166585; VI-NEXT:    s_add_i32 s20, s20, 36586; VI-NEXT:    s_or_b32 s4, s5, s46587; VI-NEXT:    s_and_b32 s5, s20, 0xff6588; VI-NEXT:    s_lshl_b32 s6, s21, 86589; VI-NEXT:    s_add_i32 s22, s22, 36590; VI-NEXT:    s_or_b32 s5, s6, s56591; VI-NEXT:    s_and_b32 s6, s22, 0xff6592; VI-NEXT:    s_lshl_b32 s7, s23, 86593; VI-NEXT:    s_addk_i32 s5, 0x3006594; VI-NEXT:    s_or_b32 s6, s7, s66595; VI-NEXT:    s_and_b32 s5, s5, 0xffff6596; VI-NEXT:    s_lshl_b32 s6, s6, 166597; VI-NEXT:    s_or_b32 s5, s6, s56598; VI-NEXT:    s_add_i32 s4, s4, 0x30000006599; VI-NEXT:    s_add_i32 s5, s5, 0x30000006600; VI-NEXT:  .LBB51_3: ; %end6601; VI-NEXT:    v_mov_b32_e32 v0, s46602; VI-NEXT:    v_mov_b32_e32 v1, s56603; VI-NEXT:    s_setpc_b64 s[30:31]6604; VI-NEXT:  .LBB51_4:6605; VI-NEXT:    ; implicit-def: $sgpr4_sgpr56606; VI-NEXT:    s_branch .LBB51_26607;6608; GFX9-LABEL: bitcast_v8i8_to_f64_scalar:6609; GFX9:       ; %bb.0:6610; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6611; GFX9-NEXT:    s_cmp_lg_u32 s24, 06612; GFX9-NEXT:    s_cbranch_scc0 .LBB51_46613; GFX9-NEXT:  ; %bb.1: ; %cmp.false6614; GFX9-NEXT:    s_and_b32 s4, s16, 0xff6615; GFX9-NEXT:    s_lshl_b32 s5, s17, 86616; GFX9-NEXT:    s_or_b32 s4, s4, s56617; GFX9-NEXT:    s_and_b32 s5, s18, 0xff6618; GFX9-NEXT:    s_lshl_b32 s6, s19, 86619; GFX9-NEXT:    s_or_b32 s5, s5, s66620; GFX9-NEXT:    s_and_b32 s4, s4, 0xffff6621; GFX9-NEXT:    s_lshl_b32 s5, s5, 166622; GFX9-NEXT:    s_or_b32 s4, s4, s56623; GFX9-NEXT:    s_and_b32 s5, s20, 0xff6624; GFX9-NEXT:    s_lshl_b32 s6, s21, 86625; GFX9-NEXT:    s_or_b32 s5, s5, s66626; GFX9-NEXT:    s_and_b32 s6, s22, 0xff6627; GFX9-NEXT:    s_lshl_b32 s7, s23, 86628; GFX9-NEXT:    s_or_b32 s6, s6, s76629; GFX9-NEXT:    s_and_b32 s5, s5, 0xffff6630; GFX9-NEXT:    s_lshl_b32 s6, s6, 166631; GFX9-NEXT:    s_or_b32 s5, s5, s66632; GFX9-NEXT:    s_cbranch_execnz .LBB51_36633; GFX9-NEXT:  .LBB51_2: ; %cmp.true6634; GFX9-NEXT:    s_add_i32 s16, s16, 36635; GFX9-NEXT:    s_and_b32 s4, s16, 0xff6636; GFX9-NEXT:    s_lshl_b32 s5, s17, 86637; GFX9-NEXT:    s_add_i32 s18, s18, 36638; GFX9-NEXT:    s_or_b32 s4, s5, s46639; GFX9-NEXT:    s_and_b32 s5, s18, 0xff6640; GFX9-NEXT:    s_lshl_b32 s6, s19, 86641; GFX9-NEXT:    s_or_b32 s5, s6, s56642; GFX9-NEXT:    s_addk_i32 s4, 0x3006643; GFX9-NEXT:    s_addk_i32 s5, 0x3006644; GFX9-NEXT:    s_and_b32 s4, s4, 0xffff6645; GFX9-NEXT:    s_lshl_b32 s5, s5, 166646; GFX9-NEXT:    s_add_i32 s20, s20, 36647; GFX9-NEXT:    s_or_b32 s4, s4, s56648; GFX9-NEXT:    s_and_b32 s5, s20, 0xff6649; GFX9-NEXT:    s_lshl_b32 s6, s21, 86650; GFX9-NEXT:    s_add_i32 s22, s22, 36651; GFX9-NEXT:    s_or_b32 s5, s6, s56652; GFX9-NEXT:    s_and_b32 s6, s22, 0xff6653; GFX9-NEXT:    s_lshl_b32 s7, s23, 86654; GFX9-NEXT:    s_or_b32 s6, s7, s66655; GFX9-NEXT:    s_addk_i32 s5, 0x3006656; GFX9-NEXT:    s_addk_i32 s6, 0x3006657; GFX9-NEXT:    s_and_b32 s5, s5, 0xffff6658; GFX9-NEXT:    s_lshl_b32 s6, s6, 166659; GFX9-NEXT:    s_or_b32 s5, s5, s66660; GFX9-NEXT:  .LBB51_3: ; %end6661; GFX9-NEXT:    v_mov_b32_e32 v0, s46662; GFX9-NEXT:    v_mov_b32_e32 v1, s56663; GFX9-NEXT:    s_setpc_b64 s[30:31]6664; GFX9-NEXT:  .LBB51_4:6665; GFX9-NEXT:    ; implicit-def: $sgpr4_sgpr56666; GFX9-NEXT:    s_branch .LBB51_26667;6668; GFX11-LABEL: bitcast_v8i8_to_f64_scalar:6669; GFX11:       ; %bb.0:6670; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6671; GFX11-NEXT:    s_cmp_lg_u32 s20, 06672; GFX11-NEXT:    s_mov_b32 s6, 06673; GFX11-NEXT:    s_cbranch_scc0 .LBB51_46674; GFX11-NEXT:  ; %bb.1: ; %cmp.false6675; GFX11-NEXT:    s_and_b32 s4, s0, 0xff6676; GFX11-NEXT:    s_lshl_b32 s5, s1, 86677; GFX11-NEXT:    s_and_b32 s7, s2, 0xff6678; GFX11-NEXT:    s_lshl_b32 s8, s3, 86679; GFX11-NEXT:    s_or_b32 s4, s4, s56680; GFX11-NEXT:    s_or_b32 s5, s7, s86681; GFX11-NEXT:    s_and_b32 s7, s16, 0xff6682; GFX11-NEXT:    s_lshl_b32 s8, s17, 86683; GFX11-NEXT:    s_and_b32 s9, s18, 0xff6684; GFX11-NEXT:    s_lshl_b32 s10, s19, 86685; GFX11-NEXT:    s_or_b32 s7, s7, s86686; GFX11-NEXT:    s_or_b32 s8, s9, s106687; GFX11-NEXT:    s_and_b32 s4, s4, 0xffff6688; GFX11-NEXT:    s_lshl_b32 s5, s5, 166689; GFX11-NEXT:    s_and_b32 s7, s7, 0xffff6690; GFX11-NEXT:    s_lshl_b32 s8, s8, 166691; GFX11-NEXT:    s_or_b32 s4, s4, s56692; GFX11-NEXT:    s_or_b32 s5, s7, s86693; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s66694; GFX11-NEXT:    s_cbranch_vccnz .LBB51_36695; GFX11-NEXT:  .LBB51_2: ; %cmp.true6696; GFX11-NEXT:    s_add_i32 s0, s0, 36697; GFX11-NEXT:    s_lshl_b32 s1, s1, 86698; GFX11-NEXT:    s_and_b32 s0, s0, 0xff6699; GFX11-NEXT:    s_add_i32 s2, s2, 36700; GFX11-NEXT:    s_or_b32 s0, s1, s06701; GFX11-NEXT:    s_and_b32 s1, s2, 0xff6702; GFX11-NEXT:    s_lshl_b32 s2, s3, 86703; GFX11-NEXT:    s_add_i32 s16, s16, 36704; GFX11-NEXT:    s_add_i32 s18, s18, 36705; GFX11-NEXT:    s_or_b32 s1, s2, s16706; GFX11-NEXT:    s_and_b32 s2, s16, 0xff6707; GFX11-NEXT:    s_lshl_b32 s3, s17, 86708; GFX11-NEXT:    s_and_b32 s4, s18, 0xff6709; GFX11-NEXT:    s_lshl_b32 s5, s19, 86710; GFX11-NEXT:    s_or_b32 s2, s3, s26711; GFX11-NEXT:    s_or_b32 s3, s5, s46712; GFX11-NEXT:    s_addk_i32 s0, 0x3006713; GFX11-NEXT:    s_addk_i32 s1, 0x3006714; GFX11-NEXT:    s_addk_i32 s2, 0x3006715; GFX11-NEXT:    s_addk_i32 s3, 0x3006716; GFX11-NEXT:    s_and_b32 s0, s0, 0xffff6717; GFX11-NEXT:    s_lshl_b32 s1, s1, 166718; GFX11-NEXT:    s_and_b32 s2, s2, 0xffff6719; GFX11-NEXT:    s_lshl_b32 s3, s3, 166720; GFX11-NEXT:    s_or_b32 s4, s0, s16721; GFX11-NEXT:    s_or_b32 s5, s2, s36722; GFX11-NEXT:  .LBB51_3: ; %end6723; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)6724; GFX11-NEXT:    v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s56725; GFX11-NEXT:    s_setpc_b64 s[30:31]6726; GFX11-NEXT:  .LBB51_4:6727; GFX11-NEXT:    ; implicit-def: $sgpr4_sgpr56728; GFX11-NEXT:    s_branch .LBB51_26729  %cmp = icmp eq i32 %b, 06730  br i1 %cmp, label %cmp.true, label %cmp.false6731 6732cmp.true:6733  %a1 = add <8 x i8> %a, splat (i8 3)6734  %a2 = bitcast <8 x i8> %a1 to double6735  br label %end6736 6737cmp.false:6738  %a3 = bitcast <8 x i8> %a to double6739  br label %end6740 6741end:6742  %phi = phi double [ %a2, %cmp.true ], [ %a3, %cmp.false ]6743  ret double %phi6744}6745 6746define <2 x float> @bitcast_v2i32_to_v2f32(<2 x i32> %a, i32 %b) {6747; SI-LABEL: bitcast_v2i32_to_v2f32:6748; SI:       ; %bb.0:6749; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6750; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v26751; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc6752; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]6753; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]6754; SI-NEXT:  ; %bb.1: ; %cmp.true6755; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v16756; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v06757; SI-NEXT:  ; %bb.2: ; %end6758; SI-NEXT:    s_or_b64 exec, exec, s[4:5]6759; SI-NEXT:    s_setpc_b64 s[30:31]6760;6761; VI-LABEL: bitcast_v2i32_to_v2f32:6762; VI:       ; %bb.0:6763; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6764; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v26765; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc6766; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]6767; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]6768; VI-NEXT:  ; %bb.1: ; %cmp.true6769; VI-NEXT:    v_add_u32_e32 v1, vcc, 3, v16770; VI-NEXT:    v_add_u32_e32 v0, vcc, 3, v06771; VI-NEXT:  ; %bb.2: ; %end6772; VI-NEXT:    s_or_b64 exec, exec, s[4:5]6773; VI-NEXT:    s_setpc_b64 s[30:31]6774;6775; GFX9-LABEL: bitcast_v2i32_to_v2f32:6776; GFX9:       ; %bb.0:6777; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6778; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v26779; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc6780; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]6781; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]6782; GFX9-NEXT:  ; %bb.1: ; %cmp.true6783; GFX9-NEXT:    v_add_u32_e32 v1, 3, v16784; GFX9-NEXT:    v_add_u32_e32 v0, 3, v06785; GFX9-NEXT:  ; %bb.2: ; %end6786; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]6787; GFX9-NEXT:    s_setpc_b64 s[30:31]6788;6789; GFX11-LABEL: bitcast_v2i32_to_v2f32:6790; GFX11:       ; %bb.0:6791; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6792; GFX11-NEXT:    s_mov_b32 s0, exec_lo6793; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v26794; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s06795; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)6796; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s06797; GFX11-NEXT:  ; %bb.1: ; %cmp.true6798; GFX11-NEXT:    v_add_nc_u32_e32 v1, 3, v16799; GFX11-NEXT:    v_add_nc_u32_e32 v0, 3, v06800; GFX11-NEXT:  ; %bb.2: ; %end6801; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s06802; GFX11-NEXT:    s_setpc_b64 s[30:31]6803  %cmp = icmp eq i32 %b, 06804  br i1 %cmp, label %cmp.true, label %cmp.false6805 6806cmp.true:6807  %a1 = add <2 x i32> %a, splat (i32 3)6808  %a2 = bitcast <2 x i32> %a1 to <2 x float>6809  br label %end6810 6811cmp.false:6812  %a3 = bitcast <2 x i32> %a to <2 x float>6813  br label %end6814 6815end:6816  %phi = phi <2 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]6817  ret <2 x float> %phi6818}6819 6820define inreg <2 x float> @bitcast_v2i32_to_v2f32_scalar(<2 x i32> inreg %a, i32 inreg %b) {6821; SI-LABEL: bitcast_v2i32_to_v2f32_scalar:6822; SI:       ; %bb.0:6823; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6824; SI-NEXT:    s_cmp_lg_u32 s18, 06825; SI-NEXT:    s_cbranch_scc0 .LBB53_46826; SI-NEXT:  ; %bb.1: ; %cmp.false6827; SI-NEXT:    s_cbranch_execnz .LBB53_36828; SI-NEXT:  .LBB53_2: ; %cmp.true6829; SI-NEXT:    s_add_i32 s17, s17, 36830; SI-NEXT:    s_add_i32 s16, s16, 36831; SI-NEXT:  .LBB53_3: ; %end6832; SI-NEXT:    v_mov_b32_e32 v0, s166833; SI-NEXT:    v_mov_b32_e32 v1, s176834; SI-NEXT:    s_setpc_b64 s[30:31]6835; SI-NEXT:  .LBB53_4:6836; SI-NEXT:    s_branch .LBB53_26837;6838; VI-LABEL: bitcast_v2i32_to_v2f32_scalar:6839; VI:       ; %bb.0:6840; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6841; VI-NEXT:    s_cmp_lg_u32 s18, 06842; VI-NEXT:    s_cbranch_scc0 .LBB53_46843; VI-NEXT:  ; %bb.1: ; %cmp.false6844; VI-NEXT:    s_cbranch_execnz .LBB53_36845; VI-NEXT:  .LBB53_2: ; %cmp.true6846; VI-NEXT:    s_add_i32 s17, s17, 36847; VI-NEXT:    s_add_i32 s16, s16, 36848; VI-NEXT:  .LBB53_3: ; %end6849; VI-NEXT:    v_mov_b32_e32 v0, s166850; VI-NEXT:    v_mov_b32_e32 v1, s176851; VI-NEXT:    s_setpc_b64 s[30:31]6852; VI-NEXT:  .LBB53_4:6853; VI-NEXT:    s_branch .LBB53_26854;6855; GFX9-LABEL: bitcast_v2i32_to_v2f32_scalar:6856; GFX9:       ; %bb.0:6857; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6858; GFX9-NEXT:    s_cmp_lg_u32 s18, 06859; GFX9-NEXT:    s_cbranch_scc0 .LBB53_46860; GFX9-NEXT:  ; %bb.1: ; %cmp.false6861; GFX9-NEXT:    s_cbranch_execnz .LBB53_36862; GFX9-NEXT:  .LBB53_2: ; %cmp.true6863; GFX9-NEXT:    s_add_i32 s17, s17, 36864; GFX9-NEXT:    s_add_i32 s16, s16, 36865; GFX9-NEXT:  .LBB53_3: ; %end6866; GFX9-NEXT:    v_mov_b32_e32 v0, s166867; GFX9-NEXT:    v_mov_b32_e32 v1, s176868; GFX9-NEXT:    s_setpc_b64 s[30:31]6869; GFX9-NEXT:  .LBB53_4:6870; GFX9-NEXT:    s_branch .LBB53_26871;6872; GFX11-LABEL: bitcast_v2i32_to_v2f32_scalar:6873; GFX11:       ; %bb.0:6874; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6875; GFX11-NEXT:    s_cmp_lg_u32 s2, 06876; GFX11-NEXT:    s_mov_b32 s2, 06877; GFX11-NEXT:    s_cbranch_scc0 .LBB53_46878; GFX11-NEXT:  ; %bb.1: ; %Flow6879; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s26880; GFX11-NEXT:    s_cbranch_vccnz .LBB53_36881; GFX11-NEXT:  .LBB53_2: ; %cmp.true6882; GFX11-NEXT:    s_add_i32 s1, s1, 36883; GFX11-NEXT:    s_add_i32 s0, s0, 36884; GFX11-NEXT:  .LBB53_3: ; %end6885; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)6886; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s16887; GFX11-NEXT:    s_setpc_b64 s[30:31]6888; GFX11-NEXT:  .LBB53_4:6889; GFX11-NEXT:    s_branch .LBB53_26890  %cmp = icmp eq i32 %b, 06891  br i1 %cmp, label %cmp.true, label %cmp.false6892 6893cmp.true:6894  %a1 = add <2 x i32> %a, splat (i32 3)6895  %a2 = bitcast <2 x i32> %a1 to <2 x float>6896  br label %end6897 6898cmp.false:6899  %a3 = bitcast <2 x i32> %a to <2 x float>6900  br label %end6901 6902end:6903  %phi = phi <2 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]6904  ret <2 x float> %phi6905}6906 6907define <2 x i32> @bitcast_v2f32_to_v2i32(<2 x float> %a, i32 %b) {6908; SI-LABEL: bitcast_v2f32_to_v2i32:6909; SI:       ; %bb.0:6910; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6911; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v26912; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc6913; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]6914; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]6915; SI-NEXT:  ; %bb.1: ; %cmp.true6916; SI-NEXT:    v_add_f32_e32 v1, 1.0, v16917; SI-NEXT:    v_add_f32_e32 v0, 1.0, v06918; SI-NEXT:  ; %bb.2: ; %end6919; SI-NEXT:    s_or_b64 exec, exec, s[4:5]6920; SI-NEXT:    s_setpc_b64 s[30:31]6921;6922; VI-LABEL: bitcast_v2f32_to_v2i32:6923; VI:       ; %bb.0:6924; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6925; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v26926; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc6927; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]6928; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]6929; VI-NEXT:  ; %bb.1: ; %cmp.true6930; VI-NEXT:    v_add_f32_e32 v1, 1.0, v16931; VI-NEXT:    v_add_f32_e32 v0, 1.0, v06932; VI-NEXT:  ; %bb.2: ; %end6933; VI-NEXT:    s_or_b64 exec, exec, s[4:5]6934; VI-NEXT:    s_setpc_b64 s[30:31]6935;6936; GFX9-LABEL: bitcast_v2f32_to_v2i32:6937; GFX9:       ; %bb.0:6938; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6939; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v26940; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc6941; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]6942; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]6943; GFX9-NEXT:  ; %bb.1: ; %cmp.true6944; GFX9-NEXT:    v_add_f32_e32 v1, 1.0, v16945; GFX9-NEXT:    v_add_f32_e32 v0, 1.0, v06946; GFX9-NEXT:  ; %bb.2: ; %end6947; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]6948; GFX9-NEXT:    s_setpc_b64 s[30:31]6949;6950; GFX11-LABEL: bitcast_v2f32_to_v2i32:6951; GFX11:       ; %bb.0:6952; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6953; GFX11-NEXT:    s_mov_b32 s0, exec_lo6954; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v26955; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s06956; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)6957; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s06958; GFX11-NEXT:  ; %bb.1: ; %cmp.true6959; GFX11-NEXT:    v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v06960; GFX11-NEXT:  ; %bb.2: ; %end6961; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s06962; GFX11-NEXT:    s_setpc_b64 s[30:31]6963  %cmp = icmp eq i32 %b, 06964  br i1 %cmp, label %cmp.true, label %cmp.false6965 6966cmp.true:6967  %a1 = fadd <2 x float> %a, splat (float 1.000000e+00)6968  %a2 = bitcast <2 x float> %a1 to <2 x i32>6969  br label %end6970 6971cmp.false:6972  %a3 = bitcast <2 x float> %a to <2 x i32>6973  br label %end6974 6975end:6976  %phi = phi <2 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]6977  ret <2 x i32> %phi6978}6979 6980define inreg <2 x i32> @bitcast_v2f32_to_v2i32_scalar(<2 x float> inreg %a, i32 inreg %b) {6981; SI-LABEL: bitcast_v2f32_to_v2i32_scalar:6982; SI:       ; %bb.0:6983; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6984; SI-NEXT:    s_cmp_lg_u32 s18, 06985; SI-NEXT:    s_cbranch_scc0 .LBB55_36986; SI-NEXT:  ; %bb.1: ; %cmp.false6987; SI-NEXT:    s_cbranch_execnz .LBB55_46988; SI-NEXT:  .LBB55_2: ; %cmp.true6989; SI-NEXT:    v_add_f32_e64 v1, s17, 1.06990; SI-NEXT:    v_add_f32_e64 v0, s16, 1.06991; SI-NEXT:    s_setpc_b64 s[30:31]6992; SI-NEXT:  .LBB55_3:6993; SI-NEXT:    s_branch .LBB55_26994; SI-NEXT:  .LBB55_4:6995; SI-NEXT:    v_mov_b32_e32 v0, s166996; SI-NEXT:    v_mov_b32_e32 v1, s176997; SI-NEXT:    s_setpc_b64 s[30:31]6998;6999; VI-LABEL: bitcast_v2f32_to_v2i32_scalar:7000; VI:       ; %bb.0:7001; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7002; VI-NEXT:    s_cmp_lg_u32 s18, 07003; VI-NEXT:    s_cbranch_scc0 .LBB55_37004; VI-NEXT:  ; %bb.1: ; %cmp.false7005; VI-NEXT:    s_cbranch_execnz .LBB55_47006; VI-NEXT:  .LBB55_2: ; %cmp.true7007; VI-NEXT:    v_add_f32_e64 v1, s17, 1.07008; VI-NEXT:    v_add_f32_e64 v0, s16, 1.07009; VI-NEXT:    s_setpc_b64 s[30:31]7010; VI-NEXT:  .LBB55_3:7011; VI-NEXT:    s_branch .LBB55_27012; VI-NEXT:  .LBB55_4:7013; VI-NEXT:    v_mov_b32_e32 v0, s167014; VI-NEXT:    v_mov_b32_e32 v1, s177015; VI-NEXT:    s_setpc_b64 s[30:31]7016;7017; GFX9-LABEL: bitcast_v2f32_to_v2i32_scalar:7018; GFX9:       ; %bb.0:7019; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7020; GFX9-NEXT:    s_cmp_lg_u32 s18, 07021; GFX9-NEXT:    s_cbranch_scc0 .LBB55_37022; GFX9-NEXT:  ; %bb.1: ; %cmp.false7023; GFX9-NEXT:    s_cbranch_execnz .LBB55_47024; GFX9-NEXT:  .LBB55_2: ; %cmp.true7025; GFX9-NEXT:    v_add_f32_e64 v1, s17, 1.07026; GFX9-NEXT:    v_add_f32_e64 v0, s16, 1.07027; GFX9-NEXT:    s_setpc_b64 s[30:31]7028; GFX9-NEXT:  .LBB55_3:7029; GFX9-NEXT:    s_branch .LBB55_27030; GFX9-NEXT:  .LBB55_4:7031; GFX9-NEXT:    v_mov_b32_e32 v0, s167032; GFX9-NEXT:    v_mov_b32_e32 v1, s177033; GFX9-NEXT:    s_setpc_b64 s[30:31]7034;7035; GFX11-LABEL: bitcast_v2f32_to_v2i32_scalar:7036; GFX11:       ; %bb.0:7037; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7038; GFX11-NEXT:    s_cmp_lg_u32 s2, 07039; GFX11-NEXT:    s_mov_b32 s2, 07040; GFX11-NEXT:    s_cbranch_scc0 .LBB55_37041; GFX11-NEXT:  ; %bb.1: ; %Flow7042; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s27043; GFX11-NEXT:    s_cbranch_vccnz .LBB55_47044; GFX11-NEXT:  .LBB55_2: ; %cmp.true7045; GFX11-NEXT:    v_add_f32_e64 v1, s1, 1.07046; GFX11-NEXT:    v_add_f32_e64 v0, s0, 1.07047; GFX11-NEXT:    s_setpc_b64 s[30:31]7048; GFX11-NEXT:  .LBB55_3:7049; GFX11-NEXT:    s_branch .LBB55_27050; GFX11-NEXT:  .LBB55_4:7051; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s17052; GFX11-NEXT:    s_setpc_b64 s[30:31]7053  %cmp = icmp eq i32 %b, 07054  br i1 %cmp, label %cmp.true, label %cmp.false7055 7056cmp.true:7057  %a1 = fadd <2 x float> %a, splat (float 1.000000e+00)7058  %a2 = bitcast <2 x float> %a1 to <2 x i32>7059  br label %end7060 7061cmp.false:7062  %a3 = bitcast <2 x float> %a to <2 x i32>7063  br label %end7064 7065end:7066  %phi = phi <2 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]7067  ret <2 x i32> %phi7068}7069 7070define <4 x i16> @bitcast_v2i32_to_v4i16(<2 x i32> %a, i32 %b) {7071; SI-LABEL: bitcast_v2i32_to_v4i16:7072; SI:       ; %bb.0:7073; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7074; SI-NEXT:    v_mov_b32_e32 v4, v17075; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v27076; SI-NEXT:    ; implicit-def: $vgpr17077; SI-NEXT:    ; implicit-def: $vgpr37078; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc7079; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]7080; SI-NEXT:  ; %bb.1: ; %cmp.false7081; SI-NEXT:    v_alignbit_b32 v1, v4, v0, 167082; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v47083; SI-NEXT:  ; %bb.2: ; %Flow7084; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]7085; SI-NEXT:  ; %bb.3: ; %cmp.true7086; SI-NEXT:    v_add_i32_e32 v4, vcc, 3, v47087; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v07088; SI-NEXT:    v_alignbit_b32 v1, v4, v0, 167089; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v47090; SI-NEXT:  ; %bb.4: ; %end7091; SI-NEXT:    s_or_b64 exec, exec, s[4:5]7092; SI-NEXT:    v_mov_b32_e32 v2, v47093; SI-NEXT:    s_setpc_b64 s[30:31]7094;7095; VI-LABEL: bitcast_v2i32_to_v4i16:7096; VI:       ; %bb.0:7097; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7098; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v27099; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc7100; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]7101; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]7102; VI-NEXT:  ; %bb.1: ; %cmp.true7103; VI-NEXT:    v_add_u32_e32 v1, vcc, 3, v17104; VI-NEXT:    v_add_u32_e32 v0, vcc, 3, v07105; VI-NEXT:  ; %bb.2: ; %end7106; VI-NEXT:    s_or_b64 exec, exec, s[4:5]7107; VI-NEXT:    s_setpc_b64 s[30:31]7108;7109; GFX9-LABEL: bitcast_v2i32_to_v4i16:7110; GFX9:       ; %bb.0:7111; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7112; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v27113; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc7114; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]7115; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]7116; GFX9-NEXT:  ; %bb.1: ; %cmp.true7117; GFX9-NEXT:    v_add_u32_e32 v1, 3, v17118; GFX9-NEXT:    v_add_u32_e32 v0, 3, v07119; GFX9-NEXT:  ; %bb.2: ; %end7120; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]7121; GFX9-NEXT:    s_setpc_b64 s[30:31]7122;7123; GFX11-LABEL: bitcast_v2i32_to_v4i16:7124; GFX11:       ; %bb.0:7125; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7126; GFX11-NEXT:    s_mov_b32 s0, exec_lo7127; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v27128; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s07129; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)7130; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s07131; GFX11-NEXT:  ; %bb.1: ; %cmp.true7132; GFX11-NEXT:    v_add_nc_u32_e32 v1, 3, v17133; GFX11-NEXT:    v_add_nc_u32_e32 v0, 3, v07134; GFX11-NEXT:  ; %bb.2: ; %end7135; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s07136; GFX11-NEXT:    s_setpc_b64 s[30:31]7137  %cmp = icmp eq i32 %b, 07138  br i1 %cmp, label %cmp.true, label %cmp.false7139 7140cmp.true:7141  %a1 = add <2 x i32> %a, splat (i32 3)7142  %a2 = bitcast <2 x i32> %a1 to <4 x i16>7143  br label %end7144 7145cmp.false:7146  %a3 = bitcast <2 x i32> %a to <4 x i16>7147  br label %end7148 7149end:7150  %phi = phi <4 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]7151  ret <4 x i16> %phi7152}7153 7154define inreg <4 x i16> @bitcast_v2i32_to_v4i16_scalar(<2 x i32> inreg %a, i32 inreg %b) {7155; SI-LABEL: bitcast_v2i32_to_v4i16_scalar:7156; SI:       ; %bb.0:7157; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7158; SI-NEXT:    s_cmp_lg_u32 s18, 07159; SI-NEXT:    s_cbranch_scc0 .LBB57_47160; SI-NEXT:  ; %bb.1: ; %cmp.false7161; SI-NEXT:    s_lshr_b32 s8, s17, 167162; SI-NEXT:    s_lshr_b64 s[4:5], s[16:17], 167163; SI-NEXT:    s_cbranch_execnz .LBB57_37164; SI-NEXT:  .LBB57_2: ; %cmp.true7165; SI-NEXT:    s_add_i32 s17, s17, 37166; SI-NEXT:    s_add_i32 s16, s16, 37167; SI-NEXT:    s_lshr_b64 s[4:5], s[16:17], 167168; SI-NEXT:    s_lshr_b32 s8, s17, 167169; SI-NEXT:  .LBB57_3: ; %end7170; SI-NEXT:    v_mov_b32_e32 v0, s167171; SI-NEXT:    v_mov_b32_e32 v1, s47172; SI-NEXT:    v_mov_b32_e32 v2, s177173; SI-NEXT:    v_mov_b32_e32 v3, s87174; SI-NEXT:    s_setpc_b64 s[30:31]7175; SI-NEXT:  .LBB57_4:7176; SI-NEXT:    ; implicit-def: $sgpr47177; SI-NEXT:    ; implicit-def: $sgpr87178; SI-NEXT:    s_branch .LBB57_27179;7180; VI-LABEL: bitcast_v2i32_to_v4i16_scalar:7181; VI:       ; %bb.0:7182; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7183; VI-NEXT:    s_cmp_lg_u32 s18, 07184; VI-NEXT:    s_cbranch_scc0 .LBB57_47185; VI-NEXT:  ; %bb.1: ; %cmp.false7186; VI-NEXT:    s_cbranch_execnz .LBB57_37187; VI-NEXT:  .LBB57_2: ; %cmp.true7188; VI-NEXT:    s_add_i32 s17, s17, 37189; VI-NEXT:    s_add_i32 s16, s16, 37190; VI-NEXT:  .LBB57_3: ; %end7191; VI-NEXT:    v_mov_b32_e32 v0, s167192; VI-NEXT:    v_mov_b32_e32 v1, s177193; VI-NEXT:    s_setpc_b64 s[30:31]7194; VI-NEXT:  .LBB57_4:7195; VI-NEXT:    s_branch .LBB57_27196;7197; GFX9-LABEL: bitcast_v2i32_to_v4i16_scalar:7198; GFX9:       ; %bb.0:7199; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7200; GFX9-NEXT:    s_cmp_lg_u32 s18, 07201; GFX9-NEXT:    s_cbranch_scc0 .LBB57_47202; GFX9-NEXT:  ; %bb.1: ; %cmp.false7203; GFX9-NEXT:    s_cbranch_execnz .LBB57_37204; GFX9-NEXT:  .LBB57_2: ; %cmp.true7205; GFX9-NEXT:    s_add_i32 s17, s17, 37206; GFX9-NEXT:    s_add_i32 s16, s16, 37207; GFX9-NEXT:  .LBB57_3: ; %end7208; GFX9-NEXT:    v_mov_b32_e32 v0, s167209; GFX9-NEXT:    v_mov_b32_e32 v1, s177210; GFX9-NEXT:    s_setpc_b64 s[30:31]7211; GFX9-NEXT:  .LBB57_4:7212; GFX9-NEXT:    s_branch .LBB57_27213;7214; GFX11-LABEL: bitcast_v2i32_to_v4i16_scalar:7215; GFX11:       ; %bb.0:7216; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7217; GFX11-NEXT:    s_cmp_lg_u32 s2, 07218; GFX11-NEXT:    s_mov_b32 s2, 07219; GFX11-NEXT:    s_cbranch_scc0 .LBB57_47220; GFX11-NEXT:  ; %bb.1: ; %Flow7221; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s27222; GFX11-NEXT:    s_cbranch_vccnz .LBB57_37223; GFX11-NEXT:  .LBB57_2: ; %cmp.true7224; GFX11-NEXT:    s_add_i32 s1, s1, 37225; GFX11-NEXT:    s_add_i32 s0, s0, 37226; GFX11-NEXT:  .LBB57_3: ; %end7227; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)7228; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s17229; GFX11-NEXT:    s_setpc_b64 s[30:31]7230; GFX11-NEXT:  .LBB57_4:7231; GFX11-NEXT:    s_branch .LBB57_27232  %cmp = icmp eq i32 %b, 07233  br i1 %cmp, label %cmp.true, label %cmp.false7234 7235cmp.true:7236  %a1 = add <2 x i32> %a, splat (i32 3)7237  %a2 = bitcast <2 x i32> %a1 to <4 x i16>7238  br label %end7239 7240cmp.false:7241  %a3 = bitcast <2 x i32> %a to <4 x i16>7242  br label %end7243 7244end:7245  %phi = phi <4 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]7246  ret <4 x i16> %phi7247}7248 7249define <2 x i32> @bitcast_v4i16_to_v2i32(<4 x i16> %a, i32 %b) {7250; SI-LABEL: bitcast_v4i16_to_v2i32:7251; SI:       ; %bb.0:7252; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7253; SI-NEXT:    v_mov_b32_e32 v5, v07254; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v47255; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v17256; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v37257; SI-NEXT:    ; implicit-def: $vgpr0_vgpr17258; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc7259; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]7260; SI-NEXT:    s_cbranch_execnz .LBB58_37261; SI-NEXT:  ; %bb.1: ; %Flow7262; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]7263; SI-NEXT:    s_cbranch_execnz .LBB58_47264; SI-NEXT:  .LBB58_2: ; %end7265; SI-NEXT:    s_or_b64 exec, exec, s[4:5]7266; SI-NEXT:    s_setpc_b64 s[30:31]7267; SI-NEXT:  .LBB58_3: ; %cmp.false7268; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v57269; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v27270; SI-NEXT:    v_or_b32_e32 v0, v0, v47271; SI-NEXT:    v_or_b32_e32 v1, v1, v37272; SI-NEXT:    ; implicit-def: $vgpr57273; SI-NEXT:    ; implicit-def: $vgpr47274; SI-NEXT:    ; implicit-def: $vgpr27275; SI-NEXT:    ; implicit-def: $vgpr37276; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]7277; SI-NEXT:    s_cbranch_execz .LBB58_27278; SI-NEXT:  .LBB58_4: ; %cmp.true7279; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v57280; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v27281; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v07282; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v17283; SI-NEXT:    v_or_b32_e32 v0, v4, v07284; SI-NEXT:    v_or_b32_e32 v1, v3, v17285; SI-NEXT:    v_add_i32_e32 v0, vcc, 0x30000, v07286; SI-NEXT:    v_add_i32_e32 v1, vcc, 0x30000, v17287; SI-NEXT:    s_or_b64 exec, exec, s[4:5]7288; SI-NEXT:    s_setpc_b64 s[30:31]7289;7290; VI-LABEL: bitcast_v4i16_to_v2i32:7291; VI:       ; %bb.0:7292; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7293; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v27294; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc7295; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]7296; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]7297; VI-NEXT:  ; %bb.1: ; %cmp.true7298; VI-NEXT:    v_mov_b32_e32 v3, 37299; VI-NEXT:    v_add_u16_e32 v2, 3, v17300; VI-NEXT:    v_add_u16_sdwa v1, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD7301; VI-NEXT:    v_or_b32_e32 v1, v2, v17302; VI-NEXT:    v_add_u16_e32 v2, 3, v07303; VI-NEXT:    v_add_u16_sdwa v0, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD7304; VI-NEXT:    v_or_b32_e32 v0, v2, v07305; VI-NEXT:  ; %bb.2: ; %end7306; VI-NEXT:    s_or_b64 exec, exec, s[4:5]7307; VI-NEXT:    s_setpc_b64 s[30:31]7308;7309; GFX9-LABEL: bitcast_v4i16_to_v2i32:7310; GFX9:       ; %bb.0:7311; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7312; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v27313; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc7314; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]7315; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]7316; GFX9-NEXT:  ; %bb.1: ; %cmp.true7317; GFX9-NEXT:    v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]7318; GFX9-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]7319; GFX9-NEXT:  ; %bb.2: ; %end7320; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]7321; GFX9-NEXT:    s_setpc_b64 s[30:31]7322;7323; GFX11-LABEL: bitcast_v4i16_to_v2i32:7324; GFX11:       ; %bb.0:7325; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7326; GFX11-NEXT:    s_mov_b32 s0, exec_lo7327; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v27328; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s07329; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)7330; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s07331; GFX11-NEXT:  ; %bb.1: ; %cmp.true7332; GFX11-NEXT:    v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]7333; GFX11-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]7334; GFX11-NEXT:  ; %bb.2: ; %end7335; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s07336; GFX11-NEXT:    s_setpc_b64 s[30:31]7337  %cmp = icmp eq i32 %b, 07338  br i1 %cmp, label %cmp.true, label %cmp.false7339 7340cmp.true:7341  %a1 = add <4 x i16> %a, splat (i16 3)7342  %a2 = bitcast <4 x i16> %a1 to <2 x i32>7343  br label %end7344 7345cmp.false:7346  %a3 = bitcast <4 x i16> %a to <2 x i32>7347  br label %end7348 7349end:7350  %phi = phi <2 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]7351  ret <2 x i32> %phi7352}7353 7354define inreg <2 x i32> @bitcast_v4i16_to_v2i32_scalar(<4 x i16> inreg %a, i32 inreg %b) {7355; SI-LABEL: bitcast_v4i16_to_v2i32_scalar:7356; SI:       ; %bb.0:7357; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7358; SI-NEXT:    s_cmp_lg_u32 s20, 07359; SI-NEXT:    s_cbranch_scc0 .LBB59_47360; SI-NEXT:  ; %bb.1: ; %cmp.false7361; SI-NEXT:    s_and_b32 s4, s16, 0xffff7362; SI-NEXT:    s_lshl_b32 s5, s17, 167363; SI-NEXT:    s_or_b32 s4, s4, s57364; SI-NEXT:    s_and_b32 s5, s18, 0xffff7365; SI-NEXT:    s_lshl_b32 s6, s19, 167366; SI-NEXT:    s_or_b32 s5, s5, s67367; SI-NEXT:    s_cbranch_execnz .LBB59_37368; SI-NEXT:  .LBB59_2: ; %cmp.true7369; SI-NEXT:    s_add_i32 s16, s16, 37370; SI-NEXT:    s_and_b32 s4, s16, 0xffff7371; SI-NEXT:    s_lshl_b32 s5, s17, 167372; SI-NEXT:    s_add_i32 s18, s18, 37373; SI-NEXT:    s_or_b32 s4, s5, s47374; SI-NEXT:    s_and_b32 s5, s18, 0xffff7375; SI-NEXT:    s_lshl_b32 s6, s19, 167376; SI-NEXT:    s_or_b32 s5, s6, s57377; SI-NEXT:    s_add_i32 s4, s4, 0x300007378; SI-NEXT:    s_add_i32 s5, s5, 0x300007379; SI-NEXT:  .LBB59_3: ; %end7380; SI-NEXT:    v_mov_b32_e32 v0, s47381; SI-NEXT:    v_mov_b32_e32 v1, s57382; SI-NEXT:    s_setpc_b64 s[30:31]7383; SI-NEXT:  .LBB59_4:7384; SI-NEXT:    ; implicit-def: $sgpr4_sgpr57385; SI-NEXT:    s_branch .LBB59_27386;7387; VI-LABEL: bitcast_v4i16_to_v2i32_scalar:7388; VI:       ; %bb.0:7389; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7390; VI-NEXT:    s_cmp_lg_u32 s18, 07391; VI-NEXT:    s_cbranch_scc0 .LBB59_47392; VI-NEXT:  ; %bb.1: ; %cmp.false7393; VI-NEXT:    s_cbranch_execnz .LBB59_37394; VI-NEXT:  .LBB59_2: ; %cmp.true7395; VI-NEXT:    s_add_i32 s5, s17, 37396; VI-NEXT:    s_and_b32 s4, s17, 0xffff00007397; VI-NEXT:    s_and_b32 s5, s5, 0xffff7398; VI-NEXT:    s_or_b32 s4, s4, s57399; VI-NEXT:    s_add_i32 s5, s16, 37400; VI-NEXT:    s_add_i32 s17, s4, 0x300007401; VI-NEXT:    s_and_b32 s4, s16, 0xffff00007402; VI-NEXT:    s_and_b32 s5, s5, 0xffff7403; VI-NEXT:    s_or_b32 s4, s4, s57404; VI-NEXT:    s_add_i32 s16, s4, 0x300007405; VI-NEXT:  .LBB59_3: ; %end7406; VI-NEXT:    v_mov_b32_e32 v0, s167407; VI-NEXT:    v_mov_b32_e32 v1, s177408; VI-NEXT:    s_setpc_b64 s[30:31]7409; VI-NEXT:  .LBB59_4:7410; VI-NEXT:    s_branch .LBB59_27411;7412; GFX9-LABEL: bitcast_v4i16_to_v2i32_scalar:7413; GFX9:       ; %bb.0:7414; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7415; GFX9-NEXT:    s_cmp_lg_u32 s18, 07416; GFX9-NEXT:    s_cbranch_scc0 .LBB59_37417; GFX9-NEXT:  ; %bb.1: ; %cmp.false7418; GFX9-NEXT:    s_cbranch_execnz .LBB59_47419; GFX9-NEXT:  .LBB59_2: ; %cmp.true7420; GFX9-NEXT:    v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]7421; GFX9-NEXT:    v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]7422; GFX9-NEXT:    s_setpc_b64 s[30:31]7423; GFX9-NEXT:  .LBB59_3:7424; GFX9-NEXT:    s_branch .LBB59_27425; GFX9-NEXT:  .LBB59_4:7426; GFX9-NEXT:    v_mov_b32_e32 v0, s167427; GFX9-NEXT:    v_mov_b32_e32 v1, s177428; GFX9-NEXT:    s_setpc_b64 s[30:31]7429;7430; GFX11-LABEL: bitcast_v4i16_to_v2i32_scalar:7431; GFX11:       ; %bb.0:7432; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7433; GFX11-NEXT:    s_cmp_lg_u32 s2, 07434; GFX11-NEXT:    s_mov_b32 s2, 07435; GFX11-NEXT:    s_cbranch_scc0 .LBB59_37436; GFX11-NEXT:  ; %bb.1: ; %Flow7437; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s27438; GFX11-NEXT:    s_cbranch_vccnz .LBB59_47439; GFX11-NEXT:  .LBB59_2: ; %cmp.true7440; GFX11-NEXT:    v_pk_add_u16 v1, s1, 3 op_sel_hi:[1,0]7441; GFX11-NEXT:    v_pk_add_u16 v0, s0, 3 op_sel_hi:[1,0]7442; GFX11-NEXT:    s_setpc_b64 s[30:31]7443; GFX11-NEXT:  .LBB59_3:7444; GFX11-NEXT:    s_branch .LBB59_27445; GFX11-NEXT:  .LBB59_4:7446; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s17447; GFX11-NEXT:    s_setpc_b64 s[30:31]7448  %cmp = icmp eq i32 %b, 07449  br i1 %cmp, label %cmp.true, label %cmp.false7450 7451cmp.true:7452  %a1 = add <4 x i16> %a, splat (i16 3)7453  %a2 = bitcast <4 x i16> %a1 to <2 x i32>7454  br label %end7455 7456cmp.false:7457  %a3 = bitcast <4 x i16> %a to <2 x i32>7458  br label %end7459 7460end:7461  %phi = phi <2 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]7462  ret <2 x i32> %phi7463}7464 7465define <4 x half> @bitcast_v2i32_to_v4f16(<2 x i32> %a, i32 %b) {7466; SI-LABEL: bitcast_v2i32_to_v4f16:7467; SI:       ; %bb.0:7468; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7469; SI-NEXT:    v_mov_b32_e32 v4, v17470; SI-NEXT:    v_mov_b32_e32 v5, v07471; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v27472; SI-NEXT:    ; implicit-def: $vgpr07473; SI-NEXT:    ; implicit-def: $vgpr17474; SI-NEXT:    ; implicit-def: $vgpr27475; SI-NEXT:    ; implicit-def: $vgpr37476; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc7477; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]7478; SI-NEXT:    s_cbranch_execnz .LBB60_37479; SI-NEXT:  ; %bb.1: ; %Flow7480; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]7481; SI-NEXT:    s_cbranch_execnz .LBB60_47482; SI-NEXT:  .LBB60_2: ; %end7483; SI-NEXT:    s_or_b64 exec, exec, s[4:5]7484; SI-NEXT:    s_setpc_b64 s[30:31]7485; SI-NEXT:  .LBB60_3: ; %cmp.false7486; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v47487; SI-NEXT:    v_cvt_f32_f16_e32 v3, v07488; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v57489; SI-NEXT:    v_cvt_f32_f16_e32 v1, v07490; SI-NEXT:    v_cvt_f32_f16_e32 v2, v47491; SI-NEXT:    v_cvt_f32_f16_e32 v0, v57492; SI-NEXT:    ; implicit-def: $vgpr57493; SI-NEXT:    ; implicit-def: $vgpr47494; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]7495; SI-NEXT:    s_cbranch_execz .LBB60_27496; SI-NEXT:  .LBB60_4: ; %cmp.true7497; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v57498; SI-NEXT:    v_add_i32_e32 v2, vcc, 3, v47499; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v07500; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v27501; SI-NEXT:    v_cvt_f32_f16_e32 v2, v27502; SI-NEXT:    v_cvt_f32_f16_e32 v0, v07503; SI-NEXT:    v_cvt_f32_f16_e32 v3, v37504; SI-NEXT:    v_cvt_f32_f16_e32 v1, v17505; SI-NEXT:    s_or_b64 exec, exec, s[4:5]7506; SI-NEXT:    s_setpc_b64 s[30:31]7507;7508; VI-LABEL: bitcast_v2i32_to_v4f16:7509; VI:       ; %bb.0:7510; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7511; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v27512; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc7513; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]7514; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]7515; VI-NEXT:  ; %bb.1: ; %cmp.true7516; VI-NEXT:    v_add_u32_e32 v1, vcc, 3, v17517; VI-NEXT:    v_add_u32_e32 v0, vcc, 3, v07518; VI-NEXT:  ; %bb.2: ; %end7519; VI-NEXT:    s_or_b64 exec, exec, s[4:5]7520; VI-NEXT:    s_setpc_b64 s[30:31]7521;7522; GFX9-LABEL: bitcast_v2i32_to_v4f16:7523; GFX9:       ; %bb.0:7524; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7525; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v27526; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc7527; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]7528; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]7529; GFX9-NEXT:  ; %bb.1: ; %cmp.true7530; GFX9-NEXT:    v_add_u32_e32 v1, 3, v17531; GFX9-NEXT:    v_add_u32_e32 v0, 3, v07532; GFX9-NEXT:  ; %bb.2: ; %end7533; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]7534; GFX9-NEXT:    s_setpc_b64 s[30:31]7535;7536; GFX11-LABEL: bitcast_v2i32_to_v4f16:7537; GFX11:       ; %bb.0:7538; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7539; GFX11-NEXT:    s_mov_b32 s0, exec_lo7540; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v27541; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s07542; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)7543; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s07544; GFX11-NEXT:  ; %bb.1: ; %cmp.true7545; GFX11-NEXT:    v_add_nc_u32_e32 v1, 3, v17546; GFX11-NEXT:    v_add_nc_u32_e32 v0, 3, v07547; GFX11-NEXT:  ; %bb.2: ; %end7548; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s07549; GFX11-NEXT:    s_setpc_b64 s[30:31]7550  %cmp = icmp eq i32 %b, 07551  br i1 %cmp, label %cmp.true, label %cmp.false7552 7553cmp.true:7554  %a1 = add <2 x i32> %a, splat (i32 3)7555  %a2 = bitcast <2 x i32> %a1 to <4 x half>7556  br label %end7557 7558cmp.false:7559  %a3 = bitcast <2 x i32> %a to <4 x half>7560  br label %end7561 7562end:7563  %phi = phi <4 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]7564  ret <4 x half> %phi7565}7566 7567define inreg <4 x half> @bitcast_v2i32_to_v4f16_scalar(<2 x i32> inreg %a, i32 inreg %b) {7568; SI-LABEL: bitcast_v2i32_to_v4f16_scalar:7569; SI:       ; %bb.0:7570; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7571; SI-NEXT:    s_cmp_lg_u32 s18, 07572; SI-NEXT:    s_cbranch_scc0 .LBB61_47573; SI-NEXT:  ; %bb.1: ; %cmp.false7574; SI-NEXT:    s_lshr_b32 s4, s17, 167575; SI-NEXT:    v_cvt_f32_f16_e32 v3, s47576; SI-NEXT:    s_lshr_b32 s4, s16, 167577; SI-NEXT:    v_cvt_f32_f16_e32 v1, s47578; SI-NEXT:    v_cvt_f32_f16_e32 v2, s177579; SI-NEXT:    v_cvt_f32_f16_e32 v0, s167580; SI-NEXT:    s_cbranch_execnz .LBB61_37581; SI-NEXT:  .LBB61_2: ; %cmp.true7582; SI-NEXT:    s_add_i32 s4, s16, 37583; SI-NEXT:    s_add_i32 s6, s17, 37584; SI-NEXT:    s_lshr_b32 s5, s4, 167585; SI-NEXT:    s_lshr_b32 s7, s6, 167586; SI-NEXT:    v_cvt_f32_f16_e32 v2, s67587; SI-NEXT:    v_cvt_f32_f16_e32 v0, s47588; SI-NEXT:    v_cvt_f32_f16_e32 v3, s77589; SI-NEXT:    v_cvt_f32_f16_e32 v1, s57590; SI-NEXT:  .LBB61_3: ; %end7591; SI-NEXT:    s_setpc_b64 s[30:31]7592; SI-NEXT:  .LBB61_4:7593; SI-NEXT:    ; implicit-def: $vgpr07594; SI-NEXT:    ; implicit-def: $vgpr17595; SI-NEXT:    ; implicit-def: $vgpr27596; SI-NEXT:    ; implicit-def: $vgpr37597; SI-NEXT:    s_branch .LBB61_27598;7599; VI-LABEL: bitcast_v2i32_to_v4f16_scalar:7600; VI:       ; %bb.0:7601; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7602; VI-NEXT:    s_cmp_lg_u32 s18, 07603; VI-NEXT:    s_cbranch_scc0 .LBB61_47604; VI-NEXT:  ; %bb.1: ; %cmp.false7605; VI-NEXT:    s_cbranch_execnz .LBB61_37606; VI-NEXT:  .LBB61_2: ; %cmp.true7607; VI-NEXT:    s_add_i32 s17, s17, 37608; VI-NEXT:    s_add_i32 s16, s16, 37609; VI-NEXT:  .LBB61_3: ; %end7610; VI-NEXT:    v_mov_b32_e32 v0, s167611; VI-NEXT:    v_mov_b32_e32 v1, s177612; VI-NEXT:    s_setpc_b64 s[30:31]7613; VI-NEXT:  .LBB61_4:7614; VI-NEXT:    s_branch .LBB61_27615;7616; GFX9-LABEL: bitcast_v2i32_to_v4f16_scalar:7617; GFX9:       ; %bb.0:7618; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7619; GFX9-NEXT:    s_cmp_lg_u32 s18, 07620; GFX9-NEXT:    s_cbranch_scc0 .LBB61_47621; GFX9-NEXT:  ; %bb.1: ; %cmp.false7622; GFX9-NEXT:    s_cbranch_execnz .LBB61_37623; GFX9-NEXT:  .LBB61_2: ; %cmp.true7624; GFX9-NEXT:    s_add_i32 s17, s17, 37625; GFX9-NEXT:    s_add_i32 s16, s16, 37626; GFX9-NEXT:  .LBB61_3: ; %end7627; GFX9-NEXT:    v_mov_b32_e32 v0, s167628; GFX9-NEXT:    v_mov_b32_e32 v1, s177629; GFX9-NEXT:    s_setpc_b64 s[30:31]7630; GFX9-NEXT:  .LBB61_4:7631; GFX9-NEXT:    s_branch .LBB61_27632;7633; GFX11-LABEL: bitcast_v2i32_to_v4f16_scalar:7634; GFX11:       ; %bb.0:7635; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7636; GFX11-NEXT:    s_cmp_lg_u32 s2, 07637; GFX11-NEXT:    s_mov_b32 s2, 07638; GFX11-NEXT:    s_cbranch_scc0 .LBB61_47639; GFX11-NEXT:  ; %bb.1: ; %Flow7640; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s27641; GFX11-NEXT:    s_cbranch_vccnz .LBB61_37642; GFX11-NEXT:  .LBB61_2: ; %cmp.true7643; GFX11-NEXT:    s_add_i32 s1, s1, 37644; GFX11-NEXT:    s_add_i32 s0, s0, 37645; GFX11-NEXT:  .LBB61_3: ; %end7646; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)7647; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s17648; GFX11-NEXT:    s_setpc_b64 s[30:31]7649; GFX11-NEXT:  .LBB61_4:7650; GFX11-NEXT:    s_branch .LBB61_27651  %cmp = icmp eq i32 %b, 07652  br i1 %cmp, label %cmp.true, label %cmp.false7653 7654cmp.true:7655  %a1 = add <2 x i32> %a, splat (i32 3)7656  %a2 = bitcast <2 x i32> %a1 to <4 x half>7657  br label %end7658 7659cmp.false:7660  %a3 = bitcast <2 x i32> %a to <4 x half>7661  br label %end7662 7663end:7664  %phi = phi <4 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]7665  ret <4 x half> %phi7666}7667 7668define <2 x i32> @bitcast_v4f16_to_v2i32(<4 x half> %a, i32 %b) {7669; SI-LABEL: bitcast_v4f16_to_v2i32:7670; SI:       ; %bb.0:7671; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7672; SI-NEXT:    v_cvt_f16_f32_e32 v6, v17673; SI-NEXT:    v_cvt_f16_f32_e32 v5, v07674; SI-NEXT:    v_cvt_f16_f32_e32 v3, v37675; SI-NEXT:    v_cvt_f16_f32_e32 v2, v27676; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v47677; SI-NEXT:    ; implicit-def: $vgpr0_vgpr17678; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc7679; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]7680; SI-NEXT:    s_cbranch_execnz .LBB62_37681; SI-NEXT:  ; %bb.1: ; %Flow7682; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]7683; SI-NEXT:    s_cbranch_execnz .LBB62_47684; SI-NEXT:  .LBB62_2: ; %end7685; SI-NEXT:    s_or_b64 exec, exec, s[4:5]7686; SI-NEXT:    s_setpc_b64 s[30:31]7687; SI-NEXT:  .LBB62_3: ; %cmp.false7688; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v67689; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v37690; SI-NEXT:    v_or_b32_e32 v0, v5, v07691; SI-NEXT:    v_or_b32_e32 v1, v2, v17692; SI-NEXT:    ; implicit-def: $vgpr67693; SI-NEXT:    ; implicit-def: $vgpr57694; SI-NEXT:    ; implicit-def: $vgpr37695; SI-NEXT:    ; implicit-def: $vgpr27696; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]7697; SI-NEXT:    s_cbranch_execz .LBB62_27698; SI-NEXT:  .LBB62_4: ; %cmp.true7699; SI-NEXT:    v_cvt_f32_f16_e32 v0, v67700; SI-NEXT:    v_cvt_f32_f16_e32 v1, v57701; SI-NEXT:    v_cvt_f32_f16_e32 v3, v37702; SI-NEXT:    v_cvt_f32_f16_e32 v2, v27703; SI-NEXT:    v_add_f32_e32 v0, 0x38000000, v07704; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v17705; SI-NEXT:    v_cvt_f16_f32_e32 v0, v07706; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v37707; SI-NEXT:    v_cvt_f16_f32_e32 v1, v17708; SI-NEXT:    v_cvt_f16_f32_e32 v3, v37709; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v27710; SI-NEXT:    v_cvt_f16_f32_e32 v2, v27711; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v07712; SI-NEXT:    v_or_b32_e32 v0, v1, v07713; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v37714; SI-NEXT:    v_or_b32_e32 v1, v2, v17715; SI-NEXT:    s_or_b64 exec, exec, s[4:5]7716; SI-NEXT:    s_setpc_b64 s[30:31]7717;7718; VI-LABEL: bitcast_v4f16_to_v2i32:7719; VI:       ; %bb.0:7720; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7721; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v27722; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc7723; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]7724; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]7725; VI-NEXT:  ; %bb.1: ; %cmp.true7726; VI-NEXT:    v_mov_b32_e32 v2, 0x2007727; VI-NEXT:    v_add_f16_sdwa v3, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD7728; VI-NEXT:    v_add_f16_e32 v1, 0x200, v17729; VI-NEXT:    v_add_f16_sdwa v2, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD7730; VI-NEXT:    v_add_f16_e32 v0, 0x200, v07731; VI-NEXT:    v_or_b32_e32 v1, v1, v37732; VI-NEXT:    v_or_b32_e32 v0, v0, v27733; VI-NEXT:  ; %bb.2: ; %end7734; VI-NEXT:    s_or_b64 exec, exec, s[4:5]7735; VI-NEXT:    s_setpc_b64 s[30:31]7736;7737; GFX9-LABEL: bitcast_v4f16_to_v2i32:7738; GFX9:       ; %bb.0:7739; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7740; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v27741; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc7742; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]7743; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]7744; GFX9-NEXT:  ; %bb.1: ; %cmp.true7745; GFX9-NEXT:    s_movk_i32 s6, 0x2007746; GFX9-NEXT:    v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]7747; GFX9-NEXT:    v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]7748; GFX9-NEXT:  ; %bb.2: ; %end7749; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]7750; GFX9-NEXT:    s_setpc_b64 s[30:31]7751;7752; GFX11-LABEL: bitcast_v4f16_to_v2i32:7753; GFX11:       ; %bb.0:7754; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7755; GFX11-NEXT:    s_mov_b32 s0, exec_lo7756; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v27757; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s07758; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)7759; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s07760; GFX11-NEXT:  ; %bb.1: ; %cmp.true7761; GFX11-NEXT:    v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]7762; GFX11-NEXT:    v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]7763; GFX11-NEXT:  ; %bb.2: ; %end7764; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s07765; GFX11-NEXT:    s_setpc_b64 s[30:31]7766  %cmp = icmp eq i32 %b, 07767  br i1 %cmp, label %cmp.true, label %cmp.false7768 7769cmp.true:7770  %a1 = fadd <4 x half> %a, splat (half 0xH0200)7771  %a2 = bitcast <4 x half> %a1 to <2 x i32>7772  br label %end7773 7774cmp.false:7775  %a3 = bitcast <4 x half> %a to <2 x i32>7776  br label %end7777 7778end:7779  %phi = phi <2 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]7780  ret <2 x i32> %phi7781}7782 7783define inreg <2 x i32> @bitcast_v4f16_to_v2i32_scalar(<4 x half> inreg %a, i32 inreg %b) {7784; SI-LABEL: bitcast_v4f16_to_v2i32_scalar:7785; SI:       ; %bb.0:7786; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7787; SI-NEXT:    v_cvt_f16_f32_e32 v5, s177788; SI-NEXT:    v_cvt_f16_f32_e32 v4, s167789; SI-NEXT:    v_cvt_f16_f32_e32 v3, s197790; SI-NEXT:    v_cvt_f16_f32_e32 v2, s187791; SI-NEXT:    s_cmp_lg_u32 s20, 07792; SI-NEXT:    s_cbranch_scc0 .LBB63_47793; SI-NEXT:  ; %bb.1: ; %cmp.false7794; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v57795; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v37796; SI-NEXT:    v_or_b32_e32 v0, v4, v07797; SI-NEXT:    v_or_b32_e32 v1, v2, v17798; SI-NEXT:    s_cbranch_execnz .LBB63_37799; SI-NEXT:  .LBB63_2: ; %cmp.true7800; SI-NEXT:    v_cvt_f32_f16_e32 v0, v57801; SI-NEXT:    v_cvt_f32_f16_e32 v1, v47802; SI-NEXT:    v_cvt_f32_f16_e32 v3, v37803; SI-NEXT:    v_cvt_f32_f16_e32 v2, v27804; SI-NEXT:    v_add_f32_e32 v0, 0x38000000, v07805; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v17806; SI-NEXT:    v_cvt_f16_f32_e32 v0, v07807; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v37808; SI-NEXT:    v_cvt_f16_f32_e32 v1, v17809; SI-NEXT:    v_cvt_f16_f32_e32 v3, v37810; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v27811; SI-NEXT:    v_cvt_f16_f32_e32 v2, v27812; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v07813; SI-NEXT:    v_or_b32_e32 v0, v1, v07814; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v37815; SI-NEXT:    v_or_b32_e32 v1, v2, v17816; SI-NEXT:  .LBB63_3: ; %end7817; SI-NEXT:    s_setpc_b64 s[30:31]7818; SI-NEXT:  .LBB63_4:7819; SI-NEXT:    ; implicit-def: $vgpr0_vgpr17820; SI-NEXT:    s_branch .LBB63_27821;7822; VI-LABEL: bitcast_v4f16_to_v2i32_scalar:7823; VI:       ; %bb.0:7824; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7825; VI-NEXT:    s_cmp_lg_u32 s18, 07826; VI-NEXT:    s_cbranch_scc0 .LBB63_37827; VI-NEXT:  ; %bb.1: ; %cmp.false7828; VI-NEXT:    s_cbranch_execnz .LBB63_47829; VI-NEXT:  .LBB63_2: ; %cmp.true7830; VI-NEXT:    s_lshr_b32 s4, s17, 167831; VI-NEXT:    v_mov_b32_e32 v0, 0x2007832; VI-NEXT:    v_mov_b32_e32 v1, s47833; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD7834; VI-NEXT:    v_add_f16_e32 v2, s17, v07835; VI-NEXT:    s_lshr_b32 s4, s16, 167836; VI-NEXT:    v_or_b32_e32 v1, v2, v17837; VI-NEXT:    v_mov_b32_e32 v2, s47838; VI-NEXT:    v_add_f16_sdwa v2, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD7839; VI-NEXT:    v_add_f16_e32 v0, s16, v07840; VI-NEXT:    v_or_b32_e32 v0, v0, v27841; VI-NEXT:    s_setpc_b64 s[30:31]7842; VI-NEXT:  .LBB63_3:7843; VI-NEXT:    s_branch .LBB63_27844; VI-NEXT:  .LBB63_4:7845; VI-NEXT:    v_mov_b32_e32 v0, s167846; VI-NEXT:    v_mov_b32_e32 v1, s177847; VI-NEXT:    s_setpc_b64 s[30:31]7848;7849; GFX9-LABEL: bitcast_v4f16_to_v2i32_scalar:7850; GFX9:       ; %bb.0:7851; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7852; GFX9-NEXT:    s_cmp_lg_u32 s18, 07853; GFX9-NEXT:    s_cbranch_scc0 .LBB63_37854; GFX9-NEXT:  ; %bb.1: ; %cmp.false7855; GFX9-NEXT:    s_cbranch_execnz .LBB63_47856; GFX9-NEXT:  .LBB63_2: ; %cmp.true7857; GFX9-NEXT:    v_mov_b32_e32 v0, 0x2007858; GFX9-NEXT:    v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]7859; GFX9-NEXT:    v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]7860; GFX9-NEXT:    s_setpc_b64 s[30:31]7861; GFX9-NEXT:  .LBB63_3:7862; GFX9-NEXT:    s_branch .LBB63_27863; GFX9-NEXT:  .LBB63_4:7864; GFX9-NEXT:    v_mov_b32_e32 v0, s167865; GFX9-NEXT:    v_mov_b32_e32 v1, s177866; GFX9-NEXT:    s_setpc_b64 s[30:31]7867;7868; GFX11-LABEL: bitcast_v4f16_to_v2i32_scalar:7869; GFX11:       ; %bb.0:7870; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7871; GFX11-NEXT:    s_cmp_lg_u32 s2, 07872; GFX11-NEXT:    s_mov_b32 s2, 07873; GFX11-NEXT:    s_cbranch_scc0 .LBB63_37874; GFX11-NEXT:  ; %bb.1: ; %Flow7875; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s27876; GFX11-NEXT:    s_cbranch_vccnz .LBB63_47877; GFX11-NEXT:  .LBB63_2: ; %cmp.true7878; GFX11-NEXT:    v_pk_add_f16 v1, 0x200, s1 op_sel_hi:[0,1]7879; GFX11-NEXT:    v_pk_add_f16 v0, 0x200, s0 op_sel_hi:[0,1]7880; GFX11-NEXT:    s_setpc_b64 s[30:31]7881; GFX11-NEXT:  .LBB63_3:7882; GFX11-NEXT:    s_branch .LBB63_27883; GFX11-NEXT:  .LBB63_4:7884; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s17885; GFX11-NEXT:    s_setpc_b64 s[30:31]7886  %cmp = icmp eq i32 %b, 07887  br i1 %cmp, label %cmp.true, label %cmp.false7888 7889cmp.true:7890  %a1 = fadd <4 x half> %a, splat (half 0xH0200)7891  %a2 = bitcast <4 x half> %a1 to <2 x i32>7892  br label %end7893 7894cmp.false:7895  %a3 = bitcast <4 x half> %a to <2 x i32>7896  br label %end7897 7898end:7899  %phi = phi <2 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]7900  ret <2 x i32> %phi7901}7902 7903define <4 x bfloat> @bitcast_v2i32_to_v4bf16(<2 x i32> %a, i32 %b) {7904; SI-LABEL: bitcast_v2i32_to_v4bf16:7905; SI:       ; %bb.0:7906; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7907; SI-NEXT:    v_mov_b32_e32 v5, v17908; SI-NEXT:    v_mov_b32_e32 v4, v07909; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v27910; SI-NEXT:    ; implicit-def: $vgpr07911; SI-NEXT:    ; implicit-def: $vgpr17912; SI-NEXT:    ; implicit-def: $vgpr27913; SI-NEXT:    ; implicit-def: $vgpr37914; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc7915; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]7916; SI-NEXT:    s_cbranch_execnz .LBB64_37917; SI-NEXT:  ; %bb.1: ; %Flow7918; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]7919; SI-NEXT:    s_cbranch_execnz .LBB64_47920; SI-NEXT:  .LBB64_2: ; %end7921; SI-NEXT:    s_or_b64 exec, exec, s[4:5]7922; SI-NEXT:    s_setpc_b64 s[30:31]7923; SI-NEXT:  .LBB64_3: ; %cmp.false7924; SI-NEXT:    v_and_b32_e32 v3, 0xffff0000, v57925; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v57926; SI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v47927; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v47928; SI-NEXT:    ; implicit-def: $vgpr47929; SI-NEXT:    ; implicit-def: $vgpr57930; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]7931; SI-NEXT:    s_cbranch_execz .LBB64_27932; SI-NEXT:  .LBB64_4: ; %cmp.true7933; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v47934; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v57935; SI-NEXT:    v_and_b32_e32 v3, 0xffff0000, v17936; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v17937; SI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v07938; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v07939; SI-NEXT:    s_or_b64 exec, exec, s[4:5]7940; SI-NEXT:    s_setpc_b64 s[30:31]7941;7942; VI-LABEL: bitcast_v2i32_to_v4bf16:7943; VI:       ; %bb.0:7944; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7945; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v27946; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc7947; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]7948; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]7949; VI-NEXT:  ; %bb.1: ; %cmp.true7950; VI-NEXT:    v_add_u32_e32 v1, vcc, 3, v17951; VI-NEXT:    v_add_u32_e32 v0, vcc, 3, v07952; VI-NEXT:  ; %bb.2: ; %end7953; VI-NEXT:    s_or_b64 exec, exec, s[4:5]7954; VI-NEXT:    s_setpc_b64 s[30:31]7955;7956; GFX9-LABEL: bitcast_v2i32_to_v4bf16:7957; GFX9:       ; %bb.0:7958; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7959; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v27960; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc7961; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]7962; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]7963; GFX9-NEXT:  ; %bb.1: ; %cmp.true7964; GFX9-NEXT:    v_add_u32_e32 v1, 3, v17965; GFX9-NEXT:    v_add_u32_e32 v0, 3, v07966; GFX9-NEXT:  ; %bb.2: ; %end7967; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]7968; GFX9-NEXT:    s_setpc_b64 s[30:31]7969;7970; GFX11-LABEL: bitcast_v2i32_to_v4bf16:7971; GFX11:       ; %bb.0:7972; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7973; GFX11-NEXT:    s_mov_b32 s0, exec_lo7974; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v27975; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s07976; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)7977; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s07978; GFX11-NEXT:  ; %bb.1: ; %cmp.true7979; GFX11-NEXT:    v_add_nc_u32_e32 v1, 3, v17980; GFX11-NEXT:    v_add_nc_u32_e32 v0, 3, v07981; GFX11-NEXT:  ; %bb.2: ; %end7982; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s07983; GFX11-NEXT:    s_setpc_b64 s[30:31]7984  %cmp = icmp eq i32 %b, 07985  br i1 %cmp, label %cmp.true, label %cmp.false7986 7987cmp.true:7988  %a1 = add <2 x i32> %a, splat (i32 3)7989  %a2 = bitcast <2 x i32> %a1 to <4 x bfloat>7990  br label %end7991 7992cmp.false:7993  %a3 = bitcast <2 x i32> %a to <4 x bfloat>7994  br label %end7995 7996end:7997  %phi = phi <4 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ]7998  ret <4 x bfloat> %phi7999}8000 8001define inreg <4 x bfloat> @bitcast_v2i32_to_v4bf16_scalar(<2 x i32> inreg %a, i32 inreg %b) {8002; SI-LABEL: bitcast_v2i32_to_v4bf16_scalar:8003; SI:       ; %bb.0:8004; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8005; SI-NEXT:    s_cmp_lg_u32 s18, 08006; SI-NEXT:    s_cbranch_scc0 .LBB65_48007; SI-NEXT:  ; %bb.1: ; %cmp.false8008; SI-NEXT:    s_and_b32 s6, s17, 0xffff00008009; SI-NEXT:    s_lshl_b32 s7, s17, 168010; SI-NEXT:    s_and_b32 s8, s16, 0xffff00008011; SI-NEXT:    s_lshl_b32 s9, s16, 168012; SI-NEXT:    s_cbranch_execnz .LBB65_38013; SI-NEXT:  .LBB65_2: ; %cmp.true8014; SI-NEXT:    s_add_i32 s4, s16, 38015; SI-NEXT:    s_add_i32 s5, s17, 38016; SI-NEXT:    s_and_b32 s6, s5, 0xffff00008017; SI-NEXT:    s_lshl_b32 s7, s5, 168018; SI-NEXT:    s_and_b32 s8, s4, 0xffff00008019; SI-NEXT:    s_lshl_b32 s9, s4, 168020; SI-NEXT:  .LBB65_3: ; %end8021; SI-NEXT:    v_mov_b32_e32 v0, s98022; SI-NEXT:    v_mov_b32_e32 v1, s88023; SI-NEXT:    v_mov_b32_e32 v2, s78024; SI-NEXT:    v_mov_b32_e32 v3, s68025; SI-NEXT:    s_setpc_b64 s[30:31]8026; SI-NEXT:  .LBB65_4:8027; SI-NEXT:    ; implicit-def: $sgpr98028; SI-NEXT:    ; implicit-def: $sgpr88029; SI-NEXT:    ; implicit-def: $sgpr78030; SI-NEXT:    ; implicit-def: $sgpr68031; SI-NEXT:    s_branch .LBB65_28032;8033; VI-LABEL: bitcast_v2i32_to_v4bf16_scalar:8034; VI:       ; %bb.0:8035; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8036; VI-NEXT:    s_cmp_lg_u32 s18, 08037; VI-NEXT:    s_cbranch_scc0 .LBB65_48038; VI-NEXT:  ; %bb.1: ; %cmp.false8039; VI-NEXT:    s_cbranch_execnz .LBB65_38040; VI-NEXT:  .LBB65_2: ; %cmp.true8041; VI-NEXT:    s_add_i32 s17, s17, 38042; VI-NEXT:    s_add_i32 s16, s16, 38043; VI-NEXT:  .LBB65_3: ; %end8044; VI-NEXT:    v_mov_b32_e32 v0, s168045; VI-NEXT:    v_mov_b32_e32 v1, s178046; VI-NEXT:    s_setpc_b64 s[30:31]8047; VI-NEXT:  .LBB65_4:8048; VI-NEXT:    s_branch .LBB65_28049;8050; GFX9-LABEL: bitcast_v2i32_to_v4bf16_scalar:8051; GFX9:       ; %bb.0:8052; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8053; GFX9-NEXT:    s_cmp_lg_u32 s18, 08054; GFX9-NEXT:    s_cbranch_scc0 .LBB65_48055; GFX9-NEXT:  ; %bb.1: ; %cmp.false8056; GFX9-NEXT:    s_cbranch_execnz .LBB65_38057; GFX9-NEXT:  .LBB65_2: ; %cmp.true8058; GFX9-NEXT:    s_add_i32 s17, s17, 38059; GFX9-NEXT:    s_add_i32 s16, s16, 38060; GFX9-NEXT:  .LBB65_3: ; %end8061; GFX9-NEXT:    v_mov_b32_e32 v0, s168062; GFX9-NEXT:    v_mov_b32_e32 v1, s178063; GFX9-NEXT:    s_setpc_b64 s[30:31]8064; GFX9-NEXT:  .LBB65_4:8065; GFX9-NEXT:    s_branch .LBB65_28066;8067; GFX11-LABEL: bitcast_v2i32_to_v4bf16_scalar:8068; GFX11:       ; %bb.0:8069; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8070; GFX11-NEXT:    s_cmp_lg_u32 s2, 08071; GFX11-NEXT:    s_mov_b32 s2, 08072; GFX11-NEXT:    s_cbranch_scc0 .LBB65_48073; GFX11-NEXT:  ; %bb.1: ; %Flow8074; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s28075; GFX11-NEXT:    s_cbranch_vccnz .LBB65_38076; GFX11-NEXT:  .LBB65_2: ; %cmp.true8077; GFX11-NEXT:    s_add_i32 s1, s1, 38078; GFX11-NEXT:    s_add_i32 s0, s0, 38079; GFX11-NEXT:  .LBB65_3: ; %end8080; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)8081; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s18082; GFX11-NEXT:    s_setpc_b64 s[30:31]8083; GFX11-NEXT:  .LBB65_4:8084; GFX11-NEXT:    s_branch .LBB65_28085  %cmp = icmp eq i32 %b, 08086  br i1 %cmp, label %cmp.true, label %cmp.false8087 8088cmp.true:8089  %a1 = add <2 x i32> %a, splat (i32 3)8090  %a2 = bitcast <2 x i32> %a1 to <4 x bfloat>8091  br label %end8092 8093cmp.false:8094  %a3 = bitcast <2 x i32> %a to <4 x bfloat>8095  br label %end8096 8097end:8098  %phi = phi <4 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ]8099  ret <4 x bfloat> %phi8100}8101 8102define <2 x i32> @bitcast_v4bf16_to_v2i32(<4 x bfloat> %a, i32 %b) {8103; SI-LABEL: bitcast_v4bf16_to_v2i32:8104; SI:       ; %bb.0:8105; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8106; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v48107; SI-NEXT:    v_mul_f32_e32 v4, 1.0, v18108; SI-NEXT:    v_mul_f32_e32 v5, 1.0, v08109; SI-NEXT:    v_mul_f32_e32 v3, 1.0, v38110; SI-NEXT:    v_mul_f32_e32 v2, 1.0, v28111; SI-NEXT:    ; implicit-def: $vgpr0_vgpr18112; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc8113; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]8114; SI-NEXT:    s_cbranch_execnz .LBB66_38115; SI-NEXT:  ; %bb.1: ; %Flow8116; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]8117; SI-NEXT:    s_cbranch_execnz .LBB66_48118; SI-NEXT:  .LBB66_2: ; %end8119; SI-NEXT:    s_or_b64 exec, exec, s[4:5]8120; SI-NEXT:    s_setpc_b64 s[30:31]8121; SI-NEXT:  .LBB66_3: ; %cmp.false8122; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v48123; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v38124; SI-NEXT:    v_alignbit_b32 v0, v0, v5, 168125; SI-NEXT:    v_alignbit_b32 v1, v1, v2, 168126; SI-NEXT:    ; implicit-def: $vgpr58127; SI-NEXT:    ; implicit-def: $vgpr48128; SI-NEXT:    ; implicit-def: $vgpr28129; SI-NEXT:    ; implicit-def: $vgpr38130; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]8131; SI-NEXT:    s_cbranch_execz .LBB66_28132; SI-NEXT:  .LBB66_4: ; %cmp.true8133; SI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v48134; SI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v58135; SI-NEXT:    v_add_f32_e32 v1, 0x40c00000, v18136; SI-NEXT:    v_add_f32_e32 v0, 0x40c00000, v08137; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v18138; SI-NEXT:    v_alignbit_b32 v0, v1, v0, 168139; SI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v28140; SI-NEXT:    v_and_b32_e32 v2, 0xffff0000, v38141; SI-NEXT:    v_add_f32_e32 v2, 0x40c00000, v28142; SI-NEXT:    v_add_f32_e32 v1, 0x40c00000, v18143; SI-NEXT:    v_lshrrev_b32_e32 v2, 16, v28144; SI-NEXT:    v_alignbit_b32 v1, v2, v1, 168145; SI-NEXT:    s_or_b64 exec, exec, s[4:5]8146; SI-NEXT:    s_setpc_b64 s[30:31]8147;8148; VI-LABEL: bitcast_v4bf16_to_v2i32:8149; VI:       ; %bb.0:8150; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8151; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v28152; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc8153; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]8154; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]8155; VI-NEXT:    s_cbranch_execz .LBB66_28156; VI-NEXT:  ; %bb.1: ; %cmp.true8157; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v18158; VI-NEXT:    v_add_f32_e32 v2, 0x40c00000, v28159; VI-NEXT:    v_bfe_u32 v3, v2, 16, 18160; VI-NEXT:    v_add_u32_e32 v3, vcc, v3, v28161; VI-NEXT:    v_add_u32_e32 v3, vcc, 0x7fff, v38162; VI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v18163; VI-NEXT:    v_or_b32_e32 v4, 0x400000, v28164; VI-NEXT:    v_cmp_u_f32_e32 vcc, v2, v28165; VI-NEXT:    v_add_f32_e32 v1, 0x40c00000, v18166; VI-NEXT:    v_cndmask_b32_e32 v2, v3, v4, vcc8167; VI-NEXT:    v_bfe_u32 v3, v1, 16, 18168; VI-NEXT:    s_movk_i32 s6, 0x7fff8169; VI-NEXT:    v_add_u32_e32 v3, vcc, v3, v18170; VI-NEXT:    v_add_u32_e32 v3, vcc, s6, v38171; VI-NEXT:    v_or_b32_e32 v4, 0x400000, v18172; VI-NEXT:    v_cmp_u_f32_e32 vcc, v1, v18173; VI-NEXT:    v_cndmask_b32_e32 v1, v3, v4, vcc8174; VI-NEXT:    v_lshrrev_b32_e32 v1, 16, v18175; VI-NEXT:    v_alignbit_b32 v1, v1, v2, 168176; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v08177; VI-NEXT:    v_add_f32_e32 v2, 0x40c00000, v28178; VI-NEXT:    v_bfe_u32 v3, v2, 16, 18179; VI-NEXT:    v_add_u32_e32 v3, vcc, v3, v28180; VI-NEXT:    v_add_u32_e32 v3, vcc, s6, v38181; VI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v08182; VI-NEXT:    v_or_b32_e32 v4, 0x400000, v28183; VI-NEXT:    v_cmp_u_f32_e32 vcc, v2, v28184; VI-NEXT:    v_add_f32_e32 v0, 0x40c00000, v08185; VI-NEXT:    v_cndmask_b32_e32 v2, v3, v4, vcc8186; VI-NEXT:    v_bfe_u32 v3, v0, 16, 18187; VI-NEXT:    v_add_u32_e32 v3, vcc, v3, v08188; VI-NEXT:    v_add_u32_e32 v3, vcc, 0x7fff, v38189; VI-NEXT:    v_or_b32_e32 v4, 0x400000, v08190; VI-NEXT:    v_cmp_u_f32_e32 vcc, v0, v08191; VI-NEXT:    v_cndmask_b32_e32 v0, v3, v4, vcc8192; VI-NEXT:    v_lshrrev_b32_e32 v0, 16, v08193; VI-NEXT:    v_alignbit_b32 v0, v0, v2, 168194; VI-NEXT:  .LBB66_2: ; %end8195; VI-NEXT:    s_or_b64 exec, exec, s[4:5]8196; VI-NEXT:    s_setpc_b64 s[30:31]8197;8198; GFX9-LABEL: bitcast_v4bf16_to_v2i32:8199; GFX9:       ; %bb.0:8200; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8201; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v28202; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc8203; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]8204; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]8205; GFX9-NEXT:    s_cbranch_execz .LBB66_28206; GFX9-NEXT:  ; %bb.1: ; %cmp.true8207; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 16, v08208; GFX9-NEXT:    v_add_f32_e32 v2, 0x40c00000, v28209; GFX9-NEXT:    v_bfe_u32 v3, v2, 16, 18210; GFX9-NEXT:    s_movk_i32 s6, 0x7fff8211; GFX9-NEXT:    v_and_b32_e32 v0, 0xffff0000, v08212; GFX9-NEXT:    v_add3_u32 v3, v3, v2, s68213; GFX9-NEXT:    v_or_b32_e32 v4, 0x400000, v28214; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v2, v28215; GFX9-NEXT:    v_add_f32_e32 v0, 0x40c00000, v08216; GFX9-NEXT:    v_cndmask_b32_e32 v2, v3, v4, vcc8217; GFX9-NEXT:    v_bfe_u32 v3, v0, 16, 18218; GFX9-NEXT:    v_add3_u32 v3, v3, v0, s68219; GFX9-NEXT:    v_or_b32_e32 v4, 0x400000, v08220; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v0, v08221; GFX9-NEXT:    v_cndmask_b32_e32 v0, v3, v4, vcc8222; GFX9-NEXT:    s_mov_b32 s7, 0x70603028223; GFX9-NEXT:    v_perm_b32 v0, v0, v2, s78224; GFX9-NEXT:    v_and_b32_e32 v2, 0xffff0000, v18225; GFX9-NEXT:    v_add_f32_e32 v2, 0x40c00000, v28226; GFX9-NEXT:    v_bfe_u32 v3, v2, 16, 18227; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 16, v18228; GFX9-NEXT:    v_add3_u32 v3, v3, v2, s68229; GFX9-NEXT:    v_or_b32_e32 v4, 0x400000, v28230; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v2, v28231; GFX9-NEXT:    v_add_f32_e32 v1, 0x40c00000, v18232; GFX9-NEXT:    v_cndmask_b32_e32 v2, v3, v4, vcc8233; GFX9-NEXT:    v_bfe_u32 v3, v1, 16, 18234; GFX9-NEXT:    v_add3_u32 v3, v3, v1, s68235; GFX9-NEXT:    v_or_b32_e32 v4, 0x400000, v18236; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v1, v18237; GFX9-NEXT:    v_cndmask_b32_e32 v1, v3, v4, vcc8238; GFX9-NEXT:    v_perm_b32 v1, v2, v1, s78239; GFX9-NEXT:  .LBB66_2: ; %end8240; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]8241; GFX9-NEXT:    s_setpc_b64 s[30:31]8242;8243; GFX11-TRUE16-LABEL: bitcast_v4bf16_to_v2i32:8244; GFX11-TRUE16:       ; %bb.0:8245; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8246; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v28247; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_vgpr38248; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo8249; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)8250; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s08251; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false8252; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v08253; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr08254; GFX11-TRUE16-NEXT:  ; %bb.2: ; %Flow8255; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s08256; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB66_48257; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true8258; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, 08259; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.h, v0.l8260; GFX11-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v08261; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v18262; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)8263; GFX11-TRUE16-NEXT:    v_add_f32_e32 v4, 0x40c00000, v38264; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.h, v1.l8265; GFX11-TRUE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v28266; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)8267; GFX11-TRUE16-NEXT:    v_add_f32_e32 v0, 0x40c00000, v08268; GFX11-TRUE16-NEXT:    v_bfe_u32 v6, v4, 16, 18269; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)8270; GFX11-TRUE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v38271; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, 0x400000, v48272; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v48273; GFX11-TRUE16-NEXT:    v_bfe_u32 v1, v2, 16, 18274; GFX11-TRUE16-NEXT:    v_add3_u32 v6, v6, v4, 0x7fff8275; GFX11-TRUE16-NEXT:    v_bfe_u32 v9, v3, 16, 18276; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, 0x400000, v38277; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, 0x400000, v28278; GFX11-TRUE16-NEXT:    v_bfe_u32 v8, v0, 16, 18279; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v4, v6, v7, vcc_lo8280; GFX11-TRUE16-NEXT:    v_add3_u32 v9, v9, v3, 0x7fff8281; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v38282; GFX11-TRUE16-NEXT:    v_add3_u32 v1, v1, v2, 0x7fff8283; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, 0x400000, v08284; GFX11-TRUE16-NEXT:    v_add3_u32 v8, v8, v0, 0x7fff8285; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v6, v9, v11, vcc_lo8286; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v28287; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v1, v5, vcc_lo8288; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v08289; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v4.h8290; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v8, v10, vcc_lo8291; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v6.h8292; GFX11-TRUE16-NEXT:  .LBB66_4: ; %end8293; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s08294; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)8295; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v38296; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]8297;8298; GFX11-FAKE16-LABEL: bitcast_v4bf16_to_v2i32:8299; GFX11-FAKE16:       ; %bb.0:8300; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8301; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo8302; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v28303; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s08304; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)8305; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s08306; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB66_28307; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true8308; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff0000, v18309; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)8310; GFX11-FAKE16-NEXT:    v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v2, 16, v08311; GFX11-FAKE16-NEXT:    v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v1, 16, v18312; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)8313; GFX11-FAKE16-NEXT:    v_bfe_u32 v8, v3, 16, 18314; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, 0x400000, v38315; GFX11-FAKE16-NEXT:    v_bfe_u32 v4, v2, 16, 18316; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, 0x400000, v28317; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v28318; GFX11-FAKE16-NEXT:    v_add3_u32 v8, v8, v3, 0x7fff8319; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v08320; GFX11-FAKE16-NEXT:    v_add3_u32 v4, v4, v2, 0x7fff8321; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)8322; GFX11-FAKE16-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v08323; GFX11-FAKE16-NEXT:    v_bfe_u32 v9, v1, 16, 18324; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)8325; GFX11-FAKE16-NEXT:    v_bfe_u32 v6, v0, 16, 18326; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, 0x400000, v08327; GFX11-FAKE16-NEXT:    v_add3_u32 v9, v9, v1, 0x7fff8328; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v4, v5, vcc_lo8329; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v08330; GFX11-FAKE16-NEXT:    v_add3_u32 v6, v6, v0, 0x7fff8331; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, 0x400000, v18332; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)8333; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v6, v7, vcc_lo8334; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v38335; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v8, v10, vcc_lo8336; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v18337; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v9, v4, vcc_lo8338; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v2, 0x70603028339; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)8340; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v3, v1, 0x70603028341; GFX11-FAKE16-NEXT:  .LBB66_2: ; %end8342; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s08343; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]8344  %cmp = icmp eq i32 %b, 08345  br i1 %cmp, label %cmp.true, label %cmp.false8346 8347cmp.true:8348  %a1 = fadd <4 x bfloat> %a, splat (bfloat 0xR40C0)8349  %a2 = bitcast <4 x bfloat> %a1 to <2 x i32>8350  br label %end8351 8352cmp.false:8353  %a3 = bitcast <4 x bfloat> %a to <2 x i32>8354  br label %end8355 8356end:8357  %phi = phi <2 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]8358  ret <2 x i32> %phi8359}8360 8361define inreg <2 x i32> @bitcast_v4bf16_to_v2i32_scalar(<4 x bfloat> inreg %a, i32 inreg %b) {8362; SI-LABEL: bitcast_v4bf16_to_v2i32_scalar:8363; SI:       ; %bb.0:8364; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8365; SI-NEXT:    s_cmp_lg_u32 s20, 08366; SI-NEXT:    v_mul_f32_e64 v8, 1.0, s178367; SI-NEXT:    v_mul_f32_e64 v5, 1.0, s168368; SI-NEXT:    v_mul_f32_e64 v7, 1.0, s198369; SI-NEXT:    v_mul_f32_e64 v3, 1.0, s188370; SI-NEXT:    s_cbranch_scc0 .LBB67_48371; SI-NEXT:  ; %bb.1: ; %cmp.false8372; SI-NEXT:    v_lshrrev_b32_e32 v6, 16, v88373; SI-NEXT:    v_lshr_b64 v[0:1], v[5:6], 168374; SI-NEXT:    v_lshrrev_b32_e32 v4, 16, v78375; SI-NEXT:    v_lshr_b64 v[1:2], v[3:4], 168376; SI-NEXT:    s_cbranch_execnz .LBB67_38377; SI-NEXT:  .LBB67_2: ; %cmp.true8378; SI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v88379; SI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v58380; SI-NEXT:    v_add_f32_e32 v1, 0x40c00000, v18381; SI-NEXT:    v_add_f32_e32 v0, 0x40c00000, v08382; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v18383; SI-NEXT:    v_lshr_b64 v[0:1], v[0:1], 168384; SI-NEXT:    v_and_b32_e32 v2, 0xffff0000, v78385; SI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v38386; SI-NEXT:    v_add_f32_e32 v2, 0x40c00000, v28387; SI-NEXT:    v_add_f32_e32 v1, 0x40c00000, v18388; SI-NEXT:    v_lshrrev_b32_e32 v2, 16, v28389; SI-NEXT:    v_lshr_b64 v[1:2], v[1:2], 168390; SI-NEXT:  .LBB67_3: ; %end8391; SI-NEXT:    s_setpc_b64 s[30:31]8392; SI-NEXT:  .LBB67_4:8393; SI-NEXT:    ; implicit-def: $vgpr0_vgpr18394; SI-NEXT:    s_branch .LBB67_28395;8396; VI-LABEL: bitcast_v4bf16_to_v2i32_scalar:8397; VI:       ; %bb.0:8398; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8399; VI-NEXT:    s_cmp_lg_u32 s18, 08400; VI-NEXT:    s_cbranch_scc0 .LBB67_38401; VI-NEXT:  ; %bb.1: ; %cmp.false8402; VI-NEXT:    s_cbranch_execnz .LBB67_48403; VI-NEXT:  .LBB67_2: ; %cmp.true8404; VI-NEXT:    s_lshl_b32 s4, s17, 168405; VI-NEXT:    v_mov_b32_e32 v4, 0x40c000008406; VI-NEXT:    v_add_f32_e32 v0, s4, v48407; VI-NEXT:    v_bfe_u32 v1, v0, 16, 18408; VI-NEXT:    v_add_u32_e32 v1, vcc, v1, v08409; VI-NEXT:    v_add_u32_e32 v1, vcc, 0x7fff, v18410; VI-NEXT:    v_or_b32_e32 v2, 0x400000, v08411; VI-NEXT:    v_cmp_u_f32_e32 vcc, v0, v08412; VI-NEXT:    s_and_b32 s4, s17, 0xffff00008413; VI-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc8414; VI-NEXT:    v_add_f32_e32 v1, s4, v48415; VI-NEXT:    v_bfe_u32 v2, v1, 16, 18416; VI-NEXT:    v_add_u32_e32 v2, vcc, v2, v18417; VI-NEXT:    v_add_u32_e32 v2, vcc, 0x7fff, v28418; VI-NEXT:    v_or_b32_e32 v3, 0x400000, v18419; VI-NEXT:    v_cmp_u_f32_e32 vcc, v1, v18420; VI-NEXT:    v_cndmask_b32_e32 v1, v2, v3, vcc8421; VI-NEXT:    v_lshrrev_b32_e32 v1, 16, v18422; VI-NEXT:    s_lshl_b32 s4, s16, 168423; VI-NEXT:    v_lshrrev_b64 v[2:3], 16, v[0:1]8424; VI-NEXT:    v_add_f32_e32 v0, s4, v48425; VI-NEXT:    v_bfe_u32 v1, v0, 16, 18426; VI-NEXT:    v_add_u32_e32 v1, vcc, v1, v08427; VI-NEXT:    v_add_u32_e32 v1, vcc, 0x7fff, v18428; VI-NEXT:    v_or_b32_e32 v3, 0x400000, v08429; VI-NEXT:    v_cmp_u_f32_e32 vcc, v0, v08430; VI-NEXT:    s_and_b32 s4, s16, 0xffff00008431; VI-NEXT:    v_cndmask_b32_e32 v0, v1, v3, vcc8432; VI-NEXT:    v_add_f32_e32 v1, s4, v48433; VI-NEXT:    v_bfe_u32 v3, v1, 16, 18434; VI-NEXT:    v_add_u32_e32 v3, vcc, v3, v18435; VI-NEXT:    v_add_u32_e32 v3, vcc, 0x7fff, v38436; VI-NEXT:    v_or_b32_e32 v4, 0x400000, v18437; VI-NEXT:    v_cmp_u_f32_e32 vcc, v1, v18438; VI-NEXT:    v_cndmask_b32_e32 v1, v3, v4, vcc8439; VI-NEXT:    v_lshrrev_b32_e32 v1, 16, v18440; VI-NEXT:    v_lshrrev_b64 v[0:1], 16, v[0:1]8441; VI-NEXT:    v_mov_b32_e32 v1, v28442; VI-NEXT:    s_setpc_b64 s[30:31]8443; VI-NEXT:  .LBB67_3:8444; VI-NEXT:    s_branch .LBB67_28445; VI-NEXT:  .LBB67_4:8446; VI-NEXT:    v_mov_b32_e32 v0, s168447; VI-NEXT:    v_mov_b32_e32 v1, s178448; VI-NEXT:    s_setpc_b64 s[30:31]8449;8450; GFX9-LABEL: bitcast_v4bf16_to_v2i32_scalar:8451; GFX9:       ; %bb.0:8452; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8453; GFX9-NEXT:    s_cmp_lg_u32 s18, 08454; GFX9-NEXT:    s_cbranch_scc0 .LBB67_38455; GFX9-NEXT:  ; %bb.1: ; %cmp.false8456; GFX9-NEXT:    s_cbranch_execnz .LBB67_48457; GFX9-NEXT:  .LBB67_2: ; %cmp.true8458; GFX9-NEXT:    s_pack_lh_b32_b16 s4, 0, s168459; GFX9-NEXT:    v_mov_b32_e32 v1, 0x40c000008460; GFX9-NEXT:    v_add_f32_e32 v0, s4, v18461; GFX9-NEXT:    v_bfe_u32 v2, v0, 16, 18462; GFX9-NEXT:    v_add_u32_e32 v2, v2, v08463; GFX9-NEXT:    v_add_u32_e32 v2, 0x7fff, v28464; GFX9-NEXT:    v_or_b32_e32 v3, 0x400000, v08465; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v0, v08466; GFX9-NEXT:    s_lshl_b32 s4, s16, 168467; GFX9-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc8468; GFX9-NEXT:    v_add_f32_e32 v2, s4, v18469; GFX9-NEXT:    v_bfe_u32 v3, v2, 16, 18470; GFX9-NEXT:    v_add_u32_e32 v3, v3, v28471; GFX9-NEXT:    v_add_u32_e32 v3, 0x7fff, v38472; GFX9-NEXT:    v_or_b32_e32 v4, 0x400000, v28473; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v2, v28474; GFX9-NEXT:    v_cndmask_b32_e32 v2, v3, v4, vcc8475; GFX9-NEXT:    v_mov_b32_e32 v3, 0xffff8476; GFX9-NEXT:    v_lshrrev_b32_e32 v0, 16, v08477; GFX9-NEXT:    v_and_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_18478; GFX9-NEXT:    s_pack_lh_b32_b16 s4, 0, s178479; GFX9-NEXT:    v_lshl_or_b32 v0, v0, 16, v28480; GFX9-NEXT:    v_add_f32_e32 v2, s4, v18481; GFX9-NEXT:    v_bfe_u32 v4, v2, 16, 18482; GFX9-NEXT:    v_add_u32_e32 v4, v4, v28483; GFX9-NEXT:    s_lshl_b32 s4, s17, 168484; GFX9-NEXT:    v_add_u32_e32 v4, 0x7fff, v48485; GFX9-NEXT:    v_or_b32_e32 v5, 0x400000, v28486; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v2, v28487; GFX9-NEXT:    v_add_f32_e32 v1, s4, v18488; GFX9-NEXT:    v_cndmask_b32_e32 v2, v4, v5, vcc8489; GFX9-NEXT:    v_bfe_u32 v4, v1, 16, 18490; GFX9-NEXT:    v_add_u32_e32 v4, v4, v18491; GFX9-NEXT:    v_add_u32_e32 v4, 0x7fff, v48492; GFX9-NEXT:    v_or_b32_e32 v5, 0x400000, v18493; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v1, v18494; GFX9-NEXT:    v_cndmask_b32_e32 v1, v4, v5, vcc8495; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 16, v28496; GFX9-NEXT:    v_and_b32_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_18497; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v18498; GFX9-NEXT:    s_setpc_b64 s[30:31]8499; GFX9-NEXT:  .LBB67_3:8500; GFX9-NEXT:    s_branch .LBB67_28501; GFX9-NEXT:  .LBB67_4:8502; GFX9-NEXT:    v_mov_b32_e32 v0, s168503; GFX9-NEXT:    v_mov_b32_e32 v1, s178504; GFX9-NEXT:    s_setpc_b64 s[30:31]8505;8506; GFX11-TRUE16-LABEL: bitcast_v4bf16_to_v2i32_scalar:8507; GFX11-TRUE16:       ; %bb.0:8508; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8509; GFX11-TRUE16-NEXT:    s_cmp_lg_u32 s2, 08510; GFX11-TRUE16-NEXT:    s_mov_b32 s2, 08511; GFX11-TRUE16-NEXT:    s_cbranch_scc0 .LBB67_38512; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow8513; GFX11-TRUE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s28514; GFX11-TRUE16-NEXT:    s_cbranch_vccnz .LBB67_48515; GFX11-TRUE16-NEXT:  .LBB67_2: ; %cmp.true8516; GFX11-TRUE16-NEXT:    s_pack_lh_b32_b16 s2, 0, s08517; GFX11-TRUE16-NEXT:    s_lshl_b32 s0, s0, 168518; GFX11-TRUE16-NEXT:    v_add_f32_e64 v0, 0x40c00000, s28519; GFX11-TRUE16-NEXT:    v_add_f32_e64 v1, 0x40c00000, s08520; GFX11-TRUE16-NEXT:    s_pack_lh_b32_b16 s2, 0, s18521; GFX11-TRUE16-NEXT:    s_lshl_b32 s1, s1, 168522; GFX11-TRUE16-NEXT:    v_add_f32_e64 v3, 0x40c00000, s28523; GFX11-TRUE16-NEXT:    v_bfe_u32 v2, v0, 16, 18524; GFX11-TRUE16-NEXT:    v_bfe_u32 v6, v1, 16, 18525; GFX11-TRUE16-NEXT:    v_add_f32_e64 v4, 0x40c00000, s18526; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, 0x400000, v08527; GFX11-TRUE16-NEXT:    v_bfe_u32 v8, v3, 16, 18528; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v2, v2, v08529; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v6, v6, v18530; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, 0x400000, v18531; GFX11-TRUE16-NEXT:    v_bfe_u32 v9, v4, 16, 18532; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v8, v8, v38533; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v08534; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v6, 0x7fff, v68535; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v2, 0x7fff, v28536; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, 0x400000, v38537; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)8538; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v0, v2, v5 :: v_dual_add_nc_u32 v9, v9, v48539; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, 0x400000, v48540; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v5, 0x7fff, v88541; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v38542; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v8, 0x7fff, v98543; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v9, 16, v08544; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)8545; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v5, v10, vcc_lo8546; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v18547; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v08548; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v6, v7, vcc_lo8549; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v48550; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)8551; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v18552; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v8, v2, vcc_lo8553; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v9.l8554; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v28555; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v3.l8556; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]8557; GFX11-TRUE16-NEXT:  .LBB67_3:8558; GFX11-TRUE16-NEXT:    s_branch .LBB67_28559; GFX11-TRUE16-NEXT:  .LBB67_4:8560; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s18561; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]8562;8563; GFX11-FAKE16-LABEL: bitcast_v4bf16_to_v2i32_scalar:8564; GFX11-FAKE16:       ; %bb.0:8565; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8566; GFX11-FAKE16-NEXT:    s_cmp_lg_u32 s2, 08567; GFX11-FAKE16-NEXT:    s_mov_b32 s2, 08568; GFX11-FAKE16-NEXT:    s_cbranch_scc0 .LBB67_38569; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow8570; GFX11-FAKE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s28571; GFX11-FAKE16-NEXT:    s_cbranch_vccnz .LBB67_48572; GFX11-FAKE16-NEXT:  .LBB67_2: ; %cmp.true8573; GFX11-FAKE16-NEXT:    s_pack_lh_b32_b16 s2, 0, s08574; GFX11-FAKE16-NEXT:    s_lshl_b32 s0, s0, 168575; GFX11-FAKE16-NEXT:    v_add_f32_e64 v0, 0x40c00000, s28576; GFX11-FAKE16-NEXT:    v_add_f32_e64 v1, 0x40c00000, s08577; GFX11-FAKE16-NEXT:    s_lshl_b32 s0, s1, 168578; GFX11-FAKE16-NEXT:    s_pack_lh_b32_b16 s1, 0, s18579; GFX11-FAKE16-NEXT:    v_add_f32_e64 v2, 0x40c00000, s08580; GFX11-FAKE16-NEXT:    v_add_f32_e64 v5, 0x40c00000, s18581; GFX11-FAKE16-NEXT:    v_bfe_u32 v4, v1, 16, 18582; GFX11-FAKE16-NEXT:    v_bfe_u32 v3, v0, 16, 18583; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, 0x400000, v18584; GFX11-FAKE16-NEXT:    v_bfe_u32 v6, v2, 16, 18585; GFX11-FAKE16-NEXT:    v_bfe_u32 v8, v5, 16, 18586; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v4, v4, v18587; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v18588; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, 0x400000, v28589; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, 0x400000, v08590; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v8, v8, v58591; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v4, 0x7fff, v48592; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)8593; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v1, v4, v9 :: v_dual_add_nc_u32 v6, v6, v28594; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v4, 0x7fff, v88595; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, 0x400000, v58596; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)8597; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v6, 0x7fff, v68598; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v28599; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v3, v3, v08600; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v18601; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v2, v6, v10 :: v_dual_add_nc_u32 v3, 0x7fff, v38602; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v08603; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)8604; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v18605; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v28606; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)8607; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v3, v7, vcc_lo8608; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v58609; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v28610; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)8611; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v08612; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v4, v8, vcc_lo8613; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v0, v0, 16, v18614; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)8615; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v38616; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, v3, 16, v28617; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]8618; GFX11-FAKE16-NEXT:  .LBB67_3:8619; GFX11-FAKE16-NEXT:    s_branch .LBB67_28620; GFX11-FAKE16-NEXT:  .LBB67_4:8621; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s18622; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]8623  %cmp = icmp eq i32 %b, 08624  br i1 %cmp, label %cmp.true, label %cmp.false8625 8626cmp.true:8627  %a1 = fadd <4 x bfloat> %a, splat (bfloat 0xR40C0)8628  %a2 = bitcast <4 x bfloat> %a1 to <2 x i32>8629  br label %end8630 8631cmp.false:8632  %a3 = bitcast <4 x bfloat> %a to <2 x i32>8633  br label %end8634 8635end:8636  %phi = phi <2 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]8637  ret <2 x i32> %phi8638}8639 8640define <8 x i8> @bitcast_v2i32_to_v8i8(<2 x i32> %a, i32 %b) {8641; SI-LABEL: bitcast_v2i32_to_v8i8:8642; SI:       ; %bb.0:8643; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8644; SI-NEXT:    v_mov_b32_e32 v4, v18645; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v28646; SI-NEXT:    ; implicit-def: $vgpr18647; SI-NEXT:    ; implicit-def: $vgpr28648; SI-NEXT:    ; implicit-def: $vgpr38649; SI-NEXT:    ; implicit-def: $vgpr58650; SI-NEXT:    ; implicit-def: $vgpr68651; SI-NEXT:    ; implicit-def: $vgpr78652; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc8653; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]8654; SI-NEXT:    s_cbranch_execnz .LBB68_38655; SI-NEXT:  ; %bb.1: ; %Flow8656; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]8657; SI-NEXT:    s_cbranch_execnz .LBB68_48658; SI-NEXT:  .LBB68_2: ; %end8659; SI-NEXT:    s_or_b64 exec, exec, s[4:5]8660; SI-NEXT:    s_setpc_b64 s[30:31]8661; SI-NEXT:  .LBB68_3: ; %cmp.false8662; SI-NEXT:    v_alignbit_b32 v3, v4, v0, 248663; SI-NEXT:    v_alignbit_b32 v2, v4, v0, 168664; SI-NEXT:    v_alignbit_b32 v1, v4, v0, 88665; SI-NEXT:    v_lshrrev_b32_e32 v7, 24, v48666; SI-NEXT:    v_lshrrev_b32_e32 v6, 16, v48667; SI-NEXT:    v_lshrrev_b32_e32 v5, 8, v48668; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]8669; SI-NEXT:    s_cbranch_execz .LBB68_28670; SI-NEXT:  .LBB68_4: ; %cmp.true8671; SI-NEXT:    v_add_i32_e32 v4, vcc, 3, v48672; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v08673; SI-NEXT:    v_alignbit_b32 v3, v4, v0, 248674; SI-NEXT:    v_alignbit_b32 v2, v4, v0, 168675; SI-NEXT:    v_alignbit_b32 v1, v4, v0, 88676; SI-NEXT:    v_lshrrev_b32_e32 v7, 24, v48677; SI-NEXT:    v_lshrrev_b32_e32 v6, 16, v48678; SI-NEXT:    v_lshrrev_b32_e32 v5, 8, v48679; SI-NEXT:    s_or_b64 exec, exec, s[4:5]8680; SI-NEXT:    s_setpc_b64 s[30:31]8681;8682; VI-LABEL: bitcast_v2i32_to_v8i8:8683; VI:       ; %bb.0:8684; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8685; VI-NEXT:    v_mov_b32_e32 v9, v18686; VI-NEXT:    v_mov_b32_e32 v8, v08687; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v28688; VI-NEXT:    ; implicit-def: $vgpr18689; VI-NEXT:    ; implicit-def: $vgpr28690; VI-NEXT:    ; implicit-def: $vgpr38691; VI-NEXT:    ; implicit-def: $vgpr58692; VI-NEXT:    ; implicit-def: $vgpr68693; VI-NEXT:    ; implicit-def: $vgpr78694; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc8695; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]8696; VI-NEXT:  ; %bb.1: ; %cmp.false8697; VI-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]8698; VI-NEXT:    v_lshrrev_b32_e32 v7, 24, v98699; VI-NEXT:    v_lshrrev_b32_e32 v6, 16, v98700; VI-NEXT:    v_lshrrev_b32_e32 v5, 8, v98701; VI-NEXT:    v_lshrrev_b32_e32 v2, 16, v88702; VI-NEXT:    v_lshrrev_b32_e32 v1, 8, v88703; VI-NEXT:  ; %bb.2: ; %Flow8704; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]8705; VI-NEXT:  ; %bb.3: ; %cmp.true8706; VI-NEXT:    v_add_u32_e32 v9, vcc, 3, v98707; VI-NEXT:    v_add_u32_e32 v8, vcc, 3, v88708; VI-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]8709; VI-NEXT:    v_lshrrev_b32_e32 v7, 24, v98710; VI-NEXT:    v_lshrrev_b32_e32 v6, 16, v98711; VI-NEXT:    v_lshrrev_b32_e32 v5, 8, v98712; VI-NEXT:    v_lshrrev_b32_e32 v2, 16, v88713; VI-NEXT:    v_lshrrev_b32_e32 v1, 8, v88714; VI-NEXT:  ; %bb.4: ; %end8715; VI-NEXT:    s_or_b64 exec, exec, s[4:5]8716; VI-NEXT:    v_mov_b32_e32 v0, v88717; VI-NEXT:    v_mov_b32_e32 v4, v98718; VI-NEXT:    s_setpc_b64 s[30:31]8719;8720; GFX9-LABEL: bitcast_v2i32_to_v8i8:8721; GFX9:       ; %bb.0:8722; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8723; GFX9-NEXT:    v_mov_b32_e32 v9, v18724; GFX9-NEXT:    v_mov_b32_e32 v8, v08725; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v28726; GFX9-NEXT:    ; implicit-def: $vgpr18727; GFX9-NEXT:    ; implicit-def: $vgpr28728; GFX9-NEXT:    ; implicit-def: $vgpr38729; GFX9-NEXT:    ; implicit-def: $vgpr58730; GFX9-NEXT:    ; implicit-def: $vgpr68731; GFX9-NEXT:    ; implicit-def: $vgpr78732; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc8733; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]8734; GFX9-NEXT:  ; %bb.1: ; %cmp.false8735; GFX9-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]8736; GFX9-NEXT:    v_lshrrev_b32_e32 v7, 24, v98737; GFX9-NEXT:    v_lshrrev_b32_e32 v6, 16, v98738; GFX9-NEXT:    v_lshrrev_b32_e32 v5, 8, v98739; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 16, v88740; GFX9-NEXT:    v_lshrrev_b32_e32 v1, 8, v88741; GFX9-NEXT:  ; %bb.2: ; %Flow8742; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]8743; GFX9-NEXT:  ; %bb.3: ; %cmp.true8744; GFX9-NEXT:    v_add_u32_e32 v9, 3, v98745; GFX9-NEXT:    v_add_u32_e32 v8, 3, v88746; GFX9-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]8747; GFX9-NEXT:    v_lshrrev_b32_e32 v7, 24, v98748; GFX9-NEXT:    v_lshrrev_b32_e32 v6, 16, v98749; GFX9-NEXT:    v_lshrrev_b32_e32 v5, 8, v98750; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 16, v88751; GFX9-NEXT:    v_lshrrev_b32_e32 v1, 8, v88752; GFX9-NEXT:  ; %bb.4: ; %end8753; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]8754; GFX9-NEXT:    v_mov_b32_e32 v0, v88755; GFX9-NEXT:    v_mov_b32_e32 v4, v98756; GFX9-NEXT:    s_setpc_b64 s[30:31]8757;8758; GFX11-TRUE16-LABEL: bitcast_v2i32_to_v8i8:8759; GFX11-TRUE16:       ; %bb.0:8760; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8761; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v08762; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo8763; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo168764; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo168765; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo168766; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_lo168767; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v28768; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s08769; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false8770; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)8771; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]8772; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v98773; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v98774; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v88775; GFX11-TRUE16-NEXT:  ; %bb.2: ; %Flow8776; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s08777; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true8778; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v9, 3, v98779; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v8, 3, v88780; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)8781; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v98782; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]8783; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v98784; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v88785; GFX11-TRUE16-NEXT:  ; %bb.4: ; %end8786; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s08787; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v8.l8788; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v8.h8789; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v9.l8790; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v9.h8791; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]8792;8793; GFX11-FAKE16-LABEL: bitcast_v2i32_to_v8i8:8794; GFX11-FAKE16:       ; %bb.0:8795; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8796; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v08797; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v28798; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18799; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr28800; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38801; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr58802; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr68803; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr78804; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo8805; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)8806; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s08807; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false8808; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)8809; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]8810; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v98811; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v98812; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v98813; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v88814; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v88815; GFX11-FAKE16-NEXT:  ; %bb.2: ; %Flow8816; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s08817; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB68_48818; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true8819; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v9, 3, v98820; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v8, 3, v88821; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)8822; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v98823; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]8824; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v98825; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v98826; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v88827; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v88828; GFX11-FAKE16-NEXT:  .LBB68_4: ; %end8829; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s08830; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, v88831; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, v98832; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]8833  %cmp = icmp eq i32 %b, 08834  br i1 %cmp, label %cmp.true, label %cmp.false8835 8836cmp.true:8837  %a1 = add <2 x i32> %a, splat (i32 3)8838  %a2 = bitcast <2 x i32> %a1 to <8 x i8>8839  br label %end8840 8841cmp.false:8842  %a3 = bitcast <2 x i32> %a to <8 x i8>8843  br label %end8844 8845end:8846  %phi = phi <8 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]8847  ret <8 x i8> %phi8848}8849 8850define inreg <8 x i8> @bitcast_v2i32_to_v8i8_scalar(<2 x i32> inreg %a, i32 inreg %b) {8851; SI-LABEL: bitcast_v2i32_to_v8i8_scalar:8852; SI:       ; %bb.0:8853; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8854; SI-NEXT:    s_cmp_lg_u32 s18, 08855; SI-NEXT:    s_cbranch_scc0 .LBB69_48856; SI-NEXT:  ; %bb.1: ; %cmp.false8857; SI-NEXT:    s_lshr_b32 s12, s17, 248858; SI-NEXT:    s_lshr_b32 s13, s17, 168859; SI-NEXT:    s_lshr_b32 s14, s17, 88860; SI-NEXT:    s_lshr_b64 s[4:5], s[16:17], 248861; SI-NEXT:    s_lshr_b64 s[6:7], s[16:17], 168862; SI-NEXT:    s_lshr_b64 s[8:9], s[16:17], 88863; SI-NEXT:    s_cbranch_execnz .LBB69_38864; SI-NEXT:  .LBB69_2: ; %cmp.true8865; SI-NEXT:    s_add_i32 s17, s17, 38866; SI-NEXT:    s_add_i32 s16, s16, 38867; SI-NEXT:    s_lshr_b64 s[4:5], s[16:17], 248868; SI-NEXT:    s_lshr_b64 s[6:7], s[16:17], 168869; SI-NEXT:    s_lshr_b64 s[8:9], s[16:17], 88870; SI-NEXT:    s_lshr_b32 s12, s17, 248871; SI-NEXT:    s_lshr_b32 s13, s17, 168872; SI-NEXT:    s_lshr_b32 s14, s17, 88873; SI-NEXT:  .LBB69_3: ; %end8874; SI-NEXT:    v_mov_b32_e32 v0, s168875; SI-NEXT:    v_mov_b32_e32 v1, s88876; SI-NEXT:    v_mov_b32_e32 v2, s68877; SI-NEXT:    v_mov_b32_e32 v3, s48878; SI-NEXT:    v_mov_b32_e32 v4, s178879; SI-NEXT:    v_mov_b32_e32 v5, s148880; SI-NEXT:    v_mov_b32_e32 v6, s138881; SI-NEXT:    v_mov_b32_e32 v7, s128882; SI-NEXT:    s_setpc_b64 s[30:31]8883; SI-NEXT:  .LBB69_4:8884; SI-NEXT:    ; implicit-def: $sgpr88885; SI-NEXT:    ; implicit-def: $sgpr68886; SI-NEXT:    ; implicit-def: $sgpr48887; SI-NEXT:    ; implicit-def: $sgpr148888; SI-NEXT:    ; implicit-def: $sgpr138889; SI-NEXT:    ; implicit-def: $sgpr128890; SI-NEXT:    s_branch .LBB69_28891;8892; VI-LABEL: bitcast_v2i32_to_v8i8_scalar:8893; VI:       ; %bb.0:8894; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8895; VI-NEXT:    s_cmp_lg_u32 s18, 08896; VI-NEXT:    s_cbranch_scc0 .LBB69_48897; VI-NEXT:  ; %bb.1: ; %cmp.false8898; VI-NEXT:    s_lshr_b64 s[4:5], s[16:17], 248899; VI-NEXT:    s_lshr_b32 s5, s17, 248900; VI-NEXT:    s_lshr_b32 s8, s17, 168901; VI-NEXT:    s_lshr_b32 s9, s17, 88902; VI-NEXT:    s_lshr_b32 s10, s16, 168903; VI-NEXT:    s_lshr_b32 s11, s16, 88904; VI-NEXT:    s_cbranch_execnz .LBB69_38905; VI-NEXT:  .LBB69_2: ; %cmp.true8906; VI-NEXT:    s_add_i32 s17, s17, 38907; VI-NEXT:    s_add_i32 s16, s16, 38908; VI-NEXT:    s_lshr_b64 s[4:5], s[16:17], 248909; VI-NEXT:    s_lshr_b32 s5, s17, 248910; VI-NEXT:    s_lshr_b32 s8, s17, 168911; VI-NEXT:    s_lshr_b32 s9, s17, 88912; VI-NEXT:    s_lshr_b32 s10, s16, 168913; VI-NEXT:    s_lshr_b32 s11, s16, 88914; VI-NEXT:  .LBB69_3: ; %end8915; VI-NEXT:    v_mov_b32_e32 v0, s168916; VI-NEXT:    v_mov_b32_e32 v1, s118917; VI-NEXT:    v_mov_b32_e32 v2, s108918; VI-NEXT:    v_mov_b32_e32 v3, s48919; VI-NEXT:    v_mov_b32_e32 v4, s178920; VI-NEXT:    v_mov_b32_e32 v5, s98921; VI-NEXT:    v_mov_b32_e32 v6, s88922; VI-NEXT:    v_mov_b32_e32 v7, s58923; VI-NEXT:    s_setpc_b64 s[30:31]8924; VI-NEXT:  .LBB69_4:8925; VI-NEXT:    ; implicit-def: $sgpr118926; VI-NEXT:    ; implicit-def: $sgpr108927; VI-NEXT:    ; implicit-def: $sgpr48928; VI-NEXT:    ; implicit-def: $sgpr98929; VI-NEXT:    ; implicit-def: $sgpr88930; VI-NEXT:    ; implicit-def: $sgpr58931; VI-NEXT:    s_branch .LBB69_28932;8933; GFX9-LABEL: bitcast_v2i32_to_v8i8_scalar:8934; GFX9:       ; %bb.0:8935; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8936; GFX9-NEXT:    s_cmp_lg_u32 s18, 08937; GFX9-NEXT:    s_cbranch_scc0 .LBB69_48938; GFX9-NEXT:  ; %bb.1: ; %cmp.false8939; GFX9-NEXT:    s_lshr_b64 s[4:5], s[16:17], 248940; GFX9-NEXT:    s_lshr_b32 s5, s17, 248941; GFX9-NEXT:    s_lshr_b32 s8, s17, 168942; GFX9-NEXT:    s_lshr_b32 s9, s17, 88943; GFX9-NEXT:    s_lshr_b32 s10, s16, 168944; GFX9-NEXT:    s_lshr_b32 s11, s16, 88945; GFX9-NEXT:    s_cbranch_execnz .LBB69_38946; GFX9-NEXT:  .LBB69_2: ; %cmp.true8947; GFX9-NEXT:    s_add_i32 s17, s17, 38948; GFX9-NEXT:    s_add_i32 s16, s16, 38949; GFX9-NEXT:    s_lshr_b64 s[4:5], s[16:17], 248950; GFX9-NEXT:    s_lshr_b32 s5, s17, 248951; GFX9-NEXT:    s_lshr_b32 s8, s17, 168952; GFX9-NEXT:    s_lshr_b32 s9, s17, 88953; GFX9-NEXT:    s_lshr_b32 s10, s16, 168954; GFX9-NEXT:    s_lshr_b32 s11, s16, 88955; GFX9-NEXT:  .LBB69_3: ; %end8956; GFX9-NEXT:    v_mov_b32_e32 v0, s168957; GFX9-NEXT:    v_mov_b32_e32 v1, s118958; GFX9-NEXT:    v_mov_b32_e32 v2, s108959; GFX9-NEXT:    v_mov_b32_e32 v3, s48960; GFX9-NEXT:    v_mov_b32_e32 v4, s178961; GFX9-NEXT:    v_mov_b32_e32 v5, s98962; GFX9-NEXT:    v_mov_b32_e32 v6, s88963; GFX9-NEXT:    v_mov_b32_e32 v7, s58964; GFX9-NEXT:    s_setpc_b64 s[30:31]8965; GFX9-NEXT:  .LBB69_4:8966; GFX9-NEXT:    ; implicit-def: $sgpr118967; GFX9-NEXT:    ; implicit-def: $sgpr108968; GFX9-NEXT:    ; implicit-def: $sgpr48969; GFX9-NEXT:    ; implicit-def: $sgpr98970; GFX9-NEXT:    ; implicit-def: $sgpr88971; GFX9-NEXT:    ; implicit-def: $sgpr58972; GFX9-NEXT:    s_branch .LBB69_28973;8974; GFX11-LABEL: bitcast_v2i32_to_v8i8_scalar:8975; GFX11:       ; %bb.0:8976; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8977; GFX11-NEXT:    s_cmp_lg_u32 s2, 08978; GFX11-NEXT:    s_mov_b32 s8, 08979; GFX11-NEXT:    s_cbranch_scc0 .LBB69_48980; GFX11-NEXT:  ; %bb.1: ; %cmp.false8981; GFX11-NEXT:    s_lshr_b64 s[2:3], s[0:1], 248982; GFX11-NEXT:    s_lshr_b32 s3, s1, 248983; GFX11-NEXT:    s_lshr_b32 s4, s1, 168984; GFX11-NEXT:    s_lshr_b32 s5, s1, 88985; GFX11-NEXT:    s_lshr_b32 s6, s0, 168986; GFX11-NEXT:    s_lshr_b32 s7, s0, 88987; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s88988; GFX11-NEXT:    s_cbranch_vccnz .LBB69_38989; GFX11-NEXT:  .LBB69_2: ; %cmp.true8990; GFX11-NEXT:    s_add_i32 s1, s1, 38991; GFX11-NEXT:    s_add_i32 s0, s0, 38992; GFX11-NEXT:    s_lshr_b32 s4, s1, 168993; GFX11-NEXT:    s_lshr_b64 s[2:3], s[0:1], 248994; GFX11-NEXT:    s_lshr_b32 s3, s1, 248995; GFX11-NEXT:    s_lshr_b32 s5, s1, 88996; GFX11-NEXT:    s_lshr_b32 s6, s0, 168997; GFX11-NEXT:    s_lshr_b32 s7, s0, 88998; GFX11-NEXT:  .LBB69_3: ; %end8999; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)9000; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s79001; GFX11-NEXT:    v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s29002; GFX11-NEXT:    v_dual_mov_b32 v4, s1 :: v_dual_mov_b32 v5, s59003; GFX11-NEXT:    v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s39004; GFX11-NEXT:    s_setpc_b64 s[30:31]9005; GFX11-NEXT:  .LBB69_4:9006; GFX11-NEXT:    ; implicit-def: $sgpr79007; GFX11-NEXT:    ; implicit-def: $sgpr69008; GFX11-NEXT:    ; implicit-def: $sgpr29009; GFX11-NEXT:    ; implicit-def: $sgpr59010; GFX11-NEXT:    ; implicit-def: $sgpr49011; GFX11-NEXT:    ; implicit-def: $sgpr39012; GFX11-NEXT:    s_branch .LBB69_29013  %cmp = icmp eq i32 %b, 09014  br i1 %cmp, label %cmp.true, label %cmp.false9015 9016cmp.true:9017  %a1 = add <2 x i32> %a, splat (i32 3)9018  %a2 = bitcast <2 x i32> %a1 to <8 x i8>9019  br label %end9020 9021cmp.false:9022  %a3 = bitcast <2 x i32> %a to <8 x i8>9023  br label %end9024 9025end:9026  %phi = phi <8 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]9027  ret <8 x i8> %phi9028}9029 9030define <2 x i32> @bitcast_v8i8_to_v2i32(<8 x i8> %a, i32 %b) {9031; SI-LABEL: bitcast_v8i8_to_v2i32:9032; SI:       ; %bb.0:9033; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9034; SI-NEXT:    v_mov_b32_e32 v9, v09035; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v89036; SI-NEXT:    v_lshlrev_b32_e32 v10, 8, v19037; SI-NEXT:    v_lshlrev_b32_e32 v8, 24, v39038; SI-NEXT:    v_lshlrev_b32_e32 v5, 8, v59039; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v79040; SI-NEXT:    ; implicit-def: $vgpr0_vgpr19041; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc9042; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]9043; SI-NEXT:    s_cbranch_execnz .LBB70_39044; SI-NEXT:  ; %bb.1: ; %Flow9045; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]9046; SI-NEXT:    s_cbranch_execnz .LBB70_49047; SI-NEXT:  .LBB70_2: ; %end9048; SI-NEXT:    s_or_b64 exec, exec, s[4:5]9049; SI-NEXT:    s_setpc_b64 s[30:31]9050; SI-NEXT:  .LBB70_3: ; %cmp.false9051; SI-NEXT:    v_and_b32_e32 v0, 0xff, v99052; SI-NEXT:    v_and_b32_e32 v1, 0xff, v29053; SI-NEXT:    v_or_b32_e32 v0, v0, v109054; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v19055; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v09056; SI-NEXT:    v_or_b32_e32 v1, v8, v19057; SI-NEXT:    v_or_b32_e32 v0, v0, v19058; SI-NEXT:    v_and_b32_e32 v1, 0xff, v49059; SI-NEXT:    v_and_b32_e32 v2, 0xff, v69060; SI-NEXT:    v_or_b32_e32 v1, v1, v59061; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v29062; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v19063; SI-NEXT:    v_or_b32_e32 v2, v3, v29064; SI-NEXT:    v_or_b32_e32 v1, v1, v29065; SI-NEXT:    ; implicit-def: $vgpr99066; SI-NEXT:    ; implicit-def: $vgpr109067; SI-NEXT:    ; implicit-def: $vgpr29068; SI-NEXT:    ; implicit-def: $vgpr89069; SI-NEXT:    ; implicit-def: $vgpr49070; SI-NEXT:    ; implicit-def: $vgpr59071; SI-NEXT:    ; implicit-def: $vgpr69072; SI-NEXT:    ; implicit-def: $vgpr39073; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]9074; SI-NEXT:    s_cbranch_execz .LBB70_29075; SI-NEXT:  .LBB70_4: ; %cmp.true9076; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v99077; SI-NEXT:    v_and_b32_e32 v0, 0xff, v09078; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v29079; SI-NEXT:    v_or_b32_e32 v0, v10, v09080; SI-NEXT:    v_and_b32_e32 v1, 0xff, v19081; SI-NEXT:    v_add_i32_e32 v0, vcc, 0x300, v09082; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v19083; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v09084; SI-NEXT:    v_or_b32_e32 v1, v8, v19085; SI-NEXT:    v_or_b32_e32 v0, v1, v09086; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v49087; SI-NEXT:    v_and_b32_e32 v1, 0xff, v19088; SI-NEXT:    v_add_i32_e32 v2, vcc, 3, v69089; SI-NEXT:    v_or_b32_e32 v1, v5, v19090; SI-NEXT:    v_and_b32_e32 v2, 0xff, v29091; SI-NEXT:    v_add_i32_e32 v1, vcc, 0x300, v19092; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v29093; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v19094; SI-NEXT:    v_or_b32_e32 v2, v3, v29095; SI-NEXT:    v_or_b32_e32 v1, v2, v19096; SI-NEXT:    v_add_i32_e32 v0, vcc, 0x3000000, v09097; SI-NEXT:    v_add_i32_e32 v1, vcc, 0x3000000, v19098; SI-NEXT:    s_or_b64 exec, exec, s[4:5]9099; SI-NEXT:    s_setpc_b64 s[30:31]9100;9101; VI-LABEL: bitcast_v8i8_to_v2i32:9102; VI:       ; %bb.0:9103; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9104; VI-NEXT:    v_mov_b32_e32 v9, v09105; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v89106; VI-NEXT:    v_lshlrev_b16_e32 v10, 8, v19107; VI-NEXT:    v_lshlrev_b16_e32 v8, 8, v39108; VI-NEXT:    v_lshlrev_b16_e32 v5, 8, v59109; VI-NEXT:    v_lshlrev_b16_e32 v3, 8, v79110; VI-NEXT:    ; implicit-def: $vgpr0_vgpr19111; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc9112; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]9113; VI-NEXT:    s_cbranch_execnz .LBB70_39114; VI-NEXT:  ; %bb.1: ; %Flow9115; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]9116; VI-NEXT:    s_cbranch_execnz .LBB70_49117; VI-NEXT:  .LBB70_2: ; %end9118; VI-NEXT:    s_or_b64 exec, exec, s[4:5]9119; VI-NEXT:    s_setpc_b64 s[30:31]9120; VI-NEXT:  .LBB70_3: ; %cmp.false9121; VI-NEXT:    v_or_b32_sdwa v0, v9, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD9122; VI-NEXT:    v_or_b32_sdwa v1, v2, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD9123; VI-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD9124; VI-NEXT:    v_or_b32_sdwa v1, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD9125; VI-NEXT:    v_or_b32_sdwa v2, v6, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD9126; VI-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD9127; VI-NEXT:    ; implicit-def: $vgpr99128; VI-NEXT:    ; implicit-def: $vgpr109129; VI-NEXT:    ; implicit-def: $vgpr29130; VI-NEXT:    ; implicit-def: $vgpr89131; VI-NEXT:    ; implicit-def: $vgpr49132; VI-NEXT:    ; implicit-def: $vgpr59133; VI-NEXT:    ; implicit-def: $vgpr69134; VI-NEXT:    ; implicit-def: $vgpr39135; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]9136; VI-NEXT:    s_cbranch_execz .LBB70_29137; VI-NEXT:  .LBB70_4: ; %cmp.true9138; VI-NEXT:    v_add_u16_e32 v0, 3, v99139; VI-NEXT:    v_add_u16_e32 v1, 3, v29140; VI-NEXT:    v_or_b32_sdwa v0, v10, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_09141; VI-NEXT:    v_or_b32_sdwa v1, v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_09142; VI-NEXT:    v_mov_b32_e32 v2, 0x3009143; VI-NEXT:    v_add_u16_e32 v0, 0x300, v09144; VI-NEXT:    v_add_u16_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD9145; VI-NEXT:    v_or_b32_e32 v0, v0, v19146; VI-NEXT:    v_add_u16_e32 v1, 3, v49147; VI-NEXT:    v_add_u16_e32 v4, 3, v69148; VI-NEXT:    v_or_b32_sdwa v1, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_09149; VI-NEXT:    v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_09150; VI-NEXT:    v_add_u16_e32 v1, 0x300, v19151; VI-NEXT:    v_add_u16_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD9152; VI-NEXT:    v_or_b32_e32 v1, v1, v29153; VI-NEXT:    s_or_b64 exec, exec, s[4:5]9154; VI-NEXT:    s_setpc_b64 s[30:31]9155;9156; GFX9-LABEL: bitcast_v8i8_to_v2i32:9157; GFX9:       ; %bb.0:9158; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9159; GFX9-NEXT:    v_mov_b32_e32 v9, v09160; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v89161; GFX9-NEXT:    v_lshlrev_b16_e32 v10, 8, v19162; GFX9-NEXT:    v_lshlrev_b16_e32 v8, 8, v39163; GFX9-NEXT:    v_lshlrev_b16_e32 v5, 8, v59164; GFX9-NEXT:    v_lshlrev_b16_e32 v3, 8, v79165; GFX9-NEXT:    ; implicit-def: $vgpr0_vgpr19166; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc9167; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]9168; GFX9-NEXT:    s_cbranch_execnz .LBB70_39169; GFX9-NEXT:  ; %bb.1: ; %Flow9170; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]9171; GFX9-NEXT:    s_cbranch_execnz .LBB70_49172; GFX9-NEXT:  .LBB70_2: ; %end9173; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]9174; GFX9-NEXT:    s_setpc_b64 s[30:31]9175; GFX9-NEXT:  .LBB70_3: ; %cmp.false9176; GFX9-NEXT:    v_or_b32_sdwa v0, v9, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD9177; GFX9-NEXT:    v_or_b32_sdwa v1, v2, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD9178; GFX9-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD9179; GFX9-NEXT:    v_or_b32_sdwa v1, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD9180; GFX9-NEXT:    v_or_b32_sdwa v2, v6, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD9181; GFX9-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD9182; GFX9-NEXT:    ; implicit-def: $vgpr99183; GFX9-NEXT:    ; implicit-def: $vgpr109184; GFX9-NEXT:    ; implicit-def: $vgpr29185; GFX9-NEXT:    ; implicit-def: $vgpr89186; GFX9-NEXT:    ; implicit-def: $vgpr49187; GFX9-NEXT:    ; implicit-def: $vgpr59188; GFX9-NEXT:    ; implicit-def: $vgpr69189; GFX9-NEXT:    ; implicit-def: $vgpr39190; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]9191; GFX9-NEXT:    s_cbranch_execz .LBB70_29192; GFX9-NEXT:  .LBB70_4: ; %cmp.true9193; GFX9-NEXT:    v_add_u16_e32 v0, 3, v99194; GFX9-NEXT:    v_add_u16_e32 v1, 3, v29195; GFX9-NEXT:    v_or_b32_sdwa v0, v10, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_09196; GFX9-NEXT:    s_movk_i32 s6, 0x3009197; GFX9-NEXT:    v_or_b32_sdwa v1, v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_09198; GFX9-NEXT:    v_add_u16_e32 v0, 0x300, v09199; GFX9-NEXT:    v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD9200; GFX9-NEXT:    v_or_b32_e32 v0, v0, v19201; GFX9-NEXT:    v_add_u16_e32 v1, 3, v49202; GFX9-NEXT:    v_add_u16_e32 v2, 3, v69203; GFX9-NEXT:    v_or_b32_sdwa v1, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_09204; GFX9-NEXT:    v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_09205; GFX9-NEXT:    v_add_u16_e32 v1, 0x300, v19206; GFX9-NEXT:    v_add_u16_sdwa v2, v2, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD9207; GFX9-NEXT:    v_or_b32_e32 v1, v1, v29208; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]9209; GFX9-NEXT:    s_setpc_b64 s[30:31]9210;9211; GFX11-TRUE16-LABEL: bitcast_v8i8_to_v2i32:9212; GFX11-TRUE16:       ; %bb.0:9213; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9214; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.h, v5.l9215; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.h, v2.l9216; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v0.l9217; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.l, 8, v1.l9218; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.h, 8, v3.l9219; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.l, 8, v5.h9220; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.h, 8, v7.l9221; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo9222; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr19223; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v89224; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s09225; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB70_39226; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow9227; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s09228; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB70_49229; GFX11-TRUE16-NEXT:  .LBB70_2: ; %end9230; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s09231; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]9232; GFX11-TRUE16-NEXT:  .LBB70_3: ; %cmp.false9233; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v5.l9234; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v4.h9235; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v4.l9236; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v6.l9237; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo169238; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_hi169239; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_lo169240; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr6_lo169241; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)9242; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v2.l9243; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v0.h, v2.h9244; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)9245; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v3.l9246; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v1.h, v3.h9247; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_lo169248; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_hi169249; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo169250; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_hi169251; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s09252; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB70_29253; GFX11-TRUE16-NEXT:  .LBB70_4: ; %cmp.true9254; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v5.l, 39255; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v4.h, 39256; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v4.l, 39257; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v6.l, 39258; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)9259; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l9260; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h9261; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)9262; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l9263; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h9264; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)9265; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v2.l, v0.l9266; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v2.h, v0.h9267; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)9268; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v3.l, v1.l9269; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v3.h, v1.h9270; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)9271; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l9272; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, 0x300, v0.h9273; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)9274; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.l9275; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, 0x300, v1.h9276; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s09277; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]9278;9279; GFX11-FAKE16-LABEL: bitcast_v8i8_to_v2i32:9280; GFX11-FAKE16:       ; %bb.0:9281; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9282; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v9, v09283; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v89284; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v8, 8, v19285; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v3, 8, v39286; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v5, 8, v59287; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v7, 8, v79288; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr19289; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo9290; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)9291; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s09292; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB70_39293; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow9294; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s09295; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB70_49296; GFX11-FAKE16-NEXT:  .LBB70_2: ; %end9297; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s09298; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]9299; GFX11-FAKE16-NEXT:  .LBB70_3: ; %cmp.false9300; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v99301; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v29302; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v49303; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v69304; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr99305; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr69306; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)9307; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v89308; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v39309; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)9310; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v59311; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v4, v79312; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr89313; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr49314; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr59315; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr79316; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)9317; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v09318; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v19319; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)9320; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v29321; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v39322; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)9323; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v19324; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v39325; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr29326; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr39327; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s09328; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB70_29329; GFX11-FAKE16-NEXT:  .LBB70_4: ; %cmp.true9330; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v9, 39331; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v2, 39332; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v4, 39333; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v6, 39334; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)9335; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v09336; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v19337; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)9338; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v29339; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v49340; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)9341; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v8, v09342; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v3, v19343; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)9344; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v5, v29345; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v7, v49346; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)9347; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v09348; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v19349; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)9350; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x300, v29351; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v39352; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)9353; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v09354; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v19355; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)9356; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v29357; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v39358; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)9359; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v19360; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v39361; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s09362; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]9363  %cmp = icmp eq i32 %b, 09364  br i1 %cmp, label %cmp.true, label %cmp.false9365 9366cmp.true:9367  %a1 = add <8 x i8> %a, splat (i8 3)9368  %a2 = bitcast <8 x i8> %a1 to <2 x i32>9369  br label %end9370 9371cmp.false:9372  %a3 = bitcast <8 x i8> %a to <2 x i32>9373  br label %end9374 9375end:9376  %phi = phi <2 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]9377  ret <2 x i32> %phi9378}9379 9380define inreg <2 x i32> @bitcast_v8i8_to_v2i32_scalar(<8 x i8> inreg %a, i32 inreg %b) {9381; SI-LABEL: bitcast_v8i8_to_v2i32_scalar:9382; SI:       ; %bb.0:9383; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9384; SI-NEXT:    s_cmp_lg_u32 s24, 09385; SI-NEXT:    s_cbranch_scc0 .LBB71_49386; SI-NEXT:  ; %bb.1: ; %cmp.false9387; SI-NEXT:    s_and_b32 s4, s16, 0xff9388; SI-NEXT:    s_lshl_b32 s5, s17, 89389; SI-NEXT:    s_or_b32 s4, s4, s59390; SI-NEXT:    s_and_b32 s5, s18, 0xff9391; SI-NEXT:    s_lshl_b32 s5, s5, 169392; SI-NEXT:    s_lshl_b32 s6, s19, 249393; SI-NEXT:    s_and_b32 s4, s4, 0xffff9394; SI-NEXT:    s_or_b32 s5, s6, s59395; SI-NEXT:    s_or_b32 s4, s4, s59396; SI-NEXT:    s_and_b32 s5, s20, 0xff9397; SI-NEXT:    s_lshl_b32 s6, s21, 89398; SI-NEXT:    s_or_b32 s5, s5, s69399; SI-NEXT:    s_and_b32 s6, s22, 0xff9400; SI-NEXT:    s_lshl_b32 s6, s6, 169401; SI-NEXT:    s_lshl_b32 s7, s23, 249402; SI-NEXT:    s_and_b32 s5, s5, 0xffff9403; SI-NEXT:    s_or_b32 s6, s7, s69404; SI-NEXT:    s_or_b32 s5, s5, s69405; SI-NEXT:    s_cbranch_execnz .LBB71_39406; SI-NEXT:  .LBB71_2: ; %cmp.true9407; SI-NEXT:    s_add_i32 s16, s16, 39408; SI-NEXT:    s_and_b32 s4, s16, 0xff9409; SI-NEXT:    s_lshl_b32 s5, s17, 89410; SI-NEXT:    s_add_i32 s18, s18, 39411; SI-NEXT:    s_or_b32 s4, s5, s49412; SI-NEXT:    s_and_b32 s6, s18, 0xff9413; SI-NEXT:    s_addk_i32 s4, 0x3009414; SI-NEXT:    s_lshl_b32 s5, s19, 249415; SI-NEXT:    s_lshl_b32 s6, s6, 169416; SI-NEXT:    s_and_b32 s4, s4, 0xffff9417; SI-NEXT:    s_or_b32 s5, s5, s69418; SI-NEXT:    s_add_i32 s20, s20, 39419; SI-NEXT:    s_or_b32 s4, s5, s49420; SI-NEXT:    s_and_b32 s5, s20, 0xff9421; SI-NEXT:    s_lshl_b32 s6, s21, 89422; SI-NEXT:    s_add_i32 s22, s22, 39423; SI-NEXT:    s_or_b32 s5, s6, s59424; SI-NEXT:    s_and_b32 s7, s22, 0xff9425; SI-NEXT:    s_addk_i32 s5, 0x3009426; SI-NEXT:    s_lshl_b32 s6, s23, 249427; SI-NEXT:    s_lshl_b32 s7, s7, 169428; SI-NEXT:    s_and_b32 s5, s5, 0xffff9429; SI-NEXT:    s_or_b32 s6, s6, s79430; SI-NEXT:    s_or_b32 s5, s6, s59431; SI-NEXT:    s_add_i32 s4, s4, 0x30000009432; SI-NEXT:    s_add_i32 s5, s5, 0x30000009433; SI-NEXT:  .LBB71_3: ; %end9434; SI-NEXT:    v_mov_b32_e32 v0, s49435; SI-NEXT:    v_mov_b32_e32 v1, s59436; SI-NEXT:    s_setpc_b64 s[30:31]9437; SI-NEXT:  .LBB71_4:9438; SI-NEXT:    ; implicit-def: $sgpr4_sgpr59439; SI-NEXT:    s_branch .LBB71_29440;9441; VI-LABEL: bitcast_v8i8_to_v2i32_scalar:9442; VI:       ; %bb.0:9443; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9444; VI-NEXT:    s_cmp_lg_u32 s24, 09445; VI-NEXT:    s_cbranch_scc0 .LBB71_49446; VI-NEXT:  ; %bb.1: ; %cmp.false9447; VI-NEXT:    s_and_b32 s4, s16, 0xff9448; VI-NEXT:    s_lshl_b32 s5, s17, 89449; VI-NEXT:    s_or_b32 s4, s4, s59450; VI-NEXT:    s_and_b32 s5, s18, 0xff9451; VI-NEXT:    s_lshl_b32 s6, s19, 89452; VI-NEXT:    s_or_b32 s5, s5, s69453; VI-NEXT:    s_and_b32 s4, s4, 0xffff9454; VI-NEXT:    s_lshl_b32 s5, s5, 169455; VI-NEXT:    s_or_b32 s4, s4, s59456; VI-NEXT:    s_and_b32 s5, s20, 0xff9457; VI-NEXT:    s_lshl_b32 s6, s21, 89458; VI-NEXT:    s_or_b32 s5, s5, s69459; VI-NEXT:    s_and_b32 s6, s22, 0xff9460; VI-NEXT:    s_lshl_b32 s7, s23, 89461; VI-NEXT:    s_or_b32 s6, s6, s79462; VI-NEXT:    s_and_b32 s5, s5, 0xffff9463; VI-NEXT:    s_lshl_b32 s6, s6, 169464; VI-NEXT:    s_or_b32 s5, s5, s69465; VI-NEXT:    s_cbranch_execnz .LBB71_39466; VI-NEXT:  .LBB71_2: ; %cmp.true9467; VI-NEXT:    s_add_i32 s16, s16, 39468; VI-NEXT:    s_and_b32 s4, s16, 0xff9469; VI-NEXT:    s_lshl_b32 s5, s17, 89470; VI-NEXT:    s_add_i32 s18, s18, 39471; VI-NEXT:    s_or_b32 s4, s5, s49472; VI-NEXT:    s_and_b32 s5, s18, 0xff9473; VI-NEXT:    s_lshl_b32 s6, s19, 89474; VI-NEXT:    s_addk_i32 s4, 0x3009475; VI-NEXT:    s_or_b32 s5, s6, s59476; VI-NEXT:    s_and_b32 s4, s4, 0xffff9477; VI-NEXT:    s_lshl_b32 s5, s5, 169478; VI-NEXT:    s_add_i32 s20, s20, 39479; VI-NEXT:    s_or_b32 s4, s5, s49480; VI-NEXT:    s_and_b32 s5, s20, 0xff9481; VI-NEXT:    s_lshl_b32 s6, s21, 89482; VI-NEXT:    s_add_i32 s22, s22, 39483; VI-NEXT:    s_or_b32 s5, s6, s59484; VI-NEXT:    s_and_b32 s6, s22, 0xff9485; VI-NEXT:    s_lshl_b32 s7, s23, 89486; VI-NEXT:    s_addk_i32 s5, 0x3009487; VI-NEXT:    s_or_b32 s6, s7, s69488; VI-NEXT:    s_and_b32 s5, s5, 0xffff9489; VI-NEXT:    s_lshl_b32 s6, s6, 169490; VI-NEXT:    s_or_b32 s5, s6, s59491; VI-NEXT:    s_add_i32 s4, s4, 0x30000009492; VI-NEXT:    s_add_i32 s5, s5, 0x30000009493; VI-NEXT:  .LBB71_3: ; %end9494; VI-NEXT:    v_mov_b32_e32 v0, s49495; VI-NEXT:    v_mov_b32_e32 v1, s59496; VI-NEXT:    s_setpc_b64 s[30:31]9497; VI-NEXT:  .LBB71_4:9498; VI-NEXT:    ; implicit-def: $sgpr4_sgpr59499; VI-NEXT:    s_branch .LBB71_29500;9501; GFX9-LABEL: bitcast_v8i8_to_v2i32_scalar:9502; GFX9:       ; %bb.0:9503; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9504; GFX9-NEXT:    s_cmp_lg_u32 s24, 09505; GFX9-NEXT:    s_cbranch_scc0 .LBB71_49506; GFX9-NEXT:  ; %bb.1: ; %cmp.false9507; GFX9-NEXT:    s_and_b32 s4, s16, 0xff9508; GFX9-NEXT:    s_lshl_b32 s5, s17, 89509; GFX9-NEXT:    s_or_b32 s4, s4, s59510; GFX9-NEXT:    s_and_b32 s5, s18, 0xff9511; GFX9-NEXT:    s_lshl_b32 s6, s19, 89512; GFX9-NEXT:    s_or_b32 s5, s5, s69513; GFX9-NEXT:    s_and_b32 s4, s4, 0xffff9514; GFX9-NEXT:    s_lshl_b32 s5, s5, 169515; GFX9-NEXT:    s_or_b32 s4, s4, s59516; GFX9-NEXT:    s_and_b32 s5, s20, 0xff9517; GFX9-NEXT:    s_lshl_b32 s6, s21, 89518; GFX9-NEXT:    s_or_b32 s5, s5, s69519; GFX9-NEXT:    s_and_b32 s6, s22, 0xff9520; GFX9-NEXT:    s_lshl_b32 s7, s23, 89521; GFX9-NEXT:    s_or_b32 s6, s6, s79522; GFX9-NEXT:    s_and_b32 s5, s5, 0xffff9523; GFX9-NEXT:    s_lshl_b32 s6, s6, 169524; GFX9-NEXT:    s_or_b32 s5, s5, s69525; GFX9-NEXT:    s_cbranch_execnz .LBB71_39526; GFX9-NEXT:  .LBB71_2: ; %cmp.true9527; GFX9-NEXT:    s_add_i32 s16, s16, 39528; GFX9-NEXT:    s_and_b32 s4, s16, 0xff9529; GFX9-NEXT:    s_lshl_b32 s5, s17, 89530; GFX9-NEXT:    s_add_i32 s18, s18, 39531; GFX9-NEXT:    s_or_b32 s4, s5, s49532; GFX9-NEXT:    s_and_b32 s5, s18, 0xff9533; GFX9-NEXT:    s_lshl_b32 s6, s19, 89534; GFX9-NEXT:    s_or_b32 s5, s6, s59535; GFX9-NEXT:    s_addk_i32 s4, 0x3009536; GFX9-NEXT:    s_addk_i32 s5, 0x3009537; GFX9-NEXT:    s_and_b32 s4, s4, 0xffff9538; GFX9-NEXT:    s_lshl_b32 s5, s5, 169539; GFX9-NEXT:    s_add_i32 s20, s20, 39540; GFX9-NEXT:    s_or_b32 s4, s4, s59541; GFX9-NEXT:    s_and_b32 s5, s20, 0xff9542; GFX9-NEXT:    s_lshl_b32 s6, s21, 89543; GFX9-NEXT:    s_add_i32 s22, s22, 39544; GFX9-NEXT:    s_or_b32 s5, s6, s59545; GFX9-NEXT:    s_and_b32 s6, s22, 0xff9546; GFX9-NEXT:    s_lshl_b32 s7, s23, 89547; GFX9-NEXT:    s_or_b32 s6, s7, s69548; GFX9-NEXT:    s_addk_i32 s5, 0x3009549; GFX9-NEXT:    s_addk_i32 s6, 0x3009550; GFX9-NEXT:    s_and_b32 s5, s5, 0xffff9551; GFX9-NEXT:    s_lshl_b32 s6, s6, 169552; GFX9-NEXT:    s_or_b32 s5, s5, s69553; GFX9-NEXT:  .LBB71_3: ; %end9554; GFX9-NEXT:    v_mov_b32_e32 v0, s49555; GFX9-NEXT:    v_mov_b32_e32 v1, s59556; GFX9-NEXT:    s_setpc_b64 s[30:31]9557; GFX9-NEXT:  .LBB71_4:9558; GFX9-NEXT:    ; implicit-def: $sgpr4_sgpr59559; GFX9-NEXT:    s_branch .LBB71_29560;9561; GFX11-LABEL: bitcast_v8i8_to_v2i32_scalar:9562; GFX11:       ; %bb.0:9563; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9564; GFX11-NEXT:    s_cmp_lg_u32 s20, 09565; GFX11-NEXT:    s_mov_b32 s6, 09566; GFX11-NEXT:    s_cbranch_scc0 .LBB71_49567; GFX11-NEXT:  ; %bb.1: ; %cmp.false9568; GFX11-NEXT:    s_and_b32 s4, s0, 0xff9569; GFX11-NEXT:    s_lshl_b32 s5, s1, 89570; GFX11-NEXT:    s_and_b32 s7, s2, 0xff9571; GFX11-NEXT:    s_lshl_b32 s8, s3, 89572; GFX11-NEXT:    s_or_b32 s4, s4, s59573; GFX11-NEXT:    s_or_b32 s5, s7, s89574; GFX11-NEXT:    s_and_b32 s7, s16, 0xff9575; GFX11-NEXT:    s_lshl_b32 s8, s17, 89576; GFX11-NEXT:    s_and_b32 s9, s18, 0xff9577; GFX11-NEXT:    s_lshl_b32 s10, s19, 89578; GFX11-NEXT:    s_or_b32 s7, s7, s89579; GFX11-NEXT:    s_or_b32 s8, s9, s109580; GFX11-NEXT:    s_and_b32 s4, s4, 0xffff9581; GFX11-NEXT:    s_lshl_b32 s5, s5, 169582; GFX11-NEXT:    s_and_b32 s7, s7, 0xffff9583; GFX11-NEXT:    s_lshl_b32 s8, s8, 169584; GFX11-NEXT:    s_or_b32 s4, s4, s59585; GFX11-NEXT:    s_or_b32 s5, s7, s89586; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s69587; GFX11-NEXT:    s_cbranch_vccnz .LBB71_39588; GFX11-NEXT:  .LBB71_2: ; %cmp.true9589; GFX11-NEXT:    s_add_i32 s0, s0, 39590; GFX11-NEXT:    s_lshl_b32 s1, s1, 89591; GFX11-NEXT:    s_and_b32 s0, s0, 0xff9592; GFX11-NEXT:    s_add_i32 s2, s2, 39593; GFX11-NEXT:    s_or_b32 s0, s1, s09594; GFX11-NEXT:    s_and_b32 s1, s2, 0xff9595; GFX11-NEXT:    s_lshl_b32 s2, s3, 89596; GFX11-NEXT:    s_add_i32 s16, s16, 39597; GFX11-NEXT:    s_add_i32 s18, s18, 39598; GFX11-NEXT:    s_or_b32 s1, s2, s19599; GFX11-NEXT:    s_and_b32 s2, s16, 0xff9600; GFX11-NEXT:    s_lshl_b32 s3, s17, 89601; GFX11-NEXT:    s_and_b32 s4, s18, 0xff9602; GFX11-NEXT:    s_lshl_b32 s5, s19, 89603; GFX11-NEXT:    s_or_b32 s2, s3, s29604; GFX11-NEXT:    s_or_b32 s3, s5, s49605; GFX11-NEXT:    s_addk_i32 s0, 0x3009606; GFX11-NEXT:    s_addk_i32 s1, 0x3009607; GFX11-NEXT:    s_addk_i32 s2, 0x3009608; GFX11-NEXT:    s_addk_i32 s3, 0x3009609; GFX11-NEXT:    s_and_b32 s0, s0, 0xffff9610; GFX11-NEXT:    s_lshl_b32 s1, s1, 169611; GFX11-NEXT:    s_and_b32 s2, s2, 0xffff9612; GFX11-NEXT:    s_lshl_b32 s3, s3, 169613; GFX11-NEXT:    s_or_b32 s4, s0, s19614; GFX11-NEXT:    s_or_b32 s5, s2, s39615; GFX11-NEXT:  .LBB71_3: ; %end9616; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)9617; GFX11-NEXT:    v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s59618; GFX11-NEXT:    s_setpc_b64 s[30:31]9619; GFX11-NEXT:  .LBB71_4:9620; GFX11-NEXT:    ; implicit-def: $sgpr4_sgpr59621; GFX11-NEXT:    s_branch .LBB71_29622  %cmp = icmp eq i32 %b, 09623  br i1 %cmp, label %cmp.true, label %cmp.false9624 9625cmp.true:9626  %a1 = add <8 x i8> %a, splat (i8 3)9627  %a2 = bitcast <8 x i8> %a1 to <2 x i32>9628  br label %end9629 9630cmp.false:9631  %a3 = bitcast <8 x i8> %a to <2 x i32>9632  br label %end9633 9634end:9635  %phi = phi <2 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]9636  ret <2 x i32> %phi9637}9638 9639define <4 x i16> @bitcast_v2f32_to_v4i16(<2 x float> %a, i32 %b) {9640; SI-LABEL: bitcast_v2f32_to_v4i16:9641; SI:       ; %bb.0:9642; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9643; SI-NEXT:    v_mov_b32_e32 v4, v19644; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v29645; SI-NEXT:    ; implicit-def: $vgpr19646; SI-NEXT:    ; implicit-def: $vgpr39647; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc9648; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]9649; SI-NEXT:  ; %bb.1: ; %cmp.false9650; SI-NEXT:    v_alignbit_b32 v1, v4, v0, 169651; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v49652; SI-NEXT:  ; %bb.2: ; %Flow9653; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]9654; SI-NEXT:  ; %bb.3: ; %cmp.true9655; SI-NEXT:    v_add_f32_e32 v4, 1.0, v49656; SI-NEXT:    v_add_f32_e32 v0, 1.0, v09657; SI-NEXT:    v_alignbit_b32 v1, v4, v0, 169658; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v49659; SI-NEXT:  ; %bb.4: ; %end9660; SI-NEXT:    s_or_b64 exec, exec, s[4:5]9661; SI-NEXT:    v_mov_b32_e32 v2, v49662; SI-NEXT:    s_setpc_b64 s[30:31]9663;9664; VI-LABEL: bitcast_v2f32_to_v4i16:9665; VI:       ; %bb.0:9666; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9667; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v29668; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc9669; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]9670; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]9671; VI-NEXT:  ; %bb.1: ; %cmp.true9672; VI-NEXT:    v_add_f32_e32 v1, 1.0, v19673; VI-NEXT:    v_add_f32_e32 v0, 1.0, v09674; VI-NEXT:  ; %bb.2: ; %end9675; VI-NEXT:    s_or_b64 exec, exec, s[4:5]9676; VI-NEXT:    s_setpc_b64 s[30:31]9677;9678; GFX9-LABEL: bitcast_v2f32_to_v4i16:9679; GFX9:       ; %bb.0:9680; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9681; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v29682; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc9683; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]9684; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]9685; GFX9-NEXT:  ; %bb.1: ; %cmp.true9686; GFX9-NEXT:    v_add_f32_e32 v1, 1.0, v19687; GFX9-NEXT:    v_add_f32_e32 v0, 1.0, v09688; GFX9-NEXT:  ; %bb.2: ; %end9689; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]9690; GFX9-NEXT:    s_setpc_b64 s[30:31]9691;9692; GFX11-LABEL: bitcast_v2f32_to_v4i16:9693; GFX11:       ; %bb.0:9694; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9695; GFX11-NEXT:    s_mov_b32 s0, exec_lo9696; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v29697; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s09698; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)9699; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s09700; GFX11-NEXT:  ; %bb.1: ; %cmp.true9701; GFX11-NEXT:    v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v09702; GFX11-NEXT:  ; %bb.2: ; %end9703; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s09704; GFX11-NEXT:    s_setpc_b64 s[30:31]9705  %cmp = icmp eq i32 %b, 09706  br i1 %cmp, label %cmp.true, label %cmp.false9707 9708cmp.true:9709  %a1 = fadd <2 x float> %a, splat (float 1.000000e+00)9710  %a2 = bitcast <2 x float> %a1 to <4 x i16>9711  br label %end9712 9713cmp.false:9714  %a3 = bitcast <2 x float> %a to <4 x i16>9715  br label %end9716 9717end:9718  %phi = phi <4 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]9719  ret <4 x i16> %phi9720}9721 9722define inreg <4 x i16> @bitcast_v2f32_to_v4i16_scalar(<2 x float> inreg %a, i32 inreg %b) {9723; SI-LABEL: bitcast_v2f32_to_v4i16_scalar:9724; SI:       ; %bb.0:9725; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9726; SI-NEXT:    s_cmp_lg_u32 s18, 09727; SI-NEXT:    s_cbranch_scc0 .LBB73_39728; SI-NEXT:  ; %bb.1: ; %cmp.false9729; SI-NEXT:    s_lshr_b32 s8, s17, 169730; SI-NEXT:    s_lshr_b64 s[4:5], s[16:17], 169731; SI-NEXT:    s_cbranch_execnz .LBB73_49732; SI-NEXT:  .LBB73_2: ; %cmp.true9733; SI-NEXT:    v_add_f32_e64 v5, s17, 1.09734; SI-NEXT:    v_add_f32_e64 v4, s16, 1.09735; SI-NEXT:    v_lshr_b64 v[1:2], v[4:5], 169736; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v59737; SI-NEXT:    s_branch .LBB73_59738; SI-NEXT:  .LBB73_3:9739; SI-NEXT:    ; implicit-def: $sgpr49740; SI-NEXT:    ; implicit-def: $sgpr89741; SI-NEXT:    s_branch .LBB73_29742; SI-NEXT:  .LBB73_4:9743; SI-NEXT:    v_mov_b32_e32 v4, s169744; SI-NEXT:    v_mov_b32_e32 v5, s179745; SI-NEXT:    v_mov_b32_e32 v3, s89746; SI-NEXT:    v_mov_b32_e32 v1, s49747; SI-NEXT:  .LBB73_5: ; %end9748; SI-NEXT:    v_mov_b32_e32 v0, v49749; SI-NEXT:    v_mov_b32_e32 v2, v59750; SI-NEXT:    s_setpc_b64 s[30:31]9751;9752; VI-LABEL: bitcast_v2f32_to_v4i16_scalar:9753; VI:       ; %bb.0:9754; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9755; VI-NEXT:    s_cmp_lg_u32 s18, 09756; VI-NEXT:    s_cbranch_scc0 .LBB73_39757; VI-NEXT:  ; %bb.1: ; %cmp.false9758; VI-NEXT:    s_cbranch_execnz .LBB73_49759; VI-NEXT:  .LBB73_2: ; %cmp.true9760; VI-NEXT:    v_add_f32_e64 v1, s17, 1.09761; VI-NEXT:    v_add_f32_e64 v0, s16, 1.09762; VI-NEXT:    s_setpc_b64 s[30:31]9763; VI-NEXT:  .LBB73_3:9764; VI-NEXT:    s_branch .LBB73_29765; VI-NEXT:  .LBB73_4:9766; VI-NEXT:    v_mov_b32_e32 v0, s169767; VI-NEXT:    v_mov_b32_e32 v1, s179768; VI-NEXT:    s_setpc_b64 s[30:31]9769;9770; GFX9-LABEL: bitcast_v2f32_to_v4i16_scalar:9771; GFX9:       ; %bb.0:9772; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9773; GFX9-NEXT:    s_cmp_lg_u32 s18, 09774; GFX9-NEXT:    s_cbranch_scc0 .LBB73_39775; GFX9-NEXT:  ; %bb.1: ; %cmp.false9776; GFX9-NEXT:    s_cbranch_execnz .LBB73_49777; GFX9-NEXT:  .LBB73_2: ; %cmp.true9778; GFX9-NEXT:    v_add_f32_e64 v1, s17, 1.09779; GFX9-NEXT:    v_add_f32_e64 v0, s16, 1.09780; GFX9-NEXT:    s_setpc_b64 s[30:31]9781; GFX9-NEXT:  .LBB73_3:9782; GFX9-NEXT:    s_branch .LBB73_29783; GFX9-NEXT:  .LBB73_4:9784; GFX9-NEXT:    v_mov_b32_e32 v0, s169785; GFX9-NEXT:    v_mov_b32_e32 v1, s179786; GFX9-NEXT:    s_setpc_b64 s[30:31]9787;9788; GFX11-LABEL: bitcast_v2f32_to_v4i16_scalar:9789; GFX11:       ; %bb.0:9790; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9791; GFX11-NEXT:    s_cmp_lg_u32 s2, 09792; GFX11-NEXT:    s_mov_b32 s2, 09793; GFX11-NEXT:    s_cbranch_scc0 .LBB73_39794; GFX11-NEXT:  ; %bb.1: ; %Flow9795; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s29796; GFX11-NEXT:    s_cbranch_vccnz .LBB73_49797; GFX11-NEXT:  .LBB73_2: ; %cmp.true9798; GFX11-NEXT:    v_add_f32_e64 v1, s1, 1.09799; GFX11-NEXT:    v_add_f32_e64 v0, s0, 1.09800; GFX11-NEXT:    s_setpc_b64 s[30:31]9801; GFX11-NEXT:  .LBB73_3:9802; GFX11-NEXT:    s_branch .LBB73_29803; GFX11-NEXT:  .LBB73_4:9804; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s19805; GFX11-NEXT:    s_setpc_b64 s[30:31]9806  %cmp = icmp eq i32 %b, 09807  br i1 %cmp, label %cmp.true, label %cmp.false9808 9809cmp.true:9810  %a1 = fadd <2 x float> %a, splat (float 1.000000e+00)9811  %a2 = bitcast <2 x float> %a1 to <4 x i16>9812  br label %end9813 9814cmp.false:9815  %a3 = bitcast <2 x float> %a to <4 x i16>9816  br label %end9817 9818end:9819  %phi = phi <4 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]9820  ret <4 x i16> %phi9821}9822 9823define <2 x float> @bitcast_v4i16_to_v2f32(<4 x i16> %a, i32 %b) {9824; SI-LABEL: bitcast_v4i16_to_v2f32:9825; SI:       ; %bb.0:9826; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9827; SI-NEXT:    v_mov_b32_e32 v5, v09828; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v49829; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v19830; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v39831; SI-NEXT:    ; implicit-def: $vgpr0_vgpr19832; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc9833; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]9834; SI-NEXT:    s_cbranch_execnz .LBB74_39835; SI-NEXT:  ; %bb.1: ; %Flow9836; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]9837; SI-NEXT:    s_cbranch_execnz .LBB74_49838; SI-NEXT:  .LBB74_2: ; %end9839; SI-NEXT:    s_or_b64 exec, exec, s[4:5]9840; SI-NEXT:    s_setpc_b64 s[30:31]9841; SI-NEXT:  .LBB74_3: ; %cmp.false9842; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v59843; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v29844; SI-NEXT:    v_or_b32_e32 v0, v0, v49845; SI-NEXT:    v_or_b32_e32 v1, v1, v39846; SI-NEXT:    ; implicit-def: $vgpr59847; SI-NEXT:    ; implicit-def: $vgpr49848; SI-NEXT:    ; implicit-def: $vgpr29849; SI-NEXT:    ; implicit-def: $vgpr39850; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]9851; SI-NEXT:    s_cbranch_execz .LBB74_29852; SI-NEXT:  .LBB74_4: ; %cmp.true9853; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v59854; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v29855; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v09856; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v19857; SI-NEXT:    v_or_b32_e32 v0, v4, v09858; SI-NEXT:    v_or_b32_e32 v1, v3, v19859; SI-NEXT:    v_add_i32_e32 v0, vcc, 0x30000, v09860; SI-NEXT:    v_add_i32_e32 v1, vcc, 0x30000, v19861; SI-NEXT:    s_or_b64 exec, exec, s[4:5]9862; SI-NEXT:    s_setpc_b64 s[30:31]9863;9864; VI-LABEL: bitcast_v4i16_to_v2f32:9865; VI:       ; %bb.0:9866; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9867; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v29868; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc9869; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]9870; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]9871; VI-NEXT:  ; %bb.1: ; %cmp.true9872; VI-NEXT:    v_mov_b32_e32 v3, 39873; VI-NEXT:    v_add_u16_e32 v2, 3, v19874; VI-NEXT:    v_add_u16_sdwa v1, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD9875; VI-NEXT:    v_or_b32_e32 v1, v2, v19876; VI-NEXT:    v_add_u16_e32 v2, 3, v09877; VI-NEXT:    v_add_u16_sdwa v0, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD9878; VI-NEXT:    v_or_b32_e32 v0, v2, v09879; VI-NEXT:  ; %bb.2: ; %end9880; VI-NEXT:    s_or_b64 exec, exec, s[4:5]9881; VI-NEXT:    s_setpc_b64 s[30:31]9882;9883; GFX9-LABEL: bitcast_v4i16_to_v2f32:9884; GFX9:       ; %bb.0:9885; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9886; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v29887; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc9888; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]9889; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]9890; GFX9-NEXT:  ; %bb.1: ; %cmp.true9891; GFX9-NEXT:    v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]9892; GFX9-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]9893; GFX9-NEXT:  ; %bb.2: ; %end9894; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]9895; GFX9-NEXT:    s_setpc_b64 s[30:31]9896;9897; GFX11-LABEL: bitcast_v4i16_to_v2f32:9898; GFX11:       ; %bb.0:9899; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9900; GFX11-NEXT:    s_mov_b32 s0, exec_lo9901; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v29902; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s09903; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)9904; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s09905; GFX11-NEXT:  ; %bb.1: ; %cmp.true9906; GFX11-NEXT:    v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]9907; GFX11-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]9908; GFX11-NEXT:  ; %bb.2: ; %end9909; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s09910; GFX11-NEXT:    s_setpc_b64 s[30:31]9911  %cmp = icmp eq i32 %b, 09912  br i1 %cmp, label %cmp.true, label %cmp.false9913 9914cmp.true:9915  %a1 = add <4 x i16> %a, splat (i16 3)9916  %a2 = bitcast <4 x i16> %a1 to <2 x float>9917  br label %end9918 9919cmp.false:9920  %a3 = bitcast <4 x i16> %a to <2 x float>9921  br label %end9922 9923end:9924  %phi = phi <2 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]9925  ret <2 x float> %phi9926}9927 9928define inreg <2 x float> @bitcast_v4i16_to_v2f32_scalar(<4 x i16> inreg %a, i32 inreg %b) {9929; SI-LABEL: bitcast_v4i16_to_v2f32_scalar:9930; SI:       ; %bb.0:9931; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9932; SI-NEXT:    s_cmp_lg_u32 s20, 09933; SI-NEXT:    s_cbranch_scc0 .LBB75_49934; SI-NEXT:  ; %bb.1: ; %cmp.false9935; SI-NEXT:    s_and_b32 s4, s16, 0xffff9936; SI-NEXT:    s_lshl_b32 s5, s17, 169937; SI-NEXT:    s_or_b32 s4, s4, s59938; SI-NEXT:    s_and_b32 s5, s18, 0xffff9939; SI-NEXT:    s_lshl_b32 s6, s19, 169940; SI-NEXT:    s_or_b32 s5, s5, s69941; SI-NEXT:    s_cbranch_execnz .LBB75_39942; SI-NEXT:  .LBB75_2: ; %cmp.true9943; SI-NEXT:    s_add_i32 s16, s16, 39944; SI-NEXT:    s_and_b32 s4, s16, 0xffff9945; SI-NEXT:    s_lshl_b32 s5, s17, 169946; SI-NEXT:    s_add_i32 s18, s18, 39947; SI-NEXT:    s_or_b32 s4, s5, s49948; SI-NEXT:    s_and_b32 s5, s18, 0xffff9949; SI-NEXT:    s_lshl_b32 s6, s19, 169950; SI-NEXT:    s_or_b32 s5, s6, s59951; SI-NEXT:    s_add_i32 s4, s4, 0x300009952; SI-NEXT:    s_add_i32 s5, s5, 0x300009953; SI-NEXT:  .LBB75_3: ; %end9954; SI-NEXT:    v_mov_b32_e32 v0, s49955; SI-NEXT:    v_mov_b32_e32 v1, s59956; SI-NEXT:    s_setpc_b64 s[30:31]9957; SI-NEXT:  .LBB75_4:9958; SI-NEXT:    ; implicit-def: $sgpr4_sgpr59959; SI-NEXT:    s_branch .LBB75_29960;9961; VI-LABEL: bitcast_v4i16_to_v2f32_scalar:9962; VI:       ; %bb.0:9963; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9964; VI-NEXT:    s_cmp_lg_u32 s18, 09965; VI-NEXT:    s_cbranch_scc0 .LBB75_49966; VI-NEXT:  ; %bb.1: ; %cmp.false9967; VI-NEXT:    s_cbranch_execnz .LBB75_39968; VI-NEXT:  .LBB75_2: ; %cmp.true9969; VI-NEXT:    s_add_i32 s5, s17, 39970; VI-NEXT:    s_and_b32 s4, s17, 0xffff00009971; VI-NEXT:    s_and_b32 s5, s5, 0xffff9972; VI-NEXT:    s_or_b32 s4, s4, s59973; VI-NEXT:    s_add_i32 s5, s16, 39974; VI-NEXT:    s_add_i32 s17, s4, 0x300009975; VI-NEXT:    s_and_b32 s4, s16, 0xffff00009976; VI-NEXT:    s_and_b32 s5, s5, 0xffff9977; VI-NEXT:    s_or_b32 s4, s4, s59978; VI-NEXT:    s_add_i32 s16, s4, 0x300009979; VI-NEXT:  .LBB75_3: ; %end9980; VI-NEXT:    v_mov_b32_e32 v0, s169981; VI-NEXT:    v_mov_b32_e32 v1, s179982; VI-NEXT:    s_setpc_b64 s[30:31]9983; VI-NEXT:  .LBB75_4:9984; VI-NEXT:    s_branch .LBB75_29985;9986; GFX9-LABEL: bitcast_v4i16_to_v2f32_scalar:9987; GFX9:       ; %bb.0:9988; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9989; GFX9-NEXT:    s_cmp_lg_u32 s18, 09990; GFX9-NEXT:    s_cbranch_scc0 .LBB75_39991; GFX9-NEXT:  ; %bb.1: ; %cmp.false9992; GFX9-NEXT:    s_cbranch_execnz .LBB75_49993; GFX9-NEXT:  .LBB75_2: ; %cmp.true9994; GFX9-NEXT:    v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]9995; GFX9-NEXT:    v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]9996; GFX9-NEXT:    s_setpc_b64 s[30:31]9997; GFX9-NEXT:  .LBB75_3:9998; GFX9-NEXT:    s_branch .LBB75_29999; GFX9-NEXT:  .LBB75_4:10000; GFX9-NEXT:    v_mov_b32_e32 v0, s1610001; GFX9-NEXT:    v_mov_b32_e32 v1, s1710002; GFX9-NEXT:    s_setpc_b64 s[30:31]10003;10004; GFX11-LABEL: bitcast_v4i16_to_v2f32_scalar:10005; GFX11:       ; %bb.0:10006; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10007; GFX11-NEXT:    s_cmp_lg_u32 s2, 010008; GFX11-NEXT:    s_mov_b32 s2, 010009; GFX11-NEXT:    s_cbranch_scc0 .LBB75_310010; GFX11-NEXT:  ; %bb.1: ; %Flow10011; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s210012; GFX11-NEXT:    s_cbranch_vccnz .LBB75_410013; GFX11-NEXT:  .LBB75_2: ; %cmp.true10014; GFX11-NEXT:    v_pk_add_u16 v1, s1, 3 op_sel_hi:[1,0]10015; GFX11-NEXT:    v_pk_add_u16 v0, s0, 3 op_sel_hi:[1,0]10016; GFX11-NEXT:    s_setpc_b64 s[30:31]10017; GFX11-NEXT:  .LBB75_3:10018; GFX11-NEXT:    s_branch .LBB75_210019; GFX11-NEXT:  .LBB75_4:10020; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s110021; GFX11-NEXT:    s_setpc_b64 s[30:31]10022  %cmp = icmp eq i32 %b, 010023  br i1 %cmp, label %cmp.true, label %cmp.false10024 10025cmp.true:10026  %a1 = add <4 x i16> %a, splat (i16 3)10027  %a2 = bitcast <4 x i16> %a1 to <2 x float>10028  br label %end10029 10030cmp.false:10031  %a3 = bitcast <4 x i16> %a to <2 x float>10032  br label %end10033 10034end:10035  %phi = phi <2 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]10036  ret <2 x float> %phi10037}10038 10039define <4 x half> @bitcast_v2f32_to_v4f16(<2 x float> %a, i32 %b) {10040; SI-LABEL: bitcast_v2f32_to_v4f16:10041; SI:       ; %bb.0:10042; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10043; SI-NEXT:    v_mov_b32_e32 v4, v110044; SI-NEXT:    v_mov_b32_e32 v5, v010045; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v210046; SI-NEXT:    ; implicit-def: $vgpr010047; SI-NEXT:    ; implicit-def: $vgpr110048; SI-NEXT:    ; implicit-def: $vgpr210049; SI-NEXT:    ; implicit-def: $vgpr310050; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc10051; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]10052; SI-NEXT:    s_cbranch_execnz .LBB76_310053; SI-NEXT:  ; %bb.1: ; %Flow10054; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]10055; SI-NEXT:    s_cbranch_execnz .LBB76_410056; SI-NEXT:  .LBB76_2: ; %end10057; SI-NEXT:    s_or_b64 exec, exec, s[4:5]10058; SI-NEXT:    s_setpc_b64 s[30:31]10059; SI-NEXT:  .LBB76_3: ; %cmp.false10060; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v410061; SI-NEXT:    v_cvt_f32_f16_e32 v3, v010062; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v510063; SI-NEXT:    v_cvt_f32_f16_e32 v1, v010064; SI-NEXT:    v_cvt_f32_f16_e32 v2, v410065; SI-NEXT:    v_cvt_f32_f16_e32 v0, v510066; SI-NEXT:    ; implicit-def: $vgpr510067; SI-NEXT:    ; implicit-def: $vgpr410068; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]10069; SI-NEXT:    s_cbranch_execz .LBB76_210070; SI-NEXT:  .LBB76_4: ; %cmp.true10071; SI-NEXT:    v_add_f32_e32 v0, 1.0, v510072; SI-NEXT:    v_add_f32_e32 v2, 1.0, v410073; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v010074; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v210075; SI-NEXT:    v_cvt_f32_f16_e32 v2, v210076; SI-NEXT:    v_cvt_f32_f16_e32 v0, v010077; SI-NEXT:    v_cvt_f32_f16_e32 v3, v310078; SI-NEXT:    v_cvt_f32_f16_e32 v1, v110079; SI-NEXT:    s_or_b64 exec, exec, s[4:5]10080; SI-NEXT:    s_setpc_b64 s[30:31]10081;10082; VI-LABEL: bitcast_v2f32_to_v4f16:10083; VI:       ; %bb.0:10084; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10085; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v210086; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc10087; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]10088; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]10089; VI-NEXT:  ; %bb.1: ; %cmp.true10090; VI-NEXT:    v_add_f32_e32 v1, 1.0, v110091; VI-NEXT:    v_add_f32_e32 v0, 1.0, v010092; VI-NEXT:  ; %bb.2: ; %end10093; VI-NEXT:    s_or_b64 exec, exec, s[4:5]10094; VI-NEXT:    s_setpc_b64 s[30:31]10095;10096; GFX9-LABEL: bitcast_v2f32_to_v4f16:10097; GFX9:       ; %bb.0:10098; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10099; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v210100; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc10101; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]10102; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]10103; GFX9-NEXT:  ; %bb.1: ; %cmp.true10104; GFX9-NEXT:    v_add_f32_e32 v1, 1.0, v110105; GFX9-NEXT:    v_add_f32_e32 v0, 1.0, v010106; GFX9-NEXT:  ; %bb.2: ; %end10107; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]10108; GFX9-NEXT:    s_setpc_b64 s[30:31]10109;10110; GFX11-LABEL: bitcast_v2f32_to_v4f16:10111; GFX11:       ; %bb.0:10112; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10113; GFX11-NEXT:    s_mov_b32 s0, exec_lo10114; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v210115; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s010116; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)10117; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s010118; GFX11-NEXT:  ; %bb.1: ; %cmp.true10119; GFX11-NEXT:    v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v010120; GFX11-NEXT:  ; %bb.2: ; %end10121; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s010122; GFX11-NEXT:    s_setpc_b64 s[30:31]10123  %cmp = icmp eq i32 %b, 010124  br i1 %cmp, label %cmp.true, label %cmp.false10125 10126cmp.true:10127  %a1 = fadd <2 x float> %a, splat (float 1.000000e+00)10128  %a2 = bitcast <2 x float> %a1 to <4 x half>10129  br label %end10130 10131cmp.false:10132  %a3 = bitcast <2 x float> %a to <4 x half>10133  br label %end10134 10135end:10136  %phi = phi <4 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]10137  ret <4 x half> %phi10138}10139 10140define inreg <4 x half> @bitcast_v2f32_to_v4f16_scalar(<2 x float> inreg %a, i32 inreg %b) {10141; SI-LABEL: bitcast_v2f32_to_v4f16_scalar:10142; SI:       ; %bb.0:10143; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10144; SI-NEXT:    s_cmp_lg_u32 s18, 010145; SI-NEXT:    s_cbranch_scc0 .LBB77_410146; SI-NEXT:  ; %bb.1: ; %cmp.false10147; SI-NEXT:    s_lshr_b32 s4, s17, 1610148; SI-NEXT:    v_cvt_f32_f16_e32 v3, s410149; SI-NEXT:    s_lshr_b32 s4, s16, 1610150; SI-NEXT:    v_cvt_f32_f16_e32 v1, s410151; SI-NEXT:    v_cvt_f32_f16_e32 v2, s1710152; SI-NEXT:    v_cvt_f32_f16_e32 v0, s1610153; SI-NEXT:    s_cbranch_execnz .LBB77_310154; SI-NEXT:  .LBB77_2: ; %cmp.true10155; SI-NEXT:    v_add_f32_e64 v0, s16, 1.010156; SI-NEXT:    v_add_f32_e64 v2, s17, 1.010157; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v010158; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v210159; SI-NEXT:    v_cvt_f32_f16_e32 v2, v210160; SI-NEXT:    v_cvt_f32_f16_e32 v0, v010161; SI-NEXT:    v_cvt_f32_f16_e32 v3, v310162; SI-NEXT:    v_cvt_f32_f16_e32 v1, v110163; SI-NEXT:  .LBB77_3: ; %end10164; SI-NEXT:    s_setpc_b64 s[30:31]10165; SI-NEXT:  .LBB77_4:10166; SI-NEXT:    ; implicit-def: $vgpr010167; SI-NEXT:    ; implicit-def: $vgpr110168; SI-NEXT:    ; implicit-def: $vgpr210169; SI-NEXT:    ; implicit-def: $vgpr310170; SI-NEXT:    s_branch .LBB77_210171;10172; VI-LABEL: bitcast_v2f32_to_v4f16_scalar:10173; VI:       ; %bb.0:10174; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10175; VI-NEXT:    s_cmp_lg_u32 s18, 010176; VI-NEXT:    s_cbranch_scc0 .LBB77_310177; VI-NEXT:  ; %bb.1: ; %cmp.false10178; VI-NEXT:    s_cbranch_execnz .LBB77_410179; VI-NEXT:  .LBB77_2: ; %cmp.true10180; VI-NEXT:    v_add_f32_e64 v1, s17, 1.010181; VI-NEXT:    v_add_f32_e64 v0, s16, 1.010182; VI-NEXT:    s_setpc_b64 s[30:31]10183; VI-NEXT:  .LBB77_3:10184; VI-NEXT:    s_branch .LBB77_210185; VI-NEXT:  .LBB77_4:10186; VI-NEXT:    v_mov_b32_e32 v0, s1610187; VI-NEXT:    v_mov_b32_e32 v1, s1710188; VI-NEXT:    s_setpc_b64 s[30:31]10189;10190; GFX9-LABEL: bitcast_v2f32_to_v4f16_scalar:10191; GFX9:       ; %bb.0:10192; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10193; GFX9-NEXT:    s_cmp_lg_u32 s18, 010194; GFX9-NEXT:    s_cbranch_scc0 .LBB77_310195; GFX9-NEXT:  ; %bb.1: ; %cmp.false10196; GFX9-NEXT:    s_cbranch_execnz .LBB77_410197; GFX9-NEXT:  .LBB77_2: ; %cmp.true10198; GFX9-NEXT:    v_add_f32_e64 v1, s17, 1.010199; GFX9-NEXT:    v_add_f32_e64 v0, s16, 1.010200; GFX9-NEXT:    s_setpc_b64 s[30:31]10201; GFX9-NEXT:  .LBB77_3:10202; GFX9-NEXT:    s_branch .LBB77_210203; GFX9-NEXT:  .LBB77_4:10204; GFX9-NEXT:    v_mov_b32_e32 v0, s1610205; GFX9-NEXT:    v_mov_b32_e32 v1, s1710206; GFX9-NEXT:    s_setpc_b64 s[30:31]10207;10208; GFX11-LABEL: bitcast_v2f32_to_v4f16_scalar:10209; GFX11:       ; %bb.0:10210; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10211; GFX11-NEXT:    s_cmp_lg_u32 s2, 010212; GFX11-NEXT:    s_mov_b32 s2, 010213; GFX11-NEXT:    s_cbranch_scc0 .LBB77_310214; GFX11-NEXT:  ; %bb.1: ; %Flow10215; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s210216; GFX11-NEXT:    s_cbranch_vccnz .LBB77_410217; GFX11-NEXT:  .LBB77_2: ; %cmp.true10218; GFX11-NEXT:    v_add_f32_e64 v1, s1, 1.010219; GFX11-NEXT:    v_add_f32_e64 v0, s0, 1.010220; GFX11-NEXT:    s_setpc_b64 s[30:31]10221; GFX11-NEXT:  .LBB77_3:10222; GFX11-NEXT:    s_branch .LBB77_210223; GFX11-NEXT:  .LBB77_4:10224; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s110225; GFX11-NEXT:    s_setpc_b64 s[30:31]10226  %cmp = icmp eq i32 %b, 010227  br i1 %cmp, label %cmp.true, label %cmp.false10228 10229cmp.true:10230  %a1 = fadd <2 x float> %a, splat (float 1.000000e+00)10231  %a2 = bitcast <2 x float> %a1 to <4 x half>10232  br label %end10233 10234cmp.false:10235  %a3 = bitcast <2 x float> %a to <4 x half>10236  br label %end10237 10238end:10239  %phi = phi <4 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]10240  ret <4 x half> %phi10241}10242 10243define <2 x float> @bitcast_v4f16_to_v2f32(<4 x half> %a, i32 %b) {10244; SI-LABEL: bitcast_v4f16_to_v2f32:10245; SI:       ; %bb.0:10246; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10247; SI-NEXT:    v_cvt_f16_f32_e32 v6, v110248; SI-NEXT:    v_cvt_f16_f32_e32 v5, v010249; SI-NEXT:    v_cvt_f16_f32_e32 v3, v310250; SI-NEXT:    v_cvt_f16_f32_e32 v2, v210251; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v410252; SI-NEXT:    ; implicit-def: $vgpr0_vgpr110253; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc10254; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]10255; SI-NEXT:    s_cbranch_execnz .LBB78_310256; SI-NEXT:  ; %bb.1: ; %Flow10257; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]10258; SI-NEXT:    s_cbranch_execnz .LBB78_410259; SI-NEXT:  .LBB78_2: ; %end10260; SI-NEXT:    s_or_b64 exec, exec, s[4:5]10261; SI-NEXT:    s_setpc_b64 s[30:31]10262; SI-NEXT:  .LBB78_3: ; %cmp.false10263; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v610264; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v310265; SI-NEXT:    v_or_b32_e32 v0, v5, v010266; SI-NEXT:    v_or_b32_e32 v1, v2, v110267; SI-NEXT:    ; implicit-def: $vgpr610268; SI-NEXT:    ; implicit-def: $vgpr510269; SI-NEXT:    ; implicit-def: $vgpr310270; SI-NEXT:    ; implicit-def: $vgpr210271; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]10272; SI-NEXT:    s_cbranch_execz .LBB78_210273; SI-NEXT:  .LBB78_4: ; %cmp.true10274; SI-NEXT:    v_cvt_f32_f16_e32 v0, v610275; SI-NEXT:    v_cvt_f32_f16_e32 v1, v510276; SI-NEXT:    v_cvt_f32_f16_e32 v3, v310277; SI-NEXT:    v_cvt_f32_f16_e32 v2, v210278; SI-NEXT:    v_add_f32_e32 v0, 0x38000000, v010279; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v110280; SI-NEXT:    v_cvt_f16_f32_e32 v0, v010281; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v310282; SI-NEXT:    v_cvt_f16_f32_e32 v1, v110283; SI-NEXT:    v_cvt_f16_f32_e32 v3, v310284; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v210285; SI-NEXT:    v_cvt_f16_f32_e32 v2, v210286; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v010287; SI-NEXT:    v_or_b32_e32 v0, v1, v010288; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v310289; SI-NEXT:    v_or_b32_e32 v1, v2, v110290; SI-NEXT:    s_or_b64 exec, exec, s[4:5]10291; SI-NEXT:    s_setpc_b64 s[30:31]10292;10293; VI-LABEL: bitcast_v4f16_to_v2f32:10294; VI:       ; %bb.0:10295; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10296; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v210297; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc10298; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]10299; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]10300; VI-NEXT:  ; %bb.1: ; %cmp.true10301; VI-NEXT:    v_mov_b32_e32 v2, 0x20010302; VI-NEXT:    v_add_f16_sdwa v3, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD10303; VI-NEXT:    v_add_f16_e32 v1, 0x200, v110304; VI-NEXT:    v_add_f16_sdwa v2, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD10305; VI-NEXT:    v_add_f16_e32 v0, 0x200, v010306; VI-NEXT:    v_or_b32_e32 v1, v1, v310307; VI-NEXT:    v_or_b32_e32 v0, v0, v210308; VI-NEXT:  ; %bb.2: ; %end10309; VI-NEXT:    s_or_b64 exec, exec, s[4:5]10310; VI-NEXT:    s_setpc_b64 s[30:31]10311;10312; GFX9-LABEL: bitcast_v4f16_to_v2f32:10313; GFX9:       ; %bb.0:10314; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10315; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v210316; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc10317; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]10318; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]10319; GFX9-NEXT:  ; %bb.1: ; %cmp.true10320; GFX9-NEXT:    s_movk_i32 s6, 0x20010321; GFX9-NEXT:    v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]10322; GFX9-NEXT:    v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]10323; GFX9-NEXT:  ; %bb.2: ; %end10324; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]10325; GFX9-NEXT:    s_setpc_b64 s[30:31]10326;10327; GFX11-LABEL: bitcast_v4f16_to_v2f32:10328; GFX11:       ; %bb.0:10329; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10330; GFX11-NEXT:    s_mov_b32 s0, exec_lo10331; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v210332; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s010333; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)10334; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s010335; GFX11-NEXT:  ; %bb.1: ; %cmp.true10336; GFX11-NEXT:    v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]10337; GFX11-NEXT:    v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]10338; GFX11-NEXT:  ; %bb.2: ; %end10339; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s010340; GFX11-NEXT:    s_setpc_b64 s[30:31]10341  %cmp = icmp eq i32 %b, 010342  br i1 %cmp, label %cmp.true, label %cmp.false10343 10344cmp.true:10345  %a1 = fadd <4 x half> %a, splat (half 0xH0200)10346  %a2 = bitcast <4 x half> %a1 to <2 x float>10347  br label %end10348 10349cmp.false:10350  %a3 = bitcast <4 x half> %a to <2 x float>10351  br label %end10352 10353end:10354  %phi = phi <2 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]10355  ret <2 x float> %phi10356}10357 10358define inreg <2 x float> @bitcast_v4f16_to_v2f32_scalar(<4 x half> inreg %a, i32 inreg %b) {10359; SI-LABEL: bitcast_v4f16_to_v2f32_scalar:10360; SI:       ; %bb.0:10361; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10362; SI-NEXT:    v_cvt_f16_f32_e32 v5, s1710363; SI-NEXT:    v_cvt_f16_f32_e32 v4, s1610364; SI-NEXT:    v_cvt_f16_f32_e32 v3, s1910365; SI-NEXT:    v_cvt_f16_f32_e32 v2, s1810366; SI-NEXT:    s_cmp_lg_u32 s20, 010367; SI-NEXT:    s_cbranch_scc0 .LBB79_410368; SI-NEXT:  ; %bb.1: ; %cmp.false10369; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v510370; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v310371; SI-NEXT:    v_or_b32_e32 v0, v4, v010372; SI-NEXT:    v_or_b32_e32 v1, v2, v110373; SI-NEXT:    s_cbranch_execnz .LBB79_310374; SI-NEXT:  .LBB79_2: ; %cmp.true10375; SI-NEXT:    v_cvt_f32_f16_e32 v0, v510376; SI-NEXT:    v_cvt_f32_f16_e32 v1, v410377; SI-NEXT:    v_cvt_f32_f16_e32 v3, v310378; SI-NEXT:    v_cvt_f32_f16_e32 v2, v210379; SI-NEXT:    v_add_f32_e32 v0, 0x38000000, v010380; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v110381; SI-NEXT:    v_cvt_f16_f32_e32 v0, v010382; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v310383; SI-NEXT:    v_cvt_f16_f32_e32 v1, v110384; SI-NEXT:    v_cvt_f16_f32_e32 v3, v310385; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v210386; SI-NEXT:    v_cvt_f16_f32_e32 v2, v210387; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v010388; SI-NEXT:    v_or_b32_e32 v0, v1, v010389; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v310390; SI-NEXT:    v_or_b32_e32 v1, v2, v110391; SI-NEXT:  .LBB79_3: ; %end10392; SI-NEXT:    s_setpc_b64 s[30:31]10393; SI-NEXT:  .LBB79_4:10394; SI-NEXT:    ; implicit-def: $vgpr0_vgpr110395; SI-NEXT:    s_branch .LBB79_210396;10397; VI-LABEL: bitcast_v4f16_to_v2f32_scalar:10398; VI:       ; %bb.0:10399; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10400; VI-NEXT:    s_cmp_lg_u32 s18, 010401; VI-NEXT:    s_cbranch_scc0 .LBB79_310402; VI-NEXT:  ; %bb.1: ; %cmp.false10403; VI-NEXT:    s_cbranch_execnz .LBB79_410404; VI-NEXT:  .LBB79_2: ; %cmp.true10405; VI-NEXT:    s_lshr_b32 s4, s17, 1610406; VI-NEXT:    v_mov_b32_e32 v0, 0x20010407; VI-NEXT:    v_mov_b32_e32 v1, s410408; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD10409; VI-NEXT:    v_add_f16_e32 v2, s17, v010410; VI-NEXT:    s_lshr_b32 s4, s16, 1610411; VI-NEXT:    v_or_b32_e32 v1, v2, v110412; VI-NEXT:    v_mov_b32_e32 v2, s410413; VI-NEXT:    v_add_f16_sdwa v2, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD10414; VI-NEXT:    v_add_f16_e32 v0, s16, v010415; VI-NEXT:    v_or_b32_e32 v0, v0, v210416; VI-NEXT:    s_setpc_b64 s[30:31]10417; VI-NEXT:  .LBB79_3:10418; VI-NEXT:    s_branch .LBB79_210419; VI-NEXT:  .LBB79_4:10420; VI-NEXT:    v_mov_b32_e32 v0, s1610421; VI-NEXT:    v_mov_b32_e32 v1, s1710422; VI-NEXT:    s_setpc_b64 s[30:31]10423;10424; GFX9-LABEL: bitcast_v4f16_to_v2f32_scalar:10425; GFX9:       ; %bb.0:10426; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10427; GFX9-NEXT:    s_cmp_lg_u32 s18, 010428; GFX9-NEXT:    s_cbranch_scc0 .LBB79_310429; GFX9-NEXT:  ; %bb.1: ; %cmp.false10430; GFX9-NEXT:    s_cbranch_execnz .LBB79_410431; GFX9-NEXT:  .LBB79_2: ; %cmp.true10432; GFX9-NEXT:    v_mov_b32_e32 v0, 0x20010433; GFX9-NEXT:    v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]10434; GFX9-NEXT:    v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]10435; GFX9-NEXT:    s_setpc_b64 s[30:31]10436; GFX9-NEXT:  .LBB79_3:10437; GFX9-NEXT:    s_branch .LBB79_210438; GFX9-NEXT:  .LBB79_4:10439; GFX9-NEXT:    v_mov_b32_e32 v0, s1610440; GFX9-NEXT:    v_mov_b32_e32 v1, s1710441; GFX9-NEXT:    s_setpc_b64 s[30:31]10442;10443; GFX11-LABEL: bitcast_v4f16_to_v2f32_scalar:10444; GFX11:       ; %bb.0:10445; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10446; GFX11-NEXT:    s_cmp_lg_u32 s2, 010447; GFX11-NEXT:    s_mov_b32 s2, 010448; GFX11-NEXT:    s_cbranch_scc0 .LBB79_310449; GFX11-NEXT:  ; %bb.1: ; %Flow10450; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s210451; GFX11-NEXT:    s_cbranch_vccnz .LBB79_410452; GFX11-NEXT:  .LBB79_2: ; %cmp.true10453; GFX11-NEXT:    v_pk_add_f16 v1, 0x200, s1 op_sel_hi:[0,1]10454; GFX11-NEXT:    v_pk_add_f16 v0, 0x200, s0 op_sel_hi:[0,1]10455; GFX11-NEXT:    s_setpc_b64 s[30:31]10456; GFX11-NEXT:  .LBB79_3:10457; GFX11-NEXT:    s_branch .LBB79_210458; GFX11-NEXT:  .LBB79_4:10459; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s110460; GFX11-NEXT:    s_setpc_b64 s[30:31]10461  %cmp = icmp eq i32 %b, 010462  br i1 %cmp, label %cmp.true, label %cmp.false10463 10464cmp.true:10465  %a1 = fadd <4 x half> %a, splat (half 0xH0200)10466  %a2 = bitcast <4 x half> %a1 to <2 x float>10467  br label %end10468 10469cmp.false:10470  %a3 = bitcast <4 x half> %a to <2 x float>10471  br label %end10472 10473end:10474  %phi = phi <2 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]10475  ret <2 x float> %phi10476}10477 10478define <4 x bfloat> @bitcast_v2f32_to_v4bf16(<2 x float> %a, i32 %b) {10479; SI-LABEL: bitcast_v2f32_to_v4bf16:10480; SI:       ; %bb.0:10481; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10482; SI-NEXT:    v_mov_b32_e32 v5, v110483; SI-NEXT:    v_mov_b32_e32 v4, v010484; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v210485; SI-NEXT:    ; implicit-def: $vgpr010486; SI-NEXT:    ; implicit-def: $vgpr110487; SI-NEXT:    ; implicit-def: $vgpr210488; SI-NEXT:    ; implicit-def: $vgpr310489; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc10490; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]10491; SI-NEXT:    s_cbranch_execnz .LBB80_310492; SI-NEXT:  ; %bb.1: ; %Flow10493; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]10494; SI-NEXT:    s_cbranch_execnz .LBB80_410495; SI-NEXT:  .LBB80_2: ; %end10496; SI-NEXT:    s_or_b64 exec, exec, s[4:5]10497; SI-NEXT:    s_setpc_b64 s[30:31]10498; SI-NEXT:  .LBB80_3: ; %cmp.false10499; SI-NEXT:    v_and_b32_e32 v3, 0xffff0000, v510500; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v510501; SI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v410502; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v410503; SI-NEXT:    ; implicit-def: $vgpr410504; SI-NEXT:    ; implicit-def: $vgpr510505; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]10506; SI-NEXT:    s_cbranch_execz .LBB80_210507; SI-NEXT:  .LBB80_4: ; %cmp.true10508; SI-NEXT:    v_add_f32_e32 v0, 1.0, v410509; SI-NEXT:    v_add_f32_e32 v1, 1.0, v510510; SI-NEXT:    v_and_b32_e32 v3, 0xffff0000, v110511; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v110512; SI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v010513; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v010514; SI-NEXT:    s_or_b64 exec, exec, s[4:5]10515; SI-NEXT:    s_setpc_b64 s[30:31]10516;10517; VI-LABEL: bitcast_v2f32_to_v4bf16:10518; VI:       ; %bb.0:10519; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10520; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v210521; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc10522; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]10523; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]10524; VI-NEXT:  ; %bb.1: ; %cmp.true10525; VI-NEXT:    v_add_f32_e32 v1, 1.0, v110526; VI-NEXT:    v_add_f32_e32 v0, 1.0, v010527; VI-NEXT:  ; %bb.2: ; %end10528; VI-NEXT:    s_or_b64 exec, exec, s[4:5]10529; VI-NEXT:    s_setpc_b64 s[30:31]10530;10531; GFX9-LABEL: bitcast_v2f32_to_v4bf16:10532; GFX9:       ; %bb.0:10533; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10534; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v210535; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc10536; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]10537; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]10538; GFX9-NEXT:  ; %bb.1: ; %cmp.true10539; GFX9-NEXT:    v_add_f32_e32 v1, 1.0, v110540; GFX9-NEXT:    v_add_f32_e32 v0, 1.0, v010541; GFX9-NEXT:  ; %bb.2: ; %end10542; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]10543; GFX9-NEXT:    s_setpc_b64 s[30:31]10544;10545; GFX11-LABEL: bitcast_v2f32_to_v4bf16:10546; GFX11:       ; %bb.0:10547; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10548; GFX11-NEXT:    s_mov_b32 s0, exec_lo10549; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v210550; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s010551; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)10552; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s010553; GFX11-NEXT:  ; %bb.1: ; %cmp.true10554; GFX11-NEXT:    v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v010555; GFX11-NEXT:  ; %bb.2: ; %end10556; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s010557; GFX11-NEXT:    s_setpc_b64 s[30:31]10558  %cmp = icmp eq i32 %b, 010559  br i1 %cmp, label %cmp.true, label %cmp.false10560 10561cmp.true:10562  %a1 = fadd <2 x float> %a, splat (float 1.000000e+00)10563  %a2 = bitcast <2 x float> %a1 to <4 x bfloat>10564  br label %end10565 10566cmp.false:10567  %a3 = bitcast <2 x float> %a to <4 x bfloat>10568  br label %end10569 10570end:10571  %phi = phi <4 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ]10572  ret <4 x bfloat> %phi10573}10574 10575define inreg <4 x bfloat> @bitcast_v2f32_to_v4bf16_scalar(<2 x float> inreg %a, i32 inreg %b) {10576; SI-LABEL: bitcast_v2f32_to_v4bf16_scalar:10577; SI:       ; %bb.0:10578; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10579; SI-NEXT:    s_cmp_lg_u32 s18, 010580; SI-NEXT:    s_cbranch_scc0 .LBB81_310581; SI-NEXT:  ; %bb.1: ; %cmp.false10582; SI-NEXT:    s_and_b32 s6, s17, 0xffff000010583; SI-NEXT:    s_lshl_b32 s7, s17, 1610584; SI-NEXT:    s_and_b32 s8, s16, 0xffff000010585; SI-NEXT:    s_lshl_b32 s9, s16, 1610586; SI-NEXT:    s_cbranch_execnz .LBB81_410587; SI-NEXT:  .LBB81_2: ; %cmp.true10588; SI-NEXT:    v_add_f32_e64 v0, s16, 1.010589; SI-NEXT:    v_add_f32_e64 v1, s17, 1.010590; SI-NEXT:    v_and_b32_e32 v3, 0xffff0000, v110591; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v110592; SI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v010593; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v010594; SI-NEXT:    s_setpc_b64 s[30:31]10595; SI-NEXT:  .LBB81_3:10596; SI-NEXT:    ; implicit-def: $sgpr910597; SI-NEXT:    ; implicit-def: $sgpr810598; SI-NEXT:    ; implicit-def: $sgpr710599; SI-NEXT:    ; implicit-def: $sgpr610600; SI-NEXT:    s_branch .LBB81_210601; SI-NEXT:  .LBB81_4:10602; SI-NEXT:    v_mov_b32_e32 v0, s910603; SI-NEXT:    v_mov_b32_e32 v1, s810604; SI-NEXT:    v_mov_b32_e32 v2, s710605; SI-NEXT:    v_mov_b32_e32 v3, s610606; SI-NEXT:    s_setpc_b64 s[30:31]10607;10608; VI-LABEL: bitcast_v2f32_to_v4bf16_scalar:10609; VI:       ; %bb.0:10610; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10611; VI-NEXT:    s_cmp_lg_u32 s18, 010612; VI-NEXT:    s_cbranch_scc0 .LBB81_310613; VI-NEXT:  ; %bb.1: ; %cmp.false10614; VI-NEXT:    s_cbranch_execnz .LBB81_410615; VI-NEXT:  .LBB81_2: ; %cmp.true10616; VI-NEXT:    v_add_f32_e64 v1, s17, 1.010617; VI-NEXT:    v_add_f32_e64 v0, s16, 1.010618; VI-NEXT:    s_setpc_b64 s[30:31]10619; VI-NEXT:  .LBB81_3:10620; VI-NEXT:    s_branch .LBB81_210621; VI-NEXT:  .LBB81_4:10622; VI-NEXT:    v_mov_b32_e32 v0, s1610623; VI-NEXT:    v_mov_b32_e32 v1, s1710624; VI-NEXT:    s_setpc_b64 s[30:31]10625;10626; GFX9-LABEL: bitcast_v2f32_to_v4bf16_scalar:10627; GFX9:       ; %bb.0:10628; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10629; GFX9-NEXT:    s_cmp_lg_u32 s18, 010630; GFX9-NEXT:    s_cbranch_scc0 .LBB81_310631; GFX9-NEXT:  ; %bb.1: ; %cmp.false10632; GFX9-NEXT:    s_cbranch_execnz .LBB81_410633; GFX9-NEXT:  .LBB81_2: ; %cmp.true10634; GFX9-NEXT:    v_add_f32_e64 v1, s17, 1.010635; GFX9-NEXT:    v_add_f32_e64 v0, s16, 1.010636; GFX9-NEXT:    s_setpc_b64 s[30:31]10637; GFX9-NEXT:  .LBB81_3:10638; GFX9-NEXT:    s_branch .LBB81_210639; GFX9-NEXT:  .LBB81_4:10640; GFX9-NEXT:    v_mov_b32_e32 v0, s1610641; GFX9-NEXT:    v_mov_b32_e32 v1, s1710642; GFX9-NEXT:    s_setpc_b64 s[30:31]10643;10644; GFX11-LABEL: bitcast_v2f32_to_v4bf16_scalar:10645; GFX11:       ; %bb.0:10646; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10647; GFX11-NEXT:    s_cmp_lg_u32 s2, 010648; GFX11-NEXT:    s_mov_b32 s2, 010649; GFX11-NEXT:    s_cbranch_scc0 .LBB81_310650; GFX11-NEXT:  ; %bb.1: ; %Flow10651; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s210652; GFX11-NEXT:    s_cbranch_vccnz .LBB81_410653; GFX11-NEXT:  .LBB81_2: ; %cmp.true10654; GFX11-NEXT:    v_add_f32_e64 v1, s1, 1.010655; GFX11-NEXT:    v_add_f32_e64 v0, s0, 1.010656; GFX11-NEXT:    s_setpc_b64 s[30:31]10657; GFX11-NEXT:  .LBB81_3:10658; GFX11-NEXT:    s_branch .LBB81_210659; GFX11-NEXT:  .LBB81_4:10660; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s110661; GFX11-NEXT:    s_setpc_b64 s[30:31]10662  %cmp = icmp eq i32 %b, 010663  br i1 %cmp, label %cmp.true, label %cmp.false10664 10665cmp.true:10666  %a1 = fadd <2 x float> %a, splat (float 1.000000e+00)10667  %a2 = bitcast <2 x float> %a1 to <4 x bfloat>10668  br label %end10669 10670cmp.false:10671  %a3 = bitcast <2 x float> %a to <4 x bfloat>10672  br label %end10673 10674end:10675  %phi = phi <4 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ]10676  ret <4 x bfloat> %phi10677}10678 10679define <2 x float> @bitcast_v4bf16_to_v2f32(<4 x bfloat> %a, i32 %b) {10680; SI-LABEL: bitcast_v4bf16_to_v2f32:10681; SI:       ; %bb.0:10682; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10683; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v410684; SI-NEXT:    v_mul_f32_e32 v4, 1.0, v110685; SI-NEXT:    v_mul_f32_e32 v5, 1.0, v010686; SI-NEXT:    v_mul_f32_e32 v3, 1.0, v310687; SI-NEXT:    v_mul_f32_e32 v2, 1.0, v210688; SI-NEXT:    ; implicit-def: $vgpr0_vgpr110689; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc10690; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]10691; SI-NEXT:    s_cbranch_execnz .LBB82_310692; SI-NEXT:  ; %bb.1: ; %Flow10693; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]10694; SI-NEXT:    s_cbranch_execnz .LBB82_410695; SI-NEXT:  .LBB82_2: ; %end10696; SI-NEXT:    s_or_b64 exec, exec, s[4:5]10697; SI-NEXT:    s_setpc_b64 s[30:31]10698; SI-NEXT:  .LBB82_3: ; %cmp.false10699; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v410700; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v310701; SI-NEXT:    v_alignbit_b32 v0, v0, v5, 1610702; SI-NEXT:    v_alignbit_b32 v1, v1, v2, 1610703; SI-NEXT:    ; implicit-def: $vgpr510704; SI-NEXT:    ; implicit-def: $vgpr410705; SI-NEXT:    ; implicit-def: $vgpr210706; SI-NEXT:    ; implicit-def: $vgpr310707; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]10708; SI-NEXT:    s_cbranch_execz .LBB82_210709; SI-NEXT:  .LBB82_4: ; %cmp.true10710; SI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v410711; SI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v510712; SI-NEXT:    v_add_f32_e32 v1, 0x40c00000, v110713; SI-NEXT:    v_add_f32_e32 v0, 0x40c00000, v010714; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v110715; SI-NEXT:    v_alignbit_b32 v0, v1, v0, 1610716; SI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v210717; SI-NEXT:    v_and_b32_e32 v2, 0xffff0000, v310718; SI-NEXT:    v_add_f32_e32 v2, 0x40c00000, v210719; SI-NEXT:    v_add_f32_e32 v1, 0x40c00000, v110720; SI-NEXT:    v_lshrrev_b32_e32 v2, 16, v210721; SI-NEXT:    v_alignbit_b32 v1, v2, v1, 1610722; SI-NEXT:    s_or_b64 exec, exec, s[4:5]10723; SI-NEXT:    s_setpc_b64 s[30:31]10724;10725; VI-LABEL: bitcast_v4bf16_to_v2f32:10726; VI:       ; %bb.0:10727; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10728; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v210729; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc10730; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]10731; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]10732; VI-NEXT:    s_cbranch_execz .LBB82_210733; VI-NEXT:  ; %bb.1: ; %cmp.true10734; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v110735; VI-NEXT:    v_add_f32_e32 v2, 0x40c00000, v210736; VI-NEXT:    v_bfe_u32 v3, v2, 16, 110737; VI-NEXT:    v_add_u32_e32 v3, vcc, v3, v210738; VI-NEXT:    v_add_u32_e32 v3, vcc, 0x7fff, v310739; VI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v110740; VI-NEXT:    v_or_b32_e32 v4, 0x400000, v210741; VI-NEXT:    v_cmp_u_f32_e32 vcc, v2, v210742; VI-NEXT:    v_add_f32_e32 v1, 0x40c00000, v110743; VI-NEXT:    v_cndmask_b32_e32 v2, v3, v4, vcc10744; VI-NEXT:    v_bfe_u32 v3, v1, 16, 110745; VI-NEXT:    s_movk_i32 s6, 0x7fff10746; VI-NEXT:    v_add_u32_e32 v3, vcc, v3, v110747; VI-NEXT:    v_add_u32_e32 v3, vcc, s6, v310748; VI-NEXT:    v_or_b32_e32 v4, 0x400000, v110749; VI-NEXT:    v_cmp_u_f32_e32 vcc, v1, v110750; VI-NEXT:    v_cndmask_b32_e32 v1, v3, v4, vcc10751; VI-NEXT:    v_lshrrev_b32_e32 v1, 16, v110752; VI-NEXT:    v_alignbit_b32 v1, v1, v2, 1610753; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v010754; VI-NEXT:    v_add_f32_e32 v2, 0x40c00000, v210755; VI-NEXT:    v_bfe_u32 v3, v2, 16, 110756; VI-NEXT:    v_add_u32_e32 v3, vcc, v3, v210757; VI-NEXT:    v_add_u32_e32 v3, vcc, s6, v310758; VI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v010759; VI-NEXT:    v_or_b32_e32 v4, 0x400000, v210760; VI-NEXT:    v_cmp_u_f32_e32 vcc, v2, v210761; VI-NEXT:    v_add_f32_e32 v0, 0x40c00000, v010762; VI-NEXT:    v_cndmask_b32_e32 v2, v3, v4, vcc10763; VI-NEXT:    v_bfe_u32 v3, v0, 16, 110764; VI-NEXT:    v_add_u32_e32 v3, vcc, v3, v010765; VI-NEXT:    v_add_u32_e32 v3, vcc, 0x7fff, v310766; VI-NEXT:    v_or_b32_e32 v4, 0x400000, v010767; VI-NEXT:    v_cmp_u_f32_e32 vcc, v0, v010768; VI-NEXT:    v_cndmask_b32_e32 v0, v3, v4, vcc10769; VI-NEXT:    v_lshrrev_b32_e32 v0, 16, v010770; VI-NEXT:    v_alignbit_b32 v0, v0, v2, 1610771; VI-NEXT:  .LBB82_2: ; %end10772; VI-NEXT:    s_or_b64 exec, exec, s[4:5]10773; VI-NEXT:    s_setpc_b64 s[30:31]10774;10775; GFX9-LABEL: bitcast_v4bf16_to_v2f32:10776; GFX9:       ; %bb.0:10777; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10778; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v210779; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc10780; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]10781; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]10782; GFX9-NEXT:    s_cbranch_execz .LBB82_210783; GFX9-NEXT:  ; %bb.1: ; %cmp.true10784; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 16, v010785; GFX9-NEXT:    v_add_f32_e32 v2, 0x40c00000, v210786; GFX9-NEXT:    v_bfe_u32 v3, v2, 16, 110787; GFX9-NEXT:    s_movk_i32 s6, 0x7fff10788; GFX9-NEXT:    v_and_b32_e32 v0, 0xffff0000, v010789; GFX9-NEXT:    v_add3_u32 v3, v3, v2, s610790; GFX9-NEXT:    v_or_b32_e32 v4, 0x400000, v210791; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v2, v210792; GFX9-NEXT:    v_add_f32_e32 v0, 0x40c00000, v010793; GFX9-NEXT:    v_cndmask_b32_e32 v2, v3, v4, vcc10794; GFX9-NEXT:    v_bfe_u32 v3, v0, 16, 110795; GFX9-NEXT:    v_add3_u32 v3, v3, v0, s610796; GFX9-NEXT:    v_or_b32_e32 v4, 0x400000, v010797; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v0, v010798; GFX9-NEXT:    v_cndmask_b32_e32 v0, v3, v4, vcc10799; GFX9-NEXT:    s_mov_b32 s7, 0x706030210800; GFX9-NEXT:    v_perm_b32 v0, v0, v2, s710801; GFX9-NEXT:    v_and_b32_e32 v2, 0xffff0000, v110802; GFX9-NEXT:    v_add_f32_e32 v2, 0x40c00000, v210803; GFX9-NEXT:    v_bfe_u32 v3, v2, 16, 110804; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 16, v110805; GFX9-NEXT:    v_add3_u32 v3, v3, v2, s610806; GFX9-NEXT:    v_or_b32_e32 v4, 0x400000, v210807; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v2, v210808; GFX9-NEXT:    v_add_f32_e32 v1, 0x40c00000, v110809; GFX9-NEXT:    v_cndmask_b32_e32 v2, v3, v4, vcc10810; GFX9-NEXT:    v_bfe_u32 v3, v1, 16, 110811; GFX9-NEXT:    v_add3_u32 v3, v3, v1, s610812; GFX9-NEXT:    v_or_b32_e32 v4, 0x400000, v110813; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v1, v110814; GFX9-NEXT:    v_cndmask_b32_e32 v1, v3, v4, vcc10815; GFX9-NEXT:    v_perm_b32 v1, v2, v1, s710816; GFX9-NEXT:  .LBB82_2: ; %end10817; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]10818; GFX9-NEXT:    s_setpc_b64 s[30:31]10819;10820; GFX11-TRUE16-LABEL: bitcast_v4bf16_to_v2f32:10821; GFX11-TRUE16:       ; %bb.0:10822; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10823; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v210824; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_vgpr310825; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo10826; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)10827; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s010828; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false10829; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v010830; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr010831; GFX11-TRUE16-NEXT:  ; %bb.2: ; %Flow10832; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s010833; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB82_410834; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true10835; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, 010836; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.h, v0.l10837; GFX11-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v010838; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v110839; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)10840; GFX11-TRUE16-NEXT:    v_add_f32_e32 v4, 0x40c00000, v310841; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.h, v1.l10842; GFX11-TRUE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v210843; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)10844; GFX11-TRUE16-NEXT:    v_add_f32_e32 v0, 0x40c00000, v010845; GFX11-TRUE16-NEXT:    v_bfe_u32 v6, v4, 16, 110846; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)10847; GFX11-TRUE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v310848; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, 0x400000, v410849; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v410850; GFX11-TRUE16-NEXT:    v_bfe_u32 v1, v2, 16, 110851; GFX11-TRUE16-NEXT:    v_add3_u32 v6, v6, v4, 0x7fff10852; GFX11-TRUE16-NEXT:    v_bfe_u32 v9, v3, 16, 110853; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, 0x400000, v310854; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, 0x400000, v210855; GFX11-TRUE16-NEXT:    v_bfe_u32 v8, v0, 16, 110856; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v4, v6, v7, vcc_lo10857; GFX11-TRUE16-NEXT:    v_add3_u32 v9, v9, v3, 0x7fff10858; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v310859; GFX11-TRUE16-NEXT:    v_add3_u32 v1, v1, v2, 0x7fff10860; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, 0x400000, v010861; GFX11-TRUE16-NEXT:    v_add3_u32 v8, v8, v0, 0x7fff10862; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v6, v9, v11, vcc_lo10863; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v210864; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v1, v5, vcc_lo10865; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v010866; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v4.h10867; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v8, v10, vcc_lo10868; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v6.h10869; GFX11-TRUE16-NEXT:  .LBB82_4: ; %end10870; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s010871; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)10872; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v310873; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]10874;10875; GFX11-FAKE16-LABEL: bitcast_v4bf16_to_v2f32:10876; GFX11-FAKE16:       ; %bb.0:10877; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10878; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo10879; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v210880; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s010881; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)10882; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s010883; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB82_210884; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true10885; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff0000, v110886; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)10887; GFX11-FAKE16-NEXT:    v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v2, 16, v010888; GFX11-FAKE16-NEXT:    v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v1, 16, v110889; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)10890; GFX11-FAKE16-NEXT:    v_bfe_u32 v8, v3, 16, 110891; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, 0x400000, v310892; GFX11-FAKE16-NEXT:    v_bfe_u32 v4, v2, 16, 110893; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, 0x400000, v210894; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v210895; GFX11-FAKE16-NEXT:    v_add3_u32 v8, v8, v3, 0x7fff10896; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v010897; GFX11-FAKE16-NEXT:    v_add3_u32 v4, v4, v2, 0x7fff10898; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)10899; GFX11-FAKE16-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v010900; GFX11-FAKE16-NEXT:    v_bfe_u32 v9, v1, 16, 110901; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)10902; GFX11-FAKE16-NEXT:    v_bfe_u32 v6, v0, 16, 110903; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, 0x400000, v010904; GFX11-FAKE16-NEXT:    v_add3_u32 v9, v9, v1, 0x7fff10905; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v4, v5, vcc_lo10906; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v010907; GFX11-FAKE16-NEXT:    v_add3_u32 v6, v6, v0, 0x7fff10908; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, 0x400000, v110909; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)10910; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v6, v7, vcc_lo10911; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v310912; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v8, v10, vcc_lo10913; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v110914; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v9, v4, vcc_lo10915; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v2, 0x706030210916; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)10917; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v3, v1, 0x706030210918; GFX11-FAKE16-NEXT:  .LBB82_2: ; %end10919; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s010920; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]10921  %cmp = icmp eq i32 %b, 010922  br i1 %cmp, label %cmp.true, label %cmp.false10923 10924cmp.true:10925  %a1 = fadd <4 x bfloat> %a, splat (bfloat 0xR40C0)10926  %a2 = bitcast <4 x bfloat> %a1 to <2 x float>10927  br label %end10928 10929cmp.false:10930  %a3 = bitcast <4 x bfloat> %a to <2 x float>10931  br label %end10932 10933end:10934  %phi = phi <2 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]10935  ret <2 x float> %phi10936}10937 10938define inreg <2 x float> @bitcast_v4bf16_to_v2f32_scalar(<4 x bfloat> inreg %a, i32 inreg %b) {10939; SI-LABEL: bitcast_v4bf16_to_v2f32_scalar:10940; SI:       ; %bb.0:10941; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10942; SI-NEXT:    s_cmp_lg_u32 s20, 010943; SI-NEXT:    v_mul_f32_e64 v8, 1.0, s1710944; SI-NEXT:    v_mul_f32_e64 v5, 1.0, s1610945; SI-NEXT:    v_mul_f32_e64 v7, 1.0, s1910946; SI-NEXT:    v_mul_f32_e64 v3, 1.0, s1810947; SI-NEXT:    s_cbranch_scc0 .LBB83_410948; SI-NEXT:  ; %bb.1: ; %cmp.false10949; SI-NEXT:    v_lshrrev_b32_e32 v6, 16, v810950; SI-NEXT:    v_lshr_b64 v[0:1], v[5:6], 1610951; SI-NEXT:    v_lshrrev_b32_e32 v4, 16, v710952; SI-NEXT:    v_lshr_b64 v[1:2], v[3:4], 1610953; SI-NEXT:    s_cbranch_execnz .LBB83_310954; SI-NEXT:  .LBB83_2: ; %cmp.true10955; SI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v810956; SI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v510957; SI-NEXT:    v_add_f32_e32 v1, 0x40c00000, v110958; SI-NEXT:    v_add_f32_e32 v0, 0x40c00000, v010959; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v110960; SI-NEXT:    v_lshr_b64 v[0:1], v[0:1], 1610961; SI-NEXT:    v_and_b32_e32 v2, 0xffff0000, v710962; SI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v310963; SI-NEXT:    v_add_f32_e32 v2, 0x40c00000, v210964; SI-NEXT:    v_add_f32_e32 v1, 0x40c00000, v110965; SI-NEXT:    v_lshrrev_b32_e32 v2, 16, v210966; SI-NEXT:    v_lshr_b64 v[1:2], v[1:2], 1610967; SI-NEXT:  .LBB83_3: ; %end10968; SI-NEXT:    s_setpc_b64 s[30:31]10969; SI-NEXT:  .LBB83_4:10970; SI-NEXT:    ; implicit-def: $vgpr0_vgpr110971; SI-NEXT:    s_branch .LBB83_210972;10973; VI-LABEL: bitcast_v4bf16_to_v2f32_scalar:10974; VI:       ; %bb.0:10975; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10976; VI-NEXT:    s_cmp_lg_u32 s18, 010977; VI-NEXT:    s_cbranch_scc0 .LBB83_310978; VI-NEXT:  ; %bb.1: ; %cmp.false10979; VI-NEXT:    s_cbranch_execnz .LBB83_410980; VI-NEXT:  .LBB83_2: ; %cmp.true10981; VI-NEXT:    s_lshl_b32 s4, s17, 1610982; VI-NEXT:    v_mov_b32_e32 v4, 0x40c0000010983; VI-NEXT:    v_add_f32_e32 v0, s4, v410984; VI-NEXT:    v_bfe_u32 v1, v0, 16, 110985; VI-NEXT:    v_add_u32_e32 v1, vcc, v1, v010986; VI-NEXT:    v_add_u32_e32 v1, vcc, 0x7fff, v110987; VI-NEXT:    v_or_b32_e32 v2, 0x400000, v010988; VI-NEXT:    v_cmp_u_f32_e32 vcc, v0, v010989; VI-NEXT:    s_and_b32 s4, s17, 0xffff000010990; VI-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc10991; VI-NEXT:    v_add_f32_e32 v1, s4, v410992; VI-NEXT:    v_bfe_u32 v2, v1, 16, 110993; VI-NEXT:    v_add_u32_e32 v2, vcc, v2, v110994; VI-NEXT:    v_add_u32_e32 v2, vcc, 0x7fff, v210995; VI-NEXT:    v_or_b32_e32 v3, 0x400000, v110996; VI-NEXT:    v_cmp_u_f32_e32 vcc, v1, v110997; VI-NEXT:    v_cndmask_b32_e32 v1, v2, v3, vcc10998; VI-NEXT:    v_lshrrev_b32_e32 v1, 16, v110999; VI-NEXT:    s_lshl_b32 s4, s16, 1611000; VI-NEXT:    v_lshrrev_b64 v[2:3], 16, v[0:1]11001; VI-NEXT:    v_add_f32_e32 v0, s4, v411002; VI-NEXT:    v_bfe_u32 v1, v0, 16, 111003; VI-NEXT:    v_add_u32_e32 v1, vcc, v1, v011004; VI-NEXT:    v_add_u32_e32 v1, vcc, 0x7fff, v111005; VI-NEXT:    v_or_b32_e32 v3, 0x400000, v011006; VI-NEXT:    v_cmp_u_f32_e32 vcc, v0, v011007; VI-NEXT:    s_and_b32 s4, s16, 0xffff000011008; VI-NEXT:    v_cndmask_b32_e32 v0, v1, v3, vcc11009; VI-NEXT:    v_add_f32_e32 v1, s4, v411010; VI-NEXT:    v_bfe_u32 v3, v1, 16, 111011; VI-NEXT:    v_add_u32_e32 v3, vcc, v3, v111012; VI-NEXT:    v_add_u32_e32 v3, vcc, 0x7fff, v311013; VI-NEXT:    v_or_b32_e32 v4, 0x400000, v111014; VI-NEXT:    v_cmp_u_f32_e32 vcc, v1, v111015; VI-NEXT:    v_cndmask_b32_e32 v1, v3, v4, vcc11016; VI-NEXT:    v_lshrrev_b32_e32 v1, 16, v111017; VI-NEXT:    v_lshrrev_b64 v[0:1], 16, v[0:1]11018; VI-NEXT:    v_mov_b32_e32 v1, v211019; VI-NEXT:    s_setpc_b64 s[30:31]11020; VI-NEXT:  .LBB83_3:11021; VI-NEXT:    s_branch .LBB83_211022; VI-NEXT:  .LBB83_4:11023; VI-NEXT:    v_mov_b32_e32 v0, s1611024; VI-NEXT:    v_mov_b32_e32 v1, s1711025; VI-NEXT:    s_setpc_b64 s[30:31]11026;11027; GFX9-LABEL: bitcast_v4bf16_to_v2f32_scalar:11028; GFX9:       ; %bb.0:11029; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)11030; GFX9-NEXT:    s_cmp_lg_u32 s18, 011031; GFX9-NEXT:    s_cbranch_scc0 .LBB83_311032; GFX9-NEXT:  ; %bb.1: ; %cmp.false11033; GFX9-NEXT:    s_cbranch_execnz .LBB83_411034; GFX9-NEXT:  .LBB83_2: ; %cmp.true11035; GFX9-NEXT:    s_pack_lh_b32_b16 s4, 0, s1611036; GFX9-NEXT:    v_mov_b32_e32 v1, 0x40c0000011037; GFX9-NEXT:    v_add_f32_e32 v0, s4, v111038; GFX9-NEXT:    v_bfe_u32 v2, v0, 16, 111039; GFX9-NEXT:    v_add_u32_e32 v2, v2, v011040; GFX9-NEXT:    v_add_u32_e32 v2, 0x7fff, v211041; GFX9-NEXT:    v_or_b32_e32 v3, 0x400000, v011042; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v0, v011043; GFX9-NEXT:    s_lshl_b32 s4, s16, 1611044; GFX9-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc11045; GFX9-NEXT:    v_add_f32_e32 v2, s4, v111046; GFX9-NEXT:    v_bfe_u32 v3, v2, 16, 111047; GFX9-NEXT:    v_add_u32_e32 v3, v3, v211048; GFX9-NEXT:    v_add_u32_e32 v3, 0x7fff, v311049; GFX9-NEXT:    v_or_b32_e32 v4, 0x400000, v211050; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v2, v211051; GFX9-NEXT:    v_cndmask_b32_e32 v2, v3, v4, vcc11052; GFX9-NEXT:    v_mov_b32_e32 v3, 0xffff11053; GFX9-NEXT:    v_lshrrev_b32_e32 v0, 16, v011054; GFX9-NEXT:    v_and_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_111055; GFX9-NEXT:    s_pack_lh_b32_b16 s4, 0, s1711056; GFX9-NEXT:    v_lshl_or_b32 v0, v0, 16, v211057; GFX9-NEXT:    v_add_f32_e32 v2, s4, v111058; GFX9-NEXT:    v_bfe_u32 v4, v2, 16, 111059; GFX9-NEXT:    v_add_u32_e32 v4, v4, v211060; GFX9-NEXT:    s_lshl_b32 s4, s17, 1611061; GFX9-NEXT:    v_add_u32_e32 v4, 0x7fff, v411062; GFX9-NEXT:    v_or_b32_e32 v5, 0x400000, v211063; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v2, v211064; GFX9-NEXT:    v_add_f32_e32 v1, s4, v111065; GFX9-NEXT:    v_cndmask_b32_e32 v2, v4, v5, vcc11066; GFX9-NEXT:    v_bfe_u32 v4, v1, 16, 111067; GFX9-NEXT:    v_add_u32_e32 v4, v4, v111068; GFX9-NEXT:    v_add_u32_e32 v4, 0x7fff, v411069; GFX9-NEXT:    v_or_b32_e32 v5, 0x400000, v111070; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v1, v111071; GFX9-NEXT:    v_cndmask_b32_e32 v1, v4, v5, vcc11072; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 16, v211073; GFX9-NEXT:    v_and_b32_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_111074; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v111075; GFX9-NEXT:    s_setpc_b64 s[30:31]11076; GFX9-NEXT:  .LBB83_3:11077; GFX9-NEXT:    s_branch .LBB83_211078; GFX9-NEXT:  .LBB83_4:11079; GFX9-NEXT:    v_mov_b32_e32 v0, s1611080; GFX9-NEXT:    v_mov_b32_e32 v1, s1711081; GFX9-NEXT:    s_setpc_b64 s[30:31]11082;11083; GFX11-TRUE16-LABEL: bitcast_v4bf16_to_v2f32_scalar:11084; GFX11-TRUE16:       ; %bb.0:11085; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)11086; GFX11-TRUE16-NEXT:    s_cmp_lg_u32 s2, 011087; GFX11-TRUE16-NEXT:    s_mov_b32 s2, 011088; GFX11-TRUE16-NEXT:    s_cbranch_scc0 .LBB83_311089; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow11090; GFX11-TRUE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s211091; GFX11-TRUE16-NEXT:    s_cbranch_vccnz .LBB83_411092; GFX11-TRUE16-NEXT:  .LBB83_2: ; %cmp.true11093; GFX11-TRUE16-NEXT:    s_pack_lh_b32_b16 s2, 0, s011094; GFX11-TRUE16-NEXT:    s_lshl_b32 s0, s0, 1611095; GFX11-TRUE16-NEXT:    v_add_f32_e64 v0, 0x40c00000, s211096; GFX11-TRUE16-NEXT:    v_add_f32_e64 v1, 0x40c00000, s011097; GFX11-TRUE16-NEXT:    s_pack_lh_b32_b16 s2, 0, s111098; GFX11-TRUE16-NEXT:    s_lshl_b32 s1, s1, 1611099; GFX11-TRUE16-NEXT:    v_add_f32_e64 v3, 0x40c00000, s211100; GFX11-TRUE16-NEXT:    v_bfe_u32 v2, v0, 16, 111101; GFX11-TRUE16-NEXT:    v_bfe_u32 v6, v1, 16, 111102; GFX11-TRUE16-NEXT:    v_add_f32_e64 v4, 0x40c00000, s111103; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, 0x400000, v011104; GFX11-TRUE16-NEXT:    v_bfe_u32 v8, v3, 16, 111105; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v2, v2, v011106; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v6, v6, v111107; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, 0x400000, v111108; GFX11-TRUE16-NEXT:    v_bfe_u32 v9, v4, 16, 111109; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v8, v8, v311110; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v011111; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v6, 0x7fff, v611112; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v2, 0x7fff, v211113; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, 0x400000, v311114; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)11115; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v0, v2, v5 :: v_dual_add_nc_u32 v9, v9, v411116; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, 0x400000, v411117; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v5, 0x7fff, v811118; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v311119; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v8, 0x7fff, v911120; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v9, 16, v011121; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)11122; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v5, v10, vcc_lo11123; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v111124; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v011125; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v6, v7, vcc_lo11126; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v411127; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)11128; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v111129; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v8, v2, vcc_lo11130; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v9.l11131; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v211132; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v3.l11133; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]11134; GFX11-TRUE16-NEXT:  .LBB83_3:11135; GFX11-TRUE16-NEXT:    s_branch .LBB83_211136; GFX11-TRUE16-NEXT:  .LBB83_4:11137; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s111138; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]11139;11140; GFX11-FAKE16-LABEL: bitcast_v4bf16_to_v2f32_scalar:11141; GFX11-FAKE16:       ; %bb.0:11142; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)11143; GFX11-FAKE16-NEXT:    s_cmp_lg_u32 s2, 011144; GFX11-FAKE16-NEXT:    s_mov_b32 s2, 011145; GFX11-FAKE16-NEXT:    s_cbranch_scc0 .LBB83_311146; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow11147; GFX11-FAKE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s211148; GFX11-FAKE16-NEXT:    s_cbranch_vccnz .LBB83_411149; GFX11-FAKE16-NEXT:  .LBB83_2: ; %cmp.true11150; GFX11-FAKE16-NEXT:    s_pack_lh_b32_b16 s2, 0, s011151; GFX11-FAKE16-NEXT:    s_lshl_b32 s0, s0, 1611152; GFX11-FAKE16-NEXT:    v_add_f32_e64 v0, 0x40c00000, s211153; GFX11-FAKE16-NEXT:    v_add_f32_e64 v1, 0x40c00000, s011154; GFX11-FAKE16-NEXT:    s_lshl_b32 s0, s1, 1611155; GFX11-FAKE16-NEXT:    s_pack_lh_b32_b16 s1, 0, s111156; GFX11-FAKE16-NEXT:    v_add_f32_e64 v2, 0x40c00000, s011157; GFX11-FAKE16-NEXT:    v_add_f32_e64 v5, 0x40c00000, s111158; GFX11-FAKE16-NEXT:    v_bfe_u32 v4, v1, 16, 111159; GFX11-FAKE16-NEXT:    v_bfe_u32 v3, v0, 16, 111160; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, 0x400000, v111161; GFX11-FAKE16-NEXT:    v_bfe_u32 v6, v2, 16, 111162; GFX11-FAKE16-NEXT:    v_bfe_u32 v8, v5, 16, 111163; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v4, v4, v111164; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v111165; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, 0x400000, v211166; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, 0x400000, v011167; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v8, v8, v511168; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v4, 0x7fff, v411169; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)11170; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v1, v4, v9 :: v_dual_add_nc_u32 v6, v6, v211171; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v4, 0x7fff, v811172; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, 0x400000, v511173; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)11174; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v6, 0x7fff, v611175; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v211176; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v3, v3, v011177; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v111178; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v2, v6, v10 :: v_dual_add_nc_u32 v3, 0x7fff, v311179; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v011180; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)11181; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v111182; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v211183; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)11184; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v3, v7, vcc_lo11185; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v511186; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v211187; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)11188; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v011189; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v4, v8, vcc_lo11190; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v0, v0, 16, v111191; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)11192; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v311193; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, v3, 16, v211194; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]11195; GFX11-FAKE16-NEXT:  .LBB83_3:11196; GFX11-FAKE16-NEXT:    s_branch .LBB83_211197; GFX11-FAKE16-NEXT:  .LBB83_4:11198; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s111199; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]11200  %cmp = icmp eq i32 %b, 011201  br i1 %cmp, label %cmp.true, label %cmp.false11202 11203cmp.true:11204  %a1 = fadd <4 x bfloat> %a, splat (bfloat 0xR40C0)11205  %a2 = bitcast <4 x bfloat> %a1 to <2 x float>11206  br label %end11207 11208cmp.false:11209  %a3 = bitcast <4 x bfloat> %a to <2 x float>11210  br label %end11211 11212end:11213  %phi = phi <2 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]11214  ret <2 x float> %phi11215}11216 11217define <8 x i8> @bitcast_v2f32_to_v8i8(<2 x float> %a, i32 %b) {11218; SI-LABEL: bitcast_v2f32_to_v8i8:11219; SI:       ; %bb.0:11220; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)11221; SI-NEXT:    v_mov_b32_e32 v4, v111222; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v211223; SI-NEXT:    ; implicit-def: $vgpr111224; SI-NEXT:    ; implicit-def: $vgpr211225; SI-NEXT:    ; implicit-def: $vgpr311226; SI-NEXT:    ; implicit-def: $vgpr511227; SI-NEXT:    ; implicit-def: $vgpr611228; SI-NEXT:    ; implicit-def: $vgpr711229; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc11230; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]11231; SI-NEXT:    s_cbranch_execnz .LBB84_311232; SI-NEXT:  ; %bb.1: ; %Flow11233; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]11234; SI-NEXT:    s_cbranch_execnz .LBB84_411235; SI-NEXT:  .LBB84_2: ; %end11236; SI-NEXT:    s_or_b64 exec, exec, s[4:5]11237; SI-NEXT:    s_setpc_b64 s[30:31]11238; SI-NEXT:  .LBB84_3: ; %cmp.false11239; SI-NEXT:    v_alignbit_b32 v3, v4, v0, 2411240; SI-NEXT:    v_alignbit_b32 v2, v4, v0, 1611241; SI-NEXT:    v_alignbit_b32 v1, v4, v0, 811242; SI-NEXT:    v_lshrrev_b32_e32 v7, 24, v411243; SI-NEXT:    v_lshrrev_b32_e32 v6, 16, v411244; SI-NEXT:    v_lshrrev_b32_e32 v5, 8, v411245; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]11246; SI-NEXT:    s_cbranch_execz .LBB84_211247; SI-NEXT:  .LBB84_4: ; %cmp.true11248; SI-NEXT:    v_add_f32_e32 v4, 1.0, v411249; SI-NEXT:    v_add_f32_e32 v0, 1.0, v011250; SI-NEXT:    v_alignbit_b32 v3, v4, v0, 2411251; SI-NEXT:    v_alignbit_b32 v2, v4, v0, 1611252; SI-NEXT:    v_alignbit_b32 v1, v4, v0, 811253; SI-NEXT:    v_lshrrev_b32_e32 v7, 24, v411254; SI-NEXT:    v_lshrrev_b32_e32 v6, 16, v411255; SI-NEXT:    v_lshrrev_b32_e32 v5, 8, v411256; SI-NEXT:    s_or_b64 exec, exec, s[4:5]11257; SI-NEXT:    s_setpc_b64 s[30:31]11258;11259; VI-LABEL: bitcast_v2f32_to_v8i8:11260; VI:       ; %bb.0:11261; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)11262; VI-NEXT:    v_mov_b32_e32 v9, v111263; VI-NEXT:    v_mov_b32_e32 v8, v011264; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v211265; VI-NEXT:    ; implicit-def: $vgpr111266; VI-NEXT:    ; implicit-def: $vgpr211267; VI-NEXT:    ; implicit-def: $vgpr311268; VI-NEXT:    ; implicit-def: $vgpr511269; VI-NEXT:    ; implicit-def: $vgpr611270; VI-NEXT:    ; implicit-def: $vgpr711271; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc11272; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]11273; VI-NEXT:  ; %bb.1: ; %cmp.false11274; VI-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]11275; VI-NEXT:    v_lshrrev_b32_e32 v7, 24, v911276; VI-NEXT:    v_lshrrev_b32_e32 v6, 16, v911277; VI-NEXT:    v_lshrrev_b32_e32 v5, 8, v911278; VI-NEXT:    v_lshrrev_b32_e32 v2, 16, v811279; VI-NEXT:    v_lshrrev_b32_e32 v1, 8, v811280; VI-NEXT:  ; %bb.2: ; %Flow11281; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]11282; VI-NEXT:  ; %bb.3: ; %cmp.true11283; VI-NEXT:    v_add_f32_e32 v9, 1.0, v911284; VI-NEXT:    v_add_f32_e32 v8, 1.0, v811285; VI-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]11286; VI-NEXT:    v_lshrrev_b32_e32 v7, 24, v911287; VI-NEXT:    v_lshrrev_b32_e32 v6, 16, v911288; VI-NEXT:    v_lshrrev_b32_e32 v5, 8, v911289; VI-NEXT:    v_lshrrev_b32_e32 v2, 16, v811290; VI-NEXT:    v_lshrrev_b32_e32 v1, 8, v811291; VI-NEXT:  ; %bb.4: ; %end11292; VI-NEXT:    s_or_b64 exec, exec, s[4:5]11293; VI-NEXT:    v_mov_b32_e32 v0, v811294; VI-NEXT:    v_mov_b32_e32 v4, v911295; VI-NEXT:    s_setpc_b64 s[30:31]11296;11297; GFX9-LABEL: bitcast_v2f32_to_v8i8:11298; GFX9:       ; %bb.0:11299; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)11300; GFX9-NEXT:    v_mov_b32_e32 v9, v111301; GFX9-NEXT:    v_mov_b32_e32 v8, v011302; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v211303; GFX9-NEXT:    ; implicit-def: $vgpr111304; GFX9-NEXT:    ; implicit-def: $vgpr211305; GFX9-NEXT:    ; implicit-def: $vgpr311306; GFX9-NEXT:    ; implicit-def: $vgpr511307; GFX9-NEXT:    ; implicit-def: $vgpr611308; GFX9-NEXT:    ; implicit-def: $vgpr711309; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc11310; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]11311; GFX9-NEXT:  ; %bb.1: ; %cmp.false11312; GFX9-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]11313; GFX9-NEXT:    v_lshrrev_b32_e32 v7, 24, v911314; GFX9-NEXT:    v_lshrrev_b32_e32 v6, 16, v911315; GFX9-NEXT:    v_lshrrev_b32_e32 v5, 8, v911316; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 16, v811317; GFX9-NEXT:    v_lshrrev_b32_e32 v1, 8, v811318; GFX9-NEXT:  ; %bb.2: ; %Flow11319; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]11320; GFX9-NEXT:  ; %bb.3: ; %cmp.true11321; GFX9-NEXT:    v_add_f32_e32 v9, 1.0, v911322; GFX9-NEXT:    v_add_f32_e32 v8, 1.0, v811323; GFX9-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]11324; GFX9-NEXT:    v_lshrrev_b32_e32 v7, 24, v911325; GFX9-NEXT:    v_lshrrev_b32_e32 v6, 16, v911326; GFX9-NEXT:    v_lshrrev_b32_e32 v5, 8, v911327; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 16, v811328; GFX9-NEXT:    v_lshrrev_b32_e32 v1, 8, v811329; GFX9-NEXT:  ; %bb.4: ; %end11330; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]11331; GFX9-NEXT:    v_mov_b32_e32 v0, v811332; GFX9-NEXT:    v_mov_b32_e32 v4, v911333; GFX9-NEXT:    s_setpc_b64 s[30:31]11334;11335; GFX11-TRUE16-LABEL: bitcast_v2f32_to_v8i8:11336; GFX11-TRUE16:       ; %bb.0:11337; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)11338; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v011339; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo11340; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo1611341; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo1611342; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo1611343; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_lo1611344; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v211345; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s011346; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false11347; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)11348; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]11349; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v911350; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v911351; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v811352; GFX11-TRUE16-NEXT:  ; %bb.2: ; %Flow11353; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s011354; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true11355; GFX11-TRUE16-NEXT:    v_dual_add_f32 v9, 1.0, v9 :: v_dual_add_f32 v8, 1.0, v811356; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)11357; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v911358; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]11359; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v911360; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v811361; GFX11-TRUE16-NEXT:  ; %bb.4: ; %end11362; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s011363; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v8.l11364; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v8.h11365; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v9.l11366; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v9.h11367; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]11368;11369; GFX11-FAKE16-LABEL: bitcast_v2f32_to_v8i8:11370; GFX11-FAKE16:       ; %bb.0:11371; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)11372; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v011373; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v211374; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr111375; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr211376; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr311377; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr511378; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr611379; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr711380; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo11381; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)11382; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s011383; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false11384; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)11385; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]11386; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v911387; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v911388; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v911389; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v811390; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v811391; GFX11-FAKE16-NEXT:  ; %bb.2: ; %Flow11392; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s011393; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB84_411394; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true11395; GFX11-FAKE16-NEXT:    v_dual_add_f32 v9, 1.0, v9 :: v_dual_add_f32 v8, 1.0, v811396; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)11397; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v911398; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]11399; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v911400; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v911401; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v811402; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v811403; GFX11-FAKE16-NEXT:  .LBB84_4: ; %end11404; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s011405; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, v811406; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, v911407; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]11408  %cmp = icmp eq i32 %b, 011409  br i1 %cmp, label %cmp.true, label %cmp.false11410 11411cmp.true:11412  %a1 = fadd <2 x float> %a, splat (float 1.000000e+00)11413  %a2 = bitcast <2 x float> %a1 to <8 x i8>11414  br label %end11415 11416cmp.false:11417  %a3 = bitcast <2 x float> %a to <8 x i8>11418  br label %end11419 11420end:11421  %phi = phi <8 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]11422  ret <8 x i8> %phi11423}11424 11425define inreg <8 x i8> @bitcast_v2f32_to_v8i8_scalar(<2 x float> inreg %a, i32 inreg %b) {11426; SI-LABEL: bitcast_v2f32_to_v8i8_scalar:11427; SI:       ; %bb.0:11428; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)11429; SI-NEXT:    s_cmp_lg_u32 s18, 011430; SI-NEXT:    s_cbranch_scc0 .LBB85_311431; SI-NEXT:  ; %bb.1: ; %cmp.false11432; SI-NEXT:    s_lshr_b32 s12, s17, 2411433; SI-NEXT:    s_lshr_b32 s13, s17, 1611434; SI-NEXT:    s_lshr_b32 s14, s17, 811435; SI-NEXT:    s_lshr_b64 s[4:5], s[16:17], 2411436; SI-NEXT:    s_lshr_b64 s[6:7], s[16:17], 1611437; SI-NEXT:    s_lshr_b64 s[8:9], s[16:17], 811438; SI-NEXT:    s_cbranch_execnz .LBB85_411439; SI-NEXT:  .LBB85_2: ; %cmp.true11440; SI-NEXT:    v_add_f32_e64 v11, s17, 1.011441; SI-NEXT:    v_add_f32_e64 v10, s16, 1.011442; SI-NEXT:    v_lshr_b64 v[3:4], v[10:11], 2411443; SI-NEXT:    v_lshr_b64 v[8:9], v[10:11], 1611444; SI-NEXT:    v_lshr_b64 v[1:2], v[10:11], 811445; SI-NEXT:    v_lshrrev_b32_e32 v7, 24, v1111446; SI-NEXT:    v_lshrrev_b32_e32 v6, 16, v1111447; SI-NEXT:    v_lshrrev_b32_e32 v5, 8, v1111448; SI-NEXT:    s_branch .LBB85_511449; SI-NEXT:  .LBB85_3:11450; SI-NEXT:    ; implicit-def: $sgpr811451; SI-NEXT:    ; implicit-def: $sgpr611452; SI-NEXT:    ; implicit-def: $sgpr411453; SI-NEXT:    ; implicit-def: $sgpr1411454; SI-NEXT:    ; implicit-def: $sgpr1311455; SI-NEXT:    ; implicit-def: $sgpr1211456; SI-NEXT:    s_branch .LBB85_211457; SI-NEXT:  .LBB85_4:11458; SI-NEXT:    v_mov_b32_e32 v10, s1611459; SI-NEXT:    v_mov_b32_e32 v11, s1711460; SI-NEXT:    v_mov_b32_e32 v5, s1411461; SI-NEXT:    v_mov_b32_e32 v6, s1311462; SI-NEXT:    v_mov_b32_e32 v7, s1211463; SI-NEXT:    v_mov_b32_e32 v3, s411464; SI-NEXT:    v_mov_b32_e32 v8, s611465; SI-NEXT:    v_mov_b32_e32 v1, s811466; SI-NEXT:  .LBB85_5: ; %end11467; SI-NEXT:    v_mov_b32_e32 v0, v1011468; SI-NEXT:    v_mov_b32_e32 v2, v811469; SI-NEXT:    v_mov_b32_e32 v4, v1111470; SI-NEXT:    s_setpc_b64 s[30:31]11471;11472; VI-LABEL: bitcast_v2f32_to_v8i8_scalar:11473; VI:       ; %bb.0:11474; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)11475; VI-NEXT:    s_cmp_lg_u32 s18, 011476; VI-NEXT:    s_cbranch_scc0 .LBB85_311477; VI-NEXT:  ; %bb.1: ; %cmp.false11478; VI-NEXT:    s_lshr_b64 s[4:5], s[16:17], 2411479; VI-NEXT:    s_lshr_b32 s5, s17, 2411480; VI-NEXT:    s_lshr_b32 s8, s17, 1611481; VI-NEXT:    s_lshr_b32 s10, s17, 811482; VI-NEXT:    s_lshr_b32 s9, s16, 1611483; VI-NEXT:    s_lshr_b32 s11, s16, 811484; VI-NEXT:    s_cbranch_execnz .LBB85_411485; VI-NEXT:  .LBB85_2: ; %cmp.true11486; VI-NEXT:    v_add_f32_e64 v9, s17, 1.011487; VI-NEXT:    v_add_f32_e64 v8, s16, 1.011488; VI-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]11489; VI-NEXT:    v_lshrrev_b32_e32 v7, 24, v911490; VI-NEXT:    v_lshrrev_b32_e32 v6, 16, v911491; VI-NEXT:    v_lshrrev_b32_e32 v5, 8, v911492; VI-NEXT:    v_lshrrev_b32_e32 v2, 16, v811493; VI-NEXT:    v_lshrrev_b32_e32 v1, 8, v811494; VI-NEXT:    s_branch .LBB85_511495; VI-NEXT:  .LBB85_3:11496; VI-NEXT:    ; implicit-def: $sgpr1111497; VI-NEXT:    ; implicit-def: $sgpr911498; VI-NEXT:    ; implicit-def: $sgpr411499; VI-NEXT:    ; implicit-def: $sgpr1011500; VI-NEXT:    ; implicit-def: $sgpr811501; VI-NEXT:    ; implicit-def: $sgpr511502; VI-NEXT:    s_branch .LBB85_211503; VI-NEXT:  .LBB85_4:11504; VI-NEXT:    v_mov_b32_e32 v8, s1611505; VI-NEXT:    v_mov_b32_e32 v9, s1711506; VI-NEXT:    v_mov_b32_e32 v1, s1111507; VI-NEXT:    v_mov_b32_e32 v2, s911508; VI-NEXT:    v_mov_b32_e32 v5, s1011509; VI-NEXT:    v_mov_b32_e32 v6, s811510; VI-NEXT:    v_mov_b32_e32 v7, s511511; VI-NEXT:    v_mov_b32_e32 v3, s411512; VI-NEXT:  .LBB85_5: ; %end11513; VI-NEXT:    v_mov_b32_e32 v0, v811514; VI-NEXT:    v_mov_b32_e32 v4, v911515; VI-NEXT:    s_setpc_b64 s[30:31]11516;11517; GFX9-LABEL: bitcast_v2f32_to_v8i8_scalar:11518; GFX9:       ; %bb.0:11519; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)11520; GFX9-NEXT:    s_cmp_lg_u32 s18, 011521; GFX9-NEXT:    s_cbranch_scc0 .LBB85_311522; GFX9-NEXT:  ; %bb.1: ; %cmp.false11523; GFX9-NEXT:    s_lshr_b64 s[4:5], s[16:17], 2411524; GFX9-NEXT:    s_lshr_b32 s5, s17, 2411525; GFX9-NEXT:    s_lshr_b32 s8, s17, 1611526; GFX9-NEXT:    s_lshr_b32 s10, s17, 811527; GFX9-NEXT:    s_lshr_b32 s9, s16, 1611528; GFX9-NEXT:    s_lshr_b32 s11, s16, 811529; GFX9-NEXT:    s_cbranch_execnz .LBB85_411530; GFX9-NEXT:  .LBB85_2: ; %cmp.true11531; GFX9-NEXT:    v_add_f32_e64 v9, s17, 1.011532; GFX9-NEXT:    v_add_f32_e64 v8, s16, 1.011533; GFX9-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]11534; GFX9-NEXT:    v_lshrrev_b32_e32 v7, 24, v911535; GFX9-NEXT:    v_lshrrev_b32_e32 v6, 16, v911536; GFX9-NEXT:    v_lshrrev_b32_e32 v5, 8, v911537; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 16, v811538; GFX9-NEXT:    v_lshrrev_b32_e32 v1, 8, v811539; GFX9-NEXT:    s_branch .LBB85_511540; GFX9-NEXT:  .LBB85_3:11541; GFX9-NEXT:    ; implicit-def: $sgpr1111542; GFX9-NEXT:    ; implicit-def: $sgpr911543; GFX9-NEXT:    ; implicit-def: $sgpr411544; GFX9-NEXT:    ; implicit-def: $sgpr1011545; GFX9-NEXT:    ; implicit-def: $sgpr811546; GFX9-NEXT:    ; implicit-def: $sgpr511547; GFX9-NEXT:    s_branch .LBB85_211548; GFX9-NEXT:  .LBB85_4:11549; GFX9-NEXT:    v_mov_b32_e32 v8, s1611550; GFX9-NEXT:    v_mov_b32_e32 v9, s1711551; GFX9-NEXT:    v_mov_b32_e32 v1, s1111552; GFX9-NEXT:    v_mov_b32_e32 v2, s911553; GFX9-NEXT:    v_mov_b32_e32 v5, s1011554; GFX9-NEXT:    v_mov_b32_e32 v6, s811555; GFX9-NEXT:    v_mov_b32_e32 v7, s511556; GFX9-NEXT:    v_mov_b32_e32 v3, s411557; GFX9-NEXT:  .LBB85_5: ; %end11558; GFX9-NEXT:    v_mov_b32_e32 v0, v811559; GFX9-NEXT:    v_mov_b32_e32 v4, v911560; GFX9-NEXT:    s_setpc_b64 s[30:31]11561;11562; GFX11-LABEL: bitcast_v2f32_to_v8i8_scalar:11563; GFX11:       ; %bb.0:11564; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)11565; GFX11-NEXT:    s_cmp_lg_u32 s2, 011566; GFX11-NEXT:    s_mov_b32 s4, 011567; GFX11-NEXT:    s_cbranch_scc0 .LBB85_311568; GFX11-NEXT:  ; %bb.1: ; %cmp.false11569; GFX11-NEXT:    s_lshr_b64 s[2:3], s[0:1], 2411570; GFX11-NEXT:    s_lshr_b32 s3, s1, 2411571; GFX11-NEXT:    s_lshr_b32 s5, s1, 1611572; GFX11-NEXT:    s_lshr_b32 s7, s1, 811573; GFX11-NEXT:    s_lshr_b32 s6, s0, 1611574; GFX11-NEXT:    s_lshr_b32 s8, s0, 811575; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s411576; GFX11-NEXT:    s_cbranch_vccnz .LBB85_411577; GFX11-NEXT:  .LBB85_2: ; %cmp.true11578; GFX11-NEXT:    v_add_f32_e64 v9, s1, 1.011579; GFX11-NEXT:    v_add_f32_e64 v8, s0, 1.011580; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)11581; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v911582; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]11583; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v911584; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v911585; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v811586; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v811587; GFX11-NEXT:    s_branch .LBB85_511588; GFX11-NEXT:  .LBB85_3:11589; GFX11-NEXT:    ; implicit-def: $sgpr811590; GFX11-NEXT:    ; implicit-def: $sgpr611591; GFX11-NEXT:    ; implicit-def: $sgpr211592; GFX11-NEXT:    ; implicit-def: $sgpr711593; GFX11-NEXT:    ; implicit-def: $sgpr511594; GFX11-NEXT:    ; implicit-def: $sgpr311595; GFX11-NEXT:    s_branch .LBB85_211596; GFX11-NEXT:  .LBB85_4:11597; GFX11-NEXT:    v_dual_mov_b32 v8, s0 :: v_dual_mov_b32 v9, s111598; GFX11-NEXT:    v_dual_mov_b32 v1, s8 :: v_dual_mov_b32 v2, s611599; GFX11-NEXT:    v_dual_mov_b32 v5, s7 :: v_dual_mov_b32 v6, s511600; GFX11-NEXT:    v_mov_b32_e32 v7, s311601; GFX11-NEXT:    v_mov_b32_e32 v3, s211602; GFX11-NEXT:  .LBB85_5: ; %end11603; GFX11-NEXT:    v_mov_b32_e32 v0, v811604; GFX11-NEXT:    v_mov_b32_e32 v4, v911605; GFX11-NEXT:    s_setpc_b64 s[30:31]11606  %cmp = icmp eq i32 %b, 011607  br i1 %cmp, label %cmp.true, label %cmp.false11608 11609cmp.true:11610  %a1 = fadd <2 x float> %a, splat (float 1.000000e+00)11611  %a2 = bitcast <2 x float> %a1 to <8 x i8>11612  br label %end11613 11614cmp.false:11615  %a3 = bitcast <2 x float> %a to <8 x i8>11616  br label %end11617 11618end:11619  %phi = phi <8 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]11620  ret <8 x i8> %phi11621}11622 11623define <2 x float> @bitcast_v8i8_to_v2f32(<8 x i8> %a, i32 %b) {11624; SI-LABEL: bitcast_v8i8_to_v2f32:11625; SI:       ; %bb.0:11626; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)11627; SI-NEXT:    v_mov_b32_e32 v9, v011628; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v811629; SI-NEXT:    v_lshlrev_b32_e32 v10, 8, v111630; SI-NEXT:    v_lshlrev_b32_e32 v8, 24, v311631; SI-NEXT:    v_lshlrev_b32_e32 v5, 8, v511632; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v711633; SI-NEXT:    ; implicit-def: $vgpr0_vgpr111634; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc11635; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]11636; SI-NEXT:    s_cbranch_execnz .LBB86_311637; SI-NEXT:  ; %bb.1: ; %Flow11638; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]11639; SI-NEXT:    s_cbranch_execnz .LBB86_411640; SI-NEXT:  .LBB86_2: ; %end11641; SI-NEXT:    s_or_b64 exec, exec, s[4:5]11642; SI-NEXT:    s_setpc_b64 s[30:31]11643; SI-NEXT:  .LBB86_3: ; %cmp.false11644; SI-NEXT:    v_and_b32_e32 v0, 0xff, v911645; SI-NEXT:    v_and_b32_e32 v1, 0xff, v211646; SI-NEXT:    v_or_b32_e32 v0, v0, v1011647; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v111648; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v011649; SI-NEXT:    v_or_b32_e32 v1, v8, v111650; SI-NEXT:    v_or_b32_e32 v0, v0, v111651; SI-NEXT:    v_and_b32_e32 v1, 0xff, v411652; SI-NEXT:    v_and_b32_e32 v2, 0xff, v611653; SI-NEXT:    v_or_b32_e32 v1, v1, v511654; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v211655; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v111656; SI-NEXT:    v_or_b32_e32 v2, v3, v211657; SI-NEXT:    v_or_b32_e32 v1, v1, v211658; SI-NEXT:    ; implicit-def: $vgpr911659; SI-NEXT:    ; implicit-def: $vgpr1011660; SI-NEXT:    ; implicit-def: $vgpr211661; SI-NEXT:    ; implicit-def: $vgpr811662; SI-NEXT:    ; implicit-def: $vgpr411663; SI-NEXT:    ; implicit-def: $vgpr511664; SI-NEXT:    ; implicit-def: $vgpr611665; SI-NEXT:    ; implicit-def: $vgpr311666; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]11667; SI-NEXT:    s_cbranch_execz .LBB86_211668; SI-NEXT:  .LBB86_4: ; %cmp.true11669; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v911670; SI-NEXT:    v_and_b32_e32 v0, 0xff, v011671; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v211672; SI-NEXT:    v_or_b32_e32 v0, v10, v011673; SI-NEXT:    v_and_b32_e32 v1, 0xff, v111674; SI-NEXT:    v_add_i32_e32 v0, vcc, 0x300, v011675; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v111676; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v011677; SI-NEXT:    v_or_b32_e32 v1, v8, v111678; SI-NEXT:    v_or_b32_e32 v0, v1, v011679; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v411680; SI-NEXT:    v_and_b32_e32 v1, 0xff, v111681; SI-NEXT:    v_add_i32_e32 v2, vcc, 3, v611682; SI-NEXT:    v_or_b32_e32 v1, v5, v111683; SI-NEXT:    v_and_b32_e32 v2, 0xff, v211684; SI-NEXT:    v_add_i32_e32 v1, vcc, 0x300, v111685; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v211686; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v111687; SI-NEXT:    v_or_b32_e32 v2, v3, v211688; SI-NEXT:    v_or_b32_e32 v1, v2, v111689; SI-NEXT:    v_add_i32_e32 v0, vcc, 0x3000000, v011690; SI-NEXT:    v_add_i32_e32 v1, vcc, 0x3000000, v111691; SI-NEXT:    s_or_b64 exec, exec, s[4:5]11692; SI-NEXT:    s_setpc_b64 s[30:31]11693;11694; VI-LABEL: bitcast_v8i8_to_v2f32:11695; VI:       ; %bb.0:11696; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)11697; VI-NEXT:    v_mov_b32_e32 v9, v011698; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v811699; VI-NEXT:    v_lshlrev_b16_e32 v10, 8, v111700; VI-NEXT:    v_lshlrev_b16_e32 v8, 8, v311701; VI-NEXT:    v_lshlrev_b16_e32 v5, 8, v511702; VI-NEXT:    v_lshlrev_b16_e32 v3, 8, v711703; VI-NEXT:    ; implicit-def: $vgpr0_vgpr111704; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc11705; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]11706; VI-NEXT:    s_cbranch_execnz .LBB86_311707; VI-NEXT:  ; %bb.1: ; %Flow11708; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]11709; VI-NEXT:    s_cbranch_execnz .LBB86_411710; VI-NEXT:  .LBB86_2: ; %end11711; VI-NEXT:    s_or_b64 exec, exec, s[4:5]11712; VI-NEXT:    s_setpc_b64 s[30:31]11713; VI-NEXT:  .LBB86_3: ; %cmp.false11714; VI-NEXT:    v_or_b32_sdwa v0, v9, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD11715; VI-NEXT:    v_or_b32_sdwa v1, v2, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD11716; VI-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD11717; VI-NEXT:    v_or_b32_sdwa v1, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD11718; VI-NEXT:    v_or_b32_sdwa v2, v6, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD11719; VI-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD11720; VI-NEXT:    ; implicit-def: $vgpr911721; VI-NEXT:    ; implicit-def: $vgpr1011722; VI-NEXT:    ; implicit-def: $vgpr211723; VI-NEXT:    ; implicit-def: $vgpr811724; VI-NEXT:    ; implicit-def: $vgpr411725; VI-NEXT:    ; implicit-def: $vgpr511726; VI-NEXT:    ; implicit-def: $vgpr611727; VI-NEXT:    ; implicit-def: $vgpr311728; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]11729; VI-NEXT:    s_cbranch_execz .LBB86_211730; VI-NEXT:  .LBB86_4: ; %cmp.true11731; VI-NEXT:    v_add_u16_e32 v0, 3, v911732; VI-NEXT:    v_add_u16_e32 v1, 3, v211733; VI-NEXT:    v_or_b32_sdwa v0, v10, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_011734; VI-NEXT:    v_or_b32_sdwa v1, v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_011735; VI-NEXT:    v_mov_b32_e32 v2, 0x30011736; VI-NEXT:    v_add_u16_e32 v0, 0x300, v011737; VI-NEXT:    v_add_u16_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD11738; VI-NEXT:    v_or_b32_e32 v0, v0, v111739; VI-NEXT:    v_add_u16_e32 v1, 3, v411740; VI-NEXT:    v_add_u16_e32 v4, 3, v611741; VI-NEXT:    v_or_b32_sdwa v1, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_011742; VI-NEXT:    v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_011743; VI-NEXT:    v_add_u16_e32 v1, 0x300, v111744; VI-NEXT:    v_add_u16_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD11745; VI-NEXT:    v_or_b32_e32 v1, v1, v211746; VI-NEXT:    s_or_b64 exec, exec, s[4:5]11747; VI-NEXT:    s_setpc_b64 s[30:31]11748;11749; GFX9-LABEL: bitcast_v8i8_to_v2f32:11750; GFX9:       ; %bb.0:11751; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)11752; GFX9-NEXT:    v_mov_b32_e32 v9, v011753; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v811754; GFX9-NEXT:    v_lshlrev_b16_e32 v10, 8, v111755; GFX9-NEXT:    v_lshlrev_b16_e32 v8, 8, v311756; GFX9-NEXT:    v_lshlrev_b16_e32 v5, 8, v511757; GFX9-NEXT:    v_lshlrev_b16_e32 v3, 8, v711758; GFX9-NEXT:    ; implicit-def: $vgpr0_vgpr111759; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc11760; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]11761; GFX9-NEXT:    s_cbranch_execnz .LBB86_311762; GFX9-NEXT:  ; %bb.1: ; %Flow11763; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]11764; GFX9-NEXT:    s_cbranch_execnz .LBB86_411765; GFX9-NEXT:  .LBB86_2: ; %end11766; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]11767; GFX9-NEXT:    s_setpc_b64 s[30:31]11768; GFX9-NEXT:  .LBB86_3: ; %cmp.false11769; GFX9-NEXT:    v_or_b32_sdwa v0, v9, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD11770; GFX9-NEXT:    v_or_b32_sdwa v1, v2, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD11771; GFX9-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD11772; GFX9-NEXT:    v_or_b32_sdwa v1, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD11773; GFX9-NEXT:    v_or_b32_sdwa v2, v6, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD11774; GFX9-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD11775; GFX9-NEXT:    ; implicit-def: $vgpr911776; GFX9-NEXT:    ; implicit-def: $vgpr1011777; GFX9-NEXT:    ; implicit-def: $vgpr211778; GFX9-NEXT:    ; implicit-def: $vgpr811779; GFX9-NEXT:    ; implicit-def: $vgpr411780; GFX9-NEXT:    ; implicit-def: $vgpr511781; GFX9-NEXT:    ; implicit-def: $vgpr611782; GFX9-NEXT:    ; implicit-def: $vgpr311783; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]11784; GFX9-NEXT:    s_cbranch_execz .LBB86_211785; GFX9-NEXT:  .LBB86_4: ; %cmp.true11786; GFX9-NEXT:    v_add_u16_e32 v0, 3, v911787; GFX9-NEXT:    v_add_u16_e32 v1, 3, v211788; GFX9-NEXT:    v_or_b32_sdwa v0, v10, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_011789; GFX9-NEXT:    s_movk_i32 s6, 0x30011790; GFX9-NEXT:    v_or_b32_sdwa v1, v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_011791; GFX9-NEXT:    v_add_u16_e32 v0, 0x300, v011792; GFX9-NEXT:    v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD11793; GFX9-NEXT:    v_or_b32_e32 v0, v0, v111794; GFX9-NEXT:    v_add_u16_e32 v1, 3, v411795; GFX9-NEXT:    v_add_u16_e32 v2, 3, v611796; GFX9-NEXT:    v_or_b32_sdwa v1, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_011797; GFX9-NEXT:    v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_011798; GFX9-NEXT:    v_add_u16_e32 v1, 0x300, v111799; GFX9-NEXT:    v_add_u16_sdwa v2, v2, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD11800; GFX9-NEXT:    v_or_b32_e32 v1, v1, v211801; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]11802; GFX9-NEXT:    s_setpc_b64 s[30:31]11803;11804; GFX11-TRUE16-LABEL: bitcast_v8i8_to_v2f32:11805; GFX11-TRUE16:       ; %bb.0:11806; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)11807; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.h, v5.l11808; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.h, v2.l11809; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v0.l11810; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.l, 8, v1.l11811; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.h, 8, v3.l11812; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.l, 8, v5.h11813; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.h, 8, v7.l11814; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo11815; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr111816; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v811817; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s011818; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB86_311819; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow11820; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s011821; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB86_411822; GFX11-TRUE16-NEXT:  .LBB86_2: ; %end11823; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s011824; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]11825; GFX11-TRUE16-NEXT:  .LBB86_3: ; %cmp.false11826; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v5.l11827; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v4.h11828; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v4.l11829; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v6.l11830; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo1611831; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_hi1611832; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_lo1611833; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr6_lo1611834; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)11835; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v2.l11836; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v0.h, v2.h11837; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)11838; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v3.l11839; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v1.h, v3.h11840; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_lo1611841; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_hi1611842; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo1611843; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_hi1611844; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s011845; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB86_211846; GFX11-TRUE16-NEXT:  .LBB86_4: ; %cmp.true11847; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v5.l, 311848; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v4.h, 311849; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v4.l, 311850; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v6.l, 311851; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)11852; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l11853; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h11854; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)11855; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l11856; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h11857; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)11858; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v2.l, v0.l11859; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v2.h, v0.h11860; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)11861; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v3.l, v1.l11862; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v3.h, v1.h11863; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)11864; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l11865; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, 0x300, v0.h11866; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)11867; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.l11868; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, 0x300, v1.h11869; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s011870; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]11871;11872; GFX11-FAKE16-LABEL: bitcast_v8i8_to_v2f32:11873; GFX11-FAKE16:       ; %bb.0:11874; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)11875; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v9, v011876; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v811877; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v8, 8, v111878; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v3, 8, v311879; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v5, 8, v511880; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v7, 8, v711881; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr111882; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo11883; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)11884; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s011885; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB86_311886; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow11887; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s011888; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB86_411889; GFX11-FAKE16-NEXT:  .LBB86_2: ; %end11890; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s011891; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]11892; GFX11-FAKE16-NEXT:  .LBB86_3: ; %cmp.false11893; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v911894; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v211895; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v411896; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v611897; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr911898; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr611899; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)11900; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v811901; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v311902; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)11903; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v511904; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v4, v711905; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr811906; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr411907; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr511908; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr711909; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)11910; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v011911; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v111912; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)11913; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v211914; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v311915; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)11916; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v111917; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v311918; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr211919; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr311920; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s011921; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB86_211922; GFX11-FAKE16-NEXT:  .LBB86_4: ; %cmp.true11923; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v9, 311924; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v2, 311925; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v4, 311926; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v6, 311927; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)11928; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v011929; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v111930; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)11931; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v211932; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v411933; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)11934; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v8, v011935; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v3, v111936; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)11937; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v5, v211938; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v7, v411939; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)11940; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v011941; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v111942; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)11943; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x300, v211944; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v311945; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)11946; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v011947; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v111948; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)11949; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v211950; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v311951; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)11952; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v111953; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v311954; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s011955; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]11956  %cmp = icmp eq i32 %b, 011957  br i1 %cmp, label %cmp.true, label %cmp.false11958 11959cmp.true:11960  %a1 = add <8 x i8> %a, splat (i8 3)11961  %a2 = bitcast <8 x i8> %a1 to <2 x float>11962  br label %end11963 11964cmp.false:11965  %a3 = bitcast <8 x i8> %a to <2 x float>11966  br label %end11967 11968end:11969  %phi = phi <2 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]11970  ret <2 x float> %phi11971}11972 11973define inreg <2 x float> @bitcast_v8i8_to_v2f32_scalar(<8 x i8> inreg %a, i32 inreg %b) {11974; SI-LABEL: bitcast_v8i8_to_v2f32_scalar:11975; SI:       ; %bb.0:11976; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)11977; SI-NEXT:    s_cmp_lg_u32 s24, 011978; SI-NEXT:    s_cbranch_scc0 .LBB87_411979; SI-NEXT:  ; %bb.1: ; %cmp.false11980; SI-NEXT:    s_and_b32 s4, s16, 0xff11981; SI-NEXT:    s_lshl_b32 s5, s17, 811982; SI-NEXT:    s_or_b32 s4, s4, s511983; SI-NEXT:    s_and_b32 s5, s18, 0xff11984; SI-NEXT:    s_lshl_b32 s5, s5, 1611985; SI-NEXT:    s_lshl_b32 s6, s19, 2411986; SI-NEXT:    s_and_b32 s4, s4, 0xffff11987; SI-NEXT:    s_or_b32 s5, s6, s511988; SI-NEXT:    s_or_b32 s4, s4, s511989; SI-NEXT:    s_and_b32 s5, s20, 0xff11990; SI-NEXT:    s_lshl_b32 s6, s21, 811991; SI-NEXT:    s_or_b32 s5, s5, s611992; SI-NEXT:    s_and_b32 s6, s22, 0xff11993; SI-NEXT:    s_lshl_b32 s6, s6, 1611994; SI-NEXT:    s_lshl_b32 s7, s23, 2411995; SI-NEXT:    s_and_b32 s5, s5, 0xffff11996; SI-NEXT:    s_or_b32 s6, s7, s611997; SI-NEXT:    s_or_b32 s5, s5, s611998; SI-NEXT:    s_cbranch_execnz .LBB87_311999; SI-NEXT:  .LBB87_2: ; %cmp.true12000; SI-NEXT:    s_add_i32 s16, s16, 312001; SI-NEXT:    s_and_b32 s4, s16, 0xff12002; SI-NEXT:    s_lshl_b32 s5, s17, 812003; SI-NEXT:    s_add_i32 s18, s18, 312004; SI-NEXT:    s_or_b32 s4, s5, s412005; SI-NEXT:    s_and_b32 s6, s18, 0xff12006; SI-NEXT:    s_addk_i32 s4, 0x30012007; SI-NEXT:    s_lshl_b32 s5, s19, 2412008; SI-NEXT:    s_lshl_b32 s6, s6, 1612009; SI-NEXT:    s_and_b32 s4, s4, 0xffff12010; SI-NEXT:    s_or_b32 s5, s5, s612011; SI-NEXT:    s_add_i32 s20, s20, 312012; SI-NEXT:    s_or_b32 s4, s5, s412013; SI-NEXT:    s_and_b32 s5, s20, 0xff12014; SI-NEXT:    s_lshl_b32 s6, s21, 812015; SI-NEXT:    s_add_i32 s22, s22, 312016; SI-NEXT:    s_or_b32 s5, s6, s512017; SI-NEXT:    s_and_b32 s7, s22, 0xff12018; SI-NEXT:    s_addk_i32 s5, 0x30012019; SI-NEXT:    s_lshl_b32 s6, s23, 2412020; SI-NEXT:    s_lshl_b32 s7, s7, 1612021; SI-NEXT:    s_and_b32 s5, s5, 0xffff12022; SI-NEXT:    s_or_b32 s6, s6, s712023; SI-NEXT:    s_or_b32 s5, s6, s512024; SI-NEXT:    s_add_i32 s4, s4, 0x300000012025; SI-NEXT:    s_add_i32 s5, s5, 0x300000012026; SI-NEXT:  .LBB87_3: ; %end12027; SI-NEXT:    v_mov_b32_e32 v0, s412028; SI-NEXT:    v_mov_b32_e32 v1, s512029; SI-NEXT:    s_setpc_b64 s[30:31]12030; SI-NEXT:  .LBB87_4:12031; SI-NEXT:    ; implicit-def: $sgpr4_sgpr512032; SI-NEXT:    s_branch .LBB87_212033;12034; VI-LABEL: bitcast_v8i8_to_v2f32_scalar:12035; VI:       ; %bb.0:12036; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12037; VI-NEXT:    s_cmp_lg_u32 s24, 012038; VI-NEXT:    s_cbranch_scc0 .LBB87_412039; VI-NEXT:  ; %bb.1: ; %cmp.false12040; VI-NEXT:    s_and_b32 s4, s16, 0xff12041; VI-NEXT:    s_lshl_b32 s5, s17, 812042; VI-NEXT:    s_or_b32 s4, s4, s512043; VI-NEXT:    s_and_b32 s5, s18, 0xff12044; VI-NEXT:    s_lshl_b32 s6, s19, 812045; VI-NEXT:    s_or_b32 s5, s5, s612046; VI-NEXT:    s_and_b32 s4, s4, 0xffff12047; VI-NEXT:    s_lshl_b32 s5, s5, 1612048; VI-NEXT:    s_or_b32 s4, s4, s512049; VI-NEXT:    s_and_b32 s5, s20, 0xff12050; VI-NEXT:    s_lshl_b32 s6, s21, 812051; VI-NEXT:    s_or_b32 s5, s5, s612052; VI-NEXT:    s_and_b32 s6, s22, 0xff12053; VI-NEXT:    s_lshl_b32 s7, s23, 812054; VI-NEXT:    s_or_b32 s6, s6, s712055; VI-NEXT:    s_and_b32 s5, s5, 0xffff12056; VI-NEXT:    s_lshl_b32 s6, s6, 1612057; VI-NEXT:    s_or_b32 s5, s5, s612058; VI-NEXT:    s_cbranch_execnz .LBB87_312059; VI-NEXT:  .LBB87_2: ; %cmp.true12060; VI-NEXT:    s_add_i32 s16, s16, 312061; VI-NEXT:    s_and_b32 s4, s16, 0xff12062; VI-NEXT:    s_lshl_b32 s5, s17, 812063; VI-NEXT:    s_add_i32 s18, s18, 312064; VI-NEXT:    s_or_b32 s4, s5, s412065; VI-NEXT:    s_and_b32 s5, s18, 0xff12066; VI-NEXT:    s_lshl_b32 s6, s19, 812067; VI-NEXT:    s_addk_i32 s4, 0x30012068; VI-NEXT:    s_or_b32 s5, s6, s512069; VI-NEXT:    s_and_b32 s4, s4, 0xffff12070; VI-NEXT:    s_lshl_b32 s5, s5, 1612071; VI-NEXT:    s_add_i32 s20, s20, 312072; VI-NEXT:    s_or_b32 s4, s5, s412073; VI-NEXT:    s_and_b32 s5, s20, 0xff12074; VI-NEXT:    s_lshl_b32 s6, s21, 812075; VI-NEXT:    s_add_i32 s22, s22, 312076; VI-NEXT:    s_or_b32 s5, s6, s512077; VI-NEXT:    s_and_b32 s6, s22, 0xff12078; VI-NEXT:    s_lshl_b32 s7, s23, 812079; VI-NEXT:    s_addk_i32 s5, 0x30012080; VI-NEXT:    s_or_b32 s6, s7, s612081; VI-NEXT:    s_and_b32 s5, s5, 0xffff12082; VI-NEXT:    s_lshl_b32 s6, s6, 1612083; VI-NEXT:    s_or_b32 s5, s6, s512084; VI-NEXT:    s_add_i32 s4, s4, 0x300000012085; VI-NEXT:    s_add_i32 s5, s5, 0x300000012086; VI-NEXT:  .LBB87_3: ; %end12087; VI-NEXT:    v_mov_b32_e32 v0, s412088; VI-NEXT:    v_mov_b32_e32 v1, s512089; VI-NEXT:    s_setpc_b64 s[30:31]12090; VI-NEXT:  .LBB87_4:12091; VI-NEXT:    ; implicit-def: $sgpr4_sgpr512092; VI-NEXT:    s_branch .LBB87_212093;12094; GFX9-LABEL: bitcast_v8i8_to_v2f32_scalar:12095; GFX9:       ; %bb.0:12096; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12097; GFX9-NEXT:    s_cmp_lg_u32 s24, 012098; GFX9-NEXT:    s_cbranch_scc0 .LBB87_412099; GFX9-NEXT:  ; %bb.1: ; %cmp.false12100; GFX9-NEXT:    s_and_b32 s4, s16, 0xff12101; GFX9-NEXT:    s_lshl_b32 s5, s17, 812102; GFX9-NEXT:    s_or_b32 s4, s4, s512103; GFX9-NEXT:    s_and_b32 s5, s18, 0xff12104; GFX9-NEXT:    s_lshl_b32 s6, s19, 812105; GFX9-NEXT:    s_or_b32 s5, s5, s612106; GFX9-NEXT:    s_and_b32 s4, s4, 0xffff12107; GFX9-NEXT:    s_lshl_b32 s5, s5, 1612108; GFX9-NEXT:    s_or_b32 s4, s4, s512109; GFX9-NEXT:    s_and_b32 s5, s20, 0xff12110; GFX9-NEXT:    s_lshl_b32 s6, s21, 812111; GFX9-NEXT:    s_or_b32 s5, s5, s612112; GFX9-NEXT:    s_and_b32 s6, s22, 0xff12113; GFX9-NEXT:    s_lshl_b32 s7, s23, 812114; GFX9-NEXT:    s_or_b32 s6, s6, s712115; GFX9-NEXT:    s_and_b32 s5, s5, 0xffff12116; GFX9-NEXT:    s_lshl_b32 s6, s6, 1612117; GFX9-NEXT:    s_or_b32 s5, s5, s612118; GFX9-NEXT:    s_cbranch_execnz .LBB87_312119; GFX9-NEXT:  .LBB87_2: ; %cmp.true12120; GFX9-NEXT:    s_add_i32 s16, s16, 312121; GFX9-NEXT:    s_and_b32 s4, s16, 0xff12122; GFX9-NEXT:    s_lshl_b32 s5, s17, 812123; GFX9-NEXT:    s_add_i32 s18, s18, 312124; GFX9-NEXT:    s_or_b32 s4, s5, s412125; GFX9-NEXT:    s_and_b32 s5, s18, 0xff12126; GFX9-NEXT:    s_lshl_b32 s6, s19, 812127; GFX9-NEXT:    s_or_b32 s5, s6, s512128; GFX9-NEXT:    s_addk_i32 s4, 0x30012129; GFX9-NEXT:    s_addk_i32 s5, 0x30012130; GFX9-NEXT:    s_and_b32 s4, s4, 0xffff12131; GFX9-NEXT:    s_lshl_b32 s5, s5, 1612132; GFX9-NEXT:    s_add_i32 s20, s20, 312133; GFX9-NEXT:    s_or_b32 s4, s4, s512134; GFX9-NEXT:    s_and_b32 s5, s20, 0xff12135; GFX9-NEXT:    s_lshl_b32 s6, s21, 812136; GFX9-NEXT:    s_add_i32 s22, s22, 312137; GFX9-NEXT:    s_or_b32 s5, s6, s512138; GFX9-NEXT:    s_and_b32 s6, s22, 0xff12139; GFX9-NEXT:    s_lshl_b32 s7, s23, 812140; GFX9-NEXT:    s_or_b32 s6, s7, s612141; GFX9-NEXT:    s_addk_i32 s5, 0x30012142; GFX9-NEXT:    s_addk_i32 s6, 0x30012143; GFX9-NEXT:    s_and_b32 s5, s5, 0xffff12144; GFX9-NEXT:    s_lshl_b32 s6, s6, 1612145; GFX9-NEXT:    s_or_b32 s5, s5, s612146; GFX9-NEXT:  .LBB87_3: ; %end12147; GFX9-NEXT:    v_mov_b32_e32 v0, s412148; GFX9-NEXT:    v_mov_b32_e32 v1, s512149; GFX9-NEXT:    s_setpc_b64 s[30:31]12150; GFX9-NEXT:  .LBB87_4:12151; GFX9-NEXT:    ; implicit-def: $sgpr4_sgpr512152; GFX9-NEXT:    s_branch .LBB87_212153;12154; GFX11-LABEL: bitcast_v8i8_to_v2f32_scalar:12155; GFX11:       ; %bb.0:12156; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12157; GFX11-NEXT:    s_cmp_lg_u32 s20, 012158; GFX11-NEXT:    s_mov_b32 s6, 012159; GFX11-NEXT:    s_cbranch_scc0 .LBB87_412160; GFX11-NEXT:  ; %bb.1: ; %cmp.false12161; GFX11-NEXT:    s_and_b32 s4, s0, 0xff12162; GFX11-NEXT:    s_lshl_b32 s5, s1, 812163; GFX11-NEXT:    s_and_b32 s7, s2, 0xff12164; GFX11-NEXT:    s_lshl_b32 s8, s3, 812165; GFX11-NEXT:    s_or_b32 s4, s4, s512166; GFX11-NEXT:    s_or_b32 s5, s7, s812167; GFX11-NEXT:    s_and_b32 s7, s16, 0xff12168; GFX11-NEXT:    s_lshl_b32 s8, s17, 812169; GFX11-NEXT:    s_and_b32 s9, s18, 0xff12170; GFX11-NEXT:    s_lshl_b32 s10, s19, 812171; GFX11-NEXT:    s_or_b32 s7, s7, s812172; GFX11-NEXT:    s_or_b32 s8, s9, s1012173; GFX11-NEXT:    s_and_b32 s4, s4, 0xffff12174; GFX11-NEXT:    s_lshl_b32 s5, s5, 1612175; GFX11-NEXT:    s_and_b32 s7, s7, 0xffff12176; GFX11-NEXT:    s_lshl_b32 s8, s8, 1612177; GFX11-NEXT:    s_or_b32 s4, s4, s512178; GFX11-NEXT:    s_or_b32 s5, s7, s812179; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s612180; GFX11-NEXT:    s_cbranch_vccnz .LBB87_312181; GFX11-NEXT:  .LBB87_2: ; %cmp.true12182; GFX11-NEXT:    s_add_i32 s0, s0, 312183; GFX11-NEXT:    s_lshl_b32 s1, s1, 812184; GFX11-NEXT:    s_and_b32 s0, s0, 0xff12185; GFX11-NEXT:    s_add_i32 s2, s2, 312186; GFX11-NEXT:    s_or_b32 s0, s1, s012187; GFX11-NEXT:    s_and_b32 s1, s2, 0xff12188; GFX11-NEXT:    s_lshl_b32 s2, s3, 812189; GFX11-NEXT:    s_add_i32 s16, s16, 312190; GFX11-NEXT:    s_add_i32 s18, s18, 312191; GFX11-NEXT:    s_or_b32 s1, s2, s112192; GFX11-NEXT:    s_and_b32 s2, s16, 0xff12193; GFX11-NEXT:    s_lshl_b32 s3, s17, 812194; GFX11-NEXT:    s_and_b32 s4, s18, 0xff12195; GFX11-NEXT:    s_lshl_b32 s5, s19, 812196; GFX11-NEXT:    s_or_b32 s2, s3, s212197; GFX11-NEXT:    s_or_b32 s3, s5, s412198; GFX11-NEXT:    s_addk_i32 s0, 0x30012199; GFX11-NEXT:    s_addk_i32 s1, 0x30012200; GFX11-NEXT:    s_addk_i32 s2, 0x30012201; GFX11-NEXT:    s_addk_i32 s3, 0x30012202; GFX11-NEXT:    s_and_b32 s0, s0, 0xffff12203; GFX11-NEXT:    s_lshl_b32 s1, s1, 1612204; GFX11-NEXT:    s_and_b32 s2, s2, 0xffff12205; GFX11-NEXT:    s_lshl_b32 s3, s3, 1612206; GFX11-NEXT:    s_or_b32 s4, s0, s112207; GFX11-NEXT:    s_or_b32 s5, s2, s312208; GFX11-NEXT:  .LBB87_3: ; %end12209; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)12210; GFX11-NEXT:    v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s512211; GFX11-NEXT:    s_setpc_b64 s[30:31]12212; GFX11-NEXT:  .LBB87_4:12213; GFX11-NEXT:    ; implicit-def: $sgpr4_sgpr512214; GFX11-NEXT:    s_branch .LBB87_212215  %cmp = icmp eq i32 %b, 012216  br i1 %cmp, label %cmp.true, label %cmp.false12217 12218cmp.true:12219  %a1 = add <8 x i8> %a, splat (i8 3)12220  %a2 = bitcast <8 x i8> %a1 to <2 x float>12221  br label %end12222 12223cmp.false:12224  %a3 = bitcast <8 x i8> %a to <2 x float>12225  br label %end12226 12227end:12228  %phi = phi <2 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]12229  ret <2 x float> %phi12230}12231 12232define <4 x half> @bitcast_v4i16_to_v4f16(<4 x i16> %a, i32 %b) {12233; SI-LABEL: bitcast_v4i16_to_v4f16:12234; SI:       ; %bb.0:12235; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12236; SI-NEXT:    v_mov_b32_e32 v8, v312237; SI-NEXT:    v_mov_b32_e32 v5, v212238; SI-NEXT:    v_mov_b32_e32 v6, v112239; SI-NEXT:    v_mov_b32_e32 v7, v012240; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v412241; SI-NEXT:    ; implicit-def: $vgpr012242; SI-NEXT:    ; implicit-def: $vgpr112243; SI-NEXT:    ; implicit-def: $vgpr212244; SI-NEXT:    ; implicit-def: $vgpr312245; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc12246; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]12247; SI-NEXT:    s_cbranch_execnz .LBB88_312248; SI-NEXT:  ; %bb.1: ; %Flow12249; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]12250; SI-NEXT:    s_cbranch_execnz .LBB88_412251; SI-NEXT:  .LBB88_2: ; %end12252; SI-NEXT:    s_or_b64 exec, exec, s[4:5]12253; SI-NEXT:    s_setpc_b64 s[30:31]12254; SI-NEXT:  .LBB88_3: ; %cmp.false12255; SI-NEXT:    v_cvt_f32_f16_e32 v0, v712256; SI-NEXT:    v_cvt_f32_f16_e32 v1, v612257; SI-NEXT:    v_cvt_f32_f16_e32 v2, v512258; SI-NEXT:    v_cvt_f32_f16_e32 v3, v812259; SI-NEXT:    ; implicit-def: $vgpr812260; SI-NEXT:    ; implicit-def: $vgpr512261; SI-NEXT:    ; implicit-def: $vgpr612262; SI-NEXT:    ; implicit-def: $vgpr712263; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]12264; SI-NEXT:    s_cbranch_execz .LBB88_212265; SI-NEXT:  .LBB88_4: ; %cmp.true12266; SI-NEXT:    v_add_i32_e32 v3, vcc, 3, v812267; SI-NEXT:    v_add_i32_e32 v2, vcc, 3, v512268; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v612269; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v712270; SI-NEXT:    v_cvt_f32_f16_e32 v0, v012271; SI-NEXT:    v_cvt_f32_f16_e32 v1, v112272; SI-NEXT:    v_cvt_f32_f16_e32 v2, v212273; SI-NEXT:    v_cvt_f32_f16_e32 v3, v312274; SI-NEXT:    s_or_b64 exec, exec, s[4:5]12275; SI-NEXT:    s_setpc_b64 s[30:31]12276;12277; VI-LABEL: bitcast_v4i16_to_v4f16:12278; VI:       ; %bb.0:12279; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12280; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v212281; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc12282; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]12283; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]12284; VI-NEXT:  ; %bb.1: ; %cmp.true12285; VI-NEXT:    v_mov_b32_e32 v2, 312286; VI-NEXT:    v_add_u16_sdwa v3, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD12287; VI-NEXT:    v_add_u16_sdwa v2, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD12288; VI-NEXT:    v_add_u16_e32 v1, 3, v112289; VI-NEXT:    v_add_u16_e32 v0, 3, v012290; VI-NEXT:    v_or_b32_e32 v1, v1, v212291; VI-NEXT:    v_or_b32_e32 v0, v0, v312292; VI-NEXT:  ; %bb.2: ; %end12293; VI-NEXT:    s_or_b64 exec, exec, s[4:5]12294; VI-NEXT:    s_setpc_b64 s[30:31]12295;12296; GFX9-LABEL: bitcast_v4i16_to_v4f16:12297; GFX9:       ; %bb.0:12298; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12299; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v212300; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc12301; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]12302; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]12303; GFX9-NEXT:  ; %bb.1: ; %cmp.true12304; GFX9-NEXT:    v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]12305; GFX9-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]12306; GFX9-NEXT:  ; %bb.2: ; %end12307; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]12308; GFX9-NEXT:    s_setpc_b64 s[30:31]12309;12310; GFX11-LABEL: bitcast_v4i16_to_v4f16:12311; GFX11:       ; %bb.0:12312; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12313; GFX11-NEXT:    s_mov_b32 s0, exec_lo12314; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v212315; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s012316; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)12317; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s012318; GFX11-NEXT:  ; %bb.1: ; %cmp.true12319; GFX11-NEXT:    v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]12320; GFX11-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]12321; GFX11-NEXT:  ; %bb.2: ; %end12322; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s012323; GFX11-NEXT:    s_setpc_b64 s[30:31]12324  %cmp = icmp eq i32 %b, 012325  br i1 %cmp, label %cmp.true, label %cmp.false12326 12327cmp.true:12328  %a1 = add <4 x i16> %a, splat (i16 3)12329  %a2 = bitcast <4 x i16> %a1 to <4 x half>12330  br label %end12331 12332cmp.false:12333  %a3 = bitcast <4 x i16> %a to <4 x half>12334  br label %end12335 12336end:12337  %phi = phi <4 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]12338  ret <4 x half> %phi12339}12340 12341define inreg <4 x half> @bitcast_v4i16_to_v4f16_scalar(<4 x i16> inreg %a, i32 inreg %b) {12342; SI-LABEL: bitcast_v4i16_to_v4f16_scalar:12343; SI:       ; %bb.0:12344; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12345; SI-NEXT:    s_cmp_lg_u32 s20, 012346; SI-NEXT:    s_cbranch_scc0 .LBB89_412347; SI-NEXT:  ; %bb.1: ; %cmp.false12348; SI-NEXT:    v_cvt_f32_f16_e32 v0, s1612349; SI-NEXT:    v_cvt_f32_f16_e32 v1, s1712350; SI-NEXT:    v_cvt_f32_f16_e32 v2, s1812351; SI-NEXT:    v_cvt_f32_f16_e32 v3, s1912352; SI-NEXT:    s_cbranch_execnz .LBB89_312353; SI-NEXT:  .LBB89_2: ; %cmp.true12354; SI-NEXT:    s_add_i32 s19, s19, 312355; SI-NEXT:    s_add_i32 s18, s18, 312356; SI-NEXT:    s_add_i32 s17, s17, 312357; SI-NEXT:    s_add_i32 s16, s16, 312358; SI-NEXT:    v_cvt_f32_f16_e32 v0, s1612359; SI-NEXT:    v_cvt_f32_f16_e32 v1, s1712360; SI-NEXT:    v_cvt_f32_f16_e32 v2, s1812361; SI-NEXT:    v_cvt_f32_f16_e32 v3, s1912362; SI-NEXT:  .LBB89_3: ; %end12363; SI-NEXT:    s_setpc_b64 s[30:31]12364; SI-NEXT:  .LBB89_4:12365; SI-NEXT:    ; implicit-def: $vgpr012366; SI-NEXT:    ; implicit-def: $vgpr112367; SI-NEXT:    ; implicit-def: $vgpr212368; SI-NEXT:    ; implicit-def: $vgpr312369; SI-NEXT:    s_branch .LBB89_212370;12371; VI-LABEL: bitcast_v4i16_to_v4f16_scalar:12372; VI:       ; %bb.0:12373; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12374; VI-NEXT:    s_cmp_lg_u32 s18, 012375; VI-NEXT:    s_cbranch_scc0 .LBB89_412376; VI-NEXT:  ; %bb.1: ; %cmp.false12377; VI-NEXT:    s_cbranch_execnz .LBB89_312378; VI-NEXT:  .LBB89_2: ; %cmp.true12379; VI-NEXT:    s_add_i32 s5, s16, 312380; VI-NEXT:    s_add_i32 s7, s17, 312381; VI-NEXT:    s_and_b32 s4, s16, 0xffff000012382; VI-NEXT:    s_and_b32 s6, s17, 0xffff000012383; VI-NEXT:    s_and_b32 s7, s7, 0xffff12384; VI-NEXT:    s_and_b32 s5, s5, 0xffff12385; VI-NEXT:    s_or_b32 s6, s6, s712386; VI-NEXT:    s_or_b32 s4, s4, s512387; VI-NEXT:    s_add_i32 s17, s6, 0x3000012388; VI-NEXT:    s_add_i32 s16, s4, 0x3000012389; VI-NEXT:  .LBB89_3: ; %end12390; VI-NEXT:    v_mov_b32_e32 v0, s1612391; VI-NEXT:    v_mov_b32_e32 v1, s1712392; VI-NEXT:    s_setpc_b64 s[30:31]12393; VI-NEXT:  .LBB89_4:12394; VI-NEXT:    s_branch .LBB89_212395;12396; GFX9-LABEL: bitcast_v4i16_to_v4f16_scalar:12397; GFX9:       ; %bb.0:12398; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12399; GFX9-NEXT:    s_cmp_lg_u32 s18, 012400; GFX9-NEXT:    s_cbranch_scc0 .LBB89_312401; GFX9-NEXT:  ; %bb.1: ; %cmp.false12402; GFX9-NEXT:    s_cbranch_execnz .LBB89_412403; GFX9-NEXT:  .LBB89_2: ; %cmp.true12404; GFX9-NEXT:    v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]12405; GFX9-NEXT:    v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]12406; GFX9-NEXT:    s_setpc_b64 s[30:31]12407; GFX9-NEXT:  .LBB89_3:12408; GFX9-NEXT:    s_branch .LBB89_212409; GFX9-NEXT:  .LBB89_4:12410; GFX9-NEXT:    v_mov_b32_e32 v0, s1612411; GFX9-NEXT:    v_mov_b32_e32 v1, s1712412; GFX9-NEXT:    s_setpc_b64 s[30:31]12413;12414; GFX11-LABEL: bitcast_v4i16_to_v4f16_scalar:12415; GFX11:       ; %bb.0:12416; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12417; GFX11-NEXT:    s_cmp_lg_u32 s2, 012418; GFX11-NEXT:    s_mov_b32 s2, 012419; GFX11-NEXT:    s_cbranch_scc0 .LBB89_312420; GFX11-NEXT:  ; %bb.1: ; %Flow12421; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s212422; GFX11-NEXT:    s_cbranch_vccnz .LBB89_412423; GFX11-NEXT:  .LBB89_2: ; %cmp.true12424; GFX11-NEXT:    v_pk_add_u16 v1, s1, 3 op_sel_hi:[1,0]12425; GFX11-NEXT:    v_pk_add_u16 v0, s0, 3 op_sel_hi:[1,0]12426; GFX11-NEXT:    s_setpc_b64 s[30:31]12427; GFX11-NEXT:  .LBB89_3:12428; GFX11-NEXT:    s_branch .LBB89_212429; GFX11-NEXT:  .LBB89_4:12430; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s112431; GFX11-NEXT:    s_setpc_b64 s[30:31]12432  %cmp = icmp eq i32 %b, 012433  br i1 %cmp, label %cmp.true, label %cmp.false12434 12435cmp.true:12436  %a1 = add <4 x i16> %a, splat (i16 3)12437  %a2 = bitcast <4 x i16> %a1 to <4 x half>12438  br label %end12439 12440cmp.false:12441  %a3 = bitcast <4 x i16> %a to <4 x half>12442  br label %end12443 12444end:12445  %phi = phi <4 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]12446  ret <4 x half> %phi12447}12448 12449define <4 x i16> @bitcast_v4f16_to_v4i16(<4 x half> %a, i32 %b) {12450; SI-LABEL: bitcast_v4f16_to_v4i16:12451; SI:       ; %bb.0:12452; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12453; SI-NEXT:    v_cvt_f16_f32_e32 v0, v012454; SI-NEXT:    v_cvt_f16_f32_e32 v1, v112455; SI-NEXT:    v_cvt_f16_f32_e32 v2, v212456; SI-NEXT:    v_cvt_f16_f32_e32 v3, v312457; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v412458; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc12459; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]12460; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]12461; SI-NEXT:    s_cbranch_execz .LBB90_212462; SI-NEXT:  ; %bb.1: ; %cmp.true12463; SI-NEXT:    v_cvt_f32_f16_e32 v3, v312464; SI-NEXT:    v_cvt_f32_f16_e32 v1, v112465; SI-NEXT:    v_cvt_f32_f16_e32 v2, v212466; SI-NEXT:    v_cvt_f32_f16_e32 v0, v012467; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v312468; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v112469; SI-NEXT:    v_cvt_f16_f32_e32 v3, v312470; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v212471; SI-NEXT:    v_add_f32_e32 v0, 0x38000000, v012472; SI-NEXT:    v_cvt_f16_f32_e32 v1, v112473; SI-NEXT:    v_cvt_f16_f32_e32 v2, v212474; SI-NEXT:    v_cvt_f16_f32_e32 v0, v012475; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v312476; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v112477; SI-NEXT:    v_or_b32_e32 v2, v2, v412478; SI-NEXT:    v_or_b32_e32 v0, v0, v112479; SI-NEXT:    v_alignbit_b32 v1, v2, v1, 1612480; SI-NEXT:  .LBB90_2: ; %end12481; SI-NEXT:    s_or_b64 exec, exec, s[4:5]12482; SI-NEXT:    s_setpc_b64 s[30:31]12483;12484; VI-LABEL: bitcast_v4f16_to_v4i16:12485; VI:       ; %bb.0:12486; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12487; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v212488; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc12489; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]12490; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]12491; VI-NEXT:  ; %bb.1: ; %cmp.true12492; VI-NEXT:    v_mov_b32_e32 v3, 0x20012493; VI-NEXT:    v_add_f16_e32 v2, 0x200, v012494; VI-NEXT:    v_add_f16_sdwa v0, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD12495; VI-NEXT:    v_add_f16_e32 v4, 0x200, v112496; VI-NEXT:    v_add_f16_sdwa v1, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD12497; VI-NEXT:    v_or_b32_e32 v1, v4, v112498; VI-NEXT:    v_or_b32_e32 v0, v2, v012499; VI-NEXT:  ; %bb.2: ; %end12500; VI-NEXT:    s_or_b64 exec, exec, s[4:5]12501; VI-NEXT:    s_setpc_b64 s[30:31]12502;12503; GFX9-LABEL: bitcast_v4f16_to_v4i16:12504; GFX9:       ; %bb.0:12505; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12506; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v212507; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc12508; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]12509; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]12510; GFX9-NEXT:  ; %bb.1: ; %cmp.true12511; GFX9-NEXT:    s_movk_i32 s6, 0x20012512; GFX9-NEXT:    v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]12513; GFX9-NEXT:    v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]12514; GFX9-NEXT:  ; %bb.2: ; %end12515; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]12516; GFX9-NEXT:    s_setpc_b64 s[30:31]12517;12518; GFX11-LABEL: bitcast_v4f16_to_v4i16:12519; GFX11:       ; %bb.0:12520; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12521; GFX11-NEXT:    s_mov_b32 s0, exec_lo12522; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v212523; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s012524; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)12525; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s012526; GFX11-NEXT:  ; %bb.1: ; %cmp.true12527; GFX11-NEXT:    v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]12528; GFX11-NEXT:    v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]12529; GFX11-NEXT:  ; %bb.2: ; %end12530; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s012531; GFX11-NEXT:    s_setpc_b64 s[30:31]12532  %cmp = icmp eq i32 %b, 012533  br i1 %cmp, label %cmp.true, label %cmp.false12534 12535cmp.true:12536  %a1 = fadd <4 x half> %a, splat (half 0xH0200)12537  %a2 = bitcast <4 x half> %a1 to <4 x i16>12538  br label %end12539 12540cmp.false:12541  %a3 = bitcast <4 x half> %a to <4 x i16>12542  br label %end12543 12544end:12545  %phi = phi <4 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]12546  ret <4 x i16> %phi12547}12548 12549define inreg <4 x i16> @bitcast_v4f16_to_v4i16_scalar(<4 x half> inreg %a, i32 inreg %b) {12550; SI-LABEL: bitcast_v4f16_to_v4i16_scalar:12551; SI:       ; %bb.0:12552; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12553; SI-NEXT:    v_cvt_f16_f32_e32 v0, s1612554; SI-NEXT:    v_cvt_f16_f32_e32 v4, s1712555; SI-NEXT:    v_cvt_f16_f32_e32 v2, s1812556; SI-NEXT:    v_cvt_f16_f32_e32 v3, s1912557; SI-NEXT:    s_cmp_lg_u32 s20, 012558; SI-NEXT:    s_cbranch_scc0 .LBB91_412559; SI-NEXT:  ; %bb.1: ; %cmp.false12560; SI-NEXT:    s_cbranch_execnz .LBB91_312561; SI-NEXT:  .LBB91_2: ; %cmp.true12562; SI-NEXT:    v_cvt_f32_f16_e32 v3, v312563; SI-NEXT:    v_cvt_f32_f16_e32 v1, v412564; SI-NEXT:    v_cvt_f32_f16_e32 v2, v212565; SI-NEXT:    v_cvt_f32_f16_e32 v0, v012566; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v312567; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v112568; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v212569; SI-NEXT:    v_cvt_f16_f32_e32 v3, v312570; SI-NEXT:    v_cvt_f16_f32_e32 v1, v112571; SI-NEXT:    v_cvt_f16_f32_e32 v2, v212572; SI-NEXT:    v_add_f32_e32 v0, 0x38000000, v012573; SI-NEXT:    v_cvt_f16_f32_e32 v0, v012574; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v312575; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v112576; SI-NEXT:    v_or_b32_e32 v2, v2, v412577; SI-NEXT:    v_lshr_b64 v[4:5], v[1:2], 1612578; SI-NEXT:    v_or_b32_e32 v0, v0, v112579; SI-NEXT:  .LBB91_3: ; %end12580; SI-NEXT:    v_mov_b32_e32 v1, v412581; SI-NEXT:    s_setpc_b64 s[30:31]12582; SI-NEXT:  .LBB91_4:12583; SI-NEXT:    s_branch .LBB91_212584;12585; VI-LABEL: bitcast_v4f16_to_v4i16_scalar:12586; VI:       ; %bb.0:12587; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12588; VI-NEXT:    s_cmp_lg_u32 s18, 012589; VI-NEXT:    s_cbranch_scc0 .LBB91_312590; VI-NEXT:  ; %bb.1: ; %cmp.false12591; VI-NEXT:    s_cbranch_execnz .LBB91_412592; VI-NEXT:  .LBB91_2: ; %cmp.true12593; VI-NEXT:    s_lshr_b32 s4, s16, 1612594; VI-NEXT:    v_mov_b32_e32 v1, s412595; VI-NEXT:    s_lshr_b32 s4, s17, 1612596; VI-NEXT:    v_mov_b32_e32 v0, 0x20012597; VI-NEXT:    v_mov_b32_e32 v4, s412598; VI-NEXT:    v_add_f16_e32 v2, s16, v012599; VI-NEXT:    v_add_f16_sdwa v3, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD12600; VI-NEXT:    v_add_f16_e32 v1, s17, v012601; VI-NEXT:    v_add_f16_sdwa v0, v4, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD12602; VI-NEXT:    v_or_b32_e32 v1, v1, v012603; VI-NEXT:    v_or_b32_e32 v0, v2, v312604; VI-NEXT:    s_setpc_b64 s[30:31]12605; VI-NEXT:  .LBB91_3:12606; VI-NEXT:    s_branch .LBB91_212607; VI-NEXT:  .LBB91_4:12608; VI-NEXT:    v_mov_b32_e32 v0, s1612609; VI-NEXT:    v_mov_b32_e32 v1, s1712610; VI-NEXT:    s_setpc_b64 s[30:31]12611;12612; GFX9-LABEL: bitcast_v4f16_to_v4i16_scalar:12613; GFX9:       ; %bb.0:12614; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12615; GFX9-NEXT:    s_cmp_lg_u32 s18, 012616; GFX9-NEXT:    s_cbranch_scc0 .LBB91_312617; GFX9-NEXT:  ; %bb.1: ; %cmp.false12618; GFX9-NEXT:    s_cbranch_execnz .LBB91_412619; GFX9-NEXT:  .LBB91_2: ; %cmp.true12620; GFX9-NEXT:    v_mov_b32_e32 v0, 0x20012621; GFX9-NEXT:    v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]12622; GFX9-NEXT:    v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]12623; GFX9-NEXT:    s_setpc_b64 s[30:31]12624; GFX9-NEXT:  .LBB91_3:12625; GFX9-NEXT:    s_branch .LBB91_212626; GFX9-NEXT:  .LBB91_4:12627; GFX9-NEXT:    v_mov_b32_e32 v0, s1612628; GFX9-NEXT:    v_mov_b32_e32 v1, s1712629; GFX9-NEXT:    s_setpc_b64 s[30:31]12630;12631; GFX11-LABEL: bitcast_v4f16_to_v4i16_scalar:12632; GFX11:       ; %bb.0:12633; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12634; GFX11-NEXT:    s_cmp_lg_u32 s2, 012635; GFX11-NEXT:    s_mov_b32 s2, 012636; GFX11-NEXT:    s_cbranch_scc0 .LBB91_312637; GFX11-NEXT:  ; %bb.1: ; %Flow12638; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s212639; GFX11-NEXT:    s_cbranch_vccnz .LBB91_412640; GFX11-NEXT:  .LBB91_2: ; %cmp.true12641; GFX11-NEXT:    v_pk_add_f16 v1, 0x200, s1 op_sel_hi:[0,1]12642; GFX11-NEXT:    v_pk_add_f16 v0, 0x200, s0 op_sel_hi:[0,1]12643; GFX11-NEXT:    s_setpc_b64 s[30:31]12644; GFX11-NEXT:  .LBB91_3:12645; GFX11-NEXT:    s_branch .LBB91_212646; GFX11-NEXT:  .LBB91_4:12647; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s112648; GFX11-NEXT:    s_setpc_b64 s[30:31]12649  %cmp = icmp eq i32 %b, 012650  br i1 %cmp, label %cmp.true, label %cmp.false12651 12652cmp.true:12653  %a1 = fadd <4 x half> %a, splat (half 0xH0200)12654  %a2 = bitcast <4 x half> %a1 to <4 x i16>12655  br label %end12656 12657cmp.false:12658  %a3 = bitcast <4 x half> %a to <4 x i16>12659  br label %end12660 12661end:12662  %phi = phi <4 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]12663  ret <4 x i16> %phi12664}12665 12666define <4 x bfloat> @bitcast_v4i16_to_v4bf16(<4 x i16> %a, i32 %b) {12667; SI-LABEL: bitcast_v4i16_to_v4bf16:12668; SI:       ; %bb.0:12669; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12670; SI-NEXT:    v_mov_b32_e32 v6, v212671; SI-NEXT:    v_mov_b32_e32 v5, v012672; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v412673; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v112674; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v312675; SI-NEXT:    ; implicit-def: $vgpr012676; SI-NEXT:    ; implicit-def: $vgpr212677; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc12678; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]12679; SI-NEXT:    s_cbranch_execnz .LBB92_312680; SI-NEXT:  ; %bb.1: ; %Flow12681; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]12682; SI-NEXT:    s_cbranch_execnz .LBB92_412683; SI-NEXT:  .LBB92_2: ; %end12684; SI-NEXT:    s_or_b64 exec, exec, s[4:5]12685; SI-NEXT:    s_setpc_b64 s[30:31]12686; SI-NEXT:  .LBB92_3: ; %cmp.false12687; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v512688; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v612689; SI-NEXT:    ; implicit-def: $vgpr612690; SI-NEXT:    ; implicit-def: $vgpr512691; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]12692; SI-NEXT:    s_cbranch_execz .LBB92_212693; SI-NEXT:  .LBB92_4: ; %cmp.true12694; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v612695; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v012696; SI-NEXT:    v_or_b32_e32 v0, v3, v012697; SI-NEXT:    v_add_i32_e32 v2, vcc, 0x30000, v012698; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v512699; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v012700; SI-NEXT:    v_or_b32_e32 v0, v1, v012701; SI-NEXT:    v_add_i32_e32 v0, vcc, 0x30000, v012702; SI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v012703; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v012704; SI-NEXT:    v_and_b32_e32 v3, 0xffff0000, v212705; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v212706; SI-NEXT:    s_or_b64 exec, exec, s[4:5]12707; SI-NEXT:    s_setpc_b64 s[30:31]12708;12709; VI-LABEL: bitcast_v4i16_to_v4bf16:12710; VI:       ; %bb.0:12711; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12712; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v212713; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc12714; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]12715; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]12716; VI-NEXT:  ; %bb.1: ; %cmp.true12717; VI-NEXT:    v_mov_b32_e32 v2, 312718; VI-NEXT:    v_add_u16_sdwa v3, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD12719; VI-NEXT:    v_add_u16_sdwa v2, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD12720; VI-NEXT:    v_add_u16_e32 v1, 3, v112721; VI-NEXT:    v_add_u16_e32 v0, 3, v012722; VI-NEXT:    v_or_b32_e32 v1, v1, v212723; VI-NEXT:    v_or_b32_e32 v0, v0, v312724; VI-NEXT:  ; %bb.2: ; %end12725; VI-NEXT:    s_or_b64 exec, exec, s[4:5]12726; VI-NEXT:    s_setpc_b64 s[30:31]12727;12728; GFX9-LABEL: bitcast_v4i16_to_v4bf16:12729; GFX9:       ; %bb.0:12730; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12731; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v212732; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc12733; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]12734; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]12735; GFX9-NEXT:  ; %bb.1: ; %cmp.true12736; GFX9-NEXT:    v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]12737; GFX9-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]12738; GFX9-NEXT:  ; %bb.2: ; %end12739; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]12740; GFX9-NEXT:    s_setpc_b64 s[30:31]12741;12742; GFX11-LABEL: bitcast_v4i16_to_v4bf16:12743; GFX11:       ; %bb.0:12744; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12745; GFX11-NEXT:    s_mov_b32 s0, exec_lo12746; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v212747; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s012748; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)12749; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s012750; GFX11-NEXT:  ; %bb.1: ; %cmp.true12751; GFX11-NEXT:    v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]12752; GFX11-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]12753; GFX11-NEXT:  ; %bb.2: ; %end12754; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s012755; GFX11-NEXT:    s_setpc_b64 s[30:31]12756  %cmp = icmp eq i32 %b, 012757  br i1 %cmp, label %cmp.true, label %cmp.false12758 12759cmp.true:12760  %a1 = add <4 x i16> %a, splat (i16 3)12761  %a2 = bitcast <4 x i16> %a1 to <4 x bfloat>12762  br label %end12763 12764cmp.false:12765  %a3 = bitcast <4 x i16> %a to <4 x bfloat>12766  br label %end12767 12768end:12769  %phi = phi <4 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ]12770  ret <4 x bfloat> %phi12771}12772 12773define inreg <4 x bfloat> @bitcast_v4i16_to_v4bf16_scalar(<4 x i16> inreg %a, i32 inreg %b) {12774; SI-LABEL: bitcast_v4i16_to_v4bf16_scalar:12775; SI:       ; %bb.0:12776; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12777; SI-NEXT:    s_cmp_lg_u32 s20, 012778; SI-NEXT:    s_cbranch_scc0 .LBB93_412779; SI-NEXT:  ; %bb.1: ; %cmp.false12780; SI-NEXT:    s_lshl_b32 s6, s16, 1612781; SI-NEXT:    s_lshl_b32 s7, s17, 1612782; SI-NEXT:    s_lshl_b32 s9, s18, 1612783; SI-NEXT:    s_lshl_b32 s8, s19, 1612784; SI-NEXT:    s_cbranch_execnz .LBB93_312785; SI-NEXT:  .LBB93_2: ; %cmp.true12786; SI-NEXT:    s_add_i32 s18, s18, 312787; SI-NEXT:    s_and_b32 s4, s18, 0xffff12788; SI-NEXT:    s_lshl_b32 s5, s19, 1612789; SI-NEXT:    s_add_i32 s16, s16, 312790; SI-NEXT:    s_or_b32 s4, s5, s412791; SI-NEXT:    s_and_b32 s5, s16, 0xffff12792; SI-NEXT:    s_lshl_b32 s6, s17, 1612793; SI-NEXT:    s_or_b32 s5, s6, s512794; SI-NEXT:    s_add_i32 s4, s4, 0x3000012795; SI-NEXT:    s_add_i32 s5, s5, 0x3000012796; SI-NEXT:    s_and_b32 s7, s5, 0xffff000012797; SI-NEXT:    s_lshl_b32 s6, s5, 1612798; SI-NEXT:    s_and_b32 s8, s4, 0xffff000012799; SI-NEXT:    s_lshl_b32 s9, s4, 1612800; SI-NEXT:  .LBB93_3: ; %end12801; SI-NEXT:    v_mov_b32_e32 v0, s612802; SI-NEXT:    v_mov_b32_e32 v1, s712803; SI-NEXT:    v_mov_b32_e32 v2, s912804; SI-NEXT:    v_mov_b32_e32 v3, s812805; SI-NEXT:    s_setpc_b64 s[30:31]12806; SI-NEXT:  .LBB93_4:12807; SI-NEXT:    ; implicit-def: $sgpr612808; SI-NEXT:    ; implicit-def: $sgpr712809; SI-NEXT:    ; implicit-def: $sgpr912810; SI-NEXT:    ; implicit-def: $sgpr812811; SI-NEXT:    s_branch .LBB93_212812;12813; VI-LABEL: bitcast_v4i16_to_v4bf16_scalar:12814; VI:       ; %bb.0:12815; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12816; VI-NEXT:    s_cmp_lg_u32 s18, 012817; VI-NEXT:    s_cbranch_scc0 .LBB93_412818; VI-NEXT:  ; %bb.1: ; %cmp.false12819; VI-NEXT:    s_cbranch_execnz .LBB93_312820; VI-NEXT:  .LBB93_2: ; %cmp.true12821; VI-NEXT:    s_add_i32 s5, s16, 312822; VI-NEXT:    s_add_i32 s7, s17, 312823; VI-NEXT:    s_and_b32 s4, s16, 0xffff000012824; VI-NEXT:    s_and_b32 s6, s17, 0xffff000012825; VI-NEXT:    s_and_b32 s7, s7, 0xffff12826; VI-NEXT:    s_and_b32 s5, s5, 0xffff12827; VI-NEXT:    s_or_b32 s6, s6, s712828; VI-NEXT:    s_or_b32 s4, s4, s512829; VI-NEXT:    s_add_i32 s17, s6, 0x3000012830; VI-NEXT:    s_add_i32 s16, s4, 0x3000012831; VI-NEXT:  .LBB93_3: ; %end12832; VI-NEXT:    v_mov_b32_e32 v0, s1612833; VI-NEXT:    v_mov_b32_e32 v1, s1712834; VI-NEXT:    s_setpc_b64 s[30:31]12835; VI-NEXT:  .LBB93_4:12836; VI-NEXT:    s_branch .LBB93_212837;12838; GFX9-LABEL: bitcast_v4i16_to_v4bf16_scalar:12839; GFX9:       ; %bb.0:12840; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12841; GFX9-NEXT:    s_cmp_lg_u32 s18, 012842; GFX9-NEXT:    s_cbranch_scc0 .LBB93_312843; GFX9-NEXT:  ; %bb.1: ; %cmp.false12844; GFX9-NEXT:    s_cbranch_execnz .LBB93_412845; GFX9-NEXT:  .LBB93_2: ; %cmp.true12846; GFX9-NEXT:    v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]12847; GFX9-NEXT:    v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]12848; GFX9-NEXT:    s_setpc_b64 s[30:31]12849; GFX9-NEXT:  .LBB93_3:12850; GFX9-NEXT:    s_branch .LBB93_212851; GFX9-NEXT:  .LBB93_4:12852; GFX9-NEXT:    v_mov_b32_e32 v0, s1612853; GFX9-NEXT:    v_mov_b32_e32 v1, s1712854; GFX9-NEXT:    s_setpc_b64 s[30:31]12855;12856; GFX11-LABEL: bitcast_v4i16_to_v4bf16_scalar:12857; GFX11:       ; %bb.0:12858; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12859; GFX11-NEXT:    s_cmp_lg_u32 s2, 012860; GFX11-NEXT:    s_mov_b32 s2, 012861; GFX11-NEXT:    s_cbranch_scc0 .LBB93_312862; GFX11-NEXT:  ; %bb.1: ; %Flow12863; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s212864; GFX11-NEXT:    s_cbranch_vccnz .LBB93_412865; GFX11-NEXT:  .LBB93_2: ; %cmp.true12866; GFX11-NEXT:    v_pk_add_u16 v1, s1, 3 op_sel_hi:[1,0]12867; GFX11-NEXT:    v_pk_add_u16 v0, s0, 3 op_sel_hi:[1,0]12868; GFX11-NEXT:    s_setpc_b64 s[30:31]12869; GFX11-NEXT:  .LBB93_3:12870; GFX11-NEXT:    s_branch .LBB93_212871; GFX11-NEXT:  .LBB93_4:12872; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s112873; GFX11-NEXT:    s_setpc_b64 s[30:31]12874  %cmp = icmp eq i32 %b, 012875  br i1 %cmp, label %cmp.true, label %cmp.false12876 12877cmp.true:12878  %a1 = add <4 x i16> %a, splat (i16 3)12879  %a2 = bitcast <4 x i16> %a1 to <4 x bfloat>12880  br label %end12881 12882cmp.false:12883  %a3 = bitcast <4 x i16> %a to <4 x bfloat>12884  br label %end12885 12886end:12887  %phi = phi <4 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ]12888  ret <4 x bfloat> %phi12889}12890 12891define <4 x i16> @bitcast_v4bf16_to_v4i16(<4 x bfloat> %a, i32 %b) {12892; SI-LABEL: bitcast_v4bf16_to_v4i16:12893; SI:       ; %bb.0:12894; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12895; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v412896; SI-NEXT:    v_mul_f32_e32 v7, 1.0, v012897; SI-NEXT:    v_mul_f32_e32 v6, 1.0, v112898; SI-NEXT:    v_mul_f32_e32 v5, 1.0, v212899; SI-NEXT:    v_mul_f32_e32 v4, 1.0, v312900; SI-NEXT:    ; implicit-def: $vgpr012901; SI-NEXT:    ; implicit-def: $vgpr112902; SI-NEXT:    ; implicit-def: $vgpr212903; SI-NEXT:    ; implicit-def: $vgpr312904; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc12905; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]12906; SI-NEXT:    s_cbranch_execnz .LBB94_312907; SI-NEXT:  ; %bb.1: ; %Flow12908; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]12909; SI-NEXT:    s_cbranch_execnz .LBB94_412910; SI-NEXT:  .LBB94_2: ; %end12911; SI-NEXT:    s_or_b64 exec, exec, s[4:5]12912; SI-NEXT:    s_setpc_b64 s[30:31]12913; SI-NEXT:  .LBB94_3: ; %cmp.false12914; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v712915; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v612916; SI-NEXT:    v_lshrrev_b32_e32 v2, 16, v512917; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v412918; SI-NEXT:    ; implicit-def: $vgpr712919; SI-NEXT:    ; implicit-def: $vgpr612920; SI-NEXT:    ; implicit-def: $vgpr512921; SI-NEXT:    ; implicit-def: $vgpr412922; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]12923; SI-NEXT:    s_cbranch_execz .LBB94_212924; SI-NEXT:  .LBB94_4: ; %cmp.true12925; SI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v612926; SI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v712927; SI-NEXT:    v_add_f32_e32 v1, 0x40c00000, v112928; SI-NEXT:    v_add_f32_e32 v0, 0x40c00000, v012929; SI-NEXT:    v_lshrrev_b32_e32 v2, 16, v112930; SI-NEXT:    v_and_b32_e32 v3, 0xffff0000, v412931; SI-NEXT:    v_alignbit_b32 v0, v2, v0, 1612932; SI-NEXT:    v_and_b32_e32 v2, 0xffff0000, v512933; SI-NEXT:    v_add_f32_e32 v3, 0x40c00000, v312934; SI-NEXT:    v_add_f32_e32 v2, 0x40c00000, v212935; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v312936; SI-NEXT:    v_alignbit_b32 v2, v3, v2, 1612937; SI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v112938; SI-NEXT:    v_alignbit_b32 v1, v2, v1, 1612939; SI-NEXT:    s_or_b64 exec, exec, s[4:5]12940; SI-NEXT:    s_setpc_b64 s[30:31]12941;12942; VI-LABEL: bitcast_v4bf16_to_v4i16:12943; VI:       ; %bb.0:12944; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12945; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v212946; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc12947; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]12948; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]12949; VI-NEXT:    s_cbranch_execz .LBB94_212950; VI-NEXT:  ; %bb.1: ; %cmp.true12951; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v012952; VI-NEXT:    v_add_f32_e32 v2, 0x40c00000, v212953; VI-NEXT:    v_bfe_u32 v3, v2, 16, 112954; VI-NEXT:    v_add_u32_e32 v3, vcc, v3, v212955; VI-NEXT:    v_add_u32_e32 v3, vcc, 0x7fff, v312956; VI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v012957; VI-NEXT:    v_or_b32_e32 v4, 0x400000, v212958; VI-NEXT:    v_cmp_u_f32_e32 vcc, v2, v212959; VI-NEXT:    v_add_f32_e32 v0, 0x40c00000, v012960; VI-NEXT:    v_cndmask_b32_e32 v2, v3, v4, vcc12961; VI-NEXT:    v_bfe_u32 v3, v0, 16, 112962; VI-NEXT:    s_movk_i32 s6, 0x7fff12963; VI-NEXT:    v_add_u32_e32 v3, vcc, v3, v012964; VI-NEXT:    v_add_u32_e32 v3, vcc, s6, v312965; VI-NEXT:    v_or_b32_e32 v4, 0x400000, v012966; VI-NEXT:    v_cmp_u_f32_e32 vcc, v0, v012967; VI-NEXT:    v_cndmask_b32_e32 v0, v3, v4, vcc12968; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v112969; VI-NEXT:    v_add_f32_e32 v3, 0x40c00000, v312970; VI-NEXT:    v_bfe_u32 v4, v3, 16, 112971; VI-NEXT:    v_add_u32_e32 v4, vcc, v4, v312972; VI-NEXT:    v_add_u32_e32 v4, vcc, s6, v412973; VI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v112974; VI-NEXT:    v_or_b32_e32 v5, 0x400000, v312975; VI-NEXT:    v_cmp_u_f32_e32 vcc, v3, v312976; VI-NEXT:    v_add_f32_e32 v1, 0x40c00000, v112977; VI-NEXT:    v_cndmask_b32_e32 v3, v4, v5, vcc12978; VI-NEXT:    v_bfe_u32 v4, v1, 16, 112979; VI-NEXT:    v_add_u32_e32 v4, vcc, v4, v112980; VI-NEXT:    v_add_u32_e32 v4, vcc, 0x7fff, v412981; VI-NEXT:    v_or_b32_e32 v5, 0x400000, v112982; VI-NEXT:    v_cmp_u_f32_e32 vcc, v1, v112983; VI-NEXT:    v_cndmask_b32_e32 v1, v4, v5, vcc12984; VI-NEXT:    v_lshrrev_b32_e32 v0, 16, v012985; VI-NEXT:    v_lshrrev_b32_e32 v1, 16, v112986; VI-NEXT:    v_alignbit_b32 v1, v1, v3, 1612987; VI-NEXT:    v_alignbit_b32 v0, v0, v2, 1612988; VI-NEXT:  .LBB94_2: ; %end12989; VI-NEXT:    s_or_b64 exec, exec, s[4:5]12990; VI-NEXT:    s_setpc_b64 s[30:31]12991;12992; GFX9-LABEL: bitcast_v4bf16_to_v4i16:12993; GFX9:       ; %bb.0:12994; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12995; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v212996; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc12997; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]12998; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]12999; GFX9-NEXT:    s_cbranch_execz .LBB94_213000; GFX9-NEXT:  ; %bb.1: ; %cmp.true13001; GFX9-NEXT:    v_and_b32_e32 v2, 0xffff0000, v113002; GFX9-NEXT:    v_add_f32_e32 v2, 0x40c00000, v213003; GFX9-NEXT:    v_bfe_u32 v3, v2, 16, 113004; GFX9-NEXT:    s_movk_i32 s6, 0x7fff13005; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 16, v113006; GFX9-NEXT:    v_add3_u32 v3, v3, v2, s613007; GFX9-NEXT:    v_or_b32_e32 v4, 0x400000, v213008; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v2, v213009; GFX9-NEXT:    v_add_f32_e32 v1, 0x40c00000, v113010; GFX9-NEXT:    v_cndmask_b32_e32 v2, v3, v4, vcc13011; GFX9-NEXT:    v_bfe_u32 v3, v1, 16, 113012; GFX9-NEXT:    v_add3_u32 v3, v3, v1, s613013; GFX9-NEXT:    v_or_b32_e32 v4, 0x400000, v113014; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v1, v113015; GFX9-NEXT:    v_cndmask_b32_e32 v1, v3, v4, vcc13016; GFX9-NEXT:    v_lshlrev_b32_e32 v3, 16, v013017; GFX9-NEXT:    v_add_f32_e32 v3, 0x40c00000, v313018; GFX9-NEXT:    v_bfe_u32 v4, v3, 16, 113019; GFX9-NEXT:    v_and_b32_e32 v0, 0xffff0000, v013020; GFX9-NEXT:    v_add3_u32 v4, v4, v3, s613021; GFX9-NEXT:    v_or_b32_e32 v5, 0x400000, v313022; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v3, v313023; GFX9-NEXT:    v_add_f32_e32 v0, 0x40c00000, v013024; GFX9-NEXT:    v_cndmask_b32_e32 v3, v4, v5, vcc13025; GFX9-NEXT:    v_bfe_u32 v4, v0, 16, 113026; GFX9-NEXT:    v_add3_u32 v4, v4, v0, s613027; GFX9-NEXT:    v_or_b32_e32 v5, 0x400000, v013028; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v0, v013029; GFX9-NEXT:    v_cndmask_b32_e32 v0, v4, v5, vcc13030; GFX9-NEXT:    s_mov_b32 s6, 0x706030213031; GFX9-NEXT:    v_perm_b32 v0, v0, v3, s613032; GFX9-NEXT:    v_perm_b32 v1, v2, v1, s613033; GFX9-NEXT:  .LBB94_2: ; %end13034; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]13035; GFX9-NEXT:    s_setpc_b64 s[30:31]13036;13037; GFX11-TRUE16-LABEL: bitcast_v4bf16_to_v4i16:13038; GFX11-TRUE16:       ; %bb.0:13039; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)13040; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo13041; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v213042; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s013043; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)13044; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s013045; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB94_213046; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.true13047; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, 013048; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v0.l13049; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)13050; GFX11-TRUE16-NEXT:    v_add_f32_e32 v4, 0x40c00000, v213051; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v1.l13052; GFX11-TRUE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v213053; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)13054; GFX11-TRUE16-NEXT:    v_bfe_u32 v9, v2, 16, 113055; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, 0x400000, v213056; GFX11-TRUE16-NEXT:    v_add3_u32 v9, v9, v2, 0x7fff13057; GFX11-TRUE16-NEXT:    v_and_b32_e32 v3, 0xffff0000, v113058; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)13059; GFX11-TRUE16-NEXT:    v_add_f32_e32 v1, 0x40c00000, v313060; GFX11-TRUE16-NEXT:    v_bfe_u32 v3, v4, 16, 113061; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, 0x400000, v413062; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v413063; GFX11-TRUE16-NEXT:    v_bfe_u32 v8, v1, 16, 113064; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)13065; GFX11-TRUE16-NEXT:    v_add3_u32 v3, v3, v4, 0x7fff13066; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v013067; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, 0x400000, v113068; GFX11-TRUE16-NEXT:    v_add3_u32 v8, v8, v1, 0x7fff13069; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)13070; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v3, v3, v5 :: v_dual_add_f32 v0, 0x40c00000, v013071; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v213072; GFX11-TRUE16-NEXT:    v_bfe_u32 v6, v0, 16, 113073; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, 0x400000, v013074; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v9, v11, vcc_lo13075; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v013076; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)13077; GFX11-TRUE16-NEXT:    v_add3_u32 v6, v6, v0, 0x7fff13078; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v6, v7, vcc_lo13079; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v113080; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v3.h13081; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v8, v10, vcc_lo13082; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v2.h13083; GFX11-TRUE16-NEXT:  .LBB94_2: ; %end13084; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s013085; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]13086;13087; GFX11-FAKE16-LABEL: bitcast_v4bf16_to_v4i16:13088; GFX11-FAKE16:       ; %bb.0:13089; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)13090; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo13091; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v213092; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s013093; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)13094; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s013095; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB94_213096; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true13097; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v013098; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v013099; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)13100; GFX11-FAKE16-NEXT:    v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_add_f32 v0, 0x40c00000, v013101; GFX11-FAKE16-NEXT:    v_bfe_u32 v7, v3, 16, 113102; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, 0x400000, v313103; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)13104; GFX11-FAKE16-NEXT:    v_bfe_u32 v9, v0, 16, 113105; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, 0x400000, v013106; GFX11-FAKE16-NEXT:    v_add3_u32 v7, v7, v3, 0x7fff13107; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v113108; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v113109; GFX11-FAKE16-NEXT:    v_add3_u32 v9, v9, v0, 0x7fff13110; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)13111; GFX11-FAKE16-NEXT:    v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_add_f32 v1, 0x40c00000, v113112; GFX11-FAKE16-NEXT:    v_bfe_u32 v4, v2, 16, 113113; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, 0x400000, v213114; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v213115; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)13116; GFX11-FAKE16-NEXT:    v_bfe_u32 v6, v1, 16, 113117; GFX11-FAKE16-NEXT:    v_add3_u32 v4, v4, v2, 0x7fff13118; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)13119; GFX11-FAKE16-NEXT:    v_add3_u32 v6, v6, v1, 0x7fff13120; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v4, v5, vcc_lo13121; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v313122; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, 0x400000, v113123; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v7, v8, vcc_lo13124; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v013125; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v9, v10, vcc_lo13126; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v113127; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)13128; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v3, 0x706030213129; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v6, v4, vcc_lo13130; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v2, v1, 0x706030213131; GFX11-FAKE16-NEXT:  .LBB94_2: ; %end13132; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s013133; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]13134  %cmp = icmp eq i32 %b, 013135  br i1 %cmp, label %cmp.true, label %cmp.false13136 13137cmp.true:13138  %a1 = fadd <4 x bfloat> %a, splat (bfloat 0xR40C0)13139  %a2 = bitcast <4 x bfloat> %a1 to <4 x i16>13140  br label %end13141 13142cmp.false:13143  %a3 = bitcast <4 x bfloat> %a to <4 x i16>13144  br label %end13145 13146end:13147  %phi = phi <4 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]13148  ret <4 x i16> %phi13149}13150 13151define inreg <4 x i16> @bitcast_v4bf16_to_v4i16_scalar(<4 x bfloat> inreg %a, i32 inreg %b) {13152; SI-LABEL: bitcast_v4bf16_to_v4i16_scalar:13153; SI:       ; %bb.0:13154; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)13155; SI-NEXT:    s_cmp_lg_u32 s20, 013156; SI-NEXT:    v_mul_f32_e64 v7, 1.0, s1613157; SI-NEXT:    v_mul_f32_e64 v1, 1.0, s1713158; SI-NEXT:    v_mul_f32_e64 v3, 1.0, s1813159; SI-NEXT:    v_mul_f32_e64 v6, 1.0, s1913160; SI-NEXT:    s_cbranch_scc0 .LBB95_413161; SI-NEXT:  ; %bb.1: ; %cmp.false13162; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v713163; SI-NEXT:    v_lshrrev_b32_e32 v5, 16, v113164; SI-NEXT:    v_lshrrev_b32_e32 v2, 16, v313165; SI-NEXT:    v_lshrrev_b32_e32 v4, 16, v613166; SI-NEXT:    s_cbranch_execnz .LBB95_313167; SI-NEXT:  .LBB95_2: ; %cmp.true13168; SI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v113169; SI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v713170; SI-NEXT:    v_add_f32_e32 v5, 0x40c00000, v113171; SI-NEXT:    v_add_f32_e32 v0, 0x40c00000, v013172; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v513173; SI-NEXT:    v_lshr_b64 v[0:1], v[0:1], 1613174; SI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v313175; SI-NEXT:    v_add_f32_e32 v3, 0x40c00000, v113176; SI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v613177; SI-NEXT:    v_add_f32_e32 v1, 0x40c00000, v113178; SI-NEXT:    v_lshrrev_b32_e32 v4, 16, v113179; SI-NEXT:    v_lshr_b64 v[2:3], v[3:4], 1613180; SI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v513181; SI-NEXT:    v_lshr_b64 v[5:6], v[1:2], 1613182; SI-NEXT:  .LBB95_3: ; %end13183; SI-NEXT:    v_mov_b32_e32 v1, v513184; SI-NEXT:    v_mov_b32_e32 v3, v413185; SI-NEXT:    s_setpc_b64 s[30:31]13186; SI-NEXT:  .LBB95_4:13187; SI-NEXT:    ; implicit-def: $vgpr013188; SI-NEXT:    ; implicit-def: $vgpr513189; SI-NEXT:    ; implicit-def: $vgpr213190; SI-NEXT:    ; implicit-def: $vgpr413191; SI-NEXT:    s_branch .LBB95_213192;13193; VI-LABEL: bitcast_v4bf16_to_v4i16_scalar:13194; VI:       ; %bb.0:13195; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)13196; VI-NEXT:    s_cmp_lg_u32 s18, 013197; VI-NEXT:    s_cbranch_scc0 .LBB95_313198; VI-NEXT:  ; %bb.1: ; %cmp.false13199; VI-NEXT:    s_cbranch_execnz .LBB95_413200; VI-NEXT:  .LBB95_2: ; %cmp.true13201; VI-NEXT:    s_lshl_b32 s4, s16, 1613202; VI-NEXT:    v_mov_b32_e32 v3, 0x40c0000013203; VI-NEXT:    v_add_f32_e32 v0, s4, v313204; VI-NEXT:    v_bfe_u32 v1, v0, 16, 113205; VI-NEXT:    v_add_u32_e32 v1, vcc, v1, v013206; VI-NEXT:    v_add_u32_e32 v1, vcc, 0x7fff, v113207; VI-NEXT:    v_or_b32_e32 v2, 0x400000, v013208; VI-NEXT:    v_cmp_u_f32_e32 vcc, v0, v013209; VI-NEXT:    s_and_b32 s4, s16, 0xffff000013210; VI-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc13211; VI-NEXT:    v_add_f32_e32 v1, s4, v313212; VI-NEXT:    v_bfe_u32 v2, v1, 16, 113213; VI-NEXT:    v_add_u32_e32 v2, vcc, v2, v113214; VI-NEXT:    v_add_u32_e32 v2, vcc, 0x7fff, v213215; VI-NEXT:    v_or_b32_e32 v4, 0x400000, v113216; VI-NEXT:    v_cmp_u_f32_e32 vcc, v1, v113217; VI-NEXT:    s_lshl_b32 s4, s17, 1613218; VI-NEXT:    v_cndmask_b32_e32 v1, v2, v4, vcc13219; VI-NEXT:    v_add_f32_e32 v2, s4, v313220; VI-NEXT:    v_bfe_u32 v4, v2, 16, 113221; VI-NEXT:    v_add_u32_e32 v4, vcc, v4, v213222; VI-NEXT:    v_add_u32_e32 v4, vcc, 0x7fff, v413223; VI-NEXT:    s_and_b32 s4, s17, 0xffff000013224; VI-NEXT:    v_or_b32_e32 v5, 0x400000, v213225; VI-NEXT:    v_cmp_u_f32_e32 vcc, v2, v213226; VI-NEXT:    v_add_f32_e32 v3, s4, v313227; VI-NEXT:    v_cndmask_b32_e32 v2, v4, v5, vcc13228; VI-NEXT:    v_bfe_u32 v4, v3, 16, 113229; VI-NEXT:    v_add_u32_e32 v4, vcc, v4, v313230; VI-NEXT:    v_add_u32_e32 v4, vcc, 0x7fff, v413231; VI-NEXT:    v_or_b32_e32 v5, 0x400000, v313232; VI-NEXT:    v_cmp_u_f32_e32 vcc, v3, v313233; VI-NEXT:    v_cndmask_b32_e32 v3, v4, v5, vcc13234; VI-NEXT:    v_lshrrev_b32_e32 v3, 16, v313235; VI-NEXT:    v_lshrrev_b32_e32 v1, 16, v113236; VI-NEXT:    v_lshrrev_b64 v[2:3], 16, v[2:3]13237; VI-NEXT:    v_lshrrev_b64 v[0:1], 16, v[0:1]13238; VI-NEXT:    v_mov_b32_e32 v1, v213239; VI-NEXT:    s_setpc_b64 s[30:31]13240; VI-NEXT:  .LBB95_3:13241; VI-NEXT:    s_branch .LBB95_213242; VI-NEXT:  .LBB95_4:13243; VI-NEXT:    v_mov_b32_e32 v0, s1613244; VI-NEXT:    v_mov_b32_e32 v1, s1713245; VI-NEXT:    s_setpc_b64 s[30:31]13246;13247; GFX9-LABEL: bitcast_v4bf16_to_v4i16_scalar:13248; GFX9:       ; %bb.0:13249; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)13250; GFX9-NEXT:    s_cmp_lg_u32 s18, 013251; GFX9-NEXT:    s_cbranch_scc0 .LBB95_313252; GFX9-NEXT:  ; %bb.1: ; %cmp.false13253; GFX9-NEXT:    s_cbranch_execnz .LBB95_413254; GFX9-NEXT:  .LBB95_2: ; %cmp.true13255; GFX9-NEXT:    s_pack_lh_b32_b16 s4, 0, s1713256; GFX9-NEXT:    v_mov_b32_e32 v0, 0x40c0000013257; GFX9-NEXT:    v_add_f32_e32 v1, s4, v013258; GFX9-NEXT:    v_bfe_u32 v2, v1, 16, 113259; GFX9-NEXT:    v_add_u32_e32 v2, v2, v113260; GFX9-NEXT:    v_add_u32_e32 v2, 0x7fff, v213261; GFX9-NEXT:    v_or_b32_e32 v3, 0x400000, v113262; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v1, v113263; GFX9-NEXT:    s_lshl_b32 s4, s17, 1613264; GFX9-NEXT:    v_cndmask_b32_e32 v1, v2, v3, vcc13265; GFX9-NEXT:    v_add_f32_e32 v2, s4, v013266; GFX9-NEXT:    v_bfe_u32 v3, v2, 16, 113267; GFX9-NEXT:    v_add_u32_e32 v3, v3, v213268; GFX9-NEXT:    v_add_u32_e32 v3, 0x7fff, v313269; GFX9-NEXT:    v_or_b32_e32 v4, 0x400000, v213270; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v2, v213271; GFX9-NEXT:    s_pack_lh_b32_b16 s4, 0, s1613272; GFX9-NEXT:    v_cndmask_b32_e32 v2, v3, v4, vcc13273; GFX9-NEXT:    v_add_f32_e32 v3, s4, v013274; GFX9-NEXT:    v_bfe_u32 v4, v3, 16, 113275; GFX9-NEXT:    v_add_u32_e32 v4, v4, v313276; GFX9-NEXT:    s_lshl_b32 s4, s16, 1613277; GFX9-NEXT:    v_add_u32_e32 v4, 0x7fff, v413278; GFX9-NEXT:    v_or_b32_e32 v5, 0x400000, v313279; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v3, v313280; GFX9-NEXT:    v_add_f32_e32 v0, s4, v013281; GFX9-NEXT:    v_cndmask_b32_e32 v3, v4, v5, vcc13282; GFX9-NEXT:    v_bfe_u32 v4, v0, 16, 113283; GFX9-NEXT:    v_add_u32_e32 v4, v4, v013284; GFX9-NEXT:    v_add_u32_e32 v4, 0x7fff, v413285; GFX9-NEXT:    v_or_b32_e32 v5, 0x400000, v013286; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v0, v013287; GFX9-NEXT:    v_cndmask_b32_e32 v0, v4, v5, vcc13288; GFX9-NEXT:    v_lshrrev_b32_e32 v0, 16, v013289; GFX9-NEXT:    v_mov_b32_e32 v4, 0xffff000013290; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 16, v213291; GFX9-NEXT:    v_and_or_b32 v0, v3, v4, v013292; GFX9-NEXT:    v_and_or_b32 v1, v1, v4, v213293; GFX9-NEXT:    s_setpc_b64 s[30:31]13294; GFX9-NEXT:  .LBB95_3:13295; GFX9-NEXT:    s_branch .LBB95_213296; GFX9-NEXT:  .LBB95_4:13297; GFX9-NEXT:    v_mov_b32_e32 v0, s1613298; GFX9-NEXT:    v_mov_b32_e32 v1, s1713299; GFX9-NEXT:    s_setpc_b64 s[30:31]13300;13301; GFX11-TRUE16-LABEL: bitcast_v4bf16_to_v4i16_scalar:13302; GFX11-TRUE16:       ; %bb.0:13303; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)13304; GFX11-TRUE16-NEXT:    s_cmp_lg_u32 s2, 013305; GFX11-TRUE16-NEXT:    s_mov_b32 s2, 013306; GFX11-TRUE16-NEXT:    s_cbranch_scc0 .LBB95_313307; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow13308; GFX11-TRUE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s213309; GFX11-TRUE16-NEXT:    s_cbranch_vccnz .LBB95_413310; GFX11-TRUE16-NEXT:  .LBB95_2: ; %cmp.true13311; GFX11-TRUE16-NEXT:    s_pack_lh_b32_b16 s2, 0, s113312; GFX11-TRUE16-NEXT:    s_lshl_b32 s1, s1, 1613313; GFX11-TRUE16-NEXT:    v_add_f32_e64 v0, 0x40c00000, s213314; GFX11-TRUE16-NEXT:    v_add_f32_e64 v1, 0x40c00000, s113315; GFX11-TRUE16-NEXT:    s_lshl_b32 s1, s0, 1613316; GFX11-TRUE16-NEXT:    s_pack_lh_b32_b16 s0, 0, s013317; GFX11-TRUE16-NEXT:    v_add_f32_e64 v2, 0x40c00000, s113318; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, 0x400000, v013319; GFX11-TRUE16-NEXT:    v_bfe_u32 v4, v1, 16, 113320; GFX11-TRUE16-NEXT:    v_bfe_u32 v3, v0, 16, 113321; GFX11-TRUE16-NEXT:    v_add_f32_e64 v5, 0x40c00000, s013322; GFX11-TRUE16-NEXT:    v_bfe_u32 v6, v2, 16, 113323; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, 0x400000, v113324; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v4, v4, v113325; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v113326; GFX11-TRUE16-NEXT:    v_bfe_u32 v8, v5, 16, 113327; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v6, v6, v213328; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, 0x400000, v213329; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v4, 0x7fff, v413330; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v3, v3, v013331; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v8, v8, v513332; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v6, 0x7fff, v613333; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)13334; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v4, v4, v9, vcc_lo13335; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v213336; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v3, 0x7fff, v313337; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v8, 0x7fff, v813338; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, 0x400000, v513339; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v6, v10, vcc_lo13340; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v013341; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v3, v7, vcc_lo13342; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v513343; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v4.h13344; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v8, v9, vcc_lo13345; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v2.h13346; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]13347; GFX11-TRUE16-NEXT:  .LBB95_3:13348; GFX11-TRUE16-NEXT:    s_branch .LBB95_213349; GFX11-TRUE16-NEXT:  .LBB95_4:13350; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s113351; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]13352;13353; GFX11-FAKE16-LABEL: bitcast_v4bf16_to_v4i16_scalar:13354; GFX11-FAKE16:       ; %bb.0:13355; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)13356; GFX11-FAKE16-NEXT:    s_cmp_lg_u32 s2, 013357; GFX11-FAKE16-NEXT:    s_mov_b32 s2, 013358; GFX11-FAKE16-NEXT:    s_cbranch_scc0 .LBB95_313359; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow13360; GFX11-FAKE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s213361; GFX11-FAKE16-NEXT:    s_cbranch_vccnz .LBB95_413362; GFX11-FAKE16-NEXT:  .LBB95_2: ; %cmp.true13363; GFX11-FAKE16-NEXT:    s_pack_lh_b32_b16 s2, 0, s113364; GFX11-FAKE16-NEXT:    s_lshl_b32 s1, s1, 1613365; GFX11-FAKE16-NEXT:    v_add_f32_e64 v0, 0x40c00000, s213366; GFX11-FAKE16-NEXT:    v_add_f32_e64 v1, 0x40c00000, s113367; GFX11-FAKE16-NEXT:    s_lshl_b32 s1, s0, 1613368; GFX11-FAKE16-NEXT:    s_pack_lh_b32_b16 s0, 0, s013369; GFX11-FAKE16-NEXT:    v_add_f32_e64 v2, 0x40c00000, s113370; GFX11-FAKE16-NEXT:    v_add_f32_e64 v5, 0x40c00000, s013371; GFX11-FAKE16-NEXT:    v_bfe_u32 v4, v1, 16, 113372; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, 0x400000, v013373; GFX11-FAKE16-NEXT:    v_bfe_u32 v3, v0, 16, 113374; GFX11-FAKE16-NEXT:    v_bfe_u32 v6, v2, 16, 113375; GFX11-FAKE16-NEXT:    v_bfe_u32 v8, v5, 16, 113376; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v4, v4, v113377; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, 0x400000, v113378; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v113379; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, 0x400000, v213380; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v8, v8, v513381; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v4, 0x7fff, v413382; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)13383; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v1, v4, v9 :: v_dual_add_nc_u32 v6, v6, v213384; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v6, 0x7fff, v613385; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v213386; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v3, v3, v013387; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v4, 0x7fff, v813388; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, 0x400000, v513389; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v113390; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)13391; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v2, v6, v10 :: v_dual_add_nc_u32 v3, 0x7fff, v313392; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v013393; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v213394; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)13395; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v3, v7, vcc_lo13396; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v513397; GFX11-FAKE16-NEXT:    v_and_or_b32 v1, 0xffff0000, v3, v113398; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v4, v8, vcc_lo13399; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)13400; GFX11-FAKE16-NEXT:    v_and_or_b32 v0, 0xffff0000, v0, v213401; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]13402; GFX11-FAKE16-NEXT:  .LBB95_3:13403; GFX11-FAKE16-NEXT:    s_branch .LBB95_213404; GFX11-FAKE16-NEXT:  .LBB95_4:13405; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s113406; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]13407  %cmp = icmp eq i32 %b, 013408  br i1 %cmp, label %cmp.true, label %cmp.false13409 13410cmp.true:13411  %a1 = fadd <4 x bfloat> %a, splat (bfloat 0xR40C0)13412  %a2 = bitcast <4 x bfloat> %a1 to <4 x i16>13413  br label %end13414 13415cmp.false:13416  %a3 = bitcast <4 x bfloat> %a to <4 x i16>13417  br label %end13418 13419end:13420  %phi = phi <4 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]13421  ret <4 x i16> %phi13422}13423 13424define <8 x i8> @bitcast_v4i16_to_v8i8(<4 x i16> %a, i32 %b) {13425; SI-LABEL: bitcast_v4i16_to_v8i8:13426; SI:       ; %bb.0:13427; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)13428; SI-NEXT:    v_mov_b32_e32 v10, v313429; SI-NEXT:    v_mov_b32_e32 v8, v213430; SI-NEXT:    v_mov_b32_e32 v9, v013431; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v413432; SI-NEXT:    v_lshlrev_b32_e32 v12, 16, v113433; SI-NEXT:    v_lshlrev_b32_e32 v11, 16, v1013434; SI-NEXT:    ; implicit-def: $vgpr013435; SI-NEXT:    ; implicit-def: $vgpr113436; SI-NEXT:    ; implicit-def: $vgpr213437; SI-NEXT:    ; implicit-def: $vgpr313438; SI-NEXT:    ; implicit-def: $vgpr413439; SI-NEXT:    ; implicit-def: $vgpr513440; SI-NEXT:    ; implicit-def: $vgpr613441; SI-NEXT:    ; implicit-def: $vgpr713442; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc13443; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]13444; SI-NEXT:    s_cbranch_execnz .LBB96_313445; SI-NEXT:  ; %bb.1: ; %Flow13446; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]13447; SI-NEXT:    s_cbranch_execnz .LBB96_413448; SI-NEXT:  .LBB96_2: ; %end13449; SI-NEXT:    s_or_b64 exec, exec, s[4:5]13450; SI-NEXT:    s_setpc_b64 s[30:31]13451; SI-NEXT:  .LBB96_3: ; %cmp.false13452; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v913453; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v813454; SI-NEXT:    v_or_b32_e32 v0, v0, v1213455; SI-NEXT:    v_or_b32_e32 v4, v1, v1113456; SI-NEXT:    v_alignbit_b32 v3, v4, v0, 2413457; SI-NEXT:    v_alignbit_b32 v2, v4, v0, 1613458; SI-NEXT:    v_alignbit_b32 v1, v4, v0, 813459; SI-NEXT:    v_lshrrev_b32_e32 v5, 8, v413460; SI-NEXT:    v_and_b32_e32 v6, 0xffff, v1013461; SI-NEXT:    v_bfe_u32 v7, v10, 8, 813462; SI-NEXT:    ; implicit-def: $vgpr913463; SI-NEXT:    ; implicit-def: $vgpr1213464; SI-NEXT:    ; implicit-def: $vgpr813465; SI-NEXT:    ; implicit-def: $vgpr1113466; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]13467; SI-NEXT:    s_cbranch_execz .LBB96_213468; SI-NEXT:  .LBB96_4: ; %cmp.true13469; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v913470; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v813471; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v013472; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v113473; SI-NEXT:    v_or_b32_e32 v0, v12, v013474; SI-NEXT:    v_or_b32_e32 v1, v11, v113475; SI-NEXT:    v_add_i32_e32 v0, vcc, 0x30000, v013476; SI-NEXT:    v_add_i32_e32 v4, vcc, 0x30000, v113477; SI-NEXT:    v_alignbit_b32 v3, v4, v0, 2413478; SI-NEXT:    v_alignbit_b32 v2, v4, v0, 1613479; SI-NEXT:    v_alignbit_b32 v1, v4, v0, 813480; SI-NEXT:    v_lshrrev_b32_e32 v7, 24, v413481; SI-NEXT:    v_lshrrev_b32_e32 v6, 16, v413482; SI-NEXT:    v_lshrrev_b32_e32 v5, 8, v413483; SI-NEXT:    s_or_b64 exec, exec, s[4:5]13484; SI-NEXT:    s_setpc_b64 s[30:31]13485;13486; VI-LABEL: bitcast_v4i16_to_v8i8:13487; VI:       ; %bb.0:13488; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)13489; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v213490; VI-NEXT:    v_lshrrev_b32_e32 v6, 16, v113491; VI-NEXT:    v_lshrrev_b32_e32 v2, 16, v013492; VI-NEXT:    ; implicit-def: $vgpr913493; VI-NEXT:    ; implicit-def: $vgpr413494; VI-NEXT:    ; implicit-def: $vgpr313495; VI-NEXT:    ; implicit-def: $vgpr813496; VI-NEXT:    ; implicit-def: $vgpr513497; VI-NEXT:    ; implicit-def: $vgpr713498; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc13499; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]13500; VI-NEXT:  ; %bb.1: ; %cmp.false13501; VI-NEXT:    v_lshrrev_b64 v[3:4], 24, v[0:1]13502; VI-NEXT:    v_lshrrev_b32_e32 v7, 24, v113503; VI-NEXT:    v_lshrrev_b32_e32 v5, 8, v113504; VI-NEXT:    v_lshrrev_b32_e32 v4, 8, v013505; VI-NEXT:    v_mov_b32_e32 v9, v013506; VI-NEXT:    v_mov_b32_e32 v8, v113507; VI-NEXT:    ; implicit-def: $vgpr0_vgpr113508; VI-NEXT:  ; %bb.2: ; %Flow13509; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]13510; VI-NEXT:    s_cbranch_execz .LBB96_413511; VI-NEXT:  ; %bb.3: ; %cmp.true13512; VI-NEXT:    v_mov_b32_e32 v2, 313513; VI-NEXT:    v_add_u16_sdwa v6, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD13514; VI-NEXT:    v_add_u16_sdwa v2, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD13515; VI-NEXT:    v_add_u16_e32 v8, 3, v113516; VI-NEXT:    v_lshlrev_b32_e32 v1, 16, v613517; VI-NEXT:    v_add_u16_e32 v9, 3, v013518; VI-NEXT:    v_lshlrev_b32_e32 v0, 16, v213519; VI-NEXT:    v_or_b32_e32 v1, v8, v113520; VI-NEXT:    v_or_b32_e32 v0, v9, v013521; VI-NEXT:    v_lshrrev_b64 v[3:4], 24, v[0:1]13522; VI-NEXT:    v_lshrrev_b32_e32 v5, 8, v113523; VI-NEXT:    v_lshrrev_b32_e32 v4, 8, v013524; VI-NEXT:    v_bfe_u32 v7, v6, 8, 813525; VI-NEXT:  .LBB96_4: ; %end13526; VI-NEXT:    s_or_b64 exec, exec, s[4:5]13527; VI-NEXT:    v_mov_b32_e32 v0, v913528; VI-NEXT:    v_mov_b32_e32 v1, v413529; VI-NEXT:    v_mov_b32_e32 v4, v813530; VI-NEXT:    s_setpc_b64 s[30:31]13531;13532; GFX9-LABEL: bitcast_v4i16_to_v8i8:13533; GFX9:       ; %bb.0:13534; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)13535; GFX9-NEXT:    v_mov_b32_e32 v9, v113536; GFX9-NEXT:    v_mov_b32_e32 v8, v013537; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v213538; GFX9-NEXT:    ; implicit-def: $vgpr113539; GFX9-NEXT:    ; implicit-def: $vgpr213540; GFX9-NEXT:    ; implicit-def: $vgpr313541; GFX9-NEXT:    ; implicit-def: $vgpr513542; GFX9-NEXT:    ; implicit-def: $vgpr613543; GFX9-NEXT:    ; implicit-def: $vgpr713544; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc13545; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]13546; GFX9-NEXT:  ; %bb.1: ; %cmp.false13547; GFX9-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]13548; GFX9-NEXT:    v_lshrrev_b32_e32 v7, 24, v913549; GFX9-NEXT:    v_lshrrev_b32_e32 v6, 16, v913550; GFX9-NEXT:    v_lshrrev_b32_e32 v5, 8, v913551; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 16, v813552; GFX9-NEXT:    v_lshrrev_b32_e32 v1, 8, v813553; GFX9-NEXT:  ; %bb.2: ; %Flow13554; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]13555; GFX9-NEXT:  ; %bb.3: ; %cmp.true13556; GFX9-NEXT:    v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]13557; GFX9-NEXT:    v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]13558; GFX9-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]13559; GFX9-NEXT:    v_lshrrev_b32_e32 v7, 24, v913560; GFX9-NEXT:    v_lshrrev_b32_e32 v6, 16, v913561; GFX9-NEXT:    v_lshrrev_b32_e32 v5, 8, v913562; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 16, v813563; GFX9-NEXT:    v_lshrrev_b32_e32 v1, 8, v813564; GFX9-NEXT:  ; %bb.4: ; %end13565; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]13566; GFX9-NEXT:    v_mov_b32_e32 v0, v813567; GFX9-NEXT:    v_mov_b32_e32 v4, v913568; GFX9-NEXT:    s_setpc_b64 s[30:31]13569;13570; GFX11-TRUE16-LABEL: bitcast_v4i16_to_v8i8:13571; GFX11-TRUE16:       ; %bb.0:13572; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)13573; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v013574; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo13575; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo1613576; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo1613577; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo1613578; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_lo1613579; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v213580; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s013581; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false13582; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)13583; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]13584; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v913585; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v913586; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v813587; GFX11-TRUE16-NEXT:  ; %bb.2: ; %Flow13588; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s013589; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true13590; GFX11-TRUE16-NEXT:    v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]13591; GFX11-TRUE16-NEXT:    v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]13592; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)13593; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v913594; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]13595; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v913596; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v813597; GFX11-TRUE16-NEXT:  ; %bb.4: ; %end13598; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s013599; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v8.l13600; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v8.h13601; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v9.l13602; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v9.h13603; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]13604;13605; GFX11-FAKE16-LABEL: bitcast_v4i16_to_v8i8:13606; GFX11-FAKE16:       ; %bb.0:13607; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)13608; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v013609; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v213610; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr113611; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr213612; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr313613; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr513614; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr613615; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr713616; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo13617; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)13618; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s013619; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false13620; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)13621; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]13622; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v913623; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v913624; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v913625; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v813626; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v813627; GFX11-FAKE16-NEXT:  ; %bb.2: ; %Flow13628; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s013629; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB96_413630; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true13631; GFX11-FAKE16-NEXT:    v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]13632; GFX11-FAKE16-NEXT:    v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]13633; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)13634; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v913635; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]13636; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v913637; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v913638; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v813639; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v813640; GFX11-FAKE16-NEXT:  .LBB96_4: ; %end13641; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s013642; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, v813643; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, v913644; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]13645  %cmp = icmp eq i32 %b, 013646  br i1 %cmp, label %cmp.true, label %cmp.false13647 13648cmp.true:13649  %a1 = add <4 x i16> %a, splat (i16 3)13650  %a2 = bitcast <4 x i16> %a1 to <8 x i8>13651  br label %end13652 13653cmp.false:13654  %a3 = bitcast <4 x i16> %a to <8 x i8>13655  br label %end13656 13657end:13658  %phi = phi <8 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]13659  ret <8 x i8> %phi13660}13661 13662define inreg <8 x i8> @bitcast_v4i16_to_v8i8_scalar(<4 x i16> inreg %a, i32 inreg %b) {13663; SI-LABEL: bitcast_v4i16_to_v8i8_scalar:13664; SI:       ; %bb.0:13665; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)13666; SI-NEXT:    s_cmp_lg_u32 s20, 013667; SI-NEXT:    s_cbranch_scc0 .LBB97_413668; SI-NEXT:  ; %bb.1: ; %cmp.false13669; SI-NEXT:    s_and_b32 s4, s16, 0xffff13670; SI-NEXT:    s_lshl_b32 s5, s17, 1613671; SI-NEXT:    s_or_b32 s4, s4, s513672; SI-NEXT:    s_and_b32 s5, s18, 0xffff13673; SI-NEXT:    s_lshl_b32 s6, s19, 1613674; SI-NEXT:    s_or_b32 s5, s5, s613675; SI-NEXT:    s_lshr_b64 s[6:7], s[4:5], 2413676; SI-NEXT:    s_lshr_b64 s[8:9], s[4:5], 1613677; SI-NEXT:    s_lshr_b64 s[10:11], s[4:5], 813678; SI-NEXT:    s_lshr_b32 s9, s5, 813679; SI-NEXT:    s_and_b32 s11, s19, 0xffff13680; SI-NEXT:    s_bfe_u32 s7, s19, 0x8000813681; SI-NEXT:    s_cbranch_execnz .LBB97_313682; SI-NEXT:  .LBB97_2: ; %cmp.true13683; SI-NEXT:    s_add_i32 s16, s16, 313684; SI-NEXT:    s_and_b32 s4, s16, 0xffff13685; SI-NEXT:    s_lshl_b32 s5, s17, 1613686; SI-NEXT:    s_add_i32 s18, s18, 313687; SI-NEXT:    s_or_b32 s4, s5, s413688; SI-NEXT:    s_and_b32 s5, s18, 0xffff13689; SI-NEXT:    s_lshl_b32 s6, s19, 1613690; SI-NEXT:    s_or_b32 s5, s6, s513691; SI-NEXT:    s_add_i32 s4, s4, 0x3000013692; SI-NEXT:    s_add_i32 s5, s5, 0x3000013693; SI-NEXT:    s_lshr_b64 s[6:7], s[4:5], 2413694; SI-NEXT:    s_lshr_b64 s[8:9], s[4:5], 1613695; SI-NEXT:    s_lshr_b64 s[10:11], s[4:5], 813696; SI-NEXT:    s_lshr_b32 s7, s5, 2413697; SI-NEXT:    s_lshr_b32 s11, s5, 1613698; SI-NEXT:    s_lshr_b32 s9, s5, 813699; SI-NEXT:  .LBB97_3: ; %end13700; SI-NEXT:    v_mov_b32_e32 v0, s413701; SI-NEXT:    v_mov_b32_e32 v1, s1013702; SI-NEXT:    v_mov_b32_e32 v2, s813703; SI-NEXT:    v_mov_b32_e32 v3, s613704; SI-NEXT:    v_mov_b32_e32 v4, s513705; SI-NEXT:    v_mov_b32_e32 v5, s913706; SI-NEXT:    v_mov_b32_e32 v6, s1113707; SI-NEXT:    v_mov_b32_e32 v7, s713708; SI-NEXT:    s_setpc_b64 s[30:31]13709; SI-NEXT:  .LBB97_4:13710; SI-NEXT:    ; implicit-def: $sgpr413711; SI-NEXT:    ; implicit-def: $sgpr1013712; SI-NEXT:    ; implicit-def: $sgpr813713; SI-NEXT:    ; implicit-def: $sgpr613714; SI-NEXT:    ; implicit-def: $sgpr913715; SI-NEXT:    ; implicit-def: $sgpr1113716; SI-NEXT:    ; implicit-def: $sgpr713717; SI-NEXT:    s_branch .LBB97_213718;13719; VI-LABEL: bitcast_v4i16_to_v8i8_scalar:13720; VI:       ; %bb.0:13721; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)13722; VI-NEXT:    s_cmp_lg_u32 s18, 013723; VI-NEXT:    s_cbranch_scc0 .LBB97_413724; VI-NEXT:  ; %bb.1: ; %cmp.false13725; VI-NEXT:    s_lshr_b64 s[4:5], s[16:17], 2413726; VI-NEXT:    s_lshr_b32 s10, s17, 2413727; VI-NEXT:    s_lshr_b32 s8, s17, 1613728; VI-NEXT:    s_lshr_b32 s5, s17, 813729; VI-NEXT:    s_lshr_b32 s11, s16, 1613730; VI-NEXT:    s_lshr_b32 s12, s16, 813731; VI-NEXT:    s_mov_b32 s9, s1713732; VI-NEXT:    s_cbranch_execnz .LBB97_313733; VI-NEXT:  .LBB97_2: ; %cmp.true13734; VI-NEXT:    s_lshr_b32 s5, s17, 1613735; VI-NEXT:    s_add_i32 s9, s17, 313736; VI-NEXT:    s_add_i32 s8, s5, 313737; VI-NEXT:    s_and_b32 s4, s9, 0xffff13738; VI-NEXT:    s_lshl_b32 s5, s8, 1613739; VI-NEXT:    s_or_b32 s7, s4, s513740; VI-NEXT:    s_and_b32 s4, s16, 0xffff000013741; VI-NEXT:    s_add_i32 s16, s16, 313742; VI-NEXT:    s_and_b32 s5, s16, 0xffff13743; VI-NEXT:    s_or_b32 s4, s4, s513744; VI-NEXT:    s_add_i32 s6, s4, 0x3000013745; VI-NEXT:    s_lshr_b64 s[4:5], s[6:7], 2413746; VI-NEXT:    s_lshr_b32 s5, s7, 813747; VI-NEXT:    s_lshr_b32 s11, s6, 1613748; VI-NEXT:    s_lshr_b32 s12, s6, 813749; VI-NEXT:    s_bfe_u32 s10, s8, 0x8000813750; VI-NEXT:  .LBB97_3: ; %end13751; VI-NEXT:    v_mov_b32_e32 v0, s1613752; VI-NEXT:    v_mov_b32_e32 v1, s1213753; VI-NEXT:    v_mov_b32_e32 v2, s1113754; VI-NEXT:    v_mov_b32_e32 v3, s413755; VI-NEXT:    v_mov_b32_e32 v4, s913756; VI-NEXT:    v_mov_b32_e32 v5, s513757; VI-NEXT:    v_mov_b32_e32 v6, s813758; VI-NEXT:    v_mov_b32_e32 v7, s1013759; VI-NEXT:    s_setpc_b64 s[30:31]13760; VI-NEXT:  .LBB97_4:13761; VI-NEXT:    ; implicit-def: $sgpr1213762; VI-NEXT:    ; implicit-def: $sgpr1113763; VI-NEXT:    ; implicit-def: $sgpr413764; VI-NEXT:    ; implicit-def: $sgpr913765; VI-NEXT:    ; implicit-def: $sgpr513766; VI-NEXT:    ; implicit-def: $sgpr813767; VI-NEXT:    ; implicit-def: $sgpr1013768; VI-NEXT:    s_branch .LBB97_213769;13770; GFX9-LABEL: bitcast_v4i16_to_v8i8_scalar:13771; GFX9:       ; %bb.0:13772; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)13773; GFX9-NEXT:    s_cmp_lg_u32 s18, 013774; GFX9-NEXT:    s_cbranch_scc0 .LBB97_313775; GFX9-NEXT:  ; %bb.1: ; %cmp.false13776; GFX9-NEXT:    s_lshr_b64 s[4:5], s[16:17], 2413777; GFX9-NEXT:    s_lshr_b32 s5, s17, 2413778; GFX9-NEXT:    s_lshr_b32 s8, s17, 1613779; GFX9-NEXT:    s_lshr_b32 s10, s17, 813780; GFX9-NEXT:    s_lshr_b32 s9, s16, 1613781; GFX9-NEXT:    s_lshr_b32 s11, s16, 813782; GFX9-NEXT:    s_cbranch_execnz .LBB97_413783; GFX9-NEXT:  .LBB97_2: ; %cmp.true13784; GFX9-NEXT:    v_pk_add_u16 v9, s17, 3 op_sel_hi:[1,0]13785; GFX9-NEXT:    v_pk_add_u16 v8, s16, 3 op_sel_hi:[1,0]13786; GFX9-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]13787; GFX9-NEXT:    v_lshrrev_b32_e32 v7, 24, v913788; GFX9-NEXT:    v_lshrrev_b32_e32 v6, 16, v913789; GFX9-NEXT:    v_lshrrev_b32_e32 v5, 8, v913790; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 16, v813791; GFX9-NEXT:    v_lshrrev_b32_e32 v1, 8, v813792; GFX9-NEXT:    s_branch .LBB97_513793; GFX9-NEXT:  .LBB97_3:13794; GFX9-NEXT:    ; implicit-def: $sgpr1113795; GFX9-NEXT:    ; implicit-def: $sgpr913796; GFX9-NEXT:    ; implicit-def: $sgpr413797; GFX9-NEXT:    ; implicit-def: $sgpr1013798; GFX9-NEXT:    ; implicit-def: $sgpr813799; GFX9-NEXT:    ; implicit-def: $sgpr513800; GFX9-NEXT:    s_branch .LBB97_213801; GFX9-NEXT:  .LBB97_4:13802; GFX9-NEXT:    v_mov_b32_e32 v8, s1613803; GFX9-NEXT:    v_mov_b32_e32 v9, s1713804; GFX9-NEXT:    v_mov_b32_e32 v1, s1113805; GFX9-NEXT:    v_mov_b32_e32 v2, s913806; GFX9-NEXT:    v_mov_b32_e32 v5, s1013807; GFX9-NEXT:    v_mov_b32_e32 v6, s813808; GFX9-NEXT:    v_mov_b32_e32 v7, s513809; GFX9-NEXT:    v_mov_b32_e32 v3, s413810; GFX9-NEXT:  .LBB97_5: ; %end13811; GFX9-NEXT:    v_mov_b32_e32 v0, v813812; GFX9-NEXT:    v_mov_b32_e32 v4, v913813; GFX9-NEXT:    s_setpc_b64 s[30:31]13814;13815; GFX11-LABEL: bitcast_v4i16_to_v8i8_scalar:13816; GFX11:       ; %bb.0:13817; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)13818; GFX11-NEXT:    s_cmp_lg_u32 s2, 013819; GFX11-NEXT:    s_mov_b32 s4, 013820; GFX11-NEXT:    s_cbranch_scc0 .LBB97_313821; GFX11-NEXT:  ; %bb.1: ; %cmp.false13822; GFX11-NEXT:    s_lshr_b64 s[2:3], s[0:1], 2413823; GFX11-NEXT:    s_lshr_b32 s3, s1, 2413824; GFX11-NEXT:    s_lshr_b32 s5, s1, 1613825; GFX11-NEXT:    s_lshr_b32 s7, s1, 813826; GFX11-NEXT:    s_lshr_b32 s6, s0, 1613827; GFX11-NEXT:    s_lshr_b32 s8, s0, 813828; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s413829; GFX11-NEXT:    s_cbranch_vccnz .LBB97_413830; GFX11-NEXT:  .LBB97_2: ; %cmp.true13831; GFX11-NEXT:    v_pk_add_u16 v9, s1, 3 op_sel_hi:[1,0]13832; GFX11-NEXT:    v_pk_add_u16 v8, s0, 3 op_sel_hi:[1,0]13833; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)13834; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v913835; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]13836; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v913837; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v913838; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v813839; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v813840; GFX11-NEXT:    s_branch .LBB97_513841; GFX11-NEXT:  .LBB97_3:13842; GFX11-NEXT:    ; implicit-def: $sgpr813843; GFX11-NEXT:    ; implicit-def: $sgpr613844; GFX11-NEXT:    ; implicit-def: $sgpr213845; GFX11-NEXT:    ; implicit-def: $sgpr713846; GFX11-NEXT:    ; implicit-def: $sgpr513847; GFX11-NEXT:    ; implicit-def: $sgpr313848; GFX11-NEXT:    s_branch .LBB97_213849; GFX11-NEXT:  .LBB97_4:13850; GFX11-NEXT:    v_dual_mov_b32 v8, s0 :: v_dual_mov_b32 v9, s113851; GFX11-NEXT:    v_dual_mov_b32 v1, s8 :: v_dual_mov_b32 v2, s613852; GFX11-NEXT:    v_dual_mov_b32 v5, s7 :: v_dual_mov_b32 v6, s513853; GFX11-NEXT:    v_mov_b32_e32 v7, s313854; GFX11-NEXT:    v_mov_b32_e32 v3, s213855; GFX11-NEXT:  .LBB97_5: ; %end13856; GFX11-NEXT:    v_mov_b32_e32 v0, v813857; GFX11-NEXT:    v_mov_b32_e32 v4, v913858; GFX11-NEXT:    s_setpc_b64 s[30:31]13859  %cmp = icmp eq i32 %b, 013860  br i1 %cmp, label %cmp.true, label %cmp.false13861 13862cmp.true:13863  %a1 = add <4 x i16> %a, splat (i16 3)13864  %a2 = bitcast <4 x i16> %a1 to <8 x i8>13865  br label %end13866 13867cmp.false:13868  %a3 = bitcast <4 x i16> %a to <8 x i8>13869  br label %end13870 13871end:13872  %phi = phi <8 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]13873  ret <8 x i8> %phi13874}13875 13876define <4 x i16> @bitcast_v8i8_to_v4i16(<8 x i8> %a, i32 %b) {13877; SI-LABEL: bitcast_v8i8_to_v4i16:13878; SI:       ; %bb.0:13879; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)13880; SI-NEXT:    v_mov_b32_e32 v9, v213881; SI-NEXT:    v_mov_b32_e32 v10, v013882; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v813883; SI-NEXT:    v_lshlrev_b32_e32 v11, 8, v513884; SI-NEXT:    v_lshlrev_b32_e32 v5, 24, v713885; SI-NEXT:    v_lshlrev_b32_e32 v7, 24, v313886; SI-NEXT:    v_lshlrev_b32_e32 v8, 8, v113887; SI-NEXT:    ; implicit-def: $vgpr013888; SI-NEXT:    ; implicit-def: $vgpr113889; SI-NEXT:    ; implicit-def: $vgpr213890; SI-NEXT:    ; implicit-def: $vgpr313891; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc13892; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]13893; SI-NEXT:    s_cbranch_execnz .LBB98_313894; SI-NEXT:  ; %bb.1: ; %Flow13895; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]13896; SI-NEXT:    s_cbranch_execnz .LBB98_413897; SI-NEXT:  .LBB98_2: ; %end13898; SI-NEXT:    s_or_b64 exec, exec, s[4:5]13899; SI-NEXT:    s_setpc_b64 s[30:31]13900; SI-NEXT:  .LBB98_3: ; %cmp.false13901; SI-NEXT:    v_and_b32_e32 v0, 0xff, v413902; SI-NEXT:    v_and_b32_e32 v1, 0xff, v613903; SI-NEXT:    v_or_b32_e32 v0, v0, v1113904; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v113905; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v013906; SI-NEXT:    v_or_b32_e32 v3, v5, v113907; SI-NEXT:    v_or_b32_e32 v2, v0, v313908; SI-NEXT:    v_and_b32_e32 v0, 0xff, v913909; SI-NEXT:    v_and_b32_e32 v4, 0xff, v1013910; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v013911; SI-NEXT:    v_or_b32_e32 v4, v4, v813912; SI-NEXT:    v_or_b32_e32 v0, v7, v013913; SI-NEXT:    v_and_b32_e32 v4, 0xffff, v413914; SI-NEXT:    v_alignbit_b32 v1, v2, v0, 1613915; SI-NEXT:    v_or_b32_e32 v0, v4, v013916; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v313917; SI-NEXT:    ; implicit-def: $vgpr1013918; SI-NEXT:    ; implicit-def: $vgpr813919; SI-NEXT:    ; implicit-def: $vgpr913920; SI-NEXT:    ; implicit-def: $vgpr713921; SI-NEXT:    ; implicit-def: $vgpr413922; SI-NEXT:    ; implicit-def: $vgpr1113923; SI-NEXT:    ; implicit-def: $vgpr613924; SI-NEXT:    ; implicit-def: $vgpr513925; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]13926; SI-NEXT:    s_cbranch_execz .LBB98_213927; SI-NEXT:  .LBB98_4: ; %cmp.true13928; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v1013929; SI-NEXT:    v_and_b32_e32 v0, 0xff, v013930; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v913931; SI-NEXT:    v_or_b32_e32 v0, v8, v013932; SI-NEXT:    v_and_b32_e32 v1, 0xff, v113933; SI-NEXT:    v_add_i32_e32 v0, vcc, 0x300, v013934; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v113935; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v013936; SI-NEXT:    v_or_b32_e32 v1, v7, v113937; SI-NEXT:    v_or_b32_e32 v0, v1, v013938; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v413939; SI-NEXT:    v_and_b32_e32 v1, 0xff, v113940; SI-NEXT:    v_add_i32_e32 v2, vcc, 3, v613941; SI-NEXT:    v_or_b32_e32 v1, v11, v113942; SI-NEXT:    v_and_b32_e32 v2, 0xff, v213943; SI-NEXT:    v_add_i32_e32 v1, vcc, 0x300, v113944; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v213945; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v113946; SI-NEXT:    v_or_b32_e32 v2, v5, v213947; SI-NEXT:    v_or_b32_e32 v1, v2, v113948; SI-NEXT:    v_add_i32_e32 v0, vcc, 0x3000000, v013949; SI-NEXT:    v_add_i32_e32 v2, vcc, 0x3000000, v113950; SI-NEXT:    v_alignbit_b32 v1, v2, v0, 1613951; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v213952; SI-NEXT:    s_or_b64 exec, exec, s[4:5]13953; SI-NEXT:    s_setpc_b64 s[30:31]13954;13955; VI-LABEL: bitcast_v8i8_to_v4i16:13956; VI:       ; %bb.0:13957; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)13958; VI-NEXT:    v_mov_b32_e32 v9, v013959; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v813960; VI-NEXT:    v_lshlrev_b16_e32 v10, 8, v113961; VI-NEXT:    v_lshlrev_b16_e32 v8, 8, v313962; VI-NEXT:    v_lshlrev_b16_e32 v5, 8, v513963; VI-NEXT:    v_lshlrev_b16_e32 v3, 8, v713964; VI-NEXT:    ; implicit-def: $vgpr0_vgpr113965; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc13966; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]13967; VI-NEXT:    s_cbranch_execnz .LBB98_313968; VI-NEXT:  ; %bb.1: ; %Flow13969; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]13970; VI-NEXT:    s_cbranch_execnz .LBB98_413971; VI-NEXT:  .LBB98_2: ; %end13972; VI-NEXT:    s_or_b64 exec, exec, s[4:5]13973; VI-NEXT:    s_setpc_b64 s[30:31]13974; VI-NEXT:  .LBB98_3: ; %cmp.false13975; VI-NEXT:    v_or_b32_sdwa v0, v9, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD13976; VI-NEXT:    v_or_b32_sdwa v1, v2, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD13977; VI-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD13978; VI-NEXT:    v_or_b32_sdwa v1, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD13979; VI-NEXT:    v_or_b32_sdwa v2, v6, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD13980; VI-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD13981; VI-NEXT:    ; implicit-def: $vgpr913982; VI-NEXT:    ; implicit-def: $vgpr1013983; VI-NEXT:    ; implicit-def: $vgpr213984; VI-NEXT:    ; implicit-def: $vgpr813985; VI-NEXT:    ; implicit-def: $vgpr413986; VI-NEXT:    ; implicit-def: $vgpr513987; VI-NEXT:    ; implicit-def: $vgpr613988; VI-NEXT:    ; implicit-def: $vgpr313989; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]13990; VI-NEXT:    s_cbranch_execz .LBB98_213991; VI-NEXT:  .LBB98_4: ; %cmp.true13992; VI-NEXT:    v_add_u16_e32 v0, 3, v913993; VI-NEXT:    v_add_u16_e32 v1, 3, v213994; VI-NEXT:    v_or_b32_sdwa v0, v10, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_013995; VI-NEXT:    v_or_b32_sdwa v1, v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_013996; VI-NEXT:    v_mov_b32_e32 v2, 0x30013997; VI-NEXT:    v_add_u16_e32 v0, 0x300, v013998; VI-NEXT:    v_add_u16_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD13999; VI-NEXT:    v_or_b32_e32 v0, v0, v114000; VI-NEXT:    v_add_u16_e32 v1, 3, v414001; VI-NEXT:    v_add_u16_e32 v4, 3, v614002; VI-NEXT:    v_or_b32_sdwa v1, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_014003; VI-NEXT:    v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_014004; VI-NEXT:    v_add_u16_e32 v1, 0x300, v114005; VI-NEXT:    v_add_u16_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD14006; VI-NEXT:    v_or_b32_e32 v1, v1, v214007; VI-NEXT:    s_or_b64 exec, exec, s[4:5]14008; VI-NEXT:    s_setpc_b64 s[30:31]14009;14010; GFX9-LABEL: bitcast_v8i8_to_v4i16:14011; GFX9:       ; %bb.0:14012; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14013; GFX9-NEXT:    v_mov_b32_e32 v9, v014014; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v814015; GFX9-NEXT:    v_lshlrev_b16_e32 v10, 8, v114016; GFX9-NEXT:    v_lshlrev_b16_e32 v8, 8, v314017; GFX9-NEXT:    v_lshlrev_b16_e32 v5, 8, v514018; GFX9-NEXT:    v_lshlrev_b16_e32 v3, 8, v714019; GFX9-NEXT:    ; implicit-def: $vgpr0_vgpr114020; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc14021; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]14022; GFX9-NEXT:    s_cbranch_execnz .LBB98_314023; GFX9-NEXT:  ; %bb.1: ; %Flow14024; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]14025; GFX9-NEXT:    s_cbranch_execnz .LBB98_414026; GFX9-NEXT:  .LBB98_2: ; %end14027; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]14028; GFX9-NEXT:    s_setpc_b64 s[30:31]14029; GFX9-NEXT:  .LBB98_3: ; %cmp.false14030; GFX9-NEXT:    v_or_b32_sdwa v0, v9, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD14031; GFX9-NEXT:    v_or_b32_sdwa v1, v2, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD14032; GFX9-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD14033; GFX9-NEXT:    v_or_b32_sdwa v1, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD14034; GFX9-NEXT:    v_or_b32_sdwa v2, v6, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD14035; GFX9-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD14036; GFX9-NEXT:    ; implicit-def: $vgpr914037; GFX9-NEXT:    ; implicit-def: $vgpr1014038; GFX9-NEXT:    ; implicit-def: $vgpr214039; GFX9-NEXT:    ; implicit-def: $vgpr814040; GFX9-NEXT:    ; implicit-def: $vgpr414041; GFX9-NEXT:    ; implicit-def: $vgpr514042; GFX9-NEXT:    ; implicit-def: $vgpr614043; GFX9-NEXT:    ; implicit-def: $vgpr314044; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]14045; GFX9-NEXT:    s_cbranch_execz .LBB98_214046; GFX9-NEXT:  .LBB98_4: ; %cmp.true14047; GFX9-NEXT:    v_add_u16_e32 v0, 3, v914048; GFX9-NEXT:    v_add_u16_e32 v1, 3, v214049; GFX9-NEXT:    v_or_b32_sdwa v0, v10, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_014050; GFX9-NEXT:    s_movk_i32 s6, 0x30014051; GFX9-NEXT:    v_or_b32_sdwa v1, v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_014052; GFX9-NEXT:    v_add_u16_e32 v0, 0x300, v014053; GFX9-NEXT:    v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD14054; GFX9-NEXT:    v_or_b32_e32 v0, v0, v114055; GFX9-NEXT:    v_add_u16_e32 v1, 3, v414056; GFX9-NEXT:    v_add_u16_e32 v2, 3, v614057; GFX9-NEXT:    v_or_b32_sdwa v1, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_014058; GFX9-NEXT:    v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_014059; GFX9-NEXT:    v_add_u16_e32 v1, 0x300, v114060; GFX9-NEXT:    v_add_u16_sdwa v2, v2, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD14061; GFX9-NEXT:    v_or_b32_e32 v1, v1, v214062; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]14063; GFX9-NEXT:    s_setpc_b64 s[30:31]14064;14065; GFX11-TRUE16-LABEL: bitcast_v8i8_to_v4i16:14066; GFX11-TRUE16:       ; %bb.0:14067; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14068; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.h, v5.l14069; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.h, v2.l14070; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v0.l14071; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.l, 8, v1.l14072; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.h, 8, v3.l14073; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.l, 8, v5.h14074; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.h, 8, v7.l14075; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo14076; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr114077; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v814078; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s014079; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB98_314080; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow14081; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s014082; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB98_414083; GFX11-TRUE16-NEXT:  .LBB98_2: ; %end14084; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s014085; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]14086; GFX11-TRUE16-NEXT:  .LBB98_3: ; %cmp.false14087; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v5.l14088; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v4.h14089; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v4.l14090; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v6.l14091; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo1614092; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_hi1614093; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_lo1614094; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr6_lo1614095; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)14096; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v2.l14097; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v0.h, v2.h14098; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)14099; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v3.l14100; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v1.h, v3.h14101; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_lo1614102; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_hi1614103; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo1614104; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_hi1614105; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s014106; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB98_214107; GFX11-TRUE16-NEXT:  .LBB98_4: ; %cmp.true14108; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v5.l, 314109; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v4.h, 314110; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v4.l, 314111; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v6.l, 314112; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)14113; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l14114; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h14115; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)14116; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l14117; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h14118; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)14119; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v2.l, v0.l14120; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v2.h, v0.h14121; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)14122; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v3.l, v1.l14123; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v3.h, v1.h14124; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)14125; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l14126; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, 0x300, v0.h14127; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)14128; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.l14129; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, 0x300, v1.h14130; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s014131; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]14132;14133; GFX11-FAKE16-LABEL: bitcast_v8i8_to_v4i16:14134; GFX11-FAKE16:       ; %bb.0:14135; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14136; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v9, v014137; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v814138; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v8, 8, v114139; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v3, 8, v314140; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v5, 8, v514141; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v7, 8, v714142; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr114143; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo14144; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)14145; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s014146; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB98_314147; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow14148; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s014149; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB98_414150; GFX11-FAKE16-NEXT:  .LBB98_2: ; %end14151; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s014152; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]14153; GFX11-FAKE16-NEXT:  .LBB98_3: ; %cmp.false14154; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v914155; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v214156; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v414157; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v614158; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr914159; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr614160; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)14161; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v814162; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v314163; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)14164; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v514165; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v4, v714166; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr814167; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr414168; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr514169; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr714170; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)14171; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v014172; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v114173; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)14174; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v214175; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v314176; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)14177; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v114178; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v314179; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr214180; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr314181; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s014182; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB98_214183; GFX11-FAKE16-NEXT:  .LBB98_4: ; %cmp.true14184; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v9, 314185; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v2, 314186; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v4, 314187; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v6, 314188; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)14189; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v014190; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v114191; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)14192; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v214193; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v414194; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)14195; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v8, v014196; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v3, v114197; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)14198; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v5, v214199; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v7, v414200; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)14201; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v014202; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v114203; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)14204; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x300, v214205; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v314206; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)14207; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v014208; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v114209; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)14210; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v214211; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v314212; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)14213; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v114214; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v314215; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s014216; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]14217  %cmp = icmp eq i32 %b, 014218  br i1 %cmp, label %cmp.true, label %cmp.false14219 14220cmp.true:14221  %a1 = add <8 x i8> %a, splat (i8 3)14222  %a2 = bitcast <8 x i8> %a1 to <4 x i16>14223  br label %end14224 14225cmp.false:14226  %a3 = bitcast <8 x i8> %a to <4 x i16>14227  br label %end14228 14229end:14230  %phi = phi <4 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]14231  ret <4 x i16> %phi14232}14233 14234define inreg <4 x i16> @bitcast_v8i8_to_v4i16_scalar(<8 x i8> inreg %a, i32 inreg %b) {14235; SI-LABEL: bitcast_v8i8_to_v4i16_scalar:14236; SI:       ; %bb.0:14237; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14238; SI-NEXT:    s_cmp_lg_u32 s24, 014239; SI-NEXT:    s_cbranch_scc0 .LBB99_414240; SI-NEXT:  ; %bb.1: ; %cmp.false14241; SI-NEXT:    s_and_b32 s4, s16, 0xff14242; SI-NEXT:    s_lshl_b32 s5, s17, 814243; SI-NEXT:    s_or_b32 s4, s4, s514244; SI-NEXT:    s_and_b32 s5, s18, 0xff14245; SI-NEXT:    s_lshl_b32 s5, s5, 1614246; SI-NEXT:    s_lshl_b32 s6, s19, 2414247; SI-NEXT:    s_or_b32 s10, s6, s514248; SI-NEXT:    s_and_b32 s5, s20, 0xff14249; SI-NEXT:    s_lshl_b32 s6, s21, 814250; SI-NEXT:    s_or_b32 s5, s5, s614251; SI-NEXT:    s_and_b32 s6, s22, 0xff14252; SI-NEXT:    s_lshl_b32 s6, s6, 1614253; SI-NEXT:    s_lshl_b32 s7, s23, 2414254; SI-NEXT:    s_and_b32 s5, s5, 0xffff14255; SI-NEXT:    s_or_b32 s8, s7, s614256; SI-NEXT:    s_or_b32 s11, s5, s814257; SI-NEXT:    s_and_b32 s4, s4, 0xffff14258; SI-NEXT:    s_lshr_b64 s[6:7], s[10:11], 1614259; SI-NEXT:    s_or_b32 s4, s4, s1014260; SI-NEXT:    s_lshr_b32 s7, s8, 1614261; SI-NEXT:    s_mov_b32 s5, s1114262; SI-NEXT:    s_cbranch_execnz .LBB99_314263; SI-NEXT:  .LBB99_2: ; %cmp.true14264; SI-NEXT:    s_add_i32 s16, s16, 314265; SI-NEXT:    s_and_b32 s4, s16, 0xff14266; SI-NEXT:    s_lshl_b32 s5, s17, 814267; SI-NEXT:    s_add_i32 s18, s18, 314268; SI-NEXT:    s_or_b32 s4, s5, s414269; SI-NEXT:    s_and_b32 s6, s18, 0xff14270; SI-NEXT:    s_addk_i32 s4, 0x30014271; SI-NEXT:    s_lshl_b32 s5, s19, 2414272; SI-NEXT:    s_lshl_b32 s6, s6, 1614273; SI-NEXT:    s_and_b32 s4, s4, 0xffff14274; SI-NEXT:    s_or_b32 s5, s5, s614275; SI-NEXT:    s_add_i32 s20, s20, 314276; SI-NEXT:    s_or_b32 s4, s5, s414277; SI-NEXT:    s_and_b32 s5, s20, 0xff14278; SI-NEXT:    s_lshl_b32 s6, s21, 814279; SI-NEXT:    s_add_i32 s22, s22, 314280; SI-NEXT:    s_or_b32 s5, s6, s514281; SI-NEXT:    s_and_b32 s7, s22, 0xff14282; SI-NEXT:    s_addk_i32 s5, 0x30014283; SI-NEXT:    s_lshl_b32 s6, s23, 2414284; SI-NEXT:    s_lshl_b32 s7, s7, 1614285; SI-NEXT:    s_and_b32 s5, s5, 0xffff14286; SI-NEXT:    s_or_b32 s6, s6, s714287; SI-NEXT:    s_or_b32 s5, s6, s514288; SI-NEXT:    s_add_i32 s4, s4, 0x300000014289; SI-NEXT:    s_add_i32 s5, s5, 0x300000014290; SI-NEXT:    s_lshr_b64 s[6:7], s[4:5], 1614291; SI-NEXT:    s_lshr_b32 s7, s5, 1614292; SI-NEXT:  .LBB99_3: ; %end14293; SI-NEXT:    v_mov_b32_e32 v0, s414294; SI-NEXT:    v_mov_b32_e32 v1, s614295; SI-NEXT:    v_mov_b32_e32 v2, s514296; SI-NEXT:    v_mov_b32_e32 v3, s714297; SI-NEXT:    s_setpc_b64 s[30:31]14298; SI-NEXT:  .LBB99_4:14299; SI-NEXT:    ; implicit-def: $sgpr414300; SI-NEXT:    ; implicit-def: $sgpr614301; SI-NEXT:    ; implicit-def: $sgpr714302; SI-NEXT:    s_branch .LBB99_214303;14304; VI-LABEL: bitcast_v8i8_to_v4i16_scalar:14305; VI:       ; %bb.0:14306; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14307; VI-NEXT:    s_cmp_lg_u32 s24, 014308; VI-NEXT:    s_cbranch_scc0 .LBB99_414309; VI-NEXT:  ; %bb.1: ; %cmp.false14310; VI-NEXT:    s_and_b32 s4, s16, 0xff14311; VI-NEXT:    s_lshl_b32 s5, s17, 814312; VI-NEXT:    s_or_b32 s4, s4, s514313; VI-NEXT:    s_and_b32 s5, s18, 0xff14314; VI-NEXT:    s_lshl_b32 s6, s19, 814315; VI-NEXT:    s_or_b32 s5, s5, s614316; VI-NEXT:    s_and_b32 s4, s4, 0xffff14317; VI-NEXT:    s_lshl_b32 s5, s5, 1614318; VI-NEXT:    s_or_b32 s4, s4, s514319; VI-NEXT:    s_and_b32 s5, s20, 0xff14320; VI-NEXT:    s_lshl_b32 s6, s21, 814321; VI-NEXT:    s_or_b32 s5, s5, s614322; VI-NEXT:    s_and_b32 s6, s22, 0xff14323; VI-NEXT:    s_lshl_b32 s7, s23, 814324; VI-NEXT:    s_or_b32 s6, s6, s714325; VI-NEXT:    s_and_b32 s5, s5, 0xffff14326; VI-NEXT:    s_lshl_b32 s6, s6, 1614327; VI-NEXT:    s_or_b32 s5, s5, s614328; VI-NEXT:    s_cbranch_execnz .LBB99_314329; VI-NEXT:  .LBB99_2: ; %cmp.true14330; VI-NEXT:    s_add_i32 s16, s16, 314331; VI-NEXT:    s_and_b32 s4, s16, 0xff14332; VI-NEXT:    s_lshl_b32 s5, s17, 814333; VI-NEXT:    s_add_i32 s18, s18, 314334; VI-NEXT:    s_or_b32 s4, s5, s414335; VI-NEXT:    s_and_b32 s5, s18, 0xff14336; VI-NEXT:    s_lshl_b32 s6, s19, 814337; VI-NEXT:    s_addk_i32 s4, 0x30014338; VI-NEXT:    s_or_b32 s5, s6, s514339; VI-NEXT:    s_and_b32 s4, s4, 0xffff14340; VI-NEXT:    s_lshl_b32 s5, s5, 1614341; VI-NEXT:    s_add_i32 s20, s20, 314342; VI-NEXT:    s_or_b32 s4, s5, s414343; VI-NEXT:    s_and_b32 s5, s20, 0xff14344; VI-NEXT:    s_lshl_b32 s6, s21, 814345; VI-NEXT:    s_add_i32 s22, s22, 314346; VI-NEXT:    s_or_b32 s5, s6, s514347; VI-NEXT:    s_and_b32 s6, s22, 0xff14348; VI-NEXT:    s_lshl_b32 s7, s23, 814349; VI-NEXT:    s_addk_i32 s5, 0x30014350; VI-NEXT:    s_or_b32 s6, s7, s614351; VI-NEXT:    s_and_b32 s5, s5, 0xffff14352; VI-NEXT:    s_lshl_b32 s6, s6, 1614353; VI-NEXT:    s_or_b32 s5, s6, s514354; VI-NEXT:    s_add_i32 s4, s4, 0x300000014355; VI-NEXT:    s_add_i32 s5, s5, 0x300000014356; VI-NEXT:  .LBB99_3: ; %end14357; VI-NEXT:    v_mov_b32_e32 v0, s414358; VI-NEXT:    v_mov_b32_e32 v1, s514359; VI-NEXT:    s_setpc_b64 s[30:31]14360; VI-NEXT:  .LBB99_4:14361; VI-NEXT:    ; implicit-def: $sgpr4_sgpr514362; VI-NEXT:    s_branch .LBB99_214363;14364; GFX9-LABEL: bitcast_v8i8_to_v4i16_scalar:14365; GFX9:       ; %bb.0:14366; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14367; GFX9-NEXT:    s_cmp_lg_u32 s24, 014368; GFX9-NEXT:    s_cbranch_scc0 .LBB99_414369; GFX9-NEXT:  ; %bb.1: ; %cmp.false14370; GFX9-NEXT:    s_and_b32 s4, s16, 0xff14371; GFX9-NEXT:    s_lshl_b32 s5, s17, 814372; GFX9-NEXT:    s_or_b32 s4, s4, s514373; GFX9-NEXT:    s_and_b32 s5, s18, 0xff14374; GFX9-NEXT:    s_lshl_b32 s6, s19, 814375; GFX9-NEXT:    s_or_b32 s5, s5, s614376; GFX9-NEXT:    s_and_b32 s4, s4, 0xffff14377; GFX9-NEXT:    s_lshl_b32 s5, s5, 1614378; GFX9-NEXT:    s_or_b32 s4, s4, s514379; GFX9-NEXT:    s_and_b32 s5, s20, 0xff14380; GFX9-NEXT:    s_lshl_b32 s6, s21, 814381; GFX9-NEXT:    s_or_b32 s5, s5, s614382; GFX9-NEXT:    s_and_b32 s6, s22, 0xff14383; GFX9-NEXT:    s_lshl_b32 s7, s23, 814384; GFX9-NEXT:    s_or_b32 s6, s6, s714385; GFX9-NEXT:    s_and_b32 s5, s5, 0xffff14386; GFX9-NEXT:    s_lshl_b32 s6, s6, 1614387; GFX9-NEXT:    s_or_b32 s5, s5, s614388; GFX9-NEXT:    s_cbranch_execnz .LBB99_314389; GFX9-NEXT:  .LBB99_2: ; %cmp.true14390; GFX9-NEXT:    s_add_i32 s16, s16, 314391; GFX9-NEXT:    s_and_b32 s4, s16, 0xff14392; GFX9-NEXT:    s_lshl_b32 s5, s17, 814393; GFX9-NEXT:    s_add_i32 s18, s18, 314394; GFX9-NEXT:    s_or_b32 s4, s5, s414395; GFX9-NEXT:    s_and_b32 s5, s18, 0xff14396; GFX9-NEXT:    s_lshl_b32 s6, s19, 814397; GFX9-NEXT:    s_or_b32 s5, s6, s514398; GFX9-NEXT:    s_addk_i32 s4, 0x30014399; GFX9-NEXT:    s_addk_i32 s5, 0x30014400; GFX9-NEXT:    s_and_b32 s4, s4, 0xffff14401; GFX9-NEXT:    s_lshl_b32 s5, s5, 1614402; GFX9-NEXT:    s_add_i32 s20, s20, 314403; GFX9-NEXT:    s_or_b32 s4, s4, s514404; GFX9-NEXT:    s_and_b32 s5, s20, 0xff14405; GFX9-NEXT:    s_lshl_b32 s6, s21, 814406; GFX9-NEXT:    s_add_i32 s22, s22, 314407; GFX9-NEXT:    s_or_b32 s5, s6, s514408; GFX9-NEXT:    s_and_b32 s6, s22, 0xff14409; GFX9-NEXT:    s_lshl_b32 s7, s23, 814410; GFX9-NEXT:    s_or_b32 s6, s7, s614411; GFX9-NEXT:    s_addk_i32 s5, 0x30014412; GFX9-NEXT:    s_addk_i32 s6, 0x30014413; GFX9-NEXT:    s_and_b32 s5, s5, 0xffff14414; GFX9-NEXT:    s_lshl_b32 s6, s6, 1614415; GFX9-NEXT:    s_or_b32 s5, s5, s614416; GFX9-NEXT:  .LBB99_3: ; %end14417; GFX9-NEXT:    v_mov_b32_e32 v0, s414418; GFX9-NEXT:    v_mov_b32_e32 v1, s514419; GFX9-NEXT:    s_setpc_b64 s[30:31]14420; GFX9-NEXT:  .LBB99_4:14421; GFX9-NEXT:    ; implicit-def: $sgpr4_sgpr514422; GFX9-NEXT:    s_branch .LBB99_214423;14424; GFX11-LABEL: bitcast_v8i8_to_v4i16_scalar:14425; GFX11:       ; %bb.0:14426; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14427; GFX11-NEXT:    s_cmp_lg_u32 s20, 014428; GFX11-NEXT:    s_mov_b32 s6, 014429; GFX11-NEXT:    s_cbranch_scc0 .LBB99_414430; GFX11-NEXT:  ; %bb.1: ; %cmp.false14431; GFX11-NEXT:    s_and_b32 s4, s0, 0xff14432; GFX11-NEXT:    s_lshl_b32 s5, s1, 814433; GFX11-NEXT:    s_and_b32 s7, s2, 0xff14434; GFX11-NEXT:    s_lshl_b32 s8, s3, 814435; GFX11-NEXT:    s_or_b32 s4, s4, s514436; GFX11-NEXT:    s_or_b32 s5, s7, s814437; GFX11-NEXT:    s_and_b32 s7, s16, 0xff14438; GFX11-NEXT:    s_lshl_b32 s8, s17, 814439; GFX11-NEXT:    s_and_b32 s9, s18, 0xff14440; GFX11-NEXT:    s_lshl_b32 s10, s19, 814441; GFX11-NEXT:    s_or_b32 s7, s7, s814442; GFX11-NEXT:    s_or_b32 s8, s9, s1014443; GFX11-NEXT:    s_and_b32 s4, s4, 0xffff14444; GFX11-NEXT:    s_lshl_b32 s5, s5, 1614445; GFX11-NEXT:    s_and_b32 s7, s7, 0xffff14446; GFX11-NEXT:    s_lshl_b32 s8, s8, 1614447; GFX11-NEXT:    s_or_b32 s4, s4, s514448; GFX11-NEXT:    s_or_b32 s5, s7, s814449; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s614450; GFX11-NEXT:    s_cbranch_vccnz .LBB99_314451; GFX11-NEXT:  .LBB99_2: ; %cmp.true14452; GFX11-NEXT:    s_add_i32 s0, s0, 314453; GFX11-NEXT:    s_lshl_b32 s1, s1, 814454; GFX11-NEXT:    s_and_b32 s0, s0, 0xff14455; GFX11-NEXT:    s_add_i32 s2, s2, 314456; GFX11-NEXT:    s_or_b32 s0, s1, s014457; GFX11-NEXT:    s_and_b32 s1, s2, 0xff14458; GFX11-NEXT:    s_lshl_b32 s2, s3, 814459; GFX11-NEXT:    s_add_i32 s16, s16, 314460; GFX11-NEXT:    s_add_i32 s18, s18, 314461; GFX11-NEXT:    s_or_b32 s1, s2, s114462; GFX11-NEXT:    s_and_b32 s2, s16, 0xff14463; GFX11-NEXT:    s_lshl_b32 s3, s17, 814464; GFX11-NEXT:    s_and_b32 s4, s18, 0xff14465; GFX11-NEXT:    s_lshl_b32 s5, s19, 814466; GFX11-NEXT:    s_or_b32 s2, s3, s214467; GFX11-NEXT:    s_or_b32 s3, s5, s414468; GFX11-NEXT:    s_addk_i32 s0, 0x30014469; GFX11-NEXT:    s_addk_i32 s1, 0x30014470; GFX11-NEXT:    s_addk_i32 s2, 0x30014471; GFX11-NEXT:    s_addk_i32 s3, 0x30014472; GFX11-NEXT:    s_and_b32 s0, s0, 0xffff14473; GFX11-NEXT:    s_lshl_b32 s1, s1, 1614474; GFX11-NEXT:    s_and_b32 s2, s2, 0xffff14475; GFX11-NEXT:    s_lshl_b32 s3, s3, 1614476; GFX11-NEXT:    s_or_b32 s4, s0, s114477; GFX11-NEXT:    s_or_b32 s5, s2, s314478; GFX11-NEXT:  .LBB99_3: ; %end14479; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)14480; GFX11-NEXT:    v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s514481; GFX11-NEXT:    s_setpc_b64 s[30:31]14482; GFX11-NEXT:  .LBB99_4:14483; GFX11-NEXT:    ; implicit-def: $sgpr4_sgpr514484; GFX11-NEXT:    s_branch .LBB99_214485  %cmp = icmp eq i32 %b, 014486  br i1 %cmp, label %cmp.true, label %cmp.false14487 14488cmp.true:14489  %a1 = add <8 x i8> %a, splat (i8 3)14490  %a2 = bitcast <8 x i8> %a1 to <4 x i16>14491  br label %end14492 14493cmp.false:14494  %a3 = bitcast <8 x i8> %a to <4 x i16>14495  br label %end14496 14497end:14498  %phi = phi <4 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]14499  ret <4 x i16> %phi14500}14501 14502define <4 x bfloat> @bitcast_v4f16_to_v4bf16(<4 x half> %a, i32 %b) {14503; SI-LABEL: bitcast_v4f16_to_v4bf16:14504; SI:       ; %bb.0:14505; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14506; SI-NEXT:    v_cvt_f16_f32_e32 v5, v014507; SI-NEXT:    v_cvt_f16_f32_e32 v6, v114508; SI-NEXT:    v_cvt_f16_f32_e32 v7, v214509; SI-NEXT:    v_cvt_f16_f32_e32 v8, v314510; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v414511; SI-NEXT:    ; implicit-def: $vgpr014512; SI-NEXT:    ; implicit-def: $vgpr114513; SI-NEXT:    ; implicit-def: $vgpr214514; SI-NEXT:    ; implicit-def: $vgpr314515; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc14516; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]14517; SI-NEXT:    s_cbranch_execnz .LBB100_314518; SI-NEXT:  ; %bb.1: ; %Flow14519; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]14520; SI-NEXT:    s_cbranch_execnz .LBB100_414521; SI-NEXT:  .LBB100_2: ; %end14522; SI-NEXT:    s_or_b64 exec, exec, s[4:5]14523; SI-NEXT:    s_setpc_b64 s[30:31]14524; SI-NEXT:  .LBB100_3: ; %cmp.false14525; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v514526; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v614527; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v714528; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v814529; SI-NEXT:    ; implicit-def: $vgpr814530; SI-NEXT:    ; implicit-def: $vgpr714531; SI-NEXT:    ; implicit-def: $vgpr614532; SI-NEXT:    ; implicit-def: $vgpr514533; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]14534; SI-NEXT:    s_cbranch_execz .LBB100_214535; SI-NEXT:  .LBB100_4: ; %cmp.true14536; SI-NEXT:    v_cvt_f32_f16_e32 v0, v814537; SI-NEXT:    v_cvt_f32_f16_e32 v1, v714538; SI-NEXT:    v_cvt_f32_f16_e32 v2, v614539; SI-NEXT:    v_cvt_f32_f16_e32 v3, v514540; SI-NEXT:    v_add_f32_e32 v0, 0x38000000, v014541; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v114542; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v214543; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v314544; SI-NEXT:    v_cvt_f16_f32_e32 v3, v314545; SI-NEXT:    v_cvt_f16_f32_e32 v2, v214546; SI-NEXT:    v_cvt_f16_f32_e32 v4, v114547; SI-NEXT:    v_cvt_f16_f32_e32 v5, v014548; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v314549; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v214550; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v414551; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v514552; SI-NEXT:    s_or_b64 exec, exec, s[4:5]14553; SI-NEXT:    s_setpc_b64 s[30:31]14554;14555; VI-LABEL: bitcast_v4f16_to_v4bf16:14556; VI:       ; %bb.0:14557; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14558; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v214559; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc14560; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]14561; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]14562; VI-NEXT:  ; %bb.1: ; %cmp.true14563; VI-NEXT:    v_mov_b32_e32 v3, 0x20014564; VI-NEXT:    v_add_f16_e32 v2, 0x200, v014565; VI-NEXT:    v_add_f16_sdwa v0, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD14566; VI-NEXT:    v_add_f16_e32 v4, 0x200, v114567; VI-NEXT:    v_add_f16_sdwa v1, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD14568; VI-NEXT:    v_or_b32_e32 v1, v4, v114569; VI-NEXT:    v_or_b32_e32 v0, v2, v014570; VI-NEXT:  ; %bb.2: ; %end14571; VI-NEXT:    s_or_b64 exec, exec, s[4:5]14572; VI-NEXT:    s_setpc_b64 s[30:31]14573;14574; GFX9-LABEL: bitcast_v4f16_to_v4bf16:14575; GFX9:       ; %bb.0:14576; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14577; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v214578; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc14579; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]14580; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]14581; GFX9-NEXT:  ; %bb.1: ; %cmp.true14582; GFX9-NEXT:    s_movk_i32 s6, 0x20014583; GFX9-NEXT:    v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]14584; GFX9-NEXT:    v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]14585; GFX9-NEXT:  ; %bb.2: ; %end14586; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]14587; GFX9-NEXT:    s_setpc_b64 s[30:31]14588;14589; GFX11-LABEL: bitcast_v4f16_to_v4bf16:14590; GFX11:       ; %bb.0:14591; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14592; GFX11-NEXT:    s_mov_b32 s0, exec_lo14593; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v214594; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s014595; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)14596; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s014597; GFX11-NEXT:  ; %bb.1: ; %cmp.true14598; GFX11-NEXT:    v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]14599; GFX11-NEXT:    v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]14600; GFX11-NEXT:  ; %bb.2: ; %end14601; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s014602; GFX11-NEXT:    s_setpc_b64 s[30:31]14603  %cmp = icmp eq i32 %b, 014604  br i1 %cmp, label %cmp.true, label %cmp.false14605 14606cmp.true:14607  %a1 = fadd <4 x half> %a, splat (half 0xH0200)14608  %a2 = bitcast <4 x half> %a1 to <4 x bfloat>14609  br label %end14610 14611cmp.false:14612  %a3 = bitcast <4 x half> %a to <4 x bfloat>14613  br label %end14614 14615end:14616  %phi = phi <4 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ]14617  ret <4 x bfloat> %phi14618}14619 14620define inreg <4 x bfloat> @bitcast_v4f16_to_v4bf16_scalar(<4 x half> inreg %a, i32 inreg %b) {14621; SI-LABEL: bitcast_v4f16_to_v4bf16_scalar:14622; SI:       ; %bb.0:14623; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14624; SI-NEXT:    v_cvt_f16_f32_e32 v4, s1614625; SI-NEXT:    v_cvt_f16_f32_e32 v5, s1714626; SI-NEXT:    v_cvt_f16_f32_e32 v6, s1814627; SI-NEXT:    v_cvt_f16_f32_e32 v7, s1914628; SI-NEXT:    s_cmp_lg_u32 s20, 014629; SI-NEXT:    s_cbranch_scc0 .LBB101_414630; SI-NEXT:  ; %bb.1: ; %cmp.false14631; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v414632; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v514633; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v614634; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v714635; SI-NEXT:    s_cbranch_execnz .LBB101_314636; SI-NEXT:  .LBB101_2: ; %cmp.true14637; SI-NEXT:    v_cvt_f32_f16_e32 v0, v714638; SI-NEXT:    v_cvt_f32_f16_e32 v1, v614639; SI-NEXT:    v_cvt_f32_f16_e32 v2, v514640; SI-NEXT:    v_cvt_f32_f16_e32 v3, v414641; SI-NEXT:    v_add_f32_e32 v0, 0x38000000, v014642; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v114643; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v214644; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v314645; SI-NEXT:    v_cvt_f16_f32_e32 v3, v314646; SI-NEXT:    v_cvt_f16_f32_e32 v2, v214647; SI-NEXT:    v_cvt_f16_f32_e32 v4, v114648; SI-NEXT:    v_cvt_f16_f32_e32 v5, v014649; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v314650; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v214651; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v414652; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v514653; SI-NEXT:  .LBB101_3: ; %end14654; SI-NEXT:    s_setpc_b64 s[30:31]14655; SI-NEXT:  .LBB101_4:14656; SI-NEXT:    ; implicit-def: $vgpr014657; SI-NEXT:    ; implicit-def: $vgpr114658; SI-NEXT:    ; implicit-def: $vgpr214659; SI-NEXT:    ; implicit-def: $vgpr314660; SI-NEXT:    s_branch .LBB101_214661;14662; VI-LABEL: bitcast_v4f16_to_v4bf16_scalar:14663; VI:       ; %bb.0:14664; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14665; VI-NEXT:    s_cmp_lg_u32 s18, 014666; VI-NEXT:    s_cbranch_scc0 .LBB101_314667; VI-NEXT:  ; %bb.1: ; %cmp.false14668; VI-NEXT:    s_cbranch_execnz .LBB101_414669; VI-NEXT:  .LBB101_2: ; %cmp.true14670; VI-NEXT:    s_lshr_b32 s4, s16, 1614671; VI-NEXT:    v_mov_b32_e32 v1, s414672; VI-NEXT:    s_lshr_b32 s4, s17, 1614673; VI-NEXT:    v_mov_b32_e32 v0, 0x20014674; VI-NEXT:    v_mov_b32_e32 v4, s414675; VI-NEXT:    v_add_f16_e32 v2, s16, v014676; VI-NEXT:    v_add_f16_sdwa v3, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD14677; VI-NEXT:    v_add_f16_e32 v1, s17, v014678; VI-NEXT:    v_add_f16_sdwa v0, v4, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD14679; VI-NEXT:    v_or_b32_e32 v1, v1, v014680; VI-NEXT:    v_or_b32_e32 v0, v2, v314681; VI-NEXT:    s_setpc_b64 s[30:31]14682; VI-NEXT:  .LBB101_3:14683; VI-NEXT:    s_branch .LBB101_214684; VI-NEXT:  .LBB101_4:14685; VI-NEXT:    v_mov_b32_e32 v0, s1614686; VI-NEXT:    v_mov_b32_e32 v1, s1714687; VI-NEXT:    s_setpc_b64 s[30:31]14688;14689; GFX9-LABEL: bitcast_v4f16_to_v4bf16_scalar:14690; GFX9:       ; %bb.0:14691; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14692; GFX9-NEXT:    s_cmp_lg_u32 s18, 014693; GFX9-NEXT:    s_cbranch_scc0 .LBB101_314694; GFX9-NEXT:  ; %bb.1: ; %cmp.false14695; GFX9-NEXT:    s_cbranch_execnz .LBB101_414696; GFX9-NEXT:  .LBB101_2: ; %cmp.true14697; GFX9-NEXT:    v_mov_b32_e32 v0, 0x20014698; GFX9-NEXT:    v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]14699; GFX9-NEXT:    v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]14700; GFX9-NEXT:    s_setpc_b64 s[30:31]14701; GFX9-NEXT:  .LBB101_3:14702; GFX9-NEXT:    s_branch .LBB101_214703; GFX9-NEXT:  .LBB101_4:14704; GFX9-NEXT:    v_mov_b32_e32 v0, s1614705; GFX9-NEXT:    v_mov_b32_e32 v1, s1714706; GFX9-NEXT:    s_setpc_b64 s[30:31]14707;14708; GFX11-LABEL: bitcast_v4f16_to_v4bf16_scalar:14709; GFX11:       ; %bb.0:14710; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14711; GFX11-NEXT:    s_cmp_lg_u32 s2, 014712; GFX11-NEXT:    s_mov_b32 s2, 014713; GFX11-NEXT:    s_cbranch_scc0 .LBB101_314714; GFX11-NEXT:  ; %bb.1: ; %Flow14715; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s214716; GFX11-NEXT:    s_cbranch_vccnz .LBB101_414717; GFX11-NEXT:  .LBB101_2: ; %cmp.true14718; GFX11-NEXT:    v_pk_add_f16 v1, 0x200, s1 op_sel_hi:[0,1]14719; GFX11-NEXT:    v_pk_add_f16 v0, 0x200, s0 op_sel_hi:[0,1]14720; GFX11-NEXT:    s_setpc_b64 s[30:31]14721; GFX11-NEXT:  .LBB101_3:14722; GFX11-NEXT:    s_branch .LBB101_214723; GFX11-NEXT:  .LBB101_4:14724; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s114725; GFX11-NEXT:    s_setpc_b64 s[30:31]14726  %cmp = icmp eq i32 %b, 014727  br i1 %cmp, label %cmp.true, label %cmp.false14728 14729cmp.true:14730  %a1 = fadd <4 x half> %a, splat (half 0xH0200)14731  %a2 = bitcast <4 x half> %a1 to <4 x bfloat>14732  br label %end14733 14734cmp.false:14735  %a3 = bitcast <4 x half> %a to <4 x bfloat>14736  br label %end14737 14738end:14739  %phi = phi <4 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ]14740  ret <4 x bfloat> %phi14741}14742 14743define <4 x half> @bitcast_v4bf16_to_v4f16(<4 x bfloat> %a, i32 %b) {14744; SI-LABEL: bitcast_v4bf16_to_v4f16:14745; SI:       ; %bb.0:14746; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14747; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v414748; SI-NEXT:    v_mul_f32_e32 v4, 1.0, v014749; SI-NEXT:    v_mul_f32_e32 v5, 1.0, v114750; SI-NEXT:    v_mul_f32_e32 v6, 1.0, v214751; SI-NEXT:    v_mul_f32_e32 v7, 1.0, v314752; SI-NEXT:    ; implicit-def: $vgpr014753; SI-NEXT:    ; implicit-def: $vgpr114754; SI-NEXT:    ; implicit-def: $vgpr214755; SI-NEXT:    ; implicit-def: $vgpr314756; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc14757; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]14758; SI-NEXT:    s_cbranch_execnz .LBB102_314759; SI-NEXT:  ; %bb.1: ; %Flow14760; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]14761; SI-NEXT:    s_cbranch_execnz .LBB102_414762; SI-NEXT:  .LBB102_2: ; %end14763; SI-NEXT:    s_or_b64 exec, exec, s[4:5]14764; SI-NEXT:    s_setpc_b64 s[30:31]14765; SI-NEXT:  .LBB102_3: ; %cmp.false14766; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v414767; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v514768; SI-NEXT:    v_lshrrev_b32_e32 v2, 16, v614769; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v714770; SI-NEXT:    v_cvt_f32_f16_e32 v0, v014771; SI-NEXT:    v_cvt_f32_f16_e32 v1, v114772; SI-NEXT:    v_cvt_f32_f16_e32 v2, v214773; SI-NEXT:    v_cvt_f32_f16_e32 v3, v314774; SI-NEXT:    ; implicit-def: $vgpr714775; SI-NEXT:    ; implicit-def: $vgpr614776; SI-NEXT:    ; implicit-def: $vgpr514777; SI-NEXT:    ; implicit-def: $vgpr414778; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]14779; SI-NEXT:    s_cbranch_execz .LBB102_214780; SI-NEXT:  .LBB102_4: ; %cmp.true14781; SI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v714782; SI-NEXT:    v_add_f32_e32 v0, 0x40c00000, v014783; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v014784; SI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v614785; SI-NEXT:    v_add_f32_e32 v0, 0x40c00000, v014786; SI-NEXT:    v_lshrrev_b32_e32 v2, 16, v014787; SI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v514788; SI-NEXT:    v_add_f32_e32 v0, 0x40c00000, v014789; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v014790; SI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v414791; SI-NEXT:    v_add_f32_e32 v0, 0x40c00000, v014792; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v014793; SI-NEXT:    v_cvt_f32_f16_e32 v0, v014794; SI-NEXT:    v_cvt_f32_f16_e32 v1, v114795; SI-NEXT:    v_cvt_f32_f16_e32 v2, v214796; SI-NEXT:    v_cvt_f32_f16_e32 v3, v314797; SI-NEXT:    s_or_b64 exec, exec, s[4:5]14798; SI-NEXT:    s_setpc_b64 s[30:31]14799;14800; VI-LABEL: bitcast_v4bf16_to_v4f16:14801; VI:       ; %bb.0:14802; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14803; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v214804; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc14805; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]14806; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]14807; VI-NEXT:    s_cbranch_execz .LBB102_214808; VI-NEXT:  ; %bb.1: ; %cmp.true14809; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v014810; VI-NEXT:    v_add_f32_e32 v2, 0x40c00000, v214811; VI-NEXT:    v_bfe_u32 v3, v2, 16, 114812; VI-NEXT:    v_add_u32_e32 v3, vcc, v3, v214813; VI-NEXT:    v_add_u32_e32 v3, vcc, 0x7fff, v314814; VI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v014815; VI-NEXT:    v_or_b32_e32 v4, 0x400000, v214816; VI-NEXT:    v_cmp_u_f32_e32 vcc, v2, v214817; VI-NEXT:    v_add_f32_e32 v0, 0x40c00000, v014818; VI-NEXT:    v_cndmask_b32_e32 v2, v3, v4, vcc14819; VI-NEXT:    v_bfe_u32 v3, v0, 16, 114820; VI-NEXT:    s_movk_i32 s6, 0x7fff14821; VI-NEXT:    v_add_u32_e32 v3, vcc, v3, v014822; VI-NEXT:    v_add_u32_e32 v3, vcc, s6, v314823; VI-NEXT:    v_or_b32_e32 v4, 0x400000, v014824; VI-NEXT:    v_cmp_u_f32_e32 vcc, v0, v014825; VI-NEXT:    v_cndmask_b32_e32 v0, v3, v4, vcc14826; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v114827; VI-NEXT:    v_add_f32_e32 v3, 0x40c00000, v314828; VI-NEXT:    v_bfe_u32 v4, v3, 16, 114829; VI-NEXT:    v_add_u32_e32 v4, vcc, v4, v314830; VI-NEXT:    v_add_u32_e32 v4, vcc, s6, v414831; VI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v114832; VI-NEXT:    v_or_b32_e32 v5, 0x400000, v314833; VI-NEXT:    v_cmp_u_f32_e32 vcc, v3, v314834; VI-NEXT:    v_add_f32_e32 v1, 0x40c00000, v114835; VI-NEXT:    v_cndmask_b32_e32 v3, v4, v5, vcc14836; VI-NEXT:    v_bfe_u32 v4, v1, 16, 114837; VI-NEXT:    v_add_u32_e32 v4, vcc, v4, v114838; VI-NEXT:    v_add_u32_e32 v4, vcc, 0x7fff, v414839; VI-NEXT:    v_or_b32_e32 v5, 0x400000, v114840; VI-NEXT:    v_cmp_u_f32_e32 vcc, v1, v114841; VI-NEXT:    v_cndmask_b32_e32 v1, v4, v5, vcc14842; VI-NEXT:    v_lshrrev_b32_e32 v0, 16, v014843; VI-NEXT:    v_lshrrev_b32_e32 v1, 16, v114844; VI-NEXT:    v_alignbit_b32 v1, v1, v3, 1614845; VI-NEXT:    v_alignbit_b32 v0, v0, v2, 1614846; VI-NEXT:  .LBB102_2: ; %end14847; VI-NEXT:    s_or_b64 exec, exec, s[4:5]14848; VI-NEXT:    s_setpc_b64 s[30:31]14849;14850; GFX9-LABEL: bitcast_v4bf16_to_v4f16:14851; GFX9:       ; %bb.0:14852; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14853; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v214854; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc14855; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]14856; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]14857; GFX9-NEXT:    s_cbranch_execz .LBB102_214858; GFX9-NEXT:  ; %bb.1: ; %cmp.true14859; GFX9-NEXT:    v_and_b32_e32 v2, 0xffff0000, v114860; GFX9-NEXT:    v_add_f32_e32 v2, 0x40c00000, v214861; GFX9-NEXT:    v_bfe_u32 v3, v2, 16, 114862; GFX9-NEXT:    s_movk_i32 s6, 0x7fff14863; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 16, v114864; GFX9-NEXT:    v_add3_u32 v3, v3, v2, s614865; GFX9-NEXT:    v_or_b32_e32 v4, 0x400000, v214866; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v2, v214867; GFX9-NEXT:    v_add_f32_e32 v1, 0x40c00000, v114868; GFX9-NEXT:    v_cndmask_b32_e32 v2, v3, v4, vcc14869; GFX9-NEXT:    v_bfe_u32 v3, v1, 16, 114870; GFX9-NEXT:    v_add3_u32 v3, v3, v1, s614871; GFX9-NEXT:    v_or_b32_e32 v4, 0x400000, v114872; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v1, v114873; GFX9-NEXT:    v_cndmask_b32_e32 v1, v3, v4, vcc14874; GFX9-NEXT:    v_lshlrev_b32_e32 v3, 16, v014875; GFX9-NEXT:    v_add_f32_e32 v3, 0x40c00000, v314876; GFX9-NEXT:    v_bfe_u32 v4, v3, 16, 114877; GFX9-NEXT:    v_and_b32_e32 v0, 0xffff0000, v014878; GFX9-NEXT:    v_add3_u32 v4, v4, v3, s614879; GFX9-NEXT:    v_or_b32_e32 v5, 0x400000, v314880; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v3, v314881; GFX9-NEXT:    v_add_f32_e32 v0, 0x40c00000, v014882; GFX9-NEXT:    v_cndmask_b32_e32 v3, v4, v5, vcc14883; GFX9-NEXT:    v_bfe_u32 v4, v0, 16, 114884; GFX9-NEXT:    v_add3_u32 v4, v4, v0, s614885; GFX9-NEXT:    v_or_b32_e32 v5, 0x400000, v014886; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v0, v014887; GFX9-NEXT:    v_cndmask_b32_e32 v0, v4, v5, vcc14888; GFX9-NEXT:    s_mov_b32 s6, 0x706030214889; GFX9-NEXT:    v_perm_b32 v0, v0, v3, s614890; GFX9-NEXT:    v_perm_b32 v1, v2, v1, s614891; GFX9-NEXT:  .LBB102_2: ; %end14892; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]14893; GFX9-NEXT:    s_setpc_b64 s[30:31]14894;14895; GFX11-TRUE16-LABEL: bitcast_v4bf16_to_v4f16:14896; GFX11-TRUE16:       ; %bb.0:14897; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14898; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v214899; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_vgpr314900; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo14901; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)14902; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s014903; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false14904; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v014905; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr114906; GFX11-TRUE16-NEXT:  ; %bb.2: ; %Flow14907; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s014908; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB102_414909; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true14910; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, 014911; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.h, v1.l14912; GFX11-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v114913; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)14914; GFX11-TRUE16-NEXT:    v_add_f32_e32 v4, 0x40c00000, v314915; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.h, v0.l14916; GFX11-TRUE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v214917; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)14918; GFX11-TRUE16-NEXT:    v_bfe_u32 v6, v4, 16, 114919; GFX11-TRUE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v314920; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, 0x400000, v414921; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v414922; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, 0x400000, v214923; GFX11-TRUE16-NEXT:    v_add3_u32 v6, v6, v4, 0x7fff14924; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff0000, v014925; GFX11-TRUE16-NEXT:    v_bfe_u32 v9, v3, 16, 114926; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, 0x400000, v314927; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)14928; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v4, v6, v7, vcc_lo14929; GFX11-TRUE16-NEXT:    v_add_f32_e32 v0, 0x40c00000, v114930; GFX11-TRUE16-NEXT:    v_bfe_u32 v1, v2, 16, 114931; GFX11-TRUE16-NEXT:    v_add3_u32 v9, v9, v3, 0x7fff14932; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v314933; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)14934; GFX11-TRUE16-NEXT:    v_bfe_u32 v8, v0, 16, 114935; GFX11-TRUE16-NEXT:    v_add3_u32 v1, v1, v2, 0x7fff14936; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, 0x400000, v014937; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v6, v9, v11, vcc_lo14938; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v214939; GFX11-TRUE16-NEXT:    v_add3_u32 v8, v8, v0, 0x7fff14940; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v1, v5, vcc_lo14941; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v014942; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v4.h14943; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)14944; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v8, v10, vcc_lo14945; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v6.h14946; GFX11-TRUE16-NEXT:  .LBB102_4: ; %end14947; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s014948; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)14949; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v314950; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]14951;14952; GFX11-FAKE16-LABEL: bitcast_v4bf16_to_v4f16:14953; GFX11-FAKE16:       ; %bb.0:14954; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14955; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo14956; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v214957; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s014958; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)14959; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s014960; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB102_214961; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true14962; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v014963; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v014964; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)14965; GFX11-FAKE16-NEXT:    v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_add_f32 v0, 0x40c00000, v014966; GFX11-FAKE16-NEXT:    v_bfe_u32 v7, v3, 16, 114967; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, 0x400000, v314968; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)14969; GFX11-FAKE16-NEXT:    v_bfe_u32 v9, v0, 16, 114970; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, 0x400000, v014971; GFX11-FAKE16-NEXT:    v_add3_u32 v7, v7, v3, 0x7fff14972; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v114973; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v114974; GFX11-FAKE16-NEXT:    v_add3_u32 v9, v9, v0, 0x7fff14975; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)14976; GFX11-FAKE16-NEXT:    v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_add_f32 v1, 0x40c00000, v114977; GFX11-FAKE16-NEXT:    v_bfe_u32 v4, v2, 16, 114978; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, 0x400000, v214979; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v214980; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)14981; GFX11-FAKE16-NEXT:    v_bfe_u32 v6, v1, 16, 114982; GFX11-FAKE16-NEXT:    v_add3_u32 v4, v4, v2, 0x7fff14983; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)14984; GFX11-FAKE16-NEXT:    v_add3_u32 v6, v6, v1, 0x7fff14985; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v4, v5, vcc_lo14986; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v314987; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, 0x400000, v114988; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v7, v8, vcc_lo14989; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v014990; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v9, v10, vcc_lo14991; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v114992; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)14993; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v3, 0x706030214994; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v6, v4, vcc_lo14995; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v2, v1, 0x706030214996; GFX11-FAKE16-NEXT:  .LBB102_2: ; %end14997; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s014998; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]14999  %cmp = icmp eq i32 %b, 015000  br i1 %cmp, label %cmp.true, label %cmp.false15001 15002cmp.true:15003  %a1 = fadd <4 x bfloat> %a, splat (bfloat 0xR40C0)15004  %a2 = bitcast <4 x bfloat> %a1 to <4 x half>15005  br label %end15006 15007cmp.false:15008  %a3 = bitcast <4 x bfloat> %a to <4 x half>15009  br label %end15010 15011end:15012  %phi = phi <4 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]15013  ret <4 x half> %phi15014}15015 15016define inreg <4 x half> @bitcast_v4bf16_to_v4f16_scalar(<4 x bfloat> inreg %a, i32 inreg %b) {15017; SI-LABEL: bitcast_v4bf16_to_v4f16_scalar:15018; SI:       ; %bb.0:15019; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)15020; SI-NEXT:    s_cmp_lg_u32 s20, 015021; SI-NEXT:    v_mul_f32_e64 v4, 1.0, s1615022; SI-NEXT:    v_mul_f32_e64 v5, 1.0, s1715023; SI-NEXT:    v_mul_f32_e64 v6, 1.0, s1815024; SI-NEXT:    v_mul_f32_e64 v7, 1.0, s1915025; SI-NEXT:    s_cbranch_scc0 .LBB103_415026; SI-NEXT:  ; %bb.1: ; %cmp.false15027; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v415028; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v515029; SI-NEXT:    v_lshrrev_b32_e32 v2, 16, v615030; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v715031; SI-NEXT:    v_cvt_f32_f16_e32 v0, v015032; SI-NEXT:    v_cvt_f32_f16_e32 v1, v115033; SI-NEXT:    v_cvt_f32_f16_e32 v2, v215034; SI-NEXT:    v_cvt_f32_f16_e32 v3, v315035; SI-NEXT:    s_cbranch_execnz .LBB103_315036; SI-NEXT:  .LBB103_2: ; %cmp.true15037; SI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v715038; SI-NEXT:    v_add_f32_e32 v0, 0x40c00000, v015039; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v015040; SI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v615041; SI-NEXT:    v_add_f32_e32 v0, 0x40c00000, v015042; SI-NEXT:    v_lshrrev_b32_e32 v2, 16, v015043; SI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v515044; SI-NEXT:    v_add_f32_e32 v0, 0x40c00000, v015045; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v015046; SI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v415047; SI-NEXT:    v_add_f32_e32 v0, 0x40c00000, v015048; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v015049; SI-NEXT:    v_cvt_f32_f16_e32 v0, v015050; SI-NEXT:    v_cvt_f32_f16_e32 v1, v115051; SI-NEXT:    v_cvt_f32_f16_e32 v2, v215052; SI-NEXT:    v_cvt_f32_f16_e32 v3, v315053; SI-NEXT:  .LBB103_3: ; %end15054; SI-NEXT:    s_setpc_b64 s[30:31]15055; SI-NEXT:  .LBB103_4:15056; SI-NEXT:    ; implicit-def: $vgpr015057; SI-NEXT:    ; implicit-def: $vgpr115058; SI-NEXT:    ; implicit-def: $vgpr215059; SI-NEXT:    ; implicit-def: $vgpr315060; SI-NEXT:    s_branch .LBB103_215061;15062; VI-LABEL: bitcast_v4bf16_to_v4f16_scalar:15063; VI:       ; %bb.0:15064; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)15065; VI-NEXT:    s_cmp_lg_u32 s18, 015066; VI-NEXT:    s_cbranch_scc0 .LBB103_315067; VI-NEXT:  ; %bb.1: ; %cmp.false15068; VI-NEXT:    s_cbranch_execnz .LBB103_415069; VI-NEXT:  .LBB103_2: ; %cmp.true15070; VI-NEXT:    s_lshl_b32 s4, s16, 1615071; VI-NEXT:    v_mov_b32_e32 v3, 0x40c0000015072; VI-NEXT:    v_add_f32_e32 v0, s4, v315073; VI-NEXT:    v_bfe_u32 v1, v0, 16, 115074; VI-NEXT:    v_add_u32_e32 v1, vcc, v1, v015075; VI-NEXT:    v_add_u32_e32 v1, vcc, 0x7fff, v115076; VI-NEXT:    v_or_b32_e32 v2, 0x400000, v015077; VI-NEXT:    v_cmp_u_f32_e32 vcc, v0, v015078; VI-NEXT:    s_and_b32 s4, s16, 0xffff000015079; VI-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc15080; VI-NEXT:    v_add_f32_e32 v1, s4, v315081; VI-NEXT:    v_bfe_u32 v2, v1, 16, 115082; VI-NEXT:    v_add_u32_e32 v2, vcc, v2, v115083; VI-NEXT:    v_add_u32_e32 v2, vcc, 0x7fff, v215084; VI-NEXT:    v_or_b32_e32 v4, 0x400000, v115085; VI-NEXT:    v_cmp_u_f32_e32 vcc, v1, v115086; VI-NEXT:    s_lshl_b32 s4, s17, 1615087; VI-NEXT:    v_cndmask_b32_e32 v1, v2, v4, vcc15088; VI-NEXT:    v_add_f32_e32 v2, s4, v315089; VI-NEXT:    v_bfe_u32 v4, v2, 16, 115090; VI-NEXT:    v_add_u32_e32 v4, vcc, v4, v215091; VI-NEXT:    v_add_u32_e32 v4, vcc, 0x7fff, v415092; VI-NEXT:    s_and_b32 s4, s17, 0xffff000015093; VI-NEXT:    v_or_b32_e32 v5, 0x400000, v215094; VI-NEXT:    v_cmp_u_f32_e32 vcc, v2, v215095; VI-NEXT:    v_add_f32_e32 v3, s4, v315096; VI-NEXT:    v_cndmask_b32_e32 v2, v4, v5, vcc15097; VI-NEXT:    v_bfe_u32 v4, v3, 16, 115098; VI-NEXT:    v_add_u32_e32 v4, vcc, v4, v315099; VI-NEXT:    v_add_u32_e32 v4, vcc, 0x7fff, v415100; VI-NEXT:    v_or_b32_e32 v5, 0x400000, v315101; VI-NEXT:    v_cmp_u_f32_e32 vcc, v3, v315102; VI-NEXT:    v_cndmask_b32_e32 v3, v4, v5, vcc15103; VI-NEXT:    v_lshrrev_b32_e32 v3, 16, v315104; VI-NEXT:    v_lshrrev_b32_e32 v1, 16, v115105; VI-NEXT:    v_lshrrev_b64 v[2:3], 16, v[2:3]15106; VI-NEXT:    v_lshrrev_b64 v[0:1], 16, v[0:1]15107; VI-NEXT:    v_mov_b32_e32 v1, v215108; VI-NEXT:    s_setpc_b64 s[30:31]15109; VI-NEXT:  .LBB103_3:15110; VI-NEXT:    s_branch .LBB103_215111; VI-NEXT:  .LBB103_4:15112; VI-NEXT:    v_mov_b32_e32 v0, s1615113; VI-NEXT:    v_mov_b32_e32 v1, s1715114; VI-NEXT:    s_setpc_b64 s[30:31]15115;15116; GFX9-LABEL: bitcast_v4bf16_to_v4f16_scalar:15117; GFX9:       ; %bb.0:15118; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)15119; GFX9-NEXT:    s_cmp_lg_u32 s18, 015120; GFX9-NEXT:    s_cbranch_scc0 .LBB103_315121; GFX9-NEXT:  ; %bb.1: ; %cmp.false15122; GFX9-NEXT:    s_cbranch_execnz .LBB103_415123; GFX9-NEXT:  .LBB103_2: ; %cmp.true15124; GFX9-NEXT:    s_pack_lh_b32_b16 s4, 0, s1715125; GFX9-NEXT:    v_mov_b32_e32 v0, 0x40c0000015126; GFX9-NEXT:    v_add_f32_e32 v1, s4, v015127; GFX9-NEXT:    v_bfe_u32 v2, v1, 16, 115128; GFX9-NEXT:    v_add_u32_e32 v2, v2, v115129; GFX9-NEXT:    v_add_u32_e32 v2, 0x7fff, v215130; GFX9-NEXT:    v_or_b32_e32 v3, 0x400000, v115131; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v1, v115132; GFX9-NEXT:    s_lshl_b32 s4, s17, 1615133; GFX9-NEXT:    v_cndmask_b32_e32 v1, v2, v3, vcc15134; GFX9-NEXT:    v_add_f32_e32 v2, s4, v015135; GFX9-NEXT:    v_bfe_u32 v3, v2, 16, 115136; GFX9-NEXT:    v_add_u32_e32 v3, v3, v215137; GFX9-NEXT:    v_add_u32_e32 v3, 0x7fff, v315138; GFX9-NEXT:    v_or_b32_e32 v4, 0x400000, v215139; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v2, v215140; GFX9-NEXT:    s_pack_lh_b32_b16 s4, 0, s1615141; GFX9-NEXT:    v_cndmask_b32_e32 v2, v3, v4, vcc15142; GFX9-NEXT:    v_add_f32_e32 v3, s4, v015143; GFX9-NEXT:    v_bfe_u32 v4, v3, 16, 115144; GFX9-NEXT:    v_add_u32_e32 v4, v4, v315145; GFX9-NEXT:    s_lshl_b32 s4, s16, 1615146; GFX9-NEXT:    v_add_u32_e32 v4, 0x7fff, v415147; GFX9-NEXT:    v_or_b32_e32 v5, 0x400000, v315148; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v3, v315149; GFX9-NEXT:    v_add_f32_e32 v0, s4, v015150; GFX9-NEXT:    v_cndmask_b32_e32 v3, v4, v5, vcc15151; GFX9-NEXT:    v_bfe_u32 v4, v0, 16, 115152; GFX9-NEXT:    v_add_u32_e32 v4, v4, v015153; GFX9-NEXT:    v_add_u32_e32 v4, 0x7fff, v415154; GFX9-NEXT:    v_or_b32_e32 v5, 0x400000, v015155; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v0, v015156; GFX9-NEXT:    v_cndmask_b32_e32 v0, v4, v5, vcc15157; GFX9-NEXT:    v_mov_b32_e32 v4, 0xffff15158; GFX9-NEXT:    v_lshrrev_b32_e32 v1, 16, v115159; GFX9-NEXT:    v_lshrrev_b32_e32 v3, 16, v315160; GFX9-NEXT:    v_and_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_115161; GFX9-NEXT:    v_and_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_115162; GFX9-NEXT:    v_lshl_or_b32 v0, v3, 16, v015163; GFX9-NEXT:    v_lshl_or_b32 v1, v1, 16, v215164; GFX9-NEXT:    s_setpc_b64 s[30:31]15165; GFX9-NEXT:  .LBB103_3:15166; GFX9-NEXT:    s_branch .LBB103_215167; GFX9-NEXT:  .LBB103_4:15168; GFX9-NEXT:    v_mov_b32_e32 v0, s1615169; GFX9-NEXT:    v_mov_b32_e32 v1, s1715170; GFX9-NEXT:    s_setpc_b64 s[30:31]15171;15172; GFX11-TRUE16-LABEL: bitcast_v4bf16_to_v4f16_scalar:15173; GFX11-TRUE16:       ; %bb.0:15174; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)15175; GFX11-TRUE16-NEXT:    s_cmp_lg_u32 s2, 015176; GFX11-TRUE16-NEXT:    s_mov_b32 s2, 015177; GFX11-TRUE16-NEXT:    s_cbranch_scc0 .LBB103_315178; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow15179; GFX11-TRUE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s215180; GFX11-TRUE16-NEXT:    s_cbranch_vccnz .LBB103_415181; GFX11-TRUE16-NEXT:  .LBB103_2: ; %cmp.true15182; GFX11-TRUE16-NEXT:    s_pack_lh_b32_b16 s2, 0, s115183; GFX11-TRUE16-NEXT:    s_lshl_b32 s1, s1, 1615184; GFX11-TRUE16-NEXT:    v_add_f32_e64 v0, 0x40c00000, s215185; GFX11-TRUE16-NEXT:    s_pack_lh_b32_b16 s2, 0, s015186; GFX11-TRUE16-NEXT:    v_add_f32_e64 v1, 0x40c00000, s115187; GFX11-TRUE16-NEXT:    v_add_f32_e64 v2, 0x40c00000, s215188; GFX11-TRUE16-NEXT:    s_lshl_b32 s0, s0, 1615189; GFX11-TRUE16-NEXT:    v_bfe_u32 v3, v0, 16, 115190; GFX11-TRUE16-NEXT:    v_add_f32_e64 v4, 0x40c00000, s015191; GFX11-TRUE16-NEXT:    v_bfe_u32 v5, v1, 16, 115192; GFX11-TRUE16-NEXT:    v_bfe_u32 v6, v2, 16, 115193; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, 0x400000, v215194; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, 0x400000, v015195; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v015196; GFX11-TRUE16-NEXT:    v_bfe_u32 v8, v4, 16, 115197; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v6, v6, v215198; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)15199; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v8, v8, v415200; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v6, 0x7fff, v615201; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v3, v3, v015202; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)15203; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v3, 0x7fff, v315204; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v0, v3, v7 :: v_dual_add_nc_u32 v5, v5, v115205; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v215206; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)15207; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v5, 0x7fff, v515208; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, 0x400000, v115209; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v7, 0x7fff, v815210; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, 0x400000, v415211; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v6, v9, vcc_lo15212; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v115213; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)15214; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v215215; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v5, v3, vcc_lo15216; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v415217; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v015218; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v115219; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v7, v8, vcc_lo15220; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)15221; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v4.l15222; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v315223; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v2.l15224; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]15225; GFX11-TRUE16-NEXT:  .LBB103_3:15226; GFX11-TRUE16-NEXT:    s_branch .LBB103_215227; GFX11-TRUE16-NEXT:  .LBB103_4:15228; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s115229; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]15230;15231; GFX11-FAKE16-LABEL: bitcast_v4bf16_to_v4f16_scalar:15232; GFX11-FAKE16:       ; %bb.0:15233; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)15234; GFX11-FAKE16-NEXT:    s_cmp_lg_u32 s2, 015235; GFX11-FAKE16-NEXT:    s_mov_b32 s2, 015236; GFX11-FAKE16-NEXT:    s_cbranch_scc0 .LBB103_315237; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow15238; GFX11-FAKE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s215239; GFX11-FAKE16-NEXT:    s_cbranch_vccnz .LBB103_415240; GFX11-FAKE16-NEXT:  .LBB103_2: ; %cmp.true15241; GFX11-FAKE16-NEXT:    s_pack_lh_b32_b16 s2, 0, s115242; GFX11-FAKE16-NEXT:    s_lshl_b32 s1, s1, 1615243; GFX11-FAKE16-NEXT:    v_add_f32_e64 v0, 0x40c00000, s215244; GFX11-FAKE16-NEXT:    v_add_f32_e64 v1, 0x40c00000, s115245; GFX11-FAKE16-NEXT:    s_lshl_b32 s1, s0, 1615246; GFX11-FAKE16-NEXT:    s_pack_lh_b32_b16 s0, 0, s015247; GFX11-FAKE16-NEXT:    v_add_f32_e64 v2, 0x40c00000, s115248; GFX11-FAKE16-NEXT:    v_add_f32_e64 v5, 0x40c00000, s015249; GFX11-FAKE16-NEXT:    v_bfe_u32 v4, v1, 16, 115250; GFX11-FAKE16-NEXT:    v_bfe_u32 v3, v0, 16, 115251; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, 0x400000, v115252; GFX11-FAKE16-NEXT:    v_bfe_u32 v6, v2, 16, 115253; GFX11-FAKE16-NEXT:    v_bfe_u32 v8, v5, 16, 115254; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v4, v4, v115255; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v115256; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, 0x400000, v215257; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, 0x400000, v015258; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v8, v8, v515259; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v4, 0x7fff, v415260; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)15261; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v1, v4, v9 :: v_dual_add_nc_u32 v6, v6, v215262; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v4, 0x7fff, v815263; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, 0x400000, v515264; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)15265; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v6, 0x7fff, v615266; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v215267; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v3, v3, v015268; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v115269; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v2, v6, v10 :: v_dual_add_nc_u32 v3, 0x7fff, v315270; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v015271; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)15272; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v115273; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v215274; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)15275; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v3, v7, vcc_lo15276; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v515277; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v3, v4, v8 :: v_dual_and_b32 v2, 0xffff, v215278; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)15279; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v015280; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v315281; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)15282; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, v4, 16, v115283; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v0, v0, 16, v215284; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]15285; GFX11-FAKE16-NEXT:  .LBB103_3:15286; GFX11-FAKE16-NEXT:    s_branch .LBB103_215287; GFX11-FAKE16-NEXT:  .LBB103_4:15288; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s115289; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]15290  %cmp = icmp eq i32 %b, 015291  br i1 %cmp, label %cmp.true, label %cmp.false15292 15293cmp.true:15294  %a1 = fadd <4 x bfloat> %a, splat (bfloat 0xR40C0)15295  %a2 = bitcast <4 x bfloat> %a1 to <4 x half>15296  br label %end15297 15298cmp.false:15299  %a3 = bitcast <4 x bfloat> %a to <4 x half>15300  br label %end15301 15302end:15303  %phi = phi <4 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]15304  ret <4 x half> %phi15305}15306 15307define <8 x i8> @bitcast_v4f16_to_v8i8(<4 x half> %a, i32 %b) {15308; SI-LABEL: bitcast_v4f16_to_v8i8:15309; SI:       ; %bb.0:15310; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)15311; SI-NEXT:    v_cvt_f16_f32_e32 v10, v115312; SI-NEXT:    v_cvt_f16_f32_e32 v9, v015313; SI-NEXT:    v_cvt_f16_f32_e32 v6, v315314; SI-NEXT:    v_cvt_f16_f32_e32 v8, v215315; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v415316; SI-NEXT:    ; implicit-def: $vgpr015317; SI-NEXT:    ; implicit-def: $vgpr115318; SI-NEXT:    ; implicit-def: $vgpr215319; SI-NEXT:    ; implicit-def: $vgpr315320; SI-NEXT:    ; implicit-def: $vgpr415321; SI-NEXT:    ; implicit-def: $vgpr515322; SI-NEXT:    ; implicit-def: $vgpr715323; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc15324; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]15325; SI-NEXT:    s_cbranch_execnz .LBB104_315326; SI-NEXT:  ; %bb.1: ; %Flow15327; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]15328; SI-NEXT:    s_cbranch_execnz .LBB104_415329; SI-NEXT:  .LBB104_2: ; %end15330; SI-NEXT:    s_or_b64 exec, exec, s[4:5]15331; SI-NEXT:    s_setpc_b64 s[30:31]15332; SI-NEXT:  .LBB104_3: ; %cmp.false15333; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v1015334; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v615335; SI-NEXT:    v_or_b32_e32 v0, v9, v015336; SI-NEXT:    v_or_b32_e32 v4, v8, v115337; SI-NEXT:    v_alignbit_b32 v3, v4, v0, 2415338; SI-NEXT:    v_alignbit_b32 v2, v4, v0, 1615339; SI-NEXT:    v_alignbit_b32 v1, v4, v0, 815340; SI-NEXT:    v_lshrrev_b32_e32 v5, 8, v415341; SI-NEXT:    v_bfe_u32 v7, v6, 8, 815342; SI-NEXT:    ; implicit-def: $vgpr1015343; SI-NEXT:    ; implicit-def: $vgpr915344; SI-NEXT:    ; implicit-def: $vgpr815345; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]15346; SI-NEXT:    s_cbranch_execz .LBB104_215347; SI-NEXT:  .LBB104_4: ; %cmp.true15348; SI-NEXT:    v_cvt_f32_f16_e32 v0, v1015349; SI-NEXT:    v_cvt_f32_f16_e32 v1, v915350; SI-NEXT:    v_cvt_f32_f16_e32 v2, v615351; SI-NEXT:    v_cvt_f32_f16_e32 v3, v815352; SI-NEXT:    v_add_f32_e32 v0, 0x38000000, v015353; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v115354; SI-NEXT:    v_cvt_f16_f32_e32 v0, v015355; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v215356; SI-NEXT:    v_cvt_f16_f32_e32 v1, v115357; SI-NEXT:    v_cvt_f16_f32_e32 v6, v215358; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v315359; SI-NEXT:    v_cvt_f16_f32_e32 v2, v215360; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v015361; SI-NEXT:    v_or_b32_e32 v0, v1, v015362; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v615363; SI-NEXT:    v_or_b32_e32 v4, v2, v115364; SI-NEXT:    v_alignbit_b32 v3, v4, v0, 2415365; SI-NEXT:    v_alignbit_b32 v2, v4, v0, 1615366; SI-NEXT:    v_alignbit_b32 v1, v4, v0, 815367; SI-NEXT:    v_lshrrev_b32_e32 v5, 8, v415368; SI-NEXT:    v_bfe_u32 v7, v6, 8, 815369; SI-NEXT:    s_or_b64 exec, exec, s[4:5]15370; SI-NEXT:    s_setpc_b64 s[30:31]15371;15372; VI-LABEL: bitcast_v4f16_to_v8i8:15373; VI:       ; %bb.0:15374; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)15375; VI-NEXT:    v_mov_b32_e32 v9, v115376; VI-NEXT:    v_mov_b32_e32 v8, v015377; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v215378; VI-NEXT:    v_lshrrev_b32_e32 v6, 16, v915379; VI-NEXT:    v_lshrrev_b32_e32 v2, 16, v815380; VI-NEXT:    ; implicit-def: $vgpr115381; VI-NEXT:    ; implicit-def: $vgpr315382; VI-NEXT:    ; implicit-def: $vgpr515383; VI-NEXT:    ; implicit-def: $vgpr715384; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc15385; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]15386; VI-NEXT:  ; %bb.1: ; %cmp.false15387; VI-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]15388; VI-NEXT:    v_lshrrev_b32_e32 v7, 24, v915389; VI-NEXT:    v_lshrrev_b32_e32 v5, 8, v915390; VI-NEXT:    v_lshrrev_b32_e32 v1, 8, v815391; VI-NEXT:  ; %bb.2: ; %Flow15392; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]15393; VI-NEXT:    s_cbranch_execz .LBB104_415394; VI-NEXT:  ; %bb.3: ; %cmp.true15395; VI-NEXT:    v_mov_b32_e32 v0, 0x20015396; VI-NEXT:    v_add_f16_sdwa v6, v9, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD15397; VI-NEXT:    v_add_f16_sdwa v2, v8, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD15398; VI-NEXT:    v_lshlrev_b32_e32 v1, 16, v615399; VI-NEXT:    v_add_f16_e32 v9, 0x200, v915400; VI-NEXT:    v_lshlrev_b32_e32 v0, 16, v215401; VI-NEXT:    v_add_f16_e32 v8, 0x200, v815402; VI-NEXT:    v_or_b32_e32 v1, v9, v115403; VI-NEXT:    v_or_b32_e32 v0, v8, v015404; VI-NEXT:    v_lshrrev_b64 v[3:4], 24, v[0:1]15405; VI-NEXT:    v_lshrrev_b32_e32 v5, 8, v115406; VI-NEXT:    v_lshrrev_b32_e32 v1, 8, v015407; VI-NEXT:    v_bfe_u32 v7, v6, 8, 815408; VI-NEXT:  .LBB104_4: ; %end15409; VI-NEXT:    s_or_b64 exec, exec, s[4:5]15410; VI-NEXT:    v_mov_b32_e32 v0, v815411; VI-NEXT:    v_mov_b32_e32 v4, v915412; VI-NEXT:    s_setpc_b64 s[30:31]15413;15414; GFX9-LABEL: bitcast_v4f16_to_v8i8:15415; GFX9:       ; %bb.0:15416; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)15417; GFX9-NEXT:    v_mov_b32_e32 v9, v115418; GFX9-NEXT:    v_mov_b32_e32 v8, v015419; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v215420; GFX9-NEXT:    ; implicit-def: $vgpr115421; GFX9-NEXT:    ; implicit-def: $vgpr215422; GFX9-NEXT:    ; implicit-def: $vgpr315423; GFX9-NEXT:    ; implicit-def: $vgpr515424; GFX9-NEXT:    ; implicit-def: $vgpr615425; GFX9-NEXT:    ; implicit-def: $vgpr715426; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc15427; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]15428; GFX9-NEXT:  ; %bb.1: ; %cmp.false15429; GFX9-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]15430; GFX9-NEXT:    v_lshrrev_b32_e32 v7, 24, v915431; GFX9-NEXT:    v_lshrrev_b32_e32 v6, 16, v915432; GFX9-NEXT:    v_lshrrev_b32_e32 v5, 8, v915433; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 16, v815434; GFX9-NEXT:    v_lshrrev_b32_e32 v1, 8, v815435; GFX9-NEXT:  ; %bb.2: ; %Flow15436; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]15437; GFX9-NEXT:    s_cbranch_execz .LBB104_415438; GFX9-NEXT:  ; %bb.3: ; %cmp.true15439; GFX9-NEXT:    s_movk_i32 s6, 0x20015440; GFX9-NEXT:    v_pk_add_f16 v9, v9, s6 op_sel_hi:[1,0]15441; GFX9-NEXT:    v_pk_add_f16 v8, v8, s6 op_sel_hi:[1,0]15442; GFX9-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]15443; GFX9-NEXT:    v_lshrrev_b32_e32 v7, 24, v915444; GFX9-NEXT:    v_lshrrev_b32_e32 v6, 16, v915445; GFX9-NEXT:    v_lshrrev_b32_e32 v5, 8, v915446; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 16, v815447; GFX9-NEXT:    v_lshrrev_b32_e32 v1, 8, v815448; GFX9-NEXT:  .LBB104_4: ; %end15449; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]15450; GFX9-NEXT:    v_mov_b32_e32 v0, v815451; GFX9-NEXT:    v_mov_b32_e32 v4, v915452; GFX9-NEXT:    s_setpc_b64 s[30:31]15453;15454; GFX11-TRUE16-LABEL: bitcast_v4f16_to_v8i8:15455; GFX11-TRUE16:       ; %bb.0:15456; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)15457; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v015458; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo15459; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo1615460; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo1615461; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo1615462; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_lo1615463; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v215464; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s015465; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false15466; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)15467; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]15468; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v915469; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v915470; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v815471; GFX11-TRUE16-NEXT:  ; %bb.2: ; %Flow15472; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s015473; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true15474; GFX11-TRUE16-NEXT:    v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1]15475; GFX11-TRUE16-NEXT:    v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1]15476; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)15477; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v915478; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]15479; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v915480; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v815481; GFX11-TRUE16-NEXT:  ; %bb.4: ; %end15482; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s015483; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v8.l15484; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v8.h15485; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v9.l15486; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v9.h15487; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]15488;15489; GFX11-FAKE16-LABEL: bitcast_v4f16_to_v8i8:15490; GFX11-FAKE16:       ; %bb.0:15491; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)15492; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v015493; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v215494; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr115495; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr215496; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr315497; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr515498; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr615499; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr715500; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo15501; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)15502; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s015503; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false15504; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)15505; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]15506; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v915507; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v915508; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v915509; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v815510; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v815511; GFX11-FAKE16-NEXT:  ; %bb.2: ; %Flow15512; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s015513; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB104_415514; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true15515; GFX11-FAKE16-NEXT:    v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1]15516; GFX11-FAKE16-NEXT:    v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1]15517; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)15518; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v915519; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]15520; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v915521; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v915522; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v815523; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v815524; GFX11-FAKE16-NEXT:  .LBB104_4: ; %end15525; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s015526; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, v815527; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, v915528; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]15529  %cmp = icmp eq i32 %b, 015530  br i1 %cmp, label %cmp.true, label %cmp.false15531 15532cmp.true:15533  %a1 = fadd <4 x half> %a, splat (half 0xH0200)15534  %a2 = bitcast <4 x half> %a1 to <8 x i8>15535  br label %end15536 15537cmp.false:15538  %a3 = bitcast <4 x half> %a to <8 x i8>15539  br label %end15540 15541end:15542  %phi = phi <8 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]15543  ret <8 x i8> %phi15544}15545 15546define inreg <8 x i8> @bitcast_v4f16_to_v8i8_scalar(<4 x half> inreg %a, i32 inreg %b) {15547; SI-LABEL: bitcast_v4f16_to_v8i8_scalar:15548; SI:       ; %bb.0:15549; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)15550; SI-NEXT:    v_cvt_f16_f32_e32 v11, s1715551; SI-NEXT:    v_cvt_f16_f32_e32 v8, s1615552; SI-NEXT:    v_cvt_f16_f32_e32 v6, s1915553; SI-NEXT:    v_cvt_f16_f32_e32 v0, s1815554; SI-NEXT:    s_cmp_lg_u32 s20, 015555; SI-NEXT:    s_cbranch_scc0 .LBB105_415556; SI-NEXT:  ; %bb.1: ; %cmp.false15557; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1115558; SI-NEXT:    v_or_b32_e32 v9, v8, v115559; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v615560; SI-NEXT:    v_or_b32_e32 v10, v0, v115561; SI-NEXT:    v_lshr_b64 v[3:4], v[9:10], 2415562; SI-NEXT:    v_lshr_b64 v[4:5], v[9:10], 1615563; SI-NEXT:    v_lshr_b64 v[1:2], v[9:10], 815564; SI-NEXT:    v_lshrrev_b32_e32 v5, 8, v1015565; SI-NEXT:    v_bfe_u32 v7, v6, 8, 815566; SI-NEXT:    s_cbranch_execnz .LBB105_315567; SI-NEXT:  .LBB105_2: ; %cmp.true15568; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1115569; SI-NEXT:    v_cvt_f32_f16_e32 v2, v815570; SI-NEXT:    v_cvt_f32_f16_e32 v3, v615571; SI-NEXT:    v_cvt_f32_f16_e32 v0, v015572; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v115573; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v215574; SI-NEXT:    v_cvt_f16_f32_e32 v1, v115575; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v315576; SI-NEXT:    v_cvt_f16_f32_e32 v2, v215577; SI-NEXT:    v_cvt_f16_f32_e32 v6, v315578; SI-NEXT:    v_add_f32_e32 v0, 0x38000000, v015579; SI-NEXT:    v_cvt_f16_f32_e32 v0, v015580; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v115581; SI-NEXT:    v_or_b32_e32 v9, v2, v115582; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v615583; SI-NEXT:    v_or_b32_e32 v10, v0, v115584; SI-NEXT:    v_lshr_b64 v[3:4], v[9:10], 2415585; SI-NEXT:    v_lshr_b64 v[4:5], v[9:10], 1615586; SI-NEXT:    v_lshr_b64 v[1:2], v[9:10], 815587; SI-NEXT:    v_lshrrev_b32_e32 v5, 8, v1015588; SI-NEXT:    v_bfe_u32 v7, v6, 8, 815589; SI-NEXT:  .LBB105_3: ; %end15590; SI-NEXT:    v_mov_b32_e32 v0, v915591; SI-NEXT:    v_mov_b32_e32 v2, v415592; SI-NEXT:    v_mov_b32_e32 v4, v1015593; SI-NEXT:    s_setpc_b64 s[30:31]15594; SI-NEXT:  .LBB105_4:15595; SI-NEXT:    ; implicit-def: $vgpr915596; SI-NEXT:    ; implicit-def: $vgpr115597; SI-NEXT:    ; implicit-def: $vgpr415598; SI-NEXT:    ; implicit-def: $vgpr315599; SI-NEXT:    ; implicit-def: $vgpr515600; SI-NEXT:    ; implicit-def: $vgpr715601; SI-NEXT:    s_branch .LBB105_215602;15603; VI-LABEL: bitcast_v4f16_to_v8i8_scalar:15604; VI:       ; %bb.0:15605; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)15606; VI-NEXT:    s_cmp_lg_u32 s18, 015607; VI-NEXT:    s_cbranch_scc0 .LBB105_315608; VI-NEXT:  ; %bb.1: ; %cmp.false15609; VI-NEXT:    s_lshr_b64 s[4:5], s[16:17], 2415610; VI-NEXT:    s_lshr_b32 s8, s17, 2415611; VI-NEXT:    s_lshr_b32 s10, s17, 1615612; VI-NEXT:    s_lshr_b32 s5, s17, 815613; VI-NEXT:    s_lshr_b32 s11, s16, 1615614; VI-NEXT:    s_lshr_b32 s9, s16, 815615; VI-NEXT:    s_cbranch_execnz .LBB105_415616; VI-NEXT:  .LBB105_2: ; %cmp.true15617; VI-NEXT:    s_lshr_b32 s4, s17, 1615618; VI-NEXT:    v_mov_b32_e32 v0, 0x20015619; VI-NEXT:    v_add_f16_e32 v6, s4, v015620; VI-NEXT:    s_lshr_b32 s4, s16, 1615621; VI-NEXT:    v_lshlrev_b32_e32 v1, 16, v615622; VI-NEXT:    v_add_f16_e32 v8, s17, v015623; VI-NEXT:    v_add_f16_e32 v2, s4, v015624; VI-NEXT:    v_or_b32_e32 v10, v8, v115625; VI-NEXT:    v_lshlrev_b32_e32 v1, 16, v215626; VI-NEXT:    v_add_f16_e32 v0, s16, v015627; VI-NEXT:    v_or_b32_e32 v9, v0, v115628; VI-NEXT:    v_lshrrev_b64 v[3:4], 24, v[9:10]15629; VI-NEXT:    v_lshrrev_b32_e32 v5, 8, v1015630; VI-NEXT:    v_lshrrev_b32_e32 v1, 8, v915631; VI-NEXT:    v_bfe_u32 v7, v6, 8, 815632; VI-NEXT:    v_mov_b32_e32 v4, v815633; VI-NEXT:    s_setpc_b64 s[30:31]15634; VI-NEXT:  .LBB105_3:15635; VI-NEXT:    ; implicit-def: $sgpr915636; VI-NEXT:    ; implicit-def: $sgpr1115637; VI-NEXT:    ; implicit-def: $sgpr415638; VI-NEXT:    ; implicit-def: $sgpr515639; VI-NEXT:    ; implicit-def: $sgpr1015640; VI-NEXT:    ; implicit-def: $sgpr815641; VI-NEXT:    s_branch .LBB105_215642; VI-NEXT:  .LBB105_4:15643; VI-NEXT:    v_mov_b32_e32 v2, s1115644; VI-NEXT:    v_mov_b32_e32 v6, s1015645; VI-NEXT:    v_mov_b32_e32 v0, s1615646; VI-NEXT:    v_mov_b32_e32 v7, s815647; VI-NEXT:    v_mov_b32_e32 v1, s915648; VI-NEXT:    v_mov_b32_e32 v5, s515649; VI-NEXT:    v_mov_b32_e32 v3, s415650; VI-NEXT:    v_mov_b32_e32 v4, s1715651; VI-NEXT:    s_setpc_b64 s[30:31]15652;15653; GFX9-LABEL: bitcast_v4f16_to_v8i8_scalar:15654; GFX9:       ; %bb.0:15655; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)15656; GFX9-NEXT:    s_cmp_lg_u32 s18, 015657; GFX9-NEXT:    s_cbranch_scc0 .LBB105_315658; GFX9-NEXT:  ; %bb.1: ; %cmp.false15659; GFX9-NEXT:    s_lshr_b64 s[4:5], s[16:17], 2415660; GFX9-NEXT:    s_lshr_b32 s5, s17, 2415661; GFX9-NEXT:    s_lshr_b32 s8, s17, 1615662; GFX9-NEXT:    s_lshr_b32 s10, s17, 815663; GFX9-NEXT:    s_lshr_b32 s9, s16, 1615664; GFX9-NEXT:    s_lshr_b32 s11, s16, 815665; GFX9-NEXT:    s_cbranch_execnz .LBB105_415666; GFX9-NEXT:  .LBB105_2: ; %cmp.true15667; GFX9-NEXT:    v_mov_b32_e32 v0, 0x20015668; GFX9-NEXT:    v_pk_add_f16 v9, s17, v0 op_sel_hi:[1,0]15669; GFX9-NEXT:    v_pk_add_f16 v8, s16, v0 op_sel_hi:[1,0]15670; GFX9-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]15671; GFX9-NEXT:    v_lshrrev_b32_e32 v7, 24, v915672; GFX9-NEXT:    v_lshrrev_b32_e32 v6, 16, v915673; GFX9-NEXT:    v_lshrrev_b32_e32 v5, 8, v915674; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 16, v815675; GFX9-NEXT:    v_lshrrev_b32_e32 v1, 8, v815676; GFX9-NEXT:    s_branch .LBB105_515677; GFX9-NEXT:  .LBB105_3:15678; GFX9-NEXT:    ; implicit-def: $sgpr1115679; GFX9-NEXT:    ; implicit-def: $sgpr915680; GFX9-NEXT:    ; implicit-def: $sgpr415681; GFX9-NEXT:    ; implicit-def: $sgpr1015682; GFX9-NEXT:    ; implicit-def: $sgpr815683; GFX9-NEXT:    ; implicit-def: $sgpr515684; GFX9-NEXT:    s_branch .LBB105_215685; GFX9-NEXT:  .LBB105_4:15686; GFX9-NEXT:    v_mov_b32_e32 v8, s1615687; GFX9-NEXT:    v_mov_b32_e32 v9, s1715688; GFX9-NEXT:    v_mov_b32_e32 v1, s1115689; GFX9-NEXT:    v_mov_b32_e32 v2, s915690; GFX9-NEXT:    v_mov_b32_e32 v5, s1015691; GFX9-NEXT:    v_mov_b32_e32 v6, s815692; GFX9-NEXT:    v_mov_b32_e32 v7, s515693; GFX9-NEXT:    v_mov_b32_e32 v3, s415694; GFX9-NEXT:  .LBB105_5: ; %end15695; GFX9-NEXT:    v_mov_b32_e32 v0, v815696; GFX9-NEXT:    v_mov_b32_e32 v4, v915697; GFX9-NEXT:    s_setpc_b64 s[30:31]15698;15699; GFX11-LABEL: bitcast_v4f16_to_v8i8_scalar:15700; GFX11:       ; %bb.0:15701; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)15702; GFX11-NEXT:    s_cmp_lg_u32 s2, 015703; GFX11-NEXT:    s_mov_b32 s4, 015704; GFX11-NEXT:    s_cbranch_scc0 .LBB105_315705; GFX11-NEXT:  ; %bb.1: ; %cmp.false15706; GFX11-NEXT:    s_lshr_b64 s[2:3], s[0:1], 2415707; GFX11-NEXT:    s_lshr_b32 s3, s1, 2415708; GFX11-NEXT:    s_lshr_b32 s5, s1, 1615709; GFX11-NEXT:    s_lshr_b32 s7, s1, 815710; GFX11-NEXT:    s_lshr_b32 s6, s0, 1615711; GFX11-NEXT:    s_lshr_b32 s8, s0, 815712; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s415713; GFX11-NEXT:    s_cbranch_vccnz .LBB105_415714; GFX11-NEXT:  .LBB105_2: ; %cmp.true15715; GFX11-NEXT:    v_pk_add_f16 v9, 0x200, s1 op_sel_hi:[0,1]15716; GFX11-NEXT:    v_pk_add_f16 v8, 0x200, s0 op_sel_hi:[0,1]15717; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)15718; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v915719; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]15720; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v915721; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v915722; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v815723; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v815724; GFX11-NEXT:    s_branch .LBB105_515725; GFX11-NEXT:  .LBB105_3:15726; GFX11-NEXT:    ; implicit-def: $sgpr815727; GFX11-NEXT:    ; implicit-def: $sgpr615728; GFX11-NEXT:    ; implicit-def: $sgpr215729; GFX11-NEXT:    ; implicit-def: $sgpr715730; GFX11-NEXT:    ; implicit-def: $sgpr515731; GFX11-NEXT:    ; implicit-def: $sgpr315732; GFX11-NEXT:    s_branch .LBB105_215733; GFX11-NEXT:  .LBB105_4:15734; GFX11-NEXT:    v_dual_mov_b32 v8, s0 :: v_dual_mov_b32 v9, s115735; GFX11-NEXT:    v_dual_mov_b32 v1, s8 :: v_dual_mov_b32 v2, s615736; GFX11-NEXT:    v_dual_mov_b32 v5, s7 :: v_dual_mov_b32 v6, s515737; GFX11-NEXT:    v_mov_b32_e32 v7, s315738; GFX11-NEXT:    v_mov_b32_e32 v3, s215739; GFX11-NEXT:  .LBB105_5: ; %end15740; GFX11-NEXT:    v_mov_b32_e32 v0, v815741; GFX11-NEXT:    v_mov_b32_e32 v4, v915742; GFX11-NEXT:    s_setpc_b64 s[30:31]15743  %cmp = icmp eq i32 %b, 015744  br i1 %cmp, label %cmp.true, label %cmp.false15745 15746cmp.true:15747  %a1 = fadd <4 x half> %a, splat (half 0xH0200)15748  %a2 = bitcast <4 x half> %a1 to <8 x i8>15749  br label %end15750 15751cmp.false:15752  %a3 = bitcast <4 x half> %a to <8 x i8>15753  br label %end15754 15755end:15756  %phi = phi <8 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]15757  ret <8 x i8> %phi15758}15759 15760define <4 x half> @bitcast_v8i8_to_v4f16(<8 x i8> %a, i32 %b) {15761; SI-LABEL: bitcast_v8i8_to_v4f16:15762; SI:       ; %bb.0:15763; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)15764; SI-NEXT:    v_mov_b32_e32 v10, v215765; SI-NEXT:    v_mov_b32_e32 v9, v015766; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v815767; SI-NEXT:    v_lshlrev_b32_e32 v12, 8, v115768; SI-NEXT:    v_lshlrev_b32_e32 v11, 8, v315769; SI-NEXT:    v_lshlrev_b32_e32 v8, 8, v515770; SI-NEXT:    v_lshlrev_b32_e32 v5, 8, v715771; SI-NEXT:    ; implicit-def: $vgpr015772; SI-NEXT:    ; implicit-def: $vgpr115773; SI-NEXT:    ; implicit-def: $vgpr215774; SI-NEXT:    ; implicit-def: $vgpr315775; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc15776; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]15777; SI-NEXT:    s_cbranch_execnz .LBB106_315778; SI-NEXT:  ; %bb.1: ; %Flow15779; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]15780; SI-NEXT:    s_cbranch_execnz .LBB106_415781; SI-NEXT:  .LBB106_2: ; %end15782; SI-NEXT:    s_or_b64 exec, exec, s[4:5]15783; SI-NEXT:    s_setpc_b64 s[30:31]15784; SI-NEXT:  .LBB106_3: ; %cmp.false15785; SI-NEXT:    v_and_b32_e32 v0, 0xff, v915786; SI-NEXT:    v_and_b32_e32 v1, 0xff, v1015787; SI-NEXT:    v_and_b32_e32 v2, 0xff, v415788; SI-NEXT:    v_and_b32_e32 v3, 0xff, v615789; SI-NEXT:    v_or_b32_e32 v0, v0, v1215790; SI-NEXT:    v_or_b32_e32 v1, v1, v1115791; SI-NEXT:    v_or_b32_e32 v2, v2, v815792; SI-NEXT:    v_or_b32_e32 v3, v3, v515793; SI-NEXT:    v_cvt_f32_f16_e32 v0, v015794; SI-NEXT:    v_cvt_f32_f16_e32 v1, v115795; SI-NEXT:    v_cvt_f32_f16_e32 v2, v215796; SI-NEXT:    v_cvt_f32_f16_e32 v3, v315797; SI-NEXT:    ; implicit-def: $vgpr615798; SI-NEXT:    ; implicit-def: $vgpr515799; SI-NEXT:    ; implicit-def: $vgpr415800; SI-NEXT:    ; implicit-def: $vgpr815801; SI-NEXT:    ; implicit-def: $vgpr1015802; SI-NEXT:    ; implicit-def: $vgpr1115803; SI-NEXT:    ; implicit-def: $vgpr915804; SI-NEXT:    ; implicit-def: $vgpr1215805; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]15806; SI-NEXT:    s_cbranch_execz .LBB106_215807; SI-NEXT:  .LBB106_4: ; %cmp.true15808; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v615809; SI-NEXT:    v_and_b32_e32 v0, 0xff, v015810; SI-NEXT:    v_or_b32_e32 v0, v5, v015811; SI-NEXT:    v_add_i32_e32 v3, vcc, 0x300, v015812; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v415813; SI-NEXT:    v_and_b32_e32 v0, 0xff, v015814; SI-NEXT:    v_or_b32_e32 v0, v8, v015815; SI-NEXT:    v_add_i32_e32 v2, vcc, 0x300, v015816; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v1015817; SI-NEXT:    v_and_b32_e32 v0, 0xff, v015818; SI-NEXT:    v_or_b32_e32 v0, v11, v015819; SI-NEXT:    v_add_i32_e32 v1, vcc, 0x300, v015820; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v915821; SI-NEXT:    v_and_b32_e32 v0, 0xff, v015822; SI-NEXT:    v_or_b32_e32 v0, v12, v015823; SI-NEXT:    v_add_i32_e32 v0, vcc, 0x300, v015824; SI-NEXT:    v_cvt_f32_f16_e32 v0, v015825; SI-NEXT:    v_cvt_f32_f16_e32 v1, v115826; SI-NEXT:    v_cvt_f32_f16_e32 v2, v215827; SI-NEXT:    v_cvt_f32_f16_e32 v3, v315828; SI-NEXT:    s_or_b64 exec, exec, s[4:5]15829; SI-NEXT:    s_setpc_b64 s[30:31]15830;15831; VI-LABEL: bitcast_v8i8_to_v4f16:15832; VI:       ; %bb.0:15833; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)15834; VI-NEXT:    v_mov_b32_e32 v9, v015835; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v815836; VI-NEXT:    v_lshlrev_b16_e32 v10, 8, v115837; VI-NEXT:    v_lshlrev_b16_e32 v8, 8, v315838; VI-NEXT:    v_lshlrev_b16_e32 v5, 8, v515839; VI-NEXT:    v_lshlrev_b16_e32 v3, 8, v715840; VI-NEXT:    ; implicit-def: $vgpr0_vgpr115841; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc15842; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]15843; VI-NEXT:    s_cbranch_execnz .LBB106_315844; VI-NEXT:  ; %bb.1: ; %Flow15845; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]15846; VI-NEXT:    s_cbranch_execnz .LBB106_415847; VI-NEXT:  .LBB106_2: ; %end15848; VI-NEXT:    s_or_b64 exec, exec, s[4:5]15849; VI-NEXT:    s_setpc_b64 s[30:31]15850; VI-NEXT:  .LBB106_3: ; %cmp.false15851; VI-NEXT:    v_or_b32_sdwa v0, v9, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD15852; VI-NEXT:    v_or_b32_sdwa v1, v2, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD15853; VI-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD15854; VI-NEXT:    v_or_b32_sdwa v1, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD15855; VI-NEXT:    v_or_b32_sdwa v2, v6, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD15856; VI-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD15857; VI-NEXT:    ; implicit-def: $vgpr915858; VI-NEXT:    ; implicit-def: $vgpr1015859; VI-NEXT:    ; implicit-def: $vgpr215860; VI-NEXT:    ; implicit-def: $vgpr815861; VI-NEXT:    ; implicit-def: $vgpr415862; VI-NEXT:    ; implicit-def: $vgpr515863; VI-NEXT:    ; implicit-def: $vgpr615864; VI-NEXT:    ; implicit-def: $vgpr315865; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]15866; VI-NEXT:    s_cbranch_execz .LBB106_215867; VI-NEXT:  .LBB106_4: ; %cmp.true15868; VI-NEXT:    v_add_u16_e32 v0, 3, v915869; VI-NEXT:    v_add_u16_e32 v1, 3, v215870; VI-NEXT:    v_or_b32_sdwa v0, v10, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_015871; VI-NEXT:    v_or_b32_sdwa v1, v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_015872; VI-NEXT:    v_mov_b32_e32 v2, 0x30015873; VI-NEXT:    v_add_u16_e32 v0, 0x300, v015874; VI-NEXT:    v_add_u16_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD15875; VI-NEXT:    v_or_b32_e32 v0, v0, v115876; VI-NEXT:    v_add_u16_e32 v1, 3, v415877; VI-NEXT:    v_add_u16_e32 v4, 3, v615878; VI-NEXT:    v_or_b32_sdwa v1, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_015879; VI-NEXT:    v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_015880; VI-NEXT:    v_add_u16_e32 v1, 0x300, v115881; VI-NEXT:    v_add_u16_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD15882; VI-NEXT:    v_or_b32_e32 v1, v1, v215883; VI-NEXT:    s_or_b64 exec, exec, s[4:5]15884; VI-NEXT:    s_setpc_b64 s[30:31]15885;15886; GFX9-LABEL: bitcast_v8i8_to_v4f16:15887; GFX9:       ; %bb.0:15888; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)15889; GFX9-NEXT:    v_mov_b32_e32 v9, v015890; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v815891; GFX9-NEXT:    v_lshlrev_b16_e32 v10, 8, v115892; GFX9-NEXT:    v_lshlrev_b16_e32 v8, 8, v315893; GFX9-NEXT:    v_lshlrev_b16_e32 v5, 8, v515894; GFX9-NEXT:    v_lshlrev_b16_e32 v3, 8, v715895; GFX9-NEXT:    ; implicit-def: $vgpr0_vgpr115896; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc15897; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]15898; GFX9-NEXT:    s_cbranch_execnz .LBB106_315899; GFX9-NEXT:  ; %bb.1: ; %Flow15900; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]15901; GFX9-NEXT:    s_cbranch_execnz .LBB106_415902; GFX9-NEXT:  .LBB106_2: ; %end15903; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]15904; GFX9-NEXT:    s_setpc_b64 s[30:31]15905; GFX9-NEXT:  .LBB106_3: ; %cmp.false15906; GFX9-NEXT:    v_or_b32_sdwa v0, v9, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD15907; GFX9-NEXT:    v_or_b32_sdwa v1, v2, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD15908; GFX9-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD15909; GFX9-NEXT:    v_or_b32_sdwa v1, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD15910; GFX9-NEXT:    v_or_b32_sdwa v2, v6, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD15911; GFX9-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD15912; GFX9-NEXT:    ; implicit-def: $vgpr915913; GFX9-NEXT:    ; implicit-def: $vgpr1015914; GFX9-NEXT:    ; implicit-def: $vgpr215915; GFX9-NEXT:    ; implicit-def: $vgpr815916; GFX9-NEXT:    ; implicit-def: $vgpr415917; GFX9-NEXT:    ; implicit-def: $vgpr515918; GFX9-NEXT:    ; implicit-def: $vgpr615919; GFX9-NEXT:    ; implicit-def: $vgpr315920; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]15921; GFX9-NEXT:    s_cbranch_execz .LBB106_215922; GFX9-NEXT:  .LBB106_4: ; %cmp.true15923; GFX9-NEXT:    v_add_u16_e32 v0, 3, v915924; GFX9-NEXT:    v_add_u16_e32 v1, 3, v215925; GFX9-NEXT:    v_or_b32_sdwa v0, v10, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_015926; GFX9-NEXT:    s_movk_i32 s6, 0x30015927; GFX9-NEXT:    v_or_b32_sdwa v1, v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_015928; GFX9-NEXT:    v_add_u16_e32 v0, 0x300, v015929; GFX9-NEXT:    v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD15930; GFX9-NEXT:    v_or_b32_e32 v0, v0, v115931; GFX9-NEXT:    v_add_u16_e32 v1, 3, v415932; GFX9-NEXT:    v_add_u16_e32 v2, 3, v615933; GFX9-NEXT:    v_or_b32_sdwa v1, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_015934; GFX9-NEXT:    v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_015935; GFX9-NEXT:    v_add_u16_e32 v1, 0x300, v115936; GFX9-NEXT:    v_add_u16_sdwa v2, v2, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD15937; GFX9-NEXT:    v_or_b32_e32 v1, v1, v215938; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]15939; GFX9-NEXT:    s_setpc_b64 s[30:31]15940;15941; GFX11-TRUE16-LABEL: bitcast_v8i8_to_v4f16:15942; GFX11-TRUE16:       ; %bb.0:15943; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)15944; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.h, v5.l15945; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.h, v2.l15946; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v0.l15947; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.l, 8, v1.l15948; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.h, 8, v3.l15949; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.l, 8, v5.h15950; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.h, 8, v7.l15951; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo15952; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr115953; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v815954; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s015955; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB106_315956; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow15957; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s015958; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB106_415959; GFX11-TRUE16-NEXT:  .LBB106_2: ; %end15960; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s015961; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]15962; GFX11-TRUE16-NEXT:  .LBB106_3: ; %cmp.false15963; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v5.l15964; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v4.h15965; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v4.l15966; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v6.l15967; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo1615968; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_hi1615969; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_lo1615970; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr6_lo1615971; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)15972; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v2.l15973; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v0.h, v2.h15974; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)15975; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v3.l15976; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v1.h, v3.h15977; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_lo1615978; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_hi1615979; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo1615980; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_hi1615981; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s015982; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB106_215983; GFX11-TRUE16-NEXT:  .LBB106_4: ; %cmp.true15984; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v5.l, 315985; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v4.h, 315986; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v4.l, 315987; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v6.l, 315988; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)15989; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l15990; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h15991; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)15992; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l15993; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h15994; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)15995; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v2.l, v0.l15996; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v2.h, v0.h15997; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)15998; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v3.l, v1.l15999; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v3.h, v1.h16000; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)16001; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l16002; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, 0x300, v0.h16003; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)16004; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.l16005; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, 0x300, v1.h16006; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s016007; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]16008;16009; GFX11-FAKE16-LABEL: bitcast_v8i8_to_v4f16:16010; GFX11-FAKE16:       ; %bb.0:16011; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)16012; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v9, v016013; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v816014; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v8, 8, v116015; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v3, 8, v316016; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v5, 8, v516017; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v7, 8, v716018; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr116019; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo16020; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)16021; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s016022; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB106_316023; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow16024; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s016025; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB106_416026; GFX11-FAKE16-NEXT:  .LBB106_2: ; %end16027; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s016028; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]16029; GFX11-FAKE16-NEXT:  .LBB106_3: ; %cmp.false16030; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v916031; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v216032; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v416033; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v616034; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr916035; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr616036; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)16037; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v816038; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v316039; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)16040; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v516041; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v4, v716042; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr816043; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr416044; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr516045; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr716046; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)16047; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v016048; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v116049; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)16050; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v216051; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v316052; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)16053; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v116054; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v316055; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr216056; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr316057; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s016058; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB106_216059; GFX11-FAKE16-NEXT:  .LBB106_4: ; %cmp.true16060; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v9, 316061; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v2, 316062; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v4, 316063; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v6, 316064; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)16065; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v016066; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v116067; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)16068; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v216069; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v416070; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)16071; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v8, v016072; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v3, v116073; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)16074; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v5, v216075; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v7, v416076; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)16077; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v016078; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v116079; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)16080; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x300, v216081; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v316082; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)16083; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v016084; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v116085; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)16086; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v216087; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v316088; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)16089; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v116090; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v316091; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s016092; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]16093  %cmp = icmp eq i32 %b, 016094  br i1 %cmp, label %cmp.true, label %cmp.false16095 16096cmp.true:16097  %a1 = add <8 x i8> %a, splat (i8 3)16098  %a2 = bitcast <8 x i8> %a1 to <4 x half>16099  br label %end16100 16101cmp.false:16102  %a3 = bitcast <8 x i8> %a to <4 x half>16103  br label %end16104 16105end:16106  %phi = phi <4 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]16107  ret <4 x half> %phi16108}16109 16110define inreg <4 x half> @bitcast_v8i8_to_v4f16_scalar(<8 x i8> inreg %a, i32 inreg %b) {16111; SI-LABEL: bitcast_v8i8_to_v4f16_scalar:16112; SI:       ; %bb.0:16113; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)16114; SI-NEXT:    s_cmp_lg_u32 s24, 016115; SI-NEXT:    s_cbranch_scc0 .LBB107_416116; SI-NEXT:  ; %bb.1: ; %cmp.false16117; SI-NEXT:    s_and_b32 s4, s16, 0xff16118; SI-NEXT:    s_lshl_b32 s5, s17, 816119; SI-NEXT:    s_or_b32 s4, s4, s516120; SI-NEXT:    v_cvt_f32_f16_e32 v0, s416121; SI-NEXT:    s_and_b32 s4, s18, 0xff16122; SI-NEXT:    s_lshl_b32 s5, s19, 816123; SI-NEXT:    s_or_b32 s4, s4, s516124; SI-NEXT:    v_cvt_f32_f16_e32 v1, s416125; SI-NEXT:    s_and_b32 s4, s20, 0xff16126; SI-NEXT:    s_lshl_b32 s5, s21, 816127; SI-NEXT:    s_or_b32 s4, s4, s516128; SI-NEXT:    v_cvt_f32_f16_e32 v2, s416129; SI-NEXT:    s_and_b32 s4, s22, 0xff16130; SI-NEXT:    s_lshl_b32 s5, s23, 816131; SI-NEXT:    s_or_b32 s4, s4, s516132; SI-NEXT:    v_cvt_f32_f16_e32 v3, s416133; SI-NEXT:    s_cbranch_execnz .LBB107_316134; SI-NEXT:  .LBB107_2: ; %cmp.true16135; SI-NEXT:    s_add_i32 s22, s22, 316136; SI-NEXT:    s_and_b32 s4, s22, 0xff16137; SI-NEXT:    s_lshl_b32 s5, s23, 816138; SI-NEXT:    s_add_i32 s20, s20, 316139; SI-NEXT:    s_or_b32 s4, s5, s416140; SI-NEXT:    s_and_b32 s5, s20, 0xff16141; SI-NEXT:    s_lshl_b32 s6, s21, 816142; SI-NEXT:    s_add_i32 s18, s18, 316143; SI-NEXT:    s_or_b32 s5, s6, s516144; SI-NEXT:    s_and_b32 s6, s18, 0xff16145; SI-NEXT:    s_lshl_b32 s7, s19, 816146; SI-NEXT:    s_add_i32 s16, s16, 316147; SI-NEXT:    s_or_b32 s6, s7, s616148; SI-NEXT:    s_and_b32 s7, s16, 0xff16149; SI-NEXT:    s_lshl_b32 s8, s17, 816150; SI-NEXT:    s_or_b32 s7, s8, s716151; SI-NEXT:    s_addk_i32 s4, 0x30016152; SI-NEXT:    s_addk_i32 s5, 0x30016153; SI-NEXT:    s_addk_i32 s6, 0x30016154; SI-NEXT:    s_addk_i32 s7, 0x30016155; SI-NEXT:    v_cvt_f32_f16_e32 v0, s716156; SI-NEXT:    v_cvt_f32_f16_e32 v1, s616157; SI-NEXT:    v_cvt_f32_f16_e32 v2, s516158; SI-NEXT:    v_cvt_f32_f16_e32 v3, s416159; SI-NEXT:  .LBB107_3: ; %end16160; SI-NEXT:    s_setpc_b64 s[30:31]16161; SI-NEXT:  .LBB107_4:16162; SI-NEXT:    ; implicit-def: $vgpr016163; SI-NEXT:    ; implicit-def: $vgpr116164; SI-NEXT:    ; implicit-def: $vgpr216165; SI-NEXT:    ; implicit-def: $vgpr316166; SI-NEXT:    s_branch .LBB107_216167;16168; VI-LABEL: bitcast_v8i8_to_v4f16_scalar:16169; VI:       ; %bb.0:16170; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)16171; VI-NEXT:    s_cmp_lg_u32 s24, 016172; VI-NEXT:    s_cbranch_scc0 .LBB107_416173; VI-NEXT:  ; %bb.1: ; %cmp.false16174; VI-NEXT:    s_and_b32 s4, s16, 0xff16175; VI-NEXT:    s_lshl_b32 s5, s17, 816176; VI-NEXT:    s_or_b32 s4, s4, s516177; VI-NEXT:    s_and_b32 s5, s18, 0xff16178; VI-NEXT:    s_lshl_b32 s6, s19, 816179; VI-NEXT:    s_or_b32 s5, s5, s616180; VI-NEXT:    s_and_b32 s4, s4, 0xffff16181; VI-NEXT:    s_lshl_b32 s5, s5, 1616182; VI-NEXT:    s_or_b32 s4, s4, s516183; VI-NEXT:    s_and_b32 s5, s20, 0xff16184; VI-NEXT:    s_lshl_b32 s6, s21, 816185; VI-NEXT:    s_or_b32 s5, s5, s616186; VI-NEXT:    s_and_b32 s6, s22, 0xff16187; VI-NEXT:    s_lshl_b32 s7, s23, 816188; VI-NEXT:    s_or_b32 s6, s6, s716189; VI-NEXT:    s_and_b32 s5, s5, 0xffff16190; VI-NEXT:    s_lshl_b32 s6, s6, 1616191; VI-NEXT:    s_or_b32 s5, s5, s616192; VI-NEXT:    s_cbranch_execnz .LBB107_316193; VI-NEXT:  .LBB107_2: ; %cmp.true16194; VI-NEXT:    s_add_i32 s16, s16, 316195; VI-NEXT:    s_and_b32 s4, s16, 0xff16196; VI-NEXT:    s_lshl_b32 s5, s17, 816197; VI-NEXT:    s_add_i32 s18, s18, 316198; VI-NEXT:    s_or_b32 s4, s5, s416199; VI-NEXT:    s_and_b32 s5, s18, 0xff16200; VI-NEXT:    s_lshl_b32 s6, s19, 816201; VI-NEXT:    s_addk_i32 s4, 0x30016202; VI-NEXT:    s_or_b32 s5, s6, s516203; VI-NEXT:    s_and_b32 s4, s4, 0xffff16204; VI-NEXT:    s_lshl_b32 s5, s5, 1616205; VI-NEXT:    s_add_i32 s20, s20, 316206; VI-NEXT:    s_or_b32 s4, s5, s416207; VI-NEXT:    s_and_b32 s5, s20, 0xff16208; VI-NEXT:    s_lshl_b32 s6, s21, 816209; VI-NEXT:    s_add_i32 s22, s22, 316210; VI-NEXT:    s_or_b32 s5, s6, s516211; VI-NEXT:    s_and_b32 s6, s22, 0xff16212; VI-NEXT:    s_lshl_b32 s7, s23, 816213; VI-NEXT:    s_addk_i32 s5, 0x30016214; VI-NEXT:    s_or_b32 s6, s7, s616215; VI-NEXT:    s_and_b32 s5, s5, 0xffff16216; VI-NEXT:    s_lshl_b32 s6, s6, 1616217; VI-NEXT:    s_or_b32 s5, s6, s516218; VI-NEXT:    s_add_i32 s4, s4, 0x300000016219; VI-NEXT:    s_add_i32 s5, s5, 0x300000016220; VI-NEXT:  .LBB107_3: ; %end16221; VI-NEXT:    v_mov_b32_e32 v0, s416222; VI-NEXT:    v_mov_b32_e32 v1, s516223; VI-NEXT:    s_setpc_b64 s[30:31]16224; VI-NEXT:  .LBB107_4:16225; VI-NEXT:    ; implicit-def: $sgpr4_sgpr516226; VI-NEXT:    s_branch .LBB107_216227;16228; GFX9-LABEL: bitcast_v8i8_to_v4f16_scalar:16229; GFX9:       ; %bb.0:16230; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)16231; GFX9-NEXT:    s_cmp_lg_u32 s24, 016232; GFX9-NEXT:    s_cbranch_scc0 .LBB107_416233; GFX9-NEXT:  ; %bb.1: ; %cmp.false16234; GFX9-NEXT:    s_and_b32 s4, s16, 0xff16235; GFX9-NEXT:    s_lshl_b32 s5, s17, 816236; GFX9-NEXT:    s_or_b32 s4, s4, s516237; GFX9-NEXT:    s_and_b32 s5, s18, 0xff16238; GFX9-NEXT:    s_lshl_b32 s6, s19, 816239; GFX9-NEXT:    s_or_b32 s5, s5, s616240; GFX9-NEXT:    s_and_b32 s4, s4, 0xffff16241; GFX9-NEXT:    s_lshl_b32 s5, s5, 1616242; GFX9-NEXT:    s_or_b32 s4, s4, s516243; GFX9-NEXT:    s_and_b32 s5, s20, 0xff16244; GFX9-NEXT:    s_lshl_b32 s6, s21, 816245; GFX9-NEXT:    s_or_b32 s5, s5, s616246; GFX9-NEXT:    s_and_b32 s6, s22, 0xff16247; GFX9-NEXT:    s_lshl_b32 s7, s23, 816248; GFX9-NEXT:    s_or_b32 s6, s6, s716249; GFX9-NEXT:    s_and_b32 s5, s5, 0xffff16250; GFX9-NEXT:    s_lshl_b32 s6, s6, 1616251; GFX9-NEXT:    s_or_b32 s5, s5, s616252; GFX9-NEXT:    s_cbranch_execnz .LBB107_316253; GFX9-NEXT:  .LBB107_2: ; %cmp.true16254; GFX9-NEXT:    s_add_i32 s16, s16, 316255; GFX9-NEXT:    s_and_b32 s4, s16, 0xff16256; GFX9-NEXT:    s_lshl_b32 s5, s17, 816257; GFX9-NEXT:    s_add_i32 s18, s18, 316258; GFX9-NEXT:    s_or_b32 s4, s5, s416259; GFX9-NEXT:    s_and_b32 s5, s18, 0xff16260; GFX9-NEXT:    s_lshl_b32 s6, s19, 816261; GFX9-NEXT:    s_or_b32 s5, s6, s516262; GFX9-NEXT:    s_addk_i32 s4, 0x30016263; GFX9-NEXT:    s_addk_i32 s5, 0x30016264; GFX9-NEXT:    s_and_b32 s4, s4, 0xffff16265; GFX9-NEXT:    s_lshl_b32 s5, s5, 1616266; GFX9-NEXT:    s_add_i32 s20, s20, 316267; GFX9-NEXT:    s_or_b32 s4, s4, s516268; GFX9-NEXT:    s_and_b32 s5, s20, 0xff16269; GFX9-NEXT:    s_lshl_b32 s6, s21, 816270; GFX9-NEXT:    s_add_i32 s22, s22, 316271; GFX9-NEXT:    s_or_b32 s5, s6, s516272; GFX9-NEXT:    s_and_b32 s6, s22, 0xff16273; GFX9-NEXT:    s_lshl_b32 s7, s23, 816274; GFX9-NEXT:    s_or_b32 s6, s7, s616275; GFX9-NEXT:    s_addk_i32 s5, 0x30016276; GFX9-NEXT:    s_addk_i32 s6, 0x30016277; GFX9-NEXT:    s_and_b32 s5, s5, 0xffff16278; GFX9-NEXT:    s_lshl_b32 s6, s6, 1616279; GFX9-NEXT:    s_or_b32 s5, s5, s616280; GFX9-NEXT:  .LBB107_3: ; %end16281; GFX9-NEXT:    v_mov_b32_e32 v0, s416282; GFX9-NEXT:    v_mov_b32_e32 v1, s516283; GFX9-NEXT:    s_setpc_b64 s[30:31]16284; GFX9-NEXT:  .LBB107_4:16285; GFX9-NEXT:    ; implicit-def: $sgpr4_sgpr516286; GFX9-NEXT:    s_branch .LBB107_216287;16288; GFX11-LABEL: bitcast_v8i8_to_v4f16_scalar:16289; GFX11:       ; %bb.0:16290; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)16291; GFX11-NEXT:    s_cmp_lg_u32 s20, 016292; GFX11-NEXT:    s_mov_b32 s6, 016293; GFX11-NEXT:    s_cbranch_scc0 .LBB107_416294; GFX11-NEXT:  ; %bb.1: ; %cmp.false16295; GFX11-NEXT:    s_and_b32 s4, s0, 0xff16296; GFX11-NEXT:    s_lshl_b32 s5, s1, 816297; GFX11-NEXT:    s_and_b32 s7, s2, 0xff16298; GFX11-NEXT:    s_lshl_b32 s8, s3, 816299; GFX11-NEXT:    s_or_b32 s4, s4, s516300; GFX11-NEXT:    s_or_b32 s5, s7, s816301; GFX11-NEXT:    s_and_b32 s7, s16, 0xff16302; GFX11-NEXT:    s_lshl_b32 s8, s17, 816303; GFX11-NEXT:    s_and_b32 s9, s18, 0xff16304; GFX11-NEXT:    s_lshl_b32 s10, s19, 816305; GFX11-NEXT:    s_or_b32 s7, s7, s816306; GFX11-NEXT:    s_or_b32 s8, s9, s1016307; GFX11-NEXT:    s_and_b32 s4, s4, 0xffff16308; GFX11-NEXT:    s_lshl_b32 s5, s5, 1616309; GFX11-NEXT:    s_and_b32 s7, s7, 0xffff16310; GFX11-NEXT:    s_lshl_b32 s8, s8, 1616311; GFX11-NEXT:    s_or_b32 s4, s4, s516312; GFX11-NEXT:    s_or_b32 s5, s7, s816313; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s616314; GFX11-NEXT:    s_cbranch_vccnz .LBB107_316315; GFX11-NEXT:  .LBB107_2: ; %cmp.true16316; GFX11-NEXT:    s_add_i32 s0, s0, 316317; GFX11-NEXT:    s_lshl_b32 s1, s1, 816318; GFX11-NEXT:    s_and_b32 s0, s0, 0xff16319; GFX11-NEXT:    s_add_i32 s2, s2, 316320; GFX11-NEXT:    s_or_b32 s0, s1, s016321; GFX11-NEXT:    s_and_b32 s1, s2, 0xff16322; GFX11-NEXT:    s_lshl_b32 s2, s3, 816323; GFX11-NEXT:    s_add_i32 s16, s16, 316324; GFX11-NEXT:    s_add_i32 s18, s18, 316325; GFX11-NEXT:    s_or_b32 s1, s2, s116326; GFX11-NEXT:    s_and_b32 s2, s16, 0xff16327; GFX11-NEXT:    s_lshl_b32 s3, s17, 816328; GFX11-NEXT:    s_and_b32 s4, s18, 0xff16329; GFX11-NEXT:    s_lshl_b32 s5, s19, 816330; GFX11-NEXT:    s_or_b32 s2, s3, s216331; GFX11-NEXT:    s_or_b32 s3, s5, s416332; GFX11-NEXT:    s_addk_i32 s0, 0x30016333; GFX11-NEXT:    s_addk_i32 s1, 0x30016334; GFX11-NEXT:    s_addk_i32 s2, 0x30016335; GFX11-NEXT:    s_addk_i32 s3, 0x30016336; GFX11-NEXT:    s_and_b32 s0, s0, 0xffff16337; GFX11-NEXT:    s_lshl_b32 s1, s1, 1616338; GFX11-NEXT:    s_and_b32 s2, s2, 0xffff16339; GFX11-NEXT:    s_lshl_b32 s3, s3, 1616340; GFX11-NEXT:    s_or_b32 s4, s0, s116341; GFX11-NEXT:    s_or_b32 s5, s2, s316342; GFX11-NEXT:  .LBB107_3: ; %end16343; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)16344; GFX11-NEXT:    v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s516345; GFX11-NEXT:    s_setpc_b64 s[30:31]16346; GFX11-NEXT:  .LBB107_4:16347; GFX11-NEXT:    ; implicit-def: $sgpr4_sgpr516348; GFX11-NEXT:    s_branch .LBB107_216349  %cmp = icmp eq i32 %b, 016350  br i1 %cmp, label %cmp.true, label %cmp.false16351 16352cmp.true:16353  %a1 = add <8 x i8> %a, splat (i8 3)16354  %a2 = bitcast <8 x i8> %a1 to <4 x half>16355  br label %end16356 16357cmp.false:16358  %a3 = bitcast <8 x i8> %a to <4 x half>16359  br label %end16360 16361end:16362  %phi = phi <4 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]16363  ret <4 x half> %phi16364}16365 16366define <8 x i8> @bitcast_v4bf16_to_v8i8(<4 x bfloat> %a, i32 %b) {16367; SI-LABEL: bitcast_v4bf16_to_v8i8:16368; SI:       ; %bb.0:16369; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)16370; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v416371; SI-NEXT:    v_mul_f32_e32 v10, 1.0, v116372; SI-NEXT:    v_mul_f32_e32 v11, 1.0, v016373; SI-NEXT:    v_mul_f32_e32 v8, 1.0, v316374; SI-NEXT:    v_mul_f32_e32 v9, 1.0, v216375; SI-NEXT:    ; implicit-def: $vgpr016376; SI-NEXT:    ; implicit-def: $vgpr116377; SI-NEXT:    ; implicit-def: $vgpr216378; SI-NEXT:    ; implicit-def: $vgpr316379; SI-NEXT:    ; implicit-def: $vgpr416380; SI-NEXT:    ; implicit-def: $vgpr516381; SI-NEXT:    ; implicit-def: $vgpr616382; SI-NEXT:    ; implicit-def: $vgpr716383; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc16384; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]16385; SI-NEXT:    s_cbranch_execnz .LBB108_316386; SI-NEXT:  ; %bb.1: ; %Flow16387; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]16388; SI-NEXT:    s_cbranch_execnz .LBB108_416389; SI-NEXT:  .LBB108_2: ; %end16390; SI-NEXT:    s_or_b64 exec, exec, s[4:5]16391; SI-NEXT:    s_setpc_b64 s[30:31]16392; SI-NEXT:  .LBB108_3: ; %cmp.false16393; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v1016394; SI-NEXT:    v_lshrrev_b32_e32 v6, 16, v816395; SI-NEXT:    v_alignbit_b32 v0, v0, v11, 1616396; SI-NEXT:    v_alignbit_b32 v4, v6, v9, 1616397; SI-NEXT:    v_alignbit_b32 v3, v4, v0, 2416398; SI-NEXT:    v_alignbit_b32 v2, v4, v0, 1616399; SI-NEXT:    v_alignbit_b32 v1, v4, v0, 816400; SI-NEXT:    v_lshrrev_b32_e32 v7, 24, v816401; SI-NEXT:    v_lshrrev_b32_e32 v5, 8, v416402; SI-NEXT:    ; implicit-def: $vgpr1116403; SI-NEXT:    ; implicit-def: $vgpr1016404; SI-NEXT:    ; implicit-def: $vgpr916405; SI-NEXT:    ; implicit-def: $vgpr816406; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]16407; SI-NEXT:    s_cbranch_execz .LBB108_216408; SI-NEXT:  .LBB108_4: ; %cmp.true16409; SI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1016410; SI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v1116411; SI-NEXT:    v_add_f32_e32 v1, 0x40c00000, v116412; SI-NEXT:    v_add_f32_e32 v0, 0x40c00000, v016413; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v116414; SI-NEXT:    v_and_b32_e32 v2, 0xffff0000, v816415; SI-NEXT:    v_alignbit_b32 v0, v1, v0, 1616416; SI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v916417; SI-NEXT:    v_add_f32_e32 v7, 0x40c00000, v216418; SI-NEXT:    v_add_f32_e32 v1, 0x40c00000, v116419; SI-NEXT:    v_lshrrev_b32_e32 v6, 16, v716420; SI-NEXT:    v_alignbit_b32 v4, v6, v1, 1616421; SI-NEXT:    v_alignbit_b32 v3, v4, v0, 2416422; SI-NEXT:    v_alignbit_b32 v2, v4, v0, 1616423; SI-NEXT:    v_alignbit_b32 v1, v4, v0, 816424; SI-NEXT:    v_lshrrev_b32_e32 v5, 8, v416425; SI-NEXT:    v_lshrrev_b32_e32 v7, 24, v716426; SI-NEXT:    s_or_b64 exec, exec, s[4:5]16427; SI-NEXT:    s_setpc_b64 s[30:31]16428;16429; VI-LABEL: bitcast_v4bf16_to_v8i8:16430; VI:       ; %bb.0:16431; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)16432; VI-NEXT:    v_mov_b32_e32 v9, v116433; VI-NEXT:    v_mov_b32_e32 v8, v016434; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v216435; VI-NEXT:    ; implicit-def: $vgpr116436; VI-NEXT:    ; implicit-def: $vgpr216437; VI-NEXT:    ; implicit-def: $vgpr316438; VI-NEXT:    ; implicit-def: $vgpr516439; VI-NEXT:    ; implicit-def: $vgpr616440; VI-NEXT:    ; implicit-def: $vgpr716441; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc16442; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]16443; VI-NEXT:  ; %bb.1: ; %cmp.false16444; VI-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]16445; VI-NEXT:    v_lshrrev_b32_e32 v7, 24, v916446; VI-NEXT:    v_lshrrev_b32_e32 v6, 16, v916447; VI-NEXT:    v_lshrrev_b32_e32 v5, 8, v916448; VI-NEXT:    v_lshrrev_b32_e32 v2, 16, v816449; VI-NEXT:    v_lshrrev_b32_e32 v1, 8, v816450; VI-NEXT:  ; %bb.2: ; %Flow16451; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]16452; VI-NEXT:    s_cbranch_execz .LBB108_416453; VI-NEXT:  ; %bb.3: ; %cmp.true16454; VI-NEXT:    v_lshlrev_b32_e32 v0, 16, v916455; VI-NEXT:    v_add_f32_e32 v0, 0x40c00000, v016456; VI-NEXT:    v_bfe_u32 v1, v0, 16, 116457; VI-NEXT:    v_add_u32_e32 v1, vcc, v1, v016458; VI-NEXT:    v_add_u32_e32 v1, vcc, 0x7fff, v116459; VI-NEXT:    v_or_b32_e32 v2, 0x400000, v016460; VI-NEXT:    v_cmp_u_f32_e32 vcc, v0, v016461; VI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v916462; VI-NEXT:    v_add_f32_e32 v0, 0x40c00000, v016463; VI-NEXT:    v_cndmask_b32_e32 v2, v1, v2, vcc16464; VI-NEXT:    v_bfe_u32 v1, v0, 16, 116465; VI-NEXT:    s_movk_i32 s6, 0x7fff16466; VI-NEXT:    v_add_u32_e32 v1, vcc, v1, v016467; VI-NEXT:    v_add_u32_e32 v1, vcc, s6, v116468; VI-NEXT:    v_or_b32_e32 v3, 0x400000, v016469; VI-NEXT:    v_cmp_u_f32_e32 vcc, v0, v016470; VI-NEXT:    v_cndmask_b32_e32 v0, v1, v3, vcc16471; VI-NEXT:    v_lshrrev_b32_e32 v6, 16, v016472; VI-NEXT:    v_lshlrev_b32_e32 v0, 16, v816473; VI-NEXT:    v_add_f32_e32 v0, 0x40c00000, v016474; VI-NEXT:    v_bfe_u32 v3, v0, 16, 116475; VI-NEXT:    v_add_u32_e32 v3, vcc, v3, v016476; VI-NEXT:    v_add_u32_e32 v3, vcc, s6, v316477; VI-NEXT:    v_or_b32_e32 v4, 0x400000, v016478; VI-NEXT:    v_cmp_u_f32_e32 vcc, v0, v016479; VI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v816480; VI-NEXT:    v_add_f32_e32 v0, 0x40c00000, v016481; VI-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc16482; VI-NEXT:    v_bfe_u32 v4, v0, 16, 116483; VI-NEXT:    v_add_u32_e32 v4, vcc, v4, v016484; VI-NEXT:    v_add_u32_e32 v4, vcc, s6, v416485; VI-NEXT:    v_or_b32_e32 v5, 0x400000, v016486; VI-NEXT:    v_cmp_u_f32_e32 vcc, v0, v016487; VI-NEXT:    v_cndmask_b32_e32 v0, v4, v5, vcc16488; VI-NEXT:    v_lshrrev_b32_e32 v0, 16, v016489; VI-NEXT:    v_alignbit_b32 v1, v6, v2, 1616490; VI-NEXT:    v_alignbit_b32 v0, v0, v3, 1616491; VI-NEXT:    v_lshrrev_b32_e32 v8, 16, v316492; VI-NEXT:    v_lshrrev_b64 v[3:4], 24, v[0:1]16493; VI-NEXT:    v_lshrrev_b32_e32 v9, 16, v216494; VI-NEXT:    v_lshrrev_b32_e32 v7, 24, v116495; VI-NEXT:    v_lshrrev_b32_e32 v5, 8, v116496; VI-NEXT:    v_lshrrev_b32_e32 v2, 16, v016497; VI-NEXT:    v_lshrrev_b32_e32 v1, 8, v016498; VI-NEXT:  .LBB108_4: ; %end16499; VI-NEXT:    s_or_b64 exec, exec, s[4:5]16500; VI-NEXT:    v_mov_b32_e32 v0, v816501; VI-NEXT:    v_mov_b32_e32 v4, v916502; VI-NEXT:    s_setpc_b64 s[30:31]16503;16504; GFX9-LABEL: bitcast_v4bf16_to_v8i8:16505; GFX9:       ; %bb.0:16506; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)16507; GFX9-NEXT:    v_mov_b32_e32 v9, v116508; GFX9-NEXT:    v_mov_b32_e32 v8, v016509; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v216510; GFX9-NEXT:    ; implicit-def: $vgpr116511; GFX9-NEXT:    ; implicit-def: $vgpr216512; GFX9-NEXT:    ; implicit-def: $vgpr316513; GFX9-NEXT:    ; implicit-def: $vgpr516514; GFX9-NEXT:    ; implicit-def: $vgpr616515; GFX9-NEXT:    ; implicit-def: $vgpr716516; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc16517; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]16518; GFX9-NEXT:  ; %bb.1: ; %cmp.false16519; GFX9-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]16520; GFX9-NEXT:    v_lshrrev_b32_e32 v7, 24, v916521; GFX9-NEXT:    v_lshrrev_b32_e32 v6, 16, v916522; GFX9-NEXT:    v_lshrrev_b32_e32 v5, 8, v916523; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 16, v816524; GFX9-NEXT:    v_lshrrev_b32_e32 v1, 8, v816525; GFX9-NEXT:  ; %bb.2: ; %Flow16526; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]16527; GFX9-NEXT:    s_cbranch_execz .LBB108_416528; GFX9-NEXT:  ; %bb.3: ; %cmp.true16529; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 16, v816530; GFX9-NEXT:    v_add_f32_e32 v0, 0x40c00000, v016531; GFX9-NEXT:    v_bfe_u32 v1, v0, 16, 116532; GFX9-NEXT:    s_movk_i32 s6, 0x7fff16533; GFX9-NEXT:    v_add3_u32 v1, v1, v0, s616534; GFX9-NEXT:    v_or_b32_e32 v2, 0x400000, v016535; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v0, v016536; GFX9-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc16537; GFX9-NEXT:    v_and_b32_e32 v1, 0xffff0000, v816538; GFX9-NEXT:    v_add_f32_e32 v1, 0x40c00000, v116539; GFX9-NEXT:    v_bfe_u32 v2, v1, 16, 116540; GFX9-NEXT:    v_add3_u32 v2, v2, v1, s616541; GFX9-NEXT:    v_or_b32_e32 v3, 0x400000, v116542; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v1, v116543; GFX9-NEXT:    v_cndmask_b32_e32 v1, v2, v3, vcc16544; GFX9-NEXT:    s_mov_b32 s7, 0x706030216545; GFX9-NEXT:    v_perm_b32 v10, v1, v0, s716546; GFX9-NEXT:    v_and_b32_e32 v1, 0xffff0000, v916547; GFX9-NEXT:    v_add_f32_e32 v1, 0x40c00000, v116548; GFX9-NEXT:    v_bfe_u32 v2, v1, 16, 116549; GFX9-NEXT:    v_add3_u32 v2, v2, v1, s616550; GFX9-NEXT:    v_or_b32_e32 v3, 0x400000, v116551; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v1, v116552; GFX9-NEXT:    v_cndmask_b32_e32 v1, v2, v3, vcc16553; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 16, v916554; GFX9-NEXT:    v_add_f32_e32 v2, 0x40c00000, v216555; GFX9-NEXT:    v_bfe_u32 v3, v2, 16, 116556; GFX9-NEXT:    v_add3_u32 v3, v3, v2, s616557; GFX9-NEXT:    v_or_b32_e32 v4, 0x400000, v216558; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v2, v216559; GFX9-NEXT:    v_cndmask_b32_e32 v2, v3, v4, vcc16560; GFX9-NEXT:    v_perm_b32 v11, v1, v2, s716561; GFX9-NEXT:    v_lshrrev_b64 v[3:4], 24, v[10:11]16562; GFX9-NEXT:    v_lshrrev_b32_e32 v6, 16, v116563; GFX9-NEXT:    v_lshrrev_b32_e32 v8, 16, v016564; GFX9-NEXT:    v_lshrrev_b32_e32 v9, 16, v216565; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 16, v1016566; GFX9-NEXT:    v_lshrrev_b32_e32 v1, 8, v1016567; GFX9-NEXT:    v_lshrrev_b32_e32 v7, 24, v1116568; GFX9-NEXT:    v_lshrrev_b32_e32 v5, 8, v1116569; GFX9-NEXT:  .LBB108_4: ; %end16570; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]16571; GFX9-NEXT:    v_mov_b32_e32 v0, v816572; GFX9-NEXT:    v_mov_b32_e32 v4, v916573; GFX9-NEXT:    s_setpc_b64 s[30:31]16574;16575; GFX11-TRUE16-LABEL: bitcast_v4bf16_to_v8i8:16576; GFX11-TRUE16:       ; %bb.0:16577; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)16578; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v216579; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_hi1616580; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo1616581; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr8_hi1616582; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr6_lo1616583; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_hi1616584; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo1616585; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_lo1616586; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo16587; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)16588; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s016589; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB108_216590; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false16591; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[6:7], 24, v[0:1]16592; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v116593; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v116594; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 8, v016595; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v0.l16596; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.h, v0.h16597; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.h, v1.l16598; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.h, v1.h16599; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr116600; GFX11-TRUE16-NEXT:  .LBB108_2: ; %Flow16601; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s016602; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB108_416603; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true16604; GFX11-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v016605; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, 016606; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.h, v0.l16607; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v116608; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)16609; GFX11-TRUE16-NEXT:    v_dual_add_f32 v5, 0x40c00000, v2 :: v_dual_add_f32 v2, 0x40c00000, v316610; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.h, v1.l16611; GFX11-TRUE16-NEXT:    v_add_f32_e32 v0, 0x40c00000, v016612; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)16613; GFX11-TRUE16-NEXT:    v_bfe_u32 v1, v5, 16, 116614; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, 0x400000, v516615; GFX11-TRUE16-NEXT:    v_bfe_u32 v4, v2, 16, 116616; GFX11-TRUE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v316617; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, 0x400000, v216618; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v216619; GFX11-TRUE16-NEXT:    v_bfe_u32 v8, v0, 16, 116620; GFX11-TRUE16-NEXT:    v_add3_u32 v4, v4, v2, 0x7fff16621; GFX11-TRUE16-NEXT:    v_bfe_u32 v9, v3, 16, 116622; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, 0x400000, v316623; GFX11-TRUE16-NEXT:    v_add3_u32 v1, v1, v5, 0x7fff16624; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, 0x400000, v016625; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v4, v7, vcc_lo16626; GFX11-TRUE16-NEXT:    v_add3_u32 v9, v9, v3, 0x7fff16627; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v316628; GFX11-TRUE16-NEXT:    v_add3_u32 v12, v8, v0, 0x7fff16629; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)16630; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v4, v9, v11, vcc_lo16631; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v516632; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v8, v1, v6, vcc_lo16633; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v016634; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v2.h16635; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v9, v12, v10, vcc_lo16636; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.l, v4.h16637; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)16638; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 8, v816639; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[6:7], 24, v[8:9]16640; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v916641; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v916642; GFX11-TRUE16-NEXT:  .LBB108_4: ; %end16643; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s016644; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v2.h16645; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v3.l16646; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v8.h16647; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v6.l16648; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v4.h16649; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v9.h16650; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]16651;16652; GFX11-FAKE16-LABEL: bitcast_v4bf16_to_v8i8:16653; GFX11-FAKE16:       ; %bb.0:16654; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)16655; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v016656; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v216657; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr116658; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr216659; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr316660; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr516661; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr616662; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr716663; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo16664; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)16665; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s016666; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false16667; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)16668; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]16669; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v916670; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v916671; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v916672; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v816673; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v816674; GFX11-FAKE16-NEXT:  ; %bb.2: ; %Flow16675; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s016676; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB108_416677; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true16678; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff0000, v816679; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)16680; GFX11-FAKE16-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v0, 16, v816681; GFX11-FAKE16-NEXT:    v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v3, 16, v916682; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)16683; GFX11-FAKE16-NEXT:    v_bfe_u32 v6, v1, 16, 116684; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, 0x400000, v116685; GFX11-FAKE16-NEXT:    v_bfe_u32 v4, v0, 16, 116686; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, 0x400000, v016687; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v016688; GFX11-FAKE16-NEXT:    v_add3_u32 v6, v6, v1, 0x7fff16689; GFX11-FAKE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v316690; GFX11-FAKE16-NEXT:    v_add3_u32 v4, v4, v0, 0x7fff16691; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)16692; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v4, v5, vcc_lo16693; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v116694; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v916695; GFX11-FAKE16-NEXT:    v_bfe_u32 v9, v3, 16, 116696; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, 0x400000, v316697; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v1, v6, v7 :: v_dual_add_f32 v2, 0x40c00000, v216698; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)16699; GFX11-FAKE16-NEXT:    v_add3_u32 v9, v9, v3, 0x7fff16700; GFX11-FAKE16-NEXT:    v_bfe_u32 v8, v2, 16, 116701; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, 0x400000, v216702; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v216703; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)16704; GFX11-FAKE16-NEXT:    v_add3_u32 v8, v8, v2, 0x7fff16705; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v8, v10, vcc_lo16706; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v316707; GFX11-FAKE16-NEXT:    v_perm_b32 v10, v1, v0, 0x706030216708; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v8, 16, v016709; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v9, v4, vcc_lo16710; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v216711; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)16712; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v1016713; GFX11-FAKE16-NEXT:    v_perm_b32 v11, v2, v3, 0x706030216714; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 16, v316715; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v1016716; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)16717; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[10:11]16718; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v1116719; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v1116720; GFX11-FAKE16-NEXT:  .LBB108_4: ; %end16721; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s016722; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, v816723; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, v916724; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]16725  %cmp = icmp eq i32 %b, 016726  br i1 %cmp, label %cmp.true, label %cmp.false16727 16728cmp.true:16729  %a1 = fadd <4 x bfloat> %a, splat (bfloat 0xR40C0)16730  %a2 = bitcast <4 x bfloat> %a1 to <8 x i8>16731  br label %end16732 16733cmp.false:16734  %a3 = bitcast <4 x bfloat> %a to <8 x i8>16735  br label %end16736 16737end:16738  %phi = phi <8 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]16739  ret <8 x i8> %phi16740}16741 16742define inreg <8 x i8> @bitcast_v4bf16_to_v8i8_scalar(<4 x bfloat> inreg %a, i32 inreg %b) {16743; SI-LABEL: bitcast_v4bf16_to_v8i8_scalar:16744; SI:       ; %bb.0:16745; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)16746; SI-NEXT:    s_cmp_lg_u32 s20, 016747; SI-NEXT:    v_mul_f32_e64 v15, 1.0, s1716748; SI-NEXT:    v_mul_f32_e64 v0, 1.0, s1616749; SI-NEXT:    v_mul_f32_e64 v14, 1.0, s1916750; SI-NEXT:    v_mul_f32_e64 v5, 1.0, s1816751; SI-NEXT:    s_cbranch_scc0 .LBB109_416752; SI-NEXT:  ; %bb.1: ; %cmp.false16753; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v1516754; SI-NEXT:    v_lshr_b64 v[11:12], v[0:1], 1616755; SI-NEXT:    v_lshrrev_b32_e32 v6, 16, v1416756; SI-NEXT:    v_lshr_b64 v[12:13], v[5:6], 1616757; SI-NEXT:    v_lshrrev_b32_e32 v7, 24, v1416758; SI-NEXT:    v_lshr_b64 v[3:4], v[11:12], 2416759; SI-NEXT:    v_lshr_b64 v[9:10], v[11:12], 1616760; SI-NEXT:    v_lshr_b64 v[1:2], v[11:12], 816761; SI-NEXT:    v_lshrrev_b32_e32 v8, 8, v1216762; SI-NEXT:    s_cbranch_execnz .LBB109_316763; SI-NEXT:  .LBB109_2: ; %cmp.true16764; SI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1516765; SI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v016766; SI-NEXT:    v_add_f32_e32 v1, 0x40c00000, v116767; SI-NEXT:    v_add_f32_e32 v0, 0x40c00000, v016768; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v116769; SI-NEXT:    v_lshr_b64 v[11:12], v[0:1], 1616770; SI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v516771; SI-NEXT:    v_add_f32_e32 v5, 0x40c00000, v016772; SI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v1416773; SI-NEXT:    v_add_f32_e32 v0, 0x40c00000, v016774; SI-NEXT:    v_lshrrev_b32_e32 v6, 16, v016775; SI-NEXT:    v_lshr_b64 v[12:13], v[5:6], 1616776; SI-NEXT:    v_lshrrev_b32_e32 v7, 24, v016777; SI-NEXT:    v_lshr_b64 v[3:4], v[11:12], 2416778; SI-NEXT:    v_lshr_b64 v[9:10], v[11:12], 1616779; SI-NEXT:    v_lshr_b64 v[1:2], v[11:12], 816780; SI-NEXT:    v_lshrrev_b32_e32 v8, 8, v1216781; SI-NEXT:  .LBB109_3: ; %end16782; SI-NEXT:    v_mov_b32_e32 v0, v1116783; SI-NEXT:    v_mov_b32_e32 v2, v916784; SI-NEXT:    v_mov_b32_e32 v4, v1216785; SI-NEXT:    v_mov_b32_e32 v5, v816786; SI-NEXT:    s_setpc_b64 s[30:31]16787; SI-NEXT:  .LBB109_4:16788; SI-NEXT:    ; implicit-def: $vgpr1116789; SI-NEXT:    ; implicit-def: $vgpr116790; SI-NEXT:    ; implicit-def: $vgpr916791; SI-NEXT:    ; implicit-def: $vgpr316792; SI-NEXT:    ; implicit-def: $vgpr816793; SI-NEXT:    ; implicit-def: $vgpr716794; SI-NEXT:    s_branch .LBB109_216795;16796; VI-LABEL: bitcast_v4bf16_to_v8i8_scalar:16797; VI:       ; %bb.0:16798; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)16799; VI-NEXT:    s_cmp_lg_u32 s18, 016800; VI-NEXT:    s_cbranch_scc0 .LBB109_316801; VI-NEXT:  ; %bb.1: ; %cmp.false16802; VI-NEXT:    s_lshr_b64 s[4:5], s[16:17], 2416803; VI-NEXT:    s_lshr_b32 s5, s17, 2416804; VI-NEXT:    s_lshr_b32 s11, s17, 1616805; VI-NEXT:    s_lshr_b32 s8, s17, 816806; VI-NEXT:    s_lshr_b32 s10, s16, 1616807; VI-NEXT:    s_lshr_b32 s9, s16, 816808; VI-NEXT:    s_cbranch_execnz .LBB109_416809; VI-NEXT:  .LBB109_2: ; %cmp.true16810; VI-NEXT:    s_lshl_b32 s4, s17, 1616811; VI-NEXT:    v_mov_b32_e32 v0, 0x40c0000016812; VI-NEXT:    v_add_f32_e32 v1, s4, v016813; VI-NEXT:    v_bfe_u32 v2, v1, 16, 116814; VI-NEXT:    v_add_u32_e32 v2, vcc, v2, v116815; VI-NEXT:    v_add_u32_e32 v2, vcc, 0x7fff, v216816; VI-NEXT:    s_and_b32 s4, s17, 0xffff000016817; VI-NEXT:    v_or_b32_e32 v3, 0x400000, v116818; VI-NEXT:    v_cmp_u_f32_e32 vcc, v1, v116819; VI-NEXT:    v_add_f32_e32 v1, s4, v016820; VI-NEXT:    v_cndmask_b32_e32 v5, v2, v3, vcc16821; VI-NEXT:    v_bfe_u32 v2, v1, 16, 116822; VI-NEXT:    v_add_u32_e32 v2, vcc, v2, v116823; VI-NEXT:    v_add_u32_e32 v2, vcc, 0x7fff, v216824; VI-NEXT:    v_or_b32_e32 v3, 0x400000, v116825; VI-NEXT:    v_cmp_u_f32_e32 vcc, v1, v116826; VI-NEXT:    v_cndmask_b32_e32 v1, v2, v3, vcc16827; VI-NEXT:    v_lshrrev_b32_e32 v6, 16, v116828; VI-NEXT:    v_lshrrev_b64 v[1:2], 16, v[5:6]16829; VI-NEXT:    s_lshl_b32 s4, s16, 1616830; VI-NEXT:    v_add_f32_e32 v2, s4, v016831; VI-NEXT:    v_bfe_u32 v3, v2, 16, 116832; VI-NEXT:    v_add_u32_e32 v3, vcc, v3, v216833; VI-NEXT:    v_add_u32_e32 v3, vcc, 0x7fff, v316834; VI-NEXT:    s_and_b32 s4, s16, 0xffff000016835; VI-NEXT:    v_or_b32_e32 v4, 0x400000, v216836; VI-NEXT:    v_cmp_u_f32_e32 vcc, v2, v216837; VI-NEXT:    v_add_f32_e32 v0, s4, v016838; VI-NEXT:    v_cndmask_b32_e32 v2, v3, v4, vcc16839; VI-NEXT:    v_bfe_u32 v3, v0, 16, 116840; VI-NEXT:    v_add_u32_e32 v3, vcc, v3, v016841; VI-NEXT:    v_add_u32_e32 v3, vcc, 0x7fff, v316842; VI-NEXT:    v_or_b32_e32 v4, 0x400000, v016843; VI-NEXT:    v_cmp_u_f32_e32 vcc, v0, v016844; VI-NEXT:    v_cndmask_b32_e32 v0, v3, v4, vcc16845; VI-NEXT:    v_lshrrev_b32_e32 v3, 16, v016846; VI-NEXT:    v_lshrrev_b64 v[9:10], 16, v[2:3]16847; VI-NEXT:    v_mov_b32_e32 v10, v116848; VI-NEXT:    v_lshrrev_b32_e32 v8, 16, v516849; VI-NEXT:    v_lshrrev_b64 v[3:4], 24, v[9:10]16850; VI-NEXT:    v_lshrrev_b32_e32 v0, 16, v216851; VI-NEXT:    v_lshrrev_b32_e32 v7, 24, v116852; VI-NEXT:    v_lshrrev_b32_e32 v5, 8, v116853; VI-NEXT:    v_lshrrev_b32_e32 v2, 16, v916854; VI-NEXT:    v_lshrrev_b32_e32 v1, 8, v916855; VI-NEXT:    v_mov_b32_e32 v4, v816856; VI-NEXT:    s_setpc_b64 s[30:31]16857; VI-NEXT:  .LBB109_3:16858; VI-NEXT:    ; implicit-def: $sgpr916859; VI-NEXT:    ; implicit-def: $sgpr1016860; VI-NEXT:    ; implicit-def: $sgpr416861; VI-NEXT:    ; implicit-def: $sgpr816862; VI-NEXT:    ; implicit-def: $sgpr1116863; VI-NEXT:    ; implicit-def: $sgpr516864; VI-NEXT:    s_branch .LBB109_216865; VI-NEXT:  .LBB109_4:16866; VI-NEXT:    v_mov_b32_e32 v0, s1616867; VI-NEXT:    v_mov_b32_e32 v6, s1116868; VI-NEXT:    v_mov_b32_e32 v2, s1016869; VI-NEXT:    v_mov_b32_e32 v1, s916870; VI-NEXT:    v_mov_b32_e32 v7, s516871; VI-NEXT:    v_mov_b32_e32 v5, s816872; VI-NEXT:    v_mov_b32_e32 v3, s416873; VI-NEXT:    v_mov_b32_e32 v4, s1716874; VI-NEXT:    s_setpc_b64 s[30:31]16875;16876; GFX9-LABEL: bitcast_v4bf16_to_v8i8_scalar:16877; GFX9:       ; %bb.0:16878; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)16879; GFX9-NEXT:    s_cmp_lg_u32 s18, 016880; GFX9-NEXT:    s_cbranch_scc0 .LBB109_316881; GFX9-NEXT:  ; %bb.1: ; %cmp.false16882; GFX9-NEXT:    s_lshr_b64 s[4:5], s[16:17], 2416883; GFX9-NEXT:    s_lshr_b32 s9, s17, 2416884; GFX9-NEXT:    s_lshr_b32 s11, s17, 1616885; GFX9-NEXT:    s_lshr_b32 s10, s17, 816886; GFX9-NEXT:    s_lshr_b32 s8, s16, 1616887; GFX9-NEXT:    s_lshr_b32 s5, s16, 816888; GFX9-NEXT:    s_cbranch_execnz .LBB109_416889; GFX9-NEXT:  .LBB109_2: ; %cmp.true16890; GFX9-NEXT:    s_pack_lh_b32_b16 s4, 0, s1616891; GFX9-NEXT:    v_mov_b32_e32 v1, 0x40c0000016892; GFX9-NEXT:    v_add_f32_e32 v0, s4, v116893; GFX9-NEXT:    v_bfe_u32 v2, v0, 16, 116894; GFX9-NEXT:    v_add_u32_e32 v2, v2, v016895; GFX9-NEXT:    v_add_u32_e32 v2, 0x7fff, v216896; GFX9-NEXT:    v_or_b32_e32 v3, 0x400000, v016897; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v0, v016898; GFX9-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc16899; GFX9-NEXT:    s_lshl_b32 s4, s16, 1616900; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 16, v016901; GFX9-NEXT:    v_add_f32_e32 v0, s4, v116902; GFX9-NEXT:    v_bfe_u32 v3, v0, 16, 116903; GFX9-NEXT:    v_add_u32_e32 v3, v3, v016904; GFX9-NEXT:    v_add_u32_e32 v3, 0x7fff, v316905; GFX9-NEXT:    v_or_b32_e32 v4, 0x400000, v016906; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v0, v016907; GFX9-NEXT:    v_cndmask_b32_e32 v0, v3, v4, vcc16908; GFX9-NEXT:    v_lshrrev_b32_e32 v0, 16, v016909; GFX9-NEXT:    v_and_b32_e32 v3, 0xffff, v016910; GFX9-NEXT:    s_pack_lh_b32_b16 s4, 0, s1716911; GFX9-NEXT:    v_lshl_or_b32 v9, v2, 16, v316912; GFX9-NEXT:    v_add_f32_e32 v2, s4, v116913; GFX9-NEXT:    v_bfe_u32 v3, v2, 16, 116914; GFX9-NEXT:    v_add_u32_e32 v3, v3, v216915; GFX9-NEXT:    v_add_u32_e32 v3, 0x7fff, v316916; GFX9-NEXT:    v_or_b32_e32 v4, 0x400000, v216917; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v2, v216918; GFX9-NEXT:    s_lshl_b32 s4, s17, 1616919; GFX9-NEXT:    v_cndmask_b32_e32 v2, v3, v4, vcc16920; GFX9-NEXT:    v_add_f32_e32 v1, s4, v116921; GFX9-NEXT:    v_lshrrev_b32_e32 v6, 16, v216922; GFX9-NEXT:    v_bfe_u32 v2, v1, 16, 116923; GFX9-NEXT:    v_add_u32_e32 v2, v2, v116924; GFX9-NEXT:    v_add_u32_e32 v2, 0x7fff, v216925; GFX9-NEXT:    v_or_b32_e32 v3, 0x400000, v116926; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v1, v116927; GFX9-NEXT:    v_cndmask_b32_e32 v1, v2, v3, vcc16928; GFX9-NEXT:    v_lshrrev_b32_e32 v8, 16, v116929; GFX9-NEXT:    v_and_b32_e32 v1, 0xffff, v816930; GFX9-NEXT:    v_lshl_or_b32 v10, v6, 16, v116931; GFX9-NEXT:    v_lshrrev_b64 v[3:4], 24, v[9:10]16932; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 16, v916933; GFX9-NEXT:    v_lshrrev_b32_e32 v1, 8, v916934; GFX9-NEXT:    v_lshrrev_b32_e32 v7, 24, v1016935; GFX9-NEXT:    v_lshrrev_b32_e32 v5, 8, v1016936; GFX9-NEXT:    v_mov_b32_e32 v4, v816937; GFX9-NEXT:    s_setpc_b64 s[30:31]16938; GFX9-NEXT:  .LBB109_3:16939; GFX9-NEXT:    ; implicit-def: $sgpr516940; GFX9-NEXT:    ; implicit-def: $sgpr816941; GFX9-NEXT:    ; implicit-def: $sgpr416942; GFX9-NEXT:    ; implicit-def: $sgpr1016943; GFX9-NEXT:    ; implicit-def: $sgpr1116944; GFX9-NEXT:    ; implicit-def: $sgpr916945; GFX9-NEXT:    s_branch .LBB109_216946; GFX9-NEXT:  .LBB109_4:16947; GFX9-NEXT:    v_mov_b32_e32 v6, s1116948; GFX9-NEXT:    v_mov_b32_e32 v0, s1616949; GFX9-NEXT:    v_mov_b32_e32 v7, s916950; GFX9-NEXT:    v_mov_b32_e32 v5, s1016951; GFX9-NEXT:    v_mov_b32_e32 v2, s816952; GFX9-NEXT:    v_mov_b32_e32 v1, s516953; GFX9-NEXT:    v_mov_b32_e32 v3, s416954; GFX9-NEXT:    v_mov_b32_e32 v4, s1716955; GFX9-NEXT:    s_setpc_b64 s[30:31]16956;16957; GFX11-TRUE16-LABEL: bitcast_v4bf16_to_v8i8_scalar:16958; GFX11-TRUE16:       ; %bb.0:16959; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)16960; GFX11-TRUE16-NEXT:    s_cmp_lg_u32 s2, 016961; GFX11-TRUE16-NEXT:    s_mov_b32 s4, 016962; GFX11-TRUE16-NEXT:    s_cbranch_scc0 .LBB109_316963; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false16964; GFX11-TRUE16-NEXT:    s_lshr_b64 s[2:3], s[0:1], 2416965; GFX11-TRUE16-NEXT:    s_lshr_b32 s6, s1, 2416966; GFX11-TRUE16-NEXT:    s_lshr_b32 s8, s1, 1616967; GFX11-TRUE16-NEXT:    s_lshr_b32 s7, s1, 816968; GFX11-TRUE16-NEXT:    s_lshr_b32 s5, s0, 1616969; GFX11-TRUE16-NEXT:    s_lshr_b32 s3, s0, 816970; GFX11-TRUE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s416971; GFX11-TRUE16-NEXT:    s_cbranch_vccnz .LBB109_416972; GFX11-TRUE16-NEXT:  .LBB109_2: ; %cmp.true16973; GFX11-TRUE16-NEXT:    s_pack_lh_b32_b16 s2, 0, s016974; GFX11-TRUE16-NEXT:    s_lshl_b32 s0, s0, 1616975; GFX11-TRUE16-NEXT:    v_add_f32_e64 v0, 0x40c00000, s216976; GFX11-TRUE16-NEXT:    s_pack_lh_b32_b16 s2, 0, s116977; GFX11-TRUE16-NEXT:    v_add_f32_e64 v1, 0x40c00000, s016978; GFX11-TRUE16-NEXT:    s_lshl_b32 s0, s1, 1616979; GFX11-TRUE16-NEXT:    v_add_f32_e64 v2, 0x40c00000, s216980; GFX11-TRUE16-NEXT:    v_bfe_u32 v3, v0, 16, 116981; GFX11-TRUE16-NEXT:    v_add_f32_e64 v4, 0x40c00000, s016982; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, 0x400000, v016983; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v016984; GFX11-TRUE16-NEXT:    v_bfe_u32 v6, v2, 16, 116985; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v3, v3, v016986; GFX11-TRUE16-NEXT:    v_bfe_u32 v8, v4, 16, 116987; GFX11-TRUE16-NEXT:    v_bfe_u32 v5, v1, 16, 116988; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, 0x400000, v116989; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)16990; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v3, 0x7fff, v316991; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v3, v3, v7 :: v_dual_add_nc_u32 v6, v6, v216992; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v116993; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v8, v8, v416994; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)16995; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v6, 0x7fff, v616996; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, 0x400000, v416997; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v0, 0x7fff, v816998; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, 0x400000, v216999; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v5, v5, v117000; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)17001; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v5, 0x7fff, v517002; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v5, v9, vcc_lo17003; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v417004; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v4, v0, v7, vcc_lo17005; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v217006; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)17007; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v117008; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v317009; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v6, v8, vcc_lo17010; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v8, 16, v417011; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.l, v0.l17012; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)17013; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.h, v1.l17014; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v217015; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)17016; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v10.l, v8.l17017; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v917018; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v917019; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)17020; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v10.h, v6.l17021; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[9:10]17022; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v1017023; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v1017024; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v4, v817025; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]17026; GFX11-TRUE16-NEXT:  .LBB109_3:17027; GFX11-TRUE16-NEXT:    ; implicit-def: $sgpr317028; GFX11-TRUE16-NEXT:    ; implicit-def: $sgpr517029; GFX11-TRUE16-NEXT:    ; implicit-def: $sgpr217030; GFX11-TRUE16-NEXT:    ; implicit-def: $sgpr717031; GFX11-TRUE16-NEXT:    ; implicit-def: $sgpr817032; GFX11-TRUE16-NEXT:    ; implicit-def: $sgpr617033; GFX11-TRUE16-NEXT:    s_branch .LBB109_217034; GFX11-TRUE16-NEXT:  .LBB109_4:17035; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, s617036; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v5, s717037; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v2, s5 :: v_dual_mov_b32 v1, s317038; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v3, s2 :: v_dual_mov_b32 v4, s117039; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]17040;17041; GFX11-FAKE16-LABEL: bitcast_v4bf16_to_v8i8_scalar:17042; GFX11-FAKE16:       ; %bb.0:17043; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)17044; GFX11-FAKE16-NEXT:    s_cmp_lg_u32 s2, 017045; GFX11-FAKE16-NEXT:    s_mov_b32 s4, 017046; GFX11-FAKE16-NEXT:    s_cbranch_scc0 .LBB109_317047; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false17048; GFX11-FAKE16-NEXT:    s_lshr_b64 s[2:3], s[0:1], 2417049; GFX11-FAKE16-NEXT:    s_lshr_b32 s6, s1, 2417050; GFX11-FAKE16-NEXT:    s_lshr_b32 s8, s1, 1617051; GFX11-FAKE16-NEXT:    s_lshr_b32 s7, s1, 817052; GFX11-FAKE16-NEXT:    s_lshr_b32 s5, s0, 1617053; GFX11-FAKE16-NEXT:    s_lshr_b32 s3, s0, 817054; GFX11-FAKE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s417055; GFX11-FAKE16-NEXT:    s_cbranch_vccnz .LBB109_417056; GFX11-FAKE16-NEXT:  .LBB109_2: ; %cmp.true17057; GFX11-FAKE16-NEXT:    s_pack_lh_b32_b16 s2, 0, s017058; GFX11-FAKE16-NEXT:    s_lshl_b32 s0, s0, 1617059; GFX11-FAKE16-NEXT:    v_add_f32_e64 v0, 0x40c00000, s217060; GFX11-FAKE16-NEXT:    v_add_f32_e64 v1, 0x40c00000, s017061; GFX11-FAKE16-NEXT:    s_lshl_b32 s0, s1, 1617062; GFX11-FAKE16-NEXT:    s_pack_lh_b32_b16 s1, 0, s117063; GFX11-FAKE16-NEXT:    v_add_f32_e64 v2, 0x40c00000, s017064; GFX11-FAKE16-NEXT:    v_add_f32_e64 v5, 0x40c00000, s117065; GFX11-FAKE16-NEXT:    v_bfe_u32 v4, v1, 16, 117066; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, 0x400000, v017067; GFX11-FAKE16-NEXT:    v_bfe_u32 v3, v0, 16, 117068; GFX11-FAKE16-NEXT:    v_bfe_u32 v6, v2, 16, 117069; GFX11-FAKE16-NEXT:    v_bfe_u32 v8, v5, 16, 117070; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v4, v4, v117071; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, 0x400000, v117072; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v117073; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, 0x400000, v217074; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v8, v8, v517075; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v4, 0x7fff, v417076; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)17077; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v1, v4, v9 :: v_dual_add_nc_u32 v6, v6, v217078; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v4, 0x7fff, v817079; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, 0x400000, v517080; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)17081; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v6, 0x7fff, v617082; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v217083; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v2, v6, v10 :: v_dual_add_nc_u32 v3, v3, v017084; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)17085; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v3, 0x7fff, v317086; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v017087; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v117088; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v3, v7, vcc_lo17089; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v517090; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v4, v8, vcc_lo17091; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v8, 16, v217092; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)17093; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v317094; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v017095; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v117096; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)17097; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v817098; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v9, v2, 16, v317099; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)17100; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v10, v6, 16, v117101; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v917102; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v917103; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)17104; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[9:10]17105; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v1017106; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v1017107; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, v817108; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]17109; GFX11-FAKE16-NEXT:  .LBB109_3:17110; GFX11-FAKE16-NEXT:    ; implicit-def: $sgpr317111; GFX11-FAKE16-NEXT:    ; implicit-def: $sgpr517112; GFX11-FAKE16-NEXT:    ; implicit-def: $sgpr217113; GFX11-FAKE16-NEXT:    ; implicit-def: $sgpr717114; GFX11-FAKE16-NEXT:    ; implicit-def: $sgpr817115; GFX11-FAKE16-NEXT:    ; implicit-def: $sgpr617116; GFX11-FAKE16-NEXT:    s_branch .LBB109_217117; GFX11-FAKE16-NEXT:  .LBB109_4:17118; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, s617119; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v5, s717120; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v2, s5 :: v_dual_mov_b32 v1, s317121; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v3, s2 :: v_dual_mov_b32 v4, s117122; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]17123  %cmp = icmp eq i32 %b, 017124  br i1 %cmp, label %cmp.true, label %cmp.false17125 17126cmp.true:17127  %a1 = fadd <4 x bfloat> %a, splat (bfloat 0xR40C0)17128  %a2 = bitcast <4 x bfloat> %a1 to <8 x i8>17129  br label %end17130 17131cmp.false:17132  %a3 = bitcast <4 x bfloat> %a to <8 x i8>17133  br label %end17134 17135end:17136  %phi = phi <8 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]17137  ret <8 x i8> %phi17138}17139 17140define <4 x bfloat> @bitcast_v8i8_to_v4bf16(<8 x i8> %a, i32 %b) {17141; SI-LABEL: bitcast_v8i8_to_v4bf16:17142; SI:       ; %bb.0:17143; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)17144; SI-NEXT:    v_mov_b32_e32 v10, v117145; SI-NEXT:    v_mov_b32_e32 v9, v017146; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v817147; SI-NEXT:    v_lshlrev_b32_e32 v8, 24, v317148; SI-NEXT:    v_lshlrev_b32_e32 v11, 8, v517149; SI-NEXT:    v_lshlrev_b32_e32 v5, 24, v717150; SI-NEXT:    ; implicit-def: $vgpr017151; SI-NEXT:    ; implicit-def: $vgpr117152; SI-NEXT:    ; implicit-def: $vgpr717153; SI-NEXT:    ; implicit-def: $vgpr317154; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc17155; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]17156; SI-NEXT:    s_cbranch_execz .LBB110_217157; SI-NEXT:  ; %bb.1: ; %cmp.false17158; SI-NEXT:    v_and_b32_e32 v0, 0xff, v917159; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v017160; SI-NEXT:    v_lshlrev_b32_e32 v1, 24, v1017161; SI-NEXT:    v_or_b32_e32 v0, v1, v017162; SI-NEXT:    v_and_b32_e32 v1, 0xff, v217163; SI-NEXT:    v_and_b32_e32 v2, 0xff, v417164; SI-NEXT:    v_or_b32_e32 v2, v2, v1117165; SI-NEXT:    v_lshlrev_b32_e32 v7, 16, v217166; SI-NEXT:    v_and_b32_e32 v2, 0xff, v617167; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v117168; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v217169; SI-NEXT:    v_or_b32_e32 v1, v8, v117170; SI-NEXT:    v_or_b32_e32 v3, v5, v217171; SI-NEXT:    ; implicit-def: $vgpr417172; SI-NEXT:    ; implicit-def: $vgpr1117173; SI-NEXT:    ; implicit-def: $vgpr617174; SI-NEXT:    ; implicit-def: $vgpr517175; SI-NEXT:    ; implicit-def: $vgpr917176; SI-NEXT:    ; implicit-def: $vgpr1017177; SI-NEXT:    ; implicit-def: $vgpr217178; SI-NEXT:    ; implicit-def: $vgpr817179; SI-NEXT:  .LBB110_2: ; %Flow17180; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]17181; SI-NEXT:    s_cbranch_execz .LBB110_417182; SI-NEXT:  ; %bb.3: ; %cmp.true17183; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v417184; SI-NEXT:    v_and_b32_e32 v0, 0xff, v017185; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v617186; SI-NEXT:    v_or_b32_e32 v0, v11, v017187; SI-NEXT:    v_and_b32_e32 v1, 0xff, v117188; SI-NEXT:    v_add_i32_e32 v0, vcc, 0x300, v017189; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v117190; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v017191; SI-NEXT:    v_or_b32_e32 v1, v5, v117192; SI-NEXT:    v_or_b32_e32 v0, v1, v017193; SI-NEXT:    v_add_i32_e32 v4, vcc, 0x3000000, v017194; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v917195; SI-NEXT:    v_and_b32_e32 v0, 0xff, v017196; SI-NEXT:    v_lshlrev_b32_e32 v1, 8, v1017197; SI-NEXT:    v_or_b32_e32 v0, v1, v017198; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v217199; SI-NEXT:    v_and_b32_e32 v1, 0xff, v117200; SI-NEXT:    v_add_i32_e32 v0, vcc, 0x300, v017201; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v117202; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v017203; SI-NEXT:    v_or_b32_e32 v1, v8, v117204; SI-NEXT:    v_or_b32_e32 v0, v1, v017205; SI-NEXT:    v_add_i32_e32 v0, vcc, 0x3000000, v017206; SI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v017207; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v017208; SI-NEXT:    v_and_b32_e32 v3, 0xffff0000, v417209; SI-NEXT:    v_lshlrev_b32_e32 v7, 16, v417210; SI-NEXT:  .LBB110_4: ; %end17211; SI-NEXT:    s_or_b64 exec, exec, s[4:5]17212; SI-NEXT:    v_mov_b32_e32 v2, v717213; SI-NEXT:    s_setpc_b64 s[30:31]17214;17215; VI-LABEL: bitcast_v8i8_to_v4bf16:17216; VI:       ; %bb.0:17217; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)17218; VI-NEXT:    v_mov_b32_e32 v9, v017219; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v817220; VI-NEXT:    v_lshlrev_b16_e32 v10, 8, v117221; VI-NEXT:    v_lshlrev_b16_e32 v8, 8, v317222; VI-NEXT:    v_lshlrev_b16_e32 v5, 8, v517223; VI-NEXT:    v_lshlrev_b16_e32 v3, 8, v717224; VI-NEXT:    ; implicit-def: $vgpr0_vgpr117225; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc17226; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]17227; VI-NEXT:    s_cbranch_execnz .LBB110_317228; VI-NEXT:  ; %bb.1: ; %Flow17229; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]17230; VI-NEXT:    s_cbranch_execnz .LBB110_417231; VI-NEXT:  .LBB110_2: ; %end17232; VI-NEXT:    s_or_b64 exec, exec, s[4:5]17233; VI-NEXT:    s_setpc_b64 s[30:31]17234; VI-NEXT:  .LBB110_3: ; %cmp.false17235; VI-NEXT:    v_or_b32_sdwa v0, v9, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD17236; VI-NEXT:    v_or_b32_sdwa v1, v2, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD17237; VI-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD17238; VI-NEXT:    v_or_b32_sdwa v1, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD17239; VI-NEXT:    v_or_b32_sdwa v2, v6, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD17240; VI-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD17241; VI-NEXT:    ; implicit-def: $vgpr917242; VI-NEXT:    ; implicit-def: $vgpr1017243; VI-NEXT:    ; implicit-def: $vgpr217244; VI-NEXT:    ; implicit-def: $vgpr817245; VI-NEXT:    ; implicit-def: $vgpr417246; VI-NEXT:    ; implicit-def: $vgpr517247; VI-NEXT:    ; implicit-def: $vgpr617248; VI-NEXT:    ; implicit-def: $vgpr317249; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]17250; VI-NEXT:    s_cbranch_execz .LBB110_217251; VI-NEXT:  .LBB110_4: ; %cmp.true17252; VI-NEXT:    v_add_u16_e32 v0, 3, v917253; VI-NEXT:    v_add_u16_e32 v1, 3, v217254; VI-NEXT:    v_or_b32_sdwa v0, v10, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_017255; VI-NEXT:    v_or_b32_sdwa v1, v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_017256; VI-NEXT:    v_mov_b32_e32 v2, 0x30017257; VI-NEXT:    v_add_u16_e32 v0, 0x300, v017258; VI-NEXT:    v_add_u16_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD17259; VI-NEXT:    v_or_b32_e32 v0, v0, v117260; VI-NEXT:    v_add_u16_e32 v1, 3, v417261; VI-NEXT:    v_add_u16_e32 v4, 3, v617262; VI-NEXT:    v_or_b32_sdwa v1, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_017263; VI-NEXT:    v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_017264; VI-NEXT:    v_add_u16_e32 v1, 0x300, v117265; VI-NEXT:    v_add_u16_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD17266; VI-NEXT:    v_or_b32_e32 v1, v1, v217267; VI-NEXT:    s_or_b64 exec, exec, s[4:5]17268; VI-NEXT:    s_setpc_b64 s[30:31]17269;17270; GFX9-LABEL: bitcast_v8i8_to_v4bf16:17271; GFX9:       ; %bb.0:17272; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)17273; GFX9-NEXT:    v_mov_b32_e32 v9, v017274; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v817275; GFX9-NEXT:    v_lshlrev_b16_e32 v10, 8, v117276; GFX9-NEXT:    v_lshlrev_b16_e32 v8, 8, v317277; GFX9-NEXT:    v_lshlrev_b16_e32 v5, 8, v517278; GFX9-NEXT:    v_lshlrev_b16_e32 v3, 8, v717279; GFX9-NEXT:    ; implicit-def: $vgpr0_vgpr117280; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc17281; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]17282; GFX9-NEXT:    s_cbranch_execnz .LBB110_317283; GFX9-NEXT:  ; %bb.1: ; %Flow17284; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]17285; GFX9-NEXT:    s_cbranch_execnz .LBB110_417286; GFX9-NEXT:  .LBB110_2: ; %end17287; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]17288; GFX9-NEXT:    s_setpc_b64 s[30:31]17289; GFX9-NEXT:  .LBB110_3: ; %cmp.false17290; GFX9-NEXT:    v_or_b32_sdwa v0, v9, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD17291; GFX9-NEXT:    v_or_b32_sdwa v1, v2, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD17292; GFX9-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD17293; GFX9-NEXT:    v_or_b32_sdwa v1, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD17294; GFX9-NEXT:    v_or_b32_sdwa v2, v6, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD17295; GFX9-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD17296; GFX9-NEXT:    ; implicit-def: $vgpr917297; GFX9-NEXT:    ; implicit-def: $vgpr1017298; GFX9-NEXT:    ; implicit-def: $vgpr217299; GFX9-NEXT:    ; implicit-def: $vgpr817300; GFX9-NEXT:    ; implicit-def: $vgpr417301; GFX9-NEXT:    ; implicit-def: $vgpr517302; GFX9-NEXT:    ; implicit-def: $vgpr617303; GFX9-NEXT:    ; implicit-def: $vgpr317304; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]17305; GFX9-NEXT:    s_cbranch_execz .LBB110_217306; GFX9-NEXT:  .LBB110_4: ; %cmp.true17307; GFX9-NEXT:    v_add_u16_e32 v0, 3, v917308; GFX9-NEXT:    v_add_u16_e32 v1, 3, v217309; GFX9-NEXT:    v_or_b32_sdwa v0, v10, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_017310; GFX9-NEXT:    s_movk_i32 s6, 0x30017311; GFX9-NEXT:    v_or_b32_sdwa v1, v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_017312; GFX9-NEXT:    v_add_u16_e32 v0, 0x300, v017313; GFX9-NEXT:    v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD17314; GFX9-NEXT:    v_or_b32_e32 v0, v0, v117315; GFX9-NEXT:    v_add_u16_e32 v1, 3, v417316; GFX9-NEXT:    v_add_u16_e32 v2, 3, v617317; GFX9-NEXT:    v_or_b32_sdwa v1, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_017318; GFX9-NEXT:    v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_017319; GFX9-NEXT:    v_add_u16_e32 v1, 0x300, v117320; GFX9-NEXT:    v_add_u16_sdwa v2, v2, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD17321; GFX9-NEXT:    v_or_b32_e32 v1, v1, v217322; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]17323; GFX9-NEXT:    s_setpc_b64 s[30:31]17324;17325; GFX11-TRUE16-LABEL: bitcast_v8i8_to_v4bf16:17326; GFX11-TRUE16:       ; %bb.0:17327; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)17328; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.h, v5.l17329; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.h, v2.l17330; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v0.l17331; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.l, 8, v1.l17332; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.h, 8, v3.l17333; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.l, 8, v5.h17334; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.h, 8, v7.l17335; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo17336; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr117337; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v817338; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s017339; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB110_317340; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow17341; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s017342; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB110_417343; GFX11-TRUE16-NEXT:  .LBB110_2: ; %end17344; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s017345; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]17346; GFX11-TRUE16-NEXT:  .LBB110_3: ; %cmp.false17347; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v5.l17348; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v4.h17349; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v4.l17350; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v6.l17351; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo1617352; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_hi1617353; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_lo1617354; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr6_lo1617355; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)17356; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v2.l17357; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v0.h, v2.h17358; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)17359; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v3.l17360; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v1.h, v3.h17361; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_lo1617362; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_hi1617363; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo1617364; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_hi1617365; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s017366; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB110_217367; GFX11-TRUE16-NEXT:  .LBB110_4: ; %cmp.true17368; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v5.l, 317369; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v4.h, 317370; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v4.l, 317371; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v6.l, 317372; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)17373; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l17374; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h17375; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)17376; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l17377; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h17378; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)17379; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v2.l, v0.l17380; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v2.h, v0.h17381; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)17382; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v3.l, v1.l17383; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v3.h, v1.h17384; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)17385; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l17386; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, 0x300, v0.h17387; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)17388; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.l17389; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, 0x300, v1.h17390; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s017391; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]17392;17393; GFX11-FAKE16-LABEL: bitcast_v8i8_to_v4bf16:17394; GFX11-FAKE16:       ; %bb.0:17395; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)17396; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v9, v017397; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v817398; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v8, 8, v117399; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v3, 8, v317400; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v5, 8, v517401; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v7, 8, v717402; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr117403; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo17404; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)17405; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s017406; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB110_317407; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow17408; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s017409; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB110_417410; GFX11-FAKE16-NEXT:  .LBB110_2: ; %end17411; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s017412; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]17413; GFX11-FAKE16-NEXT:  .LBB110_3: ; %cmp.false17414; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v917415; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v217416; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v417417; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v617418; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr917419; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr617420; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)17421; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v817422; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v317423; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)17424; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v517425; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v4, v717426; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr817427; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr417428; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr517429; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr717430; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)17431; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v017432; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v117433; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)17434; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v217435; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v317436; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)17437; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v117438; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v317439; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr217440; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr317441; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s017442; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB110_217443; GFX11-FAKE16-NEXT:  .LBB110_4: ; %cmp.true17444; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v9, 317445; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v2, 317446; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v4, 317447; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v6, 317448; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)17449; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v017450; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v117451; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)17452; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v217453; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v417454; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)17455; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v8, v017456; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v3, v117457; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)17458; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v5, v217459; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v7, v417460; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)17461; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v017462; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v117463; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)17464; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x300, v217465; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v317466; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)17467; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v017468; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v117469; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)17470; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v217471; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v317472; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)17473; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v117474; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v317475; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s017476; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]17477  %cmp = icmp eq i32 %b, 017478  br i1 %cmp, label %cmp.true, label %cmp.false17479 17480cmp.true:17481  %a1 = add <8 x i8> %a, splat (i8 3)17482  %a2 = bitcast <8 x i8> %a1 to <4 x bfloat>17483  br label %end17484 17485cmp.false:17486  %a3 = bitcast <8 x i8> %a to <4 x bfloat>17487  br label %end17488 17489end:17490  %phi = phi <4 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ]17491  ret <4 x bfloat> %phi17492}17493 17494define inreg <4 x bfloat> @bitcast_v8i8_to_v4bf16_scalar(<8 x i8> inreg %a, i32 inreg %b) {17495; SI-LABEL: bitcast_v8i8_to_v4bf16_scalar:17496; SI:       ; %bb.0:17497; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)17498; SI-NEXT:    s_cmp_lg_u32 s24, 017499; SI-NEXT:    s_cbranch_scc0 .LBB111_417500; SI-NEXT:  ; %bb.1: ; %cmp.false17501; SI-NEXT:    s_and_b32 s4, s16, 0xff17502; SI-NEXT:    s_lshl_b32 s4, s4, 1617503; SI-NEXT:    s_lshl_b32 s5, s17, 2417504; SI-NEXT:    s_or_b32 s6, s5, s417505; SI-NEXT:    s_and_b32 s4, s18, 0xff17506; SI-NEXT:    s_lshl_b32 s4, s4, 1617507; SI-NEXT:    s_lshl_b32 s5, s19, 2417508; SI-NEXT:    s_or_b32 s7, s5, s417509; SI-NEXT:    s_and_b32 s4, s20, 0xff17510; SI-NEXT:    s_lshl_b32 s5, s21, 817511; SI-NEXT:    s_or_b32 s4, s4, s517512; SI-NEXT:    s_lshl_b32 s8, s4, 1617513; SI-NEXT:    s_and_b32 s4, s22, 0xff17514; SI-NEXT:    s_lshl_b32 s4, s4, 1617515; SI-NEXT:    s_lshl_b32 s5, s23, 2417516; SI-NEXT:    s_or_b32 s9, s5, s417517; SI-NEXT:    s_cbranch_execnz .LBB111_317518; SI-NEXT:  .LBB111_2: ; %cmp.true17519; SI-NEXT:    s_add_i32 s20, s20, 317520; SI-NEXT:    s_and_b32 s4, s20, 0xff17521; SI-NEXT:    s_lshl_b32 s5, s21, 817522; SI-NEXT:    s_add_i32 s22, s22, 317523; SI-NEXT:    s_or_b32 s4, s5, s417524; SI-NEXT:    s_and_b32 s6, s22, 0xff17525; SI-NEXT:    s_addk_i32 s4, 0x30017526; SI-NEXT:    s_lshl_b32 s5, s23, 2417527; SI-NEXT:    s_lshl_b32 s6, s6, 1617528; SI-NEXT:    s_and_b32 s4, s4, 0xffff17529; SI-NEXT:    s_or_b32 s5, s5, s617530; SI-NEXT:    s_add_i32 s16, s16, 317531; SI-NEXT:    s_or_b32 s4, s5, s417532; SI-NEXT:    s_and_b32 s5, s16, 0xff17533; SI-NEXT:    s_lshl_b32 s6, s17, 817534; SI-NEXT:    s_add_i32 s18, s18, 317535; SI-NEXT:    s_or_b32 s5, s6, s517536; SI-NEXT:    s_and_b32 s7, s18, 0xff17537; SI-NEXT:    s_addk_i32 s5, 0x30017538; SI-NEXT:    s_lshl_b32 s6, s19, 2417539; SI-NEXT:    s_lshl_b32 s7, s7, 1617540; SI-NEXT:    s_and_b32 s5, s5, 0xffff17541; SI-NEXT:    s_or_b32 s6, s6, s717542; SI-NEXT:    s_or_b32 s5, s6, s517543; SI-NEXT:    s_add_i32 s4, s4, 0x300000017544; SI-NEXT:    s_add_i32 s5, s5, 0x300000017545; SI-NEXT:    s_and_b32 s7, s5, 0xffff000017546; SI-NEXT:    s_lshl_b32 s6, s5, 1617547; SI-NEXT:    s_and_b32 s9, s4, 0xffff000017548; SI-NEXT:    s_lshl_b32 s8, s4, 1617549; SI-NEXT:  .LBB111_3: ; %end17550; SI-NEXT:    v_mov_b32_e32 v0, s617551; SI-NEXT:    v_mov_b32_e32 v1, s717552; SI-NEXT:    v_mov_b32_e32 v2, s817553; SI-NEXT:    v_mov_b32_e32 v3, s917554; SI-NEXT:    s_setpc_b64 s[30:31]17555; SI-NEXT:  .LBB111_4:17556; SI-NEXT:    ; implicit-def: $sgpr617557; SI-NEXT:    ; implicit-def: $sgpr717558; SI-NEXT:    ; implicit-def: $sgpr817559; SI-NEXT:    ; implicit-def: $sgpr917560; SI-NEXT:    s_branch .LBB111_217561;17562; VI-LABEL: bitcast_v8i8_to_v4bf16_scalar:17563; VI:       ; %bb.0:17564; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)17565; VI-NEXT:    s_cmp_lg_u32 s24, 017566; VI-NEXT:    s_cbranch_scc0 .LBB111_417567; VI-NEXT:  ; %bb.1: ; %cmp.false17568; VI-NEXT:    s_and_b32 s4, s16, 0xff17569; VI-NEXT:    s_lshl_b32 s5, s17, 817570; VI-NEXT:    s_or_b32 s4, s4, s517571; VI-NEXT:    s_and_b32 s5, s18, 0xff17572; VI-NEXT:    s_lshl_b32 s6, s19, 817573; VI-NEXT:    s_or_b32 s5, s5, s617574; VI-NEXT:    s_and_b32 s4, s4, 0xffff17575; VI-NEXT:    s_lshl_b32 s5, s5, 1617576; VI-NEXT:    s_or_b32 s4, s4, s517577; VI-NEXT:    s_and_b32 s5, s20, 0xff17578; VI-NEXT:    s_lshl_b32 s6, s21, 817579; VI-NEXT:    s_or_b32 s5, s5, s617580; VI-NEXT:    s_and_b32 s6, s22, 0xff17581; VI-NEXT:    s_lshl_b32 s7, s23, 817582; VI-NEXT:    s_or_b32 s6, s6, s717583; VI-NEXT:    s_and_b32 s5, s5, 0xffff17584; VI-NEXT:    s_lshl_b32 s6, s6, 1617585; VI-NEXT:    s_or_b32 s5, s5, s617586; VI-NEXT:    s_cbranch_execnz .LBB111_317587; VI-NEXT:  .LBB111_2: ; %cmp.true17588; VI-NEXT:    s_add_i32 s16, s16, 317589; VI-NEXT:    s_and_b32 s4, s16, 0xff17590; VI-NEXT:    s_lshl_b32 s5, s17, 817591; VI-NEXT:    s_add_i32 s18, s18, 317592; VI-NEXT:    s_or_b32 s4, s5, s417593; VI-NEXT:    s_and_b32 s5, s18, 0xff17594; VI-NEXT:    s_lshl_b32 s6, s19, 817595; VI-NEXT:    s_addk_i32 s4, 0x30017596; VI-NEXT:    s_or_b32 s5, s6, s517597; VI-NEXT:    s_and_b32 s4, s4, 0xffff17598; VI-NEXT:    s_lshl_b32 s5, s5, 1617599; VI-NEXT:    s_add_i32 s20, s20, 317600; VI-NEXT:    s_or_b32 s4, s5, s417601; VI-NEXT:    s_and_b32 s5, s20, 0xff17602; VI-NEXT:    s_lshl_b32 s6, s21, 817603; VI-NEXT:    s_add_i32 s22, s22, 317604; VI-NEXT:    s_or_b32 s5, s6, s517605; VI-NEXT:    s_and_b32 s6, s22, 0xff17606; VI-NEXT:    s_lshl_b32 s7, s23, 817607; VI-NEXT:    s_addk_i32 s5, 0x30017608; VI-NEXT:    s_or_b32 s6, s7, s617609; VI-NEXT:    s_and_b32 s5, s5, 0xffff17610; VI-NEXT:    s_lshl_b32 s6, s6, 1617611; VI-NEXT:    s_or_b32 s5, s6, s517612; VI-NEXT:    s_add_i32 s4, s4, 0x300000017613; VI-NEXT:    s_add_i32 s5, s5, 0x300000017614; VI-NEXT:  .LBB111_3: ; %end17615; VI-NEXT:    v_mov_b32_e32 v0, s417616; VI-NEXT:    v_mov_b32_e32 v1, s517617; VI-NEXT:    s_setpc_b64 s[30:31]17618; VI-NEXT:  .LBB111_4:17619; VI-NEXT:    ; implicit-def: $sgpr4_sgpr517620; VI-NEXT:    s_branch .LBB111_217621;17622; GFX9-LABEL: bitcast_v8i8_to_v4bf16_scalar:17623; GFX9:       ; %bb.0:17624; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)17625; GFX9-NEXT:    s_cmp_lg_u32 s24, 017626; GFX9-NEXT:    s_cbranch_scc0 .LBB111_417627; GFX9-NEXT:  ; %bb.1: ; %cmp.false17628; GFX9-NEXT:    s_and_b32 s4, s16, 0xff17629; GFX9-NEXT:    s_lshl_b32 s5, s17, 817630; GFX9-NEXT:    s_or_b32 s4, s4, s517631; GFX9-NEXT:    s_and_b32 s5, s18, 0xff17632; GFX9-NEXT:    s_lshl_b32 s6, s19, 817633; GFX9-NEXT:    s_or_b32 s5, s5, s617634; GFX9-NEXT:    s_and_b32 s4, s4, 0xffff17635; GFX9-NEXT:    s_lshl_b32 s5, s5, 1617636; GFX9-NEXT:    s_or_b32 s4, s4, s517637; GFX9-NEXT:    s_and_b32 s5, s20, 0xff17638; GFX9-NEXT:    s_lshl_b32 s6, s21, 817639; GFX9-NEXT:    s_or_b32 s5, s5, s617640; GFX9-NEXT:    s_and_b32 s6, s22, 0xff17641; GFX9-NEXT:    s_lshl_b32 s7, s23, 817642; GFX9-NEXT:    s_or_b32 s6, s6, s717643; GFX9-NEXT:    s_and_b32 s5, s5, 0xffff17644; GFX9-NEXT:    s_lshl_b32 s6, s6, 1617645; GFX9-NEXT:    s_or_b32 s5, s5, s617646; GFX9-NEXT:    s_cbranch_execnz .LBB111_317647; GFX9-NEXT:  .LBB111_2: ; %cmp.true17648; GFX9-NEXT:    s_add_i32 s16, s16, 317649; GFX9-NEXT:    s_and_b32 s4, s16, 0xff17650; GFX9-NEXT:    s_lshl_b32 s5, s17, 817651; GFX9-NEXT:    s_add_i32 s18, s18, 317652; GFX9-NEXT:    s_or_b32 s4, s5, s417653; GFX9-NEXT:    s_and_b32 s5, s18, 0xff17654; GFX9-NEXT:    s_lshl_b32 s6, s19, 817655; GFX9-NEXT:    s_or_b32 s5, s6, s517656; GFX9-NEXT:    s_addk_i32 s4, 0x30017657; GFX9-NEXT:    s_addk_i32 s5, 0x30017658; GFX9-NEXT:    s_and_b32 s4, s4, 0xffff17659; GFX9-NEXT:    s_lshl_b32 s5, s5, 1617660; GFX9-NEXT:    s_add_i32 s20, s20, 317661; GFX9-NEXT:    s_or_b32 s4, s4, s517662; GFX9-NEXT:    s_and_b32 s5, s20, 0xff17663; GFX9-NEXT:    s_lshl_b32 s6, s21, 817664; GFX9-NEXT:    s_add_i32 s22, s22, 317665; GFX9-NEXT:    s_or_b32 s5, s6, s517666; GFX9-NEXT:    s_and_b32 s6, s22, 0xff17667; GFX9-NEXT:    s_lshl_b32 s7, s23, 817668; GFX9-NEXT:    s_or_b32 s6, s7, s617669; GFX9-NEXT:    s_addk_i32 s5, 0x30017670; GFX9-NEXT:    s_addk_i32 s6, 0x30017671; GFX9-NEXT:    s_and_b32 s5, s5, 0xffff17672; GFX9-NEXT:    s_lshl_b32 s6, s6, 1617673; GFX9-NEXT:    s_or_b32 s5, s5, s617674; GFX9-NEXT:  .LBB111_3: ; %end17675; GFX9-NEXT:    v_mov_b32_e32 v0, s417676; GFX9-NEXT:    v_mov_b32_e32 v1, s517677; GFX9-NEXT:    s_setpc_b64 s[30:31]17678; GFX9-NEXT:  .LBB111_4:17679; GFX9-NEXT:    ; implicit-def: $sgpr4_sgpr517680; GFX9-NEXT:    s_branch .LBB111_217681;17682; GFX11-LABEL: bitcast_v8i8_to_v4bf16_scalar:17683; GFX11:       ; %bb.0:17684; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)17685; GFX11-NEXT:    s_cmp_lg_u32 s20, 017686; GFX11-NEXT:    s_mov_b32 s6, 017687; GFX11-NEXT:    s_cbranch_scc0 .LBB111_417688; GFX11-NEXT:  ; %bb.1: ; %cmp.false17689; GFX11-NEXT:    s_and_b32 s4, s0, 0xff17690; GFX11-NEXT:    s_lshl_b32 s5, s1, 817691; GFX11-NEXT:    s_and_b32 s7, s2, 0xff17692; GFX11-NEXT:    s_lshl_b32 s8, s3, 817693; GFX11-NEXT:    s_or_b32 s4, s4, s517694; GFX11-NEXT:    s_or_b32 s5, s7, s817695; GFX11-NEXT:    s_and_b32 s7, s16, 0xff17696; GFX11-NEXT:    s_lshl_b32 s8, s17, 817697; GFX11-NEXT:    s_and_b32 s9, s18, 0xff17698; GFX11-NEXT:    s_lshl_b32 s10, s19, 817699; GFX11-NEXT:    s_or_b32 s7, s7, s817700; GFX11-NEXT:    s_or_b32 s8, s9, s1017701; GFX11-NEXT:    s_and_b32 s4, s4, 0xffff17702; GFX11-NEXT:    s_lshl_b32 s5, s5, 1617703; GFX11-NEXT:    s_and_b32 s7, s7, 0xffff17704; GFX11-NEXT:    s_lshl_b32 s8, s8, 1617705; GFX11-NEXT:    s_or_b32 s4, s4, s517706; GFX11-NEXT:    s_or_b32 s5, s7, s817707; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s617708; GFX11-NEXT:    s_cbranch_vccnz .LBB111_317709; GFX11-NEXT:  .LBB111_2: ; %cmp.true17710; GFX11-NEXT:    s_add_i32 s0, s0, 317711; GFX11-NEXT:    s_lshl_b32 s1, s1, 817712; GFX11-NEXT:    s_and_b32 s0, s0, 0xff17713; GFX11-NEXT:    s_add_i32 s2, s2, 317714; GFX11-NEXT:    s_or_b32 s0, s1, s017715; GFX11-NEXT:    s_and_b32 s1, s2, 0xff17716; GFX11-NEXT:    s_lshl_b32 s2, s3, 817717; GFX11-NEXT:    s_add_i32 s16, s16, 317718; GFX11-NEXT:    s_add_i32 s18, s18, 317719; GFX11-NEXT:    s_or_b32 s1, s2, s117720; GFX11-NEXT:    s_and_b32 s2, s16, 0xff17721; GFX11-NEXT:    s_lshl_b32 s3, s17, 817722; GFX11-NEXT:    s_and_b32 s4, s18, 0xff17723; GFX11-NEXT:    s_lshl_b32 s5, s19, 817724; GFX11-NEXT:    s_or_b32 s2, s3, s217725; GFX11-NEXT:    s_or_b32 s3, s5, s417726; GFX11-NEXT:    s_addk_i32 s0, 0x30017727; GFX11-NEXT:    s_addk_i32 s1, 0x30017728; GFX11-NEXT:    s_addk_i32 s2, 0x30017729; GFX11-NEXT:    s_addk_i32 s3, 0x30017730; GFX11-NEXT:    s_and_b32 s0, s0, 0xffff17731; GFX11-NEXT:    s_lshl_b32 s1, s1, 1617732; GFX11-NEXT:    s_and_b32 s2, s2, 0xffff17733; GFX11-NEXT:    s_lshl_b32 s3, s3, 1617734; GFX11-NEXT:    s_or_b32 s4, s0, s117735; GFX11-NEXT:    s_or_b32 s5, s2, s317736; GFX11-NEXT:  .LBB111_3: ; %end17737; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)17738; GFX11-NEXT:    v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s517739; GFX11-NEXT:    s_setpc_b64 s[30:31]17740; GFX11-NEXT:  .LBB111_4:17741; GFX11-NEXT:    ; implicit-def: $sgpr4_sgpr517742; GFX11-NEXT:    s_branch .LBB111_217743  %cmp = icmp eq i32 %b, 017744  br i1 %cmp, label %cmp.true, label %cmp.false17745 17746cmp.true:17747  %a1 = add <8 x i8> %a, splat (i8 3)17748  %a2 = bitcast <8 x i8> %a1 to <4 x bfloat>17749  br label %end17750 17751cmp.false:17752  %a3 = bitcast <8 x i8> %a to <4 x bfloat>17753  br label %end17754 17755end:17756  %phi = phi <4 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ]17757  ret <4 x bfloat> %phi17758}17759