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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -amdgpu-codegenprepare %s | FileCheck -check-prefix=IR %s3; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefix=GCN %s4 5define i32 @select_sdiv_lhs_const_i32(i1 %cond) {6; IR-LABEL: @select_sdiv_lhs_const_i32(7; IR-NEXT: [[OP:%.*]] = select i1 [[COND:%.*]], i32 200000, i32 1250008; IR-NEXT: ret i32 [[OP]]9;10; GCN-LABEL: select_sdiv_lhs_const_i32:11; GCN: ; %bb.0:12; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)13; GCN-NEXT: v_and_b32_e32 v0, 1, v014; GCN-NEXT: v_mov_b32_e32 v1, 0x1e84815; GCN-NEXT: v_mov_b32_e32 v2, 0x30d4016; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v017; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc18; GCN-NEXT: s_setpc_b64 s[30:31]19 %select = select i1 %cond, i32 5, i32 820 %op = sdiv i32 1000000, %select21 ret i32 %op22}23 24define i32 @select_sdiv_rhs_const_i32(i1 %cond) {25; IR-LABEL: @select_sdiv_rhs_const_i32(26; IR-NEXT: [[OP:%.*]] = select i1 [[COND:%.*]], i32 1000, i32 1000027; IR-NEXT: ret i32 [[OP]]28;29; GCN-LABEL: select_sdiv_rhs_const_i32:30; GCN: ; %bb.0:31; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)32; GCN-NEXT: v_and_b32_e32 v0, 1, v033; GCN-NEXT: v_mov_b32_e32 v1, 0x271034; GCN-NEXT: v_mov_b32_e32 v2, 0x3e835; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v036; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc37; GCN-NEXT: s_setpc_b64 s[30:31]38 %select = select i1 %cond, i32 42000, i32 42000039 %op = sdiv i32 %select, 4240 ret i32 %op41}42 43define <2 x i32> @select_sdiv_lhs_const_v2i32(i1 %cond) {44; IR-LABEL: @select_sdiv_lhs_const_v2i32(45; IR-NEXT: [[OP:%.*]] = select i1 [[COND:%.*]], <2 x i32> <i32 666, i32 poison>, <2 x i32> <i32 555, i32 1428>46; IR-NEXT: ret <2 x i32> [[OP]]47;48; GCN-LABEL: select_sdiv_lhs_const_v2i32:49; GCN: ; %bb.0:50; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)51; GCN-NEXT: v_and_b32_e32 v0, 1, v052; GCN-NEXT: v_mov_b32_e32 v1, 0x22b53; GCN-NEXT: v_mov_b32_e32 v2, 0x29a54; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v055; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc56; GCN-NEXT: v_mov_b32_e32 v1, 0x59457; GCN-NEXT: s_setpc_b64 s[30:31]58 %select = select i1 %cond, <2 x i32> <i32 5, i32 poison>, <2 x i32> <i32 6, i32 7>59 %op = sdiv <2 x i32> <i32 3333, i32 9999>, %select60 ret <2 x i32> %op61}62 63define <2 x i32> @select_sdiv_rhs_const_v2i32(i1 %cond) {64; IR-LABEL: @select_sdiv_rhs_const_v2i32(65; IR-NEXT: [[OP:%.*]] = select i1 [[COND:%.*]], <2 x i32> <i32 198621, i32 20855308>, <2 x i32> <i32 222748, i32 2338858>66; IR-NEXT: ret <2 x i32> [[OP]]67;68; GCN-LABEL: select_sdiv_rhs_const_v2i32:69; GCN: ; %bb.0:70; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)71; GCN-NEXT: v_and_b32_e32 v0, 1, v072; GCN-NEXT: v_mov_b32_e32 v1, 0x3661c73; GCN-NEXT: v_mov_b32_e32 v2, 0x307dd74; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v075; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc76; GCN-NEXT: v_mov_b32_e32 v1, 0x23b02a77; GCN-NEXT: v_mov_b32_e32 v2, 0x13e3a0c78; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc79; GCN-NEXT: s_setpc_b64 s[30:31]80 %select = select i1 %cond, <2 x i32> <i32 8342123, i32 834212353>, <2 x i32> <i32 9355456, i32 93554321>81 %op = sdiv <2 x i32> %select, <i32 42, i32 40>82 ret <2 x i32> %op83}84 85@gv = external addrspace(1) global i3286 87define i32 @select_sdiv_lhs_opaque_const0_i32(i1 %cond) {88; IR-LABEL: @select_sdiv_lhs_opaque_const0_i32(89; IR-NEXT: [[SELECT:%.*]] = select i1 [[COND:%.*]], i32 ptrtoint (ptr addrspace(1) @gv to i32), i32 590; IR-NEXT: [[TMP1:%.*]] = ashr i32 [[SELECT]], 3191; IR-NEXT: [[TMP2:%.*]] = xor i32 0, [[TMP1]]92; IR-NEXT: [[TMP3:%.*]] = add i32 [[SELECT]], [[TMP1]]93; IR-NEXT: [[TMP4:%.*]] = xor i32 [[TMP3]], [[TMP1]]94; IR-NEXT: [[TMP5:%.*]] = uitofp i32 [[TMP4]] to float95; IR-NEXT: [[TMP6:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP5]])96; IR-NEXT: [[TMP7:%.*]] = fmul fast float [[TMP6]], 0x41EFFFFFC000000097; IR-NEXT: [[TMP8:%.*]] = fptoui float [[TMP7]] to i3298; IR-NEXT: [[TMP9:%.*]] = sub i32 0, [[TMP4]]99; IR-NEXT: [[TMP10:%.*]] = mul i32 [[TMP9]], [[TMP8]]100; IR-NEXT: [[TMP11:%.*]] = zext i32 [[TMP8]] to i64101; IR-NEXT: [[TMP12:%.*]] = zext i32 [[TMP10]] to i64102; IR-NEXT: [[TMP13:%.*]] = mul i64 [[TMP11]], [[TMP12]]103; IR-NEXT: [[TMP14:%.*]] = trunc i64 [[TMP13]] to i32104; IR-NEXT: [[TMP15:%.*]] = lshr i64 [[TMP13]], 32105; IR-NEXT: [[TMP16:%.*]] = trunc i64 [[TMP15]] to i32106; IR-NEXT: [[TMP17:%.*]] = add i32 [[TMP8]], [[TMP16]]107; IR-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64108; IR-NEXT: [[TMP19:%.*]] = mul i64 1000000, [[TMP18]]109; IR-NEXT: [[TMP20:%.*]] = trunc i64 [[TMP19]] to i32110; IR-NEXT: [[TMP21:%.*]] = lshr i64 [[TMP19]], 32111; IR-NEXT: [[TMP22:%.*]] = trunc i64 [[TMP21]] to i32112; IR-NEXT: [[TMP23:%.*]] = mul i32 [[TMP22]], [[TMP4]]113; IR-NEXT: [[TMP24:%.*]] = sub i32 1000000, [[TMP23]]114; IR-NEXT: [[TMP25:%.*]] = icmp uge i32 [[TMP24]], [[TMP4]]115; IR-NEXT: [[TMP26:%.*]] = add i32 [[TMP22]], 1116; IR-NEXT: [[TMP27:%.*]] = select i1 [[TMP25]], i32 [[TMP26]], i32 [[TMP22]]117; IR-NEXT: [[TMP28:%.*]] = sub i32 [[TMP24]], [[TMP4]]118; IR-NEXT: [[TMP29:%.*]] = select i1 [[TMP25]], i32 [[TMP28]], i32 [[TMP24]]119; IR-NEXT: [[TMP30:%.*]] = icmp uge i32 [[TMP29]], [[TMP4]]120; IR-NEXT: [[TMP31:%.*]] = add i32 [[TMP27]], 1121; IR-NEXT: [[TMP32:%.*]] = select i1 [[TMP30]], i32 [[TMP31]], i32 [[TMP27]]122; IR-NEXT: [[TMP33:%.*]] = xor i32 [[TMP32]], [[TMP2]]123; IR-NEXT: [[TMP34:%.*]] = sub i32 [[TMP33]], [[TMP2]]124; IR-NEXT: ret i32 [[TMP34]]125;126; GCN-LABEL: select_sdiv_lhs_opaque_const0_i32:127; GCN: ; %bb.0:128; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)129; GCN-NEXT: s_getpc_b64 s[4:5]130; GCN-NEXT: s_add_u32 s4, s4, gv@gotpcrel32@lo+4131; GCN-NEXT: s_addc_u32 s5, s5, gv@gotpcrel32@hi+12132; GCN-NEXT: s_load_dword s4, s[4:5], 0x0133; GCN-NEXT: v_and_b32_e32 v0, 1, v0134; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0135; GCN-NEXT: s_waitcnt lgkmcnt(0)136; GCN-NEXT: v_mov_b32_e32 v1, s4137; GCN-NEXT: v_cndmask_b32_e32 v0, 5, v1, vcc138; GCN-NEXT: v_sub_u32_e32 v1, vcc, 0, v0139; GCN-NEXT: v_max_i32_e32 v1, v1, v0140; GCN-NEXT: v_cvt_f32_u32_e32 v2, v1141; GCN-NEXT: v_sub_u32_e32 v3, vcc, 0, v1142; GCN-NEXT: s_mov_b32 s4, 0xf4240143; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v2144; GCN-NEXT: v_ashrrev_i32_e32 v0, 31, v0145; GCN-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2146; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2147; GCN-NEXT: v_mul_lo_u32 v3, v3, v2148; GCN-NEXT: v_mul_hi_u32 v3, v2, v3149; GCN-NEXT: v_add_u32_e32 v2, vcc, v2, v3150; GCN-NEXT: v_mul_hi_u32 v2, v2, s4151; GCN-NEXT: v_mul_lo_u32 v3, v2, v1152; GCN-NEXT: v_add_u32_e32 v4, vcc, 1, v2153; GCN-NEXT: v_sub_u32_e32 v3, vcc, 0xf4240, v3154; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v3, v1155; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc156; GCN-NEXT: v_sub_u32_e64 v4, s[4:5], v3, v1157; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc158; GCN-NEXT: v_add_u32_e32 v4, vcc, 1, v2159; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v3, v1160; GCN-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc161; GCN-NEXT: v_xor_b32_e32 v1, v1, v0162; GCN-NEXT: v_sub_u32_e32 v0, vcc, v1, v0163; GCN-NEXT: s_setpc_b64 s[30:31]164 %select = select i1 %cond, i32 ptrtoint (ptr addrspace(1) @gv to i32), i32 5165 %op = sdiv i32 1000000, %select166 ret i32 %op167}168 169define i32 @select_sdiv_lhs_opaque_const1_i32(i1 %cond) {170; IR-LABEL: @select_sdiv_lhs_opaque_const1_i32(171; IR-NEXT: [[SELECT:%.*]] = select i1 [[COND:%.*]], i32 5, i32 ptrtoint (ptr addrspace(1) @gv to i32)172; IR-NEXT: [[TMP1:%.*]] = ashr i32 [[SELECT]], 31173; IR-NEXT: [[TMP2:%.*]] = xor i32 0, [[TMP1]]174; IR-NEXT: [[TMP3:%.*]] = add i32 [[SELECT]], [[TMP1]]175; IR-NEXT: [[TMP4:%.*]] = xor i32 [[TMP3]], [[TMP1]]176; IR-NEXT: [[TMP5:%.*]] = uitofp i32 [[TMP4]] to float177; IR-NEXT: [[TMP6:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP5]])178; IR-NEXT: [[TMP7:%.*]] = fmul fast float [[TMP6]], 0x41EFFFFFC0000000179; IR-NEXT: [[TMP8:%.*]] = fptoui float [[TMP7]] to i32180; IR-NEXT: [[TMP9:%.*]] = sub i32 0, [[TMP4]]181; IR-NEXT: [[TMP10:%.*]] = mul i32 [[TMP9]], [[TMP8]]182; IR-NEXT: [[TMP11:%.*]] = zext i32 [[TMP8]] to i64183; IR-NEXT: [[TMP12:%.*]] = zext i32 [[TMP10]] to i64184; IR-NEXT: [[TMP13:%.*]] = mul i64 [[TMP11]], [[TMP12]]185; IR-NEXT: [[TMP14:%.*]] = trunc i64 [[TMP13]] to i32186; IR-NEXT: [[TMP15:%.*]] = lshr i64 [[TMP13]], 32187; IR-NEXT: [[TMP16:%.*]] = trunc i64 [[TMP15]] to i32188; IR-NEXT: [[TMP17:%.*]] = add i32 [[TMP8]], [[TMP16]]189; IR-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64190; IR-NEXT: [[TMP19:%.*]] = mul i64 1000000, [[TMP18]]191; IR-NEXT: [[TMP20:%.*]] = trunc i64 [[TMP19]] to i32192; IR-NEXT: [[TMP21:%.*]] = lshr i64 [[TMP19]], 32193; IR-NEXT: [[TMP22:%.*]] = trunc i64 [[TMP21]] to i32194; IR-NEXT: [[TMP23:%.*]] = mul i32 [[TMP22]], [[TMP4]]195; IR-NEXT: [[TMP24:%.*]] = sub i32 1000000, [[TMP23]]196; IR-NEXT: [[TMP25:%.*]] = icmp uge i32 [[TMP24]], [[TMP4]]197; IR-NEXT: [[TMP26:%.*]] = add i32 [[TMP22]], 1198; IR-NEXT: [[TMP27:%.*]] = select i1 [[TMP25]], i32 [[TMP26]], i32 [[TMP22]]199; IR-NEXT: [[TMP28:%.*]] = sub i32 [[TMP24]], [[TMP4]]200; IR-NEXT: [[TMP29:%.*]] = select i1 [[TMP25]], i32 [[TMP28]], i32 [[TMP24]]201; IR-NEXT: [[TMP30:%.*]] = icmp uge i32 [[TMP29]], [[TMP4]]202; IR-NEXT: [[TMP31:%.*]] = add i32 [[TMP27]], 1203; IR-NEXT: [[TMP32:%.*]] = select i1 [[TMP30]], i32 [[TMP31]], i32 [[TMP27]]204; IR-NEXT: [[TMP33:%.*]] = xor i32 [[TMP32]], [[TMP2]]205; IR-NEXT: [[TMP34:%.*]] = sub i32 [[TMP33]], [[TMP2]]206; IR-NEXT: ret i32 [[TMP34]]207;208; GCN-LABEL: select_sdiv_lhs_opaque_const1_i32:209; GCN: ; %bb.0:210; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)211; GCN-NEXT: s_getpc_b64 s[4:5]212; GCN-NEXT: s_add_u32 s4, s4, gv@gotpcrel32@lo+4213; GCN-NEXT: s_addc_u32 s5, s5, gv@gotpcrel32@hi+12214; GCN-NEXT: s_load_dword s4, s[4:5], 0x0215; GCN-NEXT: v_and_b32_e32 v0, 1, v0216; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0217; GCN-NEXT: s_waitcnt lgkmcnt(0)218; GCN-NEXT: v_mov_b32_e32 v1, s4219; GCN-NEXT: v_cndmask_b32_e64 v0, v1, 5, vcc220; GCN-NEXT: v_sub_u32_e32 v1, vcc, 0, v0221; GCN-NEXT: v_max_i32_e32 v1, v1, v0222; GCN-NEXT: v_cvt_f32_u32_e32 v2, v1223; GCN-NEXT: v_sub_u32_e32 v3, vcc, 0, v1224; GCN-NEXT: s_mov_b32 s4, 0xf4240225; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v2226; GCN-NEXT: v_ashrrev_i32_e32 v0, 31, v0227; GCN-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2228; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2229; GCN-NEXT: v_mul_lo_u32 v3, v3, v2230; GCN-NEXT: v_mul_hi_u32 v3, v2, v3231; GCN-NEXT: v_add_u32_e32 v2, vcc, v2, v3232; GCN-NEXT: v_mul_hi_u32 v2, v2, s4233; GCN-NEXT: v_mul_lo_u32 v3, v2, v1234; GCN-NEXT: v_add_u32_e32 v4, vcc, 1, v2235; GCN-NEXT: v_sub_u32_e32 v3, vcc, 0xf4240, v3236; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v3, v1237; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc238; GCN-NEXT: v_sub_u32_e64 v4, s[4:5], v3, v1239; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc240; GCN-NEXT: v_add_u32_e32 v4, vcc, 1, v2241; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v3, v1242; GCN-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc243; GCN-NEXT: v_xor_b32_e32 v1, v1, v0244; GCN-NEXT: v_sub_u32_e32 v0, vcc, v1, v0245; GCN-NEXT: s_setpc_b64 s[30:31]246 %select = select i1 %cond, i32 5, i32 ptrtoint (ptr addrspace(1) @gv to i32)247 %op = sdiv i32 1000000, %select248 ret i32 %op249}250 251define i32 @select_sdiv_rhs_opaque_const0_i32(i1 %cond) {252; IR-LABEL: @select_sdiv_rhs_opaque_const0_i32(253; IR-NEXT: [[SELECT:%.*]] = select i1 [[COND:%.*]], i32 ptrtoint (ptr addrspace(1) @gv to i32), i32 234234254; IR-NEXT: [[OP:%.*]] = sdiv i32 [[SELECT]], 42255; IR-NEXT: ret i32 [[OP]]256;257; GCN-LABEL: select_sdiv_rhs_opaque_const0_i32:258; GCN: ; %bb.0:259; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)260; GCN-NEXT: s_getpc_b64 s[4:5]261; GCN-NEXT: s_add_u32 s4, s4, gv@gotpcrel32@lo+4262; GCN-NEXT: s_addc_u32 s5, s5, gv@gotpcrel32@hi+12263; GCN-NEXT: s_load_dword s4, s[4:5], 0x0264; GCN-NEXT: v_and_b32_e32 v0, 1, v0265; GCN-NEXT: v_mov_b32_e32 v1, 0x392fa266; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0267; GCN-NEXT: s_waitcnt lgkmcnt(0)268; GCN-NEXT: v_mov_b32_e32 v2, s4269; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc270; GCN-NEXT: s_mov_b32 s4, 0x30c30c31271; GCN-NEXT: v_mul_hi_i32 v0, v0, s4272; GCN-NEXT: v_lshrrev_b32_e32 v1, 31, v0273; GCN-NEXT: v_ashrrev_i32_e32 v0, 3, v0274; GCN-NEXT: v_add_u32_e32 v0, vcc, v0, v1275; GCN-NEXT: s_setpc_b64 s[30:31]276 %select = select i1 %cond, i32 ptrtoint (ptr addrspace(1) @gv to i32), i32 234234277 %op = sdiv i32 %select, 42278 ret i32 %op279}280 281define i32 @select_sdiv_rhs_opaque_const1_i32(i1 %cond) {282; IR-LABEL: @select_sdiv_rhs_opaque_const1_i32(283; IR-NEXT: [[SELECT:%.*]] = select i1 [[COND:%.*]], i32 42000, i32 ptrtoint (ptr addrspace(1) @gv to i32)284; IR-NEXT: [[OP:%.*]] = sdiv i32 [[SELECT]], 42285; IR-NEXT: ret i32 [[OP]]286;287; GCN-LABEL: select_sdiv_rhs_opaque_const1_i32:288; GCN: ; %bb.0:289; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)290; GCN-NEXT: s_getpc_b64 s[4:5]291; GCN-NEXT: s_add_u32 s4, s4, gv@gotpcrel32@lo+4292; GCN-NEXT: s_addc_u32 s5, s5, gv@gotpcrel32@hi+12293; GCN-NEXT: s_load_dword s4, s[4:5], 0x0294; GCN-NEXT: v_and_b32_e32 v0, 1, v0295; GCN-NEXT: v_mov_b32_e32 v1, 0xa410296; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0297; GCN-NEXT: s_waitcnt lgkmcnt(0)298; GCN-NEXT: v_mov_b32_e32 v2, s4299; GCN-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc300; GCN-NEXT: s_mov_b32 s4, 0x30c30c31301; GCN-NEXT: v_mul_hi_i32 v0, v0, s4302; GCN-NEXT: v_lshrrev_b32_e32 v1, 31, v0303; GCN-NEXT: v_ashrrev_i32_e32 v0, 3, v0304; GCN-NEXT: v_add_u32_e32 v0, vcc, v0, v1305; GCN-NEXT: s_setpc_b64 s[30:31]306 %select = select i1 %cond, i32 42000, i32 ptrtoint (ptr addrspace(1) @gv to i32)307 %op = sdiv i32 %select, 42308 ret i32 %op309}310 311define i32 @select_add_lhs_const_i32(i1 %cond) {312; IR-LABEL: @select_add_lhs_const_i32(313; IR-NEXT: [[OP:%.*]] = select i1 [[COND:%.*]], i32 1000005, i32 1000008314; IR-NEXT: ret i32 [[OP]]315;316; GCN-LABEL: select_add_lhs_const_i32:317; GCN: ; %bb.0:318; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)319; GCN-NEXT: v_and_b32_e32 v0, 1, v0320; GCN-NEXT: v_mov_b32_e32 v1, 0xf4248321; GCN-NEXT: v_mov_b32_e32 v2, 0xf4245322; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0323; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc324; GCN-NEXT: s_setpc_b64 s[30:31]325 %select = select i1 %cond, i32 5, i32 8326 %op = add i32 1000000, %select327 ret i32 %op328}329 330define float @select_fadd_lhs_const_i32_fmf(i1 %cond) {331; IR-LABEL: @select_fadd_lhs_const_i32_fmf(332; IR-NEXT: [[OP:%.*]] = select nnan nsz i1 [[COND:%.*]], float 3.000000e+00, float 5.000000e+00333; IR-NEXT: ret float [[OP]]334;335; GCN-LABEL: select_fadd_lhs_const_i32_fmf:336; GCN: ; %bb.0:337; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)338; GCN-NEXT: v_and_b32_e32 v0, 1, v0339; GCN-NEXT: v_mov_b32_e32 v1, 0x40a00000340; GCN-NEXT: v_mov_b32_e32 v2, 0x40400000341; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0342; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc343; GCN-NEXT: s_setpc_b64 s[30:31]344 %select = select i1 %cond, float 2.0, float 4.0345 %op = fadd nnan nsz float 1.0, %select346 ret float %op347}348 349; Make sure we don't try to use mul24 instead350define i32 @select_mul_lhs_const_i32(i1 %cond) {351; GCN-LABEL: select_mul_lhs_const_i32:352; GCN: ; %bb.0:353; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)354; GCN-NEXT: v_and_b32_e32 v0, 1, v0355; GCN-NEXT: v_mov_b32_e32 v1, 0x1f40356; GCN-NEXT: v_mov_b32_e32 v2, 0x1388357; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0358; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc359; GCN-NEXT: s_setpc_b64 s[30:31]360; IR-LABEL: @select_mul_lhs_const_i32(361; IR-NEXT: [[OP:%.*]] = select i1 [[COND:%.*]], i32 5000, i32 8000362; IR-NEXT: ret i32 [[OP]]363 %select = select i1 %cond, i32 5, i32 8364 %op = mul i32 1000, %select365 ret i32 %op366}367 368; Make sure we don't try to use mul24 instead369define i32 @select_mul_rhs_const_i32(i1 %cond) {370; GCN-LABEL: select_mul_rhs_const_i32:371; GCN: ; %bb.0:372; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)373; GCN-NEXT: v_and_b32_e32 v0, 1, v0374; GCN-NEXT: v_mov_b32_e32 v1, 0x1f40375; GCN-NEXT: v_mov_b32_e32 v2, 0x1388376; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0377; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc378; GCN-NEXT: s_setpc_b64 s[30:31]379; IR-LABEL: @select_mul_rhs_const_i32(380; IR-NEXT: [[OP:%.*]] = select i1 [[COND:%.*]], i32 5000, i32 8000381; IR-NEXT: ret i32 [[OP]]382 %select = select i1 %cond, i32 5, i32 8383 %op = mul i32 %select, 1000384 ret i32 %op385}386 387define amdgpu_kernel void @select_add_lhs_const_i16(i1 %cond) {388; IR-LABEL: @select_add_lhs_const_i16(389; IR-NEXT: [[OP:%.*]] = select i1 [[COND:%.*]], i16 128, i16 131390; IR-NEXT: store i16 [[OP]], ptr addrspace(1) poison, align 2391; IR-NEXT: ret void392;393; GCN-LABEL: select_add_lhs_const_i16:394; GCN: ; %bb.0:395; GCN-NEXT: s_load_dword s0, s[8:9], 0x0396; GCN-NEXT: s_add_i32 s12, s12, s17397; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8398; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13399; GCN-NEXT: s_waitcnt lgkmcnt(0)400; GCN-NEXT: s_bitcmp1_b32 s0, 0401; GCN-NEXT: s_movk_i32 s0, 0x80402; GCN-NEXT: s_cselect_b32 s0, s0, 0x83403; GCN-NEXT: v_mov_b32_e32 v0, s0404; GCN-NEXT: flat_store_short v[0:1], v0405; GCN-NEXT: s_endpgm406 %select = select i1 %cond, i16 5, i16 8407 %op = add i16 %select, 123408 store i16 %op, ptr addrspace(1) poison409 ret void410}411 412define i16 @select_add_trunc_select(i1 %cond) {413; GCN-LABEL: select_add_trunc_select:414; GCN: ; %bb.0:415; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)416; GCN-NEXT: v_and_b32_e32 v0, 1, v0417; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0418; GCN-NEXT: v_cndmask_b32_e64 v0, 50, 47, vcc419; GCN-NEXT: s_setpc_b64 s[30:31]420; IR-LABEL: @select_add_trunc_select(421; IR-NEXT: [[OP:%.*]] = select i1 [[COND:%.*]], i16 47, i16 50422; IR-NEXT: ret i16 [[OP]]423 %select = select i1 %cond, i32 5, i32 8424 %trunc = trunc i32 %select to i16425 %op = add i16 %trunc, 42426 ret i16 %op427}428 429define i32 @select_add_sext_select(i1 %cond) {430; IR-LABEL: @select_add_sext_select(431; IR-NEXT: [[OP:%.*]] = select i1 [[COND:%.*]], i32 29, i32 50432; IR-NEXT: ret i32 [[OP]]433;434; GCN-LABEL: select_add_sext_select:435; GCN: ; %bb.0:436; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)437; GCN-NEXT: v_and_b32_e32 v0, 1, v0438; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0439; GCN-NEXT: v_cndmask_b32_e64 v0, 50, 29, vcc440; GCN-NEXT: s_setpc_b64 s[30:31]441 %select = select i1 %cond, i16 -13, i16 8442 %trunc = sext i16 %select to i32443 %op = add i32 %trunc, 42444 ret i32 %op445}446 447define i32 @select_add_zext_select(i1 %cond) {448; IR-LABEL: @select_add_zext_select(449; IR-NEXT: [[OP:%.*]] = select i1 [[COND:%.*]], i32 47, i32 50450; IR-NEXT: ret i32 [[OP]]451;452; GCN-LABEL: select_add_zext_select:453; GCN: ; %bb.0:454; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)455; GCN-NEXT: v_and_b32_e32 v0, 1, v0456; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0457; GCN-NEXT: v_cndmask_b32_e64 v0, 50, 47, vcc458; GCN-NEXT: s_setpc_b64 s[30:31]459 %select = select i1 %cond, i16 5, i16 8460 %trunc = zext i16 %select to i32461 %op = add i32 %trunc, 42462 ret i32 %op463}464 465define i32 @select_add_bitcast_select(i1 %cond) {466; IR-LABEL: @select_add_bitcast_select(467; IR-NEXT: [[OP:%.*]] = select i1 [[COND:%.*]], i32 1065353258, i32 1073741866468; IR-NEXT: ret i32 [[OP]]469;470; GCN-LABEL: select_add_bitcast_select:471; GCN: ; %bb.0:472; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)473; GCN-NEXT: v_and_b32_e32 v0, 1, v0474; GCN-NEXT: v_mov_b32_e32 v1, 0x4000002a475; GCN-NEXT: v_mov_b32_e32 v2, 0x3f80002a476; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0477; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc478; GCN-NEXT: s_setpc_b64 s[30:31]479 %select = select i1 %cond, float 1.0, float 2.0480 %trunc = bitcast float %select to i32481 %op = add i32 %trunc, 42482 ret i32 %op483}484 485; If we fold through a cast, we need to ensure it doesn't have486; multiple uses.487define <2 x half> @multi_use_cast_regression(i1 %cond) {488; IR-LABEL: @multi_use_cast_regression(489; IR-NEXT: [[SELECT:%.*]] = select i1 [[COND:%.*]], half 0xH3C00, half 0xH0000490; IR-NEXT: [[FPEXT:%.*]] = fpext half [[SELECT]] to float491; IR-NEXT: [[FSUB:%.*]] = fsub nsz float 1.000000e+00, [[FPEXT]]492; IR-NEXT: [[CALL:%.*]] = call nsz <2 x half> @llvm.amdgcn.cvt.pkrtz(float [[FPEXT]], float [[FSUB]])493; IR-NEXT: ret <2 x half> [[CALL]]494;495; GCN-LABEL: multi_use_cast_regression:496; GCN: ; %bb.0:497; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)498; GCN-NEXT: v_and_b32_e32 v0, 1, v0499; GCN-NEXT: v_mov_b32_e32 v1, 0x3c00500; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0501; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc502; GCN-NEXT: v_cvt_f32_f16_e32 v0, v0503; GCN-NEXT: v_sub_f32_e32 v1, 1.0, v0504; GCN-NEXT: v_cvt_pkrtz_f16_f32 v0, v0, v1505; GCN-NEXT: s_setpc_b64 s[30:31]506 %select = select i1 %cond, half 1.000000e+00, half 0.000000e+00507 %fpext = fpext half %select to float508 %fsub = fsub nsz float 1.0, %fpext509 %call = call nsz <2 x half> @llvm.amdgcn.cvt.pkrtz(float %fpext, float %fsub) #3510 ret <2 x half> %call511}512 513declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float) #0514 515attributes #0 = { nounwind readnone speculatable }516