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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: opt -S -mtriple=amdgcn-- -mcpu=tahiti -amdgpu-codegenprepare -amdgpu-bypass-slow-div=0 %s | FileCheck %s3; RUN: llc -mtriple=amdgcn-- -mcpu=tahiti -amdgpu-bypass-slow-div=0 < %s | FileCheck -check-prefix=GFX6 %s4; RUN: llc -mtriple=amdgcn-- -mcpu=gfx900 -amdgpu-bypass-slow-div=0 < %s | FileCheck -check-prefix=GFX9 %s5 6define amdgpu_kernel void @udiv_i32(ptr addrspace(1) %out, i32 %x, i32 %y) {7; CHECK-LABEL: @udiv_i32(8; CHECK-NEXT: [[TMP1:%.*]] = uitofp i32 [[Y:%.*]] to float9; CHECK-NEXT: [[TMP2:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP1]])10; CHECK-NEXT: [[TMP3:%.*]] = fmul fast float [[TMP2]], 0x41EFFFFFC000000011; CHECK-NEXT: [[TMP4:%.*]] = fptoui float [[TMP3]] to i3212; CHECK-NEXT: [[TMP5:%.*]] = sub i32 0, [[Y]]13; CHECK-NEXT: [[TMP6:%.*]] = mul i32 [[TMP5]], [[TMP4]]14; CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[TMP4]] to i6415; CHECK-NEXT: [[TMP8:%.*]] = zext i32 [[TMP6]] to i6416; CHECK-NEXT: [[TMP9:%.*]] = mul i64 [[TMP7]], [[TMP8]]17; CHECK-NEXT: [[TMP10:%.*]] = trunc i64 [[TMP9]] to i3218; CHECK-NEXT: [[TMP11:%.*]] = lshr i64 [[TMP9]], 3219; CHECK-NEXT: [[TMP12:%.*]] = trunc i64 [[TMP11]] to i3220; CHECK-NEXT: [[TMP13:%.*]] = add i32 [[TMP4]], [[TMP12]]21; CHECK-NEXT: [[TMP14:%.*]] = zext i32 [[X:%.*]] to i6422; CHECK-NEXT: [[TMP15:%.*]] = zext i32 [[TMP13]] to i6423; CHECK-NEXT: [[TMP16:%.*]] = mul i64 [[TMP14]], [[TMP15]]24; CHECK-NEXT: [[TMP17:%.*]] = trunc i64 [[TMP16]] to i3225; CHECK-NEXT: [[TMP18:%.*]] = lshr i64 [[TMP16]], 3226; CHECK-NEXT: [[TMP19:%.*]] = trunc i64 [[TMP18]] to i3227; CHECK-NEXT: [[TMP20:%.*]] = mul i32 [[TMP19]], [[Y]]28; CHECK-NEXT: [[TMP21:%.*]] = sub i32 [[X]], [[TMP20]]29; CHECK-NEXT: [[TMP22:%.*]] = icmp uge i32 [[TMP21]], [[Y]]30; CHECK-NEXT: [[TMP23:%.*]] = add i32 [[TMP19]], 131; CHECK-NEXT: [[TMP24:%.*]] = select i1 [[TMP22]], i32 [[TMP23]], i32 [[TMP19]]32; CHECK-NEXT: [[TMP25:%.*]] = sub i32 [[TMP21]], [[Y]]33; CHECK-NEXT: [[TMP26:%.*]] = select i1 [[TMP22]], i32 [[TMP25]], i32 [[TMP21]]34; CHECK-NEXT: [[TMP27:%.*]] = icmp uge i32 [[TMP26]], [[Y]]35; CHECK-NEXT: [[TMP28:%.*]] = add i32 [[TMP24]], 136; CHECK-NEXT: [[TMP29:%.*]] = select i1 [[TMP27]], i32 [[TMP28]], i32 [[TMP24]]37; CHECK-NEXT: store i32 [[TMP29]], ptr addrspace(1) [[OUT:%.*]], align 438; CHECK-NEXT: ret void39;40; GFX6-LABEL: udiv_i32:41; GFX6: ; %bb.0:42; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x943; GFX6-NEXT: s_waitcnt lgkmcnt(0)44; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]45; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s546; GFX6-NEXT: s_sub_i32 s2, 0, s547; GFX6-NEXT: s_mov_b32 s3, 0xf00048; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v049; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v050; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v051; GFX6-NEXT: v_mul_lo_u32 v1, s2, v052; GFX6-NEXT: s_mov_b32 s2, -153; GFX6-NEXT: v_mul_hi_u32 v1, v0, v154; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v155; GFX6-NEXT: v_mul_hi_u32 v0, s4, v056; GFX6-NEXT: v_readfirstlane_b32 s6, v057; GFX6-NEXT: s_mul_i32 s6, s6, s558; GFX6-NEXT: s_sub_i32 s4, s4, s659; GFX6-NEXT: s_sub_i32 s6, s4, s560; GFX6-NEXT: v_add_i32_e32 v1, vcc, 1, v061; GFX6-NEXT: s_cmp_ge_u32 s4, s562; GFX6-NEXT: s_cselect_b64 vcc, -1, 063; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc64; GFX6-NEXT: s_cselect_b32 s4, s6, s465; GFX6-NEXT: v_add_i32_e32 v1, vcc, 1, v066; GFX6-NEXT: s_cmp_ge_u32 s4, s567; GFX6-NEXT: s_cselect_b64 vcc, -1, 068; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc69; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 070; GFX6-NEXT: s_endpgm71;72; GFX9-LABEL: udiv_i32:73; GFX9: ; %bb.0:74; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2475; GFX9-NEXT: v_mov_b32_e32 v1, 076; GFX9-NEXT: s_waitcnt lgkmcnt(0)77; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s378; GFX9-NEXT: s_sub_i32 s4, 0, s379; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v080; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v081; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v082; GFX9-NEXT: v_readfirstlane_b32 s5, v083; GFX9-NEXT: s_mul_i32 s4, s4, s584; GFX9-NEXT: s_mul_hi_u32 s4, s5, s485; GFX9-NEXT: s_add_i32 s5, s5, s486; GFX9-NEXT: s_mul_hi_u32 s4, s2, s587; GFX9-NEXT: s_mul_i32 s5, s4, s388; GFX9-NEXT: s_sub_i32 s2, s2, s589; GFX9-NEXT: s_add_i32 s6, s4, 190; GFX9-NEXT: s_sub_i32 s5, s2, s391; GFX9-NEXT: s_cmp_ge_u32 s2, s392; GFX9-NEXT: s_cselect_b32 s4, s6, s493; GFX9-NEXT: s_cselect_b32 s2, s5, s294; GFX9-NEXT: s_add_i32 s5, s4, 195; GFX9-NEXT: s_cmp_ge_u32 s2, s396; GFX9-NEXT: s_cselect_b32 s2, s5, s497; GFX9-NEXT: v_mov_b32_e32 v0, s298; GFX9-NEXT: global_store_dword v1, v0, s[0:1]99; GFX9-NEXT: s_endpgm100 %r = udiv i32 %x, %y101 store i32 %r, ptr addrspace(1) %out102 ret void103}104 105define amdgpu_kernel void @urem_i32(ptr addrspace(1) %out, i32 %x, i32 %y) {106; CHECK-LABEL: @urem_i32(107; CHECK-NEXT: [[TMP1:%.*]] = uitofp i32 [[Y:%.*]] to float108; CHECK-NEXT: [[TMP2:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP1]])109; CHECK-NEXT: [[TMP3:%.*]] = fmul fast float [[TMP2]], 0x41EFFFFFC0000000110; CHECK-NEXT: [[TMP4:%.*]] = fptoui float [[TMP3]] to i32111; CHECK-NEXT: [[TMP5:%.*]] = sub i32 0, [[Y]]112; CHECK-NEXT: [[TMP6:%.*]] = mul i32 [[TMP5]], [[TMP4]]113; CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[TMP4]] to i64114; CHECK-NEXT: [[TMP8:%.*]] = zext i32 [[TMP6]] to i64115; CHECK-NEXT: [[TMP9:%.*]] = mul i64 [[TMP7]], [[TMP8]]116; CHECK-NEXT: [[TMP10:%.*]] = trunc i64 [[TMP9]] to i32117; CHECK-NEXT: [[TMP11:%.*]] = lshr i64 [[TMP9]], 32118; CHECK-NEXT: [[TMP12:%.*]] = trunc i64 [[TMP11]] to i32119; CHECK-NEXT: [[TMP13:%.*]] = add i32 [[TMP4]], [[TMP12]]120; CHECK-NEXT: [[TMP14:%.*]] = zext i32 [[X:%.*]] to i64121; CHECK-NEXT: [[TMP15:%.*]] = zext i32 [[TMP13]] to i64122; CHECK-NEXT: [[TMP16:%.*]] = mul i64 [[TMP14]], [[TMP15]]123; CHECK-NEXT: [[TMP17:%.*]] = trunc i64 [[TMP16]] to i32124; CHECK-NEXT: [[TMP18:%.*]] = lshr i64 [[TMP16]], 32125; CHECK-NEXT: [[TMP19:%.*]] = trunc i64 [[TMP18]] to i32126; CHECK-NEXT: [[TMP20:%.*]] = mul i32 [[TMP19]], [[Y]]127; CHECK-NEXT: [[TMP21:%.*]] = sub i32 [[X]], [[TMP20]]128; CHECK-NEXT: [[TMP22:%.*]] = icmp uge i32 [[TMP21]], [[Y]]129; CHECK-NEXT: [[TMP23:%.*]] = sub i32 [[TMP21]], [[Y]]130; CHECK-NEXT: [[TMP24:%.*]] = select i1 [[TMP22]], i32 [[TMP23]], i32 [[TMP21]]131; CHECK-NEXT: [[TMP25:%.*]] = icmp uge i32 [[TMP24]], [[Y]]132; CHECK-NEXT: [[TMP26:%.*]] = sub i32 [[TMP24]], [[Y]]133; CHECK-NEXT: [[TMP27:%.*]] = select i1 [[TMP25]], i32 [[TMP26]], i32 [[TMP24]]134; CHECK-NEXT: store i32 [[TMP27]], ptr addrspace(1) [[OUT:%.*]], align 4135; CHECK-NEXT: ret void136;137; GFX6-LABEL: urem_i32:138; GFX6: ; %bb.0:139; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9140; GFX6-NEXT: s_waitcnt lgkmcnt(0)141; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]142; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s5143; GFX6-NEXT: s_sub_i32 s2, 0, s5144; GFX6-NEXT: s_mov_b32 s3, 0xf000145; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0146; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0147; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0148; GFX6-NEXT: v_mul_lo_u32 v1, s2, v0149; GFX6-NEXT: s_mov_b32 s2, -1150; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1151; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1152; GFX6-NEXT: v_mul_hi_u32 v0, s4, v0153; GFX6-NEXT: v_readfirstlane_b32 s6, v0154; GFX6-NEXT: s_mul_i32 s6, s6, s5155; GFX6-NEXT: s_sub_i32 s4, s4, s6156; GFX6-NEXT: s_sub_i32 s6, s4, s5157; GFX6-NEXT: s_cmp_ge_u32 s4, s5158; GFX6-NEXT: s_cselect_b32 s4, s6, s4159; GFX6-NEXT: s_sub_i32 s6, s4, s5160; GFX6-NEXT: s_cmp_ge_u32 s4, s5161; GFX6-NEXT: s_cselect_b32 s4, s6, s4162; GFX6-NEXT: v_mov_b32_e32 v0, s4163; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0164; GFX6-NEXT: s_endpgm165;166; GFX9-LABEL: urem_i32:167; GFX9: ; %bb.0:168; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24169; GFX9-NEXT: v_mov_b32_e32 v1, 0170; GFX9-NEXT: s_waitcnt lgkmcnt(0)171; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s3172; GFX9-NEXT: s_sub_i32 s4, 0, s3173; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0174; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0175; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0176; GFX9-NEXT: v_readfirstlane_b32 s5, v0177; GFX9-NEXT: s_mul_i32 s4, s4, s5178; GFX9-NEXT: s_mul_hi_u32 s4, s5, s4179; GFX9-NEXT: s_add_i32 s5, s5, s4180; GFX9-NEXT: s_mul_hi_u32 s4, s2, s5181; GFX9-NEXT: s_mul_i32 s4, s4, s3182; GFX9-NEXT: s_sub_i32 s2, s2, s4183; GFX9-NEXT: s_sub_i32 s4, s2, s3184; GFX9-NEXT: s_cmp_ge_u32 s2, s3185; GFX9-NEXT: s_cselect_b32 s2, s4, s2186; GFX9-NEXT: s_sub_i32 s4, s2, s3187; GFX9-NEXT: s_cmp_ge_u32 s2, s3188; GFX9-NEXT: s_cselect_b32 s2, s4, s2189; GFX9-NEXT: v_mov_b32_e32 v0, s2190; GFX9-NEXT: global_store_dword v1, v0, s[0:1]191; GFX9-NEXT: s_endpgm192 %r = urem i32 %x, %y193 store i32 %r, ptr addrspace(1) %out194 ret void195}196 197define amdgpu_kernel void @sdiv_i32(ptr addrspace(1) %out, i32 %x, i32 %y) {198; CHECK-LABEL: @sdiv_i32(199; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 31200; CHECK-NEXT: [[TMP2:%.*]] = ashr i32 [[Y:%.*]], 31201; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], [[TMP2]]202; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[X]], [[TMP1]]203; CHECK-NEXT: [[TMP5:%.*]] = add i32 [[Y]], [[TMP2]]204; CHECK-NEXT: [[TMP6:%.*]] = xor i32 [[TMP4]], [[TMP1]]205; CHECK-NEXT: [[TMP7:%.*]] = xor i32 [[TMP5]], [[TMP2]]206; CHECK-NEXT: [[TMP8:%.*]] = uitofp i32 [[TMP7]] to float207; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP8]])208; CHECK-NEXT: [[TMP10:%.*]] = fmul fast float [[TMP9]], 0x41EFFFFFC0000000209; CHECK-NEXT: [[TMP11:%.*]] = fptoui float [[TMP10]] to i32210; CHECK-NEXT: [[TMP12:%.*]] = sub i32 0, [[TMP7]]211; CHECK-NEXT: [[TMP13:%.*]] = mul i32 [[TMP12]], [[TMP11]]212; CHECK-NEXT: [[TMP14:%.*]] = zext i32 [[TMP11]] to i64213; CHECK-NEXT: [[TMP15:%.*]] = zext i32 [[TMP13]] to i64214; CHECK-NEXT: [[TMP16:%.*]] = mul i64 [[TMP14]], [[TMP15]]215; CHECK-NEXT: [[TMP17:%.*]] = trunc i64 [[TMP16]] to i32216; CHECK-NEXT: [[TMP18:%.*]] = lshr i64 [[TMP16]], 32217; CHECK-NEXT: [[TMP19:%.*]] = trunc i64 [[TMP18]] to i32218; CHECK-NEXT: [[TMP20:%.*]] = add i32 [[TMP11]], [[TMP19]]219; CHECK-NEXT: [[TMP21:%.*]] = zext i32 [[TMP6]] to i64220; CHECK-NEXT: [[TMP22:%.*]] = zext i32 [[TMP20]] to i64221; CHECK-NEXT: [[TMP23:%.*]] = mul i64 [[TMP21]], [[TMP22]]222; CHECK-NEXT: [[TMP24:%.*]] = trunc i64 [[TMP23]] to i32223; CHECK-NEXT: [[TMP25:%.*]] = lshr i64 [[TMP23]], 32224; CHECK-NEXT: [[TMP26:%.*]] = trunc i64 [[TMP25]] to i32225; CHECK-NEXT: [[TMP27:%.*]] = mul i32 [[TMP26]], [[TMP7]]226; CHECK-NEXT: [[TMP28:%.*]] = sub i32 [[TMP6]], [[TMP27]]227; CHECK-NEXT: [[TMP29:%.*]] = icmp uge i32 [[TMP28]], [[TMP7]]228; CHECK-NEXT: [[TMP30:%.*]] = add i32 [[TMP26]], 1229; CHECK-NEXT: [[TMP31:%.*]] = select i1 [[TMP29]], i32 [[TMP30]], i32 [[TMP26]]230; CHECK-NEXT: [[TMP32:%.*]] = sub i32 [[TMP28]], [[TMP7]]231; CHECK-NEXT: [[TMP33:%.*]] = select i1 [[TMP29]], i32 [[TMP32]], i32 [[TMP28]]232; CHECK-NEXT: [[TMP34:%.*]] = icmp uge i32 [[TMP33]], [[TMP7]]233; CHECK-NEXT: [[TMP35:%.*]] = add i32 [[TMP31]], 1234; CHECK-NEXT: [[TMP36:%.*]] = select i1 [[TMP34]], i32 [[TMP35]], i32 [[TMP31]]235; CHECK-NEXT: [[TMP37:%.*]] = xor i32 [[TMP36]], [[TMP3]]236; CHECK-NEXT: [[TMP38:%.*]] = sub i32 [[TMP37]], [[TMP3]]237; CHECK-NEXT: store i32 [[TMP38]], ptr addrspace(1) [[OUT:%.*]], align 4238; CHECK-NEXT: ret void239;240; GFX6-LABEL: sdiv_i32:241; GFX6: ; %bb.0:242; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9243; GFX6-NEXT: s_waitcnt lgkmcnt(0)244; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]245; GFX6-NEXT: s_abs_i32 s6, s5246; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s6247; GFX6-NEXT: s_sub_i32 s2, 0, s6248; GFX6-NEXT: s_abs_i32 s7, s4249; GFX6-NEXT: s_xor_b32 s4, s4, s5250; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0251; GFX6-NEXT: s_ashr_i32 s4, s4, 31252; GFX6-NEXT: s_mov_b32 s3, 0xf000253; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0254; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0255; GFX6-NEXT: v_mul_lo_u32 v1, s2, v0256; GFX6-NEXT: s_mov_b32 s2, -1257; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1258; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1259; GFX6-NEXT: v_mul_hi_u32 v0, s7, v0260; GFX6-NEXT: v_readfirstlane_b32 s5, v0261; GFX6-NEXT: s_mul_i32 s5, s5, s6262; GFX6-NEXT: s_sub_i32 s5, s7, s5263; GFX6-NEXT: s_sub_i32 s7, s5, s6264; GFX6-NEXT: v_add_i32_e32 v1, vcc, 1, v0265; GFX6-NEXT: s_cmp_ge_u32 s5, s6266; GFX6-NEXT: s_cselect_b64 vcc, -1, 0267; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc268; GFX6-NEXT: s_cselect_b32 s5, s7, s5269; GFX6-NEXT: v_add_i32_e32 v1, vcc, 1, v0270; GFX6-NEXT: s_cmp_ge_u32 s5, s6271; GFX6-NEXT: s_cselect_b64 vcc, -1, 0272; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc273; GFX6-NEXT: v_xor_b32_e32 v0, s4, v0274; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s4, v0275; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0276; GFX6-NEXT: s_endpgm277;278; GFX9-LABEL: sdiv_i32:279; GFX9: ; %bb.0:280; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24281; GFX9-NEXT: v_mov_b32_e32 v1, 0282; GFX9-NEXT: s_waitcnt lgkmcnt(0)283; GFX9-NEXT: s_abs_i32 s4, s3284; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s4285; GFX9-NEXT: s_sub_i32 s5, 0, s4286; GFX9-NEXT: s_xor_b32 s3, s2, s3287; GFX9-NEXT: s_abs_i32 s2, s2288; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0289; GFX9-NEXT: s_ashr_i32 s3, s3, 31290; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0291; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0292; GFX9-NEXT: v_readfirstlane_b32 s6, v0293; GFX9-NEXT: s_mul_i32 s5, s5, s6294; GFX9-NEXT: s_mul_hi_u32 s5, s6, s5295; GFX9-NEXT: s_add_i32 s6, s6, s5296; GFX9-NEXT: s_mul_hi_u32 s5, s2, s6297; GFX9-NEXT: s_mul_i32 s6, s5, s4298; GFX9-NEXT: s_sub_i32 s2, s2, s6299; GFX9-NEXT: s_add_i32 s7, s5, 1300; GFX9-NEXT: s_sub_i32 s6, s2, s4301; GFX9-NEXT: s_cmp_ge_u32 s2, s4302; GFX9-NEXT: s_cselect_b32 s5, s7, s5303; GFX9-NEXT: s_cselect_b32 s2, s6, s2304; GFX9-NEXT: s_add_i32 s6, s5, 1305; GFX9-NEXT: s_cmp_ge_u32 s2, s4306; GFX9-NEXT: s_cselect_b32 s2, s6, s5307; GFX9-NEXT: s_xor_b32 s2, s2, s3308; GFX9-NEXT: s_sub_i32 s2, s2, s3309; GFX9-NEXT: v_mov_b32_e32 v0, s2310; GFX9-NEXT: global_store_dword v1, v0, s[0:1]311; GFX9-NEXT: s_endpgm312 %r = sdiv i32 %x, %y313 store i32 %r, ptr addrspace(1) %out314 ret void315}316 317define amdgpu_kernel void @srem_i32(ptr addrspace(1) %out, i32 %x, i32 %y) {318; CHECK-LABEL: @srem_i32(319; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 31320; CHECK-NEXT: [[TMP2:%.*]] = ashr i32 [[Y:%.*]], 31321; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[X]], [[TMP1]]322; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[Y]], [[TMP2]]323; CHECK-NEXT: [[TMP5:%.*]] = xor i32 [[TMP3]], [[TMP1]]324; CHECK-NEXT: [[TMP6:%.*]] = xor i32 [[TMP4]], [[TMP2]]325; CHECK-NEXT: [[TMP7:%.*]] = uitofp i32 [[TMP6]] to float326; CHECK-NEXT: [[TMP8:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP7]])327; CHECK-NEXT: [[TMP9:%.*]] = fmul fast float [[TMP8]], 0x41EFFFFFC0000000328; CHECK-NEXT: [[TMP10:%.*]] = fptoui float [[TMP9]] to i32329; CHECK-NEXT: [[TMP11:%.*]] = sub i32 0, [[TMP6]]330; CHECK-NEXT: [[TMP12:%.*]] = mul i32 [[TMP11]], [[TMP10]]331; CHECK-NEXT: [[TMP13:%.*]] = zext i32 [[TMP10]] to i64332; CHECK-NEXT: [[TMP14:%.*]] = zext i32 [[TMP12]] to i64333; CHECK-NEXT: [[TMP15:%.*]] = mul i64 [[TMP13]], [[TMP14]]334; CHECK-NEXT: [[TMP16:%.*]] = trunc i64 [[TMP15]] to i32335; CHECK-NEXT: [[TMP17:%.*]] = lshr i64 [[TMP15]], 32336; CHECK-NEXT: [[TMP18:%.*]] = trunc i64 [[TMP17]] to i32337; CHECK-NEXT: [[TMP19:%.*]] = add i32 [[TMP10]], [[TMP18]]338; CHECK-NEXT: [[TMP20:%.*]] = zext i32 [[TMP5]] to i64339; CHECK-NEXT: [[TMP21:%.*]] = zext i32 [[TMP19]] to i64340; CHECK-NEXT: [[TMP22:%.*]] = mul i64 [[TMP20]], [[TMP21]]341; CHECK-NEXT: [[TMP23:%.*]] = trunc i64 [[TMP22]] to i32342; CHECK-NEXT: [[TMP24:%.*]] = lshr i64 [[TMP22]], 32343; CHECK-NEXT: [[TMP25:%.*]] = trunc i64 [[TMP24]] to i32344; CHECK-NEXT: [[TMP26:%.*]] = mul i32 [[TMP25]], [[TMP6]]345; CHECK-NEXT: [[TMP27:%.*]] = sub i32 [[TMP5]], [[TMP26]]346; CHECK-NEXT: [[TMP28:%.*]] = icmp uge i32 [[TMP27]], [[TMP6]]347; CHECK-NEXT: [[TMP29:%.*]] = sub i32 [[TMP27]], [[TMP6]]348; CHECK-NEXT: [[TMP30:%.*]] = select i1 [[TMP28]], i32 [[TMP29]], i32 [[TMP27]]349; CHECK-NEXT: [[TMP31:%.*]] = icmp uge i32 [[TMP30]], [[TMP6]]350; CHECK-NEXT: [[TMP32:%.*]] = sub i32 [[TMP30]], [[TMP6]]351; CHECK-NEXT: [[TMP33:%.*]] = select i1 [[TMP31]], i32 [[TMP32]], i32 [[TMP30]]352; CHECK-NEXT: [[TMP34:%.*]] = xor i32 [[TMP33]], [[TMP1]]353; CHECK-NEXT: [[TMP35:%.*]] = sub i32 [[TMP34]], [[TMP1]]354; CHECK-NEXT: store i32 [[TMP35]], ptr addrspace(1) [[OUT:%.*]], align 4355; CHECK-NEXT: ret void356;357; GFX6-LABEL: srem_i32:358; GFX6: ; %bb.0:359; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9360; GFX6-NEXT: s_waitcnt lgkmcnt(0)361; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]362; GFX6-NEXT: s_abs_i32 s5, s5363; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s5364; GFX6-NEXT: s_sub_i32 s2, 0, s5365; GFX6-NEXT: s_abs_i32 s6, s4366; GFX6-NEXT: s_ashr_i32 s4, s4, 31367; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0368; GFX6-NEXT: s_mov_b32 s3, 0xf000369; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0370; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0371; GFX6-NEXT: v_mul_lo_u32 v1, s2, v0372; GFX6-NEXT: s_mov_b32 s2, -1373; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1374; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1375; GFX6-NEXT: v_mul_hi_u32 v0, s6, v0376; GFX6-NEXT: v_readfirstlane_b32 s7, v0377; GFX6-NEXT: s_mul_i32 s7, s7, s5378; GFX6-NEXT: s_sub_i32 s6, s6, s7379; GFX6-NEXT: s_sub_i32 s7, s6, s5380; GFX6-NEXT: s_cmp_ge_u32 s6, s5381; GFX6-NEXT: s_cselect_b32 s6, s7, s6382; GFX6-NEXT: s_sub_i32 s7, s6, s5383; GFX6-NEXT: s_cmp_ge_u32 s6, s5384; GFX6-NEXT: s_cselect_b32 s5, s7, s6385; GFX6-NEXT: s_xor_b32 s5, s5, s4386; GFX6-NEXT: s_sub_i32 s4, s5, s4387; GFX6-NEXT: v_mov_b32_e32 v0, s4388; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0389; GFX6-NEXT: s_endpgm390;391; GFX9-LABEL: srem_i32:392; GFX9: ; %bb.0:393; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24394; GFX9-NEXT: v_mov_b32_e32 v1, 0395; GFX9-NEXT: s_waitcnt lgkmcnt(0)396; GFX9-NEXT: s_abs_i32 s3, s3397; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s3398; GFX9-NEXT: s_sub_i32 s5, 0, s3399; GFX9-NEXT: s_ashr_i32 s4, s2, 31400; GFX9-NEXT: s_abs_i32 s2, s2401; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0402; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0403; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0404; GFX9-NEXT: v_readfirstlane_b32 s6, v0405; GFX9-NEXT: s_mul_i32 s5, s5, s6406; GFX9-NEXT: s_mul_hi_u32 s5, s6, s5407; GFX9-NEXT: s_add_i32 s6, s6, s5408; GFX9-NEXT: s_mul_hi_u32 s5, s2, s6409; GFX9-NEXT: s_mul_i32 s5, s5, s3410; GFX9-NEXT: s_sub_i32 s2, s2, s5411; GFX9-NEXT: s_sub_i32 s5, s2, s3412; GFX9-NEXT: s_cmp_ge_u32 s2, s3413; GFX9-NEXT: s_cselect_b32 s2, s5, s2414; GFX9-NEXT: s_sub_i32 s5, s2, s3415; GFX9-NEXT: s_cmp_ge_u32 s2, s3416; GFX9-NEXT: s_cselect_b32 s2, s5, s2417; GFX9-NEXT: s_xor_b32 s2, s2, s4418; GFX9-NEXT: s_sub_i32 s2, s2, s4419; GFX9-NEXT: v_mov_b32_e32 v0, s2420; GFX9-NEXT: global_store_dword v1, v0, s[0:1]421; GFX9-NEXT: s_endpgm422 %r = srem i32 %x, %y423 store i32 %r, ptr addrspace(1) %out424 ret void425}426 427define amdgpu_kernel void @udiv_i16(ptr addrspace(1) %out, i16 %x, i16 %y) {428; CHECK-LABEL: @udiv_i16(429; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[X:%.*]] to i32430; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[Y:%.*]] to i32431; CHECK-NEXT: [[TMP3:%.*]] = uitofp i32 [[TMP1]] to float432; CHECK-NEXT: [[TMP4:%.*]] = uitofp i32 [[TMP2]] to float433; CHECK-NEXT: [[TMP5:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP4]])434; CHECK-NEXT: [[TMP6:%.*]] = fmul fast float [[TMP3]], [[TMP5]]435; CHECK-NEXT: [[TMP7:%.*]] = call fast float @llvm.trunc.f32(float [[TMP6]])436; CHECK-NEXT: [[TMP8:%.*]] = fneg fast float [[TMP7]]437; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP8]], float [[TMP4]], float [[TMP3]])438; CHECK-NEXT: [[TMP10:%.*]] = fptoui float [[TMP7]] to i32439; CHECK-NEXT: [[TMP11:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])440; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.fabs.f32(float [[TMP4]])441; CHECK-NEXT: [[TMP13:%.*]] = fcmp fast oge float [[TMP11]], [[TMP12]]442; CHECK-NEXT: [[TMP14:%.*]] = select i1 [[TMP13]], i32 1, i32 0443; CHECK-NEXT: [[TMP15:%.*]] = add i32 [[TMP10]], [[TMP14]]444; CHECK-NEXT: [[TMP16:%.*]] = and i32 [[TMP15]], 65535445; CHECK-NEXT: [[TMP17:%.*]] = trunc i32 [[TMP16]] to i16446; CHECK-NEXT: store i16 [[TMP17]], ptr addrspace(1) [[OUT:%.*]], align 2447; CHECK-NEXT: ret void448;449; GFX6-LABEL: udiv_i16:450; GFX6: ; %bb.0:451; GFX6-NEXT: s_load_dword s0, s[4:5], 0xb452; GFX6-NEXT: s_mov_b32 s3, 0xf000453; GFX6-NEXT: s_mov_b32 s2, -1454; GFX6-NEXT: s_waitcnt lgkmcnt(0)455; GFX6-NEXT: s_lshr_b32 s1, s0, 16456; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s1457; GFX6-NEXT: s_and_b32 s0, s0, 0xffff458; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s0459; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9460; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v0461; GFX6-NEXT: v_mul_f32_e32 v2, v1, v2462; GFX6-NEXT: v_trunc_f32_e32 v2, v2463; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v2464; GFX6-NEXT: v_mad_f32 v1, -v2, v0, v1465; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0466; GFX6-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc467; GFX6-NEXT: s_waitcnt lgkmcnt(0)468; GFX6-NEXT: buffer_store_short v0, off, s[0:3], 0469; GFX6-NEXT: s_endpgm470;471; GFX9-LABEL: udiv_i16:472; GFX9: ; %bb.0:473; GFX9-NEXT: s_load_dword s0, s[4:5], 0x2c474; GFX9-NEXT: v_mov_b32_e32 v3, 0475; GFX9-NEXT: s_waitcnt lgkmcnt(0)476; GFX9-NEXT: s_lshr_b32 s1, s0, 16477; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s1478; GFX9-NEXT: s_and_b32 s0, s0, 0xffff479; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s0480; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24481; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v0482; GFX9-NEXT: v_mul_f32_e32 v2, v1, v2483; GFX9-NEXT: v_trunc_f32_e32 v2, v2484; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v2485; GFX9-NEXT: v_mad_f32 v1, -v2, v0, v1486; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0487; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, 0, v4, vcc488; GFX9-NEXT: s_waitcnt lgkmcnt(0)489; GFX9-NEXT: global_store_short v3, v0, s[0:1]490; GFX9-NEXT: s_endpgm491 %r = udiv i16 %x, %y492 store i16 %r, ptr addrspace(1) %out493 ret void494}495 496define amdgpu_kernel void @urem_i16(ptr addrspace(1) %out, i16 %x, i16 %y) {497; CHECK-LABEL: @urem_i16(498; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[X:%.*]] to i32499; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[Y:%.*]] to i32500; CHECK-NEXT: [[TMP3:%.*]] = uitofp i32 [[TMP1]] to float501; CHECK-NEXT: [[TMP4:%.*]] = uitofp i32 [[TMP2]] to float502; CHECK-NEXT: [[TMP5:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP4]])503; CHECK-NEXT: [[TMP6:%.*]] = fmul fast float [[TMP3]], [[TMP5]]504; CHECK-NEXT: [[TMP7:%.*]] = call fast float @llvm.trunc.f32(float [[TMP6]])505; CHECK-NEXT: [[TMP8:%.*]] = fneg fast float [[TMP7]]506; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP8]], float [[TMP4]], float [[TMP3]])507; CHECK-NEXT: [[TMP10:%.*]] = fptoui float [[TMP7]] to i32508; CHECK-NEXT: [[TMP11:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])509; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.fabs.f32(float [[TMP4]])510; CHECK-NEXT: [[TMP13:%.*]] = fcmp fast oge float [[TMP11]], [[TMP12]]511; CHECK-NEXT: [[TMP14:%.*]] = select i1 [[TMP13]], i32 1, i32 0512; CHECK-NEXT: [[TMP15:%.*]] = add i32 [[TMP10]], [[TMP14]]513; CHECK-NEXT: [[TMP16:%.*]] = mul i32 [[TMP15]], [[TMP2]]514; CHECK-NEXT: [[TMP17:%.*]] = sub i32 [[TMP1]], [[TMP16]]515; CHECK-NEXT: [[TMP18:%.*]] = and i32 [[TMP17]], 65535516; CHECK-NEXT: [[TMP19:%.*]] = trunc i32 [[TMP18]] to i16517; CHECK-NEXT: store i16 [[TMP19]], ptr addrspace(1) [[OUT:%.*]], align 2518; CHECK-NEXT: ret void519;520; GFX6-LABEL: urem_i16:521; GFX6: ; %bb.0:522; GFX6-NEXT: s_load_dword s6, s[4:5], 0xb523; GFX6-NEXT: s_mov_b32 s3, 0xf000524; GFX6-NEXT: s_waitcnt lgkmcnt(0)525; GFX6-NEXT: s_lshr_b32 s2, s6, 16526; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s2527; GFX6-NEXT: s_and_b32 s0, s6, 0xffff528; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s0529; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9530; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v0531; GFX6-NEXT: v_mul_f32_e32 v2, v1, v2532; GFX6-NEXT: v_trunc_f32_e32 v2, v2533; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v2534; GFX6-NEXT: v_mad_f32 v1, -v2, v0, v1535; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0536; GFX6-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc537; GFX6-NEXT: v_mul_lo_u32 v0, v0, s2538; GFX6-NEXT: s_mov_b32 s2, -1539; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s6, v0540; GFX6-NEXT: s_waitcnt lgkmcnt(0)541; GFX6-NEXT: buffer_store_short v0, off, s[0:3], 0542; GFX6-NEXT: s_endpgm543;544; GFX9-LABEL: urem_i16:545; GFX9: ; %bb.0:546; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c547; GFX9-NEXT: s_waitcnt lgkmcnt(0)548; GFX9-NEXT: s_lshr_b32 s3, s2, 16549; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s3550; GFX9-NEXT: s_and_b32 s0, s2, 0xffff551; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s0552; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24553; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v0554; GFX9-NEXT: v_mul_f32_e32 v2, v1, v2555; GFX9-NEXT: v_trunc_f32_e32 v2, v2556; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v2557; GFX9-NEXT: v_mad_f32 v1, -v2, v0, v1558; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0559; GFX9-NEXT: v_mov_b32_e32 v1, 0560; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, 0, v3, vcc561; GFX9-NEXT: v_mul_lo_u32 v0, v0, s3562; GFX9-NEXT: v_sub_u32_e32 v0, s2, v0563; GFX9-NEXT: s_waitcnt lgkmcnt(0)564; GFX9-NEXT: global_store_short v1, v0, s[0:1]565; GFX9-NEXT: s_endpgm566 %r = urem i16 %x, %y567 store i16 %r, ptr addrspace(1) %out568 ret void569}570 571define amdgpu_kernel void @sdiv_i16(ptr addrspace(1) %out, i16 %x, i16 %y) {572; CHECK-LABEL: @sdiv_i16(573; CHECK-NEXT: [[TMP1:%.*]] = sext i16 [[X:%.*]] to i32574; CHECK-NEXT: [[TMP2:%.*]] = sext i16 [[Y:%.*]] to i32575; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], [[TMP2]]576; CHECK-NEXT: [[TMP4:%.*]] = ashr i32 [[TMP3]], 30577; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP4]], 1578; CHECK-NEXT: [[TMP6:%.*]] = sitofp i32 [[TMP1]] to float579; CHECK-NEXT: [[TMP7:%.*]] = sitofp i32 [[TMP2]] to float580; CHECK-NEXT: [[TMP8:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP7]])581; CHECK-NEXT: [[TMP9:%.*]] = fmul fast float [[TMP6]], [[TMP8]]582; CHECK-NEXT: [[TMP10:%.*]] = call fast float @llvm.trunc.f32(float [[TMP9]])583; CHECK-NEXT: [[TMP11:%.*]] = fneg fast float [[TMP10]]584; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP11]], float [[TMP7]], float [[TMP6]])585; CHECK-NEXT: [[TMP13:%.*]] = fptosi float [[TMP10]] to i32586; CHECK-NEXT: [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP12]])587; CHECK-NEXT: [[TMP15:%.*]] = call fast float @llvm.fabs.f32(float [[TMP7]])588; CHECK-NEXT: [[TMP16:%.*]] = fcmp fast oge float [[TMP14]], [[TMP15]]589; CHECK-NEXT: [[TMP17:%.*]] = select i1 [[TMP16]], i32 [[TMP5]], i32 0590; CHECK-NEXT: [[TMP18:%.*]] = add i32 [[TMP13]], [[TMP17]]591; CHECK-NEXT: [[TMP19:%.*]] = shl i32 [[TMP18]], 16592; CHECK-NEXT: [[TMP20:%.*]] = ashr i32 [[TMP19]], 16593; CHECK-NEXT: [[TMP21:%.*]] = trunc i32 [[TMP20]] to i16594; CHECK-NEXT: store i16 [[TMP21]], ptr addrspace(1) [[OUT:%.*]], align 2595; CHECK-NEXT: ret void596;597; GFX6-LABEL: sdiv_i16:598; GFX6: ; %bb.0:599; GFX6-NEXT: s_load_dword s6, s[4:5], 0xb600; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9601; GFX6-NEXT: s_mov_b32 s3, 0xf000602; GFX6-NEXT: s_mov_b32 s2, -1603; GFX6-NEXT: s_waitcnt lgkmcnt(0)604; GFX6-NEXT: s_ashr_i32 s4, s6, 16605; GFX6-NEXT: v_cvt_f32_i32_e32 v0, s4606; GFX6-NEXT: s_sext_i32_i16 s5, s6607; GFX6-NEXT: v_cvt_f32_i32_e32 v1, s5608; GFX6-NEXT: s_xor_b32 s4, s5, s4609; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v0610; GFX6-NEXT: s_ashr_i32 s4, s4, 30611; GFX6-NEXT: s_or_b32 s6, s4, 1612; GFX6-NEXT: v_mul_f32_e32 v2, v1, v2613; GFX6-NEXT: v_trunc_f32_e32 v2, v2614; GFX6-NEXT: v_mad_f32 v1, -v2, v0, v1615; GFX6-NEXT: v_cvt_i32_f32_e32 v2, v2616; GFX6-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0|617; GFX6-NEXT: s_and_b64 s[4:5], s[4:5], exec618; GFX6-NEXT: s_cselect_b32 s4, s6, 0619; GFX6-NEXT: v_add_i32_e32 v0, vcc, s4, v2620; GFX6-NEXT: buffer_store_short v0, off, s[0:3], 0621; GFX6-NEXT: s_endpgm622;623; GFX9-LABEL: sdiv_i16:624; GFX9: ; %bb.0:625; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c626; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24627; GFX9-NEXT: v_mov_b32_e32 v1, 0628; GFX9-NEXT: s_waitcnt lgkmcnt(0)629; GFX9-NEXT: s_ashr_i32 s3, s2, 16630; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s3631; GFX9-NEXT: s_sext_i32_i16 s2, s2632; GFX9-NEXT: v_cvt_f32_i32_e32 v2, s2633; GFX9-NEXT: s_xor_b32 s2, s2, s3634; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v0635; GFX9-NEXT: s_ashr_i32 s2, s2, 30636; GFX9-NEXT: s_or_b32 s4, s2, 1637; GFX9-NEXT: v_mul_f32_e32 v3, v2, v3638; GFX9-NEXT: v_trunc_f32_e32 v3, v3639; GFX9-NEXT: v_mad_f32 v2, -v3, v0, v2640; GFX9-NEXT: v_cvt_i32_f32_e32 v3, v3641; GFX9-NEXT: v_cmp_ge_f32_e64 s[2:3], |v2|, |v0|642; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec643; GFX9-NEXT: s_cselect_b32 s2, s4, 0644; GFX9-NEXT: v_add_u32_e32 v0, s2, v3645; GFX9-NEXT: global_store_short v1, v0, s[0:1]646; GFX9-NEXT: s_endpgm647 %r = sdiv i16 %x, %y648 store i16 %r, ptr addrspace(1) %out649 ret void650}651 652define amdgpu_kernel void @srem_i16(ptr addrspace(1) %out, i16 %x, i16 %y) {653; CHECK-LABEL: @srem_i16(654; CHECK-NEXT: [[TMP1:%.*]] = sext i16 [[X:%.*]] to i32655; CHECK-NEXT: [[TMP2:%.*]] = sext i16 [[Y:%.*]] to i32656; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], [[TMP2]]657; CHECK-NEXT: [[TMP4:%.*]] = ashr i32 [[TMP3]], 30658; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP4]], 1659; CHECK-NEXT: [[TMP6:%.*]] = sitofp i32 [[TMP1]] to float660; CHECK-NEXT: [[TMP7:%.*]] = sitofp i32 [[TMP2]] to float661; CHECK-NEXT: [[TMP8:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP7]])662; CHECK-NEXT: [[TMP9:%.*]] = fmul fast float [[TMP6]], [[TMP8]]663; CHECK-NEXT: [[TMP10:%.*]] = call fast float @llvm.trunc.f32(float [[TMP9]])664; CHECK-NEXT: [[TMP11:%.*]] = fneg fast float [[TMP10]]665; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP11]], float [[TMP7]], float [[TMP6]])666; CHECK-NEXT: [[TMP13:%.*]] = fptosi float [[TMP10]] to i32667; CHECK-NEXT: [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP12]])668; CHECK-NEXT: [[TMP15:%.*]] = call fast float @llvm.fabs.f32(float [[TMP7]])669; CHECK-NEXT: [[TMP16:%.*]] = fcmp fast oge float [[TMP14]], [[TMP15]]670; CHECK-NEXT: [[TMP17:%.*]] = select i1 [[TMP16]], i32 [[TMP5]], i32 0671; CHECK-NEXT: [[TMP18:%.*]] = add i32 [[TMP13]], [[TMP17]]672; CHECK-NEXT: [[TMP19:%.*]] = mul i32 [[TMP18]], [[TMP2]]673; CHECK-NEXT: [[TMP20:%.*]] = sub i32 [[TMP1]], [[TMP19]]674; CHECK-NEXT: [[TMP21:%.*]] = shl i32 [[TMP20]], 16675; CHECK-NEXT: [[TMP22:%.*]] = ashr i32 [[TMP21]], 16676; CHECK-NEXT: [[TMP23:%.*]] = trunc i32 [[TMP22]] to i16677; CHECK-NEXT: store i16 [[TMP23]], ptr addrspace(1) [[OUT:%.*]], align 2678; CHECK-NEXT: ret void679;680; GFX6-LABEL: srem_i16:681; GFX6: ; %bb.0:682; GFX6-NEXT: s_load_dword s6, s[4:5], 0xb683; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9684; GFX6-NEXT: s_waitcnt lgkmcnt(0)685; GFX6-NEXT: s_ashr_i32 s7, s6, 16686; GFX6-NEXT: v_cvt_f32_i32_e32 v0, s7687; GFX6-NEXT: s_sext_i32_i16 s2, s6688; GFX6-NEXT: v_cvt_f32_i32_e32 v1, s2689; GFX6-NEXT: s_xor_b32 s2, s2, s7690; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v0691; GFX6-NEXT: s_ashr_i32 s2, s2, 30692; GFX6-NEXT: s_or_b32 s4, s2, 1693; GFX6-NEXT: v_mul_f32_e32 v2, v1, v2694; GFX6-NEXT: v_trunc_f32_e32 v2, v2695; GFX6-NEXT: v_mad_f32 v1, -v2, v0, v1696; GFX6-NEXT: v_cvt_i32_f32_e32 v2, v2697; GFX6-NEXT: v_cmp_ge_f32_e64 s[2:3], |v1|, |v0|698; GFX6-NEXT: s_and_b64 s[2:3], s[2:3], exec699; GFX6-NEXT: s_cselect_b32 s2, s4, 0700; GFX6-NEXT: v_add_i32_e32 v0, vcc, s2, v2701; GFX6-NEXT: v_mul_lo_u32 v0, v0, s7702; GFX6-NEXT: s_mov_b32 s3, 0xf000703; GFX6-NEXT: s_mov_b32 s2, -1704; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s6, v0705; GFX6-NEXT: buffer_store_short v0, off, s[0:3], 0706; GFX6-NEXT: s_endpgm707;708; GFX9-LABEL: srem_i16:709; GFX9: ; %bb.0:710; GFX9-NEXT: s_load_dword s6, s[4:5], 0x2c711; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24712; GFX9-NEXT: s_waitcnt lgkmcnt(0)713; GFX9-NEXT: s_ashr_i32 s7, s6, 16714; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s7715; GFX9-NEXT: s_sext_i32_i16 s2, s6716; GFX9-NEXT: v_cvt_f32_i32_e32 v1, s2717; GFX9-NEXT: s_xor_b32 s2, s2, s7718; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v0719; GFX9-NEXT: s_ashr_i32 s2, s2, 30720; GFX9-NEXT: s_or_b32 s4, s2, 1721; GFX9-NEXT: v_mul_f32_e32 v2, v1, v2722; GFX9-NEXT: v_trunc_f32_e32 v2, v2723; GFX9-NEXT: v_mad_f32 v1, -v2, v0, v1724; GFX9-NEXT: v_cvt_i32_f32_e32 v2, v2725; GFX9-NEXT: v_cmp_ge_f32_e64 s[2:3], |v1|, |v0|726; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec727; GFX9-NEXT: s_cselect_b32 s2, s4, 0728; GFX9-NEXT: v_add_u32_e32 v0, s2, v2729; GFX9-NEXT: v_mul_lo_u32 v0, v0, s7730; GFX9-NEXT: v_mov_b32_e32 v1, 0731; GFX9-NEXT: v_sub_u32_e32 v0, s6, v0732; GFX9-NEXT: global_store_short v1, v0, s[0:1]733; GFX9-NEXT: s_endpgm734 %r = srem i16 %x, %y735 store i16 %r, ptr addrspace(1) %out736 ret void737}738 739define amdgpu_kernel void @udiv_i8(ptr addrspace(1) %out, i8 %x, i8 %y) {740; CHECK-LABEL: @udiv_i8(741; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[X:%.*]] to i32742; CHECK-NEXT: [[TMP2:%.*]] = zext i8 [[Y:%.*]] to i32743; CHECK-NEXT: [[TMP3:%.*]] = uitofp i32 [[TMP1]] to float744; CHECK-NEXT: [[TMP4:%.*]] = uitofp i32 [[TMP2]] to float745; CHECK-NEXT: [[TMP5:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP4]])746; CHECK-NEXT: [[TMP6:%.*]] = fmul fast float [[TMP3]], [[TMP5]]747; CHECK-NEXT: [[TMP7:%.*]] = call fast float @llvm.trunc.f32(float [[TMP6]])748; CHECK-NEXT: [[TMP8:%.*]] = fneg fast float [[TMP7]]749; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP8]], float [[TMP4]], float [[TMP3]])750; CHECK-NEXT: [[TMP10:%.*]] = fptoui float [[TMP7]] to i32751; CHECK-NEXT: [[TMP11:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])752; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.fabs.f32(float [[TMP4]])753; CHECK-NEXT: [[TMP13:%.*]] = fcmp fast oge float [[TMP11]], [[TMP12]]754; CHECK-NEXT: [[TMP14:%.*]] = select i1 [[TMP13]], i32 1, i32 0755; CHECK-NEXT: [[TMP15:%.*]] = add i32 [[TMP10]], [[TMP14]]756; CHECK-NEXT: [[TMP16:%.*]] = and i32 [[TMP15]], 255757; CHECK-NEXT: [[TMP17:%.*]] = trunc i32 [[TMP16]] to i8758; CHECK-NEXT: store i8 [[TMP17]], ptr addrspace(1) [[OUT:%.*]], align 1759; CHECK-NEXT: ret void760;761; GFX6-LABEL: udiv_i8:762; GFX6: ; %bb.0:763; GFX6-NEXT: s_load_dword s6, s[4:5], 0xb764; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9765; GFX6-NEXT: s_mov_b32 s3, 0xf000766; GFX6-NEXT: s_mov_b32 s2, -1767; GFX6-NEXT: s_waitcnt lgkmcnt(0)768; GFX6-NEXT: v_cvt_f32_ubyte1_e32 v0, s6769; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v0770; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v2, s6771; GFX6-NEXT: v_mul_f32_e32 v1, v2, v1772; GFX6-NEXT: v_trunc_f32_e32 v1, v1773; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v1774; GFX6-NEXT: v_mad_f32 v1, -v1, v0, v2775; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0776; GFX6-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc777; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0778; GFX6-NEXT: s_endpgm779;780; GFX9-LABEL: udiv_i8:781; GFX9: ; %bb.0:782; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c783; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24784; GFX9-NEXT: v_mov_b32_e32 v2, 0785; GFX9-NEXT: s_waitcnt lgkmcnt(0)786; GFX9-NEXT: v_cvt_f32_ubyte1_e32 v0, s2787; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v0788; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v3, s2789; GFX9-NEXT: v_mul_f32_e32 v1, v3, v1790; GFX9-NEXT: v_trunc_f32_e32 v1, v1791; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v1792; GFX9-NEXT: v_mad_f32 v1, -v1, v0, v3793; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0794; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, 0, v4, vcc795; GFX9-NEXT: global_store_byte v2, v0, s[0:1]796; GFX9-NEXT: s_endpgm797 %r = udiv i8 %x, %y798 store i8 %r, ptr addrspace(1) %out799 ret void800}801 802define amdgpu_kernel void @urem_i8(ptr addrspace(1) %out, i8 %x, i8 %y) {803; CHECK-LABEL: @urem_i8(804; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[X:%.*]] to i32805; CHECK-NEXT: [[TMP2:%.*]] = zext i8 [[Y:%.*]] to i32806; CHECK-NEXT: [[TMP3:%.*]] = uitofp i32 [[TMP1]] to float807; CHECK-NEXT: [[TMP4:%.*]] = uitofp i32 [[TMP2]] to float808; CHECK-NEXT: [[TMP5:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP4]])809; CHECK-NEXT: [[TMP6:%.*]] = fmul fast float [[TMP3]], [[TMP5]]810; CHECK-NEXT: [[TMP7:%.*]] = call fast float @llvm.trunc.f32(float [[TMP6]])811; CHECK-NEXT: [[TMP8:%.*]] = fneg fast float [[TMP7]]812; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP8]], float [[TMP4]], float [[TMP3]])813; CHECK-NEXT: [[TMP10:%.*]] = fptoui float [[TMP7]] to i32814; CHECK-NEXT: [[TMP11:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])815; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.fabs.f32(float [[TMP4]])816; CHECK-NEXT: [[TMP13:%.*]] = fcmp fast oge float [[TMP11]], [[TMP12]]817; CHECK-NEXT: [[TMP14:%.*]] = select i1 [[TMP13]], i32 1, i32 0818; CHECK-NEXT: [[TMP15:%.*]] = add i32 [[TMP10]], [[TMP14]]819; CHECK-NEXT: [[TMP16:%.*]] = mul i32 [[TMP15]], [[TMP2]]820; CHECK-NEXT: [[TMP17:%.*]] = sub i32 [[TMP1]], [[TMP16]]821; CHECK-NEXT: [[TMP18:%.*]] = and i32 [[TMP17]], 255822; CHECK-NEXT: [[TMP19:%.*]] = trunc i32 [[TMP18]] to i8823; CHECK-NEXT: store i8 [[TMP19]], ptr addrspace(1) [[OUT:%.*]], align 1824; CHECK-NEXT: ret void825;826; GFX6-LABEL: urem_i8:827; GFX6: ; %bb.0:828; GFX6-NEXT: s_load_dword s6, s[4:5], 0xb829; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9830; GFX6-NEXT: s_mov_b32 s3, 0xf000831; GFX6-NEXT: s_waitcnt lgkmcnt(0)832; GFX6-NEXT: v_cvt_f32_ubyte1_e32 v0, s6833; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v0834; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v2, s6835; GFX6-NEXT: s_lshr_b32 s2, s6, 8836; GFX6-NEXT: v_mul_f32_e32 v1, v2, v1837; GFX6-NEXT: v_trunc_f32_e32 v1, v1838; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v1839; GFX6-NEXT: v_mad_f32 v1, -v1, v0, v2840; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0841; GFX6-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc842; GFX6-NEXT: v_mul_lo_u32 v0, v0, s2843; GFX6-NEXT: s_mov_b32 s2, -1844; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s6, v0845; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0846; GFX6-NEXT: s_endpgm847;848; GFX9-LABEL: urem_i8:849; GFX9: ; %bb.0:850; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c851; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24852; GFX9-NEXT: s_waitcnt lgkmcnt(0)853; GFX9-NEXT: v_cvt_f32_ubyte1_e32 v0, s2854; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v0855; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v2, s2856; GFX9-NEXT: s_lshr_b32 s3, s2, 8857; GFX9-NEXT: v_mul_f32_e32 v1, v2, v1858; GFX9-NEXT: v_trunc_f32_e32 v1, v1859; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v1860; GFX9-NEXT: v_mad_f32 v1, -v1, v0, v2861; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0862; GFX9-NEXT: v_mov_b32_e32 v1, 0863; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, 0, v3, vcc864; GFX9-NEXT: v_mul_lo_u32 v0, v0, s3865; GFX9-NEXT: v_sub_u32_e32 v0, s2, v0866; GFX9-NEXT: global_store_byte v1, v0, s[0:1]867; GFX9-NEXT: s_endpgm868 %r = urem i8 %x, %y869 store i8 %r, ptr addrspace(1) %out870 ret void871}872 873define amdgpu_kernel void @sdiv_i8(ptr addrspace(1) %out, i8 %x, i8 %y) {874; CHECK-LABEL: @sdiv_i8(875; CHECK-NEXT: [[TMP1:%.*]] = sext i8 [[X:%.*]] to i32876; CHECK-NEXT: [[TMP2:%.*]] = sext i8 [[Y:%.*]] to i32877; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], [[TMP2]]878; CHECK-NEXT: [[TMP4:%.*]] = ashr i32 [[TMP3]], 30879; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP4]], 1880; CHECK-NEXT: [[TMP6:%.*]] = sitofp i32 [[TMP1]] to float881; CHECK-NEXT: [[TMP7:%.*]] = sitofp i32 [[TMP2]] to float882; CHECK-NEXT: [[TMP8:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP7]])883; CHECK-NEXT: [[TMP9:%.*]] = fmul fast float [[TMP6]], [[TMP8]]884; CHECK-NEXT: [[TMP10:%.*]] = call fast float @llvm.trunc.f32(float [[TMP9]])885; CHECK-NEXT: [[TMP11:%.*]] = fneg fast float [[TMP10]]886; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP11]], float [[TMP7]], float [[TMP6]])887; CHECK-NEXT: [[TMP13:%.*]] = fptosi float [[TMP10]] to i32888; CHECK-NEXT: [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP12]])889; CHECK-NEXT: [[TMP15:%.*]] = call fast float @llvm.fabs.f32(float [[TMP7]])890; CHECK-NEXT: [[TMP16:%.*]] = fcmp fast oge float [[TMP14]], [[TMP15]]891; CHECK-NEXT: [[TMP17:%.*]] = select i1 [[TMP16]], i32 [[TMP5]], i32 0892; CHECK-NEXT: [[TMP18:%.*]] = add i32 [[TMP13]], [[TMP17]]893; CHECK-NEXT: [[TMP19:%.*]] = shl i32 [[TMP18]], 24894; CHECK-NEXT: [[TMP20:%.*]] = ashr i32 [[TMP19]], 24895; CHECK-NEXT: [[TMP21:%.*]] = trunc i32 [[TMP20]] to i8896; CHECK-NEXT: store i8 [[TMP21]], ptr addrspace(1) [[OUT:%.*]], align 1897; CHECK-NEXT: ret void898;899; GFX6-LABEL: sdiv_i8:900; GFX6: ; %bb.0:901; GFX6-NEXT: s_load_dword s6, s[4:5], 0xb902; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9903; GFX6-NEXT: s_mov_b32 s3, 0xf000904; GFX6-NEXT: s_mov_b32 s2, -1905; GFX6-NEXT: s_waitcnt lgkmcnt(0)906; GFX6-NEXT: s_bfe_i32 s4, s6, 0x80008907; GFX6-NEXT: v_cvt_f32_i32_e32 v0, s4908; GFX6-NEXT: s_sext_i32_i8 s5, s6909; GFX6-NEXT: v_cvt_f32_i32_e32 v1, s5910; GFX6-NEXT: s_xor_b32 s4, s5, s4911; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v0912; GFX6-NEXT: s_ashr_i32 s4, s4, 30913; GFX6-NEXT: s_or_b32 s6, s4, 1914; GFX6-NEXT: v_mul_f32_e32 v2, v1, v2915; GFX6-NEXT: v_trunc_f32_e32 v2, v2916; GFX6-NEXT: v_mad_f32 v1, -v2, v0, v1917; GFX6-NEXT: v_cvt_i32_f32_e32 v2, v2918; GFX6-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0|919; GFX6-NEXT: s_and_b64 s[4:5], s[4:5], exec920; GFX6-NEXT: s_cselect_b32 s4, s6, 0921; GFX6-NEXT: v_add_i32_e32 v0, vcc, s4, v2922; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0923; GFX6-NEXT: s_endpgm924;925; GFX9-LABEL: sdiv_i8:926; GFX9: ; %bb.0:927; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c928; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24929; GFX9-NEXT: v_mov_b32_e32 v1, 0930; GFX9-NEXT: s_waitcnt lgkmcnt(0)931; GFX9-NEXT: s_bfe_i32 s3, s2, 0x80008932; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s3933; GFX9-NEXT: s_sext_i32_i8 s2, s2934; GFX9-NEXT: v_cvt_f32_i32_e32 v2, s2935; GFX9-NEXT: s_xor_b32 s2, s2, s3936; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v0937; GFX9-NEXT: s_ashr_i32 s2, s2, 30938; GFX9-NEXT: s_or_b32 s4, s2, 1939; GFX9-NEXT: v_mul_f32_e32 v3, v2, v3940; GFX9-NEXT: v_trunc_f32_e32 v3, v3941; GFX9-NEXT: v_mad_f32 v2, -v3, v0, v2942; GFX9-NEXT: v_cvt_i32_f32_e32 v3, v3943; GFX9-NEXT: v_cmp_ge_f32_e64 s[2:3], |v2|, |v0|944; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec945; GFX9-NEXT: s_cselect_b32 s2, s4, 0946; GFX9-NEXT: v_add_u32_e32 v0, s2, v3947; GFX9-NEXT: global_store_byte v1, v0, s[0:1]948; GFX9-NEXT: s_endpgm949 %r = sdiv i8 %x, %y950 store i8 %r, ptr addrspace(1) %out951 ret void952}953 954define amdgpu_kernel void @srem_i8(ptr addrspace(1) %out, i8 %x, i8 %y) {955; CHECK-LABEL: @srem_i8(956; CHECK-NEXT: [[TMP1:%.*]] = sext i8 [[X:%.*]] to i32957; CHECK-NEXT: [[TMP2:%.*]] = sext i8 [[Y:%.*]] to i32958; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], [[TMP2]]959; CHECK-NEXT: [[TMP4:%.*]] = ashr i32 [[TMP3]], 30960; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP4]], 1961; CHECK-NEXT: [[TMP6:%.*]] = sitofp i32 [[TMP1]] to float962; CHECK-NEXT: [[TMP7:%.*]] = sitofp i32 [[TMP2]] to float963; CHECK-NEXT: [[TMP8:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP7]])964; CHECK-NEXT: [[TMP9:%.*]] = fmul fast float [[TMP6]], [[TMP8]]965; CHECK-NEXT: [[TMP10:%.*]] = call fast float @llvm.trunc.f32(float [[TMP9]])966; CHECK-NEXT: [[TMP11:%.*]] = fneg fast float [[TMP10]]967; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP11]], float [[TMP7]], float [[TMP6]])968; CHECK-NEXT: [[TMP13:%.*]] = fptosi float [[TMP10]] to i32969; CHECK-NEXT: [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP12]])970; CHECK-NEXT: [[TMP15:%.*]] = call fast float @llvm.fabs.f32(float [[TMP7]])971; CHECK-NEXT: [[TMP16:%.*]] = fcmp fast oge float [[TMP14]], [[TMP15]]972; CHECK-NEXT: [[TMP17:%.*]] = select i1 [[TMP16]], i32 [[TMP5]], i32 0973; CHECK-NEXT: [[TMP18:%.*]] = add i32 [[TMP13]], [[TMP17]]974; CHECK-NEXT: [[TMP19:%.*]] = mul i32 [[TMP18]], [[TMP2]]975; CHECK-NEXT: [[TMP20:%.*]] = sub i32 [[TMP1]], [[TMP19]]976; CHECK-NEXT: [[TMP21:%.*]] = shl i32 [[TMP20]], 24977; CHECK-NEXT: [[TMP22:%.*]] = ashr i32 [[TMP21]], 24978; CHECK-NEXT: [[TMP23:%.*]] = trunc i32 [[TMP22]] to i8979; CHECK-NEXT: store i8 [[TMP23]], ptr addrspace(1) [[OUT:%.*]], align 1980; CHECK-NEXT: ret void981;982; GFX6-LABEL: srem_i8:983; GFX6: ; %bb.0:984; GFX6-NEXT: s_load_dword s6, s[4:5], 0xb985; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9986; GFX6-NEXT: s_waitcnt lgkmcnt(0)987; GFX6-NEXT: s_bfe_i32 s2, s6, 0x80008988; GFX6-NEXT: v_cvt_f32_i32_e32 v0, s2989; GFX6-NEXT: s_sext_i32_i8 s3, s6990; GFX6-NEXT: v_cvt_f32_i32_e32 v1, s3991; GFX6-NEXT: s_xor_b32 s2, s3, s2992; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v0993; GFX6-NEXT: s_ashr_i32 s2, s2, 30994; GFX6-NEXT: s_lshr_b32 s4, s6, 8995; GFX6-NEXT: s_or_b32 s5, s2, 1996; GFX6-NEXT: v_mul_f32_e32 v2, v1, v2997; GFX6-NEXT: v_trunc_f32_e32 v2, v2998; GFX6-NEXT: v_mad_f32 v1, -v2, v0, v1999; GFX6-NEXT: v_cvt_i32_f32_e32 v2, v21000; GFX6-NEXT: v_cmp_ge_f32_e64 s[2:3], |v1|, |v0|1001; GFX6-NEXT: s_and_b64 s[2:3], s[2:3], exec1002; GFX6-NEXT: s_cselect_b32 s2, s5, 01003; GFX6-NEXT: v_add_i32_e32 v0, vcc, s2, v21004; GFX6-NEXT: v_mul_lo_u32 v0, v0, s41005; GFX6-NEXT: s_mov_b32 s3, 0xf0001006; GFX6-NEXT: s_mov_b32 s2, -11007; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s6, v01008; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 01009; GFX6-NEXT: s_endpgm1010;1011; GFX9-LABEL: srem_i8:1012; GFX9: ; %bb.0:1013; GFX9-NEXT: s_load_dword s6, s[4:5], 0x2c1014; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241015; GFX9-NEXT: s_waitcnt lgkmcnt(0)1016; GFX9-NEXT: s_bfe_i32 s2, s6, 0x800081017; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s21018; GFX9-NEXT: s_sext_i32_i8 s3, s61019; GFX9-NEXT: v_cvt_f32_i32_e32 v1, s31020; GFX9-NEXT: s_xor_b32 s2, s3, s21021; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v01022; GFX9-NEXT: s_ashr_i32 s2, s2, 301023; GFX9-NEXT: s_lshr_b32 s4, s6, 81024; GFX9-NEXT: s_or_b32 s5, s2, 11025; GFX9-NEXT: v_mul_f32_e32 v2, v1, v21026; GFX9-NEXT: v_trunc_f32_e32 v2, v21027; GFX9-NEXT: v_mad_f32 v1, -v2, v0, v11028; GFX9-NEXT: v_cvt_i32_f32_e32 v2, v21029; GFX9-NEXT: v_cmp_ge_f32_e64 s[2:3], |v1|, |v0|1030; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec1031; GFX9-NEXT: s_cselect_b32 s2, s5, 01032; GFX9-NEXT: v_add_u32_e32 v0, s2, v21033; GFX9-NEXT: v_mul_lo_u32 v0, v0, s41034; GFX9-NEXT: v_mov_b32_e32 v1, 01035; GFX9-NEXT: v_sub_u32_e32 v0, s6, v01036; GFX9-NEXT: global_store_byte v1, v0, s[0:1]1037; GFX9-NEXT: s_endpgm1038 %r = srem i8 %x, %y1039 store i8 %r, ptr addrspace(1) %out1040 ret void1041}1042 1043define amdgpu_kernel void @udiv_v4i32(ptr addrspace(1) %out, <4 x i32> %x, <4 x i32> %y) {1044; CHECK-LABEL: @udiv_v4i32(1045; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i32> [[X:%.*]], i64 01046; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i32> [[Y:%.*]], i64 01047; CHECK-NEXT: [[TMP3:%.*]] = uitofp i32 [[TMP2]] to float1048; CHECK-NEXT: [[TMP4:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP3]])1049; CHECK-NEXT: [[TMP5:%.*]] = fmul fast float [[TMP4]], 0x41EFFFFFC00000001050; CHECK-NEXT: [[TMP6:%.*]] = fptoui float [[TMP5]] to i321051; CHECK-NEXT: [[TMP7:%.*]] = sub i32 0, [[TMP2]]1052; CHECK-NEXT: [[TMP8:%.*]] = mul i32 [[TMP7]], [[TMP6]]1053; CHECK-NEXT: [[TMP9:%.*]] = zext i32 [[TMP6]] to i641054; CHECK-NEXT: [[TMP10:%.*]] = zext i32 [[TMP8]] to i641055; CHECK-NEXT: [[TMP11:%.*]] = mul i64 [[TMP9]], [[TMP10]]1056; CHECK-NEXT: [[TMP12:%.*]] = trunc i64 [[TMP11]] to i321057; CHECK-NEXT: [[TMP13:%.*]] = lshr i64 [[TMP11]], 321058; CHECK-NEXT: [[TMP14:%.*]] = trunc i64 [[TMP13]] to i321059; CHECK-NEXT: [[TMP15:%.*]] = add i32 [[TMP6]], [[TMP14]]1060; CHECK-NEXT: [[TMP16:%.*]] = zext i32 [[TMP1]] to i641061; CHECK-NEXT: [[TMP17:%.*]] = zext i32 [[TMP15]] to i641062; CHECK-NEXT: [[TMP18:%.*]] = mul i64 [[TMP16]], [[TMP17]]1063; CHECK-NEXT: [[TMP19:%.*]] = trunc i64 [[TMP18]] to i321064; CHECK-NEXT: [[TMP20:%.*]] = lshr i64 [[TMP18]], 321065; CHECK-NEXT: [[TMP21:%.*]] = trunc i64 [[TMP20]] to i321066; CHECK-NEXT: [[TMP22:%.*]] = mul i32 [[TMP21]], [[TMP2]]1067; CHECK-NEXT: [[TMP23:%.*]] = sub i32 [[TMP1]], [[TMP22]]1068; CHECK-NEXT: [[TMP24:%.*]] = icmp uge i32 [[TMP23]], [[TMP2]]1069; CHECK-NEXT: [[TMP25:%.*]] = add i32 [[TMP21]], 11070; CHECK-NEXT: [[TMP26:%.*]] = select i1 [[TMP24]], i32 [[TMP25]], i32 [[TMP21]]1071; CHECK-NEXT: [[TMP27:%.*]] = sub i32 [[TMP23]], [[TMP2]]1072; CHECK-NEXT: [[TMP28:%.*]] = select i1 [[TMP24]], i32 [[TMP27]], i32 [[TMP23]]1073; CHECK-NEXT: [[TMP29:%.*]] = icmp uge i32 [[TMP28]], [[TMP2]]1074; CHECK-NEXT: [[TMP30:%.*]] = add i32 [[TMP26]], 11075; CHECK-NEXT: [[TMP31:%.*]] = select i1 [[TMP29]], i32 [[TMP30]], i32 [[TMP26]]1076; CHECK-NEXT: [[TMP32:%.*]] = insertelement <4 x i32> poison, i32 [[TMP31]], i64 01077; CHECK-NEXT: [[TMP33:%.*]] = extractelement <4 x i32> [[X]], i64 11078; CHECK-NEXT: [[TMP34:%.*]] = extractelement <4 x i32> [[Y]], i64 11079; CHECK-NEXT: [[TMP35:%.*]] = uitofp i32 [[TMP34]] to float1080; CHECK-NEXT: [[TMP36:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP35]])1081; CHECK-NEXT: [[TMP37:%.*]] = fmul fast float [[TMP36]], 0x41EFFFFFC00000001082; CHECK-NEXT: [[TMP38:%.*]] = fptoui float [[TMP37]] to i321083; CHECK-NEXT: [[TMP39:%.*]] = sub i32 0, [[TMP34]]1084; CHECK-NEXT: [[TMP40:%.*]] = mul i32 [[TMP39]], [[TMP38]]1085; CHECK-NEXT: [[TMP41:%.*]] = zext i32 [[TMP38]] to i641086; CHECK-NEXT: [[TMP42:%.*]] = zext i32 [[TMP40]] to i641087; CHECK-NEXT: [[TMP43:%.*]] = mul i64 [[TMP41]], [[TMP42]]1088; CHECK-NEXT: [[TMP44:%.*]] = trunc i64 [[TMP43]] to i321089; CHECK-NEXT: [[TMP45:%.*]] = lshr i64 [[TMP43]], 321090; CHECK-NEXT: [[TMP46:%.*]] = trunc i64 [[TMP45]] to i321091; CHECK-NEXT: [[TMP47:%.*]] = add i32 [[TMP38]], [[TMP46]]1092; CHECK-NEXT: [[TMP48:%.*]] = zext i32 [[TMP33]] to i641093; CHECK-NEXT: [[TMP49:%.*]] = zext i32 [[TMP47]] to i641094; CHECK-NEXT: [[TMP50:%.*]] = mul i64 [[TMP48]], [[TMP49]]1095; CHECK-NEXT: [[TMP51:%.*]] = trunc i64 [[TMP50]] to i321096; CHECK-NEXT: [[TMP52:%.*]] = lshr i64 [[TMP50]], 321097; CHECK-NEXT: [[TMP53:%.*]] = trunc i64 [[TMP52]] to i321098; CHECK-NEXT: [[TMP54:%.*]] = mul i32 [[TMP53]], [[TMP34]]1099; CHECK-NEXT: [[TMP55:%.*]] = sub i32 [[TMP33]], [[TMP54]]1100; CHECK-NEXT: [[TMP56:%.*]] = icmp uge i32 [[TMP55]], [[TMP34]]1101; CHECK-NEXT: [[TMP57:%.*]] = add i32 [[TMP53]], 11102; CHECK-NEXT: [[TMP58:%.*]] = select i1 [[TMP56]], i32 [[TMP57]], i32 [[TMP53]]1103; CHECK-NEXT: [[TMP59:%.*]] = sub i32 [[TMP55]], [[TMP34]]1104; CHECK-NEXT: [[TMP60:%.*]] = select i1 [[TMP56]], i32 [[TMP59]], i32 [[TMP55]]1105; CHECK-NEXT: [[TMP61:%.*]] = icmp uge i32 [[TMP60]], [[TMP34]]1106; CHECK-NEXT: [[TMP62:%.*]] = add i32 [[TMP58]], 11107; CHECK-NEXT: [[TMP63:%.*]] = select i1 [[TMP61]], i32 [[TMP62]], i32 [[TMP58]]1108; CHECK-NEXT: [[TMP64:%.*]] = insertelement <4 x i32> [[TMP32]], i32 [[TMP63]], i64 11109; CHECK-NEXT: [[TMP65:%.*]] = extractelement <4 x i32> [[X]], i64 21110; CHECK-NEXT: [[TMP66:%.*]] = extractelement <4 x i32> [[Y]], i64 21111; CHECK-NEXT: [[TMP67:%.*]] = uitofp i32 [[TMP66]] to float1112; CHECK-NEXT: [[TMP68:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP67]])1113; CHECK-NEXT: [[TMP69:%.*]] = fmul fast float [[TMP68]], 0x41EFFFFFC00000001114; CHECK-NEXT: [[TMP70:%.*]] = fptoui float [[TMP69]] to i321115; CHECK-NEXT: [[TMP71:%.*]] = sub i32 0, [[TMP66]]1116; CHECK-NEXT: [[TMP72:%.*]] = mul i32 [[TMP71]], [[TMP70]]1117; CHECK-NEXT: [[TMP73:%.*]] = zext i32 [[TMP70]] to i641118; CHECK-NEXT: [[TMP74:%.*]] = zext i32 [[TMP72]] to i641119; CHECK-NEXT: [[TMP75:%.*]] = mul i64 [[TMP73]], [[TMP74]]1120; CHECK-NEXT: [[TMP76:%.*]] = trunc i64 [[TMP75]] to i321121; CHECK-NEXT: [[TMP77:%.*]] = lshr i64 [[TMP75]], 321122; CHECK-NEXT: [[TMP78:%.*]] = trunc i64 [[TMP77]] to i321123; CHECK-NEXT: [[TMP79:%.*]] = add i32 [[TMP70]], [[TMP78]]1124; CHECK-NEXT: [[TMP80:%.*]] = zext i32 [[TMP65]] to i641125; CHECK-NEXT: [[TMP81:%.*]] = zext i32 [[TMP79]] to i641126; CHECK-NEXT: [[TMP82:%.*]] = mul i64 [[TMP80]], [[TMP81]]1127; CHECK-NEXT: [[TMP83:%.*]] = trunc i64 [[TMP82]] to i321128; CHECK-NEXT: [[TMP84:%.*]] = lshr i64 [[TMP82]], 321129; CHECK-NEXT: [[TMP85:%.*]] = trunc i64 [[TMP84]] to i321130; CHECK-NEXT: [[TMP86:%.*]] = mul i32 [[TMP85]], [[TMP66]]1131; CHECK-NEXT: [[TMP87:%.*]] = sub i32 [[TMP65]], [[TMP86]]1132; CHECK-NEXT: [[TMP88:%.*]] = icmp uge i32 [[TMP87]], [[TMP66]]1133; CHECK-NEXT: [[TMP89:%.*]] = add i32 [[TMP85]], 11134; CHECK-NEXT: [[TMP90:%.*]] = select i1 [[TMP88]], i32 [[TMP89]], i32 [[TMP85]]1135; CHECK-NEXT: [[TMP91:%.*]] = sub i32 [[TMP87]], [[TMP66]]1136; CHECK-NEXT: [[TMP92:%.*]] = select i1 [[TMP88]], i32 [[TMP91]], i32 [[TMP87]]1137; CHECK-NEXT: [[TMP93:%.*]] = icmp uge i32 [[TMP92]], [[TMP66]]1138; CHECK-NEXT: [[TMP94:%.*]] = add i32 [[TMP90]], 11139; CHECK-NEXT: [[TMP95:%.*]] = select i1 [[TMP93]], i32 [[TMP94]], i32 [[TMP90]]1140; CHECK-NEXT: [[TMP96:%.*]] = insertelement <4 x i32> [[TMP64]], i32 [[TMP95]], i64 21141; CHECK-NEXT: [[TMP97:%.*]] = extractelement <4 x i32> [[X]], i64 31142; CHECK-NEXT: [[TMP98:%.*]] = extractelement <4 x i32> [[Y]], i64 31143; CHECK-NEXT: [[TMP99:%.*]] = uitofp i32 [[TMP98]] to float1144; CHECK-NEXT: [[TMP100:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP99]])1145; CHECK-NEXT: [[TMP101:%.*]] = fmul fast float [[TMP100]], 0x41EFFFFFC00000001146; CHECK-NEXT: [[TMP102:%.*]] = fptoui float [[TMP101]] to i321147; CHECK-NEXT: [[TMP103:%.*]] = sub i32 0, [[TMP98]]1148; CHECK-NEXT: [[TMP104:%.*]] = mul i32 [[TMP103]], [[TMP102]]1149; CHECK-NEXT: [[TMP105:%.*]] = zext i32 [[TMP102]] to i641150; CHECK-NEXT: [[TMP106:%.*]] = zext i32 [[TMP104]] to i641151; CHECK-NEXT: [[TMP107:%.*]] = mul i64 [[TMP105]], [[TMP106]]1152; CHECK-NEXT: [[TMP108:%.*]] = trunc i64 [[TMP107]] to i321153; CHECK-NEXT: [[TMP109:%.*]] = lshr i64 [[TMP107]], 321154; CHECK-NEXT: [[TMP110:%.*]] = trunc i64 [[TMP109]] to i321155; CHECK-NEXT: [[TMP111:%.*]] = add i32 [[TMP102]], [[TMP110]]1156; CHECK-NEXT: [[TMP112:%.*]] = zext i32 [[TMP97]] to i641157; CHECK-NEXT: [[TMP113:%.*]] = zext i32 [[TMP111]] to i641158; CHECK-NEXT: [[TMP114:%.*]] = mul i64 [[TMP112]], [[TMP113]]1159; CHECK-NEXT: [[TMP115:%.*]] = trunc i64 [[TMP114]] to i321160; CHECK-NEXT: [[TMP116:%.*]] = lshr i64 [[TMP114]], 321161; CHECK-NEXT: [[TMP117:%.*]] = trunc i64 [[TMP116]] to i321162; CHECK-NEXT: [[TMP118:%.*]] = mul i32 [[TMP117]], [[TMP98]]1163; CHECK-NEXT: [[TMP119:%.*]] = sub i32 [[TMP97]], [[TMP118]]1164; CHECK-NEXT: [[TMP120:%.*]] = icmp uge i32 [[TMP119]], [[TMP98]]1165; CHECK-NEXT: [[TMP121:%.*]] = add i32 [[TMP117]], 11166; CHECK-NEXT: [[TMP122:%.*]] = select i1 [[TMP120]], i32 [[TMP121]], i32 [[TMP117]]1167; CHECK-NEXT: [[TMP123:%.*]] = sub i32 [[TMP119]], [[TMP98]]1168; CHECK-NEXT: [[TMP124:%.*]] = select i1 [[TMP120]], i32 [[TMP123]], i32 [[TMP119]]1169; CHECK-NEXT: [[TMP125:%.*]] = icmp uge i32 [[TMP124]], [[TMP98]]1170; CHECK-NEXT: [[TMP126:%.*]] = add i32 [[TMP122]], 11171; CHECK-NEXT: [[TMP127:%.*]] = select i1 [[TMP125]], i32 [[TMP126]], i32 [[TMP122]]1172; CHECK-NEXT: [[TMP128:%.*]] = insertelement <4 x i32> [[TMP96]], i32 [[TMP127]], i64 31173; CHECK-NEXT: store <4 x i32> [[TMP128]], ptr addrspace(1) [[OUT:%.*]], align 161174; CHECK-NEXT: ret void1175;1176; GFX6-LABEL: udiv_v4i32:1177; GFX6: ; %bb.0:1178; GFX6-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0xd1179; GFX6-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x91180; GFX6-NEXT: s_mov_b32 s19, 0xf0001181; GFX6-NEXT: s_mov_b32 s18, -11182; GFX6-NEXT: s_waitcnt lgkmcnt(0)1183; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s121184; GFX6-NEXT: s_sub_i32 s0, 0, s121185; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s131186; GFX6-NEXT: v_cvt_f32_u32_e32 v4, s141187; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v01188; GFX6-NEXT: v_cvt_f32_u32_e32 v6, s151189; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v21190; GFX6-NEXT: v_rcp_iflag_f32_e32 v4, v41191; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v01192; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v01193; GFX6-NEXT: v_rcp_iflag_f32_e32 v6, v61194; GFX6-NEXT: v_mul_lo_u32 v1, s0, v01195; GFX6-NEXT: v_mul_hi_u32 v1, v0, v11196; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v11197; GFX6-NEXT: v_mul_hi_u32 v0, s8, v01198; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v21199; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v11200; GFX6-NEXT: v_readfirstlane_b32 s0, v01201; GFX6-NEXT: s_mul_i32 s0, s0, s121202; GFX6-NEXT: s_sub_i32 s0, s8, s01203; GFX6-NEXT: s_sub_i32 s1, s0, s121204; GFX6-NEXT: s_cmp_ge_u32 s0, s121205; GFX6-NEXT: v_add_i32_e32 v2, vcc, 1, v01206; GFX6-NEXT: s_cselect_b32 s0, s1, s01207; GFX6-NEXT: s_cselect_b64 vcc, -1, 01208; GFX6-NEXT: s_cmp_ge_u32 s0, s121209; GFX6-NEXT: s_cselect_b64 s[0:1], -1, 01210; GFX6-NEXT: s_sub_i32 s2, 0, s131211; GFX6-NEXT: v_mul_lo_u32 v3, s2, v11212; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc1213; GFX6-NEXT: v_add_i32_e32 v2, vcc, 1, v01214; GFX6-NEXT: v_mul_hi_u32 v3, v1, v31215; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]1216; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v31217; GFX6-NEXT: v_mul_hi_u32 v1, s9, v11218; GFX6-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v41219; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v31220; GFX6-NEXT: v_readfirstlane_b32 s2, v11221; GFX6-NEXT: s_mul_i32 s2, s2, s131222; GFX6-NEXT: s_sub_i32 s2, s9, s21223; GFX6-NEXT: s_sub_i32 s3, s2, s131224; GFX6-NEXT: s_cmp_ge_u32 s2, s131225; GFX6-NEXT: v_add_i32_e32 v4, vcc, 1, v11226; GFX6-NEXT: s_cselect_b32 s2, s3, s21227; GFX6-NEXT: s_cselect_b64 vcc, -1, 01228; GFX6-NEXT: s_cmp_ge_u32 s2, s131229; GFX6-NEXT: s_cselect_b64 s[2:3], -1, 01230; GFX6-NEXT: s_sub_i32 s6, 0, s141231; GFX6-NEXT: v_mul_lo_u32 v5, s6, v31232; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc1233; GFX6-NEXT: v_add_i32_e32 v4, vcc, 1, v11234; GFX6-NEXT: v_mul_hi_u32 v5, v3, v51235; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, v4, s[2:3]1236; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v51237; GFX6-NEXT: v_mul_hi_u32 v3, s10, v31238; GFX6-NEXT: v_mul_f32_e32 v5, 0x4f7ffffe, v61239; GFX6-NEXT: v_cvt_u32_f32_e32 v5, v51240; GFX6-NEXT: v_readfirstlane_b32 s6, v31241; GFX6-NEXT: s_mul_i32 s6, s6, s141242; GFX6-NEXT: s_sub_i32 s6, s10, s61243; GFX6-NEXT: s_sub_i32 s7, s6, s141244; GFX6-NEXT: s_cmp_ge_u32 s6, s141245; GFX6-NEXT: v_add_i32_e32 v6, vcc, 1, v31246; GFX6-NEXT: s_cselect_b32 s6, s7, s61247; GFX6-NEXT: s_cselect_b64 vcc, -1, 01248; GFX6-NEXT: s_cmp_ge_u32 s6, s141249; GFX6-NEXT: s_cselect_b64 s[6:7], -1, 01250; GFX6-NEXT: s_sub_i32 s8, 0, s151251; GFX6-NEXT: v_mul_lo_u32 v7, s8, v51252; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc1253; GFX6-NEXT: v_add_i32_e32 v6, vcc, 1, v31254; GFX6-NEXT: v_mul_hi_u32 v7, v5, v71255; GFX6-NEXT: v_cndmask_b32_e64 v2, v3, v6, s[6:7]1256; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v71257; GFX6-NEXT: v_mul_hi_u32 v5, s11, v51258; GFX6-NEXT: v_readfirstlane_b32 s0, v51259; GFX6-NEXT: s_mul_i32 s0, s0, s151260; GFX6-NEXT: s_sub_i32 s0, s11, s01261; GFX6-NEXT: s_sub_i32 s1, s0, s151262; GFX6-NEXT: v_add_i32_e32 v3, vcc, 1, v51263; GFX6-NEXT: s_cmp_ge_u32 s0, s151264; GFX6-NEXT: s_cselect_b64 vcc, -1, 01265; GFX6-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc1266; GFX6-NEXT: s_cselect_b32 s0, s1, s01267; GFX6-NEXT: v_add_i32_e32 v4, vcc, 1, v31268; GFX6-NEXT: s_cmp_ge_u32 s0, s151269; GFX6-NEXT: s_cselect_b64 vcc, -1, 01270; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc1271; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 01272; GFX6-NEXT: s_endpgm1273;1274; GFX9-LABEL: udiv_v4i32:1275; GFX9: ; %bb.0:1276; GFX9-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x341277; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241278; GFX9-NEXT: v_mov_b32_e32 v4, 01279; GFX9-NEXT: s_waitcnt lgkmcnt(0)1280; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s121281; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s131282; GFX9-NEXT: s_sub_i32 s2, 0, s121283; GFX9-NEXT: v_cvt_f32_u32_e32 v2, s141284; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v01285; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v11286; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v01287; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v01288; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v11289; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v11290; GFX9-NEXT: v_readfirstlane_b32 s3, v01291; GFX9-NEXT: s_mul_i32 s2, s2, s31292; GFX9-NEXT: s_mul_hi_u32 s2, s3, s21293; GFX9-NEXT: s_add_i32 s3, s3, s21294; GFX9-NEXT: s_mul_hi_u32 s2, s8, s31295; GFX9-NEXT: s_mul_i32 s3, s2, s121296; GFX9-NEXT: s_sub_i32 s3, s8, s31297; GFX9-NEXT: s_add_i32 s5, s2, 11298; GFX9-NEXT: s_sub_i32 s6, s3, s121299; GFX9-NEXT: s_cmp_ge_u32 s3, s121300; GFX9-NEXT: s_cselect_b32 s2, s5, s21301; GFX9-NEXT: s_cselect_b32 s3, s6, s31302; GFX9-NEXT: s_add_i32 s5, s2, 11303; GFX9-NEXT: s_cmp_ge_u32 s3, s121304; GFX9-NEXT: v_readfirstlane_b32 s4, v11305; GFX9-NEXT: s_cselect_b32 s2, s5, s21306; GFX9-NEXT: s_sub_i32 s3, 0, s131307; GFX9-NEXT: s_mul_i32 s3, s3, s41308; GFX9-NEXT: s_mul_hi_u32 s3, s4, s31309; GFX9-NEXT: s_add_i32 s4, s4, s31310; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v21311; GFX9-NEXT: s_mul_hi_u32 s3, s9, s41312; GFX9-NEXT: s_mul_i32 s4, s3, s131313; GFX9-NEXT: s_sub_i32 s4, s9, s41314; GFX9-NEXT: s_add_i32 s5, s3, 11315; GFX9-NEXT: s_sub_i32 s6, s4, s131316; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v01317; GFX9-NEXT: s_cmp_ge_u32 s4, s131318; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v01319; GFX9-NEXT: s_cselect_b32 s3, s5, s31320; GFX9-NEXT: s_cselect_b32 s4, s6, s41321; GFX9-NEXT: s_add_i32 s5, s3, 11322; GFX9-NEXT: s_cmp_ge_u32 s4, s131323; GFX9-NEXT: s_cselect_b32 s3, s5, s31324; GFX9-NEXT: v_readfirstlane_b32 s5, v01325; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s151326; GFX9-NEXT: s_sub_i32 s4, 0, s141327; GFX9-NEXT: s_mul_i32 s4, s4, s51328; GFX9-NEXT: s_mul_hi_u32 s4, s5, s41329; GFX9-NEXT: s_add_i32 s5, s5, s41330; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v01331; GFX9-NEXT: s_mul_hi_u32 s4, s10, s51332; GFX9-NEXT: s_mul_i32 s5, s4, s141333; GFX9-NEXT: s_sub_i32 s5, s10, s51334; GFX9-NEXT: s_add_i32 s6, s4, 11335; GFX9-NEXT: s_sub_i32 s7, s5, s141336; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v01337; GFX9-NEXT: s_cmp_ge_u32 s5, s141338; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v01339; GFX9-NEXT: s_cselect_b32 s4, s6, s41340; GFX9-NEXT: s_cselect_b32 s5, s7, s51341; GFX9-NEXT: s_add_i32 s6, s4, 11342; GFX9-NEXT: s_cmp_ge_u32 s5, s141343; GFX9-NEXT: s_cselect_b32 s4, s6, s41344; GFX9-NEXT: s_sub_i32 s5, 0, s151345; GFX9-NEXT: v_readfirstlane_b32 s6, v01346; GFX9-NEXT: s_mul_i32 s5, s5, s61347; GFX9-NEXT: s_mul_hi_u32 s5, s6, s51348; GFX9-NEXT: s_add_i32 s6, s6, s51349; GFX9-NEXT: s_mul_hi_u32 s5, s11, s61350; GFX9-NEXT: s_mul_i32 s6, s5, s151351; GFX9-NEXT: s_sub_i32 s6, s11, s61352; GFX9-NEXT: s_add_i32 s7, s5, 11353; GFX9-NEXT: s_sub_i32 s8, s6, s151354; GFX9-NEXT: s_cmp_ge_u32 s6, s151355; GFX9-NEXT: s_cselect_b32 s5, s7, s51356; GFX9-NEXT: s_cselect_b32 s6, s8, s61357; GFX9-NEXT: s_add_i32 s7, s5, 11358; GFX9-NEXT: s_cmp_ge_u32 s6, s151359; GFX9-NEXT: s_cselect_b32 s5, s7, s51360; GFX9-NEXT: v_mov_b32_e32 v0, s21361; GFX9-NEXT: v_mov_b32_e32 v1, s31362; GFX9-NEXT: v_mov_b32_e32 v2, s41363; GFX9-NEXT: v_mov_b32_e32 v3, s51364; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]1365; GFX9-NEXT: s_endpgm1366 %r = udiv <4 x i32> %x, %y1367 store <4 x i32> %r, ptr addrspace(1) %out1368 ret void1369}1370 1371define amdgpu_kernel void @urem_v4i32(ptr addrspace(1) %out, <4 x i32> %x, <4 x i32> %y) {1372; CHECK-LABEL: @urem_v4i32(1373; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i32> [[X:%.*]], i64 01374; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i32> [[Y:%.*]], i64 01375; CHECK-NEXT: [[TMP3:%.*]] = uitofp i32 [[TMP2]] to float1376; CHECK-NEXT: [[TMP4:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP3]])1377; CHECK-NEXT: [[TMP5:%.*]] = fmul fast float [[TMP4]], 0x41EFFFFFC00000001378; CHECK-NEXT: [[TMP6:%.*]] = fptoui float [[TMP5]] to i321379; CHECK-NEXT: [[TMP7:%.*]] = sub i32 0, [[TMP2]]1380; CHECK-NEXT: [[TMP8:%.*]] = mul i32 [[TMP7]], [[TMP6]]1381; CHECK-NEXT: [[TMP9:%.*]] = zext i32 [[TMP6]] to i641382; CHECK-NEXT: [[TMP10:%.*]] = zext i32 [[TMP8]] to i641383; CHECK-NEXT: [[TMP11:%.*]] = mul i64 [[TMP9]], [[TMP10]]1384; CHECK-NEXT: [[TMP12:%.*]] = trunc i64 [[TMP11]] to i321385; CHECK-NEXT: [[TMP13:%.*]] = lshr i64 [[TMP11]], 321386; CHECK-NEXT: [[TMP14:%.*]] = trunc i64 [[TMP13]] to i321387; CHECK-NEXT: [[TMP15:%.*]] = add i32 [[TMP6]], [[TMP14]]1388; CHECK-NEXT: [[TMP16:%.*]] = zext i32 [[TMP1]] to i641389; CHECK-NEXT: [[TMP17:%.*]] = zext i32 [[TMP15]] to i641390; CHECK-NEXT: [[TMP18:%.*]] = mul i64 [[TMP16]], [[TMP17]]1391; CHECK-NEXT: [[TMP19:%.*]] = trunc i64 [[TMP18]] to i321392; CHECK-NEXT: [[TMP20:%.*]] = lshr i64 [[TMP18]], 321393; CHECK-NEXT: [[TMP21:%.*]] = trunc i64 [[TMP20]] to i321394; CHECK-NEXT: [[TMP22:%.*]] = mul i32 [[TMP21]], [[TMP2]]1395; CHECK-NEXT: [[TMP23:%.*]] = sub i32 [[TMP1]], [[TMP22]]1396; CHECK-NEXT: [[TMP24:%.*]] = icmp uge i32 [[TMP23]], [[TMP2]]1397; CHECK-NEXT: [[TMP25:%.*]] = sub i32 [[TMP23]], [[TMP2]]1398; CHECK-NEXT: [[TMP26:%.*]] = select i1 [[TMP24]], i32 [[TMP25]], i32 [[TMP23]]1399; CHECK-NEXT: [[TMP27:%.*]] = icmp uge i32 [[TMP26]], [[TMP2]]1400; CHECK-NEXT: [[TMP28:%.*]] = sub i32 [[TMP26]], [[TMP2]]1401; CHECK-NEXT: [[TMP29:%.*]] = select i1 [[TMP27]], i32 [[TMP28]], i32 [[TMP26]]1402; CHECK-NEXT: [[TMP30:%.*]] = insertelement <4 x i32> poison, i32 [[TMP29]], i64 01403; CHECK-NEXT: [[TMP31:%.*]] = extractelement <4 x i32> [[X]], i64 11404; CHECK-NEXT: [[TMP32:%.*]] = extractelement <4 x i32> [[Y]], i64 11405; CHECK-NEXT: [[TMP33:%.*]] = uitofp i32 [[TMP32]] to float1406; CHECK-NEXT: [[TMP34:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP33]])1407; CHECK-NEXT: [[TMP35:%.*]] = fmul fast float [[TMP34]], 0x41EFFFFFC00000001408; CHECK-NEXT: [[TMP36:%.*]] = fptoui float [[TMP35]] to i321409; CHECK-NEXT: [[TMP37:%.*]] = sub i32 0, [[TMP32]]1410; CHECK-NEXT: [[TMP38:%.*]] = mul i32 [[TMP37]], [[TMP36]]1411; CHECK-NEXT: [[TMP39:%.*]] = zext i32 [[TMP36]] to i641412; CHECK-NEXT: [[TMP40:%.*]] = zext i32 [[TMP38]] to i641413; CHECK-NEXT: [[TMP41:%.*]] = mul i64 [[TMP39]], [[TMP40]]1414; CHECK-NEXT: [[TMP42:%.*]] = trunc i64 [[TMP41]] to i321415; CHECK-NEXT: [[TMP43:%.*]] = lshr i64 [[TMP41]], 321416; CHECK-NEXT: [[TMP44:%.*]] = trunc i64 [[TMP43]] to i321417; CHECK-NEXT: [[TMP45:%.*]] = add i32 [[TMP36]], [[TMP44]]1418; CHECK-NEXT: [[TMP46:%.*]] = zext i32 [[TMP31]] to i641419; CHECK-NEXT: [[TMP47:%.*]] = zext i32 [[TMP45]] to i641420; CHECK-NEXT: [[TMP48:%.*]] = mul i64 [[TMP46]], [[TMP47]]1421; CHECK-NEXT: [[TMP49:%.*]] = trunc i64 [[TMP48]] to i321422; CHECK-NEXT: [[TMP50:%.*]] = lshr i64 [[TMP48]], 321423; CHECK-NEXT: [[TMP51:%.*]] = trunc i64 [[TMP50]] to i321424; CHECK-NEXT: [[TMP52:%.*]] = mul i32 [[TMP51]], [[TMP32]]1425; CHECK-NEXT: [[TMP53:%.*]] = sub i32 [[TMP31]], [[TMP52]]1426; CHECK-NEXT: [[TMP54:%.*]] = icmp uge i32 [[TMP53]], [[TMP32]]1427; CHECK-NEXT: [[TMP55:%.*]] = sub i32 [[TMP53]], [[TMP32]]1428; CHECK-NEXT: [[TMP56:%.*]] = select i1 [[TMP54]], i32 [[TMP55]], i32 [[TMP53]]1429; CHECK-NEXT: [[TMP57:%.*]] = icmp uge i32 [[TMP56]], [[TMP32]]1430; CHECK-NEXT: [[TMP58:%.*]] = sub i32 [[TMP56]], [[TMP32]]1431; CHECK-NEXT: [[TMP59:%.*]] = select i1 [[TMP57]], i32 [[TMP58]], i32 [[TMP56]]1432; CHECK-NEXT: [[TMP60:%.*]] = insertelement <4 x i32> [[TMP30]], i32 [[TMP59]], i64 11433; CHECK-NEXT: [[TMP61:%.*]] = extractelement <4 x i32> [[X]], i64 21434; CHECK-NEXT: [[TMP62:%.*]] = extractelement <4 x i32> [[Y]], i64 21435; CHECK-NEXT: [[TMP63:%.*]] = uitofp i32 [[TMP62]] to float1436; CHECK-NEXT: [[TMP64:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP63]])1437; CHECK-NEXT: [[TMP65:%.*]] = fmul fast float [[TMP64]], 0x41EFFFFFC00000001438; CHECK-NEXT: [[TMP66:%.*]] = fptoui float [[TMP65]] to i321439; CHECK-NEXT: [[TMP67:%.*]] = sub i32 0, [[TMP62]]1440; CHECK-NEXT: [[TMP68:%.*]] = mul i32 [[TMP67]], [[TMP66]]1441; CHECK-NEXT: [[TMP69:%.*]] = zext i32 [[TMP66]] to i641442; CHECK-NEXT: [[TMP70:%.*]] = zext i32 [[TMP68]] to i641443; CHECK-NEXT: [[TMP71:%.*]] = mul i64 [[TMP69]], [[TMP70]]1444; CHECK-NEXT: [[TMP72:%.*]] = trunc i64 [[TMP71]] to i321445; CHECK-NEXT: [[TMP73:%.*]] = lshr i64 [[TMP71]], 321446; CHECK-NEXT: [[TMP74:%.*]] = trunc i64 [[TMP73]] to i321447; CHECK-NEXT: [[TMP75:%.*]] = add i32 [[TMP66]], [[TMP74]]1448; CHECK-NEXT: [[TMP76:%.*]] = zext i32 [[TMP61]] to i641449; CHECK-NEXT: [[TMP77:%.*]] = zext i32 [[TMP75]] to i641450; CHECK-NEXT: [[TMP78:%.*]] = mul i64 [[TMP76]], [[TMP77]]1451; CHECK-NEXT: [[TMP79:%.*]] = trunc i64 [[TMP78]] to i321452; CHECK-NEXT: [[TMP80:%.*]] = lshr i64 [[TMP78]], 321453; CHECK-NEXT: [[TMP81:%.*]] = trunc i64 [[TMP80]] to i321454; CHECK-NEXT: [[TMP82:%.*]] = mul i32 [[TMP81]], [[TMP62]]1455; CHECK-NEXT: [[TMP83:%.*]] = sub i32 [[TMP61]], [[TMP82]]1456; CHECK-NEXT: [[TMP84:%.*]] = icmp uge i32 [[TMP83]], [[TMP62]]1457; CHECK-NEXT: [[TMP85:%.*]] = sub i32 [[TMP83]], [[TMP62]]1458; CHECK-NEXT: [[TMP86:%.*]] = select i1 [[TMP84]], i32 [[TMP85]], i32 [[TMP83]]1459; CHECK-NEXT: [[TMP87:%.*]] = icmp uge i32 [[TMP86]], [[TMP62]]1460; CHECK-NEXT: [[TMP88:%.*]] = sub i32 [[TMP86]], [[TMP62]]1461; CHECK-NEXT: [[TMP89:%.*]] = select i1 [[TMP87]], i32 [[TMP88]], i32 [[TMP86]]1462; CHECK-NEXT: [[TMP90:%.*]] = insertelement <4 x i32> [[TMP60]], i32 [[TMP89]], i64 21463; CHECK-NEXT: [[TMP91:%.*]] = extractelement <4 x i32> [[X]], i64 31464; CHECK-NEXT: [[TMP92:%.*]] = extractelement <4 x i32> [[Y]], i64 31465; CHECK-NEXT: [[TMP93:%.*]] = uitofp i32 [[TMP92]] to float1466; CHECK-NEXT: [[TMP94:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP93]])1467; CHECK-NEXT: [[TMP95:%.*]] = fmul fast float [[TMP94]], 0x41EFFFFFC00000001468; CHECK-NEXT: [[TMP96:%.*]] = fptoui float [[TMP95]] to i321469; CHECK-NEXT: [[TMP97:%.*]] = sub i32 0, [[TMP92]]1470; CHECK-NEXT: [[TMP98:%.*]] = mul i32 [[TMP97]], [[TMP96]]1471; CHECK-NEXT: [[TMP99:%.*]] = zext i32 [[TMP96]] to i641472; CHECK-NEXT: [[TMP100:%.*]] = zext i32 [[TMP98]] to i641473; CHECK-NEXT: [[TMP101:%.*]] = mul i64 [[TMP99]], [[TMP100]]1474; CHECK-NEXT: [[TMP102:%.*]] = trunc i64 [[TMP101]] to i321475; CHECK-NEXT: [[TMP103:%.*]] = lshr i64 [[TMP101]], 321476; CHECK-NEXT: [[TMP104:%.*]] = trunc i64 [[TMP103]] to i321477; CHECK-NEXT: [[TMP105:%.*]] = add i32 [[TMP96]], [[TMP104]]1478; CHECK-NEXT: [[TMP106:%.*]] = zext i32 [[TMP91]] to i641479; CHECK-NEXT: [[TMP107:%.*]] = zext i32 [[TMP105]] to i641480; CHECK-NEXT: [[TMP108:%.*]] = mul i64 [[TMP106]], [[TMP107]]1481; CHECK-NEXT: [[TMP109:%.*]] = trunc i64 [[TMP108]] to i321482; CHECK-NEXT: [[TMP110:%.*]] = lshr i64 [[TMP108]], 321483; CHECK-NEXT: [[TMP111:%.*]] = trunc i64 [[TMP110]] to i321484; CHECK-NEXT: [[TMP112:%.*]] = mul i32 [[TMP111]], [[TMP92]]1485; CHECK-NEXT: [[TMP113:%.*]] = sub i32 [[TMP91]], [[TMP112]]1486; CHECK-NEXT: [[TMP114:%.*]] = icmp uge i32 [[TMP113]], [[TMP92]]1487; CHECK-NEXT: [[TMP115:%.*]] = sub i32 [[TMP113]], [[TMP92]]1488; CHECK-NEXT: [[TMP116:%.*]] = select i1 [[TMP114]], i32 [[TMP115]], i32 [[TMP113]]1489; CHECK-NEXT: [[TMP117:%.*]] = icmp uge i32 [[TMP116]], [[TMP92]]1490; CHECK-NEXT: [[TMP118:%.*]] = sub i32 [[TMP116]], [[TMP92]]1491; CHECK-NEXT: [[TMP119:%.*]] = select i1 [[TMP117]], i32 [[TMP118]], i32 [[TMP116]]1492; CHECK-NEXT: [[TMP120:%.*]] = insertelement <4 x i32> [[TMP90]], i32 [[TMP119]], i64 31493; CHECK-NEXT: store <4 x i32> [[TMP120]], ptr addrspace(1) [[OUT:%.*]], align 161494; CHECK-NEXT: ret void1495;1496; GFX6-LABEL: urem_v4i32:1497; GFX6: ; %bb.0:1498; GFX6-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0xd1499; GFX6-NEXT: s_mov_b32 s3, 0xf0001500; GFX6-NEXT: s_mov_b32 s2, -11501; GFX6-NEXT: s_waitcnt lgkmcnt(0)1502; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s121503; GFX6-NEXT: s_sub_i32 s0, 0, s121504; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s131505; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v01506; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v21507; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v01508; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v01509; GFX6-NEXT: v_mul_lo_u32 v1, s0, v01510; GFX6-NEXT: v_mul_hi_u32 v1, v0, v11511; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v11512; GFX6-NEXT: v_mul_hi_u32 v0, s8, v01513; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v21514; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v11515; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s141516; GFX6-NEXT: v_readfirstlane_b32 s0, v01517; GFX6-NEXT: s_mul_i32 s0, s0, s121518; GFX6-NEXT: s_sub_i32 s0, s8, s01519; GFX6-NEXT: s_sub_i32 s1, s0, s121520; GFX6-NEXT: s_cmp_ge_u32 s0, s121521; GFX6-NEXT: s_cselect_b32 s0, s1, s01522; GFX6-NEXT: s_sub_i32 s1, s0, s121523; GFX6-NEXT: s_cmp_ge_u32 s0, s121524; GFX6-NEXT: s_cselect_b32 s6, s1, s01525; GFX6-NEXT: s_sub_i32 s0, 0, s131526; GFX6-NEXT: v_mul_lo_u32 v0, s0, v11527; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v21528; GFX6-NEXT: v_mul_hi_u32 v0, v1, v01529; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v01530; GFX6-NEXT: v_mul_hi_u32 v0, s9, v01531; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v21532; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v11533; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s151534; GFX6-NEXT: v_readfirstlane_b32 s0, v01535; GFX6-NEXT: s_mul_i32 s0, s0, s131536; GFX6-NEXT: s_sub_i32 s0, s9, s01537; GFX6-NEXT: s_sub_i32 s1, s0, s131538; GFX6-NEXT: s_cmp_ge_u32 s0, s131539; GFX6-NEXT: s_cselect_b32 s0, s1, s01540; GFX6-NEXT: s_sub_i32 s1, s0, s131541; GFX6-NEXT: s_cmp_ge_u32 s0, s131542; GFX6-NEXT: s_cselect_b32 s7, s1, s01543; GFX6-NEXT: s_sub_i32 s0, 0, s141544; GFX6-NEXT: v_mul_lo_u32 v0, s0, v11545; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v21546; GFX6-NEXT: v_mul_hi_u32 v0, v1, v01547; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v01548; GFX6-NEXT: v_mul_hi_u32 v0, s10, v01549; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v21550; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v11551; GFX6-NEXT: v_readfirstlane_b32 s0, v01552; GFX6-NEXT: s_mul_i32 s0, s0, s141553; GFX6-NEXT: s_sub_i32 s0, s10, s01554; GFX6-NEXT: s_sub_i32 s1, s0, s141555; GFX6-NEXT: s_cmp_ge_u32 s0, s141556; GFX6-NEXT: s_cselect_b32 s0, s1, s01557; GFX6-NEXT: s_sub_i32 s1, s0, s141558; GFX6-NEXT: s_cmp_ge_u32 s0, s141559; GFX6-NEXT: s_cselect_b32 s8, s1, s01560; GFX6-NEXT: s_sub_i32 s0, 0, s151561; GFX6-NEXT: v_mul_lo_u32 v0, s0, v11562; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91563; GFX6-NEXT: v_mul_hi_u32 v0, v1, v01564; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v01565; GFX6-NEXT: v_mul_hi_u32 v2, s11, v01566; GFX6-NEXT: v_mov_b32_e32 v0, s61567; GFX6-NEXT: v_mov_b32_e32 v1, s71568; GFX6-NEXT: v_readfirstlane_b32 s4, v21569; GFX6-NEXT: s_mul_i32 s4, s4, s151570; GFX6-NEXT: s_sub_i32 s4, s11, s41571; GFX6-NEXT: s_sub_i32 s5, s4, s151572; GFX6-NEXT: s_cmp_ge_u32 s4, s151573; GFX6-NEXT: s_cselect_b32 s4, s5, s41574; GFX6-NEXT: s_sub_i32 s5, s4, s151575; GFX6-NEXT: s_cmp_ge_u32 s4, s151576; GFX6-NEXT: s_cselect_b32 s4, s5, s41577; GFX6-NEXT: v_mov_b32_e32 v2, s81578; GFX6-NEXT: v_mov_b32_e32 v3, s41579; GFX6-NEXT: s_waitcnt lgkmcnt(0)1580; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 01581; GFX6-NEXT: s_endpgm1582;1583; GFX9-LABEL: urem_v4i32:1584; GFX9: ; %bb.0:1585; GFX9-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x341586; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241587; GFX9-NEXT: v_mov_b32_e32 v4, 01588; GFX9-NEXT: s_waitcnt lgkmcnt(0)1589; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s121590; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s131591; GFX9-NEXT: s_sub_i32 s2, 0, s121592; GFX9-NEXT: v_cvt_f32_u32_e32 v2, s141593; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v01594; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v11595; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v21596; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v01597; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v01598; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v11599; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v11600; GFX9-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v21601; GFX9-NEXT: v_readfirstlane_b32 s3, v01602; GFX9-NEXT: s_mul_i32 s2, s2, s31603; GFX9-NEXT: s_mul_hi_u32 s2, s3, s21604; GFX9-NEXT: s_add_i32 s3, s3, s21605; GFX9-NEXT: s_mul_hi_u32 s2, s8, s31606; GFX9-NEXT: s_mul_i32 s2, s2, s121607; GFX9-NEXT: s_sub_i32 s2, s8, s21608; GFX9-NEXT: s_sub_i32 s3, s2, s121609; GFX9-NEXT: s_cmp_ge_u32 s2, s121610; GFX9-NEXT: s_cselect_b32 s2, s3, s21611; GFX9-NEXT: s_sub_i32 s3, s2, s121612; GFX9-NEXT: s_cmp_ge_u32 s2, s121613; GFX9-NEXT: v_readfirstlane_b32 s4, v11614; GFX9-NEXT: s_cselect_b32 s2, s3, s21615; GFX9-NEXT: s_sub_i32 s3, 0, s131616; GFX9-NEXT: s_mul_i32 s3, s3, s41617; GFX9-NEXT: s_mul_hi_u32 s3, s4, s31618; GFX9-NEXT: s_add_i32 s4, s4, s31619; GFX9-NEXT: s_mul_hi_u32 s3, s9, s41620; GFX9-NEXT: s_mul_i32 s3, s3, s131621; GFX9-NEXT: s_sub_i32 s3, s9, s31622; GFX9-NEXT: s_sub_i32 s4, s3, s131623; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v21624; GFX9-NEXT: s_cmp_ge_u32 s3, s131625; GFX9-NEXT: s_cselect_b32 s3, s4, s31626; GFX9-NEXT: s_sub_i32 s4, s3, s131627; GFX9-NEXT: s_cmp_ge_u32 s3, s131628; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s151629; GFX9-NEXT: s_cselect_b32 s3, s4, s31630; GFX9-NEXT: s_sub_i32 s4, 0, s141631; GFX9-NEXT: v_readfirstlane_b32 s5, v21632; GFX9-NEXT: s_mul_i32 s4, s4, s51633; GFX9-NEXT: s_mul_hi_u32 s4, s5, s41634; GFX9-NEXT: s_add_i32 s5, s5, s41635; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v01636; GFX9-NEXT: s_mul_hi_u32 s4, s10, s51637; GFX9-NEXT: s_mul_i32 s4, s4, s141638; GFX9-NEXT: s_sub_i32 s4, s10, s41639; GFX9-NEXT: s_sub_i32 s5, s4, s141640; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v01641; GFX9-NEXT: s_cmp_ge_u32 s4, s141642; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v01643; GFX9-NEXT: s_cselect_b32 s4, s5, s41644; GFX9-NEXT: s_sub_i32 s5, s4, s141645; GFX9-NEXT: s_cmp_ge_u32 s4, s141646; GFX9-NEXT: s_cselect_b32 s4, s5, s41647; GFX9-NEXT: s_sub_i32 s5, 0, s151648; GFX9-NEXT: v_readfirstlane_b32 s6, v01649; GFX9-NEXT: s_mul_i32 s5, s5, s61650; GFX9-NEXT: s_mul_hi_u32 s5, s6, s51651; GFX9-NEXT: s_add_i32 s6, s6, s51652; GFX9-NEXT: s_mul_hi_u32 s5, s11, s61653; GFX9-NEXT: s_mul_i32 s5, s5, s151654; GFX9-NEXT: s_sub_i32 s5, s11, s51655; GFX9-NEXT: s_sub_i32 s6, s5, s151656; GFX9-NEXT: s_cmp_ge_u32 s5, s151657; GFX9-NEXT: s_cselect_b32 s5, s6, s51658; GFX9-NEXT: s_sub_i32 s6, s5, s151659; GFX9-NEXT: s_cmp_ge_u32 s5, s151660; GFX9-NEXT: s_cselect_b32 s5, s6, s51661; GFX9-NEXT: v_mov_b32_e32 v0, s21662; GFX9-NEXT: v_mov_b32_e32 v1, s31663; GFX9-NEXT: v_mov_b32_e32 v2, s41664; GFX9-NEXT: v_mov_b32_e32 v3, s51665; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]1666; GFX9-NEXT: s_endpgm1667 %r = urem <4 x i32> %x, %y1668 store <4 x i32> %r, ptr addrspace(1) %out1669 ret void1670}1671 1672define amdgpu_kernel void @sdiv_v4i32(ptr addrspace(1) %out, <4 x i32> %x, <4 x i32> %y) {1673; CHECK-LABEL: @sdiv_v4i32(1674; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i32> [[X:%.*]], i64 01675; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i32> [[Y:%.*]], i64 01676; CHECK-NEXT: [[TMP3:%.*]] = ashr i32 [[TMP1]], 311677; CHECK-NEXT: [[TMP4:%.*]] = ashr i32 [[TMP2]], 311678; CHECK-NEXT: [[TMP5:%.*]] = xor i32 [[TMP3]], [[TMP4]]1679; CHECK-NEXT: [[TMP6:%.*]] = add i32 [[TMP1]], [[TMP3]]1680; CHECK-NEXT: [[TMP7:%.*]] = add i32 [[TMP2]], [[TMP4]]1681; CHECK-NEXT: [[TMP8:%.*]] = xor i32 [[TMP6]], [[TMP3]]1682; CHECK-NEXT: [[TMP9:%.*]] = xor i32 [[TMP7]], [[TMP4]]1683; CHECK-NEXT: [[TMP10:%.*]] = uitofp i32 [[TMP9]] to float1684; CHECK-NEXT: [[TMP11:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP10]])1685; CHECK-NEXT: [[TMP12:%.*]] = fmul fast float [[TMP11]], 0x41EFFFFFC00000001686; CHECK-NEXT: [[TMP13:%.*]] = fptoui float [[TMP12]] to i321687; CHECK-NEXT: [[TMP14:%.*]] = sub i32 0, [[TMP9]]1688; CHECK-NEXT: [[TMP15:%.*]] = mul i32 [[TMP14]], [[TMP13]]1689; CHECK-NEXT: [[TMP16:%.*]] = zext i32 [[TMP13]] to i641690; CHECK-NEXT: [[TMP17:%.*]] = zext i32 [[TMP15]] to i641691; CHECK-NEXT: [[TMP18:%.*]] = mul i64 [[TMP16]], [[TMP17]]1692; CHECK-NEXT: [[TMP19:%.*]] = trunc i64 [[TMP18]] to i321693; CHECK-NEXT: [[TMP20:%.*]] = lshr i64 [[TMP18]], 321694; CHECK-NEXT: [[TMP21:%.*]] = trunc i64 [[TMP20]] to i321695; CHECK-NEXT: [[TMP22:%.*]] = add i32 [[TMP13]], [[TMP21]]1696; CHECK-NEXT: [[TMP23:%.*]] = zext i32 [[TMP8]] to i641697; CHECK-NEXT: [[TMP24:%.*]] = zext i32 [[TMP22]] to i641698; CHECK-NEXT: [[TMP25:%.*]] = mul i64 [[TMP23]], [[TMP24]]1699; CHECK-NEXT: [[TMP26:%.*]] = trunc i64 [[TMP25]] to i321700; CHECK-NEXT: [[TMP27:%.*]] = lshr i64 [[TMP25]], 321701; CHECK-NEXT: [[TMP28:%.*]] = trunc i64 [[TMP27]] to i321702; CHECK-NEXT: [[TMP29:%.*]] = mul i32 [[TMP28]], [[TMP9]]1703; CHECK-NEXT: [[TMP30:%.*]] = sub i32 [[TMP8]], [[TMP29]]1704; CHECK-NEXT: [[TMP31:%.*]] = icmp uge i32 [[TMP30]], [[TMP9]]1705; CHECK-NEXT: [[TMP32:%.*]] = add i32 [[TMP28]], 11706; CHECK-NEXT: [[TMP33:%.*]] = select i1 [[TMP31]], i32 [[TMP32]], i32 [[TMP28]]1707; CHECK-NEXT: [[TMP34:%.*]] = sub i32 [[TMP30]], [[TMP9]]1708; CHECK-NEXT: [[TMP35:%.*]] = select i1 [[TMP31]], i32 [[TMP34]], i32 [[TMP30]]1709; CHECK-NEXT: [[TMP36:%.*]] = icmp uge i32 [[TMP35]], [[TMP9]]1710; CHECK-NEXT: [[TMP37:%.*]] = add i32 [[TMP33]], 11711; CHECK-NEXT: [[TMP38:%.*]] = select i1 [[TMP36]], i32 [[TMP37]], i32 [[TMP33]]1712; CHECK-NEXT: [[TMP39:%.*]] = xor i32 [[TMP38]], [[TMP5]]1713; CHECK-NEXT: [[TMP40:%.*]] = sub i32 [[TMP39]], [[TMP5]]1714; CHECK-NEXT: [[TMP41:%.*]] = insertelement <4 x i32> poison, i32 [[TMP40]], i64 01715; CHECK-NEXT: [[TMP42:%.*]] = extractelement <4 x i32> [[X]], i64 11716; CHECK-NEXT: [[TMP43:%.*]] = extractelement <4 x i32> [[Y]], i64 11717; CHECK-NEXT: [[TMP44:%.*]] = ashr i32 [[TMP42]], 311718; CHECK-NEXT: [[TMP45:%.*]] = ashr i32 [[TMP43]], 311719; CHECK-NEXT: [[TMP46:%.*]] = xor i32 [[TMP44]], [[TMP45]]1720; CHECK-NEXT: [[TMP47:%.*]] = add i32 [[TMP42]], [[TMP44]]1721; CHECK-NEXT: [[TMP48:%.*]] = add i32 [[TMP43]], [[TMP45]]1722; CHECK-NEXT: [[TMP49:%.*]] = xor i32 [[TMP47]], [[TMP44]]1723; CHECK-NEXT: [[TMP50:%.*]] = xor i32 [[TMP48]], [[TMP45]]1724; CHECK-NEXT: [[TMP51:%.*]] = uitofp i32 [[TMP50]] to float1725; CHECK-NEXT: [[TMP52:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP51]])1726; CHECK-NEXT: [[TMP53:%.*]] = fmul fast float [[TMP52]], 0x41EFFFFFC00000001727; CHECK-NEXT: [[TMP54:%.*]] = fptoui float [[TMP53]] to i321728; CHECK-NEXT: [[TMP55:%.*]] = sub i32 0, [[TMP50]]1729; CHECK-NEXT: [[TMP56:%.*]] = mul i32 [[TMP55]], [[TMP54]]1730; CHECK-NEXT: [[TMP57:%.*]] = zext i32 [[TMP54]] to i641731; CHECK-NEXT: [[TMP58:%.*]] = zext i32 [[TMP56]] to i641732; CHECK-NEXT: [[TMP59:%.*]] = mul i64 [[TMP57]], [[TMP58]]1733; CHECK-NEXT: [[TMP60:%.*]] = trunc i64 [[TMP59]] to i321734; CHECK-NEXT: [[TMP61:%.*]] = lshr i64 [[TMP59]], 321735; CHECK-NEXT: [[TMP62:%.*]] = trunc i64 [[TMP61]] to i321736; CHECK-NEXT: [[TMP63:%.*]] = add i32 [[TMP54]], [[TMP62]]1737; CHECK-NEXT: [[TMP64:%.*]] = zext i32 [[TMP49]] to i641738; CHECK-NEXT: [[TMP65:%.*]] = zext i32 [[TMP63]] to i641739; CHECK-NEXT: [[TMP66:%.*]] = mul i64 [[TMP64]], [[TMP65]]1740; CHECK-NEXT: [[TMP67:%.*]] = trunc i64 [[TMP66]] to i321741; CHECK-NEXT: [[TMP68:%.*]] = lshr i64 [[TMP66]], 321742; CHECK-NEXT: [[TMP69:%.*]] = trunc i64 [[TMP68]] to i321743; CHECK-NEXT: [[TMP70:%.*]] = mul i32 [[TMP69]], [[TMP50]]1744; CHECK-NEXT: [[TMP71:%.*]] = sub i32 [[TMP49]], [[TMP70]]1745; CHECK-NEXT: [[TMP72:%.*]] = icmp uge i32 [[TMP71]], [[TMP50]]1746; CHECK-NEXT: [[TMP73:%.*]] = add i32 [[TMP69]], 11747; CHECK-NEXT: [[TMP74:%.*]] = select i1 [[TMP72]], i32 [[TMP73]], i32 [[TMP69]]1748; CHECK-NEXT: [[TMP75:%.*]] = sub i32 [[TMP71]], [[TMP50]]1749; CHECK-NEXT: [[TMP76:%.*]] = select i1 [[TMP72]], i32 [[TMP75]], i32 [[TMP71]]1750; CHECK-NEXT: [[TMP77:%.*]] = icmp uge i32 [[TMP76]], [[TMP50]]1751; CHECK-NEXT: [[TMP78:%.*]] = add i32 [[TMP74]], 11752; CHECK-NEXT: [[TMP79:%.*]] = select i1 [[TMP77]], i32 [[TMP78]], i32 [[TMP74]]1753; CHECK-NEXT: [[TMP80:%.*]] = xor i32 [[TMP79]], [[TMP46]]1754; CHECK-NEXT: [[TMP81:%.*]] = sub i32 [[TMP80]], [[TMP46]]1755; CHECK-NEXT: [[TMP82:%.*]] = insertelement <4 x i32> [[TMP41]], i32 [[TMP81]], i64 11756; CHECK-NEXT: [[TMP83:%.*]] = extractelement <4 x i32> [[X]], i64 21757; CHECK-NEXT: [[TMP84:%.*]] = extractelement <4 x i32> [[Y]], i64 21758; CHECK-NEXT: [[TMP85:%.*]] = ashr i32 [[TMP83]], 311759; CHECK-NEXT: [[TMP86:%.*]] = ashr i32 [[TMP84]], 311760; CHECK-NEXT: [[TMP87:%.*]] = xor i32 [[TMP85]], [[TMP86]]1761; CHECK-NEXT: [[TMP88:%.*]] = add i32 [[TMP83]], [[TMP85]]1762; CHECK-NEXT: [[TMP89:%.*]] = add i32 [[TMP84]], [[TMP86]]1763; CHECK-NEXT: [[TMP90:%.*]] = xor i32 [[TMP88]], [[TMP85]]1764; CHECK-NEXT: [[TMP91:%.*]] = xor i32 [[TMP89]], [[TMP86]]1765; CHECK-NEXT: [[TMP92:%.*]] = uitofp i32 [[TMP91]] to float1766; CHECK-NEXT: [[TMP93:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP92]])1767; CHECK-NEXT: [[TMP94:%.*]] = fmul fast float [[TMP93]], 0x41EFFFFFC00000001768; CHECK-NEXT: [[TMP95:%.*]] = fptoui float [[TMP94]] to i321769; CHECK-NEXT: [[TMP96:%.*]] = sub i32 0, [[TMP91]]1770; CHECK-NEXT: [[TMP97:%.*]] = mul i32 [[TMP96]], [[TMP95]]1771; CHECK-NEXT: [[TMP98:%.*]] = zext i32 [[TMP95]] to i641772; CHECK-NEXT: [[TMP99:%.*]] = zext i32 [[TMP97]] to i641773; CHECK-NEXT: [[TMP100:%.*]] = mul i64 [[TMP98]], [[TMP99]]1774; CHECK-NEXT: [[TMP101:%.*]] = trunc i64 [[TMP100]] to i321775; CHECK-NEXT: [[TMP102:%.*]] = lshr i64 [[TMP100]], 321776; CHECK-NEXT: [[TMP103:%.*]] = trunc i64 [[TMP102]] to i321777; CHECK-NEXT: [[TMP104:%.*]] = add i32 [[TMP95]], [[TMP103]]1778; CHECK-NEXT: [[TMP105:%.*]] = zext i32 [[TMP90]] to i641779; CHECK-NEXT: [[TMP106:%.*]] = zext i32 [[TMP104]] to i641780; CHECK-NEXT: [[TMP107:%.*]] = mul i64 [[TMP105]], [[TMP106]]1781; CHECK-NEXT: [[TMP108:%.*]] = trunc i64 [[TMP107]] to i321782; CHECK-NEXT: [[TMP109:%.*]] = lshr i64 [[TMP107]], 321783; CHECK-NEXT: [[TMP110:%.*]] = trunc i64 [[TMP109]] to i321784; CHECK-NEXT: [[TMP111:%.*]] = mul i32 [[TMP110]], [[TMP91]]1785; CHECK-NEXT: [[TMP112:%.*]] = sub i32 [[TMP90]], [[TMP111]]1786; CHECK-NEXT: [[TMP113:%.*]] = icmp uge i32 [[TMP112]], [[TMP91]]1787; CHECK-NEXT: [[TMP114:%.*]] = add i32 [[TMP110]], 11788; CHECK-NEXT: [[TMP115:%.*]] = select i1 [[TMP113]], i32 [[TMP114]], i32 [[TMP110]]1789; CHECK-NEXT: [[TMP116:%.*]] = sub i32 [[TMP112]], [[TMP91]]1790; CHECK-NEXT: [[TMP117:%.*]] = select i1 [[TMP113]], i32 [[TMP116]], i32 [[TMP112]]1791; CHECK-NEXT: [[TMP118:%.*]] = icmp uge i32 [[TMP117]], [[TMP91]]1792; CHECK-NEXT: [[TMP119:%.*]] = add i32 [[TMP115]], 11793; CHECK-NEXT: [[TMP120:%.*]] = select i1 [[TMP118]], i32 [[TMP119]], i32 [[TMP115]]1794; CHECK-NEXT: [[TMP121:%.*]] = xor i32 [[TMP120]], [[TMP87]]1795; CHECK-NEXT: [[TMP122:%.*]] = sub i32 [[TMP121]], [[TMP87]]1796; CHECK-NEXT: [[TMP123:%.*]] = insertelement <4 x i32> [[TMP82]], i32 [[TMP122]], i64 21797; CHECK-NEXT: [[TMP124:%.*]] = extractelement <4 x i32> [[X]], i64 31798; CHECK-NEXT: [[TMP125:%.*]] = extractelement <4 x i32> [[Y]], i64 31799; CHECK-NEXT: [[TMP126:%.*]] = ashr i32 [[TMP124]], 311800; CHECK-NEXT: [[TMP127:%.*]] = ashr i32 [[TMP125]], 311801; CHECK-NEXT: [[TMP128:%.*]] = xor i32 [[TMP126]], [[TMP127]]1802; CHECK-NEXT: [[TMP129:%.*]] = add i32 [[TMP124]], [[TMP126]]1803; CHECK-NEXT: [[TMP130:%.*]] = add i32 [[TMP125]], [[TMP127]]1804; CHECK-NEXT: [[TMP131:%.*]] = xor i32 [[TMP129]], [[TMP126]]1805; CHECK-NEXT: [[TMP132:%.*]] = xor i32 [[TMP130]], [[TMP127]]1806; CHECK-NEXT: [[TMP133:%.*]] = uitofp i32 [[TMP132]] to float1807; CHECK-NEXT: [[TMP134:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP133]])1808; CHECK-NEXT: [[TMP135:%.*]] = fmul fast float [[TMP134]], 0x41EFFFFFC00000001809; CHECK-NEXT: [[TMP136:%.*]] = fptoui float [[TMP135]] to i321810; CHECK-NEXT: [[TMP137:%.*]] = sub i32 0, [[TMP132]]1811; CHECK-NEXT: [[TMP138:%.*]] = mul i32 [[TMP137]], [[TMP136]]1812; CHECK-NEXT: [[TMP139:%.*]] = zext i32 [[TMP136]] to i641813; CHECK-NEXT: [[TMP140:%.*]] = zext i32 [[TMP138]] to i641814; CHECK-NEXT: [[TMP141:%.*]] = mul i64 [[TMP139]], [[TMP140]]1815; CHECK-NEXT: [[TMP142:%.*]] = trunc i64 [[TMP141]] to i321816; CHECK-NEXT: [[TMP143:%.*]] = lshr i64 [[TMP141]], 321817; CHECK-NEXT: [[TMP144:%.*]] = trunc i64 [[TMP143]] to i321818; CHECK-NEXT: [[TMP145:%.*]] = add i32 [[TMP136]], [[TMP144]]1819; CHECK-NEXT: [[TMP146:%.*]] = zext i32 [[TMP131]] to i641820; CHECK-NEXT: [[TMP147:%.*]] = zext i32 [[TMP145]] to i641821; CHECK-NEXT: [[TMP148:%.*]] = mul i64 [[TMP146]], [[TMP147]]1822; CHECK-NEXT: [[TMP149:%.*]] = trunc i64 [[TMP148]] to i321823; CHECK-NEXT: [[TMP150:%.*]] = lshr i64 [[TMP148]], 321824; CHECK-NEXT: [[TMP151:%.*]] = trunc i64 [[TMP150]] to i321825; CHECK-NEXT: [[TMP152:%.*]] = mul i32 [[TMP151]], [[TMP132]]1826; CHECK-NEXT: [[TMP153:%.*]] = sub i32 [[TMP131]], [[TMP152]]1827; CHECK-NEXT: [[TMP154:%.*]] = icmp uge i32 [[TMP153]], [[TMP132]]1828; CHECK-NEXT: [[TMP155:%.*]] = add i32 [[TMP151]], 11829; CHECK-NEXT: [[TMP156:%.*]] = select i1 [[TMP154]], i32 [[TMP155]], i32 [[TMP151]]1830; CHECK-NEXT: [[TMP157:%.*]] = sub i32 [[TMP153]], [[TMP132]]1831; CHECK-NEXT: [[TMP158:%.*]] = select i1 [[TMP154]], i32 [[TMP157]], i32 [[TMP153]]1832; CHECK-NEXT: [[TMP159:%.*]] = icmp uge i32 [[TMP158]], [[TMP132]]1833; CHECK-NEXT: [[TMP160:%.*]] = add i32 [[TMP156]], 11834; CHECK-NEXT: [[TMP161:%.*]] = select i1 [[TMP159]], i32 [[TMP160]], i32 [[TMP156]]1835; CHECK-NEXT: [[TMP162:%.*]] = xor i32 [[TMP161]], [[TMP128]]1836; CHECK-NEXT: [[TMP163:%.*]] = sub i32 [[TMP162]], [[TMP128]]1837; CHECK-NEXT: [[TMP164:%.*]] = insertelement <4 x i32> [[TMP123]], i32 [[TMP163]], i64 31838; CHECK-NEXT: store <4 x i32> [[TMP164]], ptr addrspace(1) [[OUT:%.*]], align 161839; CHECK-NEXT: ret void1840;1841; GFX6-LABEL: sdiv_v4i32:1842; GFX6: ; %bb.0:1843; GFX6-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0xd1844; GFX6-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x91845; GFX6-NEXT: s_mov_b32 s19, 0xf0001846; GFX6-NEXT: s_mov_b32 s18, -11847; GFX6-NEXT: s_waitcnt lgkmcnt(0)1848; GFX6-NEXT: s_abs_i32 s0, s121849; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s01850; GFX6-NEXT: s_sub_i32 s1, 0, s01851; GFX6-NEXT: s_xor_b32 s2, s8, s121852; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v01853; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v01854; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v01855; GFX6-NEXT: v_mul_lo_u32 v1, s1, v01856; GFX6-NEXT: s_abs_i32 s1, s81857; GFX6-NEXT: s_ashr_i32 s8, s2, 311858; GFX6-NEXT: v_mul_hi_u32 v1, v0, v11859; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v11860; GFX6-NEXT: v_mul_hi_u32 v0, s1, v01861; GFX6-NEXT: v_readfirstlane_b32 s2, v01862; GFX6-NEXT: s_mul_i32 s2, s2, s01863; GFX6-NEXT: s_sub_i32 s1, s1, s21864; GFX6-NEXT: s_sub_i32 s2, s1, s01865; GFX6-NEXT: s_cmp_ge_u32 s1, s01866; GFX6-NEXT: v_add_i32_e32 v1, vcc, 1, v01867; GFX6-NEXT: s_cselect_b32 s1, s2, s11868; GFX6-NEXT: s_cselect_b64 vcc, -1, 01869; GFX6-NEXT: s_cmp_ge_u32 s1, s01870; GFX6-NEXT: s_cselect_b64 s[0:1], -1, 01871; GFX6-NEXT: s_abs_i32 s2, s131872; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s21873; GFX6-NEXT: s_sub_i32 s3, 0, s21874; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc1875; GFX6-NEXT: s_xor_b32 s6, s9, s131876; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v21877; GFX6-NEXT: v_add_i32_e32 v1, vcc, 1, v01878; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[0:1]1879; GFX6-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v21880; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v21881; GFX6-NEXT: v_xor_b32_e32 v0, s8, v01882; GFX6-NEXT: v_mul_lo_u32 v3, s3, v21883; GFX6-NEXT: s_abs_i32 s3, s91884; GFX6-NEXT: s_ashr_i32 s9, s6, 311885; GFX6-NEXT: v_mul_hi_u32 v3, v2, v31886; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v31887; GFX6-NEXT: v_mul_hi_u32 v2, s3, v21888; GFX6-NEXT: v_readfirstlane_b32 s6, v21889; GFX6-NEXT: s_mul_i32 s6, s6, s21890; GFX6-NEXT: s_sub_i32 s3, s3, s61891; GFX6-NEXT: s_sub_i32 s6, s3, s21892; GFX6-NEXT: s_cmp_ge_u32 s3, s21893; GFX6-NEXT: v_add_i32_e32 v3, vcc, 1, v21894; GFX6-NEXT: s_cselect_b32 s3, s6, s31895; GFX6-NEXT: s_cselect_b64 vcc, -1, 01896; GFX6-NEXT: s_cmp_ge_u32 s3, s21897; GFX6-NEXT: s_cselect_b64 s[2:3], -1, 01898; GFX6-NEXT: s_abs_i32 s6, s141899; GFX6-NEXT: v_cvt_f32_u32_e32 v4, s61900; GFX6-NEXT: s_sub_i32 s7, 0, s61901; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc1902; GFX6-NEXT: v_add_i32_e32 v3, vcc, 1, v21903; GFX6-NEXT: v_rcp_iflag_f32_e32 v4, v41904; GFX6-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v41905; GFX6-NEXT: v_cvt_u32_f32_e32 v4, v41906; GFX6-NEXT: v_mul_lo_u32 v5, s7, v41907; GFX6-NEXT: s_abs_i32 s7, s101908; GFX6-NEXT: s_xor_b32 s10, s10, s141909; GFX6-NEXT: s_ashr_i32 s10, s10, 311910; GFX6-NEXT: v_mul_hi_u32 v5, v4, v51911; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v51912; GFX6-NEXT: v_mul_hi_u32 v4, s7, v41913; GFX6-NEXT: v_readfirstlane_b32 s12, v41914; GFX6-NEXT: s_mul_i32 s12, s12, s61915; GFX6-NEXT: s_sub_i32 s7, s7, s121916; GFX6-NEXT: s_sub_i32 s12, s7, s61917; GFX6-NEXT: s_cmp_ge_u32 s7, s61918; GFX6-NEXT: v_add_i32_e32 v5, vcc, 1, v41919; GFX6-NEXT: s_cselect_b32 s7, s12, s71920; GFX6-NEXT: s_cselect_b64 vcc, -1, 01921; GFX6-NEXT: s_cmp_ge_u32 s7, s61922; GFX6-NEXT: s_cselect_b64 s[6:7], -1, 01923; GFX6-NEXT: s_abs_i32 s12, s151924; GFX6-NEXT: v_cvt_f32_u32_e32 v6, s121925; GFX6-NEXT: s_sub_i32 s0, 0, s121926; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc1927; GFX6-NEXT: v_add_i32_e32 v5, vcc, 1, v41928; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v61929; GFX6-NEXT: s_abs_i32 s1, s111930; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s8, v01931; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v11932; GFX6-NEXT: v_cvt_u32_f32_e32 v6, v11933; GFX6-NEXT: v_cndmask_b32_e64 v1, v2, v3, s[2:3]1934; GFX6-NEXT: v_cndmask_b32_e64 v3, v4, v5, s[6:7]1935; GFX6-NEXT: v_xor_b32_e32 v1, s9, v11936; GFX6-NEXT: v_mul_lo_u32 v2, s0, v61937; GFX6-NEXT: s_xor_b32 s0, s11, s151938; GFX6-NEXT: v_xor_b32_e32 v3, s10, v31939; GFX6-NEXT: s_ashr_i32 s0, s0, 311940; GFX6-NEXT: v_mul_hi_u32 v2, v6, v21941; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, s9, v11942; GFX6-NEXT: v_add_i32_e32 v2, vcc, v6, v21943; GFX6-NEXT: v_mul_hi_u32 v4, s1, v21944; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s10, v31945; GFX6-NEXT: v_readfirstlane_b32 s2, v41946; GFX6-NEXT: s_mul_i32 s2, s2, s121947; GFX6-NEXT: s_sub_i32 s1, s1, s21948; GFX6-NEXT: s_sub_i32 s2, s1, s121949; GFX6-NEXT: v_add_i32_e32 v3, vcc, 1, v41950; GFX6-NEXT: s_cmp_ge_u32 s1, s121951; GFX6-NEXT: s_cselect_b64 vcc, -1, 01952; GFX6-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc1953; GFX6-NEXT: s_cselect_b32 s1, s2, s11954; GFX6-NEXT: v_add_i32_e32 v4, vcc, 1, v31955; GFX6-NEXT: s_cmp_ge_u32 s1, s121956; GFX6-NEXT: s_cselect_b64 vcc, -1, 01957; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc1958; GFX6-NEXT: v_xor_b32_e32 v3, s0, v31959; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s0, v31960; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 01961; GFX6-NEXT: s_endpgm1962;1963; GFX9-LABEL: sdiv_v4i32:1964; GFX9: ; %bb.0:1965; GFX9-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x341966; GFX9-NEXT: v_mov_b32_e32 v4, 01967; GFX9-NEXT: s_waitcnt lgkmcnt(0)1968; GFX9-NEXT: s_abs_i32 s0, s121969; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s01970; GFX9-NEXT: s_sub_i32 s3, 0, s01971; GFX9-NEXT: s_abs_i32 s2, s81972; GFX9-NEXT: s_xor_b32 s1, s8, s121973; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v01974; GFX9-NEXT: s_ashr_i32 s1, s1, 311975; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v01976; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v01977; GFX9-NEXT: v_readfirstlane_b32 s6, v01978; GFX9-NEXT: s_mul_i32 s3, s3, s61979; GFX9-NEXT: s_mul_hi_u32 s3, s6, s31980; GFX9-NEXT: s_add_i32 s6, s6, s31981; GFX9-NEXT: s_mul_hi_u32 s3, s2, s61982; GFX9-NEXT: s_mul_i32 s6, s3, s01983; GFX9-NEXT: s_sub_i32 s2, s2, s61984; GFX9-NEXT: s_add_i32 s7, s3, 11985; GFX9-NEXT: s_sub_i32 s6, s2, s01986; GFX9-NEXT: s_cmp_ge_u32 s2, s01987; GFX9-NEXT: s_cselect_b32 s3, s7, s31988; GFX9-NEXT: s_cselect_b32 s2, s6, s21989; GFX9-NEXT: s_add_i32 s6, s3, 11990; GFX9-NEXT: s_cmp_ge_u32 s2, s01991; GFX9-NEXT: s_cselect_b32 s0, s6, s31992; GFX9-NEXT: s_abs_i32 s2, s131993; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s21994; GFX9-NEXT: s_xor_b32 s0, s0, s11995; GFX9-NEXT: s_sub_i32 s7, 0, s21996; GFX9-NEXT: s_sub_i32 s8, s0, s11997; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v01998; GFX9-NEXT: s_abs_i32 s6, s91999; GFX9-NEXT: s_xor_b32 s3, s9, s132000; GFX9-NEXT: s_ashr_i32 s3, s3, 312001; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v02002; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v02003; GFX9-NEXT: v_readfirstlane_b32 s0, v02004; GFX9-NEXT: s_mul_i32 s7, s7, s02005; GFX9-NEXT: s_mul_hi_u32 s1, s0, s72006; GFX9-NEXT: s_add_i32 s0, s0, s12007; GFX9-NEXT: s_mul_hi_u32 s0, s6, s02008; GFX9-NEXT: s_mul_i32 s1, s0, s22009; GFX9-NEXT: s_sub_i32 s1, s6, s12010; GFX9-NEXT: s_add_i32 s7, s0, 12011; GFX9-NEXT: s_sub_i32 s6, s1, s22012; GFX9-NEXT: s_cmp_ge_u32 s1, s22013; GFX9-NEXT: s_cselect_b32 s0, s7, s02014; GFX9-NEXT: s_cselect_b32 s1, s6, s12015; GFX9-NEXT: s_add_i32 s6, s0, 12016; GFX9-NEXT: s_cmp_ge_u32 s1, s22017; GFX9-NEXT: s_cselect_b32 s0, s6, s02018; GFX9-NEXT: s_abs_i32 s1, s142019; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s12020; GFX9-NEXT: s_xor_b32 s0, s0, s32021; GFX9-NEXT: s_sub_i32 s7, 0, s12022; GFX9-NEXT: s_sub_i32 s3, s0, s32023; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v02024; GFX9-NEXT: s_abs_i32 s6, s102025; GFX9-NEXT: s_xor_b32 s2, s10, s142026; GFX9-NEXT: s_ashr_i32 s2, s2, 312027; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v02028; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v02029; GFX9-NEXT: v_mov_b32_e32 v1, s32030; GFX9-NEXT: v_readfirstlane_b32 s0, v02031; GFX9-NEXT: s_mul_i32 s7, s7, s02032; GFX9-NEXT: s_mul_hi_u32 s7, s0, s72033; GFX9-NEXT: s_add_i32 s0, s0, s72034; GFX9-NEXT: s_mul_hi_u32 s0, s6, s02035; GFX9-NEXT: s_mul_i32 s7, s0, s12036; GFX9-NEXT: s_sub_i32 s6, s6, s72037; GFX9-NEXT: s_add_i32 s9, s0, 12038; GFX9-NEXT: s_sub_i32 s7, s6, s12039; GFX9-NEXT: s_cmp_ge_u32 s6, s12040; GFX9-NEXT: s_cselect_b32 s0, s9, s02041; GFX9-NEXT: s_cselect_b32 s6, s7, s62042; GFX9-NEXT: s_add_i32 s7, s0, 12043; GFX9-NEXT: s_cmp_ge_u32 s6, s12044; GFX9-NEXT: s_cselect_b32 s6, s7, s02045; GFX9-NEXT: s_abs_i32 s7, s152046; GFX9-NEXT: v_cvt_f32_u32_e32 v2, s72047; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x242048; GFX9-NEXT: s_xor_b32 s5, s6, s22049; GFX9-NEXT: s_sub_i32 s6, 0, s72050; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v22051; GFX9-NEXT: s_sub_i32 s2, s5, s22052; GFX9-NEXT: s_abs_i32 s4, s112053; GFX9-NEXT: s_xor_b32 s3, s11, s152054; GFX9-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v22055; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v22056; GFX9-NEXT: v_mov_b32_e32 v0, s82057; GFX9-NEXT: s_ashr_i32 s3, s3, 312058; GFX9-NEXT: v_readfirstlane_b32 s5, v22059; GFX9-NEXT: s_mul_i32 s6, s6, s52060; GFX9-NEXT: s_mul_hi_u32 s6, s5, s62061; GFX9-NEXT: s_add_i32 s5, s5, s62062; GFX9-NEXT: s_mul_hi_u32 s5, s4, s52063; GFX9-NEXT: s_mul_i32 s6, s5, s72064; GFX9-NEXT: s_sub_i32 s4, s4, s62065; GFX9-NEXT: s_add_i32 s8, s5, 12066; GFX9-NEXT: s_sub_i32 s6, s4, s72067; GFX9-NEXT: s_cmp_ge_u32 s4, s72068; GFX9-NEXT: s_cselect_b32 s5, s8, s52069; GFX9-NEXT: s_cselect_b32 s4, s6, s42070; GFX9-NEXT: s_add_i32 s6, s5, 12071; GFX9-NEXT: s_cmp_ge_u32 s4, s72072; GFX9-NEXT: s_cselect_b32 s4, s6, s52073; GFX9-NEXT: s_xor_b32 s4, s4, s32074; GFX9-NEXT: s_sub_i32 s3, s4, s32075; GFX9-NEXT: v_mov_b32_e32 v2, s22076; GFX9-NEXT: v_mov_b32_e32 v3, s32077; GFX9-NEXT: s_waitcnt lgkmcnt(0)2078; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]2079; GFX9-NEXT: s_endpgm2080 %r = sdiv <4 x i32> %x, %y2081 store <4 x i32> %r, ptr addrspace(1) %out2082 ret void2083}2084 2085define amdgpu_kernel void @srem_v4i32(ptr addrspace(1) %out, <4 x i32> %x, <4 x i32> %y) {2086; CHECK-LABEL: @srem_v4i32(2087; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i32> [[X:%.*]], i64 02088; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i32> [[Y:%.*]], i64 02089; CHECK-NEXT: [[TMP3:%.*]] = ashr i32 [[TMP1]], 312090; CHECK-NEXT: [[TMP4:%.*]] = ashr i32 [[TMP2]], 312091; CHECK-NEXT: [[TMP5:%.*]] = add i32 [[TMP1]], [[TMP3]]2092; CHECK-NEXT: [[TMP6:%.*]] = add i32 [[TMP2]], [[TMP4]]2093; CHECK-NEXT: [[TMP7:%.*]] = xor i32 [[TMP5]], [[TMP3]]2094; CHECK-NEXT: [[TMP8:%.*]] = xor i32 [[TMP6]], [[TMP4]]2095; CHECK-NEXT: [[TMP9:%.*]] = uitofp i32 [[TMP8]] to float2096; CHECK-NEXT: [[TMP10:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP9]])2097; CHECK-NEXT: [[TMP11:%.*]] = fmul fast float [[TMP10]], 0x41EFFFFFC00000002098; CHECK-NEXT: [[TMP12:%.*]] = fptoui float [[TMP11]] to i322099; CHECK-NEXT: [[TMP13:%.*]] = sub i32 0, [[TMP8]]2100; CHECK-NEXT: [[TMP14:%.*]] = mul i32 [[TMP13]], [[TMP12]]2101; CHECK-NEXT: [[TMP15:%.*]] = zext i32 [[TMP12]] to i642102; CHECK-NEXT: [[TMP16:%.*]] = zext i32 [[TMP14]] to i642103; CHECK-NEXT: [[TMP17:%.*]] = mul i64 [[TMP15]], [[TMP16]]2104; CHECK-NEXT: [[TMP18:%.*]] = trunc i64 [[TMP17]] to i322105; CHECK-NEXT: [[TMP19:%.*]] = lshr i64 [[TMP17]], 322106; CHECK-NEXT: [[TMP20:%.*]] = trunc i64 [[TMP19]] to i322107; CHECK-NEXT: [[TMP21:%.*]] = add i32 [[TMP12]], [[TMP20]]2108; CHECK-NEXT: [[TMP22:%.*]] = zext i32 [[TMP7]] to i642109; CHECK-NEXT: [[TMP23:%.*]] = zext i32 [[TMP21]] to i642110; CHECK-NEXT: [[TMP24:%.*]] = mul i64 [[TMP22]], [[TMP23]]2111; CHECK-NEXT: [[TMP25:%.*]] = trunc i64 [[TMP24]] to i322112; CHECK-NEXT: [[TMP26:%.*]] = lshr i64 [[TMP24]], 322113; CHECK-NEXT: [[TMP27:%.*]] = trunc i64 [[TMP26]] to i322114; CHECK-NEXT: [[TMP28:%.*]] = mul i32 [[TMP27]], [[TMP8]]2115; CHECK-NEXT: [[TMP29:%.*]] = sub i32 [[TMP7]], [[TMP28]]2116; CHECK-NEXT: [[TMP30:%.*]] = icmp uge i32 [[TMP29]], [[TMP8]]2117; CHECK-NEXT: [[TMP31:%.*]] = sub i32 [[TMP29]], [[TMP8]]2118; CHECK-NEXT: [[TMP32:%.*]] = select i1 [[TMP30]], i32 [[TMP31]], i32 [[TMP29]]2119; CHECK-NEXT: [[TMP33:%.*]] = icmp uge i32 [[TMP32]], [[TMP8]]2120; CHECK-NEXT: [[TMP34:%.*]] = sub i32 [[TMP32]], [[TMP8]]2121; CHECK-NEXT: [[TMP35:%.*]] = select i1 [[TMP33]], i32 [[TMP34]], i32 [[TMP32]]2122; CHECK-NEXT: [[TMP36:%.*]] = xor i32 [[TMP35]], [[TMP3]]2123; CHECK-NEXT: [[TMP37:%.*]] = sub i32 [[TMP36]], [[TMP3]]2124; CHECK-NEXT: [[TMP38:%.*]] = insertelement <4 x i32> poison, i32 [[TMP37]], i64 02125; CHECK-NEXT: [[TMP39:%.*]] = extractelement <4 x i32> [[X]], i64 12126; CHECK-NEXT: [[TMP40:%.*]] = extractelement <4 x i32> [[Y]], i64 12127; CHECK-NEXT: [[TMP41:%.*]] = ashr i32 [[TMP39]], 312128; CHECK-NEXT: [[TMP42:%.*]] = ashr i32 [[TMP40]], 312129; CHECK-NEXT: [[TMP43:%.*]] = add i32 [[TMP39]], [[TMP41]]2130; CHECK-NEXT: [[TMP44:%.*]] = add i32 [[TMP40]], [[TMP42]]2131; CHECK-NEXT: [[TMP45:%.*]] = xor i32 [[TMP43]], [[TMP41]]2132; CHECK-NEXT: [[TMP46:%.*]] = xor i32 [[TMP44]], [[TMP42]]2133; CHECK-NEXT: [[TMP47:%.*]] = uitofp i32 [[TMP46]] to float2134; CHECK-NEXT: [[TMP48:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP47]])2135; CHECK-NEXT: [[TMP49:%.*]] = fmul fast float [[TMP48]], 0x41EFFFFFC00000002136; CHECK-NEXT: [[TMP50:%.*]] = fptoui float [[TMP49]] to i322137; CHECK-NEXT: [[TMP51:%.*]] = sub i32 0, [[TMP46]]2138; CHECK-NEXT: [[TMP52:%.*]] = mul i32 [[TMP51]], [[TMP50]]2139; CHECK-NEXT: [[TMP53:%.*]] = zext i32 [[TMP50]] to i642140; CHECK-NEXT: [[TMP54:%.*]] = zext i32 [[TMP52]] to i642141; CHECK-NEXT: [[TMP55:%.*]] = mul i64 [[TMP53]], [[TMP54]]2142; CHECK-NEXT: [[TMP56:%.*]] = trunc i64 [[TMP55]] to i322143; CHECK-NEXT: [[TMP57:%.*]] = lshr i64 [[TMP55]], 322144; CHECK-NEXT: [[TMP58:%.*]] = trunc i64 [[TMP57]] to i322145; CHECK-NEXT: [[TMP59:%.*]] = add i32 [[TMP50]], [[TMP58]]2146; CHECK-NEXT: [[TMP60:%.*]] = zext i32 [[TMP45]] to i642147; CHECK-NEXT: [[TMP61:%.*]] = zext i32 [[TMP59]] to i642148; CHECK-NEXT: [[TMP62:%.*]] = mul i64 [[TMP60]], [[TMP61]]2149; CHECK-NEXT: [[TMP63:%.*]] = trunc i64 [[TMP62]] to i322150; CHECK-NEXT: [[TMP64:%.*]] = lshr i64 [[TMP62]], 322151; CHECK-NEXT: [[TMP65:%.*]] = trunc i64 [[TMP64]] to i322152; CHECK-NEXT: [[TMP66:%.*]] = mul i32 [[TMP65]], [[TMP46]]2153; CHECK-NEXT: [[TMP67:%.*]] = sub i32 [[TMP45]], [[TMP66]]2154; CHECK-NEXT: [[TMP68:%.*]] = icmp uge i32 [[TMP67]], [[TMP46]]2155; CHECK-NEXT: [[TMP69:%.*]] = sub i32 [[TMP67]], [[TMP46]]2156; CHECK-NEXT: [[TMP70:%.*]] = select i1 [[TMP68]], i32 [[TMP69]], i32 [[TMP67]]2157; CHECK-NEXT: [[TMP71:%.*]] = icmp uge i32 [[TMP70]], [[TMP46]]2158; CHECK-NEXT: [[TMP72:%.*]] = sub i32 [[TMP70]], [[TMP46]]2159; CHECK-NEXT: [[TMP73:%.*]] = select i1 [[TMP71]], i32 [[TMP72]], i32 [[TMP70]]2160; CHECK-NEXT: [[TMP74:%.*]] = xor i32 [[TMP73]], [[TMP41]]2161; CHECK-NEXT: [[TMP75:%.*]] = sub i32 [[TMP74]], [[TMP41]]2162; CHECK-NEXT: [[TMP76:%.*]] = insertelement <4 x i32> [[TMP38]], i32 [[TMP75]], i64 12163; CHECK-NEXT: [[TMP77:%.*]] = extractelement <4 x i32> [[X]], i64 22164; CHECK-NEXT: [[TMP78:%.*]] = extractelement <4 x i32> [[Y]], i64 22165; CHECK-NEXT: [[TMP79:%.*]] = ashr i32 [[TMP77]], 312166; CHECK-NEXT: [[TMP80:%.*]] = ashr i32 [[TMP78]], 312167; CHECK-NEXT: [[TMP81:%.*]] = add i32 [[TMP77]], [[TMP79]]2168; CHECK-NEXT: [[TMP82:%.*]] = add i32 [[TMP78]], [[TMP80]]2169; CHECK-NEXT: [[TMP83:%.*]] = xor i32 [[TMP81]], [[TMP79]]2170; CHECK-NEXT: [[TMP84:%.*]] = xor i32 [[TMP82]], [[TMP80]]2171; CHECK-NEXT: [[TMP85:%.*]] = uitofp i32 [[TMP84]] to float2172; CHECK-NEXT: [[TMP86:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP85]])2173; CHECK-NEXT: [[TMP87:%.*]] = fmul fast float [[TMP86]], 0x41EFFFFFC00000002174; CHECK-NEXT: [[TMP88:%.*]] = fptoui float [[TMP87]] to i322175; CHECK-NEXT: [[TMP89:%.*]] = sub i32 0, [[TMP84]]2176; CHECK-NEXT: [[TMP90:%.*]] = mul i32 [[TMP89]], [[TMP88]]2177; CHECK-NEXT: [[TMP91:%.*]] = zext i32 [[TMP88]] to i642178; CHECK-NEXT: [[TMP92:%.*]] = zext i32 [[TMP90]] to i642179; CHECK-NEXT: [[TMP93:%.*]] = mul i64 [[TMP91]], [[TMP92]]2180; CHECK-NEXT: [[TMP94:%.*]] = trunc i64 [[TMP93]] to i322181; CHECK-NEXT: [[TMP95:%.*]] = lshr i64 [[TMP93]], 322182; CHECK-NEXT: [[TMP96:%.*]] = trunc i64 [[TMP95]] to i322183; CHECK-NEXT: [[TMP97:%.*]] = add i32 [[TMP88]], [[TMP96]]2184; CHECK-NEXT: [[TMP98:%.*]] = zext i32 [[TMP83]] to i642185; CHECK-NEXT: [[TMP99:%.*]] = zext i32 [[TMP97]] to i642186; CHECK-NEXT: [[TMP100:%.*]] = mul i64 [[TMP98]], [[TMP99]]2187; CHECK-NEXT: [[TMP101:%.*]] = trunc i64 [[TMP100]] to i322188; CHECK-NEXT: [[TMP102:%.*]] = lshr i64 [[TMP100]], 322189; CHECK-NEXT: [[TMP103:%.*]] = trunc i64 [[TMP102]] to i322190; CHECK-NEXT: [[TMP104:%.*]] = mul i32 [[TMP103]], [[TMP84]]2191; CHECK-NEXT: [[TMP105:%.*]] = sub i32 [[TMP83]], [[TMP104]]2192; CHECK-NEXT: [[TMP106:%.*]] = icmp uge i32 [[TMP105]], [[TMP84]]2193; CHECK-NEXT: [[TMP107:%.*]] = sub i32 [[TMP105]], [[TMP84]]2194; CHECK-NEXT: [[TMP108:%.*]] = select i1 [[TMP106]], i32 [[TMP107]], i32 [[TMP105]]2195; CHECK-NEXT: [[TMP109:%.*]] = icmp uge i32 [[TMP108]], [[TMP84]]2196; CHECK-NEXT: [[TMP110:%.*]] = sub i32 [[TMP108]], [[TMP84]]2197; CHECK-NEXT: [[TMP111:%.*]] = select i1 [[TMP109]], i32 [[TMP110]], i32 [[TMP108]]2198; CHECK-NEXT: [[TMP112:%.*]] = xor i32 [[TMP111]], [[TMP79]]2199; CHECK-NEXT: [[TMP113:%.*]] = sub i32 [[TMP112]], [[TMP79]]2200; CHECK-NEXT: [[TMP114:%.*]] = insertelement <4 x i32> [[TMP76]], i32 [[TMP113]], i64 22201; CHECK-NEXT: [[TMP115:%.*]] = extractelement <4 x i32> [[X]], i64 32202; CHECK-NEXT: [[TMP116:%.*]] = extractelement <4 x i32> [[Y]], i64 32203; CHECK-NEXT: [[TMP117:%.*]] = ashr i32 [[TMP115]], 312204; CHECK-NEXT: [[TMP118:%.*]] = ashr i32 [[TMP116]], 312205; CHECK-NEXT: [[TMP119:%.*]] = add i32 [[TMP115]], [[TMP117]]2206; CHECK-NEXT: [[TMP120:%.*]] = add i32 [[TMP116]], [[TMP118]]2207; CHECK-NEXT: [[TMP121:%.*]] = xor i32 [[TMP119]], [[TMP117]]2208; CHECK-NEXT: [[TMP122:%.*]] = xor i32 [[TMP120]], [[TMP118]]2209; CHECK-NEXT: [[TMP123:%.*]] = uitofp i32 [[TMP122]] to float2210; CHECK-NEXT: [[TMP124:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP123]])2211; CHECK-NEXT: [[TMP125:%.*]] = fmul fast float [[TMP124]], 0x41EFFFFFC00000002212; CHECK-NEXT: [[TMP126:%.*]] = fptoui float [[TMP125]] to i322213; CHECK-NEXT: [[TMP127:%.*]] = sub i32 0, [[TMP122]]2214; CHECK-NEXT: [[TMP128:%.*]] = mul i32 [[TMP127]], [[TMP126]]2215; CHECK-NEXT: [[TMP129:%.*]] = zext i32 [[TMP126]] to i642216; CHECK-NEXT: [[TMP130:%.*]] = zext i32 [[TMP128]] to i642217; CHECK-NEXT: [[TMP131:%.*]] = mul i64 [[TMP129]], [[TMP130]]2218; CHECK-NEXT: [[TMP132:%.*]] = trunc i64 [[TMP131]] to i322219; CHECK-NEXT: [[TMP133:%.*]] = lshr i64 [[TMP131]], 322220; CHECK-NEXT: [[TMP134:%.*]] = trunc i64 [[TMP133]] to i322221; CHECK-NEXT: [[TMP135:%.*]] = add i32 [[TMP126]], [[TMP134]]2222; CHECK-NEXT: [[TMP136:%.*]] = zext i32 [[TMP121]] to i642223; CHECK-NEXT: [[TMP137:%.*]] = zext i32 [[TMP135]] to i642224; CHECK-NEXT: [[TMP138:%.*]] = mul i64 [[TMP136]], [[TMP137]]2225; CHECK-NEXT: [[TMP139:%.*]] = trunc i64 [[TMP138]] to i322226; CHECK-NEXT: [[TMP140:%.*]] = lshr i64 [[TMP138]], 322227; CHECK-NEXT: [[TMP141:%.*]] = trunc i64 [[TMP140]] to i322228; CHECK-NEXT: [[TMP142:%.*]] = mul i32 [[TMP141]], [[TMP122]]2229; CHECK-NEXT: [[TMP143:%.*]] = sub i32 [[TMP121]], [[TMP142]]2230; CHECK-NEXT: [[TMP144:%.*]] = icmp uge i32 [[TMP143]], [[TMP122]]2231; CHECK-NEXT: [[TMP145:%.*]] = sub i32 [[TMP143]], [[TMP122]]2232; CHECK-NEXT: [[TMP146:%.*]] = select i1 [[TMP144]], i32 [[TMP145]], i32 [[TMP143]]2233; CHECK-NEXT: [[TMP147:%.*]] = icmp uge i32 [[TMP146]], [[TMP122]]2234; CHECK-NEXT: [[TMP148:%.*]] = sub i32 [[TMP146]], [[TMP122]]2235; CHECK-NEXT: [[TMP149:%.*]] = select i1 [[TMP147]], i32 [[TMP148]], i32 [[TMP146]]2236; CHECK-NEXT: [[TMP150:%.*]] = xor i32 [[TMP149]], [[TMP117]]2237; CHECK-NEXT: [[TMP151:%.*]] = sub i32 [[TMP150]], [[TMP117]]2238; CHECK-NEXT: [[TMP152:%.*]] = insertelement <4 x i32> [[TMP114]], i32 [[TMP151]], i64 32239; CHECK-NEXT: store <4 x i32> [[TMP152]], ptr addrspace(1) [[OUT:%.*]], align 162240; CHECK-NEXT: ret void2241;2242; GFX6-LABEL: srem_v4i32:2243; GFX6: ; %bb.0:2244; GFX6-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0xd2245; GFX6-NEXT: s_waitcnt lgkmcnt(0)2246; GFX6-NEXT: s_abs_i32 s0, s122247; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s02248; GFX6-NEXT: s_sub_i32 s1, 0, s02249; GFX6-NEXT: s_ashr_i32 s2, s8, 312250; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v02251; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v02252; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v02253; GFX6-NEXT: v_mul_lo_u32 v1, s1, v02254; GFX6-NEXT: s_abs_i32 s1, s82255; GFX6-NEXT: v_mul_hi_u32 v1, v0, v12256; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v12257; GFX6-NEXT: v_mul_hi_u32 v0, s1, v02258; GFX6-NEXT: v_readfirstlane_b32 s3, v02259; GFX6-NEXT: s_mul_i32 s3, s3, s02260; GFX6-NEXT: s_sub_i32 s1, s1, s32261; GFX6-NEXT: s_sub_i32 s3, s1, s02262; GFX6-NEXT: s_cmp_ge_u32 s1, s02263; GFX6-NEXT: s_cselect_b32 s1, s3, s12264; GFX6-NEXT: s_sub_i32 s3, s1, s02265; GFX6-NEXT: s_cmp_ge_u32 s1, s02266; GFX6-NEXT: s_cselect_b32 s0, s3, s12267; GFX6-NEXT: s_abs_i32 s1, s132268; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s12269; GFX6-NEXT: s_sub_i32 s3, 0, s12270; GFX6-NEXT: s_xor_b32 s0, s0, s22271; GFX6-NEXT: s_sub_i32 s7, s0, s22272; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v02273; GFX6-NEXT: s_ashr_i32 s6, s9, 312274; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v02275; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v02276; GFX6-NEXT: v_mul_lo_u32 v1, s3, v02277; GFX6-NEXT: s_abs_i32 s3, s92278; GFX6-NEXT: v_mul_hi_u32 v1, v0, v12279; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v12280; GFX6-NEXT: v_mul_hi_u32 v0, s3, v02281; GFX6-NEXT: v_readfirstlane_b32 s0, v02282; GFX6-NEXT: s_mul_i32 s0, s0, s12283; GFX6-NEXT: s_sub_i32 s0, s3, s02284; GFX6-NEXT: s_sub_i32 s2, s0, s12285; GFX6-NEXT: s_cmp_ge_u32 s0, s12286; GFX6-NEXT: s_cselect_b32 s0, s2, s02287; GFX6-NEXT: s_sub_i32 s2, s0, s12288; GFX6-NEXT: s_cmp_ge_u32 s0, s12289; GFX6-NEXT: s_cselect_b32 s0, s2, s02290; GFX6-NEXT: s_abs_i32 s1, s142291; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s12292; GFX6-NEXT: s_sub_i32 s2, 0, s12293; GFX6-NEXT: s_xor_b32 s0, s0, s62294; GFX6-NEXT: s_sub_i32 s6, s0, s62295; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v02296; GFX6-NEXT: s_ashr_i32 s8, s10, 312297; GFX6-NEXT: s_mov_b32 s3, 0xf0002298; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v02299; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v02300; GFX6-NEXT: v_mul_lo_u32 v1, s2, v02301; GFX6-NEXT: s_abs_i32 s2, s102302; GFX6-NEXT: v_mul_hi_u32 v1, v0, v12303; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v12304; GFX6-NEXT: v_mul_hi_u32 v0, s2, v02305; GFX6-NEXT: v_readfirstlane_b32 s0, v02306; GFX6-NEXT: s_mul_i32 s0, s0, s12307; GFX6-NEXT: s_sub_i32 s0, s2, s02308; GFX6-NEXT: s_sub_i32 s2, s0, s12309; GFX6-NEXT: s_cmp_ge_u32 s0, s12310; GFX6-NEXT: s_cselect_b32 s0, s2, s02311; GFX6-NEXT: s_sub_i32 s2, s0, s12312; GFX6-NEXT: s_cmp_ge_u32 s0, s12313; GFX6-NEXT: s_cselect_b32 s9, s2, s02314; GFX6-NEXT: s_abs_i32 s10, s152315; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s102316; GFX6-NEXT: s_sub_i32 s0, 0, s102317; GFX6-NEXT: s_mov_b32 s2, -12318; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v02319; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v02320; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v02321; GFX6-NEXT: v_mov_b32_e32 v0, s72322; GFX6-NEXT: v_mul_lo_u32 v1, s0, v22323; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x92324; GFX6-NEXT: s_abs_i32 s4, s112325; GFX6-NEXT: s_ashr_i32 s5, s11, 312326; GFX6-NEXT: v_mul_hi_u32 v3, v2, v12327; GFX6-NEXT: v_mov_b32_e32 v1, s62328; GFX6-NEXT: s_xor_b32 s6, s9, s82329; GFX6-NEXT: s_sub_i32 s6, s6, s82330; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v32331; GFX6-NEXT: v_mul_hi_u32 v2, s4, v22332; GFX6-NEXT: v_readfirstlane_b32 s7, v22333; GFX6-NEXT: s_mul_i32 s7, s7, s102334; GFX6-NEXT: s_sub_i32 s4, s4, s72335; GFX6-NEXT: s_sub_i32 s7, s4, s102336; GFX6-NEXT: s_cmp_ge_u32 s4, s102337; GFX6-NEXT: s_cselect_b32 s4, s7, s42338; GFX6-NEXT: s_sub_i32 s7, s4, s102339; GFX6-NEXT: s_cmp_ge_u32 s4, s102340; GFX6-NEXT: s_cselect_b32 s4, s7, s42341; GFX6-NEXT: s_xor_b32 s4, s4, s52342; GFX6-NEXT: s_sub_i32 s4, s4, s52343; GFX6-NEXT: v_mov_b32_e32 v2, s62344; GFX6-NEXT: v_mov_b32_e32 v3, s42345; GFX6-NEXT: s_waitcnt lgkmcnt(0)2346; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 02347; GFX6-NEXT: s_endpgm2348;2349; GFX9-LABEL: srem_v4i32:2350; GFX9: ; %bb.0:2351; GFX9-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x342352; GFX9-NEXT: v_mov_b32_e32 v4, 02353; GFX9-NEXT: s_waitcnt lgkmcnt(0)2354; GFX9-NEXT: s_abs_i32 s0, s122355; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s02356; GFX9-NEXT: s_sub_i32 s3, 0, s02357; GFX9-NEXT: s_abs_i32 s2, s82358; GFX9-NEXT: s_ashr_i32 s1, s8, 312359; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v02360; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v02361; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v02362; GFX9-NEXT: v_readfirstlane_b32 s6, v02363; GFX9-NEXT: s_mul_i32 s3, s3, s62364; GFX9-NEXT: s_mul_hi_u32 s3, s6, s32365; GFX9-NEXT: s_add_i32 s6, s6, s32366; GFX9-NEXT: s_mul_hi_u32 s3, s2, s62367; GFX9-NEXT: s_mul_i32 s3, s3, s02368; GFX9-NEXT: s_sub_i32 s2, s2, s32369; GFX9-NEXT: s_sub_i32 s3, s2, s02370; GFX9-NEXT: s_cmp_ge_u32 s2, s02371; GFX9-NEXT: s_cselect_b32 s2, s3, s22372; GFX9-NEXT: s_sub_i32 s3, s2, s02373; GFX9-NEXT: s_cmp_ge_u32 s2, s02374; GFX9-NEXT: s_cselect_b32 s0, s3, s22375; GFX9-NEXT: s_abs_i32 s2, s132376; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s22377; GFX9-NEXT: s_xor_b32 s0, s0, s12378; GFX9-NEXT: s_sub_i32 s7, 0, s22379; GFX9-NEXT: s_sub_i32 s8, s0, s12380; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v02381; GFX9-NEXT: s_abs_i32 s6, s92382; GFX9-NEXT: s_ashr_i32 s3, s9, 312383; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v02384; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v02385; GFX9-NEXT: v_readfirstlane_b32 s0, v02386; GFX9-NEXT: s_mul_i32 s7, s7, s02387; GFX9-NEXT: s_mul_hi_u32 s1, s0, s72388; GFX9-NEXT: s_add_i32 s0, s0, s12389; GFX9-NEXT: s_mul_hi_u32 s0, s6, s02390; GFX9-NEXT: s_mul_i32 s0, s0, s22391; GFX9-NEXT: s_sub_i32 s0, s6, s02392; GFX9-NEXT: s_sub_i32 s1, s0, s22393; GFX9-NEXT: s_cmp_ge_u32 s0, s22394; GFX9-NEXT: s_cselect_b32 s0, s1, s02395; GFX9-NEXT: s_sub_i32 s1, s0, s22396; GFX9-NEXT: s_cmp_ge_u32 s0, s22397; GFX9-NEXT: s_cselect_b32 s0, s1, s02398; GFX9-NEXT: s_abs_i32 s1, s142399; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s12400; GFX9-NEXT: s_xor_b32 s0, s0, s32401; GFX9-NEXT: s_sub_i32 s7, 0, s12402; GFX9-NEXT: s_sub_i32 s3, s0, s32403; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v02404; GFX9-NEXT: s_abs_i32 s6, s102405; GFX9-NEXT: s_ashr_i32 s2, s10, 312406; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v02407; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v02408; GFX9-NEXT: v_readfirstlane_b32 s0, v02409; GFX9-NEXT: s_mul_i32 s7, s7, s02410; GFX9-NEXT: s_mul_hi_u32 s7, s0, s72411; GFX9-NEXT: s_add_i32 s0, s0, s72412; GFX9-NEXT: s_mul_hi_u32 s0, s6, s02413; GFX9-NEXT: s_mul_i32 s0, s0, s12414; GFX9-NEXT: s_sub_i32 s0, s6, s02415; GFX9-NEXT: s_sub_i32 s6, s0, s12416; GFX9-NEXT: s_cmp_ge_u32 s0, s12417; GFX9-NEXT: s_cselect_b32 s0, s6, s02418; GFX9-NEXT: s_sub_i32 s6, s0, s12419; GFX9-NEXT: s_cmp_ge_u32 s0, s12420; GFX9-NEXT: s_cselect_b32 s6, s6, s02421; GFX9-NEXT: s_abs_i32 s7, s152422; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s72423; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x242424; GFX9-NEXT: s_xor_b32 s5, s6, s22425; GFX9-NEXT: s_sub_i32 s6, 0, s72426; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v12427; GFX9-NEXT: s_sub_i32 s2, s5, s22428; GFX9-NEXT: s_abs_i32 s4, s112429; GFX9-NEXT: v_mov_b32_e32 v1, s32430; GFX9-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v22431; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v22432; GFX9-NEXT: s_ashr_i32 s3, s11, 312433; GFX9-NEXT: v_mov_b32_e32 v0, s82434; GFX9-NEXT: v_readfirstlane_b32 s5, v22435; GFX9-NEXT: s_mul_i32 s6, s6, s52436; GFX9-NEXT: s_mul_hi_u32 s6, s5, s62437; GFX9-NEXT: s_add_i32 s5, s5, s62438; GFX9-NEXT: s_mul_hi_u32 s5, s4, s52439; GFX9-NEXT: s_mul_i32 s5, s5, s72440; GFX9-NEXT: s_sub_i32 s4, s4, s52441; GFX9-NEXT: s_sub_i32 s5, s4, s72442; GFX9-NEXT: s_cmp_ge_u32 s4, s72443; GFX9-NEXT: s_cselect_b32 s4, s5, s42444; GFX9-NEXT: s_sub_i32 s5, s4, s72445; GFX9-NEXT: s_cmp_ge_u32 s4, s72446; GFX9-NEXT: s_cselect_b32 s4, s5, s42447; GFX9-NEXT: s_xor_b32 s4, s4, s32448; GFX9-NEXT: s_sub_i32 s3, s4, s32449; GFX9-NEXT: v_mov_b32_e32 v2, s22450; GFX9-NEXT: v_mov_b32_e32 v3, s32451; GFX9-NEXT: s_waitcnt lgkmcnt(0)2452; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]2453; GFX9-NEXT: s_endpgm2454 %r = srem <4 x i32> %x, %y2455 store <4 x i32> %r, ptr addrspace(1) %out2456 ret void2457}2458 2459define amdgpu_kernel void @udiv_v4i16(ptr addrspace(1) %out, <4 x i16> %x, <4 x i16> %y) {2460; CHECK-LABEL: @udiv_v4i16(2461; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i16> [[X:%.*]], i64 02462; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i16> [[Y:%.*]], i64 02463; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[TMP1]] to i322464; CHECK-NEXT: [[TMP4:%.*]] = zext i16 [[TMP2]] to i322465; CHECK-NEXT: [[TMP5:%.*]] = uitofp i32 [[TMP3]] to float2466; CHECK-NEXT: [[TMP6:%.*]] = uitofp i32 [[TMP4]] to float2467; CHECK-NEXT: [[TMP7:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP6]])2468; CHECK-NEXT: [[TMP8:%.*]] = fmul fast float [[TMP5]], [[TMP7]]2469; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.trunc.f32(float [[TMP8]])2470; CHECK-NEXT: [[TMP10:%.*]] = fneg fast float [[TMP9]]2471; CHECK-NEXT: [[TMP11:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP10]], float [[TMP6]], float [[TMP5]])2472; CHECK-NEXT: [[TMP12:%.*]] = fptoui float [[TMP9]] to i322473; CHECK-NEXT: [[TMP13:%.*]] = call fast float @llvm.fabs.f32(float [[TMP11]])2474; CHECK-NEXT: [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP6]])2475; CHECK-NEXT: [[TMP15:%.*]] = fcmp fast oge float [[TMP13]], [[TMP14]]2476; CHECK-NEXT: [[TMP16:%.*]] = select i1 [[TMP15]], i32 1, i32 02477; CHECK-NEXT: [[TMP17:%.*]] = add i32 [[TMP12]], [[TMP16]]2478; CHECK-NEXT: [[TMP18:%.*]] = and i32 [[TMP17]], 655352479; CHECK-NEXT: [[TMP19:%.*]] = trunc i32 [[TMP18]] to i162480; CHECK-NEXT: [[TMP20:%.*]] = insertelement <4 x i16> poison, i16 [[TMP19]], i64 02481; CHECK-NEXT: [[TMP21:%.*]] = extractelement <4 x i16> [[X]], i64 12482; CHECK-NEXT: [[TMP22:%.*]] = extractelement <4 x i16> [[Y]], i64 12483; CHECK-NEXT: [[TMP23:%.*]] = zext i16 [[TMP21]] to i322484; CHECK-NEXT: [[TMP24:%.*]] = zext i16 [[TMP22]] to i322485; CHECK-NEXT: [[TMP25:%.*]] = uitofp i32 [[TMP23]] to float2486; CHECK-NEXT: [[TMP26:%.*]] = uitofp i32 [[TMP24]] to float2487; CHECK-NEXT: [[TMP27:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP26]])2488; CHECK-NEXT: [[TMP28:%.*]] = fmul fast float [[TMP25]], [[TMP27]]2489; CHECK-NEXT: [[TMP29:%.*]] = call fast float @llvm.trunc.f32(float [[TMP28]])2490; CHECK-NEXT: [[TMP30:%.*]] = fneg fast float [[TMP29]]2491; CHECK-NEXT: [[TMP31:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP30]], float [[TMP26]], float [[TMP25]])2492; CHECK-NEXT: [[TMP32:%.*]] = fptoui float [[TMP29]] to i322493; CHECK-NEXT: [[TMP33:%.*]] = call fast float @llvm.fabs.f32(float [[TMP31]])2494; CHECK-NEXT: [[TMP34:%.*]] = call fast float @llvm.fabs.f32(float [[TMP26]])2495; CHECK-NEXT: [[TMP35:%.*]] = fcmp fast oge float [[TMP33]], [[TMP34]]2496; CHECK-NEXT: [[TMP36:%.*]] = select i1 [[TMP35]], i32 1, i32 02497; CHECK-NEXT: [[TMP37:%.*]] = add i32 [[TMP32]], [[TMP36]]2498; CHECK-NEXT: [[TMP38:%.*]] = and i32 [[TMP37]], 655352499; CHECK-NEXT: [[TMP39:%.*]] = trunc i32 [[TMP38]] to i162500; CHECK-NEXT: [[TMP40:%.*]] = insertelement <4 x i16> [[TMP20]], i16 [[TMP39]], i64 12501; CHECK-NEXT: [[TMP41:%.*]] = extractelement <4 x i16> [[X]], i64 22502; CHECK-NEXT: [[TMP42:%.*]] = extractelement <4 x i16> [[Y]], i64 22503; CHECK-NEXT: [[TMP43:%.*]] = zext i16 [[TMP41]] to i322504; CHECK-NEXT: [[TMP44:%.*]] = zext i16 [[TMP42]] to i322505; CHECK-NEXT: [[TMP45:%.*]] = uitofp i32 [[TMP43]] to float2506; CHECK-NEXT: [[TMP46:%.*]] = uitofp i32 [[TMP44]] to float2507; CHECK-NEXT: [[TMP47:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP46]])2508; CHECK-NEXT: [[TMP48:%.*]] = fmul fast float [[TMP45]], [[TMP47]]2509; CHECK-NEXT: [[TMP49:%.*]] = call fast float @llvm.trunc.f32(float [[TMP48]])2510; CHECK-NEXT: [[TMP50:%.*]] = fneg fast float [[TMP49]]2511; CHECK-NEXT: [[TMP51:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP50]], float [[TMP46]], float [[TMP45]])2512; CHECK-NEXT: [[TMP52:%.*]] = fptoui float [[TMP49]] to i322513; CHECK-NEXT: [[TMP53:%.*]] = call fast float @llvm.fabs.f32(float [[TMP51]])2514; CHECK-NEXT: [[TMP54:%.*]] = call fast float @llvm.fabs.f32(float [[TMP46]])2515; CHECK-NEXT: [[TMP55:%.*]] = fcmp fast oge float [[TMP53]], [[TMP54]]2516; CHECK-NEXT: [[TMP56:%.*]] = select i1 [[TMP55]], i32 1, i32 02517; CHECK-NEXT: [[TMP57:%.*]] = add i32 [[TMP52]], [[TMP56]]2518; CHECK-NEXT: [[TMP58:%.*]] = and i32 [[TMP57]], 655352519; CHECK-NEXT: [[TMP59:%.*]] = trunc i32 [[TMP58]] to i162520; CHECK-NEXT: [[TMP60:%.*]] = insertelement <4 x i16> [[TMP40]], i16 [[TMP59]], i64 22521; CHECK-NEXT: [[TMP61:%.*]] = extractelement <4 x i16> [[X]], i64 32522; CHECK-NEXT: [[TMP62:%.*]] = extractelement <4 x i16> [[Y]], i64 32523; CHECK-NEXT: [[TMP63:%.*]] = zext i16 [[TMP61]] to i322524; CHECK-NEXT: [[TMP64:%.*]] = zext i16 [[TMP62]] to i322525; CHECK-NEXT: [[TMP65:%.*]] = uitofp i32 [[TMP63]] to float2526; CHECK-NEXT: [[TMP66:%.*]] = uitofp i32 [[TMP64]] to float2527; CHECK-NEXT: [[TMP67:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP66]])2528; CHECK-NEXT: [[TMP68:%.*]] = fmul fast float [[TMP65]], [[TMP67]]2529; CHECK-NEXT: [[TMP69:%.*]] = call fast float @llvm.trunc.f32(float [[TMP68]])2530; CHECK-NEXT: [[TMP70:%.*]] = fneg fast float [[TMP69]]2531; CHECK-NEXT: [[TMP71:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP70]], float [[TMP66]], float [[TMP65]])2532; CHECK-NEXT: [[TMP72:%.*]] = fptoui float [[TMP69]] to i322533; CHECK-NEXT: [[TMP73:%.*]] = call fast float @llvm.fabs.f32(float [[TMP71]])2534; CHECK-NEXT: [[TMP74:%.*]] = call fast float @llvm.fabs.f32(float [[TMP66]])2535; CHECK-NEXT: [[TMP75:%.*]] = fcmp fast oge float [[TMP73]], [[TMP74]]2536; CHECK-NEXT: [[TMP76:%.*]] = select i1 [[TMP75]], i32 1, i32 02537; CHECK-NEXT: [[TMP77:%.*]] = add i32 [[TMP72]], [[TMP76]]2538; CHECK-NEXT: [[TMP78:%.*]] = and i32 [[TMP77]], 655352539; CHECK-NEXT: [[TMP79:%.*]] = trunc i32 [[TMP78]] to i162540; CHECK-NEXT: [[TMP80:%.*]] = insertelement <4 x i16> [[TMP60]], i16 [[TMP79]], i64 32541; CHECK-NEXT: store <4 x i16> [[TMP80]], ptr addrspace(1) [[OUT:%.*]], align 82542; CHECK-NEXT: ret void2543;2544; GFX6-LABEL: udiv_v4i16:2545; GFX6: ; %bb.0:2546; GFX6-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0xb2547; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x92548; GFX6-NEXT: s_mov_b32 s3, 0xf0002549; GFX6-NEXT: s_mov_b32 s2, -12550; GFX6-NEXT: s_waitcnt lgkmcnt(0)2551; GFX6-NEXT: s_and_b32 s5, s10, 0xffff2552; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s52553; GFX6-NEXT: s_lshr_b32 s5, s10, 162554; GFX6-NEXT: s_and_b32 s4, s8, 0xffff2555; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s52556; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s42557; GFX6-NEXT: v_rcp_iflag_f32_e32 v3, v02558; GFX6-NEXT: s_lshr_b32 s4, s8, 162559; GFX6-NEXT: v_cvt_f32_u32_e32 v4, s42560; GFX6-NEXT: v_rcp_iflag_f32_e32 v5, v22561; GFX6-NEXT: v_mul_f32_e32 v3, v1, v32562; GFX6-NEXT: v_trunc_f32_e32 v3, v32563; GFX6-NEXT: v_mad_f32 v1, -v3, v0, v12564; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v02565; GFX6-NEXT: v_mul_f32_e32 v1, v4, v52566; GFX6-NEXT: v_trunc_f32_e32 v1, v12567; GFX6-NEXT: s_and_b32 s4, s11, 0xffff2568; GFX6-NEXT: v_cvt_u32_f32_e32 v6, v32569; GFX6-NEXT: v_mad_f32 v3, -v1, v2, v42570; GFX6-NEXT: v_cvt_f32_u32_e32 v4, s42571; GFX6-NEXT: s_and_b32 s4, s9, 0xffff2572; GFX6-NEXT: v_addc_u32_e32 v0, vcc, 0, v6, vcc2573; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v12574; GFX6-NEXT: v_cvt_f32_u32_e32 v5, s42575; GFX6-NEXT: v_rcp_iflag_f32_e32 v6, v42576; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v22577; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v1, vcc2578; GFX6-NEXT: v_mul_f32_e32 v1, v5, v62579; GFX6-NEXT: v_trunc_f32_e32 v1, v12580; GFX6-NEXT: s_lshr_b32 s4, s11, 162581; GFX6-NEXT: v_mad_f32 v3, -v1, v4, v52582; GFX6-NEXT: v_cvt_f32_u32_e32 v5, s42583; GFX6-NEXT: s_lshr_b32 s4, s9, 162584; GFX6-NEXT: v_cvt_f32_u32_e32 v6, s42585; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v12586; GFX6-NEXT: v_rcp_iflag_f32_e32 v7, v52587; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v42588; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v22589; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2590; GFX6-NEXT: v_mul_f32_e32 v3, v6, v72591; GFX6-NEXT: v_trunc_f32_e32 v3, v32592; GFX6-NEXT: v_cvt_u32_f32_e32 v4, v32593; GFX6-NEXT: v_mad_f32 v3, -v3, v5, v62594; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v52595; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v12596; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc2597; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v32598; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v02599; GFX6-NEXT: v_or_b32_e32 v1, v1, v32600; GFX6-NEXT: v_or_b32_e32 v0, v0, v22601; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 02602; GFX6-NEXT: s_endpgm2603;2604; GFX9-LABEL: udiv_v4i16:2605; GFX9: ; %bb.0:2606; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c2607; GFX9-NEXT: v_mov_b32_e32 v6, 02608; GFX9-NEXT: s_waitcnt lgkmcnt(0)2609; GFX9-NEXT: s_and_b32 s7, s2, 0xffff2610; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s72611; GFX9-NEXT: s_and_b32 s6, s0, 0xffff2612; GFX9-NEXT: s_lshr_b32 s2, s2, 162613; GFX9-NEXT: v_cvt_f32_u32_e32 v2, s62614; GFX9-NEXT: v_rcp_iflag_f32_e32 v4, v02615; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s22616; GFX9-NEXT: s_lshr_b32 s0, s0, 162617; GFX9-NEXT: v_cvt_f32_u32_e32 v3, s02618; GFX9-NEXT: v_mul_f32_e32 v4, v2, v42619; GFX9-NEXT: v_rcp_iflag_f32_e32 v5, v12620; GFX9-NEXT: v_trunc_f32_e32 v4, v42621; GFX9-NEXT: s_and_b32 s0, s3, 0xffff2622; GFX9-NEXT: v_cvt_u32_f32_e32 v7, v42623; GFX9-NEXT: v_mad_f32 v2, -v4, v0, v22624; GFX9-NEXT: v_cvt_f32_u32_e32 v4, s02625; GFX9-NEXT: v_mul_f32_e32 v5, v3, v52626; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v02627; GFX9-NEXT: s_and_b32 s0, s1, 0xffff2628; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, 0, v7, vcc2629; GFX9-NEXT: v_trunc_f32_e32 v2, v52630; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s02631; GFX9-NEXT: v_rcp_iflag_f32_e32 v7, v42632; GFX9-NEXT: v_mad_f32 v3, -v2, v1, v32633; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v12634; GFX9-NEXT: s_lshr_b32 s0, s3, 162635; GFX9-NEXT: v_mul_f32_e32 v1, v5, v72636; GFX9-NEXT: v_trunc_f32_e32 v1, v12637; GFX9-NEXT: v_mad_f32 v3, -v1, v4, v52638; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s02639; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v22640; GFX9-NEXT: s_lshr_b32 s0, s1, 162641; GFX9-NEXT: v_cvt_f32_u32_e32 v7, s02642; GFX9-NEXT: v_rcp_iflag_f32_e32 v8, v52643; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v2, vcc2644; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v12645; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v42646; GFX9-NEXT: v_mul_f32_e32 v3, v7, v82647; GFX9-NEXT: v_trunc_f32_e32 v3, v32648; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v32649; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x242650; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc2651; GFX9-NEXT: v_mad_f32 v3, -v3, v5, v72652; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v52653; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc2654; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v12655; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v02656; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v12657; GFX9-NEXT: v_lshl_or_b32 v0, v2, 16, v02658; GFX9-NEXT: s_waitcnt lgkmcnt(0)2659; GFX9-NEXT: global_store_dwordx2 v6, v[0:1], s[6:7]2660; GFX9-NEXT: s_endpgm2661 %r = udiv <4 x i16> %x, %y2662 store <4 x i16> %r, ptr addrspace(1) %out2663 ret void2664}2665 2666define amdgpu_kernel void @urem_v4i16(ptr addrspace(1) %out, <4 x i16> %x, <4 x i16> %y) {2667; CHECK-LABEL: @urem_v4i16(2668; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i16> [[X:%.*]], i64 02669; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i16> [[Y:%.*]], i64 02670; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[TMP1]] to i322671; CHECK-NEXT: [[TMP4:%.*]] = zext i16 [[TMP2]] to i322672; CHECK-NEXT: [[TMP5:%.*]] = uitofp i32 [[TMP3]] to float2673; CHECK-NEXT: [[TMP6:%.*]] = uitofp i32 [[TMP4]] to float2674; CHECK-NEXT: [[TMP7:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP6]])2675; CHECK-NEXT: [[TMP8:%.*]] = fmul fast float [[TMP5]], [[TMP7]]2676; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.trunc.f32(float [[TMP8]])2677; CHECK-NEXT: [[TMP10:%.*]] = fneg fast float [[TMP9]]2678; CHECK-NEXT: [[TMP11:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP10]], float [[TMP6]], float [[TMP5]])2679; CHECK-NEXT: [[TMP12:%.*]] = fptoui float [[TMP9]] to i322680; CHECK-NEXT: [[TMP13:%.*]] = call fast float @llvm.fabs.f32(float [[TMP11]])2681; CHECK-NEXT: [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP6]])2682; CHECK-NEXT: [[TMP15:%.*]] = fcmp fast oge float [[TMP13]], [[TMP14]]2683; CHECK-NEXT: [[TMP16:%.*]] = select i1 [[TMP15]], i32 1, i32 02684; CHECK-NEXT: [[TMP17:%.*]] = add i32 [[TMP12]], [[TMP16]]2685; CHECK-NEXT: [[TMP18:%.*]] = mul i32 [[TMP17]], [[TMP4]]2686; CHECK-NEXT: [[TMP19:%.*]] = sub i32 [[TMP3]], [[TMP18]]2687; CHECK-NEXT: [[TMP20:%.*]] = and i32 [[TMP19]], 655352688; CHECK-NEXT: [[TMP21:%.*]] = trunc i32 [[TMP20]] to i162689; CHECK-NEXT: [[TMP22:%.*]] = insertelement <4 x i16> poison, i16 [[TMP21]], i64 02690; CHECK-NEXT: [[TMP23:%.*]] = extractelement <4 x i16> [[X]], i64 12691; CHECK-NEXT: [[TMP24:%.*]] = extractelement <4 x i16> [[Y]], i64 12692; CHECK-NEXT: [[TMP25:%.*]] = zext i16 [[TMP23]] to i322693; CHECK-NEXT: [[TMP26:%.*]] = zext i16 [[TMP24]] to i322694; CHECK-NEXT: [[TMP27:%.*]] = uitofp i32 [[TMP25]] to float2695; CHECK-NEXT: [[TMP28:%.*]] = uitofp i32 [[TMP26]] to float2696; CHECK-NEXT: [[TMP29:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP28]])2697; CHECK-NEXT: [[TMP30:%.*]] = fmul fast float [[TMP27]], [[TMP29]]2698; CHECK-NEXT: [[TMP31:%.*]] = call fast float @llvm.trunc.f32(float [[TMP30]])2699; CHECK-NEXT: [[TMP32:%.*]] = fneg fast float [[TMP31]]2700; CHECK-NEXT: [[TMP33:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP32]], float [[TMP28]], float [[TMP27]])2701; CHECK-NEXT: [[TMP34:%.*]] = fptoui float [[TMP31]] to i322702; CHECK-NEXT: [[TMP35:%.*]] = call fast float @llvm.fabs.f32(float [[TMP33]])2703; CHECK-NEXT: [[TMP36:%.*]] = call fast float @llvm.fabs.f32(float [[TMP28]])2704; CHECK-NEXT: [[TMP37:%.*]] = fcmp fast oge float [[TMP35]], [[TMP36]]2705; CHECK-NEXT: [[TMP38:%.*]] = select i1 [[TMP37]], i32 1, i32 02706; CHECK-NEXT: [[TMP39:%.*]] = add i32 [[TMP34]], [[TMP38]]2707; CHECK-NEXT: [[TMP40:%.*]] = mul i32 [[TMP39]], [[TMP26]]2708; CHECK-NEXT: [[TMP41:%.*]] = sub i32 [[TMP25]], [[TMP40]]2709; CHECK-NEXT: [[TMP42:%.*]] = and i32 [[TMP41]], 655352710; CHECK-NEXT: [[TMP43:%.*]] = trunc i32 [[TMP42]] to i162711; CHECK-NEXT: [[TMP44:%.*]] = insertelement <4 x i16> [[TMP22]], i16 [[TMP43]], i64 12712; CHECK-NEXT: [[TMP45:%.*]] = extractelement <4 x i16> [[X]], i64 22713; CHECK-NEXT: [[TMP46:%.*]] = extractelement <4 x i16> [[Y]], i64 22714; CHECK-NEXT: [[TMP47:%.*]] = zext i16 [[TMP45]] to i322715; CHECK-NEXT: [[TMP48:%.*]] = zext i16 [[TMP46]] to i322716; CHECK-NEXT: [[TMP49:%.*]] = uitofp i32 [[TMP47]] to float2717; CHECK-NEXT: [[TMP50:%.*]] = uitofp i32 [[TMP48]] to float2718; CHECK-NEXT: [[TMP51:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP50]])2719; CHECK-NEXT: [[TMP52:%.*]] = fmul fast float [[TMP49]], [[TMP51]]2720; CHECK-NEXT: [[TMP53:%.*]] = call fast float @llvm.trunc.f32(float [[TMP52]])2721; CHECK-NEXT: [[TMP54:%.*]] = fneg fast float [[TMP53]]2722; CHECK-NEXT: [[TMP55:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP54]], float [[TMP50]], float [[TMP49]])2723; CHECK-NEXT: [[TMP56:%.*]] = fptoui float [[TMP53]] to i322724; CHECK-NEXT: [[TMP57:%.*]] = call fast float @llvm.fabs.f32(float [[TMP55]])2725; CHECK-NEXT: [[TMP58:%.*]] = call fast float @llvm.fabs.f32(float [[TMP50]])2726; CHECK-NEXT: [[TMP59:%.*]] = fcmp fast oge float [[TMP57]], [[TMP58]]2727; CHECK-NEXT: [[TMP60:%.*]] = select i1 [[TMP59]], i32 1, i32 02728; CHECK-NEXT: [[TMP61:%.*]] = add i32 [[TMP56]], [[TMP60]]2729; CHECK-NEXT: [[TMP62:%.*]] = mul i32 [[TMP61]], [[TMP48]]2730; CHECK-NEXT: [[TMP63:%.*]] = sub i32 [[TMP47]], [[TMP62]]2731; CHECK-NEXT: [[TMP64:%.*]] = and i32 [[TMP63]], 655352732; CHECK-NEXT: [[TMP65:%.*]] = trunc i32 [[TMP64]] to i162733; CHECK-NEXT: [[TMP66:%.*]] = insertelement <4 x i16> [[TMP44]], i16 [[TMP65]], i64 22734; CHECK-NEXT: [[TMP67:%.*]] = extractelement <4 x i16> [[X]], i64 32735; CHECK-NEXT: [[TMP68:%.*]] = extractelement <4 x i16> [[Y]], i64 32736; CHECK-NEXT: [[TMP69:%.*]] = zext i16 [[TMP67]] to i322737; CHECK-NEXT: [[TMP70:%.*]] = zext i16 [[TMP68]] to i322738; CHECK-NEXT: [[TMP71:%.*]] = uitofp i32 [[TMP69]] to float2739; CHECK-NEXT: [[TMP72:%.*]] = uitofp i32 [[TMP70]] to float2740; CHECK-NEXT: [[TMP73:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP72]])2741; CHECK-NEXT: [[TMP74:%.*]] = fmul fast float [[TMP71]], [[TMP73]]2742; CHECK-NEXT: [[TMP75:%.*]] = call fast float @llvm.trunc.f32(float [[TMP74]])2743; CHECK-NEXT: [[TMP76:%.*]] = fneg fast float [[TMP75]]2744; CHECK-NEXT: [[TMP77:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP76]], float [[TMP72]], float [[TMP71]])2745; CHECK-NEXT: [[TMP78:%.*]] = fptoui float [[TMP75]] to i322746; CHECK-NEXT: [[TMP79:%.*]] = call fast float @llvm.fabs.f32(float [[TMP77]])2747; CHECK-NEXT: [[TMP80:%.*]] = call fast float @llvm.fabs.f32(float [[TMP72]])2748; CHECK-NEXT: [[TMP81:%.*]] = fcmp fast oge float [[TMP79]], [[TMP80]]2749; CHECK-NEXT: [[TMP82:%.*]] = select i1 [[TMP81]], i32 1, i32 02750; CHECK-NEXT: [[TMP83:%.*]] = add i32 [[TMP78]], [[TMP82]]2751; CHECK-NEXT: [[TMP84:%.*]] = mul i32 [[TMP83]], [[TMP70]]2752; CHECK-NEXT: [[TMP85:%.*]] = sub i32 [[TMP69]], [[TMP84]]2753; CHECK-NEXT: [[TMP86:%.*]] = and i32 [[TMP85]], 655352754; CHECK-NEXT: [[TMP87:%.*]] = trunc i32 [[TMP86]] to i162755; CHECK-NEXT: [[TMP88:%.*]] = insertelement <4 x i16> [[TMP66]], i16 [[TMP87]], i64 32756; CHECK-NEXT: store <4 x i16> [[TMP88]], ptr addrspace(1) [[OUT:%.*]], align 82757; CHECK-NEXT: ret void2758;2759; GFX6-LABEL: urem_v4i16:2760; GFX6: ; %bb.0:2761; GFX6-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0xb2762; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x92763; GFX6-NEXT: s_mov_b32 s3, 0xf0002764; GFX6-NEXT: s_mov_b32 s2, -12765; GFX6-NEXT: s_waitcnt lgkmcnt(0)2766; GFX6-NEXT: s_and_b32 s5, s10, 0xffff2767; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s52768; GFX6-NEXT: s_lshr_b32 s5, s10, 162769; GFX6-NEXT: s_and_b32 s4, s8, 0xffff2770; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s52771; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s42772; GFX6-NEXT: v_rcp_iflag_f32_e32 v3, v02773; GFX6-NEXT: s_lshr_b32 s4, s8, 162774; GFX6-NEXT: v_cvt_f32_u32_e32 v4, s42775; GFX6-NEXT: v_rcp_iflag_f32_e32 v5, v22776; GFX6-NEXT: v_mul_f32_e32 v3, v1, v32777; GFX6-NEXT: v_trunc_f32_e32 v3, v32778; GFX6-NEXT: v_cvt_u32_f32_e32 v6, v32779; GFX6-NEXT: v_mad_f32 v1, -v3, v0, v12780; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v02781; GFX6-NEXT: v_mul_f32_e32 v1, v4, v52782; GFX6-NEXT: v_trunc_f32_e32 v1, v12783; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v12784; GFX6-NEXT: v_addc_u32_e32 v0, vcc, 0, v6, vcc2785; GFX6-NEXT: v_mad_f32 v1, -v1, v2, v42786; GFX6-NEXT: s_and_b32 s6, s11, 0xffff2787; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v22788; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s62789; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc2790; GFX6-NEXT: v_mul_lo_u32 v1, v1, s52791; GFX6-NEXT: s_and_b32 s5, s9, 0xffff2792; GFX6-NEXT: v_cvt_f32_u32_e32 v3, s52793; GFX6-NEXT: v_rcp_iflag_f32_e32 v4, v22794; GFX6-NEXT: v_sub_i32_e32 v5, vcc, s4, v12795; GFX6-NEXT: s_lshr_b32 s4, s11, 162796; GFX6-NEXT: v_mul_f32_e32 v1, v3, v42797; GFX6-NEXT: v_cvt_f32_u32_e32 v4, s42798; GFX6-NEXT: v_mul_lo_u32 v0, v0, s102799; GFX6-NEXT: s_lshr_b32 s5, s9, 162800; GFX6-NEXT: v_cvt_f32_u32_e32 v6, s52801; GFX6-NEXT: v_rcp_iflag_f32_e32 v7, v42802; GFX6-NEXT: v_trunc_f32_e32 v1, v12803; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s8, v02804; GFX6-NEXT: v_mad_f32 v3, -v1, v2, v32805; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v12806; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v22807; GFX6-NEXT: v_mul_f32_e32 v2, v6, v72808; GFX6-NEXT: v_trunc_f32_e32 v2, v22809; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v22810; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2811; GFX6-NEXT: v_mad_f32 v2, -v2, v4, v62812; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v42813; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc2814; GFX6-NEXT: v_mul_lo_u32 v1, v1, s112815; GFX6-NEXT: v_mul_lo_u32 v2, v2, s42816; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v02817; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s9, v12818; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s5, v22819; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v22820; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v12821; GFX6-NEXT: v_or_b32_e32 v1, v1, v22822; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v52823; GFX6-NEXT: v_or_b32_e32 v0, v0, v22824; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 02825; GFX6-NEXT: s_endpgm2826;2827; GFX9-LABEL: urem_v4i16:2828; GFX9: ; %bb.0:2829; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c2830; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x242831; GFX9-NEXT: v_mov_b32_e32 v6, 02832; GFX9-NEXT: s_waitcnt lgkmcnt(0)2833; GFX9-NEXT: s_and_b32 s9, s2, 0xffff2834; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s92835; GFX9-NEXT: s_and_b32 s8, s0, 0xffff2836; GFX9-NEXT: s_lshr_b32 s2, s2, 162837; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s22838; GFX9-NEXT: v_cvt_f32_u32_e32 v2, s82839; GFX9-NEXT: v_rcp_iflag_f32_e32 v4, v02840; GFX9-NEXT: s_lshr_b32 s0, s0, 162841; GFX9-NEXT: v_cvt_f32_u32_e32 v3, s02842; GFX9-NEXT: v_rcp_iflag_f32_e32 v5, v12843; GFX9-NEXT: v_mul_f32_e32 v4, v2, v42844; GFX9-NEXT: v_trunc_f32_e32 v4, v42845; GFX9-NEXT: s_and_b32 s4, s3, 0xffff2846; GFX9-NEXT: v_cvt_u32_f32_e32 v7, v42847; GFX9-NEXT: v_mad_f32 v2, -v4, v0, v22848; GFX9-NEXT: v_cvt_f32_u32_e32 v4, s42849; GFX9-NEXT: v_mul_f32_e32 v5, v3, v52850; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v02851; GFX9-NEXT: v_trunc_f32_e32 v2, v52852; GFX9-NEXT: s_and_b32 s5, s1, 0xffff2853; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, 0, v7, vcc2854; GFX9-NEXT: v_mad_f32 v3, -v2, v1, v32855; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v22856; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s52857; GFX9-NEXT: v_rcp_iflag_f32_e32 v7, v42858; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v12859; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v2, vcc2860; GFX9-NEXT: v_mul_f32_e32 v2, v5, v72861; GFX9-NEXT: v_mul_lo_u32 v1, v1, s22862; GFX9-NEXT: v_trunc_f32_e32 v2, v22863; GFX9-NEXT: s_lshr_b32 s2, s3, 162864; GFX9-NEXT: v_mad_f32 v3, -v2, v4, v52865; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s22866; GFX9-NEXT: s_lshr_b32 s1, s1, 162867; GFX9-NEXT: v_cvt_f32_u32_e32 v7, s12868; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v22869; GFX9-NEXT: v_rcp_iflag_f32_e32 v8, v52870; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v42871; GFX9-NEXT: v_mul_lo_u32 v0, v0, s92872; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v2, vcc2873; GFX9-NEXT: v_mul_f32_e32 v3, v7, v82874; GFX9-NEXT: v_trunc_f32_e32 v3, v32875; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v32876; GFX9-NEXT: v_mad_f32 v3, -v3, v5, v72877; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v52878; GFX9-NEXT: v_mul_lo_u32 v2, v2, s42879; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc2880; GFX9-NEXT: v_mul_lo_u32 v3, v3, s22881; GFX9-NEXT: v_sub_u32_e32 v0, s8, v02882; GFX9-NEXT: v_sub_u32_e32 v4, s0, v12883; GFX9-NEXT: v_sub_u32_e32 v1, s5, v22884; GFX9-NEXT: v_sub_u32_e32 v2, s1, v32885; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v12886; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v02887; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v12888; GFX9-NEXT: v_lshl_or_b32 v0, v4, 16, v02889; GFX9-NEXT: global_store_dwordx2 v6, v[0:1], s[6:7]2890; GFX9-NEXT: s_endpgm2891 %r = urem <4 x i16> %x, %y2892 store <4 x i16> %r, ptr addrspace(1) %out2893 ret void2894}2895 2896define amdgpu_kernel void @sdiv_v4i16(ptr addrspace(1) %out, <4 x i16> %x, <4 x i16> %y) {2897; CHECK-LABEL: @sdiv_v4i16(2898; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i16> [[X:%.*]], i64 02899; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i16> [[Y:%.*]], i64 02900; CHECK-NEXT: [[TMP3:%.*]] = sext i16 [[TMP1]] to i322901; CHECK-NEXT: [[TMP4:%.*]] = sext i16 [[TMP2]] to i322902; CHECK-NEXT: [[TMP5:%.*]] = xor i32 [[TMP3]], [[TMP4]]2903; CHECK-NEXT: [[TMP6:%.*]] = ashr i32 [[TMP5]], 302904; CHECK-NEXT: [[TMP7:%.*]] = or i32 [[TMP6]], 12905; CHECK-NEXT: [[TMP8:%.*]] = sitofp i32 [[TMP3]] to float2906; CHECK-NEXT: [[TMP9:%.*]] = sitofp i32 [[TMP4]] to float2907; CHECK-NEXT: [[TMP10:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP9]])2908; CHECK-NEXT: [[TMP11:%.*]] = fmul fast float [[TMP8]], [[TMP10]]2909; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.trunc.f32(float [[TMP11]])2910; CHECK-NEXT: [[TMP13:%.*]] = fneg fast float [[TMP12]]2911; CHECK-NEXT: [[TMP14:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP13]], float [[TMP9]], float [[TMP8]])2912; CHECK-NEXT: [[TMP15:%.*]] = fptosi float [[TMP12]] to i322913; CHECK-NEXT: [[TMP16:%.*]] = call fast float @llvm.fabs.f32(float [[TMP14]])2914; CHECK-NEXT: [[TMP17:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])2915; CHECK-NEXT: [[TMP18:%.*]] = fcmp fast oge float [[TMP16]], [[TMP17]]2916; CHECK-NEXT: [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP7]], i32 02917; CHECK-NEXT: [[TMP20:%.*]] = add i32 [[TMP15]], [[TMP19]]2918; CHECK-NEXT: [[TMP21:%.*]] = shl i32 [[TMP20]], 162919; CHECK-NEXT: [[TMP22:%.*]] = ashr i32 [[TMP21]], 162920; CHECK-NEXT: [[TMP23:%.*]] = trunc i32 [[TMP22]] to i162921; CHECK-NEXT: [[TMP24:%.*]] = insertelement <4 x i16> poison, i16 [[TMP23]], i64 02922; CHECK-NEXT: [[TMP25:%.*]] = extractelement <4 x i16> [[X]], i64 12923; CHECK-NEXT: [[TMP26:%.*]] = extractelement <4 x i16> [[Y]], i64 12924; CHECK-NEXT: [[TMP27:%.*]] = sext i16 [[TMP25]] to i322925; CHECK-NEXT: [[TMP28:%.*]] = sext i16 [[TMP26]] to i322926; CHECK-NEXT: [[TMP29:%.*]] = xor i32 [[TMP27]], [[TMP28]]2927; CHECK-NEXT: [[TMP30:%.*]] = ashr i32 [[TMP29]], 302928; CHECK-NEXT: [[TMP31:%.*]] = or i32 [[TMP30]], 12929; CHECK-NEXT: [[TMP32:%.*]] = sitofp i32 [[TMP27]] to float2930; CHECK-NEXT: [[TMP33:%.*]] = sitofp i32 [[TMP28]] to float2931; CHECK-NEXT: [[TMP34:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP33]])2932; CHECK-NEXT: [[TMP35:%.*]] = fmul fast float [[TMP32]], [[TMP34]]2933; CHECK-NEXT: [[TMP36:%.*]] = call fast float @llvm.trunc.f32(float [[TMP35]])2934; CHECK-NEXT: [[TMP37:%.*]] = fneg fast float [[TMP36]]2935; CHECK-NEXT: [[TMP38:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP37]], float [[TMP33]], float [[TMP32]])2936; CHECK-NEXT: [[TMP39:%.*]] = fptosi float [[TMP36]] to i322937; CHECK-NEXT: [[TMP40:%.*]] = call fast float @llvm.fabs.f32(float [[TMP38]])2938; CHECK-NEXT: [[TMP41:%.*]] = call fast float @llvm.fabs.f32(float [[TMP33]])2939; CHECK-NEXT: [[TMP42:%.*]] = fcmp fast oge float [[TMP40]], [[TMP41]]2940; CHECK-NEXT: [[TMP43:%.*]] = select i1 [[TMP42]], i32 [[TMP31]], i32 02941; CHECK-NEXT: [[TMP44:%.*]] = add i32 [[TMP39]], [[TMP43]]2942; CHECK-NEXT: [[TMP45:%.*]] = shl i32 [[TMP44]], 162943; CHECK-NEXT: [[TMP46:%.*]] = ashr i32 [[TMP45]], 162944; CHECK-NEXT: [[TMP47:%.*]] = trunc i32 [[TMP46]] to i162945; CHECK-NEXT: [[TMP48:%.*]] = insertelement <4 x i16> [[TMP24]], i16 [[TMP47]], i64 12946; CHECK-NEXT: [[TMP49:%.*]] = extractelement <4 x i16> [[X]], i64 22947; CHECK-NEXT: [[TMP50:%.*]] = extractelement <4 x i16> [[Y]], i64 22948; CHECK-NEXT: [[TMP51:%.*]] = sext i16 [[TMP49]] to i322949; CHECK-NEXT: [[TMP52:%.*]] = sext i16 [[TMP50]] to i322950; CHECK-NEXT: [[TMP53:%.*]] = xor i32 [[TMP51]], [[TMP52]]2951; CHECK-NEXT: [[TMP54:%.*]] = ashr i32 [[TMP53]], 302952; CHECK-NEXT: [[TMP55:%.*]] = or i32 [[TMP54]], 12953; CHECK-NEXT: [[TMP56:%.*]] = sitofp i32 [[TMP51]] to float2954; CHECK-NEXT: [[TMP57:%.*]] = sitofp i32 [[TMP52]] to float2955; CHECK-NEXT: [[TMP58:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP57]])2956; CHECK-NEXT: [[TMP59:%.*]] = fmul fast float [[TMP56]], [[TMP58]]2957; CHECK-NEXT: [[TMP60:%.*]] = call fast float @llvm.trunc.f32(float [[TMP59]])2958; CHECK-NEXT: [[TMP61:%.*]] = fneg fast float [[TMP60]]2959; CHECK-NEXT: [[TMP62:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP61]], float [[TMP57]], float [[TMP56]])2960; CHECK-NEXT: [[TMP63:%.*]] = fptosi float [[TMP60]] to i322961; CHECK-NEXT: [[TMP64:%.*]] = call fast float @llvm.fabs.f32(float [[TMP62]])2962; CHECK-NEXT: [[TMP65:%.*]] = call fast float @llvm.fabs.f32(float [[TMP57]])2963; CHECK-NEXT: [[TMP66:%.*]] = fcmp fast oge float [[TMP64]], [[TMP65]]2964; CHECK-NEXT: [[TMP67:%.*]] = select i1 [[TMP66]], i32 [[TMP55]], i32 02965; CHECK-NEXT: [[TMP68:%.*]] = add i32 [[TMP63]], [[TMP67]]2966; CHECK-NEXT: [[TMP69:%.*]] = shl i32 [[TMP68]], 162967; CHECK-NEXT: [[TMP70:%.*]] = ashr i32 [[TMP69]], 162968; CHECK-NEXT: [[TMP71:%.*]] = trunc i32 [[TMP70]] to i162969; CHECK-NEXT: [[TMP72:%.*]] = insertelement <4 x i16> [[TMP48]], i16 [[TMP71]], i64 22970; CHECK-NEXT: [[TMP73:%.*]] = extractelement <4 x i16> [[X]], i64 32971; CHECK-NEXT: [[TMP74:%.*]] = extractelement <4 x i16> [[Y]], i64 32972; CHECK-NEXT: [[TMP75:%.*]] = sext i16 [[TMP73]] to i322973; CHECK-NEXT: [[TMP76:%.*]] = sext i16 [[TMP74]] to i322974; CHECK-NEXT: [[TMP77:%.*]] = xor i32 [[TMP75]], [[TMP76]]2975; CHECK-NEXT: [[TMP78:%.*]] = ashr i32 [[TMP77]], 302976; CHECK-NEXT: [[TMP79:%.*]] = or i32 [[TMP78]], 12977; CHECK-NEXT: [[TMP80:%.*]] = sitofp i32 [[TMP75]] to float2978; CHECK-NEXT: [[TMP81:%.*]] = sitofp i32 [[TMP76]] to float2979; CHECK-NEXT: [[TMP82:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP81]])2980; CHECK-NEXT: [[TMP83:%.*]] = fmul fast float [[TMP80]], [[TMP82]]2981; CHECK-NEXT: [[TMP84:%.*]] = call fast float @llvm.trunc.f32(float [[TMP83]])2982; CHECK-NEXT: [[TMP85:%.*]] = fneg fast float [[TMP84]]2983; CHECK-NEXT: [[TMP86:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP85]], float [[TMP81]], float [[TMP80]])2984; CHECK-NEXT: [[TMP87:%.*]] = fptosi float [[TMP84]] to i322985; CHECK-NEXT: [[TMP88:%.*]] = call fast float @llvm.fabs.f32(float [[TMP86]])2986; CHECK-NEXT: [[TMP89:%.*]] = call fast float @llvm.fabs.f32(float [[TMP81]])2987; CHECK-NEXT: [[TMP90:%.*]] = fcmp fast oge float [[TMP88]], [[TMP89]]2988; CHECK-NEXT: [[TMP91:%.*]] = select i1 [[TMP90]], i32 [[TMP79]], i32 02989; CHECK-NEXT: [[TMP92:%.*]] = add i32 [[TMP87]], [[TMP91]]2990; CHECK-NEXT: [[TMP93:%.*]] = shl i32 [[TMP92]], 162991; CHECK-NEXT: [[TMP94:%.*]] = ashr i32 [[TMP93]], 162992; CHECK-NEXT: [[TMP95:%.*]] = trunc i32 [[TMP94]] to i162993; CHECK-NEXT: [[TMP96:%.*]] = insertelement <4 x i16> [[TMP72]], i16 [[TMP95]], i64 32994; CHECK-NEXT: store <4 x i16> [[TMP96]], ptr addrspace(1) [[OUT:%.*]], align 82995; CHECK-NEXT: ret void2996;2997; GFX6-LABEL: sdiv_v4i16:2998; GFX6: ; %bb.0:2999; GFX6-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0xb3000; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x93001; GFX6-NEXT: s_mov_b32 s3, 0xf0003002; GFX6-NEXT: s_mov_b32 s2, -13003; GFX6-NEXT: s_waitcnt lgkmcnt(0)3004; GFX6-NEXT: s_sext_i32_i16 s4, s103005; GFX6-NEXT: v_cvt_f32_i32_e32 v0, s43006; GFX6-NEXT: s_sext_i32_i16 s5, s83007; GFX6-NEXT: v_cvt_f32_i32_e32 v1, s53008; GFX6-NEXT: s_xor_b32 s4, s5, s43009; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v03010; GFX6-NEXT: s_ashr_i32 s4, s4, 303011; GFX6-NEXT: s_or_b32 s6, s4, 13012; GFX6-NEXT: v_mul_f32_e32 v2, v1, v23013; GFX6-NEXT: v_trunc_f32_e32 v2, v23014; GFX6-NEXT: v_mad_f32 v1, -v2, v0, v13015; GFX6-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0|3016; GFX6-NEXT: s_and_b64 s[4:5], s[4:5], exec3017; GFX6-NEXT: v_cvt_i32_f32_e32 v2, v23018; GFX6-NEXT: s_cselect_b32 s4, s6, 03019; GFX6-NEXT: s_ashr_i32 s5, s10, 163020; GFX6-NEXT: v_cvt_f32_i32_e32 v0, s53021; GFX6-NEXT: v_add_i32_e32 v2, vcc, s4, v23022; GFX6-NEXT: s_ashr_i32 s4, s8, 163023; GFX6-NEXT: v_cvt_f32_i32_e32 v1, s43024; GFX6-NEXT: v_rcp_iflag_f32_e32 v3, v03025; GFX6-NEXT: s_xor_b32 s4, s4, s53026; GFX6-NEXT: s_ashr_i32 s4, s4, 303027; GFX6-NEXT: s_or_b32 s6, s4, 13028; GFX6-NEXT: v_mul_f32_e32 v3, v1, v33029; GFX6-NEXT: v_trunc_f32_e32 v3, v33030; GFX6-NEXT: v_mad_f32 v1, -v3, v0, v13031; GFX6-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0|3032; GFX6-NEXT: s_and_b64 s[4:5], s[4:5], exec3033; GFX6-NEXT: v_cvt_i32_f32_e32 v3, v33034; GFX6-NEXT: s_sext_i32_i16 s5, s113035; GFX6-NEXT: v_cvt_f32_i32_e32 v0, s53036; GFX6-NEXT: s_cselect_b32 s4, s6, 03037; GFX6-NEXT: v_add_i32_e32 v3, vcc, s4, v33038; GFX6-NEXT: s_sext_i32_i16 s4, s93039; GFX6-NEXT: v_cvt_f32_i32_e32 v1, s43040; GFX6-NEXT: v_rcp_iflag_f32_e32 v4, v03041; GFX6-NEXT: s_xor_b32 s4, s4, s53042; GFX6-NEXT: s_ashr_i32 s4, s4, 303043; GFX6-NEXT: s_or_b32 s6, s4, 13044; GFX6-NEXT: v_mul_f32_e32 v4, v1, v43045; GFX6-NEXT: v_trunc_f32_e32 v4, v43046; GFX6-NEXT: v_mad_f32 v1, -v4, v0, v13047; GFX6-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0|3048; GFX6-NEXT: s_and_b64 s[4:5], s[4:5], exec3049; GFX6-NEXT: v_cvt_i32_f32_e32 v4, v43050; GFX6-NEXT: s_cselect_b32 s4, s6, 03051; GFX6-NEXT: s_ashr_i32 s5, s11, 163052; GFX6-NEXT: v_cvt_f32_i32_e32 v0, s53053; GFX6-NEXT: v_add_i32_e32 v1, vcc, s4, v43054; GFX6-NEXT: s_ashr_i32 s4, s9, 163055; GFX6-NEXT: v_cvt_f32_i32_e32 v4, s43056; GFX6-NEXT: v_rcp_iflag_f32_e32 v5, v03057; GFX6-NEXT: s_xor_b32 s4, s4, s53058; GFX6-NEXT: s_ashr_i32 s4, s4, 303059; GFX6-NEXT: s_or_b32 s6, s4, 13060; GFX6-NEXT: v_mul_f32_e32 v5, v4, v53061; GFX6-NEXT: v_trunc_f32_e32 v5, v53062; GFX6-NEXT: v_mad_f32 v4, -v5, v0, v43063; GFX6-NEXT: v_cvt_i32_f32_e32 v5, v53064; GFX6-NEXT: v_cmp_ge_f32_e64 s[4:5], |v4|, |v0|3065; GFX6-NEXT: s_and_b64 s[4:5], s[4:5], exec3066; GFX6-NEXT: s_cselect_b32 s4, s6, 03067; GFX6-NEXT: v_add_i32_e32 v0, vcc, s4, v53068; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v03069; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v13070; GFX6-NEXT: v_or_b32_e32 v1, v1, v03071; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v33072; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v23073; GFX6-NEXT: v_or_b32_e32 v0, v2, v03074; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 03075; GFX6-NEXT: s_endpgm3076;3077; GFX9-LABEL: sdiv_v4i16:3078; GFX9: ; %bb.0:3079; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c3080; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x243081; GFX9-NEXT: v_mov_b32_e32 v2, 03082; GFX9-NEXT: s_waitcnt lgkmcnt(0)3083; GFX9-NEXT: s_sext_i32_i16 s4, s23084; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s43085; GFX9-NEXT: s_sext_i32_i16 s5, s03086; GFX9-NEXT: v_cvt_f32_i32_e32 v1, s53087; GFX9-NEXT: s_xor_b32 s4, s5, s43088; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v03089; GFX9-NEXT: s_ashr_i32 s4, s4, 303090; GFX9-NEXT: s_or_b32 s8, s4, 13091; GFX9-NEXT: v_mul_f32_e32 v3, v1, v33092; GFX9-NEXT: v_trunc_f32_e32 v3, v33093; GFX9-NEXT: v_mad_f32 v1, -v3, v0, v13094; GFX9-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0|3095; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec3096; GFX9-NEXT: s_cselect_b32 s4, s8, 03097; GFX9-NEXT: s_ashr_i32 s2, s2, 163098; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s23099; GFX9-NEXT: s_ashr_i32 s0, s0, 163100; GFX9-NEXT: v_cvt_f32_i32_e32 v1, s03101; GFX9-NEXT: v_cvt_i32_f32_e32 v3, v33102; GFX9-NEXT: v_rcp_iflag_f32_e32 v4, v03103; GFX9-NEXT: s_xor_b32 s0, s0, s23104; GFX9-NEXT: s_ashr_i32 s0, s0, 303105; GFX9-NEXT: s_sext_i32_i16 s2, s33106; GFX9-NEXT: v_mul_f32_e32 v4, v1, v43107; GFX9-NEXT: v_trunc_f32_e32 v4, v43108; GFX9-NEXT: v_mad_f32 v1, -v4, v0, v13109; GFX9-NEXT: v_cvt_i32_f32_e32 v4, v43110; GFX9-NEXT: v_add_u32_e32 v3, s4, v33111; GFX9-NEXT: s_or_b32 s0, s0, 13112; GFX9-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0|3113; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s23114; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec3115; GFX9-NEXT: s_cselect_b32 s0, s0, 03116; GFX9-NEXT: v_add_u32_e32 v4, s0, v43117; GFX9-NEXT: s_sext_i32_i16 s0, s13118; GFX9-NEXT: v_cvt_f32_i32_e32 v1, s03119; GFX9-NEXT: v_rcp_iflag_f32_e32 v5, v03120; GFX9-NEXT: s_xor_b32 s0, s0, s23121; GFX9-NEXT: s_ashr_i32 s0, s0, 303122; GFX9-NEXT: s_or_b32 s0, s0, 13123; GFX9-NEXT: v_mul_f32_e32 v5, v1, v53124; GFX9-NEXT: v_trunc_f32_e32 v5, v53125; GFX9-NEXT: v_mad_f32 v1, -v5, v0, v13126; GFX9-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0|3127; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec3128; GFX9-NEXT: v_cvt_i32_f32_e32 v5, v53129; GFX9-NEXT: s_cselect_b32 s0, s0, 03130; GFX9-NEXT: s_ashr_i32 s2, s3, 163131; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s23132; GFX9-NEXT: v_add_u32_e32 v1, s0, v53133; GFX9-NEXT: s_ashr_i32 s0, s1, 163134; GFX9-NEXT: v_cvt_f32_i32_e32 v5, s03135; GFX9-NEXT: v_rcp_iflag_f32_e32 v6, v03136; GFX9-NEXT: s_xor_b32 s0, s0, s23137; GFX9-NEXT: s_ashr_i32 s0, s0, 303138; GFX9-NEXT: s_or_b32 s2, s0, 13139; GFX9-NEXT: v_mul_f32_e32 v6, v5, v63140; GFX9-NEXT: v_trunc_f32_e32 v6, v63141; GFX9-NEXT: v_mad_f32 v5, -v6, v0, v53142; GFX9-NEXT: v_cvt_i32_f32_e32 v6, v63143; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v5|, |v0|3144; GFX9-NEXT: s_and_b64 s[0:1], s[0:1], exec3145; GFX9-NEXT: s_cselect_b32 s0, s2, 03146; GFX9-NEXT: v_add_u32_e32 v0, s0, v63147; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v13148; GFX9-NEXT: v_lshl_or_b32 v1, v0, 16, v13149; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v33150; GFX9-NEXT: v_lshl_or_b32 v0, v4, 16, v03151; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[6:7]3152; GFX9-NEXT: s_endpgm3153 %r = sdiv <4 x i16> %x, %y3154 store <4 x i16> %r, ptr addrspace(1) %out3155 ret void3156}3157 3158define amdgpu_kernel void @srem_v4i16(ptr addrspace(1) %out, <4 x i16> %x, <4 x i16> %y) {3159; CHECK-LABEL: @srem_v4i16(3160; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i16> [[X:%.*]], i64 03161; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i16> [[Y:%.*]], i64 03162; CHECK-NEXT: [[TMP3:%.*]] = sext i16 [[TMP1]] to i323163; CHECK-NEXT: [[TMP4:%.*]] = sext i16 [[TMP2]] to i323164; CHECK-NEXT: [[TMP5:%.*]] = xor i32 [[TMP3]], [[TMP4]]3165; CHECK-NEXT: [[TMP6:%.*]] = ashr i32 [[TMP5]], 303166; CHECK-NEXT: [[TMP7:%.*]] = or i32 [[TMP6]], 13167; CHECK-NEXT: [[TMP8:%.*]] = sitofp i32 [[TMP3]] to float3168; CHECK-NEXT: [[TMP9:%.*]] = sitofp i32 [[TMP4]] to float3169; CHECK-NEXT: [[TMP10:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP9]])3170; CHECK-NEXT: [[TMP11:%.*]] = fmul fast float [[TMP8]], [[TMP10]]3171; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.trunc.f32(float [[TMP11]])3172; CHECK-NEXT: [[TMP13:%.*]] = fneg fast float [[TMP12]]3173; CHECK-NEXT: [[TMP14:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP13]], float [[TMP9]], float [[TMP8]])3174; CHECK-NEXT: [[TMP15:%.*]] = fptosi float [[TMP12]] to i323175; CHECK-NEXT: [[TMP16:%.*]] = call fast float @llvm.fabs.f32(float [[TMP14]])3176; CHECK-NEXT: [[TMP17:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])3177; CHECK-NEXT: [[TMP18:%.*]] = fcmp fast oge float [[TMP16]], [[TMP17]]3178; CHECK-NEXT: [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP7]], i32 03179; CHECK-NEXT: [[TMP20:%.*]] = add i32 [[TMP15]], [[TMP19]]3180; CHECK-NEXT: [[TMP21:%.*]] = mul i32 [[TMP20]], [[TMP4]]3181; CHECK-NEXT: [[TMP22:%.*]] = sub i32 [[TMP3]], [[TMP21]]3182; CHECK-NEXT: [[TMP23:%.*]] = shl i32 [[TMP22]], 163183; CHECK-NEXT: [[TMP24:%.*]] = ashr i32 [[TMP23]], 163184; CHECK-NEXT: [[TMP25:%.*]] = trunc i32 [[TMP24]] to i163185; CHECK-NEXT: [[TMP26:%.*]] = insertelement <4 x i16> poison, i16 [[TMP25]], i64 03186; CHECK-NEXT: [[TMP27:%.*]] = extractelement <4 x i16> [[X]], i64 13187; CHECK-NEXT: [[TMP28:%.*]] = extractelement <4 x i16> [[Y]], i64 13188; CHECK-NEXT: [[TMP29:%.*]] = sext i16 [[TMP27]] to i323189; CHECK-NEXT: [[TMP30:%.*]] = sext i16 [[TMP28]] to i323190; CHECK-NEXT: [[TMP31:%.*]] = xor i32 [[TMP29]], [[TMP30]]3191; CHECK-NEXT: [[TMP32:%.*]] = ashr i32 [[TMP31]], 303192; CHECK-NEXT: [[TMP33:%.*]] = or i32 [[TMP32]], 13193; CHECK-NEXT: [[TMP34:%.*]] = sitofp i32 [[TMP29]] to float3194; CHECK-NEXT: [[TMP35:%.*]] = sitofp i32 [[TMP30]] to float3195; CHECK-NEXT: [[TMP36:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP35]])3196; CHECK-NEXT: [[TMP37:%.*]] = fmul fast float [[TMP34]], [[TMP36]]3197; CHECK-NEXT: [[TMP38:%.*]] = call fast float @llvm.trunc.f32(float [[TMP37]])3198; CHECK-NEXT: [[TMP39:%.*]] = fneg fast float [[TMP38]]3199; CHECK-NEXT: [[TMP40:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP39]], float [[TMP35]], float [[TMP34]])3200; CHECK-NEXT: [[TMP41:%.*]] = fptosi float [[TMP38]] to i323201; CHECK-NEXT: [[TMP42:%.*]] = call fast float @llvm.fabs.f32(float [[TMP40]])3202; CHECK-NEXT: [[TMP43:%.*]] = call fast float @llvm.fabs.f32(float [[TMP35]])3203; CHECK-NEXT: [[TMP44:%.*]] = fcmp fast oge float [[TMP42]], [[TMP43]]3204; CHECK-NEXT: [[TMP45:%.*]] = select i1 [[TMP44]], i32 [[TMP33]], i32 03205; CHECK-NEXT: [[TMP46:%.*]] = add i32 [[TMP41]], [[TMP45]]3206; CHECK-NEXT: [[TMP47:%.*]] = mul i32 [[TMP46]], [[TMP30]]3207; CHECK-NEXT: [[TMP48:%.*]] = sub i32 [[TMP29]], [[TMP47]]3208; CHECK-NEXT: [[TMP49:%.*]] = shl i32 [[TMP48]], 163209; CHECK-NEXT: [[TMP50:%.*]] = ashr i32 [[TMP49]], 163210; CHECK-NEXT: [[TMP51:%.*]] = trunc i32 [[TMP50]] to i163211; CHECK-NEXT: [[TMP52:%.*]] = insertelement <4 x i16> [[TMP26]], i16 [[TMP51]], i64 13212; CHECK-NEXT: [[TMP53:%.*]] = extractelement <4 x i16> [[X]], i64 23213; CHECK-NEXT: [[TMP54:%.*]] = extractelement <4 x i16> [[Y]], i64 23214; CHECK-NEXT: [[TMP55:%.*]] = sext i16 [[TMP53]] to i323215; CHECK-NEXT: [[TMP56:%.*]] = sext i16 [[TMP54]] to i323216; CHECK-NEXT: [[TMP57:%.*]] = xor i32 [[TMP55]], [[TMP56]]3217; CHECK-NEXT: [[TMP58:%.*]] = ashr i32 [[TMP57]], 303218; CHECK-NEXT: [[TMP59:%.*]] = or i32 [[TMP58]], 13219; CHECK-NEXT: [[TMP60:%.*]] = sitofp i32 [[TMP55]] to float3220; CHECK-NEXT: [[TMP61:%.*]] = sitofp i32 [[TMP56]] to float3221; CHECK-NEXT: [[TMP62:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP61]])3222; CHECK-NEXT: [[TMP63:%.*]] = fmul fast float [[TMP60]], [[TMP62]]3223; CHECK-NEXT: [[TMP64:%.*]] = call fast float @llvm.trunc.f32(float [[TMP63]])3224; CHECK-NEXT: [[TMP65:%.*]] = fneg fast float [[TMP64]]3225; CHECK-NEXT: [[TMP66:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP65]], float [[TMP61]], float [[TMP60]])3226; CHECK-NEXT: [[TMP67:%.*]] = fptosi float [[TMP64]] to i323227; CHECK-NEXT: [[TMP68:%.*]] = call fast float @llvm.fabs.f32(float [[TMP66]])3228; CHECK-NEXT: [[TMP69:%.*]] = call fast float @llvm.fabs.f32(float [[TMP61]])3229; CHECK-NEXT: [[TMP70:%.*]] = fcmp fast oge float [[TMP68]], [[TMP69]]3230; CHECK-NEXT: [[TMP71:%.*]] = select i1 [[TMP70]], i32 [[TMP59]], i32 03231; CHECK-NEXT: [[TMP72:%.*]] = add i32 [[TMP67]], [[TMP71]]3232; CHECK-NEXT: [[TMP73:%.*]] = mul i32 [[TMP72]], [[TMP56]]3233; CHECK-NEXT: [[TMP74:%.*]] = sub i32 [[TMP55]], [[TMP73]]3234; CHECK-NEXT: [[TMP75:%.*]] = shl i32 [[TMP74]], 163235; CHECK-NEXT: [[TMP76:%.*]] = ashr i32 [[TMP75]], 163236; CHECK-NEXT: [[TMP77:%.*]] = trunc i32 [[TMP76]] to i163237; CHECK-NEXT: [[TMP78:%.*]] = insertelement <4 x i16> [[TMP52]], i16 [[TMP77]], i64 23238; CHECK-NEXT: [[TMP79:%.*]] = extractelement <4 x i16> [[X]], i64 33239; CHECK-NEXT: [[TMP80:%.*]] = extractelement <4 x i16> [[Y]], i64 33240; CHECK-NEXT: [[TMP81:%.*]] = sext i16 [[TMP79]] to i323241; CHECK-NEXT: [[TMP82:%.*]] = sext i16 [[TMP80]] to i323242; CHECK-NEXT: [[TMP83:%.*]] = xor i32 [[TMP81]], [[TMP82]]3243; CHECK-NEXT: [[TMP84:%.*]] = ashr i32 [[TMP83]], 303244; CHECK-NEXT: [[TMP85:%.*]] = or i32 [[TMP84]], 13245; CHECK-NEXT: [[TMP86:%.*]] = sitofp i32 [[TMP81]] to float3246; CHECK-NEXT: [[TMP87:%.*]] = sitofp i32 [[TMP82]] to float3247; CHECK-NEXT: [[TMP88:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP87]])3248; CHECK-NEXT: [[TMP89:%.*]] = fmul fast float [[TMP86]], [[TMP88]]3249; CHECK-NEXT: [[TMP90:%.*]] = call fast float @llvm.trunc.f32(float [[TMP89]])3250; CHECK-NEXT: [[TMP91:%.*]] = fneg fast float [[TMP90]]3251; CHECK-NEXT: [[TMP92:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP91]], float [[TMP87]], float [[TMP86]])3252; CHECK-NEXT: [[TMP93:%.*]] = fptosi float [[TMP90]] to i323253; CHECK-NEXT: [[TMP94:%.*]] = call fast float @llvm.fabs.f32(float [[TMP92]])3254; CHECK-NEXT: [[TMP95:%.*]] = call fast float @llvm.fabs.f32(float [[TMP87]])3255; CHECK-NEXT: [[TMP96:%.*]] = fcmp fast oge float [[TMP94]], [[TMP95]]3256; CHECK-NEXT: [[TMP97:%.*]] = select i1 [[TMP96]], i32 [[TMP85]], i32 03257; CHECK-NEXT: [[TMP98:%.*]] = add i32 [[TMP93]], [[TMP97]]3258; CHECK-NEXT: [[TMP99:%.*]] = mul i32 [[TMP98]], [[TMP82]]3259; CHECK-NEXT: [[TMP100:%.*]] = sub i32 [[TMP81]], [[TMP99]]3260; CHECK-NEXT: [[TMP101:%.*]] = shl i32 [[TMP100]], 163261; CHECK-NEXT: [[TMP102:%.*]] = ashr i32 [[TMP101]], 163262; CHECK-NEXT: [[TMP103:%.*]] = trunc i32 [[TMP102]] to i163263; CHECK-NEXT: [[TMP104:%.*]] = insertelement <4 x i16> [[TMP78]], i16 [[TMP103]], i64 33264; CHECK-NEXT: store <4 x i16> [[TMP104]], ptr addrspace(1) [[OUT:%.*]], align 83265; CHECK-NEXT: ret void3266;3267; GFX6-LABEL: srem_v4i16:3268; GFX6: ; %bb.0:3269; GFX6-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0xb3270; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x93271; GFX6-NEXT: s_mov_b32 s3, 0xf0003272; GFX6-NEXT: s_mov_b32 s2, -13273; GFX6-NEXT: s_waitcnt lgkmcnt(0)3274; GFX6-NEXT: s_sext_i32_i16 s4, s103275; GFX6-NEXT: v_cvt_f32_i32_e32 v0, s43276; GFX6-NEXT: s_sext_i32_i16 s5, s83277; GFX6-NEXT: v_cvt_f32_i32_e32 v1, s53278; GFX6-NEXT: s_xor_b32 s4, s5, s43279; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v03280; GFX6-NEXT: s_ashr_i32 s4, s4, 303281; GFX6-NEXT: s_or_b32 s6, s4, 13282; GFX6-NEXT: v_mul_f32_e32 v2, v1, v23283; GFX6-NEXT: v_trunc_f32_e32 v2, v23284; GFX6-NEXT: v_mad_f32 v1, -v2, v0, v13285; GFX6-NEXT: v_cvt_i32_f32_e32 v2, v23286; GFX6-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0|3287; GFX6-NEXT: s_and_b64 s[4:5], s[4:5], exec3288; GFX6-NEXT: s_cselect_b32 s4, s6, 03289; GFX6-NEXT: v_add_i32_e32 v0, vcc, s4, v23290; GFX6-NEXT: s_ashr_i32 s4, s10, 163291; GFX6-NEXT: v_cvt_f32_i32_e32 v1, s43292; GFX6-NEXT: s_ashr_i32 s5, s8, 163293; GFX6-NEXT: v_cvt_f32_i32_e32 v2, s53294; GFX6-NEXT: v_mul_lo_u32 v0, v0, s103295; GFX6-NEXT: v_rcp_iflag_f32_e32 v3, v13296; GFX6-NEXT: s_xor_b32 s4, s5, s43297; GFX6-NEXT: s_ashr_i32 s4, s4, 303298; GFX6-NEXT: s_lshr_b32 s6, s8, 163299; GFX6-NEXT: v_mul_f32_e32 v3, v2, v33300; GFX6-NEXT: v_trunc_f32_e32 v3, v33301; GFX6-NEXT: v_mad_f32 v2, -v3, v1, v23302; GFX6-NEXT: v_cvt_i32_f32_e32 v3, v33303; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s8, v03304; GFX6-NEXT: s_lshr_b32 s7, s10, 163305; GFX6-NEXT: s_or_b32 s8, s4, 13306; GFX6-NEXT: v_cmp_ge_f32_e64 s[4:5], |v2|, |v1|3307; GFX6-NEXT: s_and_b64 s[4:5], s[4:5], exec3308; GFX6-NEXT: s_cselect_b32 s4, s8, 03309; GFX6-NEXT: v_add_i32_e32 v1, vcc, s4, v33310; GFX6-NEXT: s_sext_i32_i16 s4, s113311; GFX6-NEXT: v_mul_lo_u32 v1, v1, s73312; GFX6-NEXT: v_cvt_f32_i32_e32 v2, s43313; GFX6-NEXT: s_sext_i32_i16 s5, s93314; GFX6-NEXT: s_xor_b32 s4, s5, s43315; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s6, v13316; GFX6-NEXT: v_cvt_f32_i32_e32 v1, s53317; GFX6-NEXT: v_rcp_iflag_f32_e32 v4, v23318; GFX6-NEXT: s_ashr_i32 s4, s4, 303319; GFX6-NEXT: s_or_b32 s6, s4, 13320; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v03321; GFX6-NEXT: v_mul_f32_e32 v4, v1, v43322; GFX6-NEXT: v_trunc_f32_e32 v4, v43323; GFX6-NEXT: v_mad_f32 v1, -v4, v2, v13324; GFX6-NEXT: v_cvt_i32_f32_e32 v4, v43325; GFX6-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v2|3326; GFX6-NEXT: s_and_b64 s[4:5], s[4:5], exec3327; GFX6-NEXT: s_cselect_b32 s4, s6, 03328; GFX6-NEXT: v_add_i32_e32 v1, vcc, s4, v43329; GFX6-NEXT: s_ashr_i32 s4, s11, 163330; GFX6-NEXT: v_cvt_f32_i32_e32 v2, s43331; GFX6-NEXT: s_ashr_i32 s5, s9, 163332; GFX6-NEXT: v_cvt_f32_i32_e32 v4, s53333; GFX6-NEXT: s_xor_b32 s4, s5, s43334; GFX6-NEXT: v_rcp_iflag_f32_e32 v5, v23335; GFX6-NEXT: s_ashr_i32 s4, s4, 303336; GFX6-NEXT: s_lshr_b32 s6, s9, 163337; GFX6-NEXT: s_lshr_b32 s7, s11, 163338; GFX6-NEXT: v_mul_f32_e32 v5, v4, v53339; GFX6-NEXT: v_trunc_f32_e32 v5, v53340; GFX6-NEXT: v_mad_f32 v4, -v5, v2, v43341; GFX6-NEXT: v_cvt_i32_f32_e32 v5, v53342; GFX6-NEXT: s_or_b32 s8, s4, 13343; GFX6-NEXT: v_cmp_ge_f32_e64 s[4:5], |v4|, |v2|3344; GFX6-NEXT: s_and_b64 s[4:5], s[4:5], exec3345; GFX6-NEXT: s_cselect_b32 s4, s8, 03346; GFX6-NEXT: v_add_i32_e32 v2, vcc, s4, v53347; GFX6-NEXT: v_mul_lo_u32 v1, v1, s113348; GFX6-NEXT: v_mul_lo_u32 v2, v2, s73349; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s9, v13350; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s6, v23351; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v23352; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v13353; GFX6-NEXT: v_or_b32_e32 v1, v1, v23354; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v33355; GFX6-NEXT: v_or_b32_e32 v0, v0, v23356; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 03357; GFX6-NEXT: s_endpgm3358;3359; GFX9-LABEL: srem_v4i16:3360; GFX9: ; %bb.0:3361; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c3362; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x243363; GFX9-NEXT: v_mov_b32_e32 v2, 03364; GFX9-NEXT: s_waitcnt lgkmcnt(0)3365; GFX9-NEXT: s_sext_i32_i16 s8, s23366; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s83367; GFX9-NEXT: s_sext_i32_i16 s9, s03368; GFX9-NEXT: v_cvt_f32_i32_e32 v1, s93369; GFX9-NEXT: s_xor_b32 s4, s9, s83370; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v03371; GFX9-NEXT: s_ashr_i32 s4, s4, 303372; GFX9-NEXT: s_or_b32 s10, s4, 13373; GFX9-NEXT: v_mul_f32_e32 v3, v1, v33374; GFX9-NEXT: v_trunc_f32_e32 v3, v33375; GFX9-NEXT: v_mad_f32 v1, -v3, v0, v13376; GFX9-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0|3377; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec3378; GFX9-NEXT: s_cselect_b32 s4, s10, 03379; GFX9-NEXT: s_ashr_i32 s10, s0, 163380; GFX9-NEXT: s_ashr_i32 s0, s2, 163381; GFX9-NEXT: v_cvt_i32_f32_e32 v3, v33382; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s03383; GFX9-NEXT: s_xor_b32 s2, s10, s03384; GFX9-NEXT: s_ashr_i32 s2, s2, 303385; GFX9-NEXT: v_add_u32_e32 v1, s4, v33386; GFX9-NEXT: v_cvt_f32_i32_e32 v3, s103387; GFX9-NEXT: v_rcp_iflag_f32_e32 v4, v03388; GFX9-NEXT: s_or_b32 s2, s2, 13389; GFX9-NEXT: v_mul_lo_u32 v1, v1, s83390; GFX9-NEXT: s_sext_i32_i16 s8, s13391; GFX9-NEXT: v_mul_f32_e32 v4, v3, v43392; GFX9-NEXT: v_trunc_f32_e32 v4, v43393; GFX9-NEXT: v_mad_f32 v3, -v4, v0, v33394; GFX9-NEXT: v_cvt_i32_f32_e32 v4, v43395; GFX9-NEXT: v_cmp_ge_f32_e64 s[4:5], |v3|, |v0|3396; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec3397; GFX9-NEXT: s_cselect_b32 s2, s2, 03398; GFX9-NEXT: v_add_u32_e32 v0, s2, v43399; GFX9-NEXT: s_sext_i32_i16 s2, s33400; GFX9-NEXT: v_cvt_f32_i32_e32 v3, s23401; GFX9-NEXT: v_cvt_f32_i32_e32 v4, s83402; GFX9-NEXT: v_mul_lo_u32 v0, v0, s03403; GFX9-NEXT: s_xor_b32 s0, s8, s23404; GFX9-NEXT: v_rcp_iflag_f32_e32 v5, v33405; GFX9-NEXT: s_ashr_i32 s0, s0, 303406; GFX9-NEXT: s_or_b32 s0, s0, 13407; GFX9-NEXT: v_sub_u32_e32 v0, s10, v03408; GFX9-NEXT: v_mul_f32_e32 v5, v4, v53409; GFX9-NEXT: v_trunc_f32_e32 v5, v53410; GFX9-NEXT: v_mad_f32 v4, -v5, v3, v43411; GFX9-NEXT: v_cmp_ge_f32_e64 s[4:5], |v4|, |v3|3412; GFX9-NEXT: v_cvt_i32_f32_e32 v5, v53413; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec3414; GFX9-NEXT: s_cselect_b32 s0, s0, 03415; GFX9-NEXT: s_ashr_i32 s3, s3, 163416; GFX9-NEXT: v_cvt_f32_i32_e32 v4, s33417; GFX9-NEXT: v_add_u32_e32 v3, s0, v53418; GFX9-NEXT: v_mul_lo_u32 v3, v3, s23419; GFX9-NEXT: s_ashr_i32 s2, s1, 163420; GFX9-NEXT: v_cvt_f32_i32_e32 v5, s23421; GFX9-NEXT: v_rcp_iflag_f32_e32 v6, v43422; GFX9-NEXT: s_xor_b32 s0, s2, s33423; GFX9-NEXT: s_ashr_i32 s0, s0, 303424; GFX9-NEXT: s_or_b32 s4, s0, 13425; GFX9-NEXT: v_mul_f32_e32 v6, v5, v63426; GFX9-NEXT: v_trunc_f32_e32 v6, v63427; GFX9-NEXT: v_mad_f32 v5, -v6, v4, v53428; GFX9-NEXT: v_cvt_i32_f32_e32 v6, v63429; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v5|, |v4|3430; GFX9-NEXT: s_and_b64 s[0:1], s[0:1], exec3431; GFX9-NEXT: s_cselect_b32 s0, s4, 03432; GFX9-NEXT: v_add_u32_e32 v4, s0, v63433; GFX9-NEXT: v_mul_lo_u32 v4, v4, s33434; GFX9-NEXT: v_sub_u32_e32 v5, s9, v13435; GFX9-NEXT: v_sub_u32_e32 v1, s8, v33436; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v13437; GFX9-NEXT: v_sub_u32_e32 v3, s2, v43438; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v13439; GFX9-NEXT: v_and_b32_e32 v3, 0xffff, v53440; GFX9-NEXT: v_lshl_or_b32 v0, v0, 16, v33441; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[6:7]3442; GFX9-NEXT: s_endpgm3443 %r = srem <4 x i16> %x, %y3444 store <4 x i16> %r, ptr addrspace(1) %out3445 ret void3446}3447 3448define amdgpu_kernel void @udiv_i3(ptr addrspace(1) %out, i3 %x, i3 %y) {3449; CHECK-LABEL: @udiv_i3(3450; CHECK-NEXT: [[TMP1:%.*]] = zext i3 [[X:%.*]] to i323451; CHECK-NEXT: [[TMP2:%.*]] = zext i3 [[Y:%.*]] to i323452; CHECK-NEXT: [[TMP3:%.*]] = uitofp i32 [[TMP1]] to float3453; CHECK-NEXT: [[TMP4:%.*]] = uitofp i32 [[TMP2]] to float3454; CHECK-NEXT: [[TMP5:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP4]])3455; CHECK-NEXT: [[TMP6:%.*]] = fmul fast float [[TMP3]], [[TMP5]]3456; CHECK-NEXT: [[TMP7:%.*]] = call fast float @llvm.trunc.f32(float [[TMP6]])3457; CHECK-NEXT: [[TMP8:%.*]] = fneg fast float [[TMP7]]3458; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP8]], float [[TMP4]], float [[TMP3]])3459; CHECK-NEXT: [[TMP10:%.*]] = fptoui float [[TMP7]] to i323460; CHECK-NEXT: [[TMP11:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])3461; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.fabs.f32(float [[TMP4]])3462; CHECK-NEXT: [[TMP13:%.*]] = fcmp fast oge float [[TMP11]], [[TMP12]]3463; CHECK-NEXT: [[TMP14:%.*]] = select i1 [[TMP13]], i32 1, i32 03464; CHECK-NEXT: [[TMP15:%.*]] = add i32 [[TMP10]], [[TMP14]]3465; CHECK-NEXT: [[TMP16:%.*]] = and i32 [[TMP15]], 73466; CHECK-NEXT: [[TMP17:%.*]] = trunc i32 [[TMP16]] to i33467; CHECK-NEXT: store i3 [[TMP17]], ptr addrspace(1) [[OUT:%.*]], align 13468; CHECK-NEXT: ret void3469;3470; GFX6-LABEL: udiv_i3:3471; GFX6: ; %bb.0:3472; GFX6-NEXT: s_load_dword s6, s[4:5], 0xb3473; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x93474; GFX6-NEXT: s_mov_b32 s3, 0xf0003475; GFX6-NEXT: s_waitcnt lgkmcnt(0)3476; GFX6-NEXT: s_bfe_u32 s2, s6, 0x300083477; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v0, s23478; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v03479; GFX6-NEXT: s_and_b32 s4, s6, 73480; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v2, s43481; GFX6-NEXT: s_mov_b32 s2, -13482; GFX6-NEXT: v_mul_f32_e32 v1, v2, v13483; GFX6-NEXT: v_trunc_f32_e32 v1, v13484; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v13485; GFX6-NEXT: v_mad_f32 v1, -v1, v0, v23486; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v03487; GFX6-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc3488; GFX6-NEXT: v_and_b32_e32 v0, 7, v03489; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 03490; GFX6-NEXT: s_endpgm3491;3492; GFX9-LABEL: udiv_i3:3493; GFX9: ; %bb.0:3494; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c3495; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x243496; GFX9-NEXT: v_mov_b32_e32 v2, 03497; GFX9-NEXT: s_waitcnt lgkmcnt(0)3498; GFX9-NEXT: s_bfe_u32 s3, s2, 0x300083499; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v0, s33500; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v03501; GFX9-NEXT: s_and_b32 s2, s2, 73502; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v3, s23503; GFX9-NEXT: v_mul_f32_e32 v1, v3, v13504; GFX9-NEXT: v_trunc_f32_e32 v1, v13505; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v13506; GFX9-NEXT: v_mad_f32 v1, -v1, v0, v33507; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v03508; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, 0, v4, vcc3509; GFX9-NEXT: v_and_b32_e32 v0, 7, v03510; GFX9-NEXT: global_store_byte v2, v0, s[0:1]3511; GFX9-NEXT: s_endpgm3512 %r = udiv i3 %x, %y3513 store i3 %r, ptr addrspace(1) %out3514 ret void3515}3516 3517define amdgpu_kernel void @urem_i3(ptr addrspace(1) %out, i3 %x, i3 %y) {3518; CHECK-LABEL: @urem_i3(3519; CHECK-NEXT: [[TMP1:%.*]] = zext i3 [[X:%.*]] to i323520; CHECK-NEXT: [[TMP2:%.*]] = zext i3 [[Y:%.*]] to i323521; CHECK-NEXT: [[TMP3:%.*]] = uitofp i32 [[TMP1]] to float3522; CHECK-NEXT: [[TMP4:%.*]] = uitofp i32 [[TMP2]] to float3523; CHECK-NEXT: [[TMP5:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP4]])3524; CHECK-NEXT: [[TMP6:%.*]] = fmul fast float [[TMP3]], [[TMP5]]3525; CHECK-NEXT: [[TMP7:%.*]] = call fast float @llvm.trunc.f32(float [[TMP6]])3526; CHECK-NEXT: [[TMP8:%.*]] = fneg fast float [[TMP7]]3527; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP8]], float [[TMP4]], float [[TMP3]])3528; CHECK-NEXT: [[TMP10:%.*]] = fptoui float [[TMP7]] to i323529; CHECK-NEXT: [[TMP11:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])3530; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.fabs.f32(float [[TMP4]])3531; CHECK-NEXT: [[TMP13:%.*]] = fcmp fast oge float [[TMP11]], [[TMP12]]3532; CHECK-NEXT: [[TMP14:%.*]] = select i1 [[TMP13]], i32 1, i32 03533; CHECK-NEXT: [[TMP15:%.*]] = add i32 [[TMP10]], [[TMP14]]3534; CHECK-NEXT: [[TMP16:%.*]] = mul i32 [[TMP15]], [[TMP2]]3535; CHECK-NEXT: [[TMP17:%.*]] = sub i32 [[TMP1]], [[TMP16]]3536; CHECK-NEXT: [[TMP18:%.*]] = and i32 [[TMP17]], 73537; CHECK-NEXT: [[TMP19:%.*]] = trunc i32 [[TMP18]] to i33538; CHECK-NEXT: store i3 [[TMP19]], ptr addrspace(1) [[OUT:%.*]], align 13539; CHECK-NEXT: ret void3540;3541; GFX6-LABEL: urem_i3:3542; GFX6: ; %bb.0:3543; GFX6-NEXT: s_load_dword s6, s[4:5], 0xb3544; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x93545; GFX6-NEXT: s_waitcnt lgkmcnt(0)3546; GFX6-NEXT: s_bfe_u32 s2, s6, 0x300083547; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v0, s23548; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v03549; GFX6-NEXT: s_and_b32 s3, s6, 73550; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v2, s33551; GFX6-NEXT: s_lshr_b32 s2, s6, 83552; GFX6-NEXT: v_mul_f32_e32 v1, v2, v13553; GFX6-NEXT: v_trunc_f32_e32 v1, v13554; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v13555; GFX6-NEXT: v_mad_f32 v1, -v1, v0, v23556; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v03557; GFX6-NEXT: s_mov_b32 s3, 0xf0003558; GFX6-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc3559; GFX6-NEXT: v_mul_lo_u32 v0, v0, s23560; GFX6-NEXT: s_mov_b32 s2, -13561; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s6, v03562; GFX6-NEXT: v_and_b32_e32 v0, 7, v03563; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 03564; GFX6-NEXT: s_endpgm3565;3566; GFX9-LABEL: urem_i3:3567; GFX9: ; %bb.0:3568; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c3569; GFX9-NEXT: s_waitcnt lgkmcnt(0)3570; GFX9-NEXT: s_bfe_u32 s0, s2, 0x300083571; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v0, s03572; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v03573; GFX9-NEXT: s_and_b32 s1, s2, 73574; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v2, s13575; GFX9-NEXT: s_lshr_b32 s0, s2, 83576; GFX9-NEXT: v_mul_f32_e32 v1, v2, v13577; GFX9-NEXT: v_trunc_f32_e32 v1, v13578; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v13579; GFX9-NEXT: v_mad_f32 v1, -v1, v0, v23580; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v03581; GFX9-NEXT: v_mov_b32_e32 v1, 03582; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, 0, v3, vcc3583; GFX9-NEXT: v_mul_lo_u32 v0, v0, s03584; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x243585; GFX9-NEXT: v_sub_u32_e32 v0, s2, v03586; GFX9-NEXT: v_and_b32_e32 v0, 7, v03587; GFX9-NEXT: s_waitcnt lgkmcnt(0)3588; GFX9-NEXT: global_store_byte v1, v0, s[0:1]3589; GFX9-NEXT: s_endpgm3590 %r = urem i3 %x, %y3591 store i3 %r, ptr addrspace(1) %out3592 ret void3593}3594 3595define amdgpu_kernel void @sdiv_i3(ptr addrspace(1) %out, i3 %x, i3 %y) {3596; CHECK-LABEL: @sdiv_i3(3597; CHECK-NEXT: [[TMP1:%.*]] = sext i3 [[X:%.*]] to i323598; CHECK-NEXT: [[TMP2:%.*]] = sext i3 [[Y:%.*]] to i323599; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], [[TMP2]]3600; CHECK-NEXT: [[TMP4:%.*]] = ashr i32 [[TMP3]], 303601; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP4]], 13602; CHECK-NEXT: [[TMP6:%.*]] = sitofp i32 [[TMP1]] to float3603; CHECK-NEXT: [[TMP7:%.*]] = sitofp i32 [[TMP2]] to float3604; CHECK-NEXT: [[TMP8:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP7]])3605; CHECK-NEXT: [[TMP9:%.*]] = fmul fast float [[TMP6]], [[TMP8]]3606; CHECK-NEXT: [[TMP10:%.*]] = call fast float @llvm.trunc.f32(float [[TMP9]])3607; CHECK-NEXT: [[TMP11:%.*]] = fneg fast float [[TMP10]]3608; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP11]], float [[TMP7]], float [[TMP6]])3609; CHECK-NEXT: [[TMP13:%.*]] = fptosi float [[TMP10]] to i323610; CHECK-NEXT: [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP12]])3611; CHECK-NEXT: [[TMP15:%.*]] = call fast float @llvm.fabs.f32(float [[TMP7]])3612; CHECK-NEXT: [[TMP16:%.*]] = fcmp fast oge float [[TMP14]], [[TMP15]]3613; CHECK-NEXT: [[TMP17:%.*]] = select i1 [[TMP16]], i32 [[TMP5]], i32 03614; CHECK-NEXT: [[TMP18:%.*]] = add i32 [[TMP13]], [[TMP17]]3615; CHECK-NEXT: [[TMP19:%.*]] = shl i32 [[TMP18]], 293616; CHECK-NEXT: [[TMP20:%.*]] = ashr i32 [[TMP19]], 293617; CHECK-NEXT: [[TMP21:%.*]] = trunc i32 [[TMP20]] to i33618; CHECK-NEXT: store i3 [[TMP21]], ptr addrspace(1) [[OUT:%.*]], align 13619; CHECK-NEXT: ret void3620;3621; GFX6-LABEL: sdiv_i3:3622; GFX6: ; %bb.0:3623; GFX6-NEXT: s_load_dword s6, s[4:5], 0xb3624; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x93625; GFX6-NEXT: s_mov_b32 s3, 0xf0003626; GFX6-NEXT: s_mov_b32 s2, -13627; GFX6-NEXT: s_waitcnt lgkmcnt(0)3628; GFX6-NEXT: s_bfe_i32 s4, s6, 0x300083629; GFX6-NEXT: v_cvt_f32_i32_e32 v0, s43630; GFX6-NEXT: s_bfe_i32 s5, s6, 0x300003631; GFX6-NEXT: v_cvt_f32_i32_e32 v1, s53632; GFX6-NEXT: s_xor_b32 s4, s5, s43633; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v03634; GFX6-NEXT: s_ashr_i32 s4, s4, 303635; GFX6-NEXT: s_or_b32 s6, s4, 13636; GFX6-NEXT: v_mul_f32_e32 v2, v1, v23637; GFX6-NEXT: v_trunc_f32_e32 v2, v23638; GFX6-NEXT: v_mad_f32 v1, -v2, v0, v13639; GFX6-NEXT: v_cvt_i32_f32_e32 v2, v23640; GFX6-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0|3641; GFX6-NEXT: s_and_b64 s[4:5], s[4:5], exec3642; GFX6-NEXT: s_cselect_b32 s4, s6, 03643; GFX6-NEXT: v_add_i32_e32 v0, vcc, s4, v23644; GFX6-NEXT: v_and_b32_e32 v0, 7, v03645; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 03646; GFX6-NEXT: s_endpgm3647;3648; GFX9-LABEL: sdiv_i3:3649; GFX9: ; %bb.0:3650; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c3651; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x243652; GFX9-NEXT: v_mov_b32_e32 v1, 03653; GFX9-NEXT: s_waitcnt lgkmcnt(0)3654; GFX9-NEXT: s_bfe_i32 s3, s2, 0x300083655; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s33656; GFX9-NEXT: s_bfe_i32 s2, s2, 0x300003657; GFX9-NEXT: v_cvt_f32_i32_e32 v2, s23658; GFX9-NEXT: s_xor_b32 s2, s2, s33659; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v03660; GFX9-NEXT: s_ashr_i32 s2, s2, 303661; GFX9-NEXT: s_or_b32 s4, s2, 13662; GFX9-NEXT: v_mul_f32_e32 v3, v2, v33663; GFX9-NEXT: v_trunc_f32_e32 v3, v33664; GFX9-NEXT: v_mad_f32 v2, -v3, v0, v23665; GFX9-NEXT: v_cvt_i32_f32_e32 v3, v33666; GFX9-NEXT: v_cmp_ge_f32_e64 s[2:3], |v2|, |v0|3667; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec3668; GFX9-NEXT: s_cselect_b32 s2, s4, 03669; GFX9-NEXT: v_add_u32_e32 v0, s2, v33670; GFX9-NEXT: v_and_b32_e32 v0, 7, v03671; GFX9-NEXT: global_store_byte v1, v0, s[0:1]3672; GFX9-NEXT: s_endpgm3673 %r = sdiv i3 %x, %y3674 store i3 %r, ptr addrspace(1) %out3675 ret void3676}3677 3678define amdgpu_kernel void @srem_i3(ptr addrspace(1) %out, i3 %x, i3 %y) {3679; CHECK-LABEL: @srem_i3(3680; CHECK-NEXT: [[TMP1:%.*]] = sext i3 [[X:%.*]] to i323681; CHECK-NEXT: [[TMP2:%.*]] = sext i3 [[Y:%.*]] to i323682; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], [[TMP2]]3683; CHECK-NEXT: [[TMP4:%.*]] = ashr i32 [[TMP3]], 303684; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP4]], 13685; CHECK-NEXT: [[TMP6:%.*]] = sitofp i32 [[TMP1]] to float3686; CHECK-NEXT: [[TMP7:%.*]] = sitofp i32 [[TMP2]] to float3687; CHECK-NEXT: [[TMP8:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP7]])3688; CHECK-NEXT: [[TMP9:%.*]] = fmul fast float [[TMP6]], [[TMP8]]3689; CHECK-NEXT: [[TMP10:%.*]] = call fast float @llvm.trunc.f32(float [[TMP9]])3690; CHECK-NEXT: [[TMP11:%.*]] = fneg fast float [[TMP10]]3691; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP11]], float [[TMP7]], float [[TMP6]])3692; CHECK-NEXT: [[TMP13:%.*]] = fptosi float [[TMP10]] to i323693; CHECK-NEXT: [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP12]])3694; CHECK-NEXT: [[TMP15:%.*]] = call fast float @llvm.fabs.f32(float [[TMP7]])3695; CHECK-NEXT: [[TMP16:%.*]] = fcmp fast oge float [[TMP14]], [[TMP15]]3696; CHECK-NEXT: [[TMP17:%.*]] = select i1 [[TMP16]], i32 [[TMP5]], i32 03697; CHECK-NEXT: [[TMP18:%.*]] = add i32 [[TMP13]], [[TMP17]]3698; CHECK-NEXT: [[TMP19:%.*]] = mul i32 [[TMP18]], [[TMP2]]3699; CHECK-NEXT: [[TMP20:%.*]] = sub i32 [[TMP1]], [[TMP19]]3700; CHECK-NEXT: [[TMP21:%.*]] = shl i32 [[TMP20]], 293701; CHECK-NEXT: [[TMP22:%.*]] = ashr i32 [[TMP21]], 293702; CHECK-NEXT: [[TMP23:%.*]] = trunc i32 [[TMP22]] to i33703; CHECK-NEXT: store i3 [[TMP23]], ptr addrspace(1) [[OUT:%.*]], align 13704; CHECK-NEXT: ret void3705;3706; GFX6-LABEL: srem_i3:3707; GFX6: ; %bb.0:3708; GFX6-NEXT: s_load_dword s6, s[4:5], 0xb3709; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x93710; GFX6-NEXT: s_waitcnt lgkmcnt(0)3711; GFX6-NEXT: s_bfe_i32 s2, s6, 0x300083712; GFX6-NEXT: v_cvt_f32_i32_e32 v0, s23713; GFX6-NEXT: s_bfe_i32 s3, s6, 0x300003714; GFX6-NEXT: v_cvt_f32_i32_e32 v1, s33715; GFX6-NEXT: s_xor_b32 s2, s3, s23716; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v03717; GFX6-NEXT: s_ashr_i32 s2, s2, 303718; GFX6-NEXT: s_lshr_b32 s4, s6, 83719; GFX6-NEXT: s_or_b32 s5, s2, 13720; GFX6-NEXT: v_mul_f32_e32 v2, v1, v23721; GFX6-NEXT: v_trunc_f32_e32 v2, v23722; GFX6-NEXT: v_mad_f32 v1, -v2, v0, v13723; GFX6-NEXT: v_cvt_i32_f32_e32 v2, v23724; GFX6-NEXT: v_cmp_ge_f32_e64 s[2:3], |v1|, |v0|3725; GFX6-NEXT: s_and_b64 s[2:3], s[2:3], exec3726; GFX6-NEXT: s_cselect_b32 s2, s5, 03727; GFX6-NEXT: v_add_i32_e32 v0, vcc, s2, v23728; GFX6-NEXT: v_mul_lo_u32 v0, v0, s43729; GFX6-NEXT: s_mov_b32 s3, 0xf0003730; GFX6-NEXT: s_mov_b32 s2, -13731; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s6, v03732; GFX6-NEXT: v_and_b32_e32 v0, 7, v03733; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 03734; GFX6-NEXT: s_endpgm3735;3736; GFX9-LABEL: srem_i3:3737; GFX9: ; %bb.0:3738; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c3739; GFX9-NEXT: s_waitcnt lgkmcnt(0)3740; GFX9-NEXT: s_bfe_i32 s0, s2, 0x300083741; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s03742; GFX9-NEXT: s_bfe_i32 s1, s2, 0x300003743; GFX9-NEXT: v_cvt_f32_i32_e32 v1, s13744; GFX9-NEXT: s_xor_b32 s0, s1, s03745; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v03746; GFX9-NEXT: s_ashr_i32 s0, s0, 303747; GFX9-NEXT: s_lshr_b32 s3, s2, 83748; GFX9-NEXT: s_or_b32 s6, s0, 13749; GFX9-NEXT: v_mul_f32_e32 v2, v1, v23750; GFX9-NEXT: v_trunc_f32_e32 v2, v23751; GFX9-NEXT: v_mad_f32 v1, -v2, v0, v13752; GFX9-NEXT: v_cvt_i32_f32_e32 v2, v23753; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v1|, |v0|3754; GFX9-NEXT: s_and_b64 s[0:1], s[0:1], exec3755; GFX9-NEXT: s_cselect_b32 s0, s6, 03756; GFX9-NEXT: v_add_u32_e32 v0, s0, v23757; GFX9-NEXT: v_mul_lo_u32 v0, v0, s33758; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x243759; GFX9-NEXT: v_mov_b32_e32 v1, 03760; GFX9-NEXT: v_sub_u32_e32 v0, s2, v03761; GFX9-NEXT: v_and_b32_e32 v0, 7, v03762; GFX9-NEXT: s_waitcnt lgkmcnt(0)3763; GFX9-NEXT: global_store_byte v1, v0, s[0:1]3764; GFX9-NEXT: s_endpgm3765 %r = srem i3 %x, %y3766 store i3 %r, ptr addrspace(1) %out3767 ret void3768}3769 3770define amdgpu_kernel void @udiv_v3i16(ptr addrspace(1) %out, <3 x i16> %x, <3 x i16> %y) {3771; CHECK-LABEL: @udiv_v3i16(3772; CHECK-NEXT: [[TMP1:%.*]] = extractelement <3 x i16> [[X:%.*]], i64 03773; CHECK-NEXT: [[TMP2:%.*]] = extractelement <3 x i16> [[Y:%.*]], i64 03774; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[TMP1]] to i323775; CHECK-NEXT: [[TMP4:%.*]] = zext i16 [[TMP2]] to i323776; CHECK-NEXT: [[TMP5:%.*]] = uitofp i32 [[TMP3]] to float3777; CHECK-NEXT: [[TMP6:%.*]] = uitofp i32 [[TMP4]] to float3778; CHECK-NEXT: [[TMP7:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP6]])3779; CHECK-NEXT: [[TMP8:%.*]] = fmul fast float [[TMP5]], [[TMP7]]3780; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.trunc.f32(float [[TMP8]])3781; CHECK-NEXT: [[TMP10:%.*]] = fneg fast float [[TMP9]]3782; CHECK-NEXT: [[TMP11:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP10]], float [[TMP6]], float [[TMP5]])3783; CHECK-NEXT: [[TMP12:%.*]] = fptoui float [[TMP9]] to i323784; CHECK-NEXT: [[TMP13:%.*]] = call fast float @llvm.fabs.f32(float [[TMP11]])3785; CHECK-NEXT: [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP6]])3786; CHECK-NEXT: [[TMP15:%.*]] = fcmp fast oge float [[TMP13]], [[TMP14]]3787; CHECK-NEXT: [[TMP16:%.*]] = select i1 [[TMP15]], i32 1, i32 03788; CHECK-NEXT: [[TMP17:%.*]] = add i32 [[TMP12]], [[TMP16]]3789; CHECK-NEXT: [[TMP18:%.*]] = and i32 [[TMP17]], 655353790; CHECK-NEXT: [[TMP19:%.*]] = trunc i32 [[TMP18]] to i163791; CHECK-NEXT: [[TMP20:%.*]] = insertelement <3 x i16> poison, i16 [[TMP19]], i64 03792; CHECK-NEXT: [[TMP21:%.*]] = extractelement <3 x i16> [[X]], i64 13793; CHECK-NEXT: [[TMP22:%.*]] = extractelement <3 x i16> [[Y]], i64 13794; CHECK-NEXT: [[TMP23:%.*]] = zext i16 [[TMP21]] to i323795; CHECK-NEXT: [[TMP24:%.*]] = zext i16 [[TMP22]] to i323796; CHECK-NEXT: [[TMP25:%.*]] = uitofp i32 [[TMP23]] to float3797; CHECK-NEXT: [[TMP26:%.*]] = uitofp i32 [[TMP24]] to float3798; CHECK-NEXT: [[TMP27:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP26]])3799; CHECK-NEXT: [[TMP28:%.*]] = fmul fast float [[TMP25]], [[TMP27]]3800; CHECK-NEXT: [[TMP29:%.*]] = call fast float @llvm.trunc.f32(float [[TMP28]])3801; CHECK-NEXT: [[TMP30:%.*]] = fneg fast float [[TMP29]]3802; CHECK-NEXT: [[TMP31:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP30]], float [[TMP26]], float [[TMP25]])3803; CHECK-NEXT: [[TMP32:%.*]] = fptoui float [[TMP29]] to i323804; CHECK-NEXT: [[TMP33:%.*]] = call fast float @llvm.fabs.f32(float [[TMP31]])3805; CHECK-NEXT: [[TMP34:%.*]] = call fast float @llvm.fabs.f32(float [[TMP26]])3806; CHECK-NEXT: [[TMP35:%.*]] = fcmp fast oge float [[TMP33]], [[TMP34]]3807; CHECK-NEXT: [[TMP36:%.*]] = select i1 [[TMP35]], i32 1, i32 03808; CHECK-NEXT: [[TMP37:%.*]] = add i32 [[TMP32]], [[TMP36]]3809; CHECK-NEXT: [[TMP38:%.*]] = and i32 [[TMP37]], 655353810; CHECK-NEXT: [[TMP39:%.*]] = trunc i32 [[TMP38]] to i163811; CHECK-NEXT: [[TMP40:%.*]] = insertelement <3 x i16> [[TMP20]], i16 [[TMP39]], i64 13812; CHECK-NEXT: [[TMP41:%.*]] = extractelement <3 x i16> [[X]], i64 23813; CHECK-NEXT: [[TMP42:%.*]] = extractelement <3 x i16> [[Y]], i64 23814; CHECK-NEXT: [[TMP43:%.*]] = zext i16 [[TMP41]] to i323815; CHECK-NEXT: [[TMP44:%.*]] = zext i16 [[TMP42]] to i323816; CHECK-NEXT: [[TMP45:%.*]] = uitofp i32 [[TMP43]] to float3817; CHECK-NEXT: [[TMP46:%.*]] = uitofp i32 [[TMP44]] to float3818; CHECK-NEXT: [[TMP47:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP46]])3819; CHECK-NEXT: [[TMP48:%.*]] = fmul fast float [[TMP45]], [[TMP47]]3820; CHECK-NEXT: [[TMP49:%.*]] = call fast float @llvm.trunc.f32(float [[TMP48]])3821; CHECK-NEXT: [[TMP50:%.*]] = fneg fast float [[TMP49]]3822; CHECK-NEXT: [[TMP51:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP50]], float [[TMP46]], float [[TMP45]])3823; CHECK-NEXT: [[TMP52:%.*]] = fptoui float [[TMP49]] to i323824; CHECK-NEXT: [[TMP53:%.*]] = call fast float @llvm.fabs.f32(float [[TMP51]])3825; CHECK-NEXT: [[TMP54:%.*]] = call fast float @llvm.fabs.f32(float [[TMP46]])3826; CHECK-NEXT: [[TMP55:%.*]] = fcmp fast oge float [[TMP53]], [[TMP54]]3827; CHECK-NEXT: [[TMP56:%.*]] = select i1 [[TMP55]], i32 1, i32 03828; CHECK-NEXT: [[TMP57:%.*]] = add i32 [[TMP52]], [[TMP56]]3829; CHECK-NEXT: [[TMP58:%.*]] = and i32 [[TMP57]], 655353830; CHECK-NEXT: [[TMP59:%.*]] = trunc i32 [[TMP58]] to i163831; CHECK-NEXT: [[TMP60:%.*]] = insertelement <3 x i16> [[TMP40]], i16 [[TMP59]], i64 23832; CHECK-NEXT: store <3 x i16> [[TMP60]], ptr addrspace(1) [[OUT:%.*]], align 83833; CHECK-NEXT: ret void3834;3835; GFX6-LABEL: udiv_v3i16:3836; GFX6: ; %bb.0:3837; GFX6-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0xb3838; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x93839; GFX6-NEXT: s_mov_b32 s3, 0xf0003840; GFX6-NEXT: s_mov_b32 s2, -13841; GFX6-NEXT: s_waitcnt lgkmcnt(0)3842; GFX6-NEXT: s_and_b32 s5, s10, 0xffff3843; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s53844; GFX6-NEXT: s_lshr_b32 s5, s10, 163845; GFX6-NEXT: s_and_b32 s4, s8, 0xffff3846; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s53847; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s43848; GFX6-NEXT: v_rcp_iflag_f32_e32 v3, v03849; GFX6-NEXT: s_lshr_b32 s4, s8, 163850; GFX6-NEXT: v_cvt_f32_u32_e32 v4, s43851; GFX6-NEXT: v_rcp_iflag_f32_e32 v5, v23852; GFX6-NEXT: v_mul_f32_e32 v3, v1, v33853; GFX6-NEXT: v_trunc_f32_e32 v3, v33854; GFX6-NEXT: v_mad_f32 v1, -v3, v0, v13855; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v03856; GFX6-NEXT: v_mul_f32_e32 v1, v4, v53857; GFX6-NEXT: v_trunc_f32_e32 v1, v13858; GFX6-NEXT: s_and_b32 s4, s11, 0xffff3859; GFX6-NEXT: v_cvt_u32_f32_e32 v6, v33860; GFX6-NEXT: v_mad_f32 v3, -v1, v2, v43861; GFX6-NEXT: v_cvt_f32_u32_e32 v4, s43862; GFX6-NEXT: s_and_b32 s4, s9, 0xffff3863; GFX6-NEXT: v_addc_u32_e32 v0, vcc, 0, v6, vcc3864; GFX6-NEXT: v_cvt_f32_u32_e32 v5, s43865; GFX6-NEXT: v_rcp_iflag_f32_e32 v6, v43866; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v13867; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v23868; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v03869; GFX6-NEXT: v_mul_f32_e32 v2, v5, v63870; GFX6-NEXT: v_trunc_f32_e32 v2, v23871; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v23872; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc3873; GFX6-NEXT: v_mad_f32 v2, -v2, v4, v53874; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v43875; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc3876; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v13877; GFX6-NEXT: v_or_b32_e32 v0, v0, v13878; GFX6-NEXT: buffer_store_short v2, off, s[0:3], 0 offset:43879; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 03880; GFX6-NEXT: s_endpgm3881;3882; GFX9-LABEL: udiv_v3i16:3883; GFX9: ; %bb.0:3884; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c3885; GFX9-NEXT: v_mov_b32_e32 v6, 03886; GFX9-NEXT: s_waitcnt lgkmcnt(0)3887; GFX9-NEXT: s_and_b32 s7, s2, 0xffff3888; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s73889; GFX9-NEXT: s_and_b32 s6, s0, 0xffff3890; GFX9-NEXT: s_lshr_b32 s2, s2, 163891; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s23892; GFX9-NEXT: v_cvt_f32_u32_e32 v2, s63893; GFX9-NEXT: v_rcp_iflag_f32_e32 v4, v03894; GFX9-NEXT: s_lshr_b32 s0, s0, 163895; GFX9-NEXT: v_cvt_f32_u32_e32 v3, s03896; GFX9-NEXT: v_rcp_iflag_f32_e32 v5, v13897; GFX9-NEXT: v_mul_f32_e32 v4, v2, v43898; GFX9-NEXT: v_trunc_f32_e32 v4, v43899; GFX9-NEXT: s_and_b32 s0, s3, 0xffff3900; GFX9-NEXT: v_cvt_u32_f32_e32 v7, v43901; GFX9-NEXT: v_mad_f32 v2, -v4, v0, v23902; GFX9-NEXT: v_cvt_f32_u32_e32 v4, s03903; GFX9-NEXT: v_mul_f32_e32 v5, v3, v53904; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v03905; GFX9-NEXT: v_trunc_f32_e32 v2, v53906; GFX9-NEXT: s_and_b32 s0, s1, 0xffff3907; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, 0, v7, vcc3908; GFX9-NEXT: v_mad_f32 v3, -v2, v1, v33909; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v23910; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s03911; GFX9-NEXT: v_rcp_iflag_f32_e32 v7, v43912; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v13913; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v2, vcc3914; GFX9-NEXT: v_mul_f32_e32 v2, v5, v73915; GFX9-NEXT: v_trunc_f32_e32 v2, v23916; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x243917; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v23918; GFX9-NEXT: v_mad_f32 v2, -v2, v4, v53919; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v43920; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v03921; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v3, vcc3922; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v03923; GFX9-NEXT: s_waitcnt lgkmcnt(0)3924; GFX9-NEXT: global_store_short v6, v2, s[6:7] offset:43925; GFX9-NEXT: global_store_dword v6, v0, s[6:7]3926; GFX9-NEXT: s_endpgm3927 %r = udiv <3 x i16> %x, %y3928 store <3 x i16> %r, ptr addrspace(1) %out3929 ret void3930}3931 3932define amdgpu_kernel void @urem_v3i16(ptr addrspace(1) %out, <3 x i16> %x, <3 x i16> %y) {3933; CHECK-LABEL: @urem_v3i16(3934; CHECK-NEXT: [[TMP1:%.*]] = extractelement <3 x i16> [[X:%.*]], i64 03935; CHECK-NEXT: [[TMP2:%.*]] = extractelement <3 x i16> [[Y:%.*]], i64 03936; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[TMP1]] to i323937; CHECK-NEXT: [[TMP4:%.*]] = zext i16 [[TMP2]] to i323938; CHECK-NEXT: [[TMP5:%.*]] = uitofp i32 [[TMP3]] to float3939; CHECK-NEXT: [[TMP6:%.*]] = uitofp i32 [[TMP4]] to float3940; CHECK-NEXT: [[TMP7:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP6]])3941; CHECK-NEXT: [[TMP8:%.*]] = fmul fast float [[TMP5]], [[TMP7]]3942; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.trunc.f32(float [[TMP8]])3943; CHECK-NEXT: [[TMP10:%.*]] = fneg fast float [[TMP9]]3944; CHECK-NEXT: [[TMP11:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP10]], float [[TMP6]], float [[TMP5]])3945; CHECK-NEXT: [[TMP12:%.*]] = fptoui float [[TMP9]] to i323946; CHECK-NEXT: [[TMP13:%.*]] = call fast float @llvm.fabs.f32(float [[TMP11]])3947; CHECK-NEXT: [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP6]])3948; CHECK-NEXT: [[TMP15:%.*]] = fcmp fast oge float [[TMP13]], [[TMP14]]3949; CHECK-NEXT: [[TMP16:%.*]] = select i1 [[TMP15]], i32 1, i32 03950; CHECK-NEXT: [[TMP17:%.*]] = add i32 [[TMP12]], [[TMP16]]3951; CHECK-NEXT: [[TMP18:%.*]] = mul i32 [[TMP17]], [[TMP4]]3952; CHECK-NEXT: [[TMP19:%.*]] = sub i32 [[TMP3]], [[TMP18]]3953; CHECK-NEXT: [[TMP20:%.*]] = and i32 [[TMP19]], 655353954; CHECK-NEXT: [[TMP21:%.*]] = trunc i32 [[TMP20]] to i163955; CHECK-NEXT: [[TMP22:%.*]] = insertelement <3 x i16> poison, i16 [[TMP21]], i64 03956; CHECK-NEXT: [[TMP23:%.*]] = extractelement <3 x i16> [[X]], i64 13957; CHECK-NEXT: [[TMP24:%.*]] = extractelement <3 x i16> [[Y]], i64 13958; CHECK-NEXT: [[TMP25:%.*]] = zext i16 [[TMP23]] to i323959; CHECK-NEXT: [[TMP26:%.*]] = zext i16 [[TMP24]] to i323960; CHECK-NEXT: [[TMP27:%.*]] = uitofp i32 [[TMP25]] to float3961; CHECK-NEXT: [[TMP28:%.*]] = uitofp i32 [[TMP26]] to float3962; CHECK-NEXT: [[TMP29:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP28]])3963; CHECK-NEXT: [[TMP30:%.*]] = fmul fast float [[TMP27]], [[TMP29]]3964; CHECK-NEXT: [[TMP31:%.*]] = call fast float @llvm.trunc.f32(float [[TMP30]])3965; CHECK-NEXT: [[TMP32:%.*]] = fneg fast float [[TMP31]]3966; CHECK-NEXT: [[TMP33:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP32]], float [[TMP28]], float [[TMP27]])3967; CHECK-NEXT: [[TMP34:%.*]] = fptoui float [[TMP31]] to i323968; CHECK-NEXT: [[TMP35:%.*]] = call fast float @llvm.fabs.f32(float [[TMP33]])3969; CHECK-NEXT: [[TMP36:%.*]] = call fast float @llvm.fabs.f32(float [[TMP28]])3970; CHECK-NEXT: [[TMP37:%.*]] = fcmp fast oge float [[TMP35]], [[TMP36]]3971; CHECK-NEXT: [[TMP38:%.*]] = select i1 [[TMP37]], i32 1, i32 03972; CHECK-NEXT: [[TMP39:%.*]] = add i32 [[TMP34]], [[TMP38]]3973; CHECK-NEXT: [[TMP40:%.*]] = mul i32 [[TMP39]], [[TMP26]]3974; CHECK-NEXT: [[TMP41:%.*]] = sub i32 [[TMP25]], [[TMP40]]3975; CHECK-NEXT: [[TMP42:%.*]] = and i32 [[TMP41]], 655353976; CHECK-NEXT: [[TMP43:%.*]] = trunc i32 [[TMP42]] to i163977; CHECK-NEXT: [[TMP44:%.*]] = insertelement <3 x i16> [[TMP22]], i16 [[TMP43]], i64 13978; CHECK-NEXT: [[TMP45:%.*]] = extractelement <3 x i16> [[X]], i64 23979; CHECK-NEXT: [[TMP46:%.*]] = extractelement <3 x i16> [[Y]], i64 23980; CHECK-NEXT: [[TMP47:%.*]] = zext i16 [[TMP45]] to i323981; CHECK-NEXT: [[TMP48:%.*]] = zext i16 [[TMP46]] to i323982; CHECK-NEXT: [[TMP49:%.*]] = uitofp i32 [[TMP47]] to float3983; CHECK-NEXT: [[TMP50:%.*]] = uitofp i32 [[TMP48]] to float3984; CHECK-NEXT: [[TMP51:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP50]])3985; CHECK-NEXT: [[TMP52:%.*]] = fmul fast float [[TMP49]], [[TMP51]]3986; CHECK-NEXT: [[TMP53:%.*]] = call fast float @llvm.trunc.f32(float [[TMP52]])3987; CHECK-NEXT: [[TMP54:%.*]] = fneg fast float [[TMP53]]3988; CHECK-NEXT: [[TMP55:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP54]], float [[TMP50]], float [[TMP49]])3989; CHECK-NEXT: [[TMP56:%.*]] = fptoui float [[TMP53]] to i323990; CHECK-NEXT: [[TMP57:%.*]] = call fast float @llvm.fabs.f32(float [[TMP55]])3991; CHECK-NEXT: [[TMP58:%.*]] = call fast float @llvm.fabs.f32(float [[TMP50]])3992; CHECK-NEXT: [[TMP59:%.*]] = fcmp fast oge float [[TMP57]], [[TMP58]]3993; CHECK-NEXT: [[TMP60:%.*]] = select i1 [[TMP59]], i32 1, i32 03994; CHECK-NEXT: [[TMP61:%.*]] = add i32 [[TMP56]], [[TMP60]]3995; CHECK-NEXT: [[TMP62:%.*]] = mul i32 [[TMP61]], [[TMP48]]3996; CHECK-NEXT: [[TMP63:%.*]] = sub i32 [[TMP47]], [[TMP62]]3997; CHECK-NEXT: [[TMP64:%.*]] = and i32 [[TMP63]], 655353998; CHECK-NEXT: [[TMP65:%.*]] = trunc i32 [[TMP64]] to i163999; CHECK-NEXT: [[TMP66:%.*]] = insertelement <3 x i16> [[TMP44]], i16 [[TMP65]], i64 24000; CHECK-NEXT: store <3 x i16> [[TMP66]], ptr addrspace(1) [[OUT:%.*]], align 84001; CHECK-NEXT: ret void4002;4003; GFX6-LABEL: urem_v3i16:4004; GFX6: ; %bb.0:4005; GFX6-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0xb4006; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x94007; GFX6-NEXT: s_mov_b32 s3, 0xf0004008; GFX6-NEXT: s_mov_b32 s2, -14009; GFX6-NEXT: s_waitcnt lgkmcnt(0)4010; GFX6-NEXT: s_and_b32 s5, s10, 0xffff4011; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s54012; GFX6-NEXT: s_lshr_b32 s5, s10, 164013; GFX6-NEXT: s_and_b32 s4, s8, 0xffff4014; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s54015; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s44016; GFX6-NEXT: v_rcp_iflag_f32_e32 v3, v04017; GFX6-NEXT: s_lshr_b32 s4, s8, 164018; GFX6-NEXT: v_cvt_f32_u32_e32 v4, s44019; GFX6-NEXT: v_rcp_iflag_f32_e32 v5, v24020; GFX6-NEXT: v_mul_f32_e32 v3, v1, v34021; GFX6-NEXT: v_trunc_f32_e32 v3, v34022; GFX6-NEXT: v_mad_f32 v1, -v3, v0, v14023; GFX6-NEXT: v_cvt_u32_f32_e32 v6, v34024; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v04025; GFX6-NEXT: v_mul_f32_e32 v1, v4, v54026; GFX6-NEXT: v_trunc_f32_e32 v1, v14027; GFX6-NEXT: s_and_b32 s6, s11, 0xffff4028; GFX6-NEXT: v_mad_f32 v3, -v1, v2, v44029; GFX6-NEXT: v_cvt_f32_u32_e32 v4, s64030; GFX6-NEXT: v_addc_u32_e32 v0, vcc, 0, v6, vcc4031; GFX6-NEXT: v_mul_lo_u32 v0, v0, s104032; GFX6-NEXT: s_and_b32 s6, s9, 0xffff4033; GFX6-NEXT: v_cvt_f32_u32_e32 v5, s64034; GFX6-NEXT: v_rcp_iflag_f32_e32 v6, v44035; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s8, v04036; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v14037; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v24038; GFX6-NEXT: v_mul_f32_e32 v2, v5, v64039; GFX6-NEXT: v_trunc_f32_e32 v2, v24040; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v24041; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc4042; GFX6-NEXT: v_mad_f32 v2, -v2, v4, v54043; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v44044; GFX6-NEXT: v_mul_lo_u32 v1, v1, s54045; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc4046; GFX6-NEXT: v_mul_lo_u32 v2, v2, s114047; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s4, v14048; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v14049; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s9, v24050; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v04051; GFX6-NEXT: v_or_b32_e32 v0, v0, v14052; GFX6-NEXT: buffer_store_short v2, off, s[0:3], 0 offset:44053; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 04054; GFX6-NEXT: s_endpgm4055;4056; GFX9-LABEL: urem_v3i16:4057; GFX9: ; %bb.0:4058; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c4059; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x244060; GFX9-NEXT: s_waitcnt lgkmcnt(0)4061; GFX9-NEXT: s_and_b32 s9, s2, 0xffff4062; GFX9-NEXT: s_lshr_b32 s2, s2, 164063; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s94064; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s24065; GFX9-NEXT: s_and_b32 s8, s0, 0xffff4066; GFX9-NEXT: s_lshr_b32 s0, s0, 164067; GFX9-NEXT: v_cvt_f32_u32_e32 v2, s84068; GFX9-NEXT: v_rcp_iflag_f32_e32 v4, v04069; GFX9-NEXT: v_cvt_f32_u32_e32 v3, s04070; GFX9-NEXT: v_rcp_iflag_f32_e32 v5, v14071; GFX9-NEXT: s_and_b32 s3, s3, 0xffff4072; GFX9-NEXT: v_mul_f32_e32 v4, v2, v44073; GFX9-NEXT: v_trunc_f32_e32 v4, v44074; GFX9-NEXT: v_mul_f32_e32 v5, v3, v54075; GFX9-NEXT: v_trunc_f32_e32 v5, v54076; GFX9-NEXT: v_mad_f32 v2, -v4, v0, v24077; GFX9-NEXT: v_cvt_u32_f32_e32 v6, v44078; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v04079; GFX9-NEXT: v_mad_f32 v2, -v5, v1, v34080; GFX9-NEXT: v_cvt_f32_u32_e32 v3, s34081; GFX9-NEXT: s_and_b32 s1, s1, 0xffff4082; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, 0, v6, vcc4083; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v54084; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s14085; GFX9-NEXT: v_rcp_iflag_f32_e32 v6, v34086; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v14087; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v4, vcc4088; GFX9-NEXT: v_mul_f32_e32 v2, v5, v64089; GFX9-NEXT: v_trunc_f32_e32 v2, v24090; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v24091; GFX9-NEXT: v_mad_f32 v2, -v2, v3, v54092; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v34093; GFX9-NEXT: v_mul_lo_u32 v0, v0, s94094; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v4, vcc4095; GFX9-NEXT: v_mul_lo_u32 v1, v1, s24096; GFX9-NEXT: v_mul_lo_u32 v2, v2, s34097; GFX9-NEXT: v_sub_u32_e32 v0, s8, v04098; GFX9-NEXT: v_mov_b32_e32 v3, 04099; GFX9-NEXT: v_sub_u32_e32 v1, s0, v14100; GFX9-NEXT: v_sub_u32_e32 v2, s1, v24101; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v04102; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v04103; GFX9-NEXT: global_store_short v3, v2, s[6:7] offset:44104; GFX9-NEXT: global_store_dword v3, v0, s[6:7]4105; GFX9-NEXT: s_endpgm4106 %r = urem <3 x i16> %x, %y4107 store <3 x i16> %r, ptr addrspace(1) %out4108 ret void4109}4110 4111define amdgpu_kernel void @sdiv_v3i16(ptr addrspace(1) %out, <3 x i16> %x, <3 x i16> %y) {4112; CHECK-LABEL: @sdiv_v3i16(4113; CHECK-NEXT: [[TMP1:%.*]] = extractelement <3 x i16> [[X:%.*]], i64 04114; CHECK-NEXT: [[TMP2:%.*]] = extractelement <3 x i16> [[Y:%.*]], i64 04115; CHECK-NEXT: [[TMP3:%.*]] = sext i16 [[TMP1]] to i324116; CHECK-NEXT: [[TMP4:%.*]] = sext i16 [[TMP2]] to i324117; CHECK-NEXT: [[TMP5:%.*]] = xor i32 [[TMP3]], [[TMP4]]4118; CHECK-NEXT: [[TMP6:%.*]] = ashr i32 [[TMP5]], 304119; CHECK-NEXT: [[TMP7:%.*]] = or i32 [[TMP6]], 14120; CHECK-NEXT: [[TMP8:%.*]] = sitofp i32 [[TMP3]] to float4121; CHECK-NEXT: [[TMP9:%.*]] = sitofp i32 [[TMP4]] to float4122; CHECK-NEXT: [[TMP10:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP9]])4123; CHECK-NEXT: [[TMP11:%.*]] = fmul fast float [[TMP8]], [[TMP10]]4124; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.trunc.f32(float [[TMP11]])4125; CHECK-NEXT: [[TMP13:%.*]] = fneg fast float [[TMP12]]4126; CHECK-NEXT: [[TMP14:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP13]], float [[TMP9]], float [[TMP8]])4127; CHECK-NEXT: [[TMP15:%.*]] = fptosi float [[TMP12]] to i324128; CHECK-NEXT: [[TMP16:%.*]] = call fast float @llvm.fabs.f32(float [[TMP14]])4129; CHECK-NEXT: [[TMP17:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])4130; CHECK-NEXT: [[TMP18:%.*]] = fcmp fast oge float [[TMP16]], [[TMP17]]4131; CHECK-NEXT: [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP7]], i32 04132; CHECK-NEXT: [[TMP20:%.*]] = add i32 [[TMP15]], [[TMP19]]4133; CHECK-NEXT: [[TMP21:%.*]] = shl i32 [[TMP20]], 164134; CHECK-NEXT: [[TMP22:%.*]] = ashr i32 [[TMP21]], 164135; CHECK-NEXT: [[TMP23:%.*]] = trunc i32 [[TMP22]] to i164136; CHECK-NEXT: [[TMP24:%.*]] = insertelement <3 x i16> poison, i16 [[TMP23]], i64 04137; CHECK-NEXT: [[TMP25:%.*]] = extractelement <3 x i16> [[X]], i64 14138; CHECK-NEXT: [[TMP26:%.*]] = extractelement <3 x i16> [[Y]], i64 14139; CHECK-NEXT: [[TMP27:%.*]] = sext i16 [[TMP25]] to i324140; CHECK-NEXT: [[TMP28:%.*]] = sext i16 [[TMP26]] to i324141; CHECK-NEXT: [[TMP29:%.*]] = xor i32 [[TMP27]], [[TMP28]]4142; CHECK-NEXT: [[TMP30:%.*]] = ashr i32 [[TMP29]], 304143; CHECK-NEXT: [[TMP31:%.*]] = or i32 [[TMP30]], 14144; CHECK-NEXT: [[TMP32:%.*]] = sitofp i32 [[TMP27]] to float4145; CHECK-NEXT: [[TMP33:%.*]] = sitofp i32 [[TMP28]] to float4146; CHECK-NEXT: [[TMP34:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP33]])4147; CHECK-NEXT: [[TMP35:%.*]] = fmul fast float [[TMP32]], [[TMP34]]4148; CHECK-NEXT: [[TMP36:%.*]] = call fast float @llvm.trunc.f32(float [[TMP35]])4149; CHECK-NEXT: [[TMP37:%.*]] = fneg fast float [[TMP36]]4150; CHECK-NEXT: [[TMP38:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP37]], float [[TMP33]], float [[TMP32]])4151; CHECK-NEXT: [[TMP39:%.*]] = fptosi float [[TMP36]] to i324152; CHECK-NEXT: [[TMP40:%.*]] = call fast float @llvm.fabs.f32(float [[TMP38]])4153; CHECK-NEXT: [[TMP41:%.*]] = call fast float @llvm.fabs.f32(float [[TMP33]])4154; CHECK-NEXT: [[TMP42:%.*]] = fcmp fast oge float [[TMP40]], [[TMP41]]4155; CHECK-NEXT: [[TMP43:%.*]] = select i1 [[TMP42]], i32 [[TMP31]], i32 04156; CHECK-NEXT: [[TMP44:%.*]] = add i32 [[TMP39]], [[TMP43]]4157; CHECK-NEXT: [[TMP45:%.*]] = shl i32 [[TMP44]], 164158; CHECK-NEXT: [[TMP46:%.*]] = ashr i32 [[TMP45]], 164159; CHECK-NEXT: [[TMP47:%.*]] = trunc i32 [[TMP46]] to i164160; CHECK-NEXT: [[TMP48:%.*]] = insertelement <3 x i16> [[TMP24]], i16 [[TMP47]], i64 14161; CHECK-NEXT: [[TMP49:%.*]] = extractelement <3 x i16> [[X]], i64 24162; CHECK-NEXT: [[TMP50:%.*]] = extractelement <3 x i16> [[Y]], i64 24163; CHECK-NEXT: [[TMP51:%.*]] = sext i16 [[TMP49]] to i324164; CHECK-NEXT: [[TMP52:%.*]] = sext i16 [[TMP50]] to i324165; CHECK-NEXT: [[TMP53:%.*]] = xor i32 [[TMP51]], [[TMP52]]4166; CHECK-NEXT: [[TMP54:%.*]] = ashr i32 [[TMP53]], 304167; CHECK-NEXT: [[TMP55:%.*]] = or i32 [[TMP54]], 14168; CHECK-NEXT: [[TMP56:%.*]] = sitofp i32 [[TMP51]] to float4169; CHECK-NEXT: [[TMP57:%.*]] = sitofp i32 [[TMP52]] to float4170; CHECK-NEXT: [[TMP58:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP57]])4171; CHECK-NEXT: [[TMP59:%.*]] = fmul fast float [[TMP56]], [[TMP58]]4172; CHECK-NEXT: [[TMP60:%.*]] = call fast float @llvm.trunc.f32(float [[TMP59]])4173; CHECK-NEXT: [[TMP61:%.*]] = fneg fast float [[TMP60]]4174; CHECK-NEXT: [[TMP62:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP61]], float [[TMP57]], float [[TMP56]])4175; CHECK-NEXT: [[TMP63:%.*]] = fptosi float [[TMP60]] to i324176; CHECK-NEXT: [[TMP64:%.*]] = call fast float @llvm.fabs.f32(float [[TMP62]])4177; CHECK-NEXT: [[TMP65:%.*]] = call fast float @llvm.fabs.f32(float [[TMP57]])4178; CHECK-NEXT: [[TMP66:%.*]] = fcmp fast oge float [[TMP64]], [[TMP65]]4179; CHECK-NEXT: [[TMP67:%.*]] = select i1 [[TMP66]], i32 [[TMP55]], i32 04180; CHECK-NEXT: [[TMP68:%.*]] = add i32 [[TMP63]], [[TMP67]]4181; CHECK-NEXT: [[TMP69:%.*]] = shl i32 [[TMP68]], 164182; CHECK-NEXT: [[TMP70:%.*]] = ashr i32 [[TMP69]], 164183; CHECK-NEXT: [[TMP71:%.*]] = trunc i32 [[TMP70]] to i164184; CHECK-NEXT: [[TMP72:%.*]] = insertelement <3 x i16> [[TMP48]], i16 [[TMP71]], i64 24185; CHECK-NEXT: store <3 x i16> [[TMP72]], ptr addrspace(1) [[OUT:%.*]], align 84186; CHECK-NEXT: ret void4187;4188; GFX6-LABEL: sdiv_v3i16:4189; GFX6: ; %bb.0:4190; GFX6-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0xb4191; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x94192; GFX6-NEXT: s_mov_b32 s3, 0xf0004193; GFX6-NEXT: s_mov_b32 s2, -14194; GFX6-NEXT: s_waitcnt lgkmcnt(0)4195; GFX6-NEXT: s_sext_i32_i16 s4, s104196; GFX6-NEXT: v_cvt_f32_i32_e32 v0, s44197; GFX6-NEXT: s_sext_i32_i16 s5, s84198; GFX6-NEXT: v_cvt_f32_i32_e32 v1, s54199; GFX6-NEXT: s_xor_b32 s4, s5, s44200; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v04201; GFX6-NEXT: s_ashr_i32 s4, s4, 304202; GFX6-NEXT: s_or_b32 s6, s4, 14203; GFX6-NEXT: v_mul_f32_e32 v2, v1, v24204; GFX6-NEXT: v_trunc_f32_e32 v2, v24205; GFX6-NEXT: v_mad_f32 v1, -v2, v0, v14206; GFX6-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0|4207; GFX6-NEXT: s_and_b64 s[4:5], s[4:5], exec4208; GFX6-NEXT: v_cvt_i32_f32_e32 v2, v24209; GFX6-NEXT: s_cselect_b32 s4, s6, 04210; GFX6-NEXT: s_ashr_i32 s5, s10, 164211; GFX6-NEXT: v_cvt_f32_i32_e32 v0, s54212; GFX6-NEXT: v_add_i32_e32 v1, vcc, s4, v24213; GFX6-NEXT: s_ashr_i32 s4, s8, 164214; GFX6-NEXT: v_cvt_f32_i32_e32 v2, s44215; GFX6-NEXT: v_rcp_iflag_f32_e32 v3, v04216; GFX6-NEXT: s_xor_b32 s4, s4, s54217; GFX6-NEXT: s_ashr_i32 s4, s4, 304218; GFX6-NEXT: s_or_b32 s6, s4, 14219; GFX6-NEXT: v_mul_f32_e32 v3, v2, v34220; GFX6-NEXT: v_trunc_f32_e32 v3, v34221; GFX6-NEXT: v_mad_f32 v2, -v3, v0, v24222; GFX6-NEXT: v_cmp_ge_f32_e64 s[4:5], |v2|, |v0|4223; GFX6-NEXT: s_and_b64 s[4:5], s[4:5], exec4224; GFX6-NEXT: v_cvt_i32_f32_e32 v3, v34225; GFX6-NEXT: s_sext_i32_i16 s5, s114226; GFX6-NEXT: v_cvt_f32_i32_e32 v0, s54227; GFX6-NEXT: s_cselect_b32 s4, s6, 04228; GFX6-NEXT: v_add_i32_e32 v2, vcc, s4, v34229; GFX6-NEXT: s_sext_i32_i16 s4, s94230; GFX6-NEXT: v_cvt_f32_i32_e32 v3, s44231; GFX6-NEXT: v_rcp_iflag_f32_e32 v4, v04232; GFX6-NEXT: s_xor_b32 s4, s4, s54233; GFX6-NEXT: s_ashr_i32 s4, s4, 304234; GFX6-NEXT: s_or_b32 s6, s4, 14235; GFX6-NEXT: v_mul_f32_e32 v4, v3, v44236; GFX6-NEXT: v_trunc_f32_e32 v4, v44237; GFX6-NEXT: v_mad_f32 v3, -v4, v0, v34238; GFX6-NEXT: v_cvt_i32_f32_e32 v4, v44239; GFX6-NEXT: v_cmp_ge_f32_e64 s[4:5], |v3|, |v0|4240; GFX6-NEXT: s_and_b64 s[4:5], s[4:5], exec4241; GFX6-NEXT: s_cselect_b32 s4, s6, 04242; GFX6-NEXT: v_add_i32_e32 v0, vcc, s4, v44243; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v24244; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v14245; GFX6-NEXT: v_or_b32_e32 v1, v1, v24246; GFX6-NEXT: buffer_store_short v0, off, s[0:3], 0 offset:44247; GFX6-NEXT: buffer_store_dword v1, off, s[0:3], 04248; GFX6-NEXT: s_endpgm4249;4250; GFX9-LABEL: sdiv_v3i16:4251; GFX9: ; %bb.0:4252; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c4253; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x244254; GFX9-NEXT: v_mov_b32_e32 v1, 04255; GFX9-NEXT: s_waitcnt lgkmcnt(0)4256; GFX9-NEXT: s_sext_i32_i16 s4, s24257; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s44258; GFX9-NEXT: s_sext_i32_i16 s5, s04259; GFX9-NEXT: v_cvt_f32_i32_e32 v2, s54260; GFX9-NEXT: s_xor_b32 s4, s5, s44261; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v04262; GFX9-NEXT: s_ashr_i32 s4, s4, 304263; GFX9-NEXT: s_or_b32 s8, s4, 14264; GFX9-NEXT: v_mul_f32_e32 v3, v2, v34265; GFX9-NEXT: v_trunc_f32_e32 v3, v34266; GFX9-NEXT: v_mad_f32 v2, -v3, v0, v24267; GFX9-NEXT: v_cmp_ge_f32_e64 s[4:5], |v2|, |v0|4268; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec4269; GFX9-NEXT: s_cselect_b32 s4, s8, 04270; GFX9-NEXT: s_ashr_i32 s2, s2, 164271; GFX9-NEXT: v_cvt_i32_f32_e32 v3, v34272; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s24273; GFX9-NEXT: s_ashr_i32 s0, s0, 164274; GFX9-NEXT: v_add_u32_e32 v2, s4, v34275; GFX9-NEXT: v_cvt_f32_i32_e32 v3, s04276; GFX9-NEXT: v_rcp_iflag_f32_e32 v4, v04277; GFX9-NEXT: s_xor_b32 s0, s0, s24278; GFX9-NEXT: s_ashr_i32 s0, s0, 304279; GFX9-NEXT: s_sext_i32_i16 s2, s34280; GFX9-NEXT: v_mul_f32_e32 v4, v3, v44281; GFX9-NEXT: v_trunc_f32_e32 v4, v44282; GFX9-NEXT: v_mad_f32 v3, -v4, v0, v34283; GFX9-NEXT: v_cvt_i32_f32_e32 v4, v44284; GFX9-NEXT: s_or_b32 s0, s0, 14285; GFX9-NEXT: v_cmp_ge_f32_e64 s[4:5], |v3|, |v0|4286; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s24287; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec4288; GFX9-NEXT: s_cselect_b32 s0, s0, 04289; GFX9-NEXT: v_add_u32_e32 v3, s0, v44290; GFX9-NEXT: s_sext_i32_i16 s0, s14291; GFX9-NEXT: v_cvt_f32_i32_e32 v4, s04292; GFX9-NEXT: v_rcp_iflag_f32_e32 v5, v04293; GFX9-NEXT: s_xor_b32 s0, s0, s24294; GFX9-NEXT: s_ashr_i32 s0, s0, 304295; GFX9-NEXT: s_or_b32 s2, s0, 14296; GFX9-NEXT: v_mul_f32_e32 v5, v4, v54297; GFX9-NEXT: v_trunc_f32_e32 v5, v54298; GFX9-NEXT: v_mad_f32 v4, -v5, v0, v44299; GFX9-NEXT: v_cvt_i32_f32_e32 v5, v54300; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v4|, |v0|4301; GFX9-NEXT: s_and_b64 s[0:1], s[0:1], exec4302; GFX9-NEXT: s_cselect_b32 s0, s2, 04303; GFX9-NEXT: v_add_u32_e32 v0, s0, v54304; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v24305; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v24306; GFX9-NEXT: global_store_short v1, v0, s[6:7] offset:44307; GFX9-NEXT: global_store_dword v1, v2, s[6:7]4308; GFX9-NEXT: s_endpgm4309 %r = sdiv <3 x i16> %x, %y4310 store <3 x i16> %r, ptr addrspace(1) %out4311 ret void4312}4313 4314define amdgpu_kernel void @srem_v3i16(ptr addrspace(1) %out, <3 x i16> %x, <3 x i16> %y) {4315; CHECK-LABEL: @srem_v3i16(4316; CHECK-NEXT: [[TMP1:%.*]] = extractelement <3 x i16> [[X:%.*]], i64 04317; CHECK-NEXT: [[TMP2:%.*]] = extractelement <3 x i16> [[Y:%.*]], i64 04318; CHECK-NEXT: [[TMP3:%.*]] = sext i16 [[TMP1]] to i324319; CHECK-NEXT: [[TMP4:%.*]] = sext i16 [[TMP2]] to i324320; CHECK-NEXT: [[TMP5:%.*]] = xor i32 [[TMP3]], [[TMP4]]4321; CHECK-NEXT: [[TMP6:%.*]] = ashr i32 [[TMP5]], 304322; CHECK-NEXT: [[TMP7:%.*]] = or i32 [[TMP6]], 14323; CHECK-NEXT: [[TMP8:%.*]] = sitofp i32 [[TMP3]] to float4324; CHECK-NEXT: [[TMP9:%.*]] = sitofp i32 [[TMP4]] to float4325; CHECK-NEXT: [[TMP10:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP9]])4326; CHECK-NEXT: [[TMP11:%.*]] = fmul fast float [[TMP8]], [[TMP10]]4327; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.trunc.f32(float [[TMP11]])4328; CHECK-NEXT: [[TMP13:%.*]] = fneg fast float [[TMP12]]4329; CHECK-NEXT: [[TMP14:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP13]], float [[TMP9]], float [[TMP8]])4330; CHECK-NEXT: [[TMP15:%.*]] = fptosi float [[TMP12]] to i324331; CHECK-NEXT: [[TMP16:%.*]] = call fast float @llvm.fabs.f32(float [[TMP14]])4332; CHECK-NEXT: [[TMP17:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])4333; CHECK-NEXT: [[TMP18:%.*]] = fcmp fast oge float [[TMP16]], [[TMP17]]4334; CHECK-NEXT: [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP7]], i32 04335; CHECK-NEXT: [[TMP20:%.*]] = add i32 [[TMP15]], [[TMP19]]4336; CHECK-NEXT: [[TMP21:%.*]] = mul i32 [[TMP20]], [[TMP4]]4337; CHECK-NEXT: [[TMP22:%.*]] = sub i32 [[TMP3]], [[TMP21]]4338; CHECK-NEXT: [[TMP23:%.*]] = shl i32 [[TMP22]], 164339; CHECK-NEXT: [[TMP24:%.*]] = ashr i32 [[TMP23]], 164340; CHECK-NEXT: [[TMP25:%.*]] = trunc i32 [[TMP24]] to i164341; CHECK-NEXT: [[TMP26:%.*]] = insertelement <3 x i16> poison, i16 [[TMP25]], i64 04342; CHECK-NEXT: [[TMP27:%.*]] = extractelement <3 x i16> [[X]], i64 14343; CHECK-NEXT: [[TMP28:%.*]] = extractelement <3 x i16> [[Y]], i64 14344; CHECK-NEXT: [[TMP29:%.*]] = sext i16 [[TMP27]] to i324345; CHECK-NEXT: [[TMP30:%.*]] = sext i16 [[TMP28]] to i324346; CHECK-NEXT: [[TMP31:%.*]] = xor i32 [[TMP29]], [[TMP30]]4347; CHECK-NEXT: [[TMP32:%.*]] = ashr i32 [[TMP31]], 304348; CHECK-NEXT: [[TMP33:%.*]] = or i32 [[TMP32]], 14349; CHECK-NEXT: [[TMP34:%.*]] = sitofp i32 [[TMP29]] to float4350; CHECK-NEXT: [[TMP35:%.*]] = sitofp i32 [[TMP30]] to float4351; CHECK-NEXT: [[TMP36:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP35]])4352; CHECK-NEXT: [[TMP37:%.*]] = fmul fast float [[TMP34]], [[TMP36]]4353; CHECK-NEXT: [[TMP38:%.*]] = call fast float @llvm.trunc.f32(float [[TMP37]])4354; CHECK-NEXT: [[TMP39:%.*]] = fneg fast float [[TMP38]]4355; CHECK-NEXT: [[TMP40:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP39]], float [[TMP35]], float [[TMP34]])4356; CHECK-NEXT: [[TMP41:%.*]] = fptosi float [[TMP38]] to i324357; CHECK-NEXT: [[TMP42:%.*]] = call fast float @llvm.fabs.f32(float [[TMP40]])4358; CHECK-NEXT: [[TMP43:%.*]] = call fast float @llvm.fabs.f32(float [[TMP35]])4359; CHECK-NEXT: [[TMP44:%.*]] = fcmp fast oge float [[TMP42]], [[TMP43]]4360; CHECK-NEXT: [[TMP45:%.*]] = select i1 [[TMP44]], i32 [[TMP33]], i32 04361; CHECK-NEXT: [[TMP46:%.*]] = add i32 [[TMP41]], [[TMP45]]4362; CHECK-NEXT: [[TMP47:%.*]] = mul i32 [[TMP46]], [[TMP30]]4363; CHECK-NEXT: [[TMP48:%.*]] = sub i32 [[TMP29]], [[TMP47]]4364; CHECK-NEXT: [[TMP49:%.*]] = shl i32 [[TMP48]], 164365; CHECK-NEXT: [[TMP50:%.*]] = ashr i32 [[TMP49]], 164366; CHECK-NEXT: [[TMP51:%.*]] = trunc i32 [[TMP50]] to i164367; CHECK-NEXT: [[TMP52:%.*]] = insertelement <3 x i16> [[TMP26]], i16 [[TMP51]], i64 14368; CHECK-NEXT: [[TMP53:%.*]] = extractelement <3 x i16> [[X]], i64 24369; CHECK-NEXT: [[TMP54:%.*]] = extractelement <3 x i16> [[Y]], i64 24370; CHECK-NEXT: [[TMP55:%.*]] = sext i16 [[TMP53]] to i324371; CHECK-NEXT: [[TMP56:%.*]] = sext i16 [[TMP54]] to i324372; CHECK-NEXT: [[TMP57:%.*]] = xor i32 [[TMP55]], [[TMP56]]4373; CHECK-NEXT: [[TMP58:%.*]] = ashr i32 [[TMP57]], 304374; CHECK-NEXT: [[TMP59:%.*]] = or i32 [[TMP58]], 14375; CHECK-NEXT: [[TMP60:%.*]] = sitofp i32 [[TMP55]] to float4376; CHECK-NEXT: [[TMP61:%.*]] = sitofp i32 [[TMP56]] to float4377; CHECK-NEXT: [[TMP62:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP61]])4378; CHECK-NEXT: [[TMP63:%.*]] = fmul fast float [[TMP60]], [[TMP62]]4379; CHECK-NEXT: [[TMP64:%.*]] = call fast float @llvm.trunc.f32(float [[TMP63]])4380; CHECK-NEXT: [[TMP65:%.*]] = fneg fast float [[TMP64]]4381; CHECK-NEXT: [[TMP66:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP65]], float [[TMP61]], float [[TMP60]])4382; CHECK-NEXT: [[TMP67:%.*]] = fptosi float [[TMP64]] to i324383; CHECK-NEXT: [[TMP68:%.*]] = call fast float @llvm.fabs.f32(float [[TMP66]])4384; CHECK-NEXT: [[TMP69:%.*]] = call fast float @llvm.fabs.f32(float [[TMP61]])4385; CHECK-NEXT: [[TMP70:%.*]] = fcmp fast oge float [[TMP68]], [[TMP69]]4386; CHECK-NEXT: [[TMP71:%.*]] = select i1 [[TMP70]], i32 [[TMP59]], i32 04387; CHECK-NEXT: [[TMP72:%.*]] = add i32 [[TMP67]], [[TMP71]]4388; CHECK-NEXT: [[TMP73:%.*]] = mul i32 [[TMP72]], [[TMP56]]4389; CHECK-NEXT: [[TMP74:%.*]] = sub i32 [[TMP55]], [[TMP73]]4390; CHECK-NEXT: [[TMP75:%.*]] = shl i32 [[TMP74]], 164391; CHECK-NEXT: [[TMP76:%.*]] = ashr i32 [[TMP75]], 164392; CHECK-NEXT: [[TMP77:%.*]] = trunc i32 [[TMP76]] to i164393; CHECK-NEXT: [[TMP78:%.*]] = insertelement <3 x i16> [[TMP52]], i16 [[TMP77]], i64 24394; CHECK-NEXT: store <3 x i16> [[TMP78]], ptr addrspace(1) [[OUT:%.*]], align 84395; CHECK-NEXT: ret void4396;4397; GFX6-LABEL: srem_v3i16:4398; GFX6: ; %bb.0:4399; GFX6-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0xb4400; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x94401; GFX6-NEXT: s_mov_b32 s3, 0xf0004402; GFX6-NEXT: s_mov_b32 s2, -14403; GFX6-NEXT: s_waitcnt lgkmcnt(0)4404; GFX6-NEXT: s_sext_i32_i16 s4, s104405; GFX6-NEXT: v_cvt_f32_i32_e32 v0, s44406; GFX6-NEXT: s_sext_i32_i16 s5, s84407; GFX6-NEXT: v_cvt_f32_i32_e32 v1, s54408; GFX6-NEXT: s_xor_b32 s4, s5, s44409; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v04410; GFX6-NEXT: s_ashr_i32 s4, s4, 304411; GFX6-NEXT: s_or_b32 s6, s4, 14412; GFX6-NEXT: v_mul_f32_e32 v2, v1, v24413; GFX6-NEXT: v_trunc_f32_e32 v2, v24414; GFX6-NEXT: v_mad_f32 v1, -v2, v0, v14415; GFX6-NEXT: v_cvt_i32_f32_e32 v2, v24416; GFX6-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0|4417; GFX6-NEXT: s_and_b64 s[4:5], s[4:5], exec4418; GFX6-NEXT: s_cselect_b32 s4, s6, 04419; GFX6-NEXT: v_add_i32_e32 v0, vcc, s4, v24420; GFX6-NEXT: s_ashr_i32 s4, s10, 164421; GFX6-NEXT: v_cvt_f32_i32_e32 v1, s44422; GFX6-NEXT: s_ashr_i32 s5, s8, 164423; GFX6-NEXT: v_cvt_f32_i32_e32 v2, s54424; GFX6-NEXT: v_mul_lo_u32 v0, v0, s104425; GFX6-NEXT: v_rcp_iflag_f32_e32 v3, v14426; GFX6-NEXT: s_xor_b32 s4, s5, s44427; GFX6-NEXT: s_ashr_i32 s4, s4, 304428; GFX6-NEXT: s_lshr_b32 s6, s8, 164429; GFX6-NEXT: v_mul_f32_e32 v3, v2, v34430; GFX6-NEXT: v_trunc_f32_e32 v3, v34431; GFX6-NEXT: v_mad_f32 v2, -v3, v1, v24432; GFX6-NEXT: v_cvt_i32_f32_e32 v3, v34433; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s8, v04434; GFX6-NEXT: s_lshr_b32 s7, s10, 164435; GFX6-NEXT: s_or_b32 s8, s4, 14436; GFX6-NEXT: v_cmp_ge_f32_e64 s[4:5], |v2|, |v1|4437; GFX6-NEXT: s_and_b64 s[4:5], s[4:5], exec4438; GFX6-NEXT: s_cselect_b32 s4, s8, 04439; GFX6-NEXT: v_add_i32_e32 v1, vcc, s4, v34440; GFX6-NEXT: s_sext_i32_i16 s4, s114441; GFX6-NEXT: v_cvt_f32_i32_e32 v2, s44442; GFX6-NEXT: s_sext_i32_i16 s5, s94443; GFX6-NEXT: v_cvt_f32_i32_e32 v3, s54444; GFX6-NEXT: s_xor_b32 s4, s5, s44445; GFX6-NEXT: v_rcp_iflag_f32_e32 v4, v24446; GFX6-NEXT: s_ashr_i32 s4, s4, 304447; GFX6-NEXT: v_mul_lo_u32 v1, v1, s74448; GFX6-NEXT: s_or_b32 s7, s4, 14449; GFX6-NEXT: v_mul_f32_e32 v4, v3, v44450; GFX6-NEXT: v_trunc_f32_e32 v4, v44451; GFX6-NEXT: v_mad_f32 v3, -v4, v2, v34452; GFX6-NEXT: v_cvt_i32_f32_e32 v4, v44453; GFX6-NEXT: v_cmp_ge_f32_e64 s[4:5], |v3|, |v2|4454; GFX6-NEXT: s_and_b64 s[4:5], s[4:5], exec4455; GFX6-NEXT: s_cselect_b32 s4, s7, 04456; GFX6-NEXT: v_add_i32_e32 v2, vcc, s4, v44457; GFX6-NEXT: v_mul_lo_u32 v2, v2, s114458; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s6, v14459; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v14460; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s9, v24461; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v04462; GFX6-NEXT: v_or_b32_e32 v0, v0, v14463; GFX6-NEXT: buffer_store_short v2, off, s[0:3], 0 offset:44464; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 04465; GFX6-NEXT: s_endpgm4466;4467; GFX9-LABEL: srem_v3i16:4468; GFX9: ; %bb.0:4469; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c4470; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x244471; GFX9-NEXT: s_waitcnt lgkmcnt(0)4472; GFX9-NEXT: s_sext_i32_i16 s8, s24473; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s84474; GFX9-NEXT: s_sext_i32_i16 s9, s04475; GFX9-NEXT: v_cvt_f32_i32_e32 v1, s94476; GFX9-NEXT: s_xor_b32 s4, s9, s84477; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v04478; GFX9-NEXT: s_ashr_i32 s4, s4, 304479; GFX9-NEXT: s_or_b32 s10, s4, 14480; GFX9-NEXT: v_mul_f32_e32 v2, v1, v24481; GFX9-NEXT: v_trunc_f32_e32 v2, v24482; GFX9-NEXT: v_mad_f32 v1, -v2, v0, v14483; GFX9-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0|4484; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec4485; GFX9-NEXT: s_cselect_b32 s4, s10, 04486; GFX9-NEXT: s_ashr_i32 s10, s0, 164487; GFX9-NEXT: s_ashr_i32 s0, s2, 164488; GFX9-NEXT: v_cvt_i32_f32_e32 v2, v24489; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s04490; GFX9-NEXT: s_xor_b32 s2, s10, s04491; GFX9-NEXT: s_ashr_i32 s2, s2, 304492; GFX9-NEXT: v_add_u32_e32 v1, s4, v24493; GFX9-NEXT: v_cvt_f32_i32_e32 v2, s104494; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v04495; GFX9-NEXT: s_or_b32 s2, s2, 14496; GFX9-NEXT: v_mul_lo_u32 v1, v1, s84497; GFX9-NEXT: v_mul_f32_e32 v3, v2, v34498; GFX9-NEXT: v_trunc_f32_e32 v3, v34499; GFX9-NEXT: v_mad_f32 v2, -v3, v0, v24500; GFX9-NEXT: v_cvt_i32_f32_e32 v3, v34501; GFX9-NEXT: v_cmp_ge_f32_e64 s[4:5], |v2|, |v0|4502; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec4503; GFX9-NEXT: s_cselect_b32 s2, s2, 04504; GFX9-NEXT: v_add_u32_e32 v0, s2, v34505; GFX9-NEXT: s_sext_i32_i16 s2, s34506; GFX9-NEXT: v_cvt_f32_i32_e32 v2, s24507; GFX9-NEXT: s_sext_i32_i16 s3, s14508; GFX9-NEXT: v_cvt_f32_i32_e32 v3, s34509; GFX9-NEXT: v_mul_lo_u32 v0, v0, s04510; GFX9-NEXT: v_rcp_iflag_f32_e32 v4, v24511; GFX9-NEXT: s_xor_b32 s0, s3, s24512; GFX9-NEXT: s_ashr_i32 s0, s0, 304513; GFX9-NEXT: s_or_b32 s4, s0, 14514; GFX9-NEXT: v_mul_f32_e32 v4, v3, v44515; GFX9-NEXT: v_trunc_f32_e32 v4, v44516; GFX9-NEXT: v_mad_f32 v3, -v4, v2, v34517; GFX9-NEXT: v_cvt_i32_f32_e32 v4, v44518; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v3|, |v2|4519; GFX9-NEXT: s_and_b64 s[0:1], s[0:1], exec4520; GFX9-NEXT: s_cselect_b32 s0, s4, 04521; GFX9-NEXT: v_add_u32_e32 v2, s0, v44522; GFX9-NEXT: v_mul_lo_u32 v2, v2, s24523; GFX9-NEXT: v_sub_u32_e32 v1, s9, v14524; GFX9-NEXT: v_mov_b32_e32 v3, 04525; GFX9-NEXT: v_sub_u32_e32 v0, s10, v04526; GFX9-NEXT: v_sub_u32_e32 v2, s3, v24527; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v14528; GFX9-NEXT: v_lshl_or_b32 v0, v0, 16, v14529; GFX9-NEXT: global_store_short v3, v2, s[6:7] offset:44530; GFX9-NEXT: global_store_dword v3, v0, s[6:7]4531; GFX9-NEXT: s_endpgm4532 %r = srem <3 x i16> %x, %y4533 store <3 x i16> %r, ptr addrspace(1) %out4534 ret void4535}4536 4537define amdgpu_kernel void @udiv_v3i15(ptr addrspace(1) %out, <3 x i15> %x, <3 x i15> %y) {4538; CHECK-LABEL: @udiv_v3i15(4539; CHECK-NEXT: [[TMP1:%.*]] = extractelement <3 x i15> [[X:%.*]], i64 04540; CHECK-NEXT: [[TMP2:%.*]] = extractelement <3 x i15> [[Y:%.*]], i64 04541; CHECK-NEXT: [[TMP3:%.*]] = zext i15 [[TMP1]] to i324542; CHECK-NEXT: [[TMP4:%.*]] = zext i15 [[TMP2]] to i324543; CHECK-NEXT: [[TMP5:%.*]] = uitofp i32 [[TMP3]] to float4544; CHECK-NEXT: [[TMP6:%.*]] = uitofp i32 [[TMP4]] to float4545; CHECK-NEXT: [[TMP7:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP6]])4546; CHECK-NEXT: [[TMP8:%.*]] = fmul fast float [[TMP5]], [[TMP7]]4547; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.trunc.f32(float [[TMP8]])4548; CHECK-NEXT: [[TMP10:%.*]] = fneg fast float [[TMP9]]4549; CHECK-NEXT: [[TMP11:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP10]], float [[TMP6]], float [[TMP5]])4550; CHECK-NEXT: [[TMP12:%.*]] = fptoui float [[TMP9]] to i324551; CHECK-NEXT: [[TMP13:%.*]] = call fast float @llvm.fabs.f32(float [[TMP11]])4552; CHECK-NEXT: [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP6]])4553; CHECK-NEXT: [[TMP15:%.*]] = fcmp fast oge float [[TMP13]], [[TMP14]]4554; CHECK-NEXT: [[TMP16:%.*]] = select i1 [[TMP15]], i32 1, i32 04555; CHECK-NEXT: [[TMP17:%.*]] = add i32 [[TMP12]], [[TMP16]]4556; CHECK-NEXT: [[TMP18:%.*]] = and i32 [[TMP17]], 327674557; CHECK-NEXT: [[TMP19:%.*]] = trunc i32 [[TMP18]] to i154558; CHECK-NEXT: [[TMP20:%.*]] = insertelement <3 x i15> poison, i15 [[TMP19]], i64 04559; CHECK-NEXT: [[TMP21:%.*]] = extractelement <3 x i15> [[X]], i64 14560; CHECK-NEXT: [[TMP22:%.*]] = extractelement <3 x i15> [[Y]], i64 14561; CHECK-NEXT: [[TMP23:%.*]] = zext i15 [[TMP21]] to i324562; CHECK-NEXT: [[TMP24:%.*]] = zext i15 [[TMP22]] to i324563; CHECK-NEXT: [[TMP25:%.*]] = uitofp i32 [[TMP23]] to float4564; CHECK-NEXT: [[TMP26:%.*]] = uitofp i32 [[TMP24]] to float4565; CHECK-NEXT: [[TMP27:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP26]])4566; CHECK-NEXT: [[TMP28:%.*]] = fmul fast float [[TMP25]], [[TMP27]]4567; CHECK-NEXT: [[TMP29:%.*]] = call fast float @llvm.trunc.f32(float [[TMP28]])4568; CHECK-NEXT: [[TMP30:%.*]] = fneg fast float [[TMP29]]4569; CHECK-NEXT: [[TMP31:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP30]], float [[TMP26]], float [[TMP25]])4570; CHECK-NEXT: [[TMP32:%.*]] = fptoui float [[TMP29]] to i324571; CHECK-NEXT: [[TMP33:%.*]] = call fast float @llvm.fabs.f32(float [[TMP31]])4572; CHECK-NEXT: [[TMP34:%.*]] = call fast float @llvm.fabs.f32(float [[TMP26]])4573; CHECK-NEXT: [[TMP35:%.*]] = fcmp fast oge float [[TMP33]], [[TMP34]]4574; CHECK-NEXT: [[TMP36:%.*]] = select i1 [[TMP35]], i32 1, i32 04575; CHECK-NEXT: [[TMP37:%.*]] = add i32 [[TMP32]], [[TMP36]]4576; CHECK-NEXT: [[TMP38:%.*]] = and i32 [[TMP37]], 327674577; CHECK-NEXT: [[TMP39:%.*]] = trunc i32 [[TMP38]] to i154578; CHECK-NEXT: [[TMP40:%.*]] = insertelement <3 x i15> [[TMP20]], i15 [[TMP39]], i64 14579; CHECK-NEXT: [[TMP41:%.*]] = extractelement <3 x i15> [[X]], i64 24580; CHECK-NEXT: [[TMP42:%.*]] = extractelement <3 x i15> [[Y]], i64 24581; CHECK-NEXT: [[TMP43:%.*]] = zext i15 [[TMP41]] to i324582; CHECK-NEXT: [[TMP44:%.*]] = zext i15 [[TMP42]] to i324583; CHECK-NEXT: [[TMP45:%.*]] = uitofp i32 [[TMP43]] to float4584; CHECK-NEXT: [[TMP46:%.*]] = uitofp i32 [[TMP44]] to float4585; CHECK-NEXT: [[TMP47:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP46]])4586; CHECK-NEXT: [[TMP48:%.*]] = fmul fast float [[TMP45]], [[TMP47]]4587; CHECK-NEXT: [[TMP49:%.*]] = call fast float @llvm.trunc.f32(float [[TMP48]])4588; CHECK-NEXT: [[TMP50:%.*]] = fneg fast float [[TMP49]]4589; CHECK-NEXT: [[TMP51:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP50]], float [[TMP46]], float [[TMP45]])4590; CHECK-NEXT: [[TMP52:%.*]] = fptoui float [[TMP49]] to i324591; CHECK-NEXT: [[TMP53:%.*]] = call fast float @llvm.fabs.f32(float [[TMP51]])4592; CHECK-NEXT: [[TMP54:%.*]] = call fast float @llvm.fabs.f32(float [[TMP46]])4593; CHECK-NEXT: [[TMP55:%.*]] = fcmp fast oge float [[TMP53]], [[TMP54]]4594; CHECK-NEXT: [[TMP56:%.*]] = select i1 [[TMP55]], i32 1, i32 04595; CHECK-NEXT: [[TMP57:%.*]] = add i32 [[TMP52]], [[TMP56]]4596; CHECK-NEXT: [[TMP58:%.*]] = and i32 [[TMP57]], 327674597; CHECK-NEXT: [[TMP59:%.*]] = trunc i32 [[TMP58]] to i154598; CHECK-NEXT: [[TMP60:%.*]] = insertelement <3 x i15> [[TMP40]], i15 [[TMP59]], i64 24599; CHECK-NEXT: store <3 x i15> [[TMP60]], ptr addrspace(1) [[OUT:%.*]], align 84600; CHECK-NEXT: ret void4601;4602; GFX6-LABEL: udiv_v3i15:4603; GFX6: ; %bb.0:4604; GFX6-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x94605; GFX6-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd4606; GFX6-NEXT: s_mov_b32 s3, 0xf0004607; GFX6-NEXT: s_mov_b32 s2, -14608; GFX6-NEXT: s_waitcnt lgkmcnt(0)4609; GFX6-NEXT: s_lshr_b64 s[6:7], s[10:11], 304610; GFX6-NEXT: s_mov_b32 s0, s84611; GFX6-NEXT: s_and_b32 s8, s6, 0x7fff4612; GFX6-NEXT: s_and_b32 s6, s4, 0x7fff4613; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s64614; GFX6-NEXT: s_and_b32 s6, s10, 0x7fff4615; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s64616; GFX6-NEXT: s_lshr_b64 s[6:7], s[4:5], 304617; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v04618; GFX6-NEXT: s_bfe_u32 s4, s4, 0xf000f4619; GFX6-NEXT: v_cvt_f32_u32_e32 v3, s44620; GFX6-NEXT: s_mov_b32 s1, s94621; GFX6-NEXT: s_bfe_u32 s9, s10, 0xf000f4622; GFX6-NEXT: v_mul_f32_e32 v2, v1, v24623; GFX6-NEXT: v_trunc_f32_e32 v2, v24624; GFX6-NEXT: v_cvt_f32_u32_e32 v4, s94625; GFX6-NEXT: v_rcp_iflag_f32_e32 v5, v34626; GFX6-NEXT: s_and_b32 s5, s6, 0x7fff4627; GFX6-NEXT: v_mad_f32 v1, -v2, v0, v14628; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v04629; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s54630; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v24631; GFX6-NEXT: v_mul_f32_e32 v0, v4, v54632; GFX6-NEXT: v_trunc_f32_e32 v0, v04633; GFX6-NEXT: v_mad_f32 v4, -v0, v3, v44634; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v04635; GFX6-NEXT: v_cvt_f32_u32_e32 v5, s84636; GFX6-NEXT: v_rcp_iflag_f32_e32 v6, v14637; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc4638; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, v34639; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v0, vcc4640; GFX6-NEXT: v_mul_f32_e32 v0, v5, v64641; GFX6-NEXT: v_trunc_f32_e32 v0, v04642; GFX6-NEXT: v_cvt_u32_f32_e32 v4, v04643; GFX6-NEXT: v_mad_f32 v0, -v0, v1, v54644; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, v14645; GFX6-NEXT: v_and_b32_e32 v3, 0x7fff, v34646; GFX6-NEXT: v_addc_u32_e32 v0, vcc, 0, v4, vcc4647; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 304648; GFX6-NEXT: v_and_b32_e32 v2, 0x7fff, v24649; GFX6-NEXT: v_lshlrev_b32_e32 v3, 15, v34650; GFX6-NEXT: v_or_b32_e32 v2, v3, v24651; GFX6-NEXT: v_or_b32_e32 v0, v2, v04652; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 04653; GFX6-NEXT: s_waitcnt expcnt(0)4654; GFX6-NEXT: v_and_b32_e32 v0, 0x1fff, v14655; GFX6-NEXT: buffer_store_short v0, off, s[0:3], 0 offset:44656; GFX6-NEXT: s_endpgm4657;4658; GFX9-LABEL: udiv_v3i15:4659; GFX9: ; %bb.0:4660; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x244661; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x344662; GFX9-NEXT: v_mov_b32_e32 v2, 04663; GFX9-NEXT: s_waitcnt lgkmcnt(0)4664; GFX9-NEXT: s_lshr_b64 s[4:5], s[2:3], 304665; GFX9-NEXT: s_and_b32 s3, s6, 0x7fff4666; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s34667; GFX9-NEXT: s_and_b32 s5, s2, 0x7fff4668; GFX9-NEXT: s_bfe_u32 s8, s2, 0xf000f4669; GFX9-NEXT: s_lshr_b64 s[2:3], s[6:7], 304670; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s54671; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v04672; GFX9-NEXT: s_bfe_u32 s3, s6, 0xf000f4673; GFX9-NEXT: v_cvt_f32_u32_e32 v4, s34674; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s84675; GFX9-NEXT: v_mul_f32_e32 v3, v1, v34676; GFX9-NEXT: v_trunc_f32_e32 v3, v34677; GFX9-NEXT: v_rcp_iflag_f32_e32 v6, v44678; GFX9-NEXT: s_and_b32 s2, s2, 0x7fff4679; GFX9-NEXT: v_mad_f32 v1, -v3, v0, v14680; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v04681; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s24682; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v34683; GFX9-NEXT: v_mul_f32_e32 v0, v5, v64684; GFX9-NEXT: s_and_b32 s4, s4, 0x7fff4685; GFX9-NEXT: v_trunc_f32_e32 v0, v04686; GFX9-NEXT: v_mad_f32 v5, -v0, v4, v54687; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v04688; GFX9-NEXT: v_cvt_f32_u32_e32 v6, s44689; GFX9-NEXT: v_rcp_iflag_f32_e32 v7, v14690; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc4691; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v5|, v44692; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v0, vcc4693; GFX9-NEXT: v_mul_f32_e32 v0, v6, v74694; GFX9-NEXT: v_trunc_f32_e32 v0, v04695; GFX9-NEXT: v_cvt_u32_f32_e32 v5, v04696; GFX9-NEXT: v_mad_f32 v0, -v0, v1, v64697; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, v14698; GFX9-NEXT: v_and_b32_e32 v4, 0x7fff, v44699; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, 0, v5, vcc4700; GFX9-NEXT: v_lshlrev_b64 v[0:1], 30, v[0:1]4701; GFX9-NEXT: v_and_b32_e32 v3, 0x7fff, v34702; GFX9-NEXT: v_lshlrev_b32_e32 v4, 15, v44703; GFX9-NEXT: v_or_b32_e32 v3, v3, v44704; GFX9-NEXT: v_or_b32_e32 v0, v3, v04705; GFX9-NEXT: global_store_dword v2, v0, s[0:1]4706; GFX9-NEXT: v_and_b32_e32 v0, 0x1fff, v14707; GFX9-NEXT: global_store_short v2, v0, s[0:1] offset:44708; GFX9-NEXT: s_endpgm4709 %r = udiv <3 x i15> %x, %y4710 store <3 x i15> %r, ptr addrspace(1) %out4711 ret void4712}4713 4714define amdgpu_kernel void @urem_v3i15(ptr addrspace(1) %out, <3 x i15> %x, <3 x i15> %y) {4715; CHECK-LABEL: @urem_v3i15(4716; CHECK-NEXT: [[TMP1:%.*]] = extractelement <3 x i15> [[X:%.*]], i64 04717; CHECK-NEXT: [[TMP2:%.*]] = extractelement <3 x i15> [[Y:%.*]], i64 04718; CHECK-NEXT: [[TMP3:%.*]] = zext i15 [[TMP1]] to i324719; CHECK-NEXT: [[TMP4:%.*]] = zext i15 [[TMP2]] to i324720; CHECK-NEXT: [[TMP5:%.*]] = uitofp i32 [[TMP3]] to float4721; CHECK-NEXT: [[TMP6:%.*]] = uitofp i32 [[TMP4]] to float4722; CHECK-NEXT: [[TMP7:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP6]])4723; CHECK-NEXT: [[TMP8:%.*]] = fmul fast float [[TMP5]], [[TMP7]]4724; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.trunc.f32(float [[TMP8]])4725; CHECK-NEXT: [[TMP10:%.*]] = fneg fast float [[TMP9]]4726; CHECK-NEXT: [[TMP11:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP10]], float [[TMP6]], float [[TMP5]])4727; CHECK-NEXT: [[TMP12:%.*]] = fptoui float [[TMP9]] to i324728; CHECK-NEXT: [[TMP13:%.*]] = call fast float @llvm.fabs.f32(float [[TMP11]])4729; CHECK-NEXT: [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP6]])4730; CHECK-NEXT: [[TMP15:%.*]] = fcmp fast oge float [[TMP13]], [[TMP14]]4731; CHECK-NEXT: [[TMP16:%.*]] = select i1 [[TMP15]], i32 1, i32 04732; CHECK-NEXT: [[TMP17:%.*]] = add i32 [[TMP12]], [[TMP16]]4733; CHECK-NEXT: [[TMP18:%.*]] = mul i32 [[TMP17]], [[TMP4]]4734; CHECK-NEXT: [[TMP19:%.*]] = sub i32 [[TMP3]], [[TMP18]]4735; CHECK-NEXT: [[TMP20:%.*]] = and i32 [[TMP19]], 327674736; CHECK-NEXT: [[TMP21:%.*]] = trunc i32 [[TMP20]] to i154737; CHECK-NEXT: [[TMP22:%.*]] = insertelement <3 x i15> poison, i15 [[TMP21]], i64 04738; CHECK-NEXT: [[TMP23:%.*]] = extractelement <3 x i15> [[X]], i64 14739; CHECK-NEXT: [[TMP24:%.*]] = extractelement <3 x i15> [[Y]], i64 14740; CHECK-NEXT: [[TMP25:%.*]] = zext i15 [[TMP23]] to i324741; CHECK-NEXT: [[TMP26:%.*]] = zext i15 [[TMP24]] to i324742; CHECK-NEXT: [[TMP27:%.*]] = uitofp i32 [[TMP25]] to float4743; CHECK-NEXT: [[TMP28:%.*]] = uitofp i32 [[TMP26]] to float4744; CHECK-NEXT: [[TMP29:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP28]])4745; CHECK-NEXT: [[TMP30:%.*]] = fmul fast float [[TMP27]], [[TMP29]]4746; CHECK-NEXT: [[TMP31:%.*]] = call fast float @llvm.trunc.f32(float [[TMP30]])4747; CHECK-NEXT: [[TMP32:%.*]] = fneg fast float [[TMP31]]4748; CHECK-NEXT: [[TMP33:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP32]], float [[TMP28]], float [[TMP27]])4749; CHECK-NEXT: [[TMP34:%.*]] = fptoui float [[TMP31]] to i324750; CHECK-NEXT: [[TMP35:%.*]] = call fast float @llvm.fabs.f32(float [[TMP33]])4751; CHECK-NEXT: [[TMP36:%.*]] = call fast float @llvm.fabs.f32(float [[TMP28]])4752; CHECK-NEXT: [[TMP37:%.*]] = fcmp fast oge float [[TMP35]], [[TMP36]]4753; CHECK-NEXT: [[TMP38:%.*]] = select i1 [[TMP37]], i32 1, i32 04754; CHECK-NEXT: [[TMP39:%.*]] = add i32 [[TMP34]], [[TMP38]]4755; CHECK-NEXT: [[TMP40:%.*]] = mul i32 [[TMP39]], [[TMP26]]4756; CHECK-NEXT: [[TMP41:%.*]] = sub i32 [[TMP25]], [[TMP40]]4757; CHECK-NEXT: [[TMP42:%.*]] = and i32 [[TMP41]], 327674758; CHECK-NEXT: [[TMP43:%.*]] = trunc i32 [[TMP42]] to i154759; CHECK-NEXT: [[TMP44:%.*]] = insertelement <3 x i15> [[TMP22]], i15 [[TMP43]], i64 14760; CHECK-NEXT: [[TMP45:%.*]] = extractelement <3 x i15> [[X]], i64 24761; CHECK-NEXT: [[TMP46:%.*]] = extractelement <3 x i15> [[Y]], i64 24762; CHECK-NEXT: [[TMP47:%.*]] = zext i15 [[TMP45]] to i324763; CHECK-NEXT: [[TMP48:%.*]] = zext i15 [[TMP46]] to i324764; CHECK-NEXT: [[TMP49:%.*]] = uitofp i32 [[TMP47]] to float4765; CHECK-NEXT: [[TMP50:%.*]] = uitofp i32 [[TMP48]] to float4766; CHECK-NEXT: [[TMP51:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP50]])4767; CHECK-NEXT: [[TMP52:%.*]] = fmul fast float [[TMP49]], [[TMP51]]4768; CHECK-NEXT: [[TMP53:%.*]] = call fast float @llvm.trunc.f32(float [[TMP52]])4769; CHECK-NEXT: [[TMP54:%.*]] = fneg fast float [[TMP53]]4770; CHECK-NEXT: [[TMP55:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP54]], float [[TMP50]], float [[TMP49]])4771; CHECK-NEXT: [[TMP56:%.*]] = fptoui float [[TMP53]] to i324772; CHECK-NEXT: [[TMP57:%.*]] = call fast float @llvm.fabs.f32(float [[TMP55]])4773; CHECK-NEXT: [[TMP58:%.*]] = call fast float @llvm.fabs.f32(float [[TMP50]])4774; CHECK-NEXT: [[TMP59:%.*]] = fcmp fast oge float [[TMP57]], [[TMP58]]4775; CHECK-NEXT: [[TMP60:%.*]] = select i1 [[TMP59]], i32 1, i32 04776; CHECK-NEXT: [[TMP61:%.*]] = add i32 [[TMP56]], [[TMP60]]4777; CHECK-NEXT: [[TMP62:%.*]] = mul i32 [[TMP61]], [[TMP48]]4778; CHECK-NEXT: [[TMP63:%.*]] = sub i32 [[TMP47]], [[TMP62]]4779; CHECK-NEXT: [[TMP64:%.*]] = and i32 [[TMP63]], 327674780; CHECK-NEXT: [[TMP65:%.*]] = trunc i32 [[TMP64]] to i154781; CHECK-NEXT: [[TMP66:%.*]] = insertelement <3 x i15> [[TMP44]], i15 [[TMP65]], i64 24782; CHECK-NEXT: store <3 x i15> [[TMP66]], ptr addrspace(1) [[OUT:%.*]], align 84783; CHECK-NEXT: ret void4784;4785; GFX6-LABEL: urem_v3i15:4786; GFX6: ; %bb.0:4787; GFX6-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x94788; GFX6-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd4789; GFX6-NEXT: s_mov_b32 s3, 0xf0004790; GFX6-NEXT: s_mov_b32 s2, -14791; GFX6-NEXT: s_waitcnt lgkmcnt(0)4792; GFX6-NEXT: s_lshr_b64 s[6:7], s[10:11], 304793; GFX6-NEXT: s_mov_b32 s0, s84794; GFX6-NEXT: s_and_b32 s8, s6, 0x7fff4795; GFX6-NEXT: s_and_b32 s6, s4, 0x7fff4796; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s64797; GFX6-NEXT: s_and_b32 s6, s10, 0x7fff4798; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s64799; GFX6-NEXT: s_lshr_b64 s[6:7], s[4:5], 304800; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v04801; GFX6-NEXT: s_and_b32 s5, s6, 0x7fff4802; GFX6-NEXT: s_bfe_u32 s6, s4, 0xf000f4803; GFX6-NEXT: v_cvt_f32_u32_e32 v3, s64804; GFX6-NEXT: v_mul_f32_e32 v2, v1, v24805; GFX6-NEXT: v_trunc_f32_e32 v2, v24806; GFX6-NEXT: v_mad_f32 v1, -v2, v0, v14807; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v24808; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v04809; GFX6-NEXT: s_bfe_u32 s11, s10, 0xf000f4810; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s114811; GFX6-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc4812; GFX6-NEXT: v_mul_lo_u32 v0, v0, s44813; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v34814; GFX6-NEXT: v_cvt_f32_u32_e32 v5, s84815; GFX6-NEXT: s_lshr_b32 s4, s4, 154816; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s10, v04817; GFX6-NEXT: v_mul_f32_e32 v0, v1, v24818; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s54819; GFX6-NEXT: v_trunc_f32_e32 v0, v04820; GFX6-NEXT: v_mad_f32 v1, -v0, v3, v14821; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v04822; GFX6-NEXT: v_rcp_iflag_f32_e32 v6, v24823; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v34824; GFX6-NEXT: s_mov_b32 s1, s94825; GFX6-NEXT: v_addc_u32_e32 v0, vcc, 0, v0, vcc4826; GFX6-NEXT: v_mul_f32_e32 v1, v5, v64827; GFX6-NEXT: v_trunc_f32_e32 v1, v14828; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v14829; GFX6-NEXT: v_mad_f32 v1, -v1, v2, v54830; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v24831; GFX6-NEXT: v_mul_lo_u32 v0, v0, s44832; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc4833; GFX6-NEXT: v_mul_lo_u32 v1, v1, s54834; GFX6-NEXT: s_lshr_b32 s9, s10, 154835; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s9, v04836; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s8, v14837; GFX6-NEXT: v_and_b32_e32 v2, 0x7fff, v24838; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 304839; GFX6-NEXT: v_and_b32_e32 v3, 0x7fff, v44840; GFX6-NEXT: v_lshlrev_b32_e32 v2, 15, v24841; GFX6-NEXT: v_or_b32_e32 v2, v2, v34842; GFX6-NEXT: v_or_b32_e32 v0, v2, v04843; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 04844; GFX6-NEXT: s_waitcnt expcnt(0)4845; GFX6-NEXT: v_and_b32_e32 v0, 0x1fff, v14846; GFX6-NEXT: buffer_store_short v0, off, s[0:3], 0 offset:44847; GFX6-NEXT: s_endpgm4848;4849; GFX9-LABEL: urem_v3i15:4850; GFX9: ; %bb.0:4851; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x244852; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x344853; GFX9-NEXT: v_mov_b32_e32 v2, 04854; GFX9-NEXT: s_waitcnt lgkmcnt(0)4855; GFX9-NEXT: s_lshr_b64 s[4:5], s[2:3], 304856; GFX9-NEXT: s_and_b32 s5, s6, 0x7fff4857; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s54858; GFX9-NEXT: s_and_b32 s3, s2, 0x7fff4859; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s34860; GFX9-NEXT: s_and_b32 s8, s4, 0x7fff4861; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v04862; GFX9-NEXT: s_lshr_b64 s[4:5], s[6:7], 304863; GFX9-NEXT: s_bfe_u32 s5, s6, 0xf000f4864; GFX9-NEXT: v_cvt_f32_u32_e32 v4, s54865; GFX9-NEXT: v_mul_f32_e32 v3, v1, v34866; GFX9-NEXT: v_trunc_f32_e32 v3, v34867; GFX9-NEXT: v_mad_f32 v1, -v3, v0, v14868; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v34869; GFX9-NEXT: s_bfe_u32 s9, s2, 0xf000f4870; GFX9-NEXT: s_and_b32 s3, s4, 0x7fff4871; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v04872; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s94873; GFX9-NEXT: v_rcp_iflag_f32_e32 v6, v44874; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, 0, v3, vcc4875; GFX9-NEXT: v_cvt_f32_u32_e32 v3, s34876; GFX9-NEXT: v_mul_f32_e32 v1, v5, v64877; GFX9-NEXT: v_cvt_f32_u32_e32 v6, s84878; GFX9-NEXT: v_trunc_f32_e32 v1, v14879; GFX9-NEXT: v_rcp_iflag_f32_e32 v7, v34880; GFX9-NEXT: v_mad_f32 v5, -v1, v4, v54881; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v14882; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v5|, v44883; GFX9-NEXT: v_mul_f32_e32 v4, v6, v74884; GFX9-NEXT: v_trunc_f32_e32 v4, v44885; GFX9-NEXT: v_cvt_u32_f32_e32 v5, v44886; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc4887; GFX9-NEXT: v_mad_f32 v4, -v4, v3, v64888; GFX9-NEXT: s_lshr_b32 s4, s6, 154889; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, v34890; GFX9-NEXT: v_mul_lo_u32 v0, v0, s64891; GFX9-NEXT: v_mul_lo_u32 v1, v1, s44892; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v5, vcc4893; GFX9-NEXT: v_mul_lo_u32 v3, v3, s34894; GFX9-NEXT: s_lshr_b32 s3, s2, 154895; GFX9-NEXT: v_sub_u32_e32 v4, s2, v04896; GFX9-NEXT: v_sub_u32_e32 v5, s3, v14897; GFX9-NEXT: v_sub_u32_e32 v0, s8, v34898; GFX9-NEXT: v_and_b32_e32 v3, 0x7fff, v44899; GFX9-NEXT: v_and_b32_e32 v4, 0x7fff, v54900; GFX9-NEXT: v_lshlrev_b64 v[0:1], 30, v[0:1]4901; GFX9-NEXT: v_lshlrev_b32_e32 v4, 15, v44902; GFX9-NEXT: v_or_b32_e32 v3, v3, v44903; GFX9-NEXT: v_or_b32_e32 v0, v3, v04904; GFX9-NEXT: global_store_dword v2, v0, s[0:1]4905; GFX9-NEXT: v_and_b32_e32 v0, 0x1fff, v14906; GFX9-NEXT: global_store_short v2, v0, s[0:1] offset:44907; GFX9-NEXT: s_endpgm4908 %r = urem <3 x i15> %x, %y4909 store <3 x i15> %r, ptr addrspace(1) %out4910 ret void4911}4912 4913define amdgpu_kernel void @sdiv_v3i15(ptr addrspace(1) %out, <3 x i15> %x, <3 x i15> %y) {4914; CHECK-LABEL: @sdiv_v3i15(4915; CHECK-NEXT: [[TMP1:%.*]] = extractelement <3 x i15> [[X:%.*]], i64 04916; CHECK-NEXT: [[TMP2:%.*]] = extractelement <3 x i15> [[Y:%.*]], i64 04917; CHECK-NEXT: [[TMP3:%.*]] = sext i15 [[TMP1]] to i324918; CHECK-NEXT: [[TMP4:%.*]] = sext i15 [[TMP2]] to i324919; CHECK-NEXT: [[TMP5:%.*]] = xor i32 [[TMP3]], [[TMP4]]4920; CHECK-NEXT: [[TMP6:%.*]] = ashr i32 [[TMP5]], 304921; CHECK-NEXT: [[TMP7:%.*]] = or i32 [[TMP6]], 14922; CHECK-NEXT: [[TMP8:%.*]] = sitofp i32 [[TMP3]] to float4923; CHECK-NEXT: [[TMP9:%.*]] = sitofp i32 [[TMP4]] to float4924; CHECK-NEXT: [[TMP10:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP9]])4925; CHECK-NEXT: [[TMP11:%.*]] = fmul fast float [[TMP8]], [[TMP10]]4926; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.trunc.f32(float [[TMP11]])4927; CHECK-NEXT: [[TMP13:%.*]] = fneg fast float [[TMP12]]4928; CHECK-NEXT: [[TMP14:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP13]], float [[TMP9]], float [[TMP8]])4929; CHECK-NEXT: [[TMP15:%.*]] = fptosi float [[TMP12]] to i324930; CHECK-NEXT: [[TMP16:%.*]] = call fast float @llvm.fabs.f32(float [[TMP14]])4931; CHECK-NEXT: [[TMP17:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])4932; CHECK-NEXT: [[TMP18:%.*]] = fcmp fast oge float [[TMP16]], [[TMP17]]4933; CHECK-NEXT: [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP7]], i32 04934; CHECK-NEXT: [[TMP20:%.*]] = add i32 [[TMP15]], [[TMP19]]4935; CHECK-NEXT: [[TMP21:%.*]] = shl i32 [[TMP20]], 174936; CHECK-NEXT: [[TMP22:%.*]] = ashr i32 [[TMP21]], 174937; CHECK-NEXT: [[TMP23:%.*]] = trunc i32 [[TMP22]] to i154938; CHECK-NEXT: [[TMP24:%.*]] = insertelement <3 x i15> poison, i15 [[TMP23]], i64 04939; CHECK-NEXT: [[TMP25:%.*]] = extractelement <3 x i15> [[X]], i64 14940; CHECK-NEXT: [[TMP26:%.*]] = extractelement <3 x i15> [[Y]], i64 14941; CHECK-NEXT: [[TMP27:%.*]] = sext i15 [[TMP25]] to i324942; CHECK-NEXT: [[TMP28:%.*]] = sext i15 [[TMP26]] to i324943; CHECK-NEXT: [[TMP29:%.*]] = xor i32 [[TMP27]], [[TMP28]]4944; CHECK-NEXT: [[TMP30:%.*]] = ashr i32 [[TMP29]], 304945; CHECK-NEXT: [[TMP31:%.*]] = or i32 [[TMP30]], 14946; CHECK-NEXT: [[TMP32:%.*]] = sitofp i32 [[TMP27]] to float4947; CHECK-NEXT: [[TMP33:%.*]] = sitofp i32 [[TMP28]] to float4948; CHECK-NEXT: [[TMP34:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP33]])4949; CHECK-NEXT: [[TMP35:%.*]] = fmul fast float [[TMP32]], [[TMP34]]4950; CHECK-NEXT: [[TMP36:%.*]] = call fast float @llvm.trunc.f32(float [[TMP35]])4951; CHECK-NEXT: [[TMP37:%.*]] = fneg fast float [[TMP36]]4952; CHECK-NEXT: [[TMP38:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP37]], float [[TMP33]], float [[TMP32]])4953; CHECK-NEXT: [[TMP39:%.*]] = fptosi float [[TMP36]] to i324954; CHECK-NEXT: [[TMP40:%.*]] = call fast float @llvm.fabs.f32(float [[TMP38]])4955; CHECK-NEXT: [[TMP41:%.*]] = call fast float @llvm.fabs.f32(float [[TMP33]])4956; CHECK-NEXT: [[TMP42:%.*]] = fcmp fast oge float [[TMP40]], [[TMP41]]4957; CHECK-NEXT: [[TMP43:%.*]] = select i1 [[TMP42]], i32 [[TMP31]], i32 04958; CHECK-NEXT: [[TMP44:%.*]] = add i32 [[TMP39]], [[TMP43]]4959; CHECK-NEXT: [[TMP45:%.*]] = shl i32 [[TMP44]], 174960; CHECK-NEXT: [[TMP46:%.*]] = ashr i32 [[TMP45]], 174961; CHECK-NEXT: [[TMP47:%.*]] = trunc i32 [[TMP46]] to i154962; CHECK-NEXT: [[TMP48:%.*]] = insertelement <3 x i15> [[TMP24]], i15 [[TMP47]], i64 14963; CHECK-NEXT: [[TMP49:%.*]] = extractelement <3 x i15> [[X]], i64 24964; CHECK-NEXT: [[TMP50:%.*]] = extractelement <3 x i15> [[Y]], i64 24965; CHECK-NEXT: [[TMP51:%.*]] = sext i15 [[TMP49]] to i324966; CHECK-NEXT: [[TMP52:%.*]] = sext i15 [[TMP50]] to i324967; CHECK-NEXT: [[TMP53:%.*]] = xor i32 [[TMP51]], [[TMP52]]4968; CHECK-NEXT: [[TMP54:%.*]] = ashr i32 [[TMP53]], 304969; CHECK-NEXT: [[TMP55:%.*]] = or i32 [[TMP54]], 14970; CHECK-NEXT: [[TMP56:%.*]] = sitofp i32 [[TMP51]] to float4971; CHECK-NEXT: [[TMP57:%.*]] = sitofp i32 [[TMP52]] to float4972; CHECK-NEXT: [[TMP58:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP57]])4973; CHECK-NEXT: [[TMP59:%.*]] = fmul fast float [[TMP56]], [[TMP58]]4974; CHECK-NEXT: [[TMP60:%.*]] = call fast float @llvm.trunc.f32(float [[TMP59]])4975; CHECK-NEXT: [[TMP61:%.*]] = fneg fast float [[TMP60]]4976; CHECK-NEXT: [[TMP62:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP61]], float [[TMP57]], float [[TMP56]])4977; CHECK-NEXT: [[TMP63:%.*]] = fptosi float [[TMP60]] to i324978; CHECK-NEXT: [[TMP64:%.*]] = call fast float @llvm.fabs.f32(float [[TMP62]])4979; CHECK-NEXT: [[TMP65:%.*]] = call fast float @llvm.fabs.f32(float [[TMP57]])4980; CHECK-NEXT: [[TMP66:%.*]] = fcmp fast oge float [[TMP64]], [[TMP65]]4981; CHECK-NEXT: [[TMP67:%.*]] = select i1 [[TMP66]], i32 [[TMP55]], i32 04982; CHECK-NEXT: [[TMP68:%.*]] = add i32 [[TMP63]], [[TMP67]]4983; CHECK-NEXT: [[TMP69:%.*]] = shl i32 [[TMP68]], 174984; CHECK-NEXT: [[TMP70:%.*]] = ashr i32 [[TMP69]], 174985; CHECK-NEXT: [[TMP71:%.*]] = trunc i32 [[TMP70]] to i154986; CHECK-NEXT: [[TMP72:%.*]] = insertelement <3 x i15> [[TMP48]], i15 [[TMP71]], i64 24987; CHECK-NEXT: store <3 x i15> [[TMP72]], ptr addrspace(1) [[OUT:%.*]], align 84988; CHECK-NEXT: ret void4989;4990; GFX6-LABEL: sdiv_v3i15:4991; GFX6: ; %bb.0:4992; GFX6-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x94993; GFX6-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd4994; GFX6-NEXT: s_mov_b32 s3, 0xf0004995; GFX6-NEXT: s_mov_b32 s2, -14996; GFX6-NEXT: s_waitcnt lgkmcnt(0)4997; GFX6-NEXT: s_lshr_b64 s[6:7], s[10:11], 304998; GFX6-NEXT: s_bfe_i32 s7, s4, 0xf00004999; GFX6-NEXT: v_cvt_f32_i32_e32 v0, s75000; GFX6-NEXT: s_mov_b32 s0, s85001; GFX6-NEXT: s_mov_b32 s1, s95002; GFX6-NEXT: s_lshr_b64 s[8:9], s[4:5], 305003; GFX6-NEXT: s_bfe_i32 s5, s10, 0xf00005004; GFX6-NEXT: v_cvt_f32_i32_e32 v1, s55005; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v05006; GFX6-NEXT: s_xor_b32 s5, s5, s75007; GFX6-NEXT: s_ashr_i32 s5, s5, 305008; GFX6-NEXT: s_or_b32 s5, s5, 15009; GFX6-NEXT: v_mul_f32_e32 v2, v1, v25010; GFX6-NEXT: v_trunc_f32_e32 v2, v25011; GFX6-NEXT: v_mad_f32 v1, -v2, v0, v15012; GFX6-NEXT: v_cmp_ge_f32_e64 s[12:13], |v1|, |v0|5013; GFX6-NEXT: s_and_b64 s[12:13], s[12:13], exec5014; GFX6-NEXT: v_cvt_i32_f32_e32 v2, v25015; GFX6-NEXT: s_cselect_b32 s5, s5, 05016; GFX6-NEXT: s_bfe_i32 s4, s4, 0xf000f5017; GFX6-NEXT: v_cvt_f32_i32_e32 v0, s45018; GFX6-NEXT: v_add_i32_e32 v2, vcc, s5, v25019; GFX6-NEXT: s_bfe_i32 s5, s10, 0xf000f5020; GFX6-NEXT: v_cvt_f32_i32_e32 v1, s55021; GFX6-NEXT: v_rcp_iflag_f32_e32 v3, v05022; GFX6-NEXT: s_xor_b32 s4, s5, s45023; GFX6-NEXT: s_ashr_i32 s4, s4, 305024; GFX6-NEXT: s_or_b32 s7, s4, 15025; GFX6-NEXT: v_mul_f32_e32 v3, v1, v35026; GFX6-NEXT: v_trunc_f32_e32 v3, v35027; GFX6-NEXT: v_mad_f32 v1, -v3, v0, v15028; GFX6-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0|5029; GFX6-NEXT: s_and_b64 s[4:5], s[4:5], exec5030; GFX6-NEXT: v_cvt_i32_f32_e32 v3, v35031; GFX6-NEXT: s_cselect_b32 s4, s7, 05032; GFX6-NEXT: s_bfe_i32 s5, s8, 0xf00005033; GFX6-NEXT: v_cvt_f32_i32_e32 v0, s55034; GFX6-NEXT: v_add_i32_e32 v3, vcc, s4, v35035; GFX6-NEXT: s_bfe_i32 s4, s6, 0xf00005036; GFX6-NEXT: v_cvt_f32_i32_e32 v1, s45037; GFX6-NEXT: v_rcp_iflag_f32_e32 v4, v05038; GFX6-NEXT: s_xor_b32 s4, s4, s55039; GFX6-NEXT: s_ashr_i32 s4, s4, 305040; GFX6-NEXT: s_or_b32 s6, s4, 15041; GFX6-NEXT: v_mul_f32_e32 v4, v1, v45042; GFX6-NEXT: v_trunc_f32_e32 v4, v45043; GFX6-NEXT: v_mad_f32 v1, -v4, v0, v15044; GFX6-NEXT: v_cvt_i32_f32_e32 v4, v45045; GFX6-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0|5046; GFX6-NEXT: s_and_b64 s[4:5], s[4:5], exec5047; GFX6-NEXT: s_cselect_b32 s4, s6, 05048; GFX6-NEXT: v_add_i32_e32 v0, vcc, s4, v45049; GFX6-NEXT: v_and_b32_e32 v3, 0x7fff, v35050; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 305051; GFX6-NEXT: v_and_b32_e32 v2, 0x7fff, v25052; GFX6-NEXT: v_lshlrev_b32_e32 v3, 15, v35053; GFX6-NEXT: v_or_b32_e32 v2, v3, v25054; GFX6-NEXT: v_or_b32_e32 v0, v2, v05055; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 05056; GFX6-NEXT: s_waitcnt expcnt(0)5057; GFX6-NEXT: v_and_b32_e32 v0, 0x1fff, v15058; GFX6-NEXT: buffer_store_short v0, off, s[0:3], 0 offset:45059; GFX6-NEXT: s_endpgm5060;5061; GFX9-LABEL: sdiv_v3i15:5062; GFX9: ; %bb.0:5063; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x245064; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x345065; GFX9-NEXT: v_mov_b32_e32 v2, 05066; GFX9-NEXT: s_waitcnt lgkmcnt(0)5067; GFX9-NEXT: s_lshr_b64 s[4:5], s[2:3], 305068; GFX9-NEXT: s_bfe_i32 s3, s6, 0xf00005069; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s35070; GFX9-NEXT: s_bfe_i32 s5, s2, 0xf00005071; GFX9-NEXT: v_cvt_f32_i32_e32 v1, s55072; GFX9-NEXT: s_xor_b32 s3, s5, s35073; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v05074; GFX9-NEXT: s_ashr_i32 s3, s3, 305075; GFX9-NEXT: s_lshr_b64 s[8:9], s[6:7], 305076; GFX9-NEXT: s_or_b32 s3, s3, 15077; GFX9-NEXT: v_mul_f32_e32 v3, v1, v35078; GFX9-NEXT: v_trunc_f32_e32 v3, v35079; GFX9-NEXT: v_mad_f32 v1, -v3, v0, v15080; GFX9-NEXT: v_cmp_ge_f32_e64 s[10:11], |v1|, |v0|5081; GFX9-NEXT: s_and_b64 s[10:11], s[10:11], exec5082; GFX9-NEXT: s_cselect_b32 s3, s3, 05083; GFX9-NEXT: s_bfe_i32 s5, s6, 0xf000f5084; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s55085; GFX9-NEXT: s_bfe_i32 s2, s2, 0xf000f5086; GFX9-NEXT: v_cvt_f32_i32_e32 v1, s25087; GFX9-NEXT: v_cvt_i32_f32_e32 v3, v35088; GFX9-NEXT: v_rcp_iflag_f32_e32 v4, v05089; GFX9-NEXT: s_xor_b32 s2, s2, s55090; GFX9-NEXT: s_ashr_i32 s2, s2, 305091; GFX9-NEXT: v_add_u32_e32 v3, s3, v35092; GFX9-NEXT: v_mul_f32_e32 v4, v1, v45093; GFX9-NEXT: v_trunc_f32_e32 v4, v45094; GFX9-NEXT: v_mad_f32 v1, -v4, v0, v15095; GFX9-NEXT: s_or_b32 s5, s2, 15096; GFX9-NEXT: v_cmp_ge_f32_e64 s[2:3], |v1|, |v0|5097; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec5098; GFX9-NEXT: v_cvt_i32_f32_e32 v4, v45099; GFX9-NEXT: s_cselect_b32 s2, s5, 05100; GFX9-NEXT: s_bfe_i32 s3, s8, 0xf00005101; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s35102; GFX9-NEXT: v_add_u32_e32 v4, s2, v45103; GFX9-NEXT: s_bfe_i32 s2, s4, 0xf00005104; GFX9-NEXT: v_cvt_f32_i32_e32 v1, s25105; GFX9-NEXT: v_rcp_iflag_f32_e32 v5, v05106; GFX9-NEXT: s_xor_b32 s2, s2, s35107; GFX9-NEXT: s_ashr_i32 s2, s2, 305108; GFX9-NEXT: s_or_b32 s4, s2, 15109; GFX9-NEXT: v_mul_f32_e32 v5, v1, v55110; GFX9-NEXT: v_trunc_f32_e32 v5, v55111; GFX9-NEXT: v_mad_f32 v1, -v5, v0, v15112; GFX9-NEXT: v_cvt_i32_f32_e32 v5, v55113; GFX9-NEXT: v_cmp_ge_f32_e64 s[2:3], |v1|, |v0|5114; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec5115; GFX9-NEXT: s_cselect_b32 s2, s4, 05116; GFX9-NEXT: v_add_u32_e32 v0, s2, v55117; GFX9-NEXT: v_and_b32_e32 v4, 0x7fff, v45118; GFX9-NEXT: v_lshlrev_b64 v[0:1], 30, v[0:1]5119; GFX9-NEXT: v_and_b32_e32 v3, 0x7fff, v35120; GFX9-NEXT: v_lshlrev_b32_e32 v4, 15, v45121; GFX9-NEXT: v_or_b32_e32 v3, v3, v45122; GFX9-NEXT: v_or_b32_e32 v0, v3, v05123; GFX9-NEXT: global_store_dword v2, v0, s[0:1]5124; GFX9-NEXT: v_and_b32_e32 v0, 0x1fff, v15125; GFX9-NEXT: global_store_short v2, v0, s[0:1] offset:45126; GFX9-NEXT: s_endpgm5127 %r = sdiv <3 x i15> %x, %y5128 store <3 x i15> %r, ptr addrspace(1) %out5129 ret void5130}5131 5132define amdgpu_kernel void @srem_v3i15(ptr addrspace(1) %out, <3 x i15> %x, <3 x i15> %y) {5133; CHECK-LABEL: @srem_v3i15(5134; CHECK-NEXT: [[TMP1:%.*]] = extractelement <3 x i15> [[X:%.*]], i64 05135; CHECK-NEXT: [[TMP2:%.*]] = extractelement <3 x i15> [[Y:%.*]], i64 05136; CHECK-NEXT: [[TMP3:%.*]] = sext i15 [[TMP1]] to i325137; CHECK-NEXT: [[TMP4:%.*]] = sext i15 [[TMP2]] to i325138; CHECK-NEXT: [[TMP5:%.*]] = xor i32 [[TMP3]], [[TMP4]]5139; CHECK-NEXT: [[TMP6:%.*]] = ashr i32 [[TMP5]], 305140; CHECK-NEXT: [[TMP7:%.*]] = or i32 [[TMP6]], 15141; CHECK-NEXT: [[TMP8:%.*]] = sitofp i32 [[TMP3]] to float5142; CHECK-NEXT: [[TMP9:%.*]] = sitofp i32 [[TMP4]] to float5143; CHECK-NEXT: [[TMP10:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP9]])5144; CHECK-NEXT: [[TMP11:%.*]] = fmul fast float [[TMP8]], [[TMP10]]5145; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.trunc.f32(float [[TMP11]])5146; CHECK-NEXT: [[TMP13:%.*]] = fneg fast float [[TMP12]]5147; CHECK-NEXT: [[TMP14:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP13]], float [[TMP9]], float [[TMP8]])5148; CHECK-NEXT: [[TMP15:%.*]] = fptosi float [[TMP12]] to i325149; CHECK-NEXT: [[TMP16:%.*]] = call fast float @llvm.fabs.f32(float [[TMP14]])5150; CHECK-NEXT: [[TMP17:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])5151; CHECK-NEXT: [[TMP18:%.*]] = fcmp fast oge float [[TMP16]], [[TMP17]]5152; CHECK-NEXT: [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP7]], i32 05153; CHECK-NEXT: [[TMP20:%.*]] = add i32 [[TMP15]], [[TMP19]]5154; CHECK-NEXT: [[TMP21:%.*]] = mul i32 [[TMP20]], [[TMP4]]5155; CHECK-NEXT: [[TMP22:%.*]] = sub i32 [[TMP3]], [[TMP21]]5156; CHECK-NEXT: [[TMP23:%.*]] = shl i32 [[TMP22]], 175157; CHECK-NEXT: [[TMP24:%.*]] = ashr i32 [[TMP23]], 175158; CHECK-NEXT: [[TMP25:%.*]] = trunc i32 [[TMP24]] to i155159; CHECK-NEXT: [[TMP26:%.*]] = insertelement <3 x i15> poison, i15 [[TMP25]], i64 05160; CHECK-NEXT: [[TMP27:%.*]] = extractelement <3 x i15> [[X]], i64 15161; CHECK-NEXT: [[TMP28:%.*]] = extractelement <3 x i15> [[Y]], i64 15162; CHECK-NEXT: [[TMP29:%.*]] = sext i15 [[TMP27]] to i325163; CHECK-NEXT: [[TMP30:%.*]] = sext i15 [[TMP28]] to i325164; CHECK-NEXT: [[TMP31:%.*]] = xor i32 [[TMP29]], [[TMP30]]5165; CHECK-NEXT: [[TMP32:%.*]] = ashr i32 [[TMP31]], 305166; CHECK-NEXT: [[TMP33:%.*]] = or i32 [[TMP32]], 15167; CHECK-NEXT: [[TMP34:%.*]] = sitofp i32 [[TMP29]] to float5168; CHECK-NEXT: [[TMP35:%.*]] = sitofp i32 [[TMP30]] to float5169; CHECK-NEXT: [[TMP36:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP35]])5170; CHECK-NEXT: [[TMP37:%.*]] = fmul fast float [[TMP34]], [[TMP36]]5171; CHECK-NEXT: [[TMP38:%.*]] = call fast float @llvm.trunc.f32(float [[TMP37]])5172; CHECK-NEXT: [[TMP39:%.*]] = fneg fast float [[TMP38]]5173; CHECK-NEXT: [[TMP40:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP39]], float [[TMP35]], float [[TMP34]])5174; CHECK-NEXT: [[TMP41:%.*]] = fptosi float [[TMP38]] to i325175; CHECK-NEXT: [[TMP42:%.*]] = call fast float @llvm.fabs.f32(float [[TMP40]])5176; CHECK-NEXT: [[TMP43:%.*]] = call fast float @llvm.fabs.f32(float [[TMP35]])5177; CHECK-NEXT: [[TMP44:%.*]] = fcmp fast oge float [[TMP42]], [[TMP43]]5178; CHECK-NEXT: [[TMP45:%.*]] = select i1 [[TMP44]], i32 [[TMP33]], i32 05179; CHECK-NEXT: [[TMP46:%.*]] = add i32 [[TMP41]], [[TMP45]]5180; CHECK-NEXT: [[TMP47:%.*]] = mul i32 [[TMP46]], [[TMP30]]5181; CHECK-NEXT: [[TMP48:%.*]] = sub i32 [[TMP29]], [[TMP47]]5182; CHECK-NEXT: [[TMP49:%.*]] = shl i32 [[TMP48]], 175183; CHECK-NEXT: [[TMP50:%.*]] = ashr i32 [[TMP49]], 175184; CHECK-NEXT: [[TMP51:%.*]] = trunc i32 [[TMP50]] to i155185; CHECK-NEXT: [[TMP52:%.*]] = insertelement <3 x i15> [[TMP26]], i15 [[TMP51]], i64 15186; CHECK-NEXT: [[TMP53:%.*]] = extractelement <3 x i15> [[X]], i64 25187; CHECK-NEXT: [[TMP54:%.*]] = extractelement <3 x i15> [[Y]], i64 25188; CHECK-NEXT: [[TMP55:%.*]] = sext i15 [[TMP53]] to i325189; CHECK-NEXT: [[TMP56:%.*]] = sext i15 [[TMP54]] to i325190; CHECK-NEXT: [[TMP57:%.*]] = xor i32 [[TMP55]], [[TMP56]]5191; CHECK-NEXT: [[TMP58:%.*]] = ashr i32 [[TMP57]], 305192; CHECK-NEXT: [[TMP59:%.*]] = or i32 [[TMP58]], 15193; CHECK-NEXT: [[TMP60:%.*]] = sitofp i32 [[TMP55]] to float5194; CHECK-NEXT: [[TMP61:%.*]] = sitofp i32 [[TMP56]] to float5195; CHECK-NEXT: [[TMP62:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP61]])5196; CHECK-NEXT: [[TMP63:%.*]] = fmul fast float [[TMP60]], [[TMP62]]5197; CHECK-NEXT: [[TMP64:%.*]] = call fast float @llvm.trunc.f32(float [[TMP63]])5198; CHECK-NEXT: [[TMP65:%.*]] = fneg fast float [[TMP64]]5199; CHECK-NEXT: [[TMP66:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP65]], float [[TMP61]], float [[TMP60]])5200; CHECK-NEXT: [[TMP67:%.*]] = fptosi float [[TMP64]] to i325201; CHECK-NEXT: [[TMP68:%.*]] = call fast float @llvm.fabs.f32(float [[TMP66]])5202; CHECK-NEXT: [[TMP69:%.*]] = call fast float @llvm.fabs.f32(float [[TMP61]])5203; CHECK-NEXT: [[TMP70:%.*]] = fcmp fast oge float [[TMP68]], [[TMP69]]5204; CHECK-NEXT: [[TMP71:%.*]] = select i1 [[TMP70]], i32 [[TMP59]], i32 05205; CHECK-NEXT: [[TMP72:%.*]] = add i32 [[TMP67]], [[TMP71]]5206; CHECK-NEXT: [[TMP73:%.*]] = mul i32 [[TMP72]], [[TMP56]]5207; CHECK-NEXT: [[TMP74:%.*]] = sub i32 [[TMP55]], [[TMP73]]5208; CHECK-NEXT: [[TMP75:%.*]] = shl i32 [[TMP74]], 175209; CHECK-NEXT: [[TMP76:%.*]] = ashr i32 [[TMP75]], 175210; CHECK-NEXT: [[TMP77:%.*]] = trunc i32 [[TMP76]] to i155211; CHECK-NEXT: [[TMP78:%.*]] = insertelement <3 x i15> [[TMP52]], i15 [[TMP77]], i64 25212; CHECK-NEXT: store <3 x i15> [[TMP78]], ptr addrspace(1) [[OUT:%.*]], align 85213; CHECK-NEXT: ret void5214;5215; GFX6-LABEL: srem_v3i15:5216; GFX6: ; %bb.0:5217; GFX6-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x95218; GFX6-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd5219; GFX6-NEXT: s_mov_b32 s3, 0xf0005220; GFX6-NEXT: s_mov_b32 s2, -15221; GFX6-NEXT: s_waitcnt lgkmcnt(0)5222; GFX6-NEXT: s_mov_b32 s0, s85223; GFX6-NEXT: s_mov_b32 s1, s95224; GFX6-NEXT: s_lshr_b64 s[8:9], s[4:5], 305225; GFX6-NEXT: s_bfe_i32 s5, s4, 0xf00005226; GFX6-NEXT: v_cvt_f32_i32_e32 v0, s55227; GFX6-NEXT: s_bfe_i32 s12, s10, 0xf00005228; GFX6-NEXT: v_cvt_f32_i32_e32 v1, s125229; GFX6-NEXT: s_xor_b32 s5, s12, s55230; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v05231; GFX6-NEXT: s_lshr_b64 s[6:7], s[10:11], 305232; GFX6-NEXT: s_ashr_i32 s5, s5, 305233; GFX6-NEXT: s_and_b32 s7, s6, 0x7fff5234; GFX6-NEXT: v_mul_f32_e32 v2, v1, v25235; GFX6-NEXT: v_trunc_f32_e32 v2, v25236; GFX6-NEXT: v_mad_f32 v1, -v2, v0, v15237; GFX6-NEXT: v_cvt_i32_f32_e32 v2, v25238; GFX6-NEXT: s_lshr_b32 s11, s10, 155239; GFX6-NEXT: s_and_b32 s9, s8, 0x7fff5240; GFX6-NEXT: s_lshr_b32 s14, s4, 155241; GFX6-NEXT: s_or_b32 s5, s5, 15242; GFX6-NEXT: v_cmp_ge_f32_e64 s[12:13], |v1|, |v0|5243; GFX6-NEXT: s_and_b64 s[12:13], s[12:13], exec5244; GFX6-NEXT: s_cselect_b32 s5, s5, 05245; GFX6-NEXT: v_add_i32_e32 v0, vcc, s5, v25246; GFX6-NEXT: v_mul_lo_u32 v0, v0, s45247; GFX6-NEXT: s_bfe_i32 s4, s4, 0xf000f5248; GFX6-NEXT: v_cvt_f32_i32_e32 v1, s45249; GFX6-NEXT: s_bfe_i32 s5, s10, 0xf000f5250; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s10, v05251; GFX6-NEXT: v_cvt_f32_i32_e32 v0, s55252; GFX6-NEXT: v_rcp_iflag_f32_e32 v3, v15253; GFX6-NEXT: s_xor_b32 s4, s5, s45254; GFX6-NEXT: s_ashr_i32 s4, s4, 305255; GFX6-NEXT: s_or_b32 s10, s4, 15256; GFX6-NEXT: v_mul_f32_e32 v3, v0, v35257; GFX6-NEXT: v_trunc_f32_e32 v3, v35258; GFX6-NEXT: v_mad_f32 v0, -v3, v1, v05259; GFX6-NEXT: v_cvt_i32_f32_e32 v3, v35260; GFX6-NEXT: v_cmp_ge_f32_e64 s[4:5], |v0|, |v1|5261; GFX6-NEXT: s_and_b64 s[4:5], s[4:5], exec5262; GFX6-NEXT: s_cselect_b32 s4, s10, 05263; GFX6-NEXT: v_add_i32_e32 v0, vcc, s4, v35264; GFX6-NEXT: s_bfe_i32 s4, s8, 0xf00005265; GFX6-NEXT: v_cvt_f32_i32_e32 v1, s45266; GFX6-NEXT: s_bfe_i32 s5, s6, 0xf00005267; GFX6-NEXT: v_cvt_f32_i32_e32 v3, s55268; GFX6-NEXT: s_xor_b32 s4, s5, s45269; GFX6-NEXT: v_rcp_iflag_f32_e32 v4, v15270; GFX6-NEXT: s_ashr_i32 s4, s4, 305271; GFX6-NEXT: s_or_b32 s6, s4, 15272; GFX6-NEXT: v_mul_lo_u32 v0, v0, s145273; GFX6-NEXT: v_mul_f32_e32 v4, v3, v45274; GFX6-NEXT: v_trunc_f32_e32 v4, v45275; GFX6-NEXT: v_mad_f32 v3, -v4, v1, v35276; GFX6-NEXT: v_cvt_i32_f32_e32 v4, v45277; GFX6-NEXT: v_cmp_ge_f32_e64 s[4:5], |v3|, |v1|5278; GFX6-NEXT: s_and_b64 s[4:5], s[4:5], exec5279; GFX6-NEXT: s_cselect_b32 s4, s6, 05280; GFX6-NEXT: v_add_i32_e32 v1, vcc, s4, v45281; GFX6-NEXT: v_mul_lo_u32 v1, v1, s95282; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s11, v05283; GFX6-NEXT: v_and_b32_e32 v3, 0x7fff, v35284; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s7, v15285; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 305286; GFX6-NEXT: v_and_b32_e32 v2, 0x7fff, v25287; GFX6-NEXT: v_lshlrev_b32_e32 v3, 15, v35288; GFX6-NEXT: v_or_b32_e32 v2, v3, v25289; GFX6-NEXT: v_or_b32_e32 v0, v2, v05290; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 05291; GFX6-NEXT: s_waitcnt expcnt(0)5292; GFX6-NEXT: v_and_b32_e32 v0, 0x1fff, v15293; GFX6-NEXT: buffer_store_short v0, off, s[0:3], 0 offset:45294; GFX6-NEXT: s_endpgm5295;5296; GFX9-LABEL: srem_v3i15:5297; GFX9: ; %bb.0:5298; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x245299; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x345300; GFX9-NEXT: s_waitcnt lgkmcnt(0)5301; GFX9-NEXT: s_lshr_b64 s[4:5], s[2:3], 305302; GFX9-NEXT: s_bfe_i32 s5, s6, 0xf00005303; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s55304; GFX9-NEXT: s_lshr_b64 s[8:9], s[6:7], 305305; GFX9-NEXT: s_bfe_i32 s7, s2, 0xf00005306; GFX9-NEXT: v_cvt_f32_i32_e32 v1, s75307; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v05308; GFX9-NEXT: s_xor_b32 s5, s7, s55309; GFX9-NEXT: s_ashr_i32 s5, s5, 305310; GFX9-NEXT: s_lshr_b32 s3, s2, 155311; GFX9-NEXT: v_mul_f32_e32 v2, v1, v25312; GFX9-NEXT: v_trunc_f32_e32 v2, v25313; GFX9-NEXT: v_mad_f32 v1, -v2, v0, v15314; GFX9-NEXT: v_cvt_i32_f32_e32 v2, v25315; GFX9-NEXT: s_and_b32 s9, s4, 0x7fff5316; GFX9-NEXT: s_and_b32 s12, s8, 0x7fff5317; GFX9-NEXT: s_lshr_b32 s13, s6, 155318; GFX9-NEXT: s_or_b32 s5, s5, 15319; GFX9-NEXT: v_cmp_ge_f32_e64 s[10:11], |v1|, |v0|5320; GFX9-NEXT: s_and_b64 s[10:11], s[10:11], exec5321; GFX9-NEXT: s_cselect_b32 s5, s5, 05322; GFX9-NEXT: v_add_u32_e32 v0, s5, v25323; GFX9-NEXT: s_bfe_i32 s5, s6, 0xf000f5324; GFX9-NEXT: v_cvt_f32_i32_e32 v1, s55325; GFX9-NEXT: v_mul_lo_u32 v0, v0, s65326; GFX9-NEXT: s_bfe_i32 s6, s2, 0xf000f5327; GFX9-NEXT: v_cvt_f32_i32_e32 v2, s65328; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v15329; GFX9-NEXT: s_xor_b32 s5, s6, s55330; GFX9-NEXT: s_ashr_i32 s5, s5, 305331; GFX9-NEXT: s_or_b32 s5, s5, 15332; GFX9-NEXT: v_mul_f32_e32 v3, v2, v35333; GFX9-NEXT: v_trunc_f32_e32 v3, v35334; GFX9-NEXT: v_mad_f32 v2, -v3, v1, v25335; GFX9-NEXT: v_cvt_i32_f32_e32 v3, v35336; GFX9-NEXT: v_cmp_ge_f32_e64 s[6:7], |v2|, |v1|5337; GFX9-NEXT: s_and_b64 s[6:7], s[6:7], exec5338; GFX9-NEXT: s_cselect_b32 s5, s5, 05339; GFX9-NEXT: v_add_u32_e32 v1, s5, v35340; GFX9-NEXT: s_bfe_i32 s5, s8, 0xf00005341; GFX9-NEXT: v_cvt_f32_i32_e32 v2, s55342; GFX9-NEXT: s_bfe_i32 s4, s4, 0xf00005343; GFX9-NEXT: v_cvt_f32_i32_e32 v3, s45344; GFX9-NEXT: s_xor_b32 s4, s4, s55345; GFX9-NEXT: v_rcp_iflag_f32_e32 v4, v25346; GFX9-NEXT: s_ashr_i32 s4, s4, 305347; GFX9-NEXT: s_or_b32 s6, s4, 15348; GFX9-NEXT: v_mul_lo_u32 v1, v1, s135349; GFX9-NEXT: v_mul_f32_e32 v4, v3, v45350; GFX9-NEXT: v_trunc_f32_e32 v4, v45351; GFX9-NEXT: v_mad_f32 v3, -v4, v2, v35352; GFX9-NEXT: v_cvt_i32_f32_e32 v4, v45353; GFX9-NEXT: v_cmp_ge_f32_e64 s[4:5], |v3|, |v2|5354; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec5355; GFX9-NEXT: s_cselect_b32 s4, s6, 05356; GFX9-NEXT: v_add_u32_e32 v2, s4, v45357; GFX9-NEXT: v_mul_lo_u32 v2, v2, s125358; GFX9-NEXT: v_sub_u32_e32 v4, s2, v05359; GFX9-NEXT: v_sub_u32_e32 v5, s3, v15360; GFX9-NEXT: v_mov_b32_e32 v3, 05361; GFX9-NEXT: v_sub_u32_e32 v0, s9, v25362; GFX9-NEXT: v_and_b32_e32 v2, 0x7fff, v45363; GFX9-NEXT: v_and_b32_e32 v4, 0x7fff, v55364; GFX9-NEXT: v_lshlrev_b64 v[0:1], 30, v[0:1]5365; GFX9-NEXT: v_lshlrev_b32_e32 v4, 15, v45366; GFX9-NEXT: v_or_b32_e32 v2, v2, v45367; GFX9-NEXT: v_or_b32_e32 v0, v2, v05368; GFX9-NEXT: global_store_dword v3, v0, s[0:1]5369; GFX9-NEXT: v_and_b32_e32 v0, 0x1fff, v15370; GFX9-NEXT: global_store_short v3, v0, s[0:1] offset:45371; GFX9-NEXT: s_endpgm5372 %r = srem <3 x i15> %x, %y5373 store <3 x i15> %r, ptr addrspace(1) %out5374 ret void5375}5376 5377define amdgpu_kernel void @udiv_i32_oddk_denom(ptr addrspace(1) %out, i32 %x) {5378; CHECK-LABEL: @udiv_i32_oddk_denom(5379; CHECK-NEXT: [[R:%.*]] = udiv i32 [[X:%.*]], 12351955380; CHECK-NEXT: store i32 [[R]], ptr addrspace(1) [[OUT:%.*]], align 45381; CHECK-NEXT: ret void5382;5383; GFX6-LABEL: udiv_i32_oddk_denom:5384; GFX6: ; %bb.0:5385; GFX6-NEXT: s_load_dword s6, s[4:5], 0xb5386; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x95387; GFX6-NEXT: v_mov_b32_e32 v0, 0xb2a508815388; GFX6-NEXT: s_mov_b32 s3, 0xf0005389; GFX6-NEXT: s_mov_b32 s2, -15390; GFX6-NEXT: s_waitcnt lgkmcnt(0)5391; GFX6-NEXT: v_mul_hi_u32 v0, s6, v05392; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s6, v05393; GFX6-NEXT: v_lshrrev_b32_e32 v1, 1, v15394; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v05395; GFX6-NEXT: v_lshrrev_b32_e32 v0, 20, v05396; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 05397; GFX6-NEXT: s_endpgm5398;5399; GFX9-LABEL: udiv_i32_oddk_denom:5400; GFX9: ; %bb.0:5401; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c5402; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x245403; GFX9-NEXT: v_mov_b32_e32 v0, 05404; GFX9-NEXT: s_waitcnt lgkmcnt(0)5405; GFX9-NEXT: s_mul_hi_u32 s3, s2, 0xb2a508815406; GFX9-NEXT: s_sub_i32 s2, s2, s35407; GFX9-NEXT: s_lshr_b32 s2, s2, 15408; GFX9-NEXT: s_add_i32 s2, s2, s35409; GFX9-NEXT: s_lshr_b32 s2, s2, 205410; GFX9-NEXT: v_mov_b32_e32 v1, s25411; GFX9-NEXT: global_store_dword v0, v1, s[0:1]5412; GFX9-NEXT: s_endpgm5413 %r = udiv i32 %x, 12351955414 store i32 %r, ptr addrspace(1) %out5415 ret void5416}5417 5418define amdgpu_kernel void @udiv_i32_pow2k_denom(ptr addrspace(1) %out, i32 %x) {5419; CHECK-LABEL: @udiv_i32_pow2k_denom(5420; CHECK-NEXT: [[R:%.*]] = udiv i32 [[X:%.*]], 40965421; CHECK-NEXT: store i32 [[R]], ptr addrspace(1) [[OUT:%.*]], align 45422; CHECK-NEXT: ret void5423;5424; GFX6-LABEL: udiv_i32_pow2k_denom:5425; GFX6: ; %bb.0:5426; GFX6-NEXT: s_load_dword s6, s[4:5], 0xb5427; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x95428; GFX6-NEXT: s_mov_b32 s3, 0xf0005429; GFX6-NEXT: s_mov_b32 s2, -15430; GFX6-NEXT: s_waitcnt lgkmcnt(0)5431; GFX6-NEXT: s_lshr_b32 s4, s6, 125432; GFX6-NEXT: v_mov_b32_e32 v0, s45433; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 05434; GFX6-NEXT: s_endpgm5435;5436; GFX9-LABEL: udiv_i32_pow2k_denom:5437; GFX9: ; %bb.0:5438; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c5439; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x245440; GFX9-NEXT: v_mov_b32_e32 v0, 05441; GFX9-NEXT: s_waitcnt lgkmcnt(0)5442; GFX9-NEXT: s_lshr_b32 s2, s2, 125443; GFX9-NEXT: v_mov_b32_e32 v1, s25444; GFX9-NEXT: global_store_dword v0, v1, s[0:1]5445; GFX9-NEXT: s_endpgm5446 %r = udiv i32 %x, 40965447 store i32 %r, ptr addrspace(1) %out5448 ret void5449}5450 5451define amdgpu_kernel void @udiv_i32_pow2_shl_denom(ptr addrspace(1) %out, i32 %x, i32 %y) {5452; CHECK-LABEL: @udiv_i32_pow2_shl_denom(5453; CHECK-NEXT: [[SHL_Y:%.*]] = shl i32 4096, [[Y:%.*]]5454; CHECK-NEXT: [[R:%.*]] = udiv i32 [[X:%.*]], [[SHL_Y]]5455; CHECK-NEXT: store i32 [[R]], ptr addrspace(1) [[OUT:%.*]], align 45456; CHECK-NEXT: ret void5457;5458; GFX6-LABEL: udiv_i32_pow2_shl_denom:5459; GFX6: ; %bb.0:5460; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x95461; GFX6-NEXT: s_waitcnt lgkmcnt(0)5462; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]5463; GFX6-NEXT: s_add_i32 s5, s5, 125464; GFX6-NEXT: s_lshr_b32 s4, s4, s55465; GFX6-NEXT: s_mov_b32 s3, 0xf0005466; GFX6-NEXT: s_mov_b32 s2, -15467; GFX6-NEXT: v_mov_b32_e32 v0, s45468; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 05469; GFX6-NEXT: s_endpgm5470;5471; GFX9-LABEL: udiv_i32_pow2_shl_denom:5472; GFX9: ; %bb.0:5473; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x245474; GFX9-NEXT: v_mov_b32_e32 v0, 05475; GFX9-NEXT: s_waitcnt lgkmcnt(0)5476; GFX9-NEXT: s_add_i32 s3, s3, 125477; GFX9-NEXT: s_lshr_b32 s2, s2, s35478; GFX9-NEXT: v_mov_b32_e32 v1, s25479; GFX9-NEXT: global_store_dword v0, v1, s[0:1]5480; GFX9-NEXT: s_endpgm5481 %shl.y = shl i32 4096, %y5482 %r = udiv i32 %x, %shl.y5483 store i32 %r, ptr addrspace(1) %out5484 ret void5485}5486 5487define amdgpu_kernel void @udiv_v2i32_pow2k_denom(ptr addrspace(1) %out, <2 x i32> %x) {5488; CHECK-LABEL: @udiv_v2i32_pow2k_denom(5489; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[X:%.*]], i64 05490; CHECK-NEXT: [[TMP2:%.*]] = udiv i32 [[TMP1]], 40965491; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i32> poison, i32 [[TMP2]], i64 05492; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i32> [[X]], i64 15493; CHECK-NEXT: [[TMP5:%.*]] = udiv i32 [[TMP4]], 40965494; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[TMP5]], i64 15495; CHECK-NEXT: store <2 x i32> [[TMP6]], ptr addrspace(1) [[OUT:%.*]], align 85496; CHECK-NEXT: ret void5497;5498; GFX6-LABEL: udiv_v2i32_pow2k_denom:5499; GFX6: ; %bb.0:5500; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x95501; GFX6-NEXT: s_waitcnt lgkmcnt(0)5502; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]5503; GFX6-NEXT: s_lshr_b32 s4, s4, 125504; GFX6-NEXT: s_lshr_b32 s5, s5, 125505; GFX6-NEXT: s_mov_b32 s3, 0xf0005506; GFX6-NEXT: s_mov_b32 s2, -15507; GFX6-NEXT: v_mov_b32_e32 v0, s45508; GFX6-NEXT: v_mov_b32_e32 v1, s55509; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 05510; GFX6-NEXT: s_endpgm5511;5512; GFX9-LABEL: udiv_v2i32_pow2k_denom:5513; GFX9: ; %bb.0:5514; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x245515; GFX9-NEXT: v_mov_b32_e32 v2, 05516; GFX9-NEXT: s_waitcnt lgkmcnt(0)5517; GFX9-NEXT: s_lshr_b32 s2, s2, 125518; GFX9-NEXT: s_lshr_b32 s3, s3, 125519; GFX9-NEXT: v_mov_b32_e32 v0, s25520; GFX9-NEXT: v_mov_b32_e32 v1, s35521; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]5522; GFX9-NEXT: s_endpgm5523 %r = udiv <2 x i32> %x, <i32 4096, i32 4096>5524 store <2 x i32> %r, ptr addrspace(1) %out5525 ret void5526}5527 5528define amdgpu_kernel void @udiv_v2i32_mixed_pow2k_denom(ptr addrspace(1) %out, <2 x i32> %x) {5529; CHECK-LABEL: @udiv_v2i32_mixed_pow2k_denom(5530; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[X:%.*]], i64 05531; CHECK-NEXT: [[TMP2:%.*]] = udiv i32 [[TMP1]], 40965532; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i32> poison, i32 [[TMP2]], i64 05533; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i32> [[X]], i64 15534; CHECK-NEXT: [[TMP5:%.*]] = udiv i32 [[TMP4]], 40955535; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[TMP5]], i64 15536; CHECK-NEXT: store <2 x i32> [[TMP6]], ptr addrspace(1) [[OUT:%.*]], align 85537; CHECK-NEXT: ret void5538;5539; GFX6-LABEL: udiv_v2i32_mixed_pow2k_denom:5540; GFX6: ; %bb.0:5541; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x95542; GFX6-NEXT: v_mov_b32_e32 v0, 0x1001015543; GFX6-NEXT: s_waitcnt lgkmcnt(0)5544; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]5545; GFX6-NEXT: v_mul_hi_u32 v0, s5, v05546; GFX6-NEXT: s_lshr_b32 s4, s4, 125547; GFX6-NEXT: s_mov_b32 s3, 0xf0005548; GFX6-NEXT: s_mov_b32 s2, -15549; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s5, v05550; GFX6-NEXT: v_lshrrev_b32_e32 v1, 1, v15551; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v05552; GFX6-NEXT: v_lshrrev_b32_e32 v1, 11, v05553; GFX6-NEXT: v_mov_b32_e32 v0, s45554; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 05555; GFX6-NEXT: s_endpgm5556;5557; GFX9-LABEL: udiv_v2i32_mixed_pow2k_denom:5558; GFX9: ; %bb.0:5559; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x245560; GFX9-NEXT: v_mov_b32_e32 v2, 05561; GFX9-NEXT: s_waitcnt lgkmcnt(0)5562; GFX9-NEXT: s_mul_hi_u32 s4, s3, 0x1001015563; GFX9-NEXT: s_sub_i32 s3, s3, s45564; GFX9-NEXT: s_lshr_b32 s3, s3, 15565; GFX9-NEXT: s_add_i32 s3, s3, s45566; GFX9-NEXT: s_lshr_b32 s2, s2, 125567; GFX9-NEXT: s_lshr_b32 s3, s3, 115568; GFX9-NEXT: v_mov_b32_e32 v0, s25569; GFX9-NEXT: v_mov_b32_e32 v1, s35570; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]5571; GFX9-NEXT: s_endpgm5572 %r = udiv <2 x i32> %x, <i32 4096, i32 4095>5573 store <2 x i32> %r, ptr addrspace(1) %out5574 ret void5575}5576 5577define amdgpu_kernel void @udiv_v2i32_pow2_shl_denom(ptr addrspace(1) %out, <2 x i32> %x, <2 x i32> %y) {5578; CHECK-LABEL: @udiv_v2i32_pow2_shl_denom(5579; CHECK-NEXT: [[SHL_Y:%.*]] = shl <2 x i32> splat (i32 4096), [[Y:%.*]]5580; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[X:%.*]], i64 05581; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i32> [[SHL_Y]], i64 05582; CHECK-NEXT: [[TMP3:%.*]] = uitofp i32 [[TMP2]] to float5583; CHECK-NEXT: [[TMP4:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP3]])5584; CHECK-NEXT: [[TMP5:%.*]] = fmul fast float [[TMP4]], 0x41EFFFFFC00000005585; CHECK-NEXT: [[TMP6:%.*]] = fptoui float [[TMP5]] to i325586; CHECK-NEXT: [[TMP7:%.*]] = sub i32 0, [[TMP2]]5587; CHECK-NEXT: [[TMP8:%.*]] = mul i32 [[TMP7]], [[TMP6]]5588; CHECK-NEXT: [[TMP9:%.*]] = zext i32 [[TMP6]] to i645589; CHECK-NEXT: [[TMP10:%.*]] = zext i32 [[TMP8]] to i645590; CHECK-NEXT: [[TMP11:%.*]] = mul i64 [[TMP9]], [[TMP10]]5591; CHECK-NEXT: [[TMP12:%.*]] = trunc i64 [[TMP11]] to i325592; CHECK-NEXT: [[TMP13:%.*]] = lshr i64 [[TMP11]], 325593; CHECK-NEXT: [[TMP14:%.*]] = trunc i64 [[TMP13]] to i325594; CHECK-NEXT: [[TMP15:%.*]] = add i32 [[TMP6]], [[TMP14]]5595; CHECK-NEXT: [[TMP16:%.*]] = zext i32 [[TMP1]] to i645596; CHECK-NEXT: [[TMP17:%.*]] = zext i32 [[TMP15]] to i645597; CHECK-NEXT: [[TMP18:%.*]] = mul i64 [[TMP16]], [[TMP17]]5598; CHECK-NEXT: [[TMP19:%.*]] = trunc i64 [[TMP18]] to i325599; CHECK-NEXT: [[TMP20:%.*]] = lshr i64 [[TMP18]], 325600; CHECK-NEXT: [[TMP21:%.*]] = trunc i64 [[TMP20]] to i325601; CHECK-NEXT: [[TMP22:%.*]] = mul i32 [[TMP21]], [[TMP2]]5602; CHECK-NEXT: [[TMP23:%.*]] = sub i32 [[TMP1]], [[TMP22]]5603; CHECK-NEXT: [[TMP24:%.*]] = icmp uge i32 [[TMP23]], [[TMP2]]5604; CHECK-NEXT: [[TMP25:%.*]] = add i32 [[TMP21]], 15605; CHECK-NEXT: [[TMP26:%.*]] = select i1 [[TMP24]], i32 [[TMP25]], i32 [[TMP21]]5606; CHECK-NEXT: [[TMP27:%.*]] = sub i32 [[TMP23]], [[TMP2]]5607; CHECK-NEXT: [[TMP28:%.*]] = select i1 [[TMP24]], i32 [[TMP27]], i32 [[TMP23]]5608; CHECK-NEXT: [[TMP29:%.*]] = icmp uge i32 [[TMP28]], [[TMP2]]5609; CHECK-NEXT: [[TMP30:%.*]] = add i32 [[TMP26]], 15610; CHECK-NEXT: [[TMP31:%.*]] = select i1 [[TMP29]], i32 [[TMP30]], i32 [[TMP26]]5611; CHECK-NEXT: [[TMP32:%.*]] = insertelement <2 x i32> poison, i32 [[TMP31]], i64 05612; CHECK-NEXT: [[TMP33:%.*]] = extractelement <2 x i32> [[X]], i64 15613; CHECK-NEXT: [[TMP34:%.*]] = extractelement <2 x i32> [[SHL_Y]], i64 15614; CHECK-NEXT: [[TMP35:%.*]] = uitofp i32 [[TMP34]] to float5615; CHECK-NEXT: [[TMP36:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP35]])5616; CHECK-NEXT: [[TMP37:%.*]] = fmul fast float [[TMP36]], 0x41EFFFFFC00000005617; CHECK-NEXT: [[TMP38:%.*]] = fptoui float [[TMP37]] to i325618; CHECK-NEXT: [[TMP39:%.*]] = sub i32 0, [[TMP34]]5619; CHECK-NEXT: [[TMP40:%.*]] = mul i32 [[TMP39]], [[TMP38]]5620; CHECK-NEXT: [[TMP41:%.*]] = zext i32 [[TMP38]] to i645621; CHECK-NEXT: [[TMP42:%.*]] = zext i32 [[TMP40]] to i645622; CHECK-NEXT: [[TMP43:%.*]] = mul i64 [[TMP41]], [[TMP42]]5623; CHECK-NEXT: [[TMP44:%.*]] = trunc i64 [[TMP43]] to i325624; CHECK-NEXT: [[TMP45:%.*]] = lshr i64 [[TMP43]], 325625; CHECK-NEXT: [[TMP46:%.*]] = trunc i64 [[TMP45]] to i325626; CHECK-NEXT: [[TMP47:%.*]] = add i32 [[TMP38]], [[TMP46]]5627; CHECK-NEXT: [[TMP48:%.*]] = zext i32 [[TMP33]] to i645628; CHECK-NEXT: [[TMP49:%.*]] = zext i32 [[TMP47]] to i645629; CHECK-NEXT: [[TMP50:%.*]] = mul i64 [[TMP48]], [[TMP49]]5630; CHECK-NEXT: [[TMP51:%.*]] = trunc i64 [[TMP50]] to i325631; CHECK-NEXT: [[TMP52:%.*]] = lshr i64 [[TMP50]], 325632; CHECK-NEXT: [[TMP53:%.*]] = trunc i64 [[TMP52]] to i325633; CHECK-NEXT: [[TMP54:%.*]] = mul i32 [[TMP53]], [[TMP34]]5634; CHECK-NEXT: [[TMP55:%.*]] = sub i32 [[TMP33]], [[TMP54]]5635; CHECK-NEXT: [[TMP56:%.*]] = icmp uge i32 [[TMP55]], [[TMP34]]5636; CHECK-NEXT: [[TMP57:%.*]] = add i32 [[TMP53]], 15637; CHECK-NEXT: [[TMP58:%.*]] = select i1 [[TMP56]], i32 [[TMP57]], i32 [[TMP53]]5638; CHECK-NEXT: [[TMP59:%.*]] = sub i32 [[TMP55]], [[TMP34]]5639; CHECK-NEXT: [[TMP60:%.*]] = select i1 [[TMP56]], i32 [[TMP59]], i32 [[TMP55]]5640; CHECK-NEXT: [[TMP61:%.*]] = icmp uge i32 [[TMP60]], [[TMP34]]5641; CHECK-NEXT: [[TMP62:%.*]] = add i32 [[TMP58]], 15642; CHECK-NEXT: [[TMP63:%.*]] = select i1 [[TMP61]], i32 [[TMP62]], i32 [[TMP58]]5643; CHECK-NEXT: [[TMP64:%.*]] = insertelement <2 x i32> [[TMP32]], i32 [[TMP63]], i64 15644; CHECK-NEXT: store <2 x i32> [[TMP64]], ptr addrspace(1) [[OUT:%.*]], align 85645; CHECK-NEXT: ret void5646;5647; GFX6-LABEL: udiv_v2i32_pow2_shl_denom:5648; GFX6: ; %bb.0:5649; GFX6-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0xb5650; GFX6-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x95651; GFX6-NEXT: s_mov_b32 s7, 0xf0005652; GFX6-NEXT: s_mov_b32 s6, -15653; GFX6-NEXT: s_waitcnt lgkmcnt(0)5654; GFX6-NEXT: s_lshl_b32 s0, 0x1000, s105655; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s05656; GFX6-NEXT: s_sub_i32 s1, 0, s05657; GFX6-NEXT: s_lshl_b32 s2, 0x1000, s115658; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s25659; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v05660; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v25661; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v05662; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v05663; GFX6-NEXT: v_mul_lo_u32 v1, s1, v05664; GFX6-NEXT: v_mul_hi_u32 v1, v0, v15665; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v15666; GFX6-NEXT: v_mul_hi_u32 v0, s8, v05667; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v25668; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v15669; GFX6-NEXT: v_readfirstlane_b32 s1, v05670; GFX6-NEXT: s_mul_i32 s1, s1, s05671; GFX6-NEXT: s_sub_i32 s1, s8, s15672; GFX6-NEXT: s_sub_i32 s3, s1, s05673; GFX6-NEXT: s_cmp_ge_u32 s1, s05674; GFX6-NEXT: v_add_i32_e32 v2, vcc, 1, v05675; GFX6-NEXT: s_cselect_b32 s1, s3, s15676; GFX6-NEXT: s_cselect_b64 vcc, -1, 05677; GFX6-NEXT: s_cmp_ge_u32 s1, s05678; GFX6-NEXT: s_cselect_b64 s[0:1], -1, 05679; GFX6-NEXT: s_sub_i32 s3, 0, s25680; GFX6-NEXT: v_mul_lo_u32 v3, s3, v15681; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc5682; GFX6-NEXT: v_add_i32_e32 v2, vcc, 1, v05683; GFX6-NEXT: v_mul_hi_u32 v3, v1, v35684; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]5685; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v35686; GFX6-NEXT: v_mul_hi_u32 v1, s9, v15687; GFX6-NEXT: v_readfirstlane_b32 s0, v15688; GFX6-NEXT: s_mul_i32 s0, s0, s25689; GFX6-NEXT: s_sub_i32 s0, s9, s05690; GFX6-NEXT: s_sub_i32 s1, s0, s25691; GFX6-NEXT: v_add_i32_e32 v2, vcc, 1, v15692; GFX6-NEXT: s_cmp_ge_u32 s0, s25693; GFX6-NEXT: s_cselect_b64 vcc, -1, 05694; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc5695; GFX6-NEXT: s_cselect_b32 s0, s1, s05696; GFX6-NEXT: v_add_i32_e32 v2, vcc, 1, v15697; GFX6-NEXT: s_cmp_ge_u32 s0, s25698; GFX6-NEXT: s_cselect_b64 vcc, -1, 05699; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc5700; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 05701; GFX6-NEXT: s_endpgm5702;5703; GFX9-LABEL: udiv_v2i32_pow2_shl_denom:5704; GFX9: ; %bb.0:5705; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c5706; GFX9-NEXT: v_mov_b32_e32 v2, 05707; GFX9-NEXT: s_waitcnt lgkmcnt(0)5708; GFX9-NEXT: s_lshl_b32 s7, 0x1000, s25709; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s75710; GFX9-NEXT: s_lshl_b32 s6, 0x1000, s35711; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s65712; GFX9-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x245713; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v05714; GFX9-NEXT: s_sub_i32 s4, 0, s75715; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v15716; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v05717; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v05718; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v15719; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v15720; GFX9-NEXT: v_readfirstlane_b32 s5, v05721; GFX9-NEXT: s_mul_i32 s4, s4, s55722; GFX9-NEXT: s_mul_hi_u32 s4, s5, s45723; GFX9-NEXT: s_add_i32 s5, s5, s45724; GFX9-NEXT: s_mul_hi_u32 s4, s0, s55725; GFX9-NEXT: s_mul_i32 s5, s4, s75726; GFX9-NEXT: s_sub_i32 s0, s0, s55727; GFX9-NEXT: s_add_i32 s9, s4, 15728; GFX9-NEXT: s_sub_i32 s5, s0, s75729; GFX9-NEXT: s_cmp_ge_u32 s0, s75730; GFX9-NEXT: s_cselect_b32 s4, s9, s45731; GFX9-NEXT: s_cselect_b32 s0, s5, s05732; GFX9-NEXT: s_add_i32 s5, s4, 15733; GFX9-NEXT: s_cmp_ge_u32 s0, s75734; GFX9-NEXT: v_readfirstlane_b32 s8, v15735; GFX9-NEXT: s_cselect_b32 s0, s5, s45736; GFX9-NEXT: s_sub_i32 s4, 0, s65737; GFX9-NEXT: s_mul_i32 s4, s4, s85738; GFX9-NEXT: s_mul_hi_u32 s4, s8, s45739; GFX9-NEXT: s_add_i32 s8, s8, s45740; GFX9-NEXT: s_mul_hi_u32 s4, s1, s85741; GFX9-NEXT: s_mul_i32 s5, s4, s65742; GFX9-NEXT: s_sub_i32 s1, s1, s55743; GFX9-NEXT: s_add_i32 s7, s4, 15744; GFX9-NEXT: s_sub_i32 s5, s1, s65745; GFX9-NEXT: s_cmp_ge_u32 s1, s65746; GFX9-NEXT: s_cselect_b32 s4, s7, s45747; GFX9-NEXT: s_cselect_b32 s1, s5, s15748; GFX9-NEXT: s_add_i32 s5, s4, 15749; GFX9-NEXT: s_cmp_ge_u32 s1, s65750; GFX9-NEXT: s_cselect_b32 s1, s5, s45751; GFX9-NEXT: v_mov_b32_e32 v0, s05752; GFX9-NEXT: v_mov_b32_e32 v1, s15753; GFX9-NEXT: s_waitcnt lgkmcnt(0)5754; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]5755; GFX9-NEXT: s_endpgm5756 %shl.y = shl <2 x i32> <i32 4096, i32 4096>, %y5757 %r = udiv <2 x i32> %x, %shl.y5758 store <2 x i32> %r, ptr addrspace(1) %out5759 ret void5760}5761 5762define amdgpu_kernel void @urem_i32_oddk_denom(ptr addrspace(1) %out, i32 %x) {5763; CHECK-LABEL: @urem_i32_oddk_denom(5764; CHECK-NEXT: [[R:%.*]] = urem i32 [[X:%.*]], 12351955765; CHECK-NEXT: store i32 [[R]], ptr addrspace(1) [[OUT:%.*]], align 45766; CHECK-NEXT: ret void5767;5768; GFX6-LABEL: urem_i32_oddk_denom:5769; GFX6: ; %bb.0:5770; GFX6-NEXT: s_load_dword s6, s[4:5], 0xb5771; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x95772; GFX6-NEXT: v_mov_b32_e32 v0, 0xb2a508815773; GFX6-NEXT: s_mov_b32 s2, 0x12d8fb5774; GFX6-NEXT: s_mov_b32 s3, 0xf0005775; GFX6-NEXT: s_waitcnt lgkmcnt(0)5776; GFX6-NEXT: v_mul_hi_u32 v0, s6, v05777; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s6, v05778; GFX6-NEXT: v_lshrrev_b32_e32 v1, 1, v15779; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v05780; GFX6-NEXT: v_lshrrev_b32_e32 v0, 20, v05781; GFX6-NEXT: v_mul_lo_u32 v0, v0, s25782; GFX6-NEXT: s_mov_b32 s2, -15783; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s6, v05784; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 05785; GFX6-NEXT: s_endpgm5786;5787; GFX9-LABEL: urem_i32_oddk_denom:5788; GFX9: ; %bb.0:5789; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c5790; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x245791; GFX9-NEXT: v_mov_b32_e32 v0, 05792; GFX9-NEXT: s_waitcnt lgkmcnt(0)5793; GFX9-NEXT: s_mul_hi_u32 s3, s2, 0xb2a508815794; GFX9-NEXT: s_sub_i32 s4, s2, s35795; GFX9-NEXT: s_lshr_b32 s4, s4, 15796; GFX9-NEXT: s_add_i32 s4, s4, s35797; GFX9-NEXT: s_lshr_b32 s3, s4, 205798; GFX9-NEXT: s_mul_i32 s3, s3, 0x12d8fb5799; GFX9-NEXT: s_sub_i32 s2, s2, s35800; GFX9-NEXT: v_mov_b32_e32 v1, s25801; GFX9-NEXT: global_store_dword v0, v1, s[0:1]5802; GFX9-NEXT: s_endpgm5803 %r = urem i32 %x, 12351955804 store i32 %r, ptr addrspace(1) %out5805 ret void5806}5807 5808define amdgpu_kernel void @urem_i32_pow2k_denom(ptr addrspace(1) %out, i32 %x) {5809; CHECK-LABEL: @urem_i32_pow2k_denom(5810; CHECK-NEXT: [[R:%.*]] = urem i32 [[X:%.*]], 40965811; CHECK-NEXT: store i32 [[R]], ptr addrspace(1) [[OUT:%.*]], align 45812; CHECK-NEXT: ret void5813;5814; GFX6-LABEL: urem_i32_pow2k_denom:5815; GFX6: ; %bb.0:5816; GFX6-NEXT: s_load_dword s6, s[4:5], 0xb5817; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x95818; GFX6-NEXT: s_mov_b32 s3, 0xf0005819; GFX6-NEXT: s_mov_b32 s2, -15820; GFX6-NEXT: s_waitcnt lgkmcnt(0)5821; GFX6-NEXT: s_and_b32 s4, s6, 0xfff5822; GFX6-NEXT: v_mov_b32_e32 v0, s45823; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 05824; GFX6-NEXT: s_endpgm5825;5826; GFX9-LABEL: urem_i32_pow2k_denom:5827; GFX9: ; %bb.0:5828; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c5829; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x245830; GFX9-NEXT: v_mov_b32_e32 v0, 05831; GFX9-NEXT: s_waitcnt lgkmcnt(0)5832; GFX9-NEXT: s_and_b32 s2, s2, 0xfff5833; GFX9-NEXT: v_mov_b32_e32 v1, s25834; GFX9-NEXT: global_store_dword v0, v1, s[0:1]5835; GFX9-NEXT: s_endpgm5836 %r = urem i32 %x, 40965837 store i32 %r, ptr addrspace(1) %out5838 ret void5839}5840 5841define amdgpu_kernel void @urem_i32_pow2_shl_denom(ptr addrspace(1) %out, i32 %x, i32 %y) {5842; CHECK-LABEL: @urem_i32_pow2_shl_denom(5843; CHECK-NEXT: [[SHL_Y:%.*]] = shl i32 4096, [[Y:%.*]]5844; CHECK-NEXT: [[R:%.*]] = urem i32 [[X:%.*]], [[SHL_Y]]5845; CHECK-NEXT: store i32 [[R]], ptr addrspace(1) [[OUT:%.*]], align 45846; CHECK-NEXT: ret void5847;5848; GFX6-LABEL: urem_i32_pow2_shl_denom:5849; GFX6: ; %bb.0:5850; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x95851; GFX6-NEXT: s_waitcnt lgkmcnt(0)5852; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]5853; GFX6-NEXT: s_lshl_b32 s5, 0x1000, s55854; GFX6-NEXT: s_add_i32 s5, s5, -15855; GFX6-NEXT: s_and_b32 s4, s4, s55856; GFX6-NEXT: s_mov_b32 s3, 0xf0005857; GFX6-NEXT: s_mov_b32 s2, -15858; GFX6-NEXT: v_mov_b32_e32 v0, s45859; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 05860; GFX6-NEXT: s_endpgm5861;5862; GFX9-LABEL: urem_i32_pow2_shl_denom:5863; GFX9: ; %bb.0:5864; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x245865; GFX9-NEXT: v_mov_b32_e32 v0, 05866; GFX9-NEXT: s_waitcnt lgkmcnt(0)5867; GFX9-NEXT: s_lshl_b32 s3, 0x1000, s35868; GFX9-NEXT: s_add_i32 s3, s3, -15869; GFX9-NEXT: s_and_b32 s2, s2, s35870; GFX9-NEXT: v_mov_b32_e32 v1, s25871; GFX9-NEXT: global_store_dword v0, v1, s[0:1]5872; GFX9-NEXT: s_endpgm5873 %shl.y = shl i32 4096, %y5874 %r = urem i32 %x, %shl.y5875 store i32 %r, ptr addrspace(1) %out5876 ret void5877}5878 5879define amdgpu_kernel void @urem_v2i32_pow2k_denom(ptr addrspace(1) %out, <2 x i32> %x) {5880; CHECK-LABEL: @urem_v2i32_pow2k_denom(5881; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[X:%.*]], i64 05882; CHECK-NEXT: [[TMP2:%.*]] = urem i32 [[TMP1]], 40965883; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i32> poison, i32 [[TMP2]], i64 05884; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i32> [[X]], i64 15885; CHECK-NEXT: [[TMP5:%.*]] = urem i32 [[TMP4]], 40965886; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[TMP5]], i64 15887; CHECK-NEXT: store <2 x i32> [[TMP6]], ptr addrspace(1) [[OUT:%.*]], align 85888; CHECK-NEXT: ret void5889;5890; GFX6-LABEL: urem_v2i32_pow2k_denom:5891; GFX6: ; %bb.0:5892; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x95893; GFX6-NEXT: s_waitcnt lgkmcnt(0)5894; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]5895; GFX6-NEXT: s_and_b32 s4, s4, 0xfff5896; GFX6-NEXT: s_and_b32 s5, s5, 0xfff5897; GFX6-NEXT: s_mov_b32 s3, 0xf0005898; GFX6-NEXT: s_mov_b32 s2, -15899; GFX6-NEXT: v_mov_b32_e32 v0, s45900; GFX6-NEXT: v_mov_b32_e32 v1, s55901; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 05902; GFX6-NEXT: s_endpgm5903;5904; GFX9-LABEL: urem_v2i32_pow2k_denom:5905; GFX9: ; %bb.0:5906; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x245907; GFX9-NEXT: v_mov_b32_e32 v2, 05908; GFX9-NEXT: s_waitcnt lgkmcnt(0)5909; GFX9-NEXT: s_and_b32 s2, s2, 0xfff5910; GFX9-NEXT: s_and_b32 s3, s3, 0xfff5911; GFX9-NEXT: v_mov_b32_e32 v0, s25912; GFX9-NEXT: v_mov_b32_e32 v1, s35913; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]5914; GFX9-NEXT: s_endpgm5915 %r = urem <2 x i32> %x, <i32 4096, i32 4096>5916 store <2 x i32> %r, ptr addrspace(1) %out5917 ret void5918}5919 5920define amdgpu_kernel void @urem_v2i32_pow2_shl_denom(ptr addrspace(1) %out, <2 x i32> %x, <2 x i32> %y) {5921; CHECK-LABEL: @urem_v2i32_pow2_shl_denom(5922; CHECK-NEXT: [[SHL_Y:%.*]] = shl <2 x i32> splat (i32 4096), [[Y:%.*]]5923; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[X:%.*]], i64 05924; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i32> [[SHL_Y]], i64 05925; CHECK-NEXT: [[TMP3:%.*]] = uitofp i32 [[TMP2]] to float5926; CHECK-NEXT: [[TMP4:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP3]])5927; CHECK-NEXT: [[TMP5:%.*]] = fmul fast float [[TMP4]], 0x41EFFFFFC00000005928; CHECK-NEXT: [[TMP6:%.*]] = fptoui float [[TMP5]] to i325929; CHECK-NEXT: [[TMP7:%.*]] = sub i32 0, [[TMP2]]5930; CHECK-NEXT: [[TMP8:%.*]] = mul i32 [[TMP7]], [[TMP6]]5931; CHECK-NEXT: [[TMP9:%.*]] = zext i32 [[TMP6]] to i645932; CHECK-NEXT: [[TMP10:%.*]] = zext i32 [[TMP8]] to i645933; CHECK-NEXT: [[TMP11:%.*]] = mul i64 [[TMP9]], [[TMP10]]5934; CHECK-NEXT: [[TMP12:%.*]] = trunc i64 [[TMP11]] to i325935; CHECK-NEXT: [[TMP13:%.*]] = lshr i64 [[TMP11]], 325936; CHECK-NEXT: [[TMP14:%.*]] = trunc i64 [[TMP13]] to i325937; CHECK-NEXT: [[TMP15:%.*]] = add i32 [[TMP6]], [[TMP14]]5938; CHECK-NEXT: [[TMP16:%.*]] = zext i32 [[TMP1]] to i645939; CHECK-NEXT: [[TMP17:%.*]] = zext i32 [[TMP15]] to i645940; CHECK-NEXT: [[TMP18:%.*]] = mul i64 [[TMP16]], [[TMP17]]5941; CHECK-NEXT: [[TMP19:%.*]] = trunc i64 [[TMP18]] to i325942; CHECK-NEXT: [[TMP20:%.*]] = lshr i64 [[TMP18]], 325943; CHECK-NEXT: [[TMP21:%.*]] = trunc i64 [[TMP20]] to i325944; CHECK-NEXT: [[TMP22:%.*]] = mul i32 [[TMP21]], [[TMP2]]5945; CHECK-NEXT: [[TMP23:%.*]] = sub i32 [[TMP1]], [[TMP22]]5946; CHECK-NEXT: [[TMP24:%.*]] = icmp uge i32 [[TMP23]], [[TMP2]]5947; CHECK-NEXT: [[TMP25:%.*]] = sub i32 [[TMP23]], [[TMP2]]5948; CHECK-NEXT: [[TMP26:%.*]] = select i1 [[TMP24]], i32 [[TMP25]], i32 [[TMP23]]5949; CHECK-NEXT: [[TMP27:%.*]] = icmp uge i32 [[TMP26]], [[TMP2]]5950; CHECK-NEXT: [[TMP28:%.*]] = sub i32 [[TMP26]], [[TMP2]]5951; CHECK-NEXT: [[TMP29:%.*]] = select i1 [[TMP27]], i32 [[TMP28]], i32 [[TMP26]]5952; CHECK-NEXT: [[TMP30:%.*]] = insertelement <2 x i32> poison, i32 [[TMP29]], i64 05953; CHECK-NEXT: [[TMP31:%.*]] = extractelement <2 x i32> [[X]], i64 15954; CHECK-NEXT: [[TMP32:%.*]] = extractelement <2 x i32> [[SHL_Y]], i64 15955; CHECK-NEXT: [[TMP33:%.*]] = uitofp i32 [[TMP32]] to float5956; CHECK-NEXT: [[TMP34:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP33]])5957; CHECK-NEXT: [[TMP35:%.*]] = fmul fast float [[TMP34]], 0x41EFFFFFC00000005958; CHECK-NEXT: [[TMP36:%.*]] = fptoui float [[TMP35]] to i325959; CHECK-NEXT: [[TMP37:%.*]] = sub i32 0, [[TMP32]]5960; CHECK-NEXT: [[TMP38:%.*]] = mul i32 [[TMP37]], [[TMP36]]5961; CHECK-NEXT: [[TMP39:%.*]] = zext i32 [[TMP36]] to i645962; CHECK-NEXT: [[TMP40:%.*]] = zext i32 [[TMP38]] to i645963; CHECK-NEXT: [[TMP41:%.*]] = mul i64 [[TMP39]], [[TMP40]]5964; CHECK-NEXT: [[TMP42:%.*]] = trunc i64 [[TMP41]] to i325965; CHECK-NEXT: [[TMP43:%.*]] = lshr i64 [[TMP41]], 325966; CHECK-NEXT: [[TMP44:%.*]] = trunc i64 [[TMP43]] to i325967; CHECK-NEXT: [[TMP45:%.*]] = add i32 [[TMP36]], [[TMP44]]5968; CHECK-NEXT: [[TMP46:%.*]] = zext i32 [[TMP31]] to i645969; CHECK-NEXT: [[TMP47:%.*]] = zext i32 [[TMP45]] to i645970; CHECK-NEXT: [[TMP48:%.*]] = mul i64 [[TMP46]], [[TMP47]]5971; CHECK-NEXT: [[TMP49:%.*]] = trunc i64 [[TMP48]] to i325972; CHECK-NEXT: [[TMP50:%.*]] = lshr i64 [[TMP48]], 325973; CHECK-NEXT: [[TMP51:%.*]] = trunc i64 [[TMP50]] to i325974; CHECK-NEXT: [[TMP52:%.*]] = mul i32 [[TMP51]], [[TMP32]]5975; CHECK-NEXT: [[TMP53:%.*]] = sub i32 [[TMP31]], [[TMP52]]5976; CHECK-NEXT: [[TMP54:%.*]] = icmp uge i32 [[TMP53]], [[TMP32]]5977; CHECK-NEXT: [[TMP55:%.*]] = sub i32 [[TMP53]], [[TMP32]]5978; CHECK-NEXT: [[TMP56:%.*]] = select i1 [[TMP54]], i32 [[TMP55]], i32 [[TMP53]]5979; CHECK-NEXT: [[TMP57:%.*]] = icmp uge i32 [[TMP56]], [[TMP32]]5980; CHECK-NEXT: [[TMP58:%.*]] = sub i32 [[TMP56]], [[TMP32]]5981; CHECK-NEXT: [[TMP59:%.*]] = select i1 [[TMP57]], i32 [[TMP58]], i32 [[TMP56]]5982; CHECK-NEXT: [[TMP60:%.*]] = insertelement <2 x i32> [[TMP30]], i32 [[TMP59]], i64 15983; CHECK-NEXT: store <2 x i32> [[TMP60]], ptr addrspace(1) [[OUT:%.*]], align 85984; CHECK-NEXT: ret void5985;5986; GFX6-LABEL: urem_v2i32_pow2_shl_denom:5987; GFX6: ; %bb.0:5988; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb5989; GFX6-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x95990; GFX6-NEXT: s_mov_b32 s7, 0xf0005991; GFX6-NEXT: s_waitcnt lgkmcnt(0)5992; GFX6-NEXT: s_lshl_b32 s2, 0x1000, s25993; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s25994; GFX6-NEXT: s_sub_i32 s6, 0, s25995; GFX6-NEXT: s_lshl_b32 s3, 0x1000, s35996; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s35997; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v05998; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v25999; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v06000; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v06001; GFX6-NEXT: v_mul_lo_u32 v1, s6, v06002; GFX6-NEXT: v_mul_hi_u32 v1, v0, v16003; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v16004; GFX6-NEXT: v_mul_hi_u32 v0, s0, v06005; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v26006; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v16007; GFX6-NEXT: v_readfirstlane_b32 s6, v06008; GFX6-NEXT: s_mul_i32 s6, s6, s26009; GFX6-NEXT: s_sub_i32 s0, s0, s66010; GFX6-NEXT: s_sub_i32 s6, s0, s26011; GFX6-NEXT: s_cmp_ge_u32 s0, s26012; GFX6-NEXT: s_cselect_b32 s0, s6, s06013; GFX6-NEXT: s_sub_i32 s6, s0, s26014; GFX6-NEXT: s_cmp_ge_u32 s0, s26015; GFX6-NEXT: s_cselect_b32 s0, s6, s06016; GFX6-NEXT: s_sub_i32 s2, 0, s36017; GFX6-NEXT: v_mul_lo_u32 v0, s2, v16018; GFX6-NEXT: s_mov_b32 s6, -16019; GFX6-NEXT: v_mul_hi_u32 v0, v1, v06020; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v06021; GFX6-NEXT: v_mul_hi_u32 v0, s1, v06022; GFX6-NEXT: v_readfirstlane_b32 s2, v06023; GFX6-NEXT: s_mul_i32 s2, s2, s36024; GFX6-NEXT: s_sub_i32 s1, s1, s26025; GFX6-NEXT: s_sub_i32 s2, s1, s36026; GFX6-NEXT: s_cmp_ge_u32 s1, s36027; GFX6-NEXT: s_cselect_b32 s1, s2, s16028; GFX6-NEXT: s_sub_i32 s2, s1, s36029; GFX6-NEXT: s_cmp_ge_u32 s1, s36030; GFX6-NEXT: s_cselect_b32 s1, s2, s16031; GFX6-NEXT: v_mov_b32_e32 v0, s06032; GFX6-NEXT: v_mov_b32_e32 v1, s16033; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 06034; GFX6-NEXT: s_endpgm6035;6036; GFX9-LABEL: urem_v2i32_pow2_shl_denom:6037; GFX9: ; %bb.0:6038; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c6039; GFX9-NEXT: v_mov_b32_e32 v2, 06040; GFX9-NEXT: s_waitcnt lgkmcnt(0)6041; GFX9-NEXT: s_lshl_b32 s7, 0x1000, s26042; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s76043; GFX9-NEXT: s_lshl_b32 s6, 0x1000, s36044; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s66045; GFX9-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x246046; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v06047; GFX9-NEXT: s_sub_i32 s4, 0, s76048; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v16049; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v06050; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v06051; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v16052; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v16053; GFX9-NEXT: v_readfirstlane_b32 s5, v06054; GFX9-NEXT: s_mul_i32 s4, s4, s56055; GFX9-NEXT: s_mul_hi_u32 s4, s5, s46056; GFX9-NEXT: s_add_i32 s5, s5, s46057; GFX9-NEXT: s_mul_hi_u32 s4, s0, s56058; GFX9-NEXT: s_mul_i32 s4, s4, s76059; GFX9-NEXT: s_sub_i32 s0, s0, s46060; GFX9-NEXT: s_sub_i32 s4, s0, s76061; GFX9-NEXT: s_cmp_ge_u32 s0, s76062; GFX9-NEXT: s_cselect_b32 s0, s4, s06063; GFX9-NEXT: s_sub_i32 s4, s0, s76064; GFX9-NEXT: s_cmp_ge_u32 s0, s76065; GFX9-NEXT: v_readfirstlane_b32 s8, v16066; GFX9-NEXT: s_cselect_b32 s0, s4, s06067; GFX9-NEXT: s_sub_i32 s4, 0, s66068; GFX9-NEXT: s_mul_i32 s4, s4, s86069; GFX9-NEXT: s_mul_hi_u32 s4, s8, s46070; GFX9-NEXT: s_add_i32 s8, s8, s46071; GFX9-NEXT: s_mul_hi_u32 s4, s1, s86072; GFX9-NEXT: s_mul_i32 s4, s4, s66073; GFX9-NEXT: s_sub_i32 s1, s1, s46074; GFX9-NEXT: s_sub_i32 s4, s1, s66075; GFX9-NEXT: s_cmp_ge_u32 s1, s66076; GFX9-NEXT: s_cselect_b32 s1, s4, s16077; GFX9-NEXT: s_sub_i32 s4, s1, s66078; GFX9-NEXT: s_cmp_ge_u32 s1, s66079; GFX9-NEXT: s_cselect_b32 s1, s4, s16080; GFX9-NEXT: v_mov_b32_e32 v0, s06081; GFX9-NEXT: v_mov_b32_e32 v1, s16082; GFX9-NEXT: s_waitcnt lgkmcnt(0)6083; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]6084; GFX9-NEXT: s_endpgm6085 %shl.y = shl <2 x i32> <i32 4096, i32 4096>, %y6086 %r = urem <2 x i32> %x, %shl.y6087 store <2 x i32> %r, ptr addrspace(1) %out6088 ret void6089}6090 6091define amdgpu_kernel void @sdiv_i32_oddk_denom(ptr addrspace(1) %out, i32 %x) {6092; CHECK-LABEL: @sdiv_i32_oddk_denom(6093; CHECK-NEXT: [[R:%.*]] = sdiv i32 [[X:%.*]], 12351956094; CHECK-NEXT: store i32 [[R]], ptr addrspace(1) [[OUT:%.*]], align 46095; CHECK-NEXT: ret void6096;6097; GFX6-LABEL: sdiv_i32_oddk_denom:6098; GFX6: ; %bb.0:6099; GFX6-NEXT: s_load_dword s6, s[4:5], 0xb6100; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x96101; GFX6-NEXT: v_mov_b32_e32 v0, 0xd95284416102; GFX6-NEXT: s_mov_b32 s3, 0xf0006103; GFX6-NEXT: s_mov_b32 s2, -16104; GFX6-NEXT: s_waitcnt lgkmcnt(0)6105; GFX6-NEXT: v_mul_hi_i32 v0, s6, v06106; GFX6-NEXT: v_add_i32_e32 v0, vcc, s6, v06107; GFX6-NEXT: v_lshrrev_b32_e32 v1, 31, v06108; GFX6-NEXT: v_ashrrev_i32_e32 v0, 20, v06109; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v16110; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 06111; GFX6-NEXT: s_endpgm6112;6113; GFX9-LABEL: sdiv_i32_oddk_denom:6114; GFX9: ; %bb.0:6115; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c6116; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x246117; GFX9-NEXT: v_mov_b32_e32 v0, 06118; GFX9-NEXT: s_waitcnt lgkmcnt(0)6119; GFX9-NEXT: s_mul_hi_i32 s3, s2, 0xd95284416120; GFX9-NEXT: s_add_i32 s3, s3, s26121; GFX9-NEXT: s_lshr_b32 s2, s3, 316122; GFX9-NEXT: s_ashr_i32 s3, s3, 206123; GFX9-NEXT: s_add_i32 s2, s3, s26124; GFX9-NEXT: v_mov_b32_e32 v1, s26125; GFX9-NEXT: global_store_dword v0, v1, s[0:1]6126; GFX9-NEXT: s_endpgm6127 %r = sdiv i32 %x, 12351956128 store i32 %r, ptr addrspace(1) %out6129 ret void6130}6131 6132define amdgpu_kernel void @sdiv_i32_pow2k_denom(ptr addrspace(1) %out, i32 %x) {6133; CHECK-LABEL: @sdiv_i32_pow2k_denom(6134; CHECK-NEXT: [[R:%.*]] = sdiv i32 [[X:%.*]], 40966135; CHECK-NEXT: store i32 [[R]], ptr addrspace(1) [[OUT:%.*]], align 46136; CHECK-NEXT: ret void6137;6138; GFX6-LABEL: sdiv_i32_pow2k_denom:6139; GFX6: ; %bb.0:6140; GFX6-NEXT: s_load_dword s6, s[4:5], 0xb6141; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x96142; GFX6-NEXT: s_mov_b32 s3, 0xf0006143; GFX6-NEXT: s_mov_b32 s2, -16144; GFX6-NEXT: s_waitcnt lgkmcnt(0)6145; GFX6-NEXT: s_ashr_i32 s4, s6, 316146; GFX6-NEXT: s_lshr_b32 s4, s4, 206147; GFX6-NEXT: s_add_i32 s6, s6, s46148; GFX6-NEXT: s_ashr_i32 s4, s6, 126149; GFX6-NEXT: v_mov_b32_e32 v0, s46150; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 06151; GFX6-NEXT: s_endpgm6152;6153; GFX9-LABEL: sdiv_i32_pow2k_denom:6154; GFX9: ; %bb.0:6155; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c6156; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x246157; GFX9-NEXT: v_mov_b32_e32 v0, 06158; GFX9-NEXT: s_waitcnt lgkmcnt(0)6159; GFX9-NEXT: s_ashr_i32 s3, s2, 316160; GFX9-NEXT: s_lshr_b32 s3, s3, 206161; GFX9-NEXT: s_add_i32 s2, s2, s36162; GFX9-NEXT: s_ashr_i32 s2, s2, 126163; GFX9-NEXT: v_mov_b32_e32 v1, s26164; GFX9-NEXT: global_store_dword v0, v1, s[0:1]6165; GFX9-NEXT: s_endpgm6166 %r = sdiv i32 %x, 40966167 store i32 %r, ptr addrspace(1) %out6168 ret void6169}6170 6171define amdgpu_kernel void @sdiv_i32_pow2_shl_denom(ptr addrspace(1) %out, i32 %x, i32 %y) {6172; CHECK-LABEL: @sdiv_i32_pow2_shl_denom(6173; CHECK-NEXT: [[SHL_Y:%.*]] = shl i32 4096, [[Y:%.*]]6174; CHECK-NEXT: [[R:%.*]] = sdiv i32 [[X:%.*]], [[SHL_Y]]6175; CHECK-NEXT: store i32 [[R]], ptr addrspace(1) [[OUT:%.*]], align 46176; CHECK-NEXT: ret void6177;6178; GFX6-LABEL: sdiv_i32_pow2_shl_denom:6179; GFX6: ; %bb.0:6180; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x96181; GFX6-NEXT: s_waitcnt lgkmcnt(0)6182; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]6183; GFX6-NEXT: s_lshl_b32 s5, 0x1000, s56184; GFX6-NEXT: s_abs_i32 s6, s56185; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s66186; GFX6-NEXT: s_sub_i32 s2, 0, s66187; GFX6-NEXT: s_abs_i32 s7, s46188; GFX6-NEXT: s_mov_b32 s3, 0xf0006189; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v06190; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v06191; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v06192; GFX6-NEXT: v_mul_lo_u32 v1, s2, v06193; GFX6-NEXT: s_mov_b32 s2, -16194; GFX6-NEXT: v_mul_hi_u32 v1, v0, v16195; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v16196; GFX6-NEXT: v_mul_hi_u32 v0, s7, v06197; GFX6-NEXT: v_readfirstlane_b32 s8, v06198; GFX6-NEXT: s_mul_i32 s8, s8, s66199; GFX6-NEXT: s_sub_i32 s7, s7, s86200; GFX6-NEXT: s_sub_i32 s8, s7, s66201; GFX6-NEXT: v_add_i32_e32 v1, vcc, 1, v06202; GFX6-NEXT: s_cmp_ge_u32 s7, s66203; GFX6-NEXT: s_cselect_b64 vcc, -1, 06204; GFX6-NEXT: s_cselect_b32 s7, s8, s76205; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc6206; GFX6-NEXT: v_add_i32_e32 v1, vcc, 1, v06207; GFX6-NEXT: s_cmp_ge_u32 s7, s66208; GFX6-NEXT: s_cselect_b64 vcc, -1, 06209; GFX6-NEXT: s_xor_b32 s4, s4, s56210; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc6211; GFX6-NEXT: s_ashr_i32 s4, s4, 316212; GFX6-NEXT: v_xor_b32_e32 v0, s4, v06213; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s4, v06214; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 06215; GFX6-NEXT: s_endpgm6216;6217; GFX9-LABEL: sdiv_i32_pow2_shl_denom:6218; GFX9: ; %bb.0:6219; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x246220; GFX9-NEXT: v_mov_b32_e32 v1, 06221; GFX9-NEXT: s_waitcnt lgkmcnt(0)6222; GFX9-NEXT: s_lshl_b32 s3, 0x1000, s36223; GFX9-NEXT: s_abs_i32 s4, s36224; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s46225; GFX9-NEXT: s_sub_i32 s6, 0, s46226; GFX9-NEXT: s_abs_i32 s5, s26227; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v06228; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v06229; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v06230; GFX9-NEXT: v_readfirstlane_b32 s7, v06231; GFX9-NEXT: s_mul_i32 s6, s6, s76232; GFX9-NEXT: s_mul_hi_u32 s6, s7, s66233; GFX9-NEXT: s_add_i32 s7, s7, s66234; GFX9-NEXT: s_mul_hi_u32 s6, s5, s76235; GFX9-NEXT: s_mul_i32 s8, s6, s46236; GFX9-NEXT: s_sub_i32 s5, s5, s86237; GFX9-NEXT: s_add_i32 s7, s6, 16238; GFX9-NEXT: s_sub_i32 s8, s5, s46239; GFX9-NEXT: s_cmp_ge_u32 s5, s46240; GFX9-NEXT: s_cselect_b32 s6, s7, s66241; GFX9-NEXT: s_cselect_b32 s5, s8, s56242; GFX9-NEXT: s_add_i32 s7, s6, 16243; GFX9-NEXT: s_cmp_ge_u32 s5, s46244; GFX9-NEXT: s_cselect_b32 s4, s7, s66245; GFX9-NEXT: s_xor_b32 s2, s2, s36246; GFX9-NEXT: s_ashr_i32 s2, s2, 316247; GFX9-NEXT: s_xor_b32 s3, s4, s26248; GFX9-NEXT: s_sub_i32 s2, s3, s26249; GFX9-NEXT: v_mov_b32_e32 v0, s26250; GFX9-NEXT: global_store_dword v1, v0, s[0:1]6251; GFX9-NEXT: s_endpgm6252 %shl.y = shl i32 4096, %y6253 %r = sdiv i32 %x, %shl.y6254 store i32 %r, ptr addrspace(1) %out6255 ret void6256}6257 6258define amdgpu_kernel void @sdiv_v2i32_pow2k_denom(ptr addrspace(1) %out, <2 x i32> %x) {6259; CHECK-LABEL: @sdiv_v2i32_pow2k_denom(6260; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[X:%.*]], i64 06261; CHECK-NEXT: [[TMP2:%.*]] = sdiv i32 [[TMP1]], 40966262; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i32> poison, i32 [[TMP2]], i64 06263; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i32> [[X]], i64 16264; CHECK-NEXT: [[TMP5:%.*]] = sdiv i32 [[TMP4]], 40966265; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[TMP5]], i64 16266; CHECK-NEXT: store <2 x i32> [[TMP6]], ptr addrspace(1) [[OUT:%.*]], align 86267; CHECK-NEXT: ret void6268;6269; GFX6-LABEL: sdiv_v2i32_pow2k_denom:6270; GFX6: ; %bb.0:6271; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x96272; GFX6-NEXT: s_waitcnt lgkmcnt(0)6273; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]6274; GFX6-NEXT: s_ashr_i32 s6, s4, 316275; GFX6-NEXT: s_ashr_i32 s7, s5, 316276; GFX6-NEXT: s_lshr_b32 s6, s6, 206277; GFX6-NEXT: s_lshr_b32 s7, s7, 206278; GFX6-NEXT: s_add_i32 s4, s4, s66279; GFX6-NEXT: s_add_i32 s5, s5, s76280; GFX6-NEXT: s_ashr_i32 s4, s4, 126281; GFX6-NEXT: s_ashr_i32 s5, s5, 126282; GFX6-NEXT: s_mov_b32 s3, 0xf0006283; GFX6-NEXT: s_mov_b32 s2, -16284; GFX6-NEXT: v_mov_b32_e32 v0, s46285; GFX6-NEXT: v_mov_b32_e32 v1, s56286; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 06287; GFX6-NEXT: s_endpgm6288;6289; GFX9-LABEL: sdiv_v2i32_pow2k_denom:6290; GFX9: ; %bb.0:6291; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x246292; GFX9-NEXT: v_mov_b32_e32 v2, 06293; GFX9-NEXT: s_waitcnt lgkmcnt(0)6294; GFX9-NEXT: s_ashr_i32 s4, s2, 316295; GFX9-NEXT: s_ashr_i32 s5, s3, 316296; GFX9-NEXT: s_lshr_b32 s4, s4, 206297; GFX9-NEXT: s_lshr_b32 s5, s5, 206298; GFX9-NEXT: s_add_i32 s2, s2, s46299; GFX9-NEXT: s_add_i32 s3, s3, s56300; GFX9-NEXT: s_ashr_i32 s2, s2, 126301; GFX9-NEXT: s_ashr_i32 s3, s3, 126302; GFX9-NEXT: v_mov_b32_e32 v0, s26303; GFX9-NEXT: v_mov_b32_e32 v1, s36304; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]6305; GFX9-NEXT: s_endpgm6306 %r = sdiv <2 x i32> %x, <i32 4096, i32 4096>6307 store <2 x i32> %r, ptr addrspace(1) %out6308 ret void6309}6310 6311define amdgpu_kernel void @ssdiv_v2i32_mixed_pow2k_denom(ptr addrspace(1) %out, <2 x i32> %x) {6312; CHECK-LABEL: @ssdiv_v2i32_mixed_pow2k_denom(6313; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[X:%.*]], i64 06314; CHECK-NEXT: [[TMP2:%.*]] = sdiv i32 [[TMP1]], 40966315; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i32> poison, i32 [[TMP2]], i64 06316; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i32> [[X]], i64 16317; CHECK-NEXT: [[TMP5:%.*]] = sdiv i32 [[TMP4]], 40956318; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[TMP5]], i64 16319; CHECK-NEXT: store <2 x i32> [[TMP6]], ptr addrspace(1) [[OUT:%.*]], align 86320; CHECK-NEXT: ret void6321;6322; GFX6-LABEL: ssdiv_v2i32_mixed_pow2k_denom:6323; GFX6: ; %bb.0:6324; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x96325; GFX6-NEXT: v_mov_b32_e32 v0, 0x800800816326; GFX6-NEXT: s_waitcnt lgkmcnt(0)6327; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]6328; GFX6-NEXT: v_mul_hi_i32 v0, s5, v06329; GFX6-NEXT: s_ashr_i32 s6, s4, 316330; GFX6-NEXT: s_lshr_b32 s6, s6, 206331; GFX6-NEXT: s_add_i32 s4, s4, s66332; GFX6-NEXT: v_add_i32_e32 v0, vcc, s5, v06333; GFX6-NEXT: s_ashr_i32 s4, s4, 126334; GFX6-NEXT: v_lshrrev_b32_e32 v1, 31, v06335; GFX6-NEXT: v_ashrrev_i32_e32 v0, 11, v06336; GFX6-NEXT: s_mov_b32 s3, 0xf0006337; GFX6-NEXT: s_mov_b32 s2, -16338; GFX6-NEXT: v_add_i32_e32 v1, vcc, v0, v16339; GFX6-NEXT: v_mov_b32_e32 v0, s46340; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 06341; GFX6-NEXT: s_endpgm6342;6343; GFX9-LABEL: ssdiv_v2i32_mixed_pow2k_denom:6344; GFX9: ; %bb.0:6345; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x246346; GFX9-NEXT: v_mov_b32_e32 v2, 06347; GFX9-NEXT: s_waitcnt lgkmcnt(0)6348; GFX9-NEXT: s_ashr_i32 s4, s2, 316349; GFX9-NEXT: s_mul_hi_i32 s5, s3, 0x800800816350; GFX9-NEXT: s_lshr_b32 s4, s4, 206351; GFX9-NEXT: s_add_i32 s5, s5, s36352; GFX9-NEXT: s_add_i32 s2, s2, s46353; GFX9-NEXT: s_lshr_b32 s3, s5, 316354; GFX9-NEXT: s_ashr_i32 s4, s5, 116355; GFX9-NEXT: s_ashr_i32 s2, s2, 126356; GFX9-NEXT: s_add_i32 s4, s4, s36357; GFX9-NEXT: v_mov_b32_e32 v0, s26358; GFX9-NEXT: v_mov_b32_e32 v1, s46359; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]6360; GFX9-NEXT: s_endpgm6361 %r = sdiv <2 x i32> %x, <i32 4096, i32 4095>6362 store <2 x i32> %r, ptr addrspace(1) %out6363 ret void6364}6365 6366define amdgpu_kernel void @sdiv_v2i32_pow2_shl_denom(ptr addrspace(1) %out, <2 x i32> %x, <2 x i32> %y) {6367; CHECK-LABEL: @sdiv_v2i32_pow2_shl_denom(6368; CHECK-NEXT: [[SHL_Y:%.*]] = shl <2 x i32> splat (i32 4096), [[Y:%.*]]6369; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[X:%.*]], i64 06370; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i32> [[SHL_Y]], i64 06371; CHECK-NEXT: [[TMP3:%.*]] = ashr i32 [[TMP1]], 316372; CHECK-NEXT: [[TMP4:%.*]] = ashr i32 [[TMP2]], 316373; CHECK-NEXT: [[TMP5:%.*]] = xor i32 [[TMP3]], [[TMP4]]6374; CHECK-NEXT: [[TMP6:%.*]] = add i32 [[TMP1]], [[TMP3]]6375; CHECK-NEXT: [[TMP7:%.*]] = add i32 [[TMP2]], [[TMP4]]6376; CHECK-NEXT: [[TMP8:%.*]] = xor i32 [[TMP6]], [[TMP3]]6377; CHECK-NEXT: [[TMP9:%.*]] = xor i32 [[TMP7]], [[TMP4]]6378; CHECK-NEXT: [[TMP10:%.*]] = uitofp i32 [[TMP9]] to float6379; CHECK-NEXT: [[TMP11:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP10]])6380; CHECK-NEXT: [[TMP12:%.*]] = fmul fast float [[TMP11]], 0x41EFFFFFC00000006381; CHECK-NEXT: [[TMP13:%.*]] = fptoui float [[TMP12]] to i326382; CHECK-NEXT: [[TMP14:%.*]] = sub i32 0, [[TMP9]]6383; CHECK-NEXT: [[TMP15:%.*]] = mul i32 [[TMP14]], [[TMP13]]6384; CHECK-NEXT: [[TMP16:%.*]] = zext i32 [[TMP13]] to i646385; CHECK-NEXT: [[TMP17:%.*]] = zext i32 [[TMP15]] to i646386; CHECK-NEXT: [[TMP18:%.*]] = mul i64 [[TMP16]], [[TMP17]]6387; CHECK-NEXT: [[TMP19:%.*]] = trunc i64 [[TMP18]] to i326388; CHECK-NEXT: [[TMP20:%.*]] = lshr i64 [[TMP18]], 326389; CHECK-NEXT: [[TMP21:%.*]] = trunc i64 [[TMP20]] to i326390; CHECK-NEXT: [[TMP22:%.*]] = add i32 [[TMP13]], [[TMP21]]6391; CHECK-NEXT: [[TMP23:%.*]] = zext i32 [[TMP8]] to i646392; CHECK-NEXT: [[TMP24:%.*]] = zext i32 [[TMP22]] to i646393; CHECK-NEXT: [[TMP25:%.*]] = mul i64 [[TMP23]], [[TMP24]]6394; CHECK-NEXT: [[TMP26:%.*]] = trunc i64 [[TMP25]] to i326395; CHECK-NEXT: [[TMP27:%.*]] = lshr i64 [[TMP25]], 326396; CHECK-NEXT: [[TMP28:%.*]] = trunc i64 [[TMP27]] to i326397; CHECK-NEXT: [[TMP29:%.*]] = mul i32 [[TMP28]], [[TMP9]]6398; CHECK-NEXT: [[TMP30:%.*]] = sub i32 [[TMP8]], [[TMP29]]6399; CHECK-NEXT: [[TMP31:%.*]] = icmp uge i32 [[TMP30]], [[TMP9]]6400; CHECK-NEXT: [[TMP32:%.*]] = add i32 [[TMP28]], 16401; CHECK-NEXT: [[TMP33:%.*]] = select i1 [[TMP31]], i32 [[TMP32]], i32 [[TMP28]]6402; CHECK-NEXT: [[TMP34:%.*]] = sub i32 [[TMP30]], [[TMP9]]6403; CHECK-NEXT: [[TMP35:%.*]] = select i1 [[TMP31]], i32 [[TMP34]], i32 [[TMP30]]6404; CHECK-NEXT: [[TMP36:%.*]] = icmp uge i32 [[TMP35]], [[TMP9]]6405; CHECK-NEXT: [[TMP37:%.*]] = add i32 [[TMP33]], 16406; CHECK-NEXT: [[TMP38:%.*]] = select i1 [[TMP36]], i32 [[TMP37]], i32 [[TMP33]]6407; CHECK-NEXT: [[TMP39:%.*]] = xor i32 [[TMP38]], [[TMP5]]6408; CHECK-NEXT: [[TMP40:%.*]] = sub i32 [[TMP39]], [[TMP5]]6409; CHECK-NEXT: [[TMP41:%.*]] = insertelement <2 x i32> poison, i32 [[TMP40]], i64 06410; CHECK-NEXT: [[TMP42:%.*]] = extractelement <2 x i32> [[X]], i64 16411; CHECK-NEXT: [[TMP43:%.*]] = extractelement <2 x i32> [[SHL_Y]], i64 16412; CHECK-NEXT: [[TMP44:%.*]] = ashr i32 [[TMP42]], 316413; CHECK-NEXT: [[TMP45:%.*]] = ashr i32 [[TMP43]], 316414; CHECK-NEXT: [[TMP46:%.*]] = xor i32 [[TMP44]], [[TMP45]]6415; CHECK-NEXT: [[TMP47:%.*]] = add i32 [[TMP42]], [[TMP44]]6416; CHECK-NEXT: [[TMP48:%.*]] = add i32 [[TMP43]], [[TMP45]]6417; CHECK-NEXT: [[TMP49:%.*]] = xor i32 [[TMP47]], [[TMP44]]6418; CHECK-NEXT: [[TMP50:%.*]] = xor i32 [[TMP48]], [[TMP45]]6419; CHECK-NEXT: [[TMP51:%.*]] = uitofp i32 [[TMP50]] to float6420; CHECK-NEXT: [[TMP52:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP51]])6421; CHECK-NEXT: [[TMP53:%.*]] = fmul fast float [[TMP52]], 0x41EFFFFFC00000006422; CHECK-NEXT: [[TMP54:%.*]] = fptoui float [[TMP53]] to i326423; CHECK-NEXT: [[TMP55:%.*]] = sub i32 0, [[TMP50]]6424; CHECK-NEXT: [[TMP56:%.*]] = mul i32 [[TMP55]], [[TMP54]]6425; CHECK-NEXT: [[TMP57:%.*]] = zext i32 [[TMP54]] to i646426; CHECK-NEXT: [[TMP58:%.*]] = zext i32 [[TMP56]] to i646427; CHECK-NEXT: [[TMP59:%.*]] = mul i64 [[TMP57]], [[TMP58]]6428; CHECK-NEXT: [[TMP60:%.*]] = trunc i64 [[TMP59]] to i326429; CHECK-NEXT: [[TMP61:%.*]] = lshr i64 [[TMP59]], 326430; CHECK-NEXT: [[TMP62:%.*]] = trunc i64 [[TMP61]] to i326431; CHECK-NEXT: [[TMP63:%.*]] = add i32 [[TMP54]], [[TMP62]]6432; CHECK-NEXT: [[TMP64:%.*]] = zext i32 [[TMP49]] to i646433; CHECK-NEXT: [[TMP65:%.*]] = zext i32 [[TMP63]] to i646434; CHECK-NEXT: [[TMP66:%.*]] = mul i64 [[TMP64]], [[TMP65]]6435; CHECK-NEXT: [[TMP67:%.*]] = trunc i64 [[TMP66]] to i326436; CHECK-NEXT: [[TMP68:%.*]] = lshr i64 [[TMP66]], 326437; CHECK-NEXT: [[TMP69:%.*]] = trunc i64 [[TMP68]] to i326438; CHECK-NEXT: [[TMP70:%.*]] = mul i32 [[TMP69]], [[TMP50]]6439; CHECK-NEXT: [[TMP71:%.*]] = sub i32 [[TMP49]], [[TMP70]]6440; CHECK-NEXT: [[TMP72:%.*]] = icmp uge i32 [[TMP71]], [[TMP50]]6441; CHECK-NEXT: [[TMP73:%.*]] = add i32 [[TMP69]], 16442; CHECK-NEXT: [[TMP74:%.*]] = select i1 [[TMP72]], i32 [[TMP73]], i32 [[TMP69]]6443; CHECK-NEXT: [[TMP75:%.*]] = sub i32 [[TMP71]], [[TMP50]]6444; CHECK-NEXT: [[TMP76:%.*]] = select i1 [[TMP72]], i32 [[TMP75]], i32 [[TMP71]]6445; CHECK-NEXT: [[TMP77:%.*]] = icmp uge i32 [[TMP76]], [[TMP50]]6446; CHECK-NEXT: [[TMP78:%.*]] = add i32 [[TMP74]], 16447; CHECK-NEXT: [[TMP79:%.*]] = select i1 [[TMP77]], i32 [[TMP78]], i32 [[TMP74]]6448; CHECK-NEXT: [[TMP80:%.*]] = xor i32 [[TMP79]], [[TMP46]]6449; CHECK-NEXT: [[TMP81:%.*]] = sub i32 [[TMP80]], [[TMP46]]6450; CHECK-NEXT: [[TMP82:%.*]] = insertelement <2 x i32> [[TMP41]], i32 [[TMP81]], i64 16451; CHECK-NEXT: store <2 x i32> [[TMP82]], ptr addrspace(1) [[OUT:%.*]], align 86452; CHECK-NEXT: ret void6453;6454; GFX6-LABEL: sdiv_v2i32_pow2_shl_denom:6455; GFX6: ; %bb.0:6456; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb6457; GFX6-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x96458; GFX6-NEXT: s_waitcnt lgkmcnt(0)6459; GFX6-NEXT: s_lshl_b32 s2, 0x1000, s26460; GFX6-NEXT: s_abs_i32 s6, s26461; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s66462; GFX6-NEXT: s_sub_i32 s7, 0, s66463; GFX6-NEXT: s_lshl_b32 s3, 0x1000, s36464; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v06465; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v06466; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v06467; GFX6-NEXT: v_mul_lo_u32 v1, s7, v06468; GFX6-NEXT: s_abs_i32 s7, s06469; GFX6-NEXT: s_xor_b32 s0, s0, s26470; GFX6-NEXT: s_ashr_i32 s0, s0, 316471; GFX6-NEXT: v_mul_hi_u32 v1, v0, v16472; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v16473; GFX6-NEXT: v_mul_hi_u32 v0, s7, v06474; GFX6-NEXT: v_readfirstlane_b32 s2, v06475; GFX6-NEXT: s_mul_i32 s2, s2, s66476; GFX6-NEXT: s_sub_i32 s2, s7, s26477; GFX6-NEXT: s_sub_i32 s7, s2, s66478; GFX6-NEXT: v_add_i32_e32 v1, vcc, 1, v06479; GFX6-NEXT: s_cmp_ge_u32 s2, s66480; GFX6-NEXT: s_cselect_b64 vcc, -1, 06481; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc6482; GFX6-NEXT: s_cselect_b32 s2, s7, s26483; GFX6-NEXT: v_add_i32_e32 v1, vcc, 1, v06484; GFX6-NEXT: s_cmp_ge_u32 s2, s66485; GFX6-NEXT: s_cselect_b64 vcc, -1, 06486; GFX6-NEXT: s_abs_i32 s2, s36487; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s26488; GFX6-NEXT: s_sub_i32 s6, 0, s26489; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc6490; GFX6-NEXT: s_xor_b32 s3, s1, s36491; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v26492; GFX6-NEXT: s_abs_i32 s1, s16493; GFX6-NEXT: v_xor_b32_e32 v0, s0, v06494; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s0, v06495; GFX6-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v26496; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v26497; GFX6-NEXT: s_ashr_i32 s3, s3, 316498; GFX6-NEXT: s_mov_b32 s7, 0xf0006499; GFX6-NEXT: v_mul_lo_u32 v3, s6, v26500; GFX6-NEXT: s_mov_b32 s6, -16501; GFX6-NEXT: v_mul_hi_u32 v1, v2, v36502; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v16503; GFX6-NEXT: v_mul_hi_u32 v1, s1, v16504; GFX6-NEXT: v_readfirstlane_b32 s0, v16505; GFX6-NEXT: s_mul_i32 s0, s0, s26506; GFX6-NEXT: s_sub_i32 s0, s1, s06507; GFX6-NEXT: s_sub_i32 s1, s0, s26508; GFX6-NEXT: v_add_i32_e32 v2, vcc, 1, v16509; GFX6-NEXT: s_cmp_ge_u32 s0, s26510; GFX6-NEXT: s_cselect_b64 vcc, -1, 06511; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc6512; GFX6-NEXT: s_cselect_b32 s0, s1, s06513; GFX6-NEXT: v_add_i32_e32 v2, vcc, 1, v16514; GFX6-NEXT: s_cmp_ge_u32 s0, s26515; GFX6-NEXT: s_cselect_b64 vcc, -1, 06516; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc6517; GFX6-NEXT: v_xor_b32_e32 v1, s3, v16518; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, s3, v16519; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 06520; GFX6-NEXT: s_endpgm6521;6522; GFX9-LABEL: sdiv_v2i32_pow2_shl_denom:6523; GFX9: ; %bb.0:6524; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c6525; GFX9-NEXT: v_mov_b32_e32 v2, 06526; GFX9-NEXT: s_waitcnt lgkmcnt(0)6527; GFX9-NEXT: s_lshl_b32 s2, 0x1000, s26528; GFX9-NEXT: s_abs_i32 s6, s26529; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s66530; GFX9-NEXT: s_lshl_b32 s7, 0x1000, s36531; GFX9-NEXT: s_abs_i32 s3, s06532; GFX9-NEXT: s_xor_b32 s0, s0, s26533; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v06534; GFX9-NEXT: s_sub_i32 s2, 0, s66535; GFX9-NEXT: s_ashr_i32 s0, s0, 316536; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v06537; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v06538; GFX9-NEXT: v_readfirstlane_b32 s8, v06539; GFX9-NEXT: s_mul_i32 s2, s2, s86540; GFX9-NEXT: s_mul_hi_u32 s2, s8, s26541; GFX9-NEXT: s_add_i32 s8, s8, s26542; GFX9-NEXT: s_mul_hi_u32 s2, s3, s86543; GFX9-NEXT: s_mul_i32 s8, s2, s66544; GFX9-NEXT: s_sub_i32 s3, s3, s86545; GFX9-NEXT: s_add_i32 s9, s2, 16546; GFX9-NEXT: s_sub_i32 s8, s3, s66547; GFX9-NEXT: s_cmp_ge_u32 s3, s66548; GFX9-NEXT: s_cselect_b32 s2, s9, s26549; GFX9-NEXT: s_cselect_b32 s3, s8, s36550; GFX9-NEXT: s_add_i32 s8, s2, 16551; GFX9-NEXT: s_cmp_ge_u32 s3, s66552; GFX9-NEXT: s_cselect_b32 s6, s8, s26553; GFX9-NEXT: s_abs_i32 s8, s76554; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s86555; GFX9-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x246556; GFX9-NEXT: s_xor_b32 s5, s6, s06557; GFX9-NEXT: s_sub_i32 s6, 0, s86558; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v06559; GFX9-NEXT: s_sub_i32 s0, s5, s06560; GFX9-NEXT: s_xor_b32 s4, s1, s76561; GFX9-NEXT: s_abs_i32 s1, s16562; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v06563; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v06564; GFX9-NEXT: s_ashr_i32 s4, s4, 316565; GFX9-NEXT: v_readfirstlane_b32 s5, v06566; GFX9-NEXT: s_mul_i32 s6, s6, s56567; GFX9-NEXT: s_mul_hi_u32 s6, s5, s66568; GFX9-NEXT: s_add_i32 s5, s5, s66569; GFX9-NEXT: s_mul_hi_u32 s5, s1, s56570; GFX9-NEXT: s_mul_i32 s6, s5, s86571; GFX9-NEXT: s_sub_i32 s1, s1, s66572; GFX9-NEXT: s_add_i32 s7, s5, 16573; GFX9-NEXT: s_sub_i32 s6, s1, s86574; GFX9-NEXT: s_cmp_ge_u32 s1, s86575; GFX9-NEXT: s_cselect_b32 s5, s7, s56576; GFX9-NEXT: s_cselect_b32 s1, s6, s16577; GFX9-NEXT: s_add_i32 s6, s5, 16578; GFX9-NEXT: s_cmp_ge_u32 s1, s86579; GFX9-NEXT: s_cselect_b32 s1, s6, s56580; GFX9-NEXT: s_xor_b32 s1, s1, s46581; GFX9-NEXT: s_sub_i32 s1, s1, s46582; GFX9-NEXT: v_mov_b32_e32 v0, s06583; GFX9-NEXT: v_mov_b32_e32 v1, s16584; GFX9-NEXT: s_waitcnt lgkmcnt(0)6585; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]6586; GFX9-NEXT: s_endpgm6587 %shl.y = shl <2 x i32> <i32 4096, i32 4096>, %y6588 %r = sdiv <2 x i32> %x, %shl.y6589 store <2 x i32> %r, ptr addrspace(1) %out6590 ret void6591}6592 6593define amdgpu_kernel void @srem_i32_oddk_denom(ptr addrspace(1) %out, i32 %x) {6594; CHECK-LABEL: @srem_i32_oddk_denom(6595; CHECK-NEXT: [[R:%.*]] = srem i32 [[X:%.*]], 12351956596; CHECK-NEXT: store i32 [[R]], ptr addrspace(1) [[OUT:%.*]], align 46597; CHECK-NEXT: ret void6598;6599; GFX6-LABEL: srem_i32_oddk_denom:6600; GFX6: ; %bb.0:6601; GFX6-NEXT: s_load_dword s6, s[4:5], 0xb6602; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x96603; GFX6-NEXT: v_mov_b32_e32 v0, 0xd95284416604; GFX6-NEXT: s_mov_b32 s3, 0xf0006605; GFX6-NEXT: s_mov_b32 s2, -16606; GFX6-NEXT: s_waitcnt lgkmcnt(0)6607; GFX6-NEXT: v_mul_hi_i32 v0, s6, v06608; GFX6-NEXT: v_readfirstlane_b32 s4, v06609; GFX6-NEXT: s_add_i32 s4, s4, s66610; GFX6-NEXT: s_lshr_b32 s5, s4, 316611; GFX6-NEXT: s_ashr_i32 s4, s4, 206612; GFX6-NEXT: s_add_i32 s4, s4, s56613; GFX6-NEXT: s_mul_i32 s4, s4, 0x12d8fb6614; GFX6-NEXT: s_sub_i32 s4, s6, s46615; GFX6-NEXT: v_mov_b32_e32 v0, s46616; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 06617; GFX6-NEXT: s_endpgm6618;6619; GFX9-LABEL: srem_i32_oddk_denom:6620; GFX9: ; %bb.0:6621; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c6622; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x246623; GFX9-NEXT: v_mov_b32_e32 v0, 06624; GFX9-NEXT: s_waitcnt lgkmcnt(0)6625; GFX9-NEXT: s_mul_hi_i32 s3, s2, 0xd95284416626; GFX9-NEXT: s_add_i32 s3, s3, s26627; GFX9-NEXT: s_lshr_b32 s4, s3, 316628; GFX9-NEXT: s_ashr_i32 s3, s3, 206629; GFX9-NEXT: s_add_i32 s3, s3, s46630; GFX9-NEXT: s_mul_i32 s3, s3, 0x12d8fb6631; GFX9-NEXT: s_sub_i32 s2, s2, s36632; GFX9-NEXT: v_mov_b32_e32 v1, s26633; GFX9-NEXT: global_store_dword v0, v1, s[0:1]6634; GFX9-NEXT: s_endpgm6635 %r = srem i32 %x, 12351956636 store i32 %r, ptr addrspace(1) %out6637 ret void6638}6639 6640define amdgpu_kernel void @srem_i32_pow2k_denom(ptr addrspace(1) %out, i32 %x) {6641; CHECK-LABEL: @srem_i32_pow2k_denom(6642; CHECK-NEXT: [[R:%.*]] = srem i32 [[X:%.*]], 40966643; CHECK-NEXT: store i32 [[R]], ptr addrspace(1) [[OUT:%.*]], align 46644; CHECK-NEXT: ret void6645;6646; GFX6-LABEL: srem_i32_pow2k_denom:6647; GFX6: ; %bb.0:6648; GFX6-NEXT: s_load_dword s6, s[4:5], 0xb6649; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x96650; GFX6-NEXT: s_mov_b32 s3, 0xf0006651; GFX6-NEXT: s_mov_b32 s2, -16652; GFX6-NEXT: s_waitcnt lgkmcnt(0)6653; GFX6-NEXT: s_ashr_i32 s4, s6, 316654; GFX6-NEXT: s_lshr_b32 s4, s4, 206655; GFX6-NEXT: s_add_i32 s4, s6, s46656; GFX6-NEXT: s_and_b32 s4, s4, 0xfffff0006657; GFX6-NEXT: s_sub_i32 s4, s6, s46658; GFX6-NEXT: v_mov_b32_e32 v0, s46659; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 06660; GFX6-NEXT: s_endpgm6661;6662; GFX9-LABEL: srem_i32_pow2k_denom:6663; GFX9: ; %bb.0:6664; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c6665; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x246666; GFX9-NEXT: v_mov_b32_e32 v0, 06667; GFX9-NEXT: s_waitcnt lgkmcnt(0)6668; GFX9-NEXT: s_ashr_i32 s3, s2, 316669; GFX9-NEXT: s_lshr_b32 s3, s3, 206670; GFX9-NEXT: s_add_i32 s3, s2, s36671; GFX9-NEXT: s_and_b32 s3, s3, 0xfffff0006672; GFX9-NEXT: s_sub_i32 s2, s2, s36673; GFX9-NEXT: v_mov_b32_e32 v1, s26674; GFX9-NEXT: global_store_dword v0, v1, s[0:1]6675; GFX9-NEXT: s_endpgm6676 %r = srem i32 %x, 40966677 store i32 %r, ptr addrspace(1) %out6678 ret void6679}6680 6681define amdgpu_kernel void @srem_i32_pow2_shl_denom(ptr addrspace(1) %out, i32 %x, i32 %y) {6682; CHECK-LABEL: @srem_i32_pow2_shl_denom(6683; CHECK-NEXT: [[SHL_Y:%.*]] = shl i32 4096, [[Y:%.*]]6684; CHECK-NEXT: [[R:%.*]] = srem i32 [[X:%.*]], [[SHL_Y]]6685; CHECK-NEXT: store i32 [[R]], ptr addrspace(1) [[OUT:%.*]], align 46686; CHECK-NEXT: ret void6687;6688; GFX6-LABEL: srem_i32_pow2_shl_denom:6689; GFX6: ; %bb.0:6690; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x96691; GFX6-NEXT: s_waitcnt lgkmcnt(0)6692; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]6693; GFX6-NEXT: s_lshl_b32 s2, 0x1000, s56694; GFX6-NEXT: s_abs_i32 s5, s26695; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s56696; GFX6-NEXT: s_sub_i32 s2, 0, s56697; GFX6-NEXT: s_abs_i32 s6, s46698; GFX6-NEXT: s_mov_b32 s3, 0xf0006699; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v06700; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v06701; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v06702; GFX6-NEXT: v_mul_lo_u32 v1, s2, v06703; GFX6-NEXT: s_mov_b32 s2, -16704; GFX6-NEXT: v_mul_hi_u32 v1, v0, v16705; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v16706; GFX6-NEXT: v_mul_hi_u32 v0, s6, v06707; GFX6-NEXT: v_readfirstlane_b32 s7, v06708; GFX6-NEXT: s_mul_i32 s7, s7, s56709; GFX6-NEXT: s_sub_i32 s6, s6, s76710; GFX6-NEXT: s_sub_i32 s7, s6, s56711; GFX6-NEXT: s_cmp_ge_u32 s6, s56712; GFX6-NEXT: s_cselect_b32 s6, s7, s66713; GFX6-NEXT: s_sub_i32 s7, s6, s56714; GFX6-NEXT: s_cmp_ge_u32 s6, s56715; GFX6-NEXT: s_cselect_b32 s5, s7, s66716; GFX6-NEXT: s_ashr_i32 s4, s4, 316717; GFX6-NEXT: s_xor_b32 s5, s5, s46718; GFX6-NEXT: s_sub_i32 s4, s5, s46719; GFX6-NEXT: v_mov_b32_e32 v0, s46720; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 06721; GFX6-NEXT: s_endpgm6722;6723; GFX9-LABEL: srem_i32_pow2_shl_denom:6724; GFX9: ; %bb.0:6725; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x246726; GFX9-NEXT: v_mov_b32_e32 v1, 06727; GFX9-NEXT: s_waitcnt lgkmcnt(0)6728; GFX9-NEXT: s_lshl_b32 s3, 0x1000, s36729; GFX9-NEXT: s_abs_i32 s3, s36730; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s36731; GFX9-NEXT: s_sub_i32 s5, 0, s36732; GFX9-NEXT: s_abs_i32 s4, s26733; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v06734; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v06735; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v06736; GFX9-NEXT: v_readfirstlane_b32 s6, v06737; GFX9-NEXT: s_mul_i32 s5, s5, s66738; GFX9-NEXT: s_mul_hi_u32 s5, s6, s56739; GFX9-NEXT: s_add_i32 s6, s6, s56740; GFX9-NEXT: s_mul_hi_u32 s5, s4, s66741; GFX9-NEXT: s_mul_i32 s5, s5, s36742; GFX9-NEXT: s_sub_i32 s4, s4, s56743; GFX9-NEXT: s_sub_i32 s5, s4, s36744; GFX9-NEXT: s_cmp_ge_u32 s4, s36745; GFX9-NEXT: s_cselect_b32 s4, s5, s46746; GFX9-NEXT: s_sub_i32 s5, s4, s36747; GFX9-NEXT: s_cmp_ge_u32 s4, s36748; GFX9-NEXT: s_cselect_b32 s3, s5, s46749; GFX9-NEXT: s_ashr_i32 s2, s2, 316750; GFX9-NEXT: s_xor_b32 s3, s3, s26751; GFX9-NEXT: s_sub_i32 s2, s3, s26752; GFX9-NEXT: v_mov_b32_e32 v0, s26753; GFX9-NEXT: global_store_dword v1, v0, s[0:1]6754; GFX9-NEXT: s_endpgm6755 %shl.y = shl i32 4096, %y6756 %r = srem i32 %x, %shl.y6757 store i32 %r, ptr addrspace(1) %out6758 ret void6759}6760 6761define amdgpu_kernel void @srem_v2i32_pow2k_denom(ptr addrspace(1) %out, <2 x i32> %x) {6762; CHECK-LABEL: @srem_v2i32_pow2k_denom(6763; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[X:%.*]], i64 06764; CHECK-NEXT: [[TMP2:%.*]] = srem i32 [[TMP1]], 40966765; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i32> poison, i32 [[TMP2]], i64 06766; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i32> [[X]], i64 16767; CHECK-NEXT: [[TMP5:%.*]] = srem i32 [[TMP4]], 40966768; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[TMP5]], i64 16769; CHECK-NEXT: store <2 x i32> [[TMP6]], ptr addrspace(1) [[OUT:%.*]], align 86770; CHECK-NEXT: ret void6771;6772; GFX6-LABEL: srem_v2i32_pow2k_denom:6773; GFX6: ; %bb.0:6774; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x96775; GFX6-NEXT: s_waitcnt lgkmcnt(0)6776; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]6777; GFX6-NEXT: s_ashr_i32 s6, s4, 316778; GFX6-NEXT: s_lshr_b32 s6, s6, 206779; GFX6-NEXT: s_ashr_i32 s7, s5, 316780; GFX6-NEXT: s_add_i32 s6, s4, s66781; GFX6-NEXT: s_lshr_b32 s7, s7, 206782; GFX6-NEXT: s_and_b32 s6, s6, 0xfffff0006783; GFX6-NEXT: s_sub_i32 s4, s4, s66784; GFX6-NEXT: s_add_i32 s6, s5, s76785; GFX6-NEXT: s_and_b32 s6, s6, 0xfffff0006786; GFX6-NEXT: s_sub_i32 s5, s5, s66787; GFX6-NEXT: s_mov_b32 s3, 0xf0006788; GFX6-NEXT: s_mov_b32 s2, -16789; GFX6-NEXT: v_mov_b32_e32 v0, s46790; GFX6-NEXT: v_mov_b32_e32 v1, s56791; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 06792; GFX6-NEXT: s_endpgm6793;6794; GFX9-LABEL: srem_v2i32_pow2k_denom:6795; GFX9: ; %bb.0:6796; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x246797; GFX9-NEXT: v_mov_b32_e32 v2, 06798; GFX9-NEXT: s_waitcnt lgkmcnt(0)6799; GFX9-NEXT: s_ashr_i32 s4, s2, 316800; GFX9-NEXT: s_ashr_i32 s5, s3, 316801; GFX9-NEXT: s_lshr_b32 s4, s4, 206802; GFX9-NEXT: s_lshr_b32 s5, s5, 206803; GFX9-NEXT: s_add_i32 s4, s2, s46804; GFX9-NEXT: s_add_i32 s5, s3, s56805; GFX9-NEXT: s_and_b32 s4, s4, 0xfffff0006806; GFX9-NEXT: s_sub_i32 s2, s2, s46807; GFX9-NEXT: s_and_b32 s4, s5, 0xfffff0006808; GFX9-NEXT: s_sub_i32 s3, s3, s46809; GFX9-NEXT: v_mov_b32_e32 v0, s26810; GFX9-NEXT: v_mov_b32_e32 v1, s36811; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]6812; GFX9-NEXT: s_endpgm6813 %r = srem <2 x i32> %x, <i32 4096, i32 4096>6814 store <2 x i32> %r, ptr addrspace(1) %out6815 ret void6816}6817 6818define amdgpu_kernel void @srem_v2i32_pow2_shl_denom(ptr addrspace(1) %out, <2 x i32> %x, <2 x i32> %y) {6819; CHECK-LABEL: @srem_v2i32_pow2_shl_denom(6820; CHECK-NEXT: [[SHL_Y:%.*]] = shl <2 x i32> splat (i32 4096), [[Y:%.*]]6821; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[X:%.*]], i64 06822; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i32> [[SHL_Y]], i64 06823; CHECK-NEXT: [[TMP3:%.*]] = ashr i32 [[TMP1]], 316824; CHECK-NEXT: [[TMP4:%.*]] = ashr i32 [[TMP2]], 316825; CHECK-NEXT: [[TMP5:%.*]] = add i32 [[TMP1]], [[TMP3]]6826; CHECK-NEXT: [[TMP6:%.*]] = add i32 [[TMP2]], [[TMP4]]6827; CHECK-NEXT: [[TMP7:%.*]] = xor i32 [[TMP5]], [[TMP3]]6828; CHECK-NEXT: [[TMP8:%.*]] = xor i32 [[TMP6]], [[TMP4]]6829; CHECK-NEXT: [[TMP9:%.*]] = uitofp i32 [[TMP8]] to float6830; CHECK-NEXT: [[TMP10:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP9]])6831; CHECK-NEXT: [[TMP11:%.*]] = fmul fast float [[TMP10]], 0x41EFFFFFC00000006832; CHECK-NEXT: [[TMP12:%.*]] = fptoui float [[TMP11]] to i326833; CHECK-NEXT: [[TMP13:%.*]] = sub i32 0, [[TMP8]]6834; CHECK-NEXT: [[TMP14:%.*]] = mul i32 [[TMP13]], [[TMP12]]6835; CHECK-NEXT: [[TMP15:%.*]] = zext i32 [[TMP12]] to i646836; CHECK-NEXT: [[TMP16:%.*]] = zext i32 [[TMP14]] to i646837; CHECK-NEXT: [[TMP17:%.*]] = mul i64 [[TMP15]], [[TMP16]]6838; CHECK-NEXT: [[TMP18:%.*]] = trunc i64 [[TMP17]] to i326839; CHECK-NEXT: [[TMP19:%.*]] = lshr i64 [[TMP17]], 326840; CHECK-NEXT: [[TMP20:%.*]] = trunc i64 [[TMP19]] to i326841; CHECK-NEXT: [[TMP21:%.*]] = add i32 [[TMP12]], [[TMP20]]6842; CHECK-NEXT: [[TMP22:%.*]] = zext i32 [[TMP7]] to i646843; CHECK-NEXT: [[TMP23:%.*]] = zext i32 [[TMP21]] to i646844; CHECK-NEXT: [[TMP24:%.*]] = mul i64 [[TMP22]], [[TMP23]]6845; CHECK-NEXT: [[TMP25:%.*]] = trunc i64 [[TMP24]] to i326846; CHECK-NEXT: [[TMP26:%.*]] = lshr i64 [[TMP24]], 326847; CHECK-NEXT: [[TMP27:%.*]] = trunc i64 [[TMP26]] to i326848; CHECK-NEXT: [[TMP28:%.*]] = mul i32 [[TMP27]], [[TMP8]]6849; CHECK-NEXT: [[TMP29:%.*]] = sub i32 [[TMP7]], [[TMP28]]6850; CHECK-NEXT: [[TMP30:%.*]] = icmp uge i32 [[TMP29]], [[TMP8]]6851; CHECK-NEXT: [[TMP31:%.*]] = sub i32 [[TMP29]], [[TMP8]]6852; CHECK-NEXT: [[TMP32:%.*]] = select i1 [[TMP30]], i32 [[TMP31]], i32 [[TMP29]]6853; CHECK-NEXT: [[TMP33:%.*]] = icmp uge i32 [[TMP32]], [[TMP8]]6854; CHECK-NEXT: [[TMP34:%.*]] = sub i32 [[TMP32]], [[TMP8]]6855; CHECK-NEXT: [[TMP35:%.*]] = select i1 [[TMP33]], i32 [[TMP34]], i32 [[TMP32]]6856; CHECK-NEXT: [[TMP36:%.*]] = xor i32 [[TMP35]], [[TMP3]]6857; CHECK-NEXT: [[TMP37:%.*]] = sub i32 [[TMP36]], [[TMP3]]6858; CHECK-NEXT: [[TMP38:%.*]] = insertelement <2 x i32> poison, i32 [[TMP37]], i64 06859; CHECK-NEXT: [[TMP39:%.*]] = extractelement <2 x i32> [[X]], i64 16860; CHECK-NEXT: [[TMP40:%.*]] = extractelement <2 x i32> [[SHL_Y]], i64 16861; CHECK-NEXT: [[TMP41:%.*]] = ashr i32 [[TMP39]], 316862; CHECK-NEXT: [[TMP42:%.*]] = ashr i32 [[TMP40]], 316863; CHECK-NEXT: [[TMP43:%.*]] = add i32 [[TMP39]], [[TMP41]]6864; CHECK-NEXT: [[TMP44:%.*]] = add i32 [[TMP40]], [[TMP42]]6865; CHECK-NEXT: [[TMP45:%.*]] = xor i32 [[TMP43]], [[TMP41]]6866; CHECK-NEXT: [[TMP46:%.*]] = xor i32 [[TMP44]], [[TMP42]]6867; CHECK-NEXT: [[TMP47:%.*]] = uitofp i32 [[TMP46]] to float6868; CHECK-NEXT: [[TMP48:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP47]])6869; CHECK-NEXT: [[TMP49:%.*]] = fmul fast float [[TMP48]], 0x41EFFFFFC00000006870; CHECK-NEXT: [[TMP50:%.*]] = fptoui float [[TMP49]] to i326871; CHECK-NEXT: [[TMP51:%.*]] = sub i32 0, [[TMP46]]6872; CHECK-NEXT: [[TMP52:%.*]] = mul i32 [[TMP51]], [[TMP50]]6873; CHECK-NEXT: [[TMP53:%.*]] = zext i32 [[TMP50]] to i646874; CHECK-NEXT: [[TMP54:%.*]] = zext i32 [[TMP52]] to i646875; CHECK-NEXT: [[TMP55:%.*]] = mul i64 [[TMP53]], [[TMP54]]6876; CHECK-NEXT: [[TMP56:%.*]] = trunc i64 [[TMP55]] to i326877; CHECK-NEXT: [[TMP57:%.*]] = lshr i64 [[TMP55]], 326878; CHECK-NEXT: [[TMP58:%.*]] = trunc i64 [[TMP57]] to i326879; CHECK-NEXT: [[TMP59:%.*]] = add i32 [[TMP50]], [[TMP58]]6880; CHECK-NEXT: [[TMP60:%.*]] = zext i32 [[TMP45]] to i646881; CHECK-NEXT: [[TMP61:%.*]] = zext i32 [[TMP59]] to i646882; CHECK-NEXT: [[TMP62:%.*]] = mul i64 [[TMP60]], [[TMP61]]6883; CHECK-NEXT: [[TMP63:%.*]] = trunc i64 [[TMP62]] to i326884; CHECK-NEXT: [[TMP64:%.*]] = lshr i64 [[TMP62]], 326885; CHECK-NEXT: [[TMP65:%.*]] = trunc i64 [[TMP64]] to i326886; CHECK-NEXT: [[TMP66:%.*]] = mul i32 [[TMP65]], [[TMP46]]6887; CHECK-NEXT: [[TMP67:%.*]] = sub i32 [[TMP45]], [[TMP66]]6888; CHECK-NEXT: [[TMP68:%.*]] = icmp uge i32 [[TMP67]], [[TMP46]]6889; CHECK-NEXT: [[TMP69:%.*]] = sub i32 [[TMP67]], [[TMP46]]6890; CHECK-NEXT: [[TMP70:%.*]] = select i1 [[TMP68]], i32 [[TMP69]], i32 [[TMP67]]6891; CHECK-NEXT: [[TMP71:%.*]] = icmp uge i32 [[TMP70]], [[TMP46]]6892; CHECK-NEXT: [[TMP72:%.*]] = sub i32 [[TMP70]], [[TMP46]]6893; CHECK-NEXT: [[TMP73:%.*]] = select i1 [[TMP71]], i32 [[TMP72]], i32 [[TMP70]]6894; CHECK-NEXT: [[TMP74:%.*]] = xor i32 [[TMP73]], [[TMP41]]6895; CHECK-NEXT: [[TMP75:%.*]] = sub i32 [[TMP74]], [[TMP41]]6896; CHECK-NEXT: [[TMP76:%.*]] = insertelement <2 x i32> [[TMP38]], i32 [[TMP75]], i64 16897; CHECK-NEXT: store <2 x i32> [[TMP76]], ptr addrspace(1) [[OUT:%.*]], align 86898; CHECK-NEXT: ret void6899;6900; GFX6-LABEL: srem_v2i32_pow2_shl_denom:6901; GFX6: ; %bb.0:6902; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb6903; GFX6-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x96904; GFX6-NEXT: s_waitcnt lgkmcnt(0)6905; GFX6-NEXT: s_lshl_b32 s2, 0x1000, s26906; GFX6-NEXT: s_abs_i32 s2, s26907; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s26908; GFX6-NEXT: s_sub_i32 s6, 0, s26909; GFX6-NEXT: s_lshl_b32 s3, 0x1000, s36910; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v06911; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v06912; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v06913; GFX6-NEXT: v_mul_lo_u32 v1, s6, v06914; GFX6-NEXT: s_abs_i32 s6, s06915; GFX6-NEXT: s_ashr_i32 s0, s0, 316916; GFX6-NEXT: v_mul_hi_u32 v1, v0, v16917; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v16918; GFX6-NEXT: v_mul_hi_u32 v0, s6, v06919; GFX6-NEXT: v_readfirstlane_b32 s7, v06920; GFX6-NEXT: s_mul_i32 s7, s7, s26921; GFX6-NEXT: s_sub_i32 s6, s6, s76922; GFX6-NEXT: s_sub_i32 s7, s6, s26923; GFX6-NEXT: s_cmp_ge_u32 s6, s26924; GFX6-NEXT: s_cselect_b32 s6, s7, s66925; GFX6-NEXT: s_sub_i32 s7, s6, s26926; GFX6-NEXT: s_cmp_ge_u32 s6, s26927; GFX6-NEXT: s_cselect_b32 s2, s7, s66928; GFX6-NEXT: s_abs_i32 s3, s36929; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s36930; GFX6-NEXT: s_sub_i32 s6, 0, s36931; GFX6-NEXT: s_abs_i32 s8, s16932; GFX6-NEXT: s_xor_b32 s2, s2, s06933; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v06934; GFX6-NEXT: s_sub_i32 s0, s2, s06935; GFX6-NEXT: s_ashr_i32 s1, s1, 316936; GFX6-NEXT: s_mov_b32 s7, 0xf0006937; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v06938; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v06939; GFX6-NEXT: v_mul_lo_u32 v1, s6, v06940; GFX6-NEXT: s_mov_b32 s6, -16941; GFX6-NEXT: v_mul_hi_u32 v1, v0, v16942; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v16943; GFX6-NEXT: v_mul_hi_u32 v0, s8, v06944; GFX6-NEXT: v_readfirstlane_b32 s2, v06945; GFX6-NEXT: s_mul_i32 s2, s2, s36946; GFX6-NEXT: s_sub_i32 s2, s8, s26947; GFX6-NEXT: s_sub_i32 s8, s2, s36948; GFX6-NEXT: s_cmp_ge_u32 s2, s36949; GFX6-NEXT: s_cselect_b32 s2, s8, s26950; GFX6-NEXT: s_sub_i32 s8, s2, s36951; GFX6-NEXT: s_cmp_ge_u32 s2, s36952; GFX6-NEXT: s_cselect_b32 s2, s8, s26953; GFX6-NEXT: s_xor_b32 s2, s2, s16954; GFX6-NEXT: s_sub_i32 s1, s2, s16955; GFX6-NEXT: v_mov_b32_e32 v0, s06956; GFX6-NEXT: v_mov_b32_e32 v1, s16957; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 06958; GFX6-NEXT: s_endpgm6959;6960; GFX9-LABEL: srem_v2i32_pow2_shl_denom:6961; GFX9: ; %bb.0:6962; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c6963; GFX9-NEXT: v_mov_b32_e32 v2, 06964; GFX9-NEXT: s_waitcnt lgkmcnt(0)6965; GFX9-NEXT: s_lshl_b32 s2, 0x1000, s26966; GFX9-NEXT: s_abs_i32 s2, s26967; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s26968; GFX9-NEXT: s_sub_i32 s7, 0, s26969; GFX9-NEXT: s_ashr_i32 s6, s0, 316970; GFX9-NEXT: s_abs_i32 s0, s06971; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v06972; GFX9-NEXT: s_lshl_b32 s3, 0x1000, s36973; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v06974; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v06975; GFX9-NEXT: v_readfirstlane_b32 s8, v06976; GFX9-NEXT: s_mul_i32 s7, s7, s86977; GFX9-NEXT: s_mul_hi_u32 s7, s8, s76978; GFX9-NEXT: s_add_i32 s8, s8, s76979; GFX9-NEXT: s_mul_hi_u32 s7, s0, s86980; GFX9-NEXT: s_mul_i32 s7, s7, s26981; GFX9-NEXT: s_sub_i32 s0, s0, s76982; GFX9-NEXT: s_sub_i32 s7, s0, s26983; GFX9-NEXT: s_cmp_ge_u32 s0, s26984; GFX9-NEXT: s_cselect_b32 s0, s7, s06985; GFX9-NEXT: s_sub_i32 s7, s0, s26986; GFX9-NEXT: s_cmp_ge_u32 s0, s26987; GFX9-NEXT: s_cselect_b32 s0, s7, s06988; GFX9-NEXT: s_abs_i32 s7, s36989; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s76990; GFX9-NEXT: s_xor_b32 s0, s0, s66991; GFX9-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x246992; GFX9-NEXT: s_sub_i32 s5, 0, s76993; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v06994; GFX9-NEXT: s_sub_i32 s0, s0, s66995; GFX9-NEXT: s_ashr_i32 s4, s1, 316996; GFX9-NEXT: s_abs_i32 s1, s16997; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v06998; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v06999; GFX9-NEXT: v_readfirstlane_b32 s6, v07000; GFX9-NEXT: s_mul_i32 s5, s5, s67001; GFX9-NEXT: s_mul_hi_u32 s5, s6, s57002; GFX9-NEXT: s_add_i32 s6, s6, s57003; GFX9-NEXT: s_mul_hi_u32 s5, s1, s67004; GFX9-NEXT: s_mul_i32 s5, s5, s77005; GFX9-NEXT: s_sub_i32 s1, s1, s57006; GFX9-NEXT: s_sub_i32 s5, s1, s77007; GFX9-NEXT: s_cmp_ge_u32 s1, s77008; GFX9-NEXT: s_cselect_b32 s1, s5, s17009; GFX9-NEXT: s_sub_i32 s5, s1, s77010; GFX9-NEXT: s_cmp_ge_u32 s1, s77011; GFX9-NEXT: s_cselect_b32 s1, s5, s17012; GFX9-NEXT: s_xor_b32 s1, s1, s47013; GFX9-NEXT: s_sub_i32 s1, s1, s47014; GFX9-NEXT: v_mov_b32_e32 v0, s07015; GFX9-NEXT: v_mov_b32_e32 v1, s17016; GFX9-NEXT: s_waitcnt lgkmcnt(0)7017; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]7018; GFX9-NEXT: s_endpgm7019 %shl.y = shl <2 x i32> <i32 4096, i32 4096>, %y7020 %r = srem <2 x i32> %x, %shl.y7021 store <2 x i32> %r, ptr addrspace(1) %out7022 ret void7023}7024 7025define amdgpu_kernel void @udiv_i64_oddk_denom(ptr addrspace(1) %out, i64 %x) {7026; CHECK-LABEL: @udiv_i64_oddk_denom(7027; CHECK-NEXT: [[R:%.*]] = udiv i64 [[X:%.*]], 12351959499437028; CHECK-NEXT: store i64 [[R]], ptr addrspace(1) [[OUT:%.*]], align 87029; CHECK-NEXT: ret void7030;7031; GFX6-LABEL: udiv_i64_oddk_denom:7032; GFX6: ; %bb.0:7033; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x97034; GFX6-NEXT: v_mov_b32_e32 v1, 0x64c139ef7035; GFX6-NEXT: v_mov_b32_e32 v0, 0x38f83e57036; GFX6-NEXT: s_mov_b32 s7, 0xf0007037; GFX6-NEXT: s_mov_b32 s6, -17038; GFX6-NEXT: s_waitcnt lgkmcnt(0)7039; GFX6-NEXT: v_mul_hi_u32 v4, s2, v17040; GFX6-NEXT: v_mul_hi_u32 v3, s3, v17041; GFX6-NEXT: s_mov_b32 s5, s17042; GFX6-NEXT: v_mul_hi_u32 v2, s2, v07043; GFX6-NEXT: s_mul_i32 s1, s3, 0x64c139ef7044; GFX6-NEXT: v_add_i32_e32 v4, vcc, s1, v47045; GFX6-NEXT: s_mov_b32 s4, s07046; GFX6-NEXT: s_mul_i32 s0, s2, 0x38f83e57047; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc7048; GFX6-NEXT: v_add_i32_e32 v4, vcc, s0, v47049; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc7050; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v27051; GFX6-NEXT: v_mul_hi_u32 v0, s3, v07052; GFX6-NEXT: v_addc_u32_e64 v3, s[0:1], 0, 0, vcc7053; GFX6-NEXT: s_mul_i32 s0, s3, 0x38f83e57054; GFX6-NEXT: v_add_i32_e32 v2, vcc, s0, v27055; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v0, v3, vcc7056; GFX6-NEXT: v_mov_b32_e32 v1, 07057; GFX6-NEXT: v_lshrrev_b32_e32 v0, 2, v07058; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 07059; GFX6-NEXT: s_endpgm7060;7061; GFX9-LABEL: udiv_i64_oddk_denom:7062; GFX9: ; %bb.0:7063; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x247064; GFX9-NEXT: v_mov_b32_e32 v1, 07065; GFX9-NEXT: s_waitcnt lgkmcnt(0)7066; GFX9-NEXT: s_mul_hi_u32 s4, s2, 0x38f83e57067; GFX9-NEXT: s_mul_i32 s5, s2, 0x38f83e57068; GFX9-NEXT: s_mul_i32 s7, s3, 0x64c139ef7069; GFX9-NEXT: s_mul_hi_u32 s2, s2, 0x64c139ef7070; GFX9-NEXT: s_mul_hi_u32 s6, s3, 0x64c139ef7071; GFX9-NEXT: s_add_u32 s2, s7, s27072; GFX9-NEXT: s_addc_u32 s6, s6, 07073; GFX9-NEXT: s_add_u32 s2, s5, s27074; GFX9-NEXT: s_addc_u32 s2, s4, 07075; GFX9-NEXT: s_add_u32 s2, s6, s27076; GFX9-NEXT: s_addc_u32 s4, 0, 07077; GFX9-NEXT: s_mul_hi_u32 s5, s3, 0x38f83e57078; GFX9-NEXT: s_mul_i32 s3, s3, 0x38f83e57079; GFX9-NEXT: s_add_u32 s2, s3, s27080; GFX9-NEXT: s_addc_u32 s2, s5, s47081; GFX9-NEXT: s_lshr_b32 s2, s2, 27082; GFX9-NEXT: v_mov_b32_e32 v0, s27083; GFX9-NEXT: global_store_dwordx2 v1, v[0:1], s[0:1]7084; GFX9-NEXT: s_endpgm7085 %r = udiv i64 %x, 12351959499437086 store i64 %r, ptr addrspace(1) %out7087 ret void7088}7089 7090define amdgpu_kernel void @udiv_i64_pow2k_denom(ptr addrspace(1) %out, i64 %x) {7091; CHECK-LABEL: @udiv_i64_pow2k_denom(7092; CHECK-NEXT: [[R:%.*]] = udiv i64 [[X:%.*]], 40967093; CHECK-NEXT: store i64 [[R]], ptr addrspace(1) [[OUT:%.*]], align 87094; CHECK-NEXT: ret void7095;7096; GFX6-LABEL: udiv_i64_pow2k_denom:7097; GFX6: ; %bb.0:7098; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x97099; GFX6-NEXT: s_mov_b32 s7, 0xf0007100; GFX6-NEXT: s_mov_b32 s6, -17101; GFX6-NEXT: s_waitcnt lgkmcnt(0)7102; GFX6-NEXT: s_mov_b32 s4, s07103; GFX6-NEXT: s_mov_b32 s5, s17104; GFX6-NEXT: s_lshr_b64 s[0:1], s[2:3], 127105; GFX6-NEXT: v_mov_b32_e32 v0, s07106; GFX6-NEXT: v_mov_b32_e32 v1, s17107; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 07108; GFX6-NEXT: s_endpgm7109;7110; GFX9-LABEL: udiv_i64_pow2k_denom:7111; GFX9: ; %bb.0:7112; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x247113; GFX9-NEXT: v_mov_b32_e32 v2, 07114; GFX9-NEXT: s_waitcnt lgkmcnt(0)7115; GFX9-NEXT: s_lshr_b64 s[2:3], s[2:3], 127116; GFX9-NEXT: v_mov_b32_e32 v0, s27117; GFX9-NEXT: v_mov_b32_e32 v1, s37118; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]7119; GFX9-NEXT: s_endpgm7120 %r = udiv i64 %x, 40967121 store i64 %r, ptr addrspace(1) %out7122 ret void7123}7124 7125define amdgpu_kernel void @udiv_i64_pow2_shl_denom(ptr addrspace(1) %out, i64 %x, i64 %y) {7126; CHECK-LABEL: @udiv_i64_pow2_shl_denom(7127; CHECK-NEXT: [[SHL_Y:%.*]] = shl i64 4096, [[Y:%.*]]7128; CHECK-NEXT: [[R:%.*]] = udiv i64 [[X:%.*]], [[SHL_Y]]7129; CHECK-NEXT: store i64 [[R]], ptr addrspace(1) [[OUT:%.*]], align 87130; CHECK-NEXT: ret void7131;7132; GFX6-LABEL: udiv_i64_pow2_shl_denom:7133; GFX6: ; %bb.0:7134; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x97135; GFX6-NEXT: s_load_dword s8, s[4:5], 0xd7136; GFX6-NEXT: s_mov_b32 s7, 0xf0007137; GFX6-NEXT: s_mov_b32 s6, -17138; GFX6-NEXT: s_waitcnt lgkmcnt(0)7139; GFX6-NEXT: s_mov_b32 s4, s07140; GFX6-NEXT: s_add_i32 s8, s8, 127141; GFX6-NEXT: s_mov_b32 s5, s17142; GFX6-NEXT: s_lshr_b64 s[0:1], s[2:3], s87143; GFX6-NEXT: v_mov_b32_e32 v0, s07144; GFX6-NEXT: v_mov_b32_e32 v1, s17145; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 07146; GFX6-NEXT: s_endpgm7147;7148; GFX9-LABEL: udiv_i64_pow2_shl_denom:7149; GFX9: ; %bb.0:7150; GFX9-NEXT: s_load_dword s6, s[4:5], 0x347151; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x247152; GFX9-NEXT: v_mov_b32_e32 v2, 07153; GFX9-NEXT: s_waitcnt lgkmcnt(0)7154; GFX9-NEXT: s_add_i32 s6, s6, 127155; GFX9-NEXT: s_lshr_b64 s[2:3], s[2:3], s67156; GFX9-NEXT: v_mov_b32_e32 v0, s27157; GFX9-NEXT: v_mov_b32_e32 v1, s37158; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]7159; GFX9-NEXT: s_endpgm7160 %shl.y = shl i64 4096, %y7161 %r = udiv i64 %x, %shl.y7162 store i64 %r, ptr addrspace(1) %out7163 ret void7164}7165 7166define amdgpu_kernel void @udiv_v2i64_pow2k_denom(ptr addrspace(1) %out, <2 x i64> %x) {7167; CHECK-LABEL: @udiv_v2i64_pow2k_denom(7168; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i64> [[X:%.*]], i64 07169; CHECK-NEXT: [[TMP2:%.*]] = udiv i64 [[TMP1]], 40967170; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i64> poison, i64 [[TMP2]], i64 07171; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[X]], i64 17172; CHECK-NEXT: [[TMP5:%.*]] = udiv i64 [[TMP4]], 40967173; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i64> [[TMP3]], i64 [[TMP5]], i64 17174; CHECK-NEXT: store <2 x i64> [[TMP6]], ptr addrspace(1) [[OUT:%.*]], align 167175; CHECK-NEXT: ret void7176;7177; GFX6-LABEL: udiv_v2i64_pow2k_denom:7178; GFX6: ; %bb.0:7179; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xd7180; GFX6-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x97181; GFX6-NEXT: s_mov_b32 s7, 0xf0007182; GFX6-NEXT: s_mov_b32 s6, -17183; GFX6-NEXT: s_waitcnt lgkmcnt(0)7184; GFX6-NEXT: s_lshr_b64 s[0:1], s[0:1], 127185; GFX6-NEXT: s_lshr_b64 s[2:3], s[2:3], 127186; GFX6-NEXT: v_mov_b32_e32 v0, s07187; GFX6-NEXT: v_mov_b32_e32 v1, s17188; GFX6-NEXT: v_mov_b32_e32 v2, s27189; GFX6-NEXT: v_mov_b32_e32 v3, s37190; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 07191; GFX6-NEXT: s_endpgm7192;7193; GFX9-LABEL: udiv_v2i64_pow2k_denom:7194; GFX9: ; %bb.0:7195; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x347196; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x247197; GFX9-NEXT: v_mov_b32_e32 v4, 07198; GFX9-NEXT: s_waitcnt lgkmcnt(0)7199; GFX9-NEXT: s_lshr_b64 s[0:1], s[0:1], 127200; GFX9-NEXT: s_lshr_b64 s[2:3], s[2:3], 127201; GFX9-NEXT: v_mov_b32_e32 v0, s07202; GFX9-NEXT: v_mov_b32_e32 v1, s17203; GFX9-NEXT: v_mov_b32_e32 v2, s27204; GFX9-NEXT: v_mov_b32_e32 v3, s37205; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7]7206; GFX9-NEXT: s_endpgm7207 %r = udiv <2 x i64> %x, <i64 4096, i64 4096>7208 store <2 x i64> %r, ptr addrspace(1) %out7209 ret void7210}7211 7212define amdgpu_kernel void @udiv_v2i64_mixed_pow2k_denom(ptr addrspace(1) %out, <2 x i64> %x) {7213; CHECK-LABEL: @udiv_v2i64_mixed_pow2k_denom(7214; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i64> [[X:%.*]], i64 07215; CHECK-NEXT: [[TMP2:%.*]] = udiv i64 [[TMP1]], 40967216; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i64> poison, i64 [[TMP2]], i64 07217; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[X]], i64 17218; CHECK-NEXT: [[TMP5:%.*]] = udiv i64 [[TMP4]], 40957219; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i64> [[TMP3]], i64 [[TMP5]], i64 17220; CHECK-NEXT: store <2 x i64> [[TMP6]], ptr addrspace(1) [[OUT:%.*]], align 167221; CHECK-NEXT: ret void7222;7223; GFX6-LABEL: udiv_v2i64_mixed_pow2k_denom:7224; GFX6: ; %bb.0:7225; GFX6-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0xd7226; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x97227; GFX6-NEXT: v_mov_b32_e32 v2, 0x100100117228; GFX6-NEXT: v_mov_b32_e32 v0, 0x1001007229; GFX6-NEXT: s_mov_b32 s3, 0xf0007230; GFX6-NEXT: s_waitcnt lgkmcnt(0)7231; GFX6-NEXT: v_mul_hi_u32 v3, s10, v27232; GFX6-NEXT: v_mul_hi_u32 v2, s11, v27233; GFX6-NEXT: v_mul_hi_u32 v1, s10, v07234; GFX6-NEXT: s_mul_i32 s7, s11, 0x100100117235; GFX6-NEXT: v_add_i32_e32 v3, vcc, s7, v37236; GFX6-NEXT: s_mul_i32 s6, s10, 0x1001007237; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc7238; GFX6-NEXT: v_add_i32_e32 v3, vcc, s6, v37239; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc7240; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v17241; GFX6-NEXT: v_mul_hi_u32 v0, s11, v07242; GFX6-NEXT: v_addc_u32_e64 v2, s[6:7], 0, 0, vcc7243; GFX6-NEXT: s_mul_i32 s6, s11, 0x1001007244; GFX6-NEXT: v_add_i32_e32 v3, vcc, s6, v17245; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v0, v2, vcc7246; GFX6-NEXT: v_mov_b32_e32 v1, s117247; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s10, v37248; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc7249; GFX6-NEXT: v_lshr_b64 v[0:1], v[0:1], 17250; GFX6-NEXT: s_lshr_b64 s[4:5], s[8:9], 127251; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v37252; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc7253; GFX6-NEXT: v_lshr_b64 v[2:3], v[0:1], 117254; GFX6-NEXT: s_mov_b32 s2, -17255; GFX6-NEXT: v_mov_b32_e32 v0, s47256; GFX6-NEXT: v_mov_b32_e32 v1, s57257; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 07258; GFX6-NEXT: s_endpgm7259;7260; GFX9-LABEL: udiv_v2i64_mixed_pow2k_denom:7261; GFX9: ; %bb.0:7262; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x347263; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x247264; GFX9-NEXT: v_mov_b32_e32 v4, 07265; GFX9-NEXT: s_waitcnt lgkmcnt(0)7266; GFX9-NEXT: s_lshr_b64 s[0:1], s[0:1], 127267; GFX9-NEXT: s_mul_i32 s9, s3, 0x100100117268; GFX9-NEXT: s_mul_hi_u32 s10, s2, 0x100100117269; GFX9-NEXT: s_mul_hi_u32 s8, s3, 0x100100117270; GFX9-NEXT: s_add_u32 s9, s9, s107271; GFX9-NEXT: s_mul_i32 s5, s2, 0x1001007272; GFX9-NEXT: s_addc_u32 s8, s8, 07273; GFX9-NEXT: s_mul_hi_u32 s4, s2, 0x1001007274; GFX9-NEXT: s_add_u32 s5, s5, s97275; GFX9-NEXT: s_addc_u32 s4, s4, 07276; GFX9-NEXT: s_add_u32 s4, s8, s47277; GFX9-NEXT: s_addc_u32 s5, 0, 07278; GFX9-NEXT: s_mul_i32 s9, s3, 0x1001007279; GFX9-NEXT: s_mul_hi_u32 s8, s3, 0x1001007280; GFX9-NEXT: s_add_u32 s4, s9, s47281; GFX9-NEXT: s_addc_u32 s5, s8, s57282; GFX9-NEXT: s_sub_u32 s2, s2, s47283; GFX9-NEXT: s_subb_u32 s3, s3, s57284; GFX9-NEXT: s_lshr_b64 s[2:3], s[2:3], 17285; GFX9-NEXT: s_add_u32 s2, s2, s47286; GFX9-NEXT: s_addc_u32 s3, s3, s57287; GFX9-NEXT: s_lshr_b64 s[2:3], s[2:3], 117288; GFX9-NEXT: v_mov_b32_e32 v0, s07289; GFX9-NEXT: v_mov_b32_e32 v1, s17290; GFX9-NEXT: v_mov_b32_e32 v2, s27291; GFX9-NEXT: v_mov_b32_e32 v3, s37292; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7]7293; GFX9-NEXT: s_endpgm7294 %r = udiv <2 x i64> %x, <i64 4096, i64 4095>7295 store <2 x i64> %r, ptr addrspace(1) %out7296 ret void7297}7298 7299define amdgpu_kernel void @udiv_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x i64> %x, <2 x i64> %y) {7300; CHECK-LABEL: @udiv_v2i64_pow2_shl_denom(7301; CHECK-NEXT: [[SHL_Y:%.*]] = shl <2 x i64> splat (i64 4096), [[Y:%.*]]7302; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i64> [[X:%.*]], i64 07303; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 07304; CHECK-NEXT: [[TMP3:%.*]] = udiv i64 [[TMP1]], [[TMP2]]7305; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i64> poison, i64 [[TMP3]], i64 07306; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i64> [[X]], i64 17307; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 17308; CHECK-NEXT: [[TMP7:%.*]] = udiv i64 [[TMP5]], [[TMP6]]7309; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x i64> [[TMP4]], i64 [[TMP7]], i64 17310; CHECK-NEXT: store <2 x i64> [[TMP8]], ptr addrspace(1) [[OUT:%.*]], align 167311; CHECK-NEXT: ret void7312;7313; GFX6-LABEL: udiv_v2i64_pow2_shl_denom:7314; GFX6: ; %bb.0:7315; GFX6-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0xd7316; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x97317; GFX6-NEXT: s_mov_b32 s3, 0xf0007318; GFX6-NEXT: s_mov_b32 s2, -17319; GFX6-NEXT: s_waitcnt lgkmcnt(0)7320; GFX6-NEXT: s_add_i32 s4, s12, 127321; GFX6-NEXT: s_add_i32 s6, s14, 127322; GFX6-NEXT: s_lshr_b64 s[4:5], s[8:9], s47323; GFX6-NEXT: s_lshr_b64 s[6:7], s[10:11], s67324; GFX6-NEXT: v_mov_b32_e32 v0, s47325; GFX6-NEXT: v_mov_b32_e32 v1, s57326; GFX6-NEXT: v_mov_b32_e32 v2, s67327; GFX6-NEXT: v_mov_b32_e32 v3, s77328; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 07329; GFX6-NEXT: s_endpgm7330;7331; GFX9-LABEL: udiv_v2i64_pow2_shl_denom:7332; GFX9: ; %bb.0:7333; GFX9-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x347334; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x247335; GFX9-NEXT: v_mov_b32_e32 v4, 07336; GFX9-NEXT: s_waitcnt lgkmcnt(0)7337; GFX9-NEXT: s_add_i32 s2, s12, 127338; GFX9-NEXT: s_add_i32 s4, s14, 127339; GFX9-NEXT: s_lshr_b64 s[2:3], s[8:9], s27340; GFX9-NEXT: s_lshr_b64 s[4:5], s[10:11], s47341; GFX9-NEXT: v_mov_b32_e32 v0, s27342; GFX9-NEXT: v_mov_b32_e32 v1, s37343; GFX9-NEXT: v_mov_b32_e32 v2, s47344; GFX9-NEXT: v_mov_b32_e32 v3, s57345; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]7346; GFX9-NEXT: s_endpgm7347 %shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y7348 %r = udiv <2 x i64> %x, %shl.y7349 store <2 x i64> %r, ptr addrspace(1) %out7350 ret void7351}7352 7353define amdgpu_kernel void @urem_i64_oddk_denom(ptr addrspace(1) %out, i64 %x) {7354; CHECK-LABEL: @urem_i64_oddk_denom(7355; CHECK-NEXT: [[R:%.*]] = urem i64 [[X:%.*]], 12351953939937356; CHECK-NEXT: store i64 [[R]], ptr addrspace(1) [[OUT:%.*]], align 87357; CHECK-NEXT: ret void7358;7359; GFX6-LABEL: urem_i64_oddk_denom:7360; GFX6: ; %bb.0:7361; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x97362; GFX6-NEXT: v_mov_b32_e32 v2, 0xf68411397363; GFX6-NEXT: v_mov_b32_e32 v0, 0xe3e100117364; GFX6-NEXT: s_mov_b32 s7, 0xf0007365; GFX6-NEXT: s_mov_b32 s6, -17366; GFX6-NEXT: s_waitcnt lgkmcnt(0)7367; GFX6-NEXT: v_mul_hi_u32 v3, s2, v27368; GFX6-NEXT: v_mul_hi_u32 v2, s3, v27369; GFX6-NEXT: v_mul_hi_u32 v1, s2, v07370; GFX6-NEXT: s_mul_i32 s5, s3, 0xf68411397371; GFX6-NEXT: v_add_i32_e32 v3, vcc, s5, v37372; GFX6-NEXT: s_mov_b32 s4, s07373; GFX6-NEXT: s_mul_i32 s0, s2, 0xe3e100117374; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc7375; GFX6-NEXT: v_add_i32_e32 v3, vcc, s0, v37376; GFX6-NEXT: v_mul_hi_u32 v0, s3, v07377; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc7378; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v17379; GFX6-NEXT: s_mul_i32 s0, s3, 0xe3e100117380; GFX6-NEXT: v_addc_u32_e64 v2, s[8:9], 0, 0, vcc7381; GFX6-NEXT: v_add_i32_e32 v1, vcc, s0, v17382; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v0, v2, vcc7383; GFX6-NEXT: v_lshrrev_b32_e32 v0, 8, v07384; GFX6-NEXT: s_movk_i32 s0, 0x11f7385; GFX6-NEXT: v_mul_lo_u32 v1, v0, s07386; GFX6-NEXT: s_mov_b32 s0, 0x9761f7c97387; GFX6-NEXT: v_mul_hi_u32 v2, v0, s07388; GFX6-NEXT: v_mul_lo_u32 v0, v0, s07389; GFX6-NEXT: s_mov_b32 s5, s17390; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v27391; GFX6-NEXT: v_mov_b32_e32 v2, s37392; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s2, v07393; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc7394; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 07395; GFX6-NEXT: s_endpgm7396;7397; GFX9-LABEL: urem_i64_oddk_denom:7398; GFX9: ; %bb.0:7399; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x247400; GFX9-NEXT: v_mov_b32_e32 v2, 07401; GFX9-NEXT: s_waitcnt lgkmcnt(0)7402; GFX9-NEXT: s_mul_i32 s7, s3, 0xf68411397403; GFX9-NEXT: s_mul_hi_u32 s8, s2, 0xf68411397404; GFX9-NEXT: s_mul_hi_u32 s6, s3, 0xf68411397405; GFX9-NEXT: s_add_u32 s7, s7, s87406; GFX9-NEXT: s_mul_i32 s5, s2, 0xe3e100117407; GFX9-NEXT: s_addc_u32 s6, s6, 07408; GFX9-NEXT: s_mul_hi_u32 s4, s2, 0xe3e100117409; GFX9-NEXT: s_add_u32 s5, s5, s77410; GFX9-NEXT: s_addc_u32 s4, s4, 07411; GFX9-NEXT: s_add_u32 s4, s6, s47412; GFX9-NEXT: s_addc_u32 s5, 0, 07413; GFX9-NEXT: s_mul_i32 s7, s3, 0xe3e100117414; GFX9-NEXT: s_mul_hi_u32 s6, s3, 0xe3e100117415; GFX9-NEXT: s_add_u32 s4, s7, s47416; GFX9-NEXT: s_addc_u32 s4, s6, s57417; GFX9-NEXT: s_lshr_b32 s4, s4, 87418; GFX9-NEXT: s_mul_i32 s5, s4, 0x11f7419; GFX9-NEXT: s_mul_hi_u32 s6, s4, 0x9761f7c97420; GFX9-NEXT: s_add_i32 s6, s6, s57421; GFX9-NEXT: s_mul_i32 s4, s4, 0x9761f7c97422; GFX9-NEXT: s_sub_u32 s2, s2, s47423; GFX9-NEXT: s_subb_u32 s3, s3, s67424; GFX9-NEXT: v_mov_b32_e32 v0, s27425; GFX9-NEXT: v_mov_b32_e32 v1, s37426; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]7427; GFX9-NEXT: s_endpgm7428 %r = urem i64 %x, 12351953939937429 store i64 %r, ptr addrspace(1) %out7430 ret void7431}7432 7433define amdgpu_kernel void @urem_i64_pow2k_denom(ptr addrspace(1) %out, i64 %x) {7434; CHECK-LABEL: @urem_i64_pow2k_denom(7435; CHECK-NEXT: [[R:%.*]] = urem i64 [[X:%.*]], 40967436; CHECK-NEXT: store i64 [[R]], ptr addrspace(1) [[OUT:%.*]], align 87437; CHECK-NEXT: ret void7438;7439; GFX6-LABEL: urem_i64_pow2k_denom:7440; GFX6: ; %bb.0:7441; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x97442; GFX6-NEXT: s_mov_b32 s7, 0xf0007443; GFX6-NEXT: s_mov_b32 s6, -17444; GFX6-NEXT: v_mov_b32_e32 v1, 07445; GFX6-NEXT: s_waitcnt lgkmcnt(0)7446; GFX6-NEXT: s_mov_b32 s4, s07447; GFX6-NEXT: s_and_b32 s0, s2, 0xfff7448; GFX6-NEXT: s_mov_b32 s5, s17449; GFX6-NEXT: v_mov_b32_e32 v0, s07450; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 07451; GFX6-NEXT: s_endpgm7452;7453; GFX9-LABEL: urem_i64_pow2k_denom:7454; GFX9: ; %bb.0:7455; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x247456; GFX9-NEXT: v_mov_b32_e32 v1, 07457; GFX9-NEXT: s_waitcnt lgkmcnt(0)7458; GFX9-NEXT: s_and_b32 s2, s2, 0xfff7459; GFX9-NEXT: v_mov_b32_e32 v0, s27460; GFX9-NEXT: global_store_dwordx2 v1, v[0:1], s[0:1]7461; GFX9-NEXT: s_endpgm7462 %r = urem i64 %x, 40967463 store i64 %r, ptr addrspace(1) %out7464 ret void7465}7466 7467define amdgpu_kernel void @urem_i64_pow2_shl_denom(ptr addrspace(1) %out, i64 %x, i64 %y) {7468; CHECK-LABEL: @urem_i64_pow2_shl_denom(7469; CHECK-NEXT: [[SHL_Y:%.*]] = shl i64 4096, [[Y:%.*]]7470; CHECK-NEXT: [[R:%.*]] = urem i64 [[X:%.*]], [[SHL_Y]]7471; CHECK-NEXT: store i64 [[R]], ptr addrspace(1) [[OUT:%.*]], align 87472; CHECK-NEXT: ret void7473;7474; GFX6-LABEL: urem_i64_pow2_shl_denom:7475; GFX6: ; %bb.0:7476; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x97477; GFX6-NEXT: s_load_dword s8, s[4:5], 0xd7478; GFX6-NEXT: s_mov_b32 s7, 0xf0007479; GFX6-NEXT: s_mov_b32 s6, -17480; GFX6-NEXT: s_waitcnt lgkmcnt(0)7481; GFX6-NEXT: s_mov_b32 s4, s07482; GFX6-NEXT: s_mov_b32 s5, s17483; GFX6-NEXT: s_lshl_b64 s[0:1], 0x1000, s87484; GFX6-NEXT: s_add_u32 s0, s0, -17485; GFX6-NEXT: s_addc_u32 s1, s1, -17486; GFX6-NEXT: s_and_b64 s[0:1], s[2:3], s[0:1]7487; GFX6-NEXT: v_mov_b32_e32 v0, s07488; GFX6-NEXT: v_mov_b32_e32 v1, s17489; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 07490; GFX6-NEXT: s_endpgm7491;7492; GFX9-LABEL: urem_i64_pow2_shl_denom:7493; GFX9: ; %bb.0:7494; GFX9-NEXT: s_load_dword s6, s[4:5], 0x347495; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x247496; GFX9-NEXT: v_mov_b32_e32 v2, 07497; GFX9-NEXT: s_waitcnt lgkmcnt(0)7498; GFX9-NEXT: s_lshl_b64 s[4:5], 0x1000, s67499; GFX9-NEXT: s_add_u32 s4, s4, -17500; GFX9-NEXT: s_addc_u32 s5, s5, -17501; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], s[4:5]7502; GFX9-NEXT: v_mov_b32_e32 v0, s27503; GFX9-NEXT: v_mov_b32_e32 v1, s37504; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]7505; GFX9-NEXT: s_endpgm7506 %shl.y = shl i64 4096, %y7507 %r = urem i64 %x, %shl.y7508 store i64 %r, ptr addrspace(1) %out7509 ret void7510}7511 7512define amdgpu_kernel void @urem_v2i64_pow2k_denom(ptr addrspace(1) %out, <2 x i64> %x) {7513; CHECK-LABEL: @urem_v2i64_pow2k_denom(7514; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i64> [[X:%.*]], i64 07515; CHECK-NEXT: [[TMP2:%.*]] = urem i64 [[TMP1]], 40967516; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i64> poison, i64 [[TMP2]], i64 07517; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[X]], i64 17518; CHECK-NEXT: [[TMP5:%.*]] = urem i64 [[TMP4]], 40967519; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i64> [[TMP3]], i64 [[TMP5]], i64 17520; CHECK-NEXT: store <2 x i64> [[TMP6]], ptr addrspace(1) [[OUT:%.*]], align 167521; CHECK-NEXT: ret void7522;7523; GFX6-LABEL: urem_v2i64_pow2k_denom:7524; GFX6: ; %bb.0:7525; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xd7526; GFX6-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x97527; GFX6-NEXT: v_mov_b32_e32 v1, 07528; GFX6-NEXT: s_mov_b32 s7, 0xf0007529; GFX6-NEXT: s_mov_b32 s6, -17530; GFX6-NEXT: s_waitcnt lgkmcnt(0)7531; GFX6-NEXT: s_and_b32 s0, s0, 0xfff7532; GFX6-NEXT: s_and_b32 s1, s2, 0xfff7533; GFX6-NEXT: v_mov_b32_e32 v0, s07534; GFX6-NEXT: v_mov_b32_e32 v2, s17535; GFX6-NEXT: v_mov_b32_e32 v3, v17536; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 07537; GFX6-NEXT: s_endpgm7538;7539; GFX9-LABEL: urem_v2i64_pow2k_denom:7540; GFX9: ; %bb.0:7541; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x347542; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x247543; GFX9-NEXT: v_mov_b32_e32 v1, 07544; GFX9-NEXT: v_mov_b32_e32 v3, v17545; GFX9-NEXT: s_waitcnt lgkmcnt(0)7546; GFX9-NEXT: s_and_b32 s0, s0, 0xfff7547; GFX9-NEXT: s_and_b32 s1, s2, 0xfff7548; GFX9-NEXT: v_mov_b32_e32 v0, s07549; GFX9-NEXT: v_mov_b32_e32 v2, s17550; GFX9-NEXT: global_store_dwordx4 v1, v[0:3], s[6:7]7551; GFX9-NEXT: s_endpgm7552 %r = urem <2 x i64> %x, <i64 4096, i64 4096>7553 store <2 x i64> %r, ptr addrspace(1) %out7554 ret void7555}7556 7557define amdgpu_kernel void @urem_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x i64> %x, <2 x i64> %y) {7558; CHECK-LABEL: @urem_v2i64_pow2_shl_denom(7559; CHECK-NEXT: [[SHL_Y:%.*]] = shl <2 x i64> splat (i64 4096), [[Y:%.*]]7560; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i64> [[X:%.*]], i64 07561; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 07562; CHECK-NEXT: [[TMP3:%.*]] = urem i64 [[TMP1]], [[TMP2]]7563; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i64> poison, i64 [[TMP3]], i64 07564; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i64> [[X]], i64 17565; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 17566; CHECK-NEXT: [[TMP7:%.*]] = urem i64 [[TMP5]], [[TMP6]]7567; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x i64> [[TMP4]], i64 [[TMP7]], i64 17568; CHECK-NEXT: store <2 x i64> [[TMP8]], ptr addrspace(1) [[OUT:%.*]], align 167569; CHECK-NEXT: ret void7570;7571; GFX6-LABEL: urem_v2i64_pow2_shl_denom:7572; GFX6: ; %bb.0:7573; GFX6-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0xd7574; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x97575; GFX6-NEXT: s_mov_b32 s3, 0xf0007576; GFX6-NEXT: s_mov_b32 s2, -17577; GFX6-NEXT: s_waitcnt lgkmcnt(0)7578; GFX6-NEXT: s_lshl_b64 s[4:5], 0x1000, s147579; GFX6-NEXT: s_lshl_b64 s[6:7], 0x1000, s127580; GFX6-NEXT: s_add_u32 s6, s6, -17581; GFX6-NEXT: s_addc_u32 s7, s7, -17582; GFX6-NEXT: s_and_b64 s[6:7], s[8:9], s[6:7]7583; GFX6-NEXT: s_add_u32 s4, s4, -17584; GFX6-NEXT: s_addc_u32 s5, s5, -17585; GFX6-NEXT: s_and_b64 s[4:5], s[10:11], s[4:5]7586; GFX6-NEXT: v_mov_b32_e32 v0, s67587; GFX6-NEXT: v_mov_b32_e32 v1, s77588; GFX6-NEXT: v_mov_b32_e32 v2, s47589; GFX6-NEXT: v_mov_b32_e32 v3, s57590; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 07591; GFX6-NEXT: s_endpgm7592;7593; GFX9-LABEL: urem_v2i64_pow2_shl_denom:7594; GFX9: ; %bb.0:7595; GFX9-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x347596; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x247597; GFX9-NEXT: v_mov_b32_e32 v4, 07598; GFX9-NEXT: s_waitcnt lgkmcnt(0)7599; GFX9-NEXT: s_lshl_b64 s[2:3], 0x1000, s147600; GFX9-NEXT: s_lshl_b64 s[4:5], 0x1000, s127601; GFX9-NEXT: s_add_u32 s4, s4, -17602; GFX9-NEXT: s_addc_u32 s5, s5, -17603; GFX9-NEXT: s_and_b64 s[4:5], s[8:9], s[4:5]7604; GFX9-NEXT: s_add_u32 s2, s2, -17605; GFX9-NEXT: s_addc_u32 s3, s3, -17606; GFX9-NEXT: s_and_b64 s[2:3], s[10:11], s[2:3]7607; GFX9-NEXT: v_mov_b32_e32 v0, s47608; GFX9-NEXT: v_mov_b32_e32 v1, s57609; GFX9-NEXT: v_mov_b32_e32 v2, s27610; GFX9-NEXT: v_mov_b32_e32 v3, s37611; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]7612; GFX9-NEXT: s_endpgm7613 %shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y7614 %r = urem <2 x i64> %x, %shl.y7615 store <2 x i64> %r, ptr addrspace(1) %out7616 ret void7617}7618 7619define amdgpu_kernel void @sdiv_i64_oddk_denom(ptr addrspace(1) %out, i64 %x) {7620; CHECK-LABEL: @sdiv_i64_oddk_denom(7621; CHECK-NEXT: [[R:%.*]] = sdiv i64 [[X:%.*]], 12351957622; CHECK-NEXT: store i64 [[R]], ptr addrspace(1) [[OUT:%.*]], align 87623; CHECK-NEXT: ret void7624;7625; GFX6-LABEL: sdiv_i64_oddk_denom:7626; GFX6: ; %bb.0:7627; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x97628; GFX6-NEXT: v_mov_b32_e32 v2, 0xfd81e197629; GFX6-NEXT: v_mov_b32_e32 v0, 0x6ca942207630; GFX6-NEXT: s_mov_b32 s7, 0xf0007631; GFX6-NEXT: s_mov_b32 s6, -17632; GFX6-NEXT: s_waitcnt lgkmcnt(0)7633; GFX6-NEXT: v_mul_hi_u32 v3, s2, v27634; GFX6-NEXT: v_mul_hi_u32 v4, s3, v27635; GFX6-NEXT: s_mov_b32 s5, s17636; GFX6-NEXT: v_mul_hi_u32 v1, s2, v07637; GFX6-NEXT: s_mul_i32 s1, s3, 0xfd81e197638; GFX6-NEXT: v_add_i32_e32 v3, vcc, s1, v37639; GFX6-NEXT: s_mov_b32 s4, s07640; GFX6-NEXT: s_mul_i32 s0, s2, 0x6ca942207641; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc7642; GFX6-NEXT: v_add_i32_e32 v3, vcc, s0, v37643; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc7644; GFX6-NEXT: v_add_i32_e32 v1, vcc, v4, v17645; GFX6-NEXT: v_addc_u32_e64 v3, s[0:1], 0, 0, vcc7646; GFX6-NEXT: s_ashr_i32 s1, s3, 317647; GFX6-NEXT: v_mul_hi_u32 v0, s3, v07648; GFX6-NEXT: v_mul_hi_u32 v2, s1, v27649; GFX6-NEXT: s_mul_i32 s0, s3, 0x6ca942207650; GFX6-NEXT: v_add_i32_e32 v1, vcc, s0, v17651; GFX6-NEXT: s_mul_i32 s0, s1, 0x6ca942207652; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v0, v3, vcc7653; GFX6-NEXT: v_add_i32_e32 v0, vcc, s0, v27654; GFX6-NEXT: s_mul_i32 s1, s1, 0xfd81e197655; GFX6-NEXT: v_add_i32_e32 v2, vcc, s1, v07656; GFX6-NEXT: v_add_i32_e32 v0, vcc, s1, v17657; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v3, v2, vcc7658; GFX6-NEXT: v_ashr_i64 v[2:3], v[0:1], 197659; GFX6-NEXT: v_lshrrev_b32_e32 v0, 31, v17660; GFX6-NEXT: v_add_i32_e32 v0, vcc, v2, v07661; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc7662; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 07663; GFX6-NEXT: s_endpgm7664;7665; GFX9-LABEL: sdiv_i64_oddk_denom:7666; GFX9: ; %bb.0:7667; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x247668; GFX9-NEXT: v_mov_b32_e32 v2, 07669; GFX9-NEXT: s_waitcnt lgkmcnt(0)7670; GFX9-NEXT: s_mul_hi_u32 s4, s2, 0x6ca942207671; GFX9-NEXT: s_mul_i32 s5, s2, 0x6ca942207672; GFX9-NEXT: s_mul_i32 s7, s3, 0xfd81e197673; GFX9-NEXT: s_mul_hi_u32 s2, s2, 0xfd81e197674; GFX9-NEXT: s_mul_hi_u32 s6, s3, 0xfd81e197675; GFX9-NEXT: s_add_u32 s2, s7, s27676; GFX9-NEXT: s_addc_u32 s6, s6, 07677; GFX9-NEXT: s_add_u32 s2, s5, s27678; GFX9-NEXT: s_addc_u32 s2, s4, 07679; GFX9-NEXT: s_add_u32 s2, s6, s27680; GFX9-NEXT: s_addc_u32 s4, 0, 07681; GFX9-NEXT: s_mul_i32 s6, s3, 0x6ca942207682; GFX9-NEXT: s_mul_hi_u32 s5, s3, 0x6ca942207683; GFX9-NEXT: s_add_u32 s2, s6, s27684; GFX9-NEXT: s_addc_u32 s4, s5, s47685; GFX9-NEXT: s_ashr_i32 s3, s3, 317686; GFX9-NEXT: s_mul_i32 s5, s3, 0x6ca942207687; GFX9-NEXT: s_mul_hi_u32 s6, s3, 0xfd81e197688; GFX9-NEXT: s_add_i32 s5, s6, s57689; GFX9-NEXT: s_mul_i32 s3, s3, 0xfd81e197690; GFX9-NEXT: s_add_i32 s5, s5, s37691; GFX9-NEXT: s_add_u32 s2, s2, s37692; GFX9-NEXT: s_addc_u32 s3, s4, s57693; GFX9-NEXT: s_ashr_i64 s[4:5], s[2:3], 197694; GFX9-NEXT: s_lshr_b32 s2, s3, 317695; GFX9-NEXT: s_add_u32 s2, s4, s27696; GFX9-NEXT: s_addc_u32 s3, s5, 07697; GFX9-NEXT: v_mov_b32_e32 v0, s27698; GFX9-NEXT: v_mov_b32_e32 v1, s37699; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]7700; GFX9-NEXT: s_endpgm7701 %r = sdiv i64 %x, 12351957702 store i64 %r, ptr addrspace(1) %out7703 ret void7704}7705 7706define amdgpu_kernel void @sdiv_i64_pow2k_denom(ptr addrspace(1) %out, i64 %x) {7707; CHECK-LABEL: @sdiv_i64_pow2k_denom(7708; CHECK-NEXT: [[R:%.*]] = sdiv i64 [[X:%.*]], 40967709; CHECK-NEXT: store i64 [[R]], ptr addrspace(1) [[OUT:%.*]], align 87710; CHECK-NEXT: ret void7711;7712; GFX6-LABEL: sdiv_i64_pow2k_denom:7713; GFX6: ; %bb.0:7714; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x97715; GFX6-NEXT: s_mov_b32 s7, 0xf0007716; GFX6-NEXT: s_mov_b32 s6, -17717; GFX6-NEXT: s_waitcnt lgkmcnt(0)7718; GFX6-NEXT: s_mov_b32 s4, s07719; GFX6-NEXT: s_ashr_i32 s0, s3, 317720; GFX6-NEXT: s_lshr_b32 s0, s0, 207721; GFX6-NEXT: s_add_u32 s0, s2, s07722; GFX6-NEXT: s_mov_b32 s5, s17723; GFX6-NEXT: s_addc_u32 s1, s3, 07724; GFX6-NEXT: s_ashr_i64 s[0:1], s[0:1], 127725; GFX6-NEXT: v_mov_b32_e32 v0, s07726; GFX6-NEXT: v_mov_b32_e32 v1, s17727; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 07728; GFX6-NEXT: s_endpgm7729;7730; GFX9-LABEL: sdiv_i64_pow2k_denom:7731; GFX9: ; %bb.0:7732; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x247733; GFX9-NEXT: v_mov_b32_e32 v2, 07734; GFX9-NEXT: s_waitcnt lgkmcnt(0)7735; GFX9-NEXT: s_ashr_i32 s4, s3, 317736; GFX9-NEXT: s_lshr_b32 s4, s4, 207737; GFX9-NEXT: s_add_u32 s2, s2, s47738; GFX9-NEXT: s_addc_u32 s3, s3, 07739; GFX9-NEXT: s_ashr_i64 s[2:3], s[2:3], 127740; GFX9-NEXT: v_mov_b32_e32 v0, s27741; GFX9-NEXT: v_mov_b32_e32 v1, s37742; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]7743; GFX9-NEXT: s_endpgm7744 %r = sdiv i64 %x, 40967745 store i64 %r, ptr addrspace(1) %out7746 ret void7747}7748 7749define amdgpu_kernel void @sdiv_i64_pow2_shl_denom(ptr addrspace(1) %out, i64 %x, i64 %y) {7750; CHECK-LABEL: @sdiv_i64_pow2_shl_denom(7751; CHECK-NEXT: [[SHL_Y:%.*]] = shl i64 4096, [[Y:%.*]]7752; CHECK-NEXT: [[R:%.*]] = sdiv i64 [[X:%.*]], [[SHL_Y]]7753; CHECK-NEXT: store i64 [[R]], ptr addrspace(1) [[OUT:%.*]], align 87754; CHECK-NEXT: ret void7755;7756; GFX6-LABEL: sdiv_i64_pow2_shl_denom:7757; GFX6: ; %bb.0:7758; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xd7759; GFX6-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x97760; GFX6-NEXT: s_mov_b32 s3, 0xf0007761; GFX6-NEXT: s_waitcnt lgkmcnt(0)7762; GFX6-NEXT: s_lshl_b64 s[0:1], 0x1000, s07763; GFX6-NEXT: s_ashr_i32 s8, s1, 317764; GFX6-NEXT: s_add_u32 s0, s0, s87765; GFX6-NEXT: s_mov_b32 s9, s87766; GFX6-NEXT: s_addc_u32 s1, s1, s87767; GFX6-NEXT: s_xor_b64 s[10:11], s[0:1], s[8:9]7768; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s107769; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s117770; GFX6-NEXT: s_sub_u32 s0, 0, s107771; GFX6-NEXT: s_subb_u32 s1, 0, s117772; GFX6-NEXT: v_madmk_f32 v0, v1, 0x4f800000, v07773; GFX6-NEXT: v_rcp_f32_e32 v0, v07774; GFX6-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v07775; GFX6-NEXT: v_mul_f32_e32 v1, 0x2f800000, v07776; GFX6-NEXT: v_trunc_f32_e32 v1, v17777; GFX6-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v07778; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v07779; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v17780; GFX6-NEXT: v_mul_hi_u32 v2, s0, v07781; GFX6-NEXT: v_readfirstlane_b32 s12, v17782; GFX6-NEXT: v_readfirstlane_b32 s2, v07783; GFX6-NEXT: s_mul_i32 s13, s0, s127784; GFX6-NEXT: v_readfirstlane_b32 s16, v27785; GFX6-NEXT: s_mul_i32 s14, s1, s27786; GFX6-NEXT: s_mul_i32 s15, s0, s27787; GFX6-NEXT: s_add_i32 s13, s16, s137788; GFX6-NEXT: v_mul_hi_u32 v3, v0, s157789; GFX6-NEXT: s_add_i32 s13, s13, s147790; GFX6-NEXT: v_mul_hi_u32 v0, v0, s137791; GFX6-NEXT: v_mul_hi_u32 v4, v1, s157792; GFX6-NEXT: v_readfirstlane_b32 s14, v37793; GFX6-NEXT: s_mul_i32 s16, s2, s137794; GFX6-NEXT: v_mul_hi_u32 v1, v1, s137795; GFX6-NEXT: s_add_u32 s14, s14, s167796; GFX6-NEXT: v_readfirstlane_b32 s16, v07797; GFX6-NEXT: s_mul_i32 s15, s12, s157798; GFX6-NEXT: s_addc_u32 s16, 0, s167799; GFX6-NEXT: v_readfirstlane_b32 s17, v47800; GFX6-NEXT: s_add_u32 s14, s14, s157801; GFX6-NEXT: s_addc_u32 s14, s16, s177802; GFX6-NEXT: v_readfirstlane_b32 s15, v17803; GFX6-NEXT: s_addc_u32 s15, s15, 07804; GFX6-NEXT: s_mul_i32 s13, s12, s137805; GFX6-NEXT: s_add_u32 s13, s14, s137806; GFX6-NEXT: s_addc_u32 s14, 0, s157807; GFX6-NEXT: s_add_u32 s13, s2, s137808; GFX6-NEXT: v_mov_b32_e32 v0, s137809; GFX6-NEXT: v_mul_hi_u32 v0, s0, v07810; GFX6-NEXT: s_addc_u32 s12, s12, s147811; GFX6-NEXT: s_mul_i32 s14, s0, s127812; GFX6-NEXT: s_mul_i32 s1, s1, s137813; GFX6-NEXT: v_readfirstlane_b32 s15, v07814; GFX6-NEXT: s_add_i32 s14, s15, s147815; GFX6-NEXT: s_mul_i32 s0, s0, s137816; GFX6-NEXT: s_add_i32 s1, s14, s17817; GFX6-NEXT: v_mov_b32_e32 v2, s07818; GFX6-NEXT: v_mov_b32_e32 v0, s17819; GFX6-NEXT: v_mul_hi_u32 v3, s12, v27820; GFX6-NEXT: v_mul_hi_u32 v2, s13, v27821; GFX6-NEXT: v_mul_hi_u32 v1, s12, v07822; GFX6-NEXT: v_mul_hi_u32 v0, s13, v07823; GFX6-NEXT: s_mul_i32 s15, s13, s17824; GFX6-NEXT: v_readfirstlane_b32 s17, v27825; GFX6-NEXT: s_add_u32 s15, s17, s157826; GFX6-NEXT: v_readfirstlane_b32 s16, v07827; GFX6-NEXT: s_mul_i32 s0, s12, s07828; GFX6-NEXT: s_addc_u32 s16, 0, s167829; GFX6-NEXT: v_readfirstlane_b32 s14, v37830; GFX6-NEXT: s_add_u32 s0, s15, s07831; GFX6-NEXT: s_addc_u32 s0, s16, s147832; GFX6-NEXT: v_readfirstlane_b32 s14, v17833; GFX6-NEXT: s_addc_u32 s14, s14, 07834; GFX6-NEXT: s_mul_i32 s1, s12, s17835; GFX6-NEXT: s_add_u32 s0, s0, s17836; GFX6-NEXT: s_addc_u32 s1, 0, s147837; GFX6-NEXT: s_add_u32 s14, s13, s07838; GFX6-NEXT: s_addc_u32 s15, s12, s17839; GFX6-NEXT: s_ashr_i32 s12, s7, 317840; GFX6-NEXT: s_add_u32 s0, s6, s127841; GFX6-NEXT: s_mov_b32 s13, s127842; GFX6-NEXT: s_addc_u32 s1, s7, s127843; GFX6-NEXT: s_xor_b64 s[6:7], s[0:1], s[12:13]7844; GFX6-NEXT: v_mov_b32_e32 v0, s157845; GFX6-NEXT: v_mul_hi_u32 v1, s6, v07846; GFX6-NEXT: v_mov_b32_e32 v2, s147847; GFX6-NEXT: v_mul_hi_u32 v3, s6, v27848; GFX6-NEXT: s_mov_b32 s0, s47849; GFX6-NEXT: v_readfirstlane_b32 s4, v17850; GFX6-NEXT: v_mul_hi_u32 v1, s7, v27851; GFX6-NEXT: s_mul_i32 s1, s6, s157852; GFX6-NEXT: v_readfirstlane_b32 s16, v37853; GFX6-NEXT: v_mul_hi_u32 v0, s7, v07854; GFX6-NEXT: s_add_u32 s1, s16, s17855; GFX6-NEXT: s_addc_u32 s4, 0, s47856; GFX6-NEXT: s_mul_i32 s14, s7, s147857; GFX6-NEXT: v_readfirstlane_b32 s16, v17858; GFX6-NEXT: s_add_u32 s1, s1, s147859; GFX6-NEXT: s_addc_u32 s1, s4, s167860; GFX6-NEXT: v_readfirstlane_b32 s4, v07861; GFX6-NEXT: s_addc_u32 s4, s4, 07862; GFX6-NEXT: s_mul_i32 s14, s7, s157863; GFX6-NEXT: s_add_u32 s14, s1, s147864; GFX6-NEXT: v_mov_b32_e32 v0, s147865; GFX6-NEXT: v_mul_hi_u32 v0, s10, v07866; GFX6-NEXT: s_addc_u32 s15, 0, s47867; GFX6-NEXT: s_mov_b32 s1, s57868; GFX6-NEXT: s_mul_i32 s4, s10, s157869; GFX6-NEXT: v_readfirstlane_b32 s5, v07870; GFX6-NEXT: s_add_i32 s4, s5, s47871; GFX6-NEXT: s_mul_i32 s5, s11, s147872; GFX6-NEXT: s_add_i32 s16, s4, s57873; GFX6-NEXT: s_sub_i32 s17, s7, s167874; GFX6-NEXT: s_mul_i32 s4, s10, s147875; GFX6-NEXT: s_sub_u32 s6, s6, s47876; GFX6-NEXT: s_cselect_b64 s[4:5], -1, 07877; GFX6-NEXT: s_subb_u32 s17, s17, s117878; GFX6-NEXT: s_sub_u32 s18, s6, s107879; GFX6-NEXT: s_subb_u32 s17, s17, 07880; GFX6-NEXT: s_cmp_ge_u32 s17, s117881; GFX6-NEXT: s_cselect_b32 s19, -1, 07882; GFX6-NEXT: s_cmp_ge_u32 s18, s107883; GFX6-NEXT: s_cselect_b32 s18, -1, 07884; GFX6-NEXT: s_cmp_eq_u32 s17, s117885; GFX6-NEXT: s_cselect_b32 s17, s18, s197886; GFX6-NEXT: s_add_u32 s18, s14, 17887; GFX6-NEXT: s_addc_u32 s19, s15, 07888; GFX6-NEXT: s_add_u32 s20, s14, 27889; GFX6-NEXT: s_addc_u32 s21, s15, 07890; GFX6-NEXT: s_cmp_lg_u32 s17, 07891; GFX6-NEXT: s_cselect_b32 s17, s20, s187892; GFX6-NEXT: s_cselect_b32 s18, s21, s197893; GFX6-NEXT: s_or_b32 s4, s4, s57894; GFX6-NEXT: s_subb_u32 s4, s7, s167895; GFX6-NEXT: s_cmp_ge_u32 s4, s117896; GFX6-NEXT: s_cselect_b32 s5, -1, 07897; GFX6-NEXT: s_cmp_ge_u32 s6, s107898; GFX6-NEXT: s_cselect_b32 s6, -1, 07899; GFX6-NEXT: s_cmp_eq_u32 s4, s117900; GFX6-NEXT: s_cselect_b32 s4, s6, s57901; GFX6-NEXT: s_cmp_lg_u32 s4, 07902; GFX6-NEXT: s_cselect_b32 s5, s18, s157903; GFX6-NEXT: s_cselect_b32 s4, s17, s147904; GFX6-NEXT: s_xor_b64 s[6:7], s[12:13], s[8:9]7905; GFX6-NEXT: s_xor_b64 s[4:5], s[4:5], s[6:7]7906; GFX6-NEXT: s_sub_u32 s4, s4, s67907; GFX6-NEXT: s_subb_u32 s5, s5, s77908; GFX6-NEXT: v_mov_b32_e32 v0, s47909; GFX6-NEXT: s_mov_b32 s2, -17910; GFX6-NEXT: v_mov_b32_e32 v1, s57911; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 07912; GFX6-NEXT: s_endpgm7913;7914; GFX9-LABEL: sdiv_i64_pow2_shl_denom:7915; GFX9: ; %bb.0:7916; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x347917; GFX9-NEXT: s_waitcnt lgkmcnt(0)7918; GFX9-NEXT: s_lshl_b64 s[0:1], 0x1000, s07919; GFX9-NEXT: s_ashr_i32 s6, s1, 317920; GFX9-NEXT: s_add_u32 s0, s0, s67921; GFX9-NEXT: s_mov_b32 s7, s67922; GFX9-NEXT: s_addc_u32 s1, s1, s67923; GFX9-NEXT: s_xor_b64 s[8:9], s[0:1], s[6:7]7924; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s87925; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s97926; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x247927; GFX9-NEXT: s_sub_u32 s4, 0, s87928; GFX9-NEXT: s_subb_u32 s5, 0, s97929; GFX9-NEXT: v_madmk_f32 v0, v1, 0x4f800000, v07930; GFX9-NEXT: v_rcp_f32_e32 v1, v07931; GFX9-NEXT: v_mov_b32_e32 v0, 07932; GFX9-NEXT: v_mul_f32_e32 v1, 0x5f7ffffc, v17933; GFX9-NEXT: v_mul_f32_e32 v2, 0x2f800000, v17934; GFX9-NEXT: v_trunc_f32_e32 v2, v27935; GFX9-NEXT: v_madmk_f32 v1, v2, 0xcf800000, v17936; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v27937; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v17938; GFX9-NEXT: v_readfirstlane_b32 s10, v27939; GFX9-NEXT: v_readfirstlane_b32 s11, v17940; GFX9-NEXT: s_mul_i32 s12, s4, s107941; GFX9-NEXT: s_mul_hi_u32 s14, s4, s117942; GFX9-NEXT: s_mul_i32 s13, s5, s117943; GFX9-NEXT: s_add_i32 s12, s14, s127944; GFX9-NEXT: s_mul_i32 s15, s4, s117945; GFX9-NEXT: s_add_i32 s12, s12, s137946; GFX9-NEXT: s_mul_hi_u32 s14, s11, s157947; GFX9-NEXT: s_mul_i32 s16, s11, s127948; GFX9-NEXT: s_mul_hi_u32 s13, s11, s127949; GFX9-NEXT: s_add_u32 s14, s14, s167950; GFX9-NEXT: s_addc_u32 s13, 0, s137951; GFX9-NEXT: s_mul_hi_u32 s17, s10, s157952; GFX9-NEXT: s_mul_i32 s15, s10, s157953; GFX9-NEXT: s_add_u32 s14, s14, s157954; GFX9-NEXT: s_mul_hi_u32 s16, s10, s127955; GFX9-NEXT: s_addc_u32 s13, s13, s177956; GFX9-NEXT: s_addc_u32 s14, s16, 07957; GFX9-NEXT: s_mul_i32 s12, s10, s127958; GFX9-NEXT: s_add_u32 s12, s13, s127959; GFX9-NEXT: s_addc_u32 s13, 0, s147960; GFX9-NEXT: s_add_u32 s11, s11, s127961; GFX9-NEXT: s_addc_u32 s10, s10, s137962; GFX9-NEXT: s_mul_i32 s12, s4, s107963; GFX9-NEXT: s_mul_hi_u32 s13, s4, s117964; GFX9-NEXT: s_add_i32 s12, s13, s127965; GFX9-NEXT: s_mul_i32 s5, s5, s117966; GFX9-NEXT: s_add_i32 s12, s12, s57967; GFX9-NEXT: s_mul_i32 s4, s4, s117968; GFX9-NEXT: s_mul_hi_u32 s13, s10, s47969; GFX9-NEXT: s_mul_i32 s14, s10, s47970; GFX9-NEXT: s_mul_i32 s16, s11, s127971; GFX9-NEXT: s_mul_hi_u32 s4, s11, s47972; GFX9-NEXT: s_mul_hi_u32 s15, s11, s127973; GFX9-NEXT: s_add_u32 s4, s4, s167974; GFX9-NEXT: s_addc_u32 s15, 0, s157975; GFX9-NEXT: s_add_u32 s4, s4, s147976; GFX9-NEXT: s_mul_hi_u32 s5, s10, s127977; GFX9-NEXT: s_addc_u32 s4, s15, s137978; GFX9-NEXT: s_addc_u32 s5, s5, 07979; GFX9-NEXT: s_mul_i32 s12, s10, s127980; GFX9-NEXT: s_add_u32 s4, s4, s127981; GFX9-NEXT: s_addc_u32 s5, 0, s57982; GFX9-NEXT: s_add_u32 s11, s11, s47983; GFX9-NEXT: s_addc_u32 s10, s10, s57984; GFX9-NEXT: s_waitcnt lgkmcnt(0)7985; GFX9-NEXT: s_ashr_i32 s4, s3, 317986; GFX9-NEXT: s_add_u32 s2, s2, s47987; GFX9-NEXT: s_mov_b32 s5, s47988; GFX9-NEXT: s_addc_u32 s3, s3, s47989; GFX9-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5]7990; GFX9-NEXT: s_mul_i32 s13, s2, s107991; GFX9-NEXT: s_mul_hi_u32 s14, s2, s117992; GFX9-NEXT: s_mul_hi_u32 s12, s2, s107993; GFX9-NEXT: s_add_u32 s13, s14, s137994; GFX9-NEXT: s_addc_u32 s12, 0, s127995; GFX9-NEXT: s_mul_hi_u32 s15, s3, s117996; GFX9-NEXT: s_mul_i32 s11, s3, s117997; GFX9-NEXT: s_add_u32 s11, s13, s117998; GFX9-NEXT: s_mul_hi_u32 s14, s3, s107999; GFX9-NEXT: s_addc_u32 s11, s12, s158000; GFX9-NEXT: s_addc_u32 s12, s14, 08001; GFX9-NEXT: s_mul_i32 s10, s3, s108002; GFX9-NEXT: s_add_u32 s13, s11, s108003; GFX9-NEXT: s_addc_u32 s12, 0, s128004; GFX9-NEXT: s_mul_i32 s10, s8, s128005; GFX9-NEXT: s_mul_hi_u32 s11, s8, s138006; GFX9-NEXT: s_add_i32 s10, s11, s108007; GFX9-NEXT: s_mul_i32 s11, s9, s138008; GFX9-NEXT: s_add_i32 s14, s10, s118009; GFX9-NEXT: s_sub_i32 s15, s3, s148010; GFX9-NEXT: s_mul_i32 s10, s8, s138011; GFX9-NEXT: s_sub_u32 s2, s2, s108012; GFX9-NEXT: s_cselect_b64 s[10:11], -1, 08013; GFX9-NEXT: s_subb_u32 s15, s15, s98014; GFX9-NEXT: s_sub_u32 s16, s2, s88015; GFX9-NEXT: s_subb_u32 s15, s15, 08016; GFX9-NEXT: s_cmp_ge_u32 s15, s98017; GFX9-NEXT: s_cselect_b32 s17, -1, 08018; GFX9-NEXT: s_cmp_ge_u32 s16, s88019; GFX9-NEXT: s_cselect_b32 s16, -1, 08020; GFX9-NEXT: s_cmp_eq_u32 s15, s98021; GFX9-NEXT: s_cselect_b32 s15, s16, s178022; GFX9-NEXT: s_add_u32 s16, s13, 18023; GFX9-NEXT: s_addc_u32 s17, s12, 08024; GFX9-NEXT: s_add_u32 s18, s13, 28025; GFX9-NEXT: s_addc_u32 s19, s12, 08026; GFX9-NEXT: s_cmp_lg_u32 s15, 08027; GFX9-NEXT: s_cselect_b32 s15, s18, s168028; GFX9-NEXT: s_cselect_b32 s16, s19, s178029; GFX9-NEXT: s_cmp_lg_u64 s[10:11], 08030; GFX9-NEXT: s_subb_u32 s3, s3, s148031; GFX9-NEXT: s_cmp_ge_u32 s3, s98032; GFX9-NEXT: s_cselect_b32 s10, -1, 08033; GFX9-NEXT: s_cmp_ge_u32 s2, s88034; GFX9-NEXT: s_cselect_b32 s2, -1, 08035; GFX9-NEXT: s_cmp_eq_u32 s3, s98036; GFX9-NEXT: s_cselect_b32 s2, s2, s108037; GFX9-NEXT: s_cmp_lg_u32 s2, 08038; GFX9-NEXT: s_cselect_b32 s3, s16, s128039; GFX9-NEXT: s_cselect_b32 s2, s15, s138040; GFX9-NEXT: s_xor_b64 s[4:5], s[4:5], s[6:7]8041; GFX9-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5]8042; GFX9-NEXT: s_sub_u32 s2, s2, s48043; GFX9-NEXT: s_subb_u32 s3, s3, s58044; GFX9-NEXT: v_mov_b32_e32 v1, s28045; GFX9-NEXT: v_mov_b32_e32 v2, s38046; GFX9-NEXT: global_store_dwordx2 v0, v[1:2], s[0:1]8047; GFX9-NEXT: s_endpgm8048 %shl.y = shl i64 4096, %y8049 %r = sdiv i64 %x, %shl.y8050 store i64 %r, ptr addrspace(1) %out8051 ret void8052}8053 8054define amdgpu_kernel void @sdiv_v2i64_pow2k_denom(ptr addrspace(1) %out, <2 x i64> %x) {8055; CHECK-LABEL: @sdiv_v2i64_pow2k_denom(8056; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i64> [[X:%.*]], i64 08057; CHECK-NEXT: [[TMP2:%.*]] = sdiv i64 [[TMP1]], 40968058; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i64> poison, i64 [[TMP2]], i64 08059; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[X]], i64 18060; CHECK-NEXT: [[TMP5:%.*]] = sdiv i64 [[TMP4]], 40968061; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i64> [[TMP3]], i64 [[TMP5]], i64 18062; CHECK-NEXT: store <2 x i64> [[TMP6]], ptr addrspace(1) [[OUT:%.*]], align 168063; CHECK-NEXT: ret void8064;8065; GFX6-LABEL: sdiv_v2i64_pow2k_denom:8066; GFX6: ; %bb.0:8067; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xd8068; GFX6-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x98069; GFX6-NEXT: s_mov_b32 s7, 0xf0008070; GFX6-NEXT: s_mov_b32 s6, -18071; GFX6-NEXT: s_waitcnt lgkmcnt(0)8072; GFX6-NEXT: s_ashr_i32 s8, s1, 318073; GFX6-NEXT: s_lshr_b32 s8, s8, 208074; GFX6-NEXT: s_add_u32 s0, s0, s88075; GFX6-NEXT: s_addc_u32 s1, s1, 08076; GFX6-NEXT: s_ashr_i32 s8, s3, 318077; GFX6-NEXT: s_ashr_i64 s[0:1], s[0:1], 128078; GFX6-NEXT: s_lshr_b32 s8, s8, 208079; GFX6-NEXT: s_add_u32 s2, s2, s88080; GFX6-NEXT: s_addc_u32 s3, s3, 08081; GFX6-NEXT: s_ashr_i64 s[2:3], s[2:3], 128082; GFX6-NEXT: v_mov_b32_e32 v0, s08083; GFX6-NEXT: v_mov_b32_e32 v1, s18084; GFX6-NEXT: v_mov_b32_e32 v2, s28085; GFX6-NEXT: v_mov_b32_e32 v3, s38086; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 08087; GFX6-NEXT: s_endpgm8088;8089; GFX9-LABEL: sdiv_v2i64_pow2k_denom:8090; GFX9: ; %bb.0:8091; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x348092; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x248093; GFX9-NEXT: v_mov_b32_e32 v4, 08094; GFX9-NEXT: s_waitcnt lgkmcnt(0)8095; GFX9-NEXT: s_ashr_i32 s4, s1, 318096; GFX9-NEXT: s_lshr_b32 s4, s4, 208097; GFX9-NEXT: s_add_u32 s0, s0, s48098; GFX9-NEXT: s_addc_u32 s1, s1, 08099; GFX9-NEXT: s_ashr_i32 s4, s3, 318100; GFX9-NEXT: s_ashr_i64 s[0:1], s[0:1], 128101; GFX9-NEXT: s_lshr_b32 s4, s4, 208102; GFX9-NEXT: s_add_u32 s2, s2, s48103; GFX9-NEXT: s_addc_u32 s3, s3, 08104; GFX9-NEXT: s_ashr_i64 s[2:3], s[2:3], 128105; GFX9-NEXT: v_mov_b32_e32 v0, s08106; GFX9-NEXT: v_mov_b32_e32 v1, s18107; GFX9-NEXT: v_mov_b32_e32 v2, s28108; GFX9-NEXT: v_mov_b32_e32 v3, s38109; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7]8110; GFX9-NEXT: s_endpgm8111 %r = sdiv <2 x i64> %x, <i64 4096, i64 4096>8112 store <2 x i64> %r, ptr addrspace(1) %out8113 ret void8114}8115 8116define amdgpu_kernel void @ssdiv_v2i64_mixed_pow2k_denom(ptr addrspace(1) %out, <2 x i64> %x) {8117; CHECK-LABEL: @ssdiv_v2i64_mixed_pow2k_denom(8118; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i64> [[X:%.*]], i64 08119; CHECK-NEXT: [[TMP2:%.*]] = sdiv i64 [[TMP1]], 40968120; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i64> poison, i64 [[TMP2]], i64 08121; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[X]], i64 18122; CHECK-NEXT: [[TMP5:%.*]] = sdiv i64 [[TMP4]], 40958123; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i64> [[TMP3]], i64 [[TMP5]], i64 18124; CHECK-NEXT: store <2 x i64> [[TMP6]], ptr addrspace(1) [[OUT:%.*]], align 168125; CHECK-NEXT: ret void8126;8127; GFX6-LABEL: ssdiv_v2i64_mixed_pow2k_denom:8128; GFX6: ; %bb.0:8129; GFX6-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0xd8130; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x98131; GFX6-NEXT: v_mov_b32_e32 v2, 0x80080098132; GFX6-NEXT: v_mov_b32_e32 v0, 0x800800808133; GFX6-NEXT: s_mov_b32 s3, 0xf0008134; GFX6-NEXT: s_waitcnt lgkmcnt(0)8135; GFX6-NEXT: v_mul_hi_u32 v3, s10, v28136; GFX6-NEXT: v_mul_hi_u32 v4, s11, v28137; GFX6-NEXT: v_mul_hi_u32 v1, s10, v08138; GFX6-NEXT: s_mul_i32 s7, s11, 0x80080098139; GFX6-NEXT: v_add_i32_e32 v3, vcc, s7, v38140; GFX6-NEXT: s_mul_i32 s6, s10, 0x800800808141; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc8142; GFX6-NEXT: v_add_i32_e32 v3, vcc, s6, v38143; GFX6-NEXT: s_ashr_i32 s4, s9, 318144; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc8145; GFX6-NEXT: s_lshr_b32 s4, s4, 208146; GFX6-NEXT: v_add_i32_e32 v1, vcc, v4, v18147; GFX6-NEXT: s_add_u32 s4, s8, s48148; GFX6-NEXT: v_addc_u32_e64 v3, s[6:7], 0, 0, vcc8149; GFX6-NEXT: s_addc_u32 s5, s9, 08150; GFX6-NEXT: s_ashr_i32 s7, s11, 318151; GFX6-NEXT: v_mul_hi_u32 v0, s11, v08152; GFX6-NEXT: v_mul_hi_u32 v2, s7, v28153; GFX6-NEXT: s_mul_i32 s6, s11, 0x800800808154; GFX6-NEXT: v_add_i32_e32 v1, vcc, s6, v18155; GFX6-NEXT: s_mul_i32 s6, s7, 0x800800808156; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v0, v3, vcc8157; GFX6-NEXT: v_add_i32_e32 v2, vcc, s6, v28158; GFX6-NEXT: s_mul_i32 s6, s7, 0x80080098159; GFX6-NEXT: v_add_i32_e32 v2, vcc, s6, v28160; GFX6-NEXT: v_mov_b32_e32 v3, s68161; GFX6-NEXT: v_mov_b32_e32 v4, s118162; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s10, v38163; GFX6-NEXT: v_subb_u32_e32 v2, vcc, v2, v4, vcc8164; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v38165; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v0, v2, vcc8166; GFX6-NEXT: v_mov_b32_e32 v3, s118167; GFX6-NEXT: v_add_i32_e32 v0, vcc, s10, v18168; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v2, v3, vcc8169; GFX6-NEXT: v_ashr_i64 v[2:3], v[0:1], 118170; GFX6-NEXT: v_lshrrev_b32_e32 v0, 31, v18171; GFX6-NEXT: s_ashr_i64 s[4:5], s[4:5], 128172; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v08173; GFX6-NEXT: s_mov_b32 s2, -18174; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc8175; GFX6-NEXT: v_mov_b32_e32 v0, s48176; GFX6-NEXT: v_mov_b32_e32 v1, s58177; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 08178; GFX6-NEXT: s_endpgm8179;8180; GFX9-LABEL: ssdiv_v2i64_mixed_pow2k_denom:8181; GFX9: ; %bb.0:8182; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x348183; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x248184; GFX9-NEXT: v_mov_b32_e32 v4, 08185; GFX9-NEXT: s_waitcnt lgkmcnt(0)8186; GFX9-NEXT: s_ashr_i32 s4, s1, 318187; GFX9-NEXT: s_lshr_b32 s4, s4, 208188; GFX9-NEXT: s_add_u32 s0, s0, s48189; GFX9-NEXT: s_addc_u32 s1, s1, 08190; GFX9-NEXT: s_ashr_i64 s[0:1], s[0:1], 128191; GFX9-NEXT: s_mul_i32 s9, s3, 0x80080098192; GFX9-NEXT: s_mul_hi_u32 s10, s2, 0x80080098193; GFX9-NEXT: s_mul_hi_u32 s4, s3, 0x80080098194; GFX9-NEXT: s_add_u32 s9, s9, s108195; GFX9-NEXT: s_mul_i32 s8, s2, 0x800800808196; GFX9-NEXT: s_addc_u32 s4, s4, 08197; GFX9-NEXT: s_mul_hi_u32 s5, s2, 0x800800808198; GFX9-NEXT: s_add_u32 s8, s8, s98199; GFX9-NEXT: s_addc_u32 s5, s5, 08200; GFX9-NEXT: s_add_u32 s4, s4, s58201; GFX9-NEXT: s_addc_u32 s5, 0, 08202; GFX9-NEXT: s_mul_i32 s9, s3, 0x800800808203; GFX9-NEXT: s_mul_hi_u32 s8, s3, 0x800800808204; GFX9-NEXT: s_add_u32 s4, s9, s48205; GFX9-NEXT: s_addc_u32 s5, s8, s58206; GFX9-NEXT: s_ashr_i32 s8, s3, 318207; GFX9-NEXT: s_mul_i32 s9, s8, 0x800800808208; GFX9-NEXT: s_mul_hi_u32 s10, s8, 0x80080098209; GFX9-NEXT: s_add_i32 s9, s10, s98210; GFX9-NEXT: s_mul_i32 s8, s8, 0x80080098211; GFX9-NEXT: s_add_i32 s9, s9, s88212; GFX9-NEXT: s_sub_u32 s8, s8, s28213; GFX9-NEXT: s_subb_u32 s9, s9, s38214; GFX9-NEXT: s_add_u32 s4, s4, s88215; GFX9-NEXT: s_addc_u32 s5, s5, s98216; GFX9-NEXT: s_add_u32 s2, s4, s28217; GFX9-NEXT: s_addc_u32 s3, s5, s38218; GFX9-NEXT: s_ashr_i64 s[4:5], s[2:3], 118219; GFX9-NEXT: s_lshr_b32 s2, s3, 318220; GFX9-NEXT: s_add_u32 s2, s4, s28221; GFX9-NEXT: s_addc_u32 s3, s5, 08222; GFX9-NEXT: v_mov_b32_e32 v0, s08223; GFX9-NEXT: v_mov_b32_e32 v1, s18224; GFX9-NEXT: v_mov_b32_e32 v2, s28225; GFX9-NEXT: v_mov_b32_e32 v3, s38226; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7]8227; GFX9-NEXT: s_endpgm8228 %r = sdiv <2 x i64> %x, <i64 4096, i64 4095>8229 store <2 x i64> %r, ptr addrspace(1) %out8230 ret void8231}8232 8233define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x i64> %x, <2 x i64> %y) {8234; CHECK-LABEL: @sdiv_v2i64_pow2_shl_denom(8235; CHECK-NEXT: [[SHL_Y:%.*]] = shl <2 x i64> splat (i64 4096), [[Y:%.*]]8236; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i64> [[X:%.*]], i64 08237; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 08238; CHECK-NEXT: [[TMP3:%.*]] = sdiv i64 [[TMP1]], [[TMP2]]8239; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i64> poison, i64 [[TMP3]], i64 08240; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i64> [[X]], i64 18241; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 18242; CHECK-NEXT: [[TMP7:%.*]] = sdiv i64 [[TMP5]], [[TMP6]]8243; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x i64> [[TMP4]], i64 [[TMP7]], i64 18244; CHECK-NEXT: store <2 x i64> [[TMP8]], ptr addrspace(1) [[OUT:%.*]], align 168245; CHECK-NEXT: ret void8246;8247; GFX6-LABEL: sdiv_v2i64_pow2_shl_denom:8248; GFX6: ; %bb.0:8249; GFX6-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0xd8250; GFX6-NEXT: s_waitcnt lgkmcnt(0)8251; GFX6-NEXT: s_lshl_b64 s[6:7], 0x1000, s128252; GFX6-NEXT: s_lshl_b64 s[0:1], 0x1000, s148253; GFX6-NEXT: s_ashr_i32 s2, s7, 318254; GFX6-NEXT: s_add_u32 s6, s6, s28255; GFX6-NEXT: s_mov_b32 s3, s28256; GFX6-NEXT: s_addc_u32 s7, s7, s28257; GFX6-NEXT: s_xor_b64 s[6:7], s[6:7], s[2:3]8258; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s68259; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s78260; GFX6-NEXT: s_sub_u32 s12, 0, s68261; GFX6-NEXT: s_subb_u32 s13, 0, s78262; GFX6-NEXT: v_mac_f32_e32 v0, 0x4f800000, v18263; GFX6-NEXT: v_rcp_f32_e32 v0, v08264; GFX6-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v08265; GFX6-NEXT: v_mul_f32_e32 v1, 0x2f800000, v08266; GFX6-NEXT: v_trunc_f32_e32 v1, v18267; GFX6-NEXT: v_mac_f32_e32 v0, 0xcf800000, v18268; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v08269; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v18270; GFX6-NEXT: v_mul_hi_u32 v2, s12, v08271; GFX6-NEXT: v_readfirstlane_b32 s14, v18272; GFX6-NEXT: v_readfirstlane_b32 s15, v08273; GFX6-NEXT: s_mul_i32 s16, s12, s148274; GFX6-NEXT: v_readfirstlane_b32 s19, v28275; GFX6-NEXT: s_mul_i32 s17, s13, s158276; GFX6-NEXT: s_mul_i32 s18, s12, s158277; GFX6-NEXT: s_add_i32 s16, s19, s168278; GFX6-NEXT: v_mul_hi_u32 v3, v0, s188279; GFX6-NEXT: s_add_i32 s16, s16, s178280; GFX6-NEXT: v_mul_hi_u32 v0, v0, s168281; GFX6-NEXT: v_mul_hi_u32 v4, v1, s188282; GFX6-NEXT: v_readfirstlane_b32 s17, v38283; GFX6-NEXT: s_mul_i32 s20, s15, s168284; GFX6-NEXT: v_mul_hi_u32 v1, v1, s168285; GFX6-NEXT: s_add_u32 s17, s17, s208286; GFX6-NEXT: v_readfirstlane_b32 s20, v08287; GFX6-NEXT: s_mul_i32 s18, s14, s188288; GFX6-NEXT: s_addc_u32 s20, 0, s208289; GFX6-NEXT: v_readfirstlane_b32 s19, v48290; GFX6-NEXT: s_add_u32 s17, s17, s188291; GFX6-NEXT: s_addc_u32 s17, s20, s198292; GFX6-NEXT: v_readfirstlane_b32 s18, v18293; GFX6-NEXT: s_addc_u32 s18, s18, 08294; GFX6-NEXT: s_mul_i32 s16, s14, s168295; GFX6-NEXT: s_add_u32 s16, s17, s168296; GFX6-NEXT: s_addc_u32 s17, 0, s188297; GFX6-NEXT: s_add_u32 s15, s15, s168298; GFX6-NEXT: v_mov_b32_e32 v0, s158299; GFX6-NEXT: v_mul_hi_u32 v0, s12, v08300; GFX6-NEXT: s_addc_u32 s14, s14, s178301; GFX6-NEXT: s_mul_i32 s16, s12, s148302; GFX6-NEXT: s_mul_i32 s13, s13, s158303; GFX6-NEXT: v_readfirstlane_b32 s17, v08304; GFX6-NEXT: s_add_i32 s16, s17, s168305; GFX6-NEXT: s_mul_i32 s12, s12, s158306; GFX6-NEXT: s_add_i32 s13, s16, s138307; GFX6-NEXT: v_mov_b32_e32 v2, s128308; GFX6-NEXT: v_mov_b32_e32 v0, s138309; GFX6-NEXT: v_mul_hi_u32 v3, s14, v28310; GFX6-NEXT: v_mul_hi_u32 v2, s15, v28311; GFX6-NEXT: v_mul_hi_u32 v1, s14, v08312; GFX6-NEXT: v_mul_hi_u32 v0, s15, v08313; GFX6-NEXT: s_mul_i32 s17, s15, s138314; GFX6-NEXT: v_readfirstlane_b32 s19, v28315; GFX6-NEXT: s_add_u32 s17, s19, s178316; GFX6-NEXT: v_readfirstlane_b32 s18, v08317; GFX6-NEXT: s_mul_i32 s12, s14, s128318; GFX6-NEXT: s_addc_u32 s18, 0, s188319; GFX6-NEXT: v_readfirstlane_b32 s16, v38320; GFX6-NEXT: s_add_u32 s12, s17, s128321; GFX6-NEXT: s_addc_u32 s12, s18, s168322; GFX6-NEXT: v_readfirstlane_b32 s16, v18323; GFX6-NEXT: s_addc_u32 s16, s16, 08324; GFX6-NEXT: s_mul_i32 s13, s14, s138325; GFX6-NEXT: s_add_u32 s12, s12, s138326; GFX6-NEXT: s_addc_u32 s13, 0, s168327; GFX6-NEXT: s_add_u32 s15, s15, s128328; GFX6-NEXT: s_addc_u32 s14, s14, s138329; GFX6-NEXT: s_ashr_i32 s12, s9, 318330; GFX6-NEXT: s_add_u32 s8, s8, s128331; GFX6-NEXT: s_mov_b32 s13, s128332; GFX6-NEXT: s_addc_u32 s9, s9, s128333; GFX6-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]8334; GFX6-NEXT: v_mov_b32_e32 v0, s148335; GFX6-NEXT: v_mul_hi_u32 v1, s8, v08336; GFX6-NEXT: v_mov_b32_e32 v2, s158337; GFX6-NEXT: v_mul_hi_u32 v3, s8, v28338; GFX6-NEXT: s_mul_i32 s16, s8, s148339; GFX6-NEXT: v_readfirstlane_b32 s17, v18340; GFX6-NEXT: v_mul_hi_u32 v1, s9, v28341; GFX6-NEXT: v_readfirstlane_b32 s18, v38342; GFX6-NEXT: v_mul_hi_u32 v0, s9, v08343; GFX6-NEXT: s_add_u32 s16, s18, s168344; GFX6-NEXT: s_addc_u32 s17, 0, s178345; GFX6-NEXT: s_mul_i32 s15, s9, s158346; GFX6-NEXT: v_readfirstlane_b32 s18, v18347; GFX6-NEXT: s_add_u32 s15, s16, s158348; GFX6-NEXT: s_addc_u32 s15, s17, s188349; GFX6-NEXT: v_readfirstlane_b32 s16, v08350; GFX6-NEXT: s_addc_u32 s16, s16, 08351; GFX6-NEXT: s_mul_i32 s14, s9, s148352; GFX6-NEXT: s_add_u32 s17, s15, s148353; GFX6-NEXT: v_mov_b32_e32 v0, s178354; GFX6-NEXT: v_mul_hi_u32 v0, s6, v08355; GFX6-NEXT: s_addc_u32 s16, 0, s168356; GFX6-NEXT: s_mul_i32 s14, s6, s168357; GFX6-NEXT: v_readfirstlane_b32 s15, v08358; GFX6-NEXT: s_add_i32 s14, s15, s148359; GFX6-NEXT: s_mul_i32 s15, s7, s178360; GFX6-NEXT: s_add_i32 s18, s14, s158361; GFX6-NEXT: s_sub_i32 s19, s9, s188362; GFX6-NEXT: s_mul_i32 s14, s6, s178363; GFX6-NEXT: s_sub_u32 s8, s8, s148364; GFX6-NEXT: s_cselect_b64 s[14:15], -1, 08365; GFX6-NEXT: s_subb_u32 s19, s19, s78366; GFX6-NEXT: s_sub_u32 s20, s8, s68367; GFX6-NEXT: s_subb_u32 s19, s19, 08368; GFX6-NEXT: s_cmp_ge_u32 s19, s78369; GFX6-NEXT: s_cselect_b32 s21, -1, 08370; GFX6-NEXT: s_cmp_ge_u32 s20, s68371; GFX6-NEXT: s_cselect_b32 s20, -1, 08372; GFX6-NEXT: s_cmp_eq_u32 s19, s78373; GFX6-NEXT: s_cselect_b32 s19, s20, s218374; GFX6-NEXT: s_add_u32 s20, s17, 18375; GFX6-NEXT: s_addc_u32 s21, s16, 08376; GFX6-NEXT: s_add_u32 s22, s17, 28377; GFX6-NEXT: s_addc_u32 s23, s16, 08378; GFX6-NEXT: s_cmp_lg_u32 s19, 08379; GFX6-NEXT: s_cselect_b32 s19, s22, s208380; GFX6-NEXT: s_cselect_b32 s20, s23, s218381; GFX6-NEXT: s_or_b32 s14, s14, s158382; GFX6-NEXT: s_subb_u32 s9, s9, s188383; GFX6-NEXT: s_cmp_ge_u32 s9, s78384; GFX6-NEXT: s_cselect_b32 s14, -1, 08385; GFX6-NEXT: s_cmp_ge_u32 s8, s68386; GFX6-NEXT: s_cselect_b32 s6, -1, 08387; GFX6-NEXT: s_cmp_eq_u32 s9, s78388; GFX6-NEXT: s_cselect_b32 s6, s6, s148389; GFX6-NEXT: s_cmp_lg_u32 s6, 08390; GFX6-NEXT: s_cselect_b32 s7, s20, s168391; GFX6-NEXT: s_cselect_b32 s6, s19, s178392; GFX6-NEXT: s_xor_b64 s[2:3], s[12:13], s[2:3]8393; GFX6-NEXT: s_xor_b64 s[6:7], s[6:7], s[2:3]8394; GFX6-NEXT: s_sub_u32 s14, s6, s28395; GFX6-NEXT: s_subb_u32 s15, s7, s38396; GFX6-NEXT: s_ashr_i32 s6, s1, 318397; GFX6-NEXT: s_add_u32 s0, s0, s68398; GFX6-NEXT: s_mov_b32 s7, s68399; GFX6-NEXT: s_addc_u32 s1, s1, s68400; GFX6-NEXT: s_xor_b64 s[8:9], s[0:1], s[6:7]8401; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s88402; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s98403; GFX6-NEXT: s_sub_u32 s2, 0, s88404; GFX6-NEXT: s_subb_u32 s3, 0, s98405; GFX6-NEXT: v_mac_f32_e32 v0, 0x4f800000, v18406; GFX6-NEXT: v_rcp_f32_e32 v0, v08407; GFX6-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v08408; GFX6-NEXT: v_mul_f32_e32 v1, 0x2f800000, v08409; GFX6-NEXT: v_trunc_f32_e32 v1, v18410; GFX6-NEXT: v_mac_f32_e32 v0, 0xcf800000, v18411; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v08412; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v18413; GFX6-NEXT: v_mul_hi_u32 v2, s2, v08414; GFX6-NEXT: v_readfirstlane_b32 s12, v18415; GFX6-NEXT: v_readfirstlane_b32 s0, v08416; GFX6-NEXT: s_mul_i32 s13, s2, s128417; GFX6-NEXT: v_readfirstlane_b32 s16, v28418; GFX6-NEXT: s_mul_i32 s1, s3, s08419; GFX6-NEXT: s_add_i32 s13, s16, s138420; GFX6-NEXT: s_add_i32 s13, s13, s18421; GFX6-NEXT: s_mul_i32 s1, s2, s08422; GFX6-NEXT: v_mul_hi_u32 v2, v0, s138423; GFX6-NEXT: v_mul_hi_u32 v0, v0, s18424; GFX6-NEXT: s_mul_i32 s16, s0, s138425; GFX6-NEXT: v_readfirstlane_b32 s17, v28426; GFX6-NEXT: v_readfirstlane_b32 s18, v08427; GFX6-NEXT: v_mul_hi_u32 v0, v1, s18428; GFX6-NEXT: v_mul_hi_u32 v1, v1, s138429; GFX6-NEXT: s_add_u32 s16, s18, s168430; GFX6-NEXT: s_addc_u32 s17, 0, s178431; GFX6-NEXT: s_mul_i32 s1, s12, s18432; GFX6-NEXT: v_readfirstlane_b32 s18, v08433; GFX6-NEXT: s_add_u32 s1, s16, s18434; GFX6-NEXT: s_addc_u32 s1, s17, s188435; GFX6-NEXT: v_readfirstlane_b32 s16, v18436; GFX6-NEXT: s_addc_u32 s16, s16, 08437; GFX6-NEXT: s_mul_i32 s13, s12, s138438; GFX6-NEXT: s_add_u32 s1, s1, s138439; GFX6-NEXT: s_addc_u32 s13, 0, s168440; GFX6-NEXT: s_add_u32 s16, s0, s18441; GFX6-NEXT: v_mov_b32_e32 v0, s168442; GFX6-NEXT: v_mul_hi_u32 v0, s2, v08443; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x98444; GFX6-NEXT: s_addc_u32 s4, s12, s138445; GFX6-NEXT: s_mul_i32 s5, s2, s48446; GFX6-NEXT: v_readfirstlane_b32 s12, v08447; GFX6-NEXT: s_add_i32 s5, s12, s58448; GFX6-NEXT: s_mul_i32 s3, s3, s168449; GFX6-NEXT: s_mul_i32 s2, s2, s168450; GFX6-NEXT: s_add_i32 s3, s5, s38451; GFX6-NEXT: v_mov_b32_e32 v2, s28452; GFX6-NEXT: v_mov_b32_e32 v0, s38453; GFX6-NEXT: v_mul_hi_u32 v3, s4, v28454; GFX6-NEXT: v_mul_hi_u32 v2, s16, v28455; GFX6-NEXT: v_mul_hi_u32 v1, s4, v08456; GFX6-NEXT: v_mul_hi_u32 v0, s16, v08457; GFX6-NEXT: s_mul_i32 s12, s16, s38458; GFX6-NEXT: v_readfirstlane_b32 s17, v28459; GFX6-NEXT: s_add_u32 s12, s17, s128460; GFX6-NEXT: v_readfirstlane_b32 s13, v08461; GFX6-NEXT: s_mul_i32 s2, s4, s28462; GFX6-NEXT: s_addc_u32 s13, 0, s138463; GFX6-NEXT: v_readfirstlane_b32 s5, v38464; GFX6-NEXT: s_add_u32 s2, s12, s28465; GFX6-NEXT: s_addc_u32 s2, s13, s58466; GFX6-NEXT: v_readfirstlane_b32 s5, v18467; GFX6-NEXT: s_addc_u32 s5, s5, 08468; GFX6-NEXT: s_mul_i32 s3, s4, s38469; GFX6-NEXT: s_add_u32 s2, s2, s38470; GFX6-NEXT: s_addc_u32 s3, 0, s58471; GFX6-NEXT: s_add_u32 s12, s16, s28472; GFX6-NEXT: s_addc_u32 s13, s4, s38473; GFX6-NEXT: s_ashr_i32 s4, s11, 318474; GFX6-NEXT: s_add_u32 s2, s10, s48475; GFX6-NEXT: s_mov_b32 s5, s48476; GFX6-NEXT: s_addc_u32 s3, s11, s48477; GFX6-NEXT: s_xor_b64 s[10:11], s[2:3], s[4:5]8478; GFX6-NEXT: v_mov_b32_e32 v0, s138479; GFX6-NEXT: v_mul_hi_u32 v1, s10, v08480; GFX6-NEXT: v_mov_b32_e32 v2, s128481; GFX6-NEXT: v_mul_hi_u32 v3, s10, v28482; GFX6-NEXT: s_mul_i32 s2, s10, s138483; GFX6-NEXT: v_readfirstlane_b32 s16, v18484; GFX6-NEXT: v_mul_hi_u32 v1, s11, v28485; GFX6-NEXT: v_readfirstlane_b32 s17, v38486; GFX6-NEXT: v_mul_hi_u32 v0, s11, v08487; GFX6-NEXT: s_add_u32 s2, s17, s28488; GFX6-NEXT: s_addc_u32 s16, 0, s168489; GFX6-NEXT: s_mul_i32 s12, s11, s128490; GFX6-NEXT: v_readfirstlane_b32 s17, v18491; GFX6-NEXT: s_add_u32 s2, s2, s128492; GFX6-NEXT: s_addc_u32 s2, s16, s178493; GFX6-NEXT: v_readfirstlane_b32 s12, v08494; GFX6-NEXT: s_addc_u32 s12, s12, 08495; GFX6-NEXT: s_mul_i32 s13, s11, s138496; GFX6-NEXT: s_add_u32 s16, s2, s138497; GFX6-NEXT: v_mov_b32_e32 v0, s168498; GFX6-NEXT: v_mul_hi_u32 v0, s8, v08499; GFX6-NEXT: s_addc_u32 s17, 0, s128500; GFX6-NEXT: s_mul_i32 s12, s8, s178501; GFX6-NEXT: s_mov_b32 s3, 0xf0008502; GFX6-NEXT: v_readfirstlane_b32 s13, v08503; GFX6-NEXT: s_add_i32 s12, s13, s128504; GFX6-NEXT: s_mul_i32 s13, s9, s168505; GFX6-NEXT: s_add_i32 s18, s12, s138506; GFX6-NEXT: s_sub_i32 s19, s11, s188507; GFX6-NEXT: s_mul_i32 s12, s8, s168508; GFX6-NEXT: s_sub_u32 s10, s10, s128509; GFX6-NEXT: s_cselect_b64 s[12:13], -1, 08510; GFX6-NEXT: s_subb_u32 s19, s19, s98511; GFX6-NEXT: s_sub_u32 s20, s10, s88512; GFX6-NEXT: s_subb_u32 s19, s19, 08513; GFX6-NEXT: s_cmp_ge_u32 s19, s98514; GFX6-NEXT: s_cselect_b32 s21, -1, 08515; GFX6-NEXT: s_cmp_ge_u32 s20, s88516; GFX6-NEXT: s_cselect_b32 s20, -1, 08517; GFX6-NEXT: s_cmp_eq_u32 s19, s98518; GFX6-NEXT: s_cselect_b32 s19, s20, s218519; GFX6-NEXT: s_add_u32 s20, s16, 18520; GFX6-NEXT: s_addc_u32 s21, s17, 08521; GFX6-NEXT: s_add_u32 s22, s16, 28522; GFX6-NEXT: s_addc_u32 s23, s17, 08523; GFX6-NEXT: s_cmp_lg_u32 s19, 08524; GFX6-NEXT: s_cselect_b32 s19, s22, s208525; GFX6-NEXT: s_cselect_b32 s20, s23, s218526; GFX6-NEXT: s_or_b32 s12, s12, s138527; GFX6-NEXT: s_subb_u32 s11, s11, s188528; GFX6-NEXT: s_cmp_ge_u32 s11, s98529; GFX6-NEXT: s_cselect_b32 s12, -1, 08530; GFX6-NEXT: s_cmp_ge_u32 s10, s88531; GFX6-NEXT: s_cselect_b32 s8, -1, 08532; GFX6-NEXT: s_cmp_eq_u32 s11, s98533; GFX6-NEXT: s_cselect_b32 s8, s8, s128534; GFX6-NEXT: s_cmp_lg_u32 s8, 08535; GFX6-NEXT: s_cselect_b32 s9, s20, s178536; GFX6-NEXT: s_cselect_b32 s8, s19, s168537; GFX6-NEXT: s_xor_b64 s[4:5], s[4:5], s[6:7]8538; GFX6-NEXT: s_xor_b64 s[6:7], s[8:9], s[4:5]8539; GFX6-NEXT: s_sub_u32 s4, s6, s48540; GFX6-NEXT: s_subb_u32 s5, s7, s58541; GFX6-NEXT: s_mov_b32 s2, -18542; GFX6-NEXT: v_mov_b32_e32 v0, s148543; GFX6-NEXT: v_mov_b32_e32 v1, s158544; GFX6-NEXT: v_mov_b32_e32 v2, s48545; GFX6-NEXT: v_mov_b32_e32 v3, s58546; GFX6-NEXT: s_waitcnt lgkmcnt(0)8547; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 08548; GFX6-NEXT: s_endpgm8549;8550; GFX9-LABEL: sdiv_v2i64_pow2_shl_denom:8551; GFX9: ; %bb.0:8552; GFX9-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x348553; GFX9-NEXT: s_waitcnt lgkmcnt(0)8554; GFX9-NEXT: s_lshl_b64 s[6:7], 0x1000, s128555; GFX9-NEXT: s_lshl_b64 s[0:1], 0x1000, s148556; GFX9-NEXT: s_ashr_i32 s2, s7, 318557; GFX9-NEXT: s_add_u32 s6, s6, s28558; GFX9-NEXT: s_mov_b32 s3, s28559; GFX9-NEXT: s_addc_u32 s7, s7, s28560; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[2:3]8561; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s68562; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s78563; GFX9-NEXT: s_sub_u32 s12, 0, s68564; GFX9-NEXT: s_subb_u32 s13, 0, s78565; GFX9-NEXT: v_mac_f32_e32 v0, 0x4f800000, v18566; GFX9-NEXT: v_rcp_f32_e32 v0, v08567; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v08568; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v08569; GFX9-NEXT: v_trunc_f32_e32 v1, v18570; GFX9-NEXT: v_mac_f32_e32 v0, 0xcf800000, v18571; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v18572; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v08573; GFX9-NEXT: v_readfirstlane_b32 s14, v18574; GFX9-NEXT: v_readfirstlane_b32 s15, v08575; GFX9-NEXT: s_mul_i32 s16, s12, s148576; GFX9-NEXT: s_mul_hi_u32 s18, s12, s158577; GFX9-NEXT: s_mul_i32 s17, s13, s158578; GFX9-NEXT: s_add_i32 s16, s18, s168579; GFX9-NEXT: s_mul_i32 s19, s12, s158580; GFX9-NEXT: s_add_i32 s16, s16, s178581; GFX9-NEXT: s_mul_hi_u32 s18, s15, s198582; GFX9-NEXT: s_mul_i32 s20, s15, s168583; GFX9-NEXT: s_mul_hi_u32 s17, s15, s168584; GFX9-NEXT: s_add_u32 s18, s18, s208585; GFX9-NEXT: s_addc_u32 s17, 0, s178586; GFX9-NEXT: s_mul_hi_u32 s20, s14, s198587; GFX9-NEXT: s_mul_i32 s19, s14, s198588; GFX9-NEXT: s_add_u32 s18, s18, s198589; GFX9-NEXT: s_mul_hi_u32 s21, s14, s168590; GFX9-NEXT: s_addc_u32 s17, s17, s208591; GFX9-NEXT: s_addc_u32 s18, s21, 08592; GFX9-NEXT: s_mul_i32 s16, s14, s168593; GFX9-NEXT: s_add_u32 s16, s17, s168594; GFX9-NEXT: s_addc_u32 s17, 0, s188595; GFX9-NEXT: s_add_u32 s15, s15, s168596; GFX9-NEXT: s_addc_u32 s14, s14, s178597; GFX9-NEXT: s_mul_i32 s16, s12, s148598; GFX9-NEXT: s_mul_hi_u32 s17, s12, s158599; GFX9-NEXT: s_add_i32 s16, s17, s168600; GFX9-NEXT: s_mul_i32 s13, s13, s158601; GFX9-NEXT: s_add_i32 s16, s16, s138602; GFX9-NEXT: s_mul_i32 s12, s12, s158603; GFX9-NEXT: s_mul_hi_u32 s17, s14, s128604; GFX9-NEXT: s_mul_i32 s18, s14, s128605; GFX9-NEXT: s_mul_i32 s20, s15, s168606; GFX9-NEXT: s_mul_hi_u32 s12, s15, s128607; GFX9-NEXT: s_mul_hi_u32 s19, s15, s168608; GFX9-NEXT: s_add_u32 s12, s12, s208609; GFX9-NEXT: s_addc_u32 s19, 0, s198610; GFX9-NEXT: s_add_u32 s12, s12, s188611; GFX9-NEXT: s_mul_hi_u32 s13, s14, s168612; GFX9-NEXT: s_addc_u32 s12, s19, s178613; GFX9-NEXT: s_addc_u32 s13, s13, 08614; GFX9-NEXT: s_mul_i32 s16, s14, s168615; GFX9-NEXT: s_add_u32 s12, s12, s168616; GFX9-NEXT: s_addc_u32 s13, 0, s138617; GFX9-NEXT: s_add_u32 s15, s15, s128618; GFX9-NEXT: s_addc_u32 s14, s14, s138619; GFX9-NEXT: s_ashr_i32 s12, s9, 318620; GFX9-NEXT: s_add_u32 s8, s8, s128621; GFX9-NEXT: s_mov_b32 s13, s128622; GFX9-NEXT: s_addc_u32 s9, s9, s128623; GFX9-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]8624; GFX9-NEXT: s_mul_i32 s17, s8, s148625; GFX9-NEXT: s_mul_hi_u32 s18, s8, s158626; GFX9-NEXT: s_mul_hi_u32 s16, s8, s148627; GFX9-NEXT: s_add_u32 s17, s18, s178628; GFX9-NEXT: s_addc_u32 s16, 0, s168629; GFX9-NEXT: s_mul_hi_u32 s19, s9, s158630; GFX9-NEXT: s_mul_i32 s15, s9, s158631; GFX9-NEXT: s_add_u32 s15, s17, s158632; GFX9-NEXT: s_mul_hi_u32 s18, s9, s148633; GFX9-NEXT: s_addc_u32 s15, s16, s198634; GFX9-NEXT: s_addc_u32 s16, s18, 08635; GFX9-NEXT: s_mul_i32 s14, s9, s148636; GFX9-NEXT: s_add_u32 s17, s15, s148637; GFX9-NEXT: s_addc_u32 s16, 0, s168638; GFX9-NEXT: s_mul_i32 s14, s6, s168639; GFX9-NEXT: s_mul_hi_u32 s15, s6, s178640; GFX9-NEXT: s_add_i32 s14, s15, s148641; GFX9-NEXT: s_mul_i32 s15, s7, s178642; GFX9-NEXT: s_add_i32 s18, s14, s158643; GFX9-NEXT: s_sub_i32 s19, s9, s188644; GFX9-NEXT: s_mul_i32 s14, s6, s178645; GFX9-NEXT: s_sub_u32 s8, s8, s148646; GFX9-NEXT: s_cselect_b64 s[14:15], -1, 08647; GFX9-NEXT: s_subb_u32 s19, s19, s78648; GFX9-NEXT: s_sub_u32 s20, s8, s68649; GFX9-NEXT: s_subb_u32 s19, s19, 08650; GFX9-NEXT: s_cmp_ge_u32 s19, s78651; GFX9-NEXT: s_cselect_b32 s21, -1, 08652; GFX9-NEXT: s_cmp_ge_u32 s20, s68653; GFX9-NEXT: s_cselect_b32 s20, -1, 08654; GFX9-NEXT: s_cmp_eq_u32 s19, s78655; GFX9-NEXT: s_cselect_b32 s19, s20, s218656; GFX9-NEXT: s_add_u32 s20, s17, 18657; GFX9-NEXT: s_addc_u32 s21, s16, 08658; GFX9-NEXT: s_add_u32 s22, s17, 28659; GFX9-NEXT: s_addc_u32 s23, s16, 08660; GFX9-NEXT: s_cmp_lg_u32 s19, 08661; GFX9-NEXT: s_cselect_b32 s19, s22, s208662; GFX9-NEXT: s_cselect_b32 s20, s23, s218663; GFX9-NEXT: s_cmp_lg_u64 s[14:15], 08664; GFX9-NEXT: s_subb_u32 s9, s9, s188665; GFX9-NEXT: s_cmp_ge_u32 s9, s78666; GFX9-NEXT: s_cselect_b32 s14, -1, 08667; GFX9-NEXT: s_cmp_ge_u32 s8, s68668; GFX9-NEXT: s_cselect_b32 s6, -1, 08669; GFX9-NEXT: s_cmp_eq_u32 s9, s78670; GFX9-NEXT: s_cselect_b32 s6, s6, s148671; GFX9-NEXT: s_cmp_lg_u32 s6, 08672; GFX9-NEXT: s_cselect_b32 s7, s20, s168673; GFX9-NEXT: s_cselect_b32 s6, s19, s178674; GFX9-NEXT: s_xor_b64 s[2:3], s[12:13], s[2:3]8675; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[2:3]8676; GFX9-NEXT: s_sub_u32 s12, s6, s28677; GFX9-NEXT: s_subb_u32 s13, s7, s38678; GFX9-NEXT: s_ashr_i32 s2, s1, 318679; GFX9-NEXT: s_add_u32 s0, s0, s28680; GFX9-NEXT: s_mov_b32 s3, s28681; GFX9-NEXT: s_addc_u32 s1, s1, s28682; GFX9-NEXT: s_xor_b64 s[6:7], s[0:1], s[2:3]8683; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s68684; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s78685; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x248686; GFX9-NEXT: s_sub_u32 s4, 0, s68687; GFX9-NEXT: s_subb_u32 s5, 0, s78688; GFX9-NEXT: v_mac_f32_e32 v0, 0x4f800000, v18689; GFX9-NEXT: v_rcp_f32_e32 v1, v08690; GFX9-NEXT: v_mov_b32_e32 v0, 08691; GFX9-NEXT: v_mul_f32_e32 v1, 0x5f7ffffc, v18692; GFX9-NEXT: v_mul_f32_e32 v2, 0x2f800000, v18693; GFX9-NEXT: v_trunc_f32_e32 v2, v28694; GFX9-NEXT: v_mac_f32_e32 v1, 0xcf800000, v28695; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v18696; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v28697; GFX9-NEXT: v_readfirstlane_b32 s8, v18698; GFX9-NEXT: v_readfirstlane_b32 s15, v28699; GFX9-NEXT: s_mul_hi_u32 s14, s4, s88700; GFX9-NEXT: s_mul_i32 s16, s4, s158701; GFX9-NEXT: s_mul_i32 s9, s5, s88702; GFX9-NEXT: s_add_i32 s14, s14, s168703; GFX9-NEXT: s_add_i32 s14, s14, s98704; GFX9-NEXT: s_mul_i32 s17, s4, s88705; GFX9-NEXT: s_mul_i32 s16, s8, s148706; GFX9-NEXT: s_mul_hi_u32 s18, s8, s178707; GFX9-NEXT: s_mul_hi_u32 s9, s8, s148708; GFX9-NEXT: s_add_u32 s16, s18, s168709; GFX9-NEXT: s_addc_u32 s9, 0, s98710; GFX9-NEXT: s_mul_hi_u32 s19, s15, s178711; GFX9-NEXT: s_mul_i32 s17, s15, s178712; GFX9-NEXT: s_add_u32 s16, s16, s178713; GFX9-NEXT: s_mul_hi_u32 s18, s15, s148714; GFX9-NEXT: s_addc_u32 s9, s9, s198715; GFX9-NEXT: s_addc_u32 s16, s18, 08716; GFX9-NEXT: s_mul_i32 s14, s15, s148717; GFX9-NEXT: s_add_u32 s9, s9, s148718; GFX9-NEXT: s_addc_u32 s14, 0, s168719; GFX9-NEXT: s_add_u32 s8, s8, s98720; GFX9-NEXT: s_addc_u32 s9, s15, s148721; GFX9-NEXT: s_mul_i32 s14, s4, s98722; GFX9-NEXT: s_mul_hi_u32 s15, s4, s88723; GFX9-NEXT: s_add_i32 s14, s15, s148724; GFX9-NEXT: s_mul_i32 s5, s5, s88725; GFX9-NEXT: s_add_i32 s14, s14, s58726; GFX9-NEXT: s_mul_i32 s4, s4, s88727; GFX9-NEXT: s_mul_hi_u32 s15, s9, s48728; GFX9-NEXT: s_mul_i32 s16, s9, s48729; GFX9-NEXT: s_mul_i32 s18, s8, s148730; GFX9-NEXT: s_mul_hi_u32 s4, s8, s48731; GFX9-NEXT: s_mul_hi_u32 s17, s8, s148732; GFX9-NEXT: s_add_u32 s4, s4, s188733; GFX9-NEXT: s_addc_u32 s17, 0, s178734; GFX9-NEXT: s_add_u32 s4, s4, s168735; GFX9-NEXT: s_mul_hi_u32 s5, s9, s148736; GFX9-NEXT: s_addc_u32 s4, s17, s158737; GFX9-NEXT: s_addc_u32 s5, s5, 08738; GFX9-NEXT: s_mul_i32 s14, s9, s148739; GFX9-NEXT: s_add_u32 s4, s4, s148740; GFX9-NEXT: s_addc_u32 s5, 0, s58741; GFX9-NEXT: s_add_u32 s14, s8, s48742; GFX9-NEXT: s_addc_u32 s15, s9, s58743; GFX9-NEXT: s_ashr_i32 s4, s11, 318744; GFX9-NEXT: s_add_u32 s8, s10, s48745; GFX9-NEXT: s_mov_b32 s5, s48746; GFX9-NEXT: s_addc_u32 s9, s11, s48747; GFX9-NEXT: s_xor_b64 s[8:9], s[8:9], s[4:5]8748; GFX9-NEXT: s_mul_i32 s11, s8, s158749; GFX9-NEXT: s_mul_hi_u32 s16, s8, s148750; GFX9-NEXT: s_mul_hi_u32 s10, s8, s158751; GFX9-NEXT: s_add_u32 s11, s16, s118752; GFX9-NEXT: s_addc_u32 s10, 0, s108753; GFX9-NEXT: s_mul_hi_u32 s17, s9, s148754; GFX9-NEXT: s_mul_i32 s14, s9, s148755; GFX9-NEXT: s_add_u32 s11, s11, s148756; GFX9-NEXT: s_mul_hi_u32 s16, s9, s158757; GFX9-NEXT: s_addc_u32 s10, s10, s178758; GFX9-NEXT: s_addc_u32 s11, s16, 08759; GFX9-NEXT: s_mul_i32 s14, s9, s158760; GFX9-NEXT: s_add_u32 s14, s10, s148761; GFX9-NEXT: s_addc_u32 s15, 0, s118762; GFX9-NEXT: s_mul_i32 s10, s6, s158763; GFX9-NEXT: s_mul_hi_u32 s11, s6, s148764; GFX9-NEXT: s_add_i32 s10, s11, s108765; GFX9-NEXT: s_mul_i32 s11, s7, s148766; GFX9-NEXT: s_add_i32 s16, s10, s118767; GFX9-NEXT: s_sub_i32 s17, s9, s168768; GFX9-NEXT: s_mul_i32 s10, s6, s148769; GFX9-NEXT: s_sub_u32 s8, s8, s108770; GFX9-NEXT: s_cselect_b64 s[10:11], -1, 08771; GFX9-NEXT: s_subb_u32 s17, s17, s78772; GFX9-NEXT: s_sub_u32 s18, s8, s68773; GFX9-NEXT: s_subb_u32 s17, s17, 08774; GFX9-NEXT: s_cmp_ge_u32 s17, s78775; GFX9-NEXT: s_cselect_b32 s19, -1, 08776; GFX9-NEXT: s_cmp_ge_u32 s18, s68777; GFX9-NEXT: s_cselect_b32 s18, -1, 08778; GFX9-NEXT: s_cmp_eq_u32 s17, s78779; GFX9-NEXT: s_cselect_b32 s17, s18, s198780; GFX9-NEXT: s_add_u32 s18, s14, 18781; GFX9-NEXT: s_addc_u32 s19, s15, 08782; GFX9-NEXT: s_add_u32 s20, s14, 28783; GFX9-NEXT: s_addc_u32 s21, s15, 08784; GFX9-NEXT: s_cmp_lg_u32 s17, 08785; GFX9-NEXT: s_cselect_b32 s17, s20, s188786; GFX9-NEXT: s_cselect_b32 s18, s21, s198787; GFX9-NEXT: s_cmp_lg_u64 s[10:11], 08788; GFX9-NEXT: s_subb_u32 s9, s9, s168789; GFX9-NEXT: s_cmp_ge_u32 s9, s78790; GFX9-NEXT: s_cselect_b32 s10, -1, 08791; GFX9-NEXT: s_cmp_ge_u32 s8, s68792; GFX9-NEXT: s_cselect_b32 s6, -1, 08793; GFX9-NEXT: s_cmp_eq_u32 s9, s78794; GFX9-NEXT: s_cselect_b32 s6, s6, s108795; GFX9-NEXT: s_cmp_lg_u32 s6, 08796; GFX9-NEXT: s_cselect_b32 s7, s18, s158797; GFX9-NEXT: s_cselect_b32 s6, s17, s148798; GFX9-NEXT: s_xor_b64 s[2:3], s[4:5], s[2:3]8799; GFX9-NEXT: s_xor_b64 s[4:5], s[6:7], s[2:3]8800; GFX9-NEXT: s_sub_u32 s2, s4, s28801; GFX9-NEXT: s_subb_u32 s3, s5, s38802; GFX9-NEXT: v_mov_b32_e32 v1, s128803; GFX9-NEXT: v_mov_b32_e32 v2, s138804; GFX9-NEXT: v_mov_b32_e32 v3, s28805; GFX9-NEXT: v_mov_b32_e32 v4, s38806; GFX9-NEXT: s_waitcnt lgkmcnt(0)8807; GFX9-NEXT: global_store_dwordx4 v0, v[1:4], s[0:1]8808; GFX9-NEXT: s_endpgm8809 %shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y8810 %r = sdiv <2 x i64> %x, %shl.y8811 store <2 x i64> %r, ptr addrspace(1) %out8812 ret void8813}8814 8815define amdgpu_kernel void @srem_i64_oddk_denom(ptr addrspace(1) %out, i64 %x) {8816; CHECK-LABEL: @srem_i64_oddk_denom(8817; CHECK-NEXT: [[R:%.*]] = srem i64 [[X:%.*]], 12351958818; CHECK-NEXT: store i64 [[R]], ptr addrspace(1) [[OUT:%.*]], align 88819; CHECK-NEXT: ret void8820;8821; GFX6-LABEL: srem_i64_oddk_denom:8822; GFX6: ; %bb.0:8823; GFX6-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x98824; GFX6-NEXT: v_mov_b32_e32 v2, 0xfd81e198825; GFX6-NEXT: v_mov_b32_e32 v0, 0x6ca942208826; GFX6-NEXT: s_mov_b32 s3, 0xf0008827; GFX6-NEXT: s_mov_b32 s2, -18828; GFX6-NEXT: s_waitcnt lgkmcnt(0)8829; GFX6-NEXT: v_mul_hi_u32 v3, s6, v28830; GFX6-NEXT: v_mul_hi_u32 v4, s7, v28831; GFX6-NEXT: s_mov_b32 s0, s48832; GFX6-NEXT: v_mul_hi_u32 v1, s6, v08833; GFX6-NEXT: s_mul_i32 s4, s7, 0xfd81e198834; GFX6-NEXT: v_add_i32_e32 v3, vcc, s4, v38835; GFX6-NEXT: s_mul_i32 s1, s6, 0x6ca942208836; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc8837; GFX6-NEXT: s_ashr_i32 s4, s7, 318838; GFX6-NEXT: v_add_i32_e32 v3, vcc, s1, v38839; GFX6-NEXT: v_mul_hi_u32 v0, s7, v08840; GFX6-NEXT: v_mul_hi_u32 v2, s4, v28841; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc8842; GFX6-NEXT: v_add_i32_e32 v1, vcc, v4, v18843; GFX6-NEXT: s_mul_i32 s1, s7, 0x6ca942208844; GFX6-NEXT: v_addc_u32_e64 v3, s[8:9], 0, 0, vcc8845; GFX6-NEXT: v_add_i32_e32 v1, vcc, s1, v18846; GFX6-NEXT: s_mul_i32 s1, s4, 0x6ca942208847; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v0, v3, vcc8848; GFX6-NEXT: v_add_i32_e32 v0, vcc, s1, v28849; GFX6-NEXT: s_mul_i32 s4, s4, 0xfd81e198850; GFX6-NEXT: v_add_i32_e32 v2, vcc, s4, v08851; GFX6-NEXT: v_add_i32_e32 v0, vcc, s4, v18852; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v3, v2, vcc8853; GFX6-NEXT: v_ashr_i64 v[2:3], v[0:1], 198854; GFX6-NEXT: v_lshrrev_b32_e32 v0, 31, v18855; GFX6-NEXT: v_add_i32_e32 v0, vcc, v2, v08856; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc8857; GFX6-NEXT: s_mov_b32 s4, 0x12d8fb8858; GFX6-NEXT: v_mul_lo_u32 v1, v1, s48859; GFX6-NEXT: v_mul_hi_u32 v2, v0, s48860; GFX6-NEXT: v_mul_lo_u32 v0, v0, s48861; GFX6-NEXT: s_mov_b32 s1, s58862; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v28863; GFX6-NEXT: v_mov_b32_e32 v2, s78864; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s6, v08865; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc8866; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 08867; GFX6-NEXT: s_endpgm8868;8869; GFX9-LABEL: srem_i64_oddk_denom:8870; GFX9: ; %bb.0:8871; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x248872; GFX9-NEXT: v_mov_b32_e32 v2, 08873; GFX9-NEXT: s_waitcnt lgkmcnt(0)8874; GFX9-NEXT: s_mul_i32 s7, s3, 0xfd81e198875; GFX9-NEXT: s_mul_hi_u32 s8, s2, 0xfd81e198876; GFX9-NEXT: s_mul_hi_u32 s6, s3, 0xfd81e198877; GFX9-NEXT: s_add_u32 s7, s7, s88878; GFX9-NEXT: s_mul_i32 s5, s2, 0x6ca942208879; GFX9-NEXT: s_addc_u32 s6, s6, 08880; GFX9-NEXT: s_mul_hi_u32 s4, s2, 0x6ca942208881; GFX9-NEXT: s_add_u32 s5, s5, s78882; GFX9-NEXT: s_addc_u32 s4, s4, 08883; GFX9-NEXT: s_add_u32 s4, s6, s48884; GFX9-NEXT: s_addc_u32 s5, 0, 08885; GFX9-NEXT: s_mul_i32 s7, s3, 0x6ca942208886; GFX9-NEXT: s_mul_hi_u32 s6, s3, 0x6ca942208887; GFX9-NEXT: s_add_u32 s4, s7, s48888; GFX9-NEXT: s_addc_u32 s5, s6, s58889; GFX9-NEXT: s_ashr_i32 s6, s3, 318890; GFX9-NEXT: s_mul_i32 s7, s6, 0x6ca942208891; GFX9-NEXT: s_mul_hi_u32 s8, s6, 0xfd81e198892; GFX9-NEXT: s_add_i32 s7, s8, s78893; GFX9-NEXT: s_mul_i32 s6, s6, 0xfd81e198894; GFX9-NEXT: s_add_i32 s7, s7, s68895; GFX9-NEXT: s_add_u32 s4, s4, s68896; GFX9-NEXT: s_addc_u32 s5, s5, s78897; GFX9-NEXT: s_ashr_i64 s[6:7], s[4:5], 198898; GFX9-NEXT: s_lshr_b32 s4, s5, 318899; GFX9-NEXT: s_add_u32 s4, s6, s48900; GFX9-NEXT: s_addc_u32 s5, s7, 08901; GFX9-NEXT: s_mul_i32 s5, s5, 0x12d8fb8902; GFX9-NEXT: s_mul_hi_u32 s6, s4, 0x12d8fb8903; GFX9-NEXT: s_add_i32 s6, s6, s58904; GFX9-NEXT: s_mul_i32 s4, s4, 0x12d8fb8905; GFX9-NEXT: s_sub_u32 s2, s2, s48906; GFX9-NEXT: s_subb_u32 s3, s3, s68907; GFX9-NEXT: v_mov_b32_e32 v0, s28908; GFX9-NEXT: v_mov_b32_e32 v1, s38909; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]8910; GFX9-NEXT: s_endpgm8911 %r = srem i64 %x, 12351958912 store i64 %r, ptr addrspace(1) %out8913 ret void8914}8915 8916define amdgpu_kernel void @srem_i64_pow2k_denom(ptr addrspace(1) %out, i64 %x) {8917; CHECK-LABEL: @srem_i64_pow2k_denom(8918; CHECK-NEXT: [[R:%.*]] = srem i64 [[X:%.*]], 40968919; CHECK-NEXT: store i64 [[R]], ptr addrspace(1) [[OUT:%.*]], align 88920; CHECK-NEXT: ret void8921;8922; GFX6-LABEL: srem_i64_pow2k_denom:8923; GFX6: ; %bb.0:8924; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x98925; GFX6-NEXT: s_mov_b32 s7, 0xf0008926; GFX6-NEXT: s_mov_b32 s6, -18927; GFX6-NEXT: s_waitcnt lgkmcnt(0)8928; GFX6-NEXT: s_mov_b32 s4, s08929; GFX6-NEXT: s_ashr_i32 s0, s3, 318930; GFX6-NEXT: s_lshr_b32 s0, s0, 208931; GFX6-NEXT: s_add_u32 s0, s2, s08932; GFX6-NEXT: s_mov_b32 s5, s18933; GFX6-NEXT: s_addc_u32 s1, s3, 08934; GFX6-NEXT: s_and_b32 s0, s0, 0xfffff0008935; GFX6-NEXT: s_sub_u32 s0, s2, s08936; GFX6-NEXT: s_subb_u32 s1, s3, s18937; GFX6-NEXT: v_mov_b32_e32 v0, s08938; GFX6-NEXT: v_mov_b32_e32 v1, s18939; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 08940; GFX6-NEXT: s_endpgm8941;8942; GFX9-LABEL: srem_i64_pow2k_denom:8943; GFX9: ; %bb.0:8944; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x248945; GFX9-NEXT: v_mov_b32_e32 v2, 08946; GFX9-NEXT: s_waitcnt lgkmcnt(0)8947; GFX9-NEXT: s_ashr_i32 s4, s3, 318948; GFX9-NEXT: s_lshr_b32 s4, s4, 208949; GFX9-NEXT: s_add_u32 s4, s2, s48950; GFX9-NEXT: s_addc_u32 s5, s3, 08951; GFX9-NEXT: s_and_b32 s4, s4, 0xfffff0008952; GFX9-NEXT: s_sub_u32 s2, s2, s48953; GFX9-NEXT: s_subb_u32 s3, s3, s58954; GFX9-NEXT: v_mov_b32_e32 v0, s28955; GFX9-NEXT: v_mov_b32_e32 v1, s38956; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]8957; GFX9-NEXT: s_endpgm8958 %r = srem i64 %x, 40968959 store i64 %r, ptr addrspace(1) %out8960 ret void8961}8962 8963define amdgpu_kernel void @srem_i64_pow2_shl_denom(ptr addrspace(1) %out, i64 %x, i64 %y) {8964; CHECK-LABEL: @srem_i64_pow2_shl_denom(8965; CHECK-NEXT: [[SHL_Y:%.*]] = shl i64 4096, [[Y:%.*]]8966; CHECK-NEXT: [[R:%.*]] = srem i64 [[X:%.*]], [[SHL_Y]]8967; CHECK-NEXT: store i64 [[R]], ptr addrspace(1) [[OUT:%.*]], align 88968; CHECK-NEXT: ret void8969;8970; GFX6-LABEL: srem_i64_pow2_shl_denom:8971; GFX6: ; %bb.0:8972; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xd8973; GFX6-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x98974; GFX6-NEXT: s_waitcnt lgkmcnt(0)8975; GFX6-NEXT: s_lshl_b64 s[0:1], 0x1000, s08976; GFX6-NEXT: s_ashr_i32 s2, s1, 318977; GFX6-NEXT: s_add_u32 s0, s0, s28978; GFX6-NEXT: s_mov_b32 s3, s28979; GFX6-NEXT: s_addc_u32 s1, s1, s28980; GFX6-NEXT: s_xor_b64 s[8:9], s[0:1], s[2:3]8981; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s88982; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s98983; GFX6-NEXT: s_sub_u32 s0, 0, s88984; GFX6-NEXT: s_subb_u32 s1, 0, s98985; GFX6-NEXT: s_mov_b32 s3, 0xf0008986; GFX6-NEXT: v_madmk_f32 v0, v1, 0x4f800000, v08987; GFX6-NEXT: v_rcp_f32_e32 v0, v08988; GFX6-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v08989; GFX6-NEXT: v_mul_f32_e32 v1, 0x2f800000, v08990; GFX6-NEXT: v_trunc_f32_e32 v1, v18991; GFX6-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v08992; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v08993; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v18994; GFX6-NEXT: v_mul_hi_u32 v2, s0, v08995; GFX6-NEXT: v_readfirstlane_b32 s10, v18996; GFX6-NEXT: v_readfirstlane_b32 s2, v08997; GFX6-NEXT: s_mul_i32 s11, s0, s108998; GFX6-NEXT: v_readfirstlane_b32 s14, v28999; GFX6-NEXT: s_mul_i32 s12, s1, s29000; GFX6-NEXT: s_mul_i32 s13, s0, s29001; GFX6-NEXT: s_add_i32 s11, s14, s119002; GFX6-NEXT: v_mul_hi_u32 v3, v0, s139003; GFX6-NEXT: s_add_i32 s11, s11, s129004; GFX6-NEXT: v_mul_hi_u32 v0, v0, s119005; GFX6-NEXT: v_mul_hi_u32 v4, v1, s139006; GFX6-NEXT: v_readfirstlane_b32 s12, v39007; GFX6-NEXT: s_mul_i32 s14, s2, s119008; GFX6-NEXT: v_mul_hi_u32 v1, v1, s119009; GFX6-NEXT: s_add_u32 s12, s12, s149010; GFX6-NEXT: v_readfirstlane_b32 s14, v09011; GFX6-NEXT: s_mul_i32 s13, s10, s139012; GFX6-NEXT: s_addc_u32 s14, 0, s149013; GFX6-NEXT: v_readfirstlane_b32 s15, v49014; GFX6-NEXT: s_add_u32 s12, s12, s139015; GFX6-NEXT: s_addc_u32 s12, s14, s159016; GFX6-NEXT: v_readfirstlane_b32 s13, v19017; GFX6-NEXT: s_addc_u32 s13, s13, 09018; GFX6-NEXT: s_mul_i32 s11, s10, s119019; GFX6-NEXT: s_add_u32 s11, s12, s119020; GFX6-NEXT: s_addc_u32 s12, 0, s139021; GFX6-NEXT: s_add_u32 s11, s2, s119022; GFX6-NEXT: v_mov_b32_e32 v0, s119023; GFX6-NEXT: v_mul_hi_u32 v0, s0, v09024; GFX6-NEXT: s_addc_u32 s10, s10, s129025; GFX6-NEXT: s_mul_i32 s12, s0, s109026; GFX6-NEXT: s_mul_i32 s1, s1, s119027; GFX6-NEXT: v_readfirstlane_b32 s13, v09028; GFX6-NEXT: s_add_i32 s12, s13, s129029; GFX6-NEXT: s_mul_i32 s0, s0, s119030; GFX6-NEXT: s_add_i32 s1, s12, s19031; GFX6-NEXT: v_mov_b32_e32 v2, s09032; GFX6-NEXT: v_mov_b32_e32 v0, s19033; GFX6-NEXT: v_mul_hi_u32 v3, s10, v29034; GFX6-NEXT: v_mul_hi_u32 v2, s11, v29035; GFX6-NEXT: v_mul_hi_u32 v1, s10, v09036; GFX6-NEXT: v_mul_hi_u32 v0, s11, v09037; GFX6-NEXT: s_mul_i32 s13, s11, s19038; GFX6-NEXT: v_readfirstlane_b32 s15, v29039; GFX6-NEXT: s_add_u32 s13, s15, s139040; GFX6-NEXT: v_readfirstlane_b32 s14, v09041; GFX6-NEXT: s_mul_i32 s0, s10, s09042; GFX6-NEXT: s_addc_u32 s14, 0, s149043; GFX6-NEXT: v_readfirstlane_b32 s12, v39044; GFX6-NEXT: s_add_u32 s0, s13, s09045; GFX6-NEXT: s_addc_u32 s0, s14, s129046; GFX6-NEXT: v_readfirstlane_b32 s12, v19047; GFX6-NEXT: s_addc_u32 s12, s12, 09048; GFX6-NEXT: s_mul_i32 s1, s10, s19049; GFX6-NEXT: s_add_u32 s0, s0, s19050; GFX6-NEXT: s_addc_u32 s1, 0, s129051; GFX6-NEXT: s_add_u32 s12, s11, s09052; GFX6-NEXT: s_addc_u32 s13, s10, s19053; GFX6-NEXT: s_ashr_i32 s10, s7, 319054; GFX6-NEXT: s_add_u32 s0, s6, s109055; GFX6-NEXT: s_mov_b32 s11, s109056; GFX6-NEXT: s_addc_u32 s1, s7, s109057; GFX6-NEXT: s_xor_b64 s[6:7], s[0:1], s[10:11]9058; GFX6-NEXT: v_mov_b32_e32 v0, s139059; GFX6-NEXT: v_mul_hi_u32 v1, s6, v09060; GFX6-NEXT: v_mov_b32_e32 v2, s129061; GFX6-NEXT: v_mul_hi_u32 v3, s6, v29062; GFX6-NEXT: s_mov_b32 s0, s49063; GFX6-NEXT: v_readfirstlane_b32 s4, v19064; GFX6-NEXT: v_mul_hi_u32 v1, s7, v29065; GFX6-NEXT: s_mul_i32 s1, s6, s139066; GFX6-NEXT: v_readfirstlane_b32 s14, v39067; GFX6-NEXT: v_mul_hi_u32 v0, s7, v09068; GFX6-NEXT: s_add_u32 s1, s14, s19069; GFX6-NEXT: s_addc_u32 s4, 0, s49070; GFX6-NEXT: s_mul_i32 s12, s7, s129071; GFX6-NEXT: v_readfirstlane_b32 s14, v19072; GFX6-NEXT: s_add_u32 s1, s1, s129073; GFX6-NEXT: s_addc_u32 s1, s4, s149074; GFX6-NEXT: v_readfirstlane_b32 s4, v09075; GFX6-NEXT: s_addc_u32 s4, s4, 09076; GFX6-NEXT: s_mul_i32 s12, s7, s139077; GFX6-NEXT: s_add_u32 s12, s1, s129078; GFX6-NEXT: v_mov_b32_e32 v0, s129079; GFX6-NEXT: v_mul_hi_u32 v0, s8, v09080; GFX6-NEXT: s_addc_u32 s4, 0, s49081; GFX6-NEXT: s_mov_b32 s1, s59082; GFX6-NEXT: s_mul_i32 s4, s8, s49083; GFX6-NEXT: v_readfirstlane_b32 s5, v09084; GFX6-NEXT: s_add_i32 s4, s5, s49085; GFX6-NEXT: s_mul_i32 s5, s9, s129086; GFX6-NEXT: s_add_i32 s14, s4, s59087; GFX6-NEXT: s_sub_i32 s13, s7, s149088; GFX6-NEXT: s_mul_i32 s4, s8, s129089; GFX6-NEXT: s_sub_u32 s6, s6, s49090; GFX6-NEXT: s_cselect_b64 s[4:5], -1, 09091; GFX6-NEXT: s_subb_u32 s15, s13, s99092; GFX6-NEXT: s_sub_u32 s16, s6, s89093; GFX6-NEXT: s_cselect_b64 s[12:13], -1, 09094; GFX6-NEXT: s_subb_u32 s17, s15, 09095; GFX6-NEXT: s_cmp_ge_u32 s17, s99096; GFX6-NEXT: s_cselect_b32 s18, -1, 09097; GFX6-NEXT: s_cmp_ge_u32 s16, s89098; GFX6-NEXT: s_cselect_b32 s19, -1, 09099; GFX6-NEXT: s_cmp_eq_u32 s17, s99100; GFX6-NEXT: s_cselect_b32 s18, s19, s189101; GFX6-NEXT: s_or_b32 s12, s12, s139102; GFX6-NEXT: s_subb_u32 s12, s15, s99103; GFX6-NEXT: s_sub_u32 s13, s16, s89104; GFX6-NEXT: s_subb_u32 s12, s12, 09105; GFX6-NEXT: s_cmp_lg_u32 s18, 09106; GFX6-NEXT: s_cselect_b32 s13, s13, s169107; GFX6-NEXT: s_cselect_b32 s12, s12, s179108; GFX6-NEXT: s_or_b32 s4, s4, s59109; GFX6-NEXT: s_subb_u32 s4, s7, s149110; GFX6-NEXT: s_cmp_ge_u32 s4, s99111; GFX6-NEXT: s_cselect_b32 s5, -1, 09112; GFX6-NEXT: s_cmp_ge_u32 s6, s89113; GFX6-NEXT: s_cselect_b32 s7, -1, 09114; GFX6-NEXT: s_cmp_eq_u32 s4, s99115; GFX6-NEXT: s_cselect_b32 s5, s7, s59116; GFX6-NEXT: s_cmp_lg_u32 s5, 09117; GFX6-NEXT: s_cselect_b32 s5, s12, s49118; GFX6-NEXT: s_cselect_b32 s4, s13, s69119; GFX6-NEXT: s_xor_b64 s[4:5], s[4:5], s[10:11]9120; GFX6-NEXT: s_sub_u32 s4, s4, s109121; GFX6-NEXT: s_subb_u32 s5, s5, s109122; GFX6-NEXT: v_mov_b32_e32 v0, s49123; GFX6-NEXT: s_mov_b32 s2, -19124; GFX6-NEXT: v_mov_b32_e32 v1, s59125; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 09126; GFX6-NEXT: s_endpgm9127;9128; GFX9-LABEL: srem_i64_pow2_shl_denom:9129; GFX9: ; %bb.0:9130; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x349131; GFX9-NEXT: s_waitcnt lgkmcnt(0)9132; GFX9-NEXT: s_lshl_b64 s[0:1], 0x1000, s09133; GFX9-NEXT: s_ashr_i32 s2, s1, 319134; GFX9-NEXT: s_add_u32 s0, s0, s29135; GFX9-NEXT: s_mov_b32 s3, s29136; GFX9-NEXT: s_addc_u32 s1, s1, s29137; GFX9-NEXT: s_xor_b64 s[6:7], s[0:1], s[2:3]9138; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s69139; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s79140; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x249141; GFX9-NEXT: s_sub_u32 s4, 0, s69142; GFX9-NEXT: s_subb_u32 s5, 0, s79143; GFX9-NEXT: v_madmk_f32 v0, v1, 0x4f800000, v09144; GFX9-NEXT: v_rcp_f32_e32 v1, v09145; GFX9-NEXT: v_mov_b32_e32 v0, 09146; GFX9-NEXT: v_mul_f32_e32 v1, 0x5f7ffffc, v19147; GFX9-NEXT: v_mul_f32_e32 v2, 0x2f800000, v19148; GFX9-NEXT: v_trunc_f32_e32 v2, v29149; GFX9-NEXT: v_madmk_f32 v1, v2, 0xcf800000, v19150; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v29151; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v19152; GFX9-NEXT: v_readfirstlane_b32 s8, v29153; GFX9-NEXT: v_readfirstlane_b32 s9, v19154; GFX9-NEXT: s_mul_i32 s10, s4, s89155; GFX9-NEXT: s_mul_hi_u32 s12, s4, s99156; GFX9-NEXT: s_mul_i32 s11, s5, s99157; GFX9-NEXT: s_add_i32 s10, s12, s109158; GFX9-NEXT: s_mul_i32 s13, s4, s99159; GFX9-NEXT: s_add_i32 s10, s10, s119160; GFX9-NEXT: s_mul_hi_u32 s12, s9, s139161; GFX9-NEXT: s_mul_i32 s14, s9, s109162; GFX9-NEXT: s_mul_hi_u32 s11, s9, s109163; GFX9-NEXT: s_add_u32 s12, s12, s149164; GFX9-NEXT: s_addc_u32 s11, 0, s119165; GFX9-NEXT: s_mul_hi_u32 s15, s8, s139166; GFX9-NEXT: s_mul_i32 s13, s8, s139167; GFX9-NEXT: s_add_u32 s12, s12, s139168; GFX9-NEXT: s_mul_hi_u32 s14, s8, s109169; GFX9-NEXT: s_addc_u32 s11, s11, s159170; GFX9-NEXT: s_addc_u32 s12, s14, 09171; GFX9-NEXT: s_mul_i32 s10, s8, s109172; GFX9-NEXT: s_add_u32 s10, s11, s109173; GFX9-NEXT: s_addc_u32 s11, 0, s129174; GFX9-NEXT: s_add_u32 s9, s9, s109175; GFX9-NEXT: s_addc_u32 s8, s8, s119176; GFX9-NEXT: s_mul_i32 s10, s4, s89177; GFX9-NEXT: s_mul_hi_u32 s11, s4, s99178; GFX9-NEXT: s_add_i32 s10, s11, s109179; GFX9-NEXT: s_mul_i32 s5, s5, s99180; GFX9-NEXT: s_add_i32 s10, s10, s59181; GFX9-NEXT: s_mul_i32 s4, s4, s99182; GFX9-NEXT: s_mul_hi_u32 s11, s8, s49183; GFX9-NEXT: s_mul_i32 s12, s8, s49184; GFX9-NEXT: s_mul_i32 s14, s9, s109185; GFX9-NEXT: s_mul_hi_u32 s4, s9, s49186; GFX9-NEXT: s_mul_hi_u32 s13, s9, s109187; GFX9-NEXT: s_add_u32 s4, s4, s149188; GFX9-NEXT: s_addc_u32 s13, 0, s139189; GFX9-NEXT: s_add_u32 s4, s4, s129190; GFX9-NEXT: s_mul_hi_u32 s5, s8, s109191; GFX9-NEXT: s_addc_u32 s4, s13, s119192; GFX9-NEXT: s_addc_u32 s5, s5, 09193; GFX9-NEXT: s_mul_i32 s10, s8, s109194; GFX9-NEXT: s_add_u32 s4, s4, s109195; GFX9-NEXT: s_addc_u32 s5, 0, s59196; GFX9-NEXT: s_add_u32 s9, s9, s49197; GFX9-NEXT: s_addc_u32 s8, s8, s59198; GFX9-NEXT: s_waitcnt lgkmcnt(0)9199; GFX9-NEXT: s_ashr_i32 s4, s3, 319200; GFX9-NEXT: s_add_u32 s2, s2, s49201; GFX9-NEXT: s_mov_b32 s5, s49202; GFX9-NEXT: s_addc_u32 s3, s3, s49203; GFX9-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5]9204; GFX9-NEXT: s_mul_i32 s11, s2, s89205; GFX9-NEXT: s_mul_hi_u32 s12, s2, s99206; GFX9-NEXT: s_mul_hi_u32 s10, s2, s89207; GFX9-NEXT: s_add_u32 s11, s12, s119208; GFX9-NEXT: s_addc_u32 s10, 0, s109209; GFX9-NEXT: s_mul_hi_u32 s13, s3, s99210; GFX9-NEXT: s_mul_i32 s9, s3, s99211; GFX9-NEXT: s_add_u32 s9, s11, s99212; GFX9-NEXT: s_mul_hi_u32 s12, s3, s89213; GFX9-NEXT: s_addc_u32 s9, s10, s139214; GFX9-NEXT: s_addc_u32 s10, s12, 09215; GFX9-NEXT: s_mul_i32 s8, s3, s89216; GFX9-NEXT: s_add_u32 s8, s9, s89217; GFX9-NEXT: s_addc_u32 s9, 0, s109218; GFX9-NEXT: s_mul_i32 s9, s6, s99219; GFX9-NEXT: s_mul_hi_u32 s10, s6, s89220; GFX9-NEXT: s_add_i32 s9, s10, s99221; GFX9-NEXT: s_mul_i32 s10, s7, s89222; GFX9-NEXT: s_add_i32 s12, s9, s109223; GFX9-NEXT: s_sub_i32 s10, s3, s129224; GFX9-NEXT: s_mul_i32 s8, s6, s89225; GFX9-NEXT: s_sub_u32 s2, s2, s89226; GFX9-NEXT: s_cselect_b64 s[8:9], -1, 09227; GFX9-NEXT: s_subb_u32 s13, s10, s79228; GFX9-NEXT: s_sub_u32 s14, s2, s69229; GFX9-NEXT: s_cselect_b64 s[10:11], -1, 09230; GFX9-NEXT: s_subb_u32 s15, s13, 09231; GFX9-NEXT: s_cmp_ge_u32 s15, s79232; GFX9-NEXT: s_cselect_b32 s16, -1, 09233; GFX9-NEXT: s_cmp_ge_u32 s14, s69234; GFX9-NEXT: s_cselect_b32 s17, -1, 09235; GFX9-NEXT: s_cmp_eq_u32 s15, s79236; GFX9-NEXT: s_cselect_b32 s16, s17, s169237; GFX9-NEXT: s_cmp_lg_u64 s[10:11], 09238; GFX9-NEXT: s_subb_u32 s10, s13, s79239; GFX9-NEXT: s_sub_u32 s11, s14, s69240; GFX9-NEXT: s_subb_u32 s10, s10, 09241; GFX9-NEXT: s_cmp_lg_u32 s16, 09242; GFX9-NEXT: s_cselect_b32 s11, s11, s149243; GFX9-NEXT: s_cselect_b32 s10, s10, s159244; GFX9-NEXT: s_cmp_lg_u64 s[8:9], 09245; GFX9-NEXT: s_subb_u32 s3, s3, s129246; GFX9-NEXT: s_cmp_ge_u32 s3, s79247; GFX9-NEXT: s_cselect_b32 s8, -1, 09248; GFX9-NEXT: s_cmp_ge_u32 s2, s69249; GFX9-NEXT: s_cselect_b32 s6, -1, 09250; GFX9-NEXT: s_cmp_eq_u32 s3, s79251; GFX9-NEXT: s_cselect_b32 s6, s6, s89252; GFX9-NEXT: s_cmp_lg_u32 s6, 09253; GFX9-NEXT: s_cselect_b32 s3, s10, s39254; GFX9-NEXT: s_cselect_b32 s2, s11, s29255; GFX9-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5]9256; GFX9-NEXT: s_sub_u32 s2, s2, s49257; GFX9-NEXT: s_subb_u32 s3, s3, s49258; GFX9-NEXT: v_mov_b32_e32 v1, s29259; GFX9-NEXT: v_mov_b32_e32 v2, s39260; GFX9-NEXT: global_store_dwordx2 v0, v[1:2], s[0:1]9261; GFX9-NEXT: s_endpgm9262 %shl.y = shl i64 4096, %y9263 %r = srem i64 %x, %shl.y9264 store i64 %r, ptr addrspace(1) %out9265 ret void9266}9267 9268define amdgpu_kernel void @srem_v2i64_pow2k_denom(ptr addrspace(1) %out, <2 x i64> %x) {9269; CHECK-LABEL: @srem_v2i64_pow2k_denom(9270; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i64> [[X:%.*]], i64 09271; CHECK-NEXT: [[TMP2:%.*]] = srem i64 [[TMP1]], 40969272; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i64> poison, i64 [[TMP2]], i64 09273; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[X]], i64 19274; CHECK-NEXT: [[TMP5:%.*]] = srem i64 [[TMP4]], 40969275; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i64> [[TMP3]], i64 [[TMP5]], i64 19276; CHECK-NEXT: store <2 x i64> [[TMP6]], ptr addrspace(1) [[OUT:%.*]], align 169277; CHECK-NEXT: ret void9278;9279; GFX6-LABEL: srem_v2i64_pow2k_denom:9280; GFX6: ; %bb.0:9281; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xd9282; GFX6-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x99283; GFX6-NEXT: s_mov_b32 s7, 0xf0009284; GFX6-NEXT: s_mov_b32 s6, -19285; GFX6-NEXT: s_waitcnt lgkmcnt(0)9286; GFX6-NEXT: s_ashr_i32 s8, s1, 319287; GFX6-NEXT: s_lshr_b32 s8, s8, 209288; GFX6-NEXT: s_add_u32 s8, s0, s89289; GFX6-NEXT: s_addc_u32 s9, s1, 09290; GFX6-NEXT: s_and_b32 s8, s8, 0xfffff0009291; GFX6-NEXT: s_sub_u32 s0, s0, s89292; GFX6-NEXT: s_subb_u32 s1, s1, s99293; GFX6-NEXT: s_ashr_i32 s8, s3, 319294; GFX6-NEXT: s_lshr_b32 s8, s8, 209295; GFX6-NEXT: s_add_u32 s8, s2, s89296; GFX6-NEXT: s_addc_u32 s9, s3, 09297; GFX6-NEXT: s_and_b32 s8, s8, 0xfffff0009298; GFX6-NEXT: s_sub_u32 s2, s2, s89299; GFX6-NEXT: s_subb_u32 s3, s3, s99300; GFX6-NEXT: v_mov_b32_e32 v0, s09301; GFX6-NEXT: v_mov_b32_e32 v1, s19302; GFX6-NEXT: v_mov_b32_e32 v2, s29303; GFX6-NEXT: v_mov_b32_e32 v3, s39304; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 09305; GFX6-NEXT: s_endpgm9306;9307; GFX9-LABEL: srem_v2i64_pow2k_denom:9308; GFX9: ; %bb.0:9309; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x349310; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x249311; GFX9-NEXT: v_mov_b32_e32 v4, 09312; GFX9-NEXT: s_waitcnt lgkmcnt(0)9313; GFX9-NEXT: s_ashr_i32 s4, s1, 319314; GFX9-NEXT: s_lshr_b32 s4, s4, 209315; GFX9-NEXT: s_add_u32 s4, s0, s49316; GFX9-NEXT: s_addc_u32 s5, s1, 09317; GFX9-NEXT: s_and_b32 s4, s4, 0xfffff0009318; GFX9-NEXT: s_sub_u32 s0, s0, s49319; GFX9-NEXT: s_subb_u32 s1, s1, s59320; GFX9-NEXT: s_ashr_i32 s4, s3, 319321; GFX9-NEXT: s_lshr_b32 s4, s4, 209322; GFX9-NEXT: s_add_u32 s4, s2, s49323; GFX9-NEXT: s_addc_u32 s5, s3, 09324; GFX9-NEXT: s_and_b32 s4, s4, 0xfffff0009325; GFX9-NEXT: s_sub_u32 s2, s2, s49326; GFX9-NEXT: s_subb_u32 s3, s3, s59327; GFX9-NEXT: v_mov_b32_e32 v0, s09328; GFX9-NEXT: v_mov_b32_e32 v1, s19329; GFX9-NEXT: v_mov_b32_e32 v2, s29330; GFX9-NEXT: v_mov_b32_e32 v3, s39331; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7]9332; GFX9-NEXT: s_endpgm9333 %r = srem <2 x i64> %x, <i64 4096, i64 4096>9334 store <2 x i64> %r, ptr addrspace(1) %out9335 ret void9336}9337 9338define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x i64> %x, <2 x i64> %y) {9339; CHECK-LABEL: @srem_v2i64_pow2_shl_denom(9340; CHECK-NEXT: [[SHL_Y:%.*]] = shl <2 x i64> splat (i64 4096), [[Y:%.*]]9341; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i64> [[X:%.*]], i64 09342; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 09343; CHECK-NEXT: [[TMP3:%.*]] = srem i64 [[TMP1]], [[TMP2]]9344; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i64> poison, i64 [[TMP3]], i64 09345; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i64> [[X]], i64 19346; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 19347; CHECK-NEXT: [[TMP7:%.*]] = srem i64 [[TMP5]], [[TMP6]]9348; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x i64> [[TMP4]], i64 [[TMP7]], i64 19349; CHECK-NEXT: store <2 x i64> [[TMP8]], ptr addrspace(1) [[OUT:%.*]], align 169350; CHECK-NEXT: ret void9351;9352; GFX6-LABEL: srem_v2i64_pow2_shl_denom:9353; GFX6: ; %bb.0:9354; GFX6-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0xd9355; GFX6-NEXT: s_waitcnt lgkmcnt(0)9356; GFX6-NEXT: s_lshl_b64 s[2:3], 0x1000, s129357; GFX6-NEXT: s_lshl_b64 s[0:1], 0x1000, s149358; GFX6-NEXT: s_ashr_i32 s6, s3, 319359; GFX6-NEXT: s_add_u32 s2, s2, s69360; GFX6-NEXT: s_mov_b32 s7, s69361; GFX6-NEXT: s_addc_u32 s3, s3, s69362; GFX6-NEXT: s_xor_b64 s[2:3], s[2:3], s[6:7]9363; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s29364; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s39365; GFX6-NEXT: s_sub_u32 s6, 0, s29366; GFX6-NEXT: s_subb_u32 s7, 0, s39367; GFX6-NEXT: v_mac_f32_e32 v0, 0x4f800000, v19368; GFX6-NEXT: v_rcp_f32_e32 v0, v09369; GFX6-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v09370; GFX6-NEXT: v_mul_f32_e32 v1, 0x2f800000, v09371; GFX6-NEXT: v_trunc_f32_e32 v1, v19372; GFX6-NEXT: v_mac_f32_e32 v0, 0xcf800000, v19373; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v09374; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v19375; GFX6-NEXT: v_mul_hi_u32 v2, s6, v09376; GFX6-NEXT: v_readfirstlane_b32 s12, v19377; GFX6-NEXT: v_readfirstlane_b32 s13, v09378; GFX6-NEXT: s_mul_i32 s14, s6, s129379; GFX6-NEXT: v_readfirstlane_b32 s17, v29380; GFX6-NEXT: s_mul_i32 s15, s7, s139381; GFX6-NEXT: s_mul_i32 s16, s6, s139382; GFX6-NEXT: s_add_i32 s14, s17, s149383; GFX6-NEXT: v_mul_hi_u32 v3, v0, s169384; GFX6-NEXT: s_add_i32 s14, s14, s159385; GFX6-NEXT: v_mul_hi_u32 v0, v0, s149386; GFX6-NEXT: v_mul_hi_u32 v4, v1, s169387; GFX6-NEXT: v_readfirstlane_b32 s15, v39388; GFX6-NEXT: s_mul_i32 s18, s13, s149389; GFX6-NEXT: v_mul_hi_u32 v1, v1, s149390; GFX6-NEXT: s_add_u32 s15, s15, s189391; GFX6-NEXT: v_readfirstlane_b32 s18, v09392; GFX6-NEXT: s_mul_i32 s16, s12, s169393; GFX6-NEXT: s_addc_u32 s18, 0, s189394; GFX6-NEXT: v_readfirstlane_b32 s17, v49395; GFX6-NEXT: s_add_u32 s15, s15, s169396; GFX6-NEXT: s_addc_u32 s15, s18, s179397; GFX6-NEXT: v_readfirstlane_b32 s16, v19398; GFX6-NEXT: s_addc_u32 s16, s16, 09399; GFX6-NEXT: s_mul_i32 s14, s12, s149400; GFX6-NEXT: s_add_u32 s14, s15, s149401; GFX6-NEXT: s_addc_u32 s15, 0, s169402; GFX6-NEXT: s_add_u32 s13, s13, s149403; GFX6-NEXT: v_mov_b32_e32 v0, s139404; GFX6-NEXT: v_mul_hi_u32 v0, s6, v09405; GFX6-NEXT: s_addc_u32 s12, s12, s159406; GFX6-NEXT: s_mul_i32 s14, s6, s129407; GFX6-NEXT: s_mul_i32 s7, s7, s139408; GFX6-NEXT: v_readfirstlane_b32 s15, v09409; GFX6-NEXT: s_add_i32 s14, s15, s149410; GFX6-NEXT: s_mul_i32 s6, s6, s139411; GFX6-NEXT: s_add_i32 s7, s14, s79412; GFX6-NEXT: v_mov_b32_e32 v2, s69413; GFX6-NEXT: v_mov_b32_e32 v0, s79414; GFX6-NEXT: v_mul_hi_u32 v3, s12, v29415; GFX6-NEXT: v_mul_hi_u32 v2, s13, v29416; GFX6-NEXT: v_mul_hi_u32 v1, s12, v09417; GFX6-NEXT: v_mul_hi_u32 v0, s13, v09418; GFX6-NEXT: s_mul_i32 s15, s13, s79419; GFX6-NEXT: v_readfirstlane_b32 s17, v29420; GFX6-NEXT: s_add_u32 s15, s17, s159421; GFX6-NEXT: v_readfirstlane_b32 s16, v09422; GFX6-NEXT: s_mul_i32 s6, s12, s69423; GFX6-NEXT: s_addc_u32 s16, 0, s169424; GFX6-NEXT: v_readfirstlane_b32 s14, v39425; GFX6-NEXT: s_add_u32 s6, s15, s69426; GFX6-NEXT: s_addc_u32 s6, s16, s149427; GFX6-NEXT: v_readfirstlane_b32 s14, v19428; GFX6-NEXT: s_addc_u32 s14, s14, 09429; GFX6-NEXT: s_mul_i32 s7, s12, s79430; GFX6-NEXT: s_add_u32 s6, s6, s79431; GFX6-NEXT: s_addc_u32 s7, 0, s149432; GFX6-NEXT: s_add_u32 s13, s13, s69433; GFX6-NEXT: s_addc_u32 s12, s12, s79434; GFX6-NEXT: s_ashr_i32 s6, s9, 319435; GFX6-NEXT: s_add_u32 s8, s8, s69436; GFX6-NEXT: s_mov_b32 s7, s69437; GFX6-NEXT: s_addc_u32 s9, s9, s69438; GFX6-NEXT: s_xor_b64 s[8:9], s[8:9], s[6:7]9439; GFX6-NEXT: v_mov_b32_e32 v0, s129440; GFX6-NEXT: v_mul_hi_u32 v1, s8, v09441; GFX6-NEXT: v_mov_b32_e32 v2, s139442; GFX6-NEXT: v_mul_hi_u32 v3, s8, v29443; GFX6-NEXT: s_mul_i32 s14, s8, s129444; GFX6-NEXT: v_readfirstlane_b32 s15, v19445; GFX6-NEXT: v_mul_hi_u32 v1, s9, v29446; GFX6-NEXT: v_readfirstlane_b32 s16, v39447; GFX6-NEXT: v_mul_hi_u32 v0, s9, v09448; GFX6-NEXT: s_add_u32 s14, s16, s149449; GFX6-NEXT: s_addc_u32 s15, 0, s159450; GFX6-NEXT: s_mul_i32 s13, s9, s139451; GFX6-NEXT: v_readfirstlane_b32 s16, v19452; GFX6-NEXT: s_add_u32 s13, s14, s139453; GFX6-NEXT: s_addc_u32 s13, s15, s169454; GFX6-NEXT: v_readfirstlane_b32 s14, v09455; GFX6-NEXT: s_addc_u32 s14, s14, 09456; GFX6-NEXT: s_mul_i32 s12, s9, s129457; GFX6-NEXT: s_add_u32 s12, s13, s129458; GFX6-NEXT: v_mov_b32_e32 v0, s129459; GFX6-NEXT: v_mul_hi_u32 v0, s2, v09460; GFX6-NEXT: s_addc_u32 s13, 0, s149461; GFX6-NEXT: s_mul_i32 s13, s2, s139462; GFX6-NEXT: v_readfirstlane_b32 s14, v09463; GFX6-NEXT: s_add_i32 s13, s14, s139464; GFX6-NEXT: s_mul_i32 s14, s3, s129465; GFX6-NEXT: s_add_i32 s16, s13, s149466; GFX6-NEXT: s_sub_i32 s14, s9, s169467; GFX6-NEXT: s_mul_i32 s12, s2, s129468; GFX6-NEXT: s_sub_u32 s8, s8, s129469; GFX6-NEXT: s_cselect_b64 s[12:13], -1, 09470; GFX6-NEXT: s_subb_u32 s17, s14, s39471; GFX6-NEXT: s_sub_u32 s18, s8, s29472; GFX6-NEXT: s_cselect_b64 s[14:15], -1, 09473; GFX6-NEXT: s_subb_u32 s19, s17, 09474; GFX6-NEXT: s_cmp_ge_u32 s19, s39475; GFX6-NEXT: s_cselect_b32 s20, -1, 09476; GFX6-NEXT: s_cmp_ge_u32 s18, s29477; GFX6-NEXT: s_cselect_b32 s21, -1, 09478; GFX6-NEXT: s_cmp_eq_u32 s19, s39479; GFX6-NEXT: s_cselect_b32 s20, s21, s209480; GFX6-NEXT: s_or_b32 s14, s14, s159481; GFX6-NEXT: s_subb_u32 s14, s17, s39482; GFX6-NEXT: s_sub_u32 s15, s18, s29483; GFX6-NEXT: s_subb_u32 s14, s14, 09484; GFX6-NEXT: s_cmp_lg_u32 s20, 09485; GFX6-NEXT: s_cselect_b32 s15, s15, s189486; GFX6-NEXT: s_cselect_b32 s14, s14, s199487; GFX6-NEXT: s_or_b32 s12, s12, s139488; GFX6-NEXT: s_subb_u32 s9, s9, s169489; GFX6-NEXT: s_cmp_ge_u32 s9, s39490; GFX6-NEXT: s_cselect_b32 s12, -1, 09491; GFX6-NEXT: s_cmp_ge_u32 s8, s29492; GFX6-NEXT: s_cselect_b32 s2, -1, 09493; GFX6-NEXT: s_cmp_eq_u32 s9, s39494; GFX6-NEXT: s_cselect_b32 s2, s2, s129495; GFX6-NEXT: s_cmp_lg_u32 s2, 09496; GFX6-NEXT: s_cselect_b32 s3, s14, s99497; GFX6-NEXT: s_cselect_b32 s2, s15, s89498; GFX6-NEXT: s_xor_b64 s[2:3], s[2:3], s[6:7]9499; GFX6-NEXT: s_sub_u32 s14, s2, s69500; GFX6-NEXT: s_subb_u32 s15, s3, s69501; GFX6-NEXT: s_ashr_i32 s2, s1, 319502; GFX6-NEXT: s_add_u32 s0, s0, s29503; GFX6-NEXT: s_mov_b32 s3, s29504; GFX6-NEXT: s_addc_u32 s1, s1, s29505; GFX6-NEXT: s_xor_b64 s[6:7], s[0:1], s[2:3]9506; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s69507; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s79508; GFX6-NEXT: s_sub_u32 s2, 0, s69509; GFX6-NEXT: s_subb_u32 s3, 0, s79510; GFX6-NEXT: v_mac_f32_e32 v0, 0x4f800000, v19511; GFX6-NEXT: v_rcp_f32_e32 v0, v09512; GFX6-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v09513; GFX6-NEXT: v_mul_f32_e32 v1, 0x2f800000, v09514; GFX6-NEXT: v_trunc_f32_e32 v1, v19515; GFX6-NEXT: v_mac_f32_e32 v0, 0xcf800000, v19516; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v09517; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v19518; GFX6-NEXT: v_mul_hi_u32 v2, s2, v09519; GFX6-NEXT: v_readfirstlane_b32 s8, v19520; GFX6-NEXT: v_readfirstlane_b32 s0, v09521; GFX6-NEXT: s_mul_i32 s9, s2, s89522; GFX6-NEXT: v_readfirstlane_b32 s12, v29523; GFX6-NEXT: s_mul_i32 s1, s3, s09524; GFX6-NEXT: s_add_i32 s9, s12, s99525; GFX6-NEXT: s_add_i32 s9, s9, s19526; GFX6-NEXT: s_mul_i32 s1, s2, s09527; GFX6-NEXT: v_mul_hi_u32 v2, v0, s99528; GFX6-NEXT: v_mul_hi_u32 v0, v0, s19529; GFX6-NEXT: s_mul_i32 s12, s0, s99530; GFX6-NEXT: v_readfirstlane_b32 s13, v29531; GFX6-NEXT: v_readfirstlane_b32 s16, v09532; GFX6-NEXT: v_mul_hi_u32 v0, v1, s19533; GFX6-NEXT: v_mul_hi_u32 v1, v1, s99534; GFX6-NEXT: s_add_u32 s12, s16, s129535; GFX6-NEXT: s_addc_u32 s13, 0, s139536; GFX6-NEXT: s_mul_i32 s1, s8, s19537; GFX6-NEXT: v_readfirstlane_b32 s16, v09538; GFX6-NEXT: s_add_u32 s1, s12, s19539; GFX6-NEXT: s_addc_u32 s1, s13, s169540; GFX6-NEXT: v_readfirstlane_b32 s12, v19541; GFX6-NEXT: s_addc_u32 s12, s12, 09542; GFX6-NEXT: s_mul_i32 s9, s8, s99543; GFX6-NEXT: s_add_u32 s1, s1, s99544; GFX6-NEXT: s_addc_u32 s9, 0, s129545; GFX6-NEXT: s_add_u32 s12, s0, s19546; GFX6-NEXT: v_mov_b32_e32 v0, s129547; GFX6-NEXT: v_mul_hi_u32 v0, s2, v09548; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x99549; GFX6-NEXT: s_addc_u32 s4, s8, s99550; GFX6-NEXT: s_mul_i32 s5, s2, s49551; GFX6-NEXT: v_readfirstlane_b32 s8, v09552; GFX6-NEXT: s_add_i32 s5, s8, s59553; GFX6-NEXT: s_mul_i32 s3, s3, s129554; GFX6-NEXT: s_mul_i32 s2, s2, s129555; GFX6-NEXT: s_add_i32 s3, s5, s39556; GFX6-NEXT: v_mov_b32_e32 v2, s29557; GFX6-NEXT: v_mov_b32_e32 v0, s39558; GFX6-NEXT: v_mul_hi_u32 v3, s4, v29559; GFX6-NEXT: v_mul_hi_u32 v2, s12, v29560; GFX6-NEXT: v_mul_hi_u32 v1, s4, v09561; GFX6-NEXT: v_mul_hi_u32 v0, s12, v09562; GFX6-NEXT: s_mul_i32 s8, s12, s39563; GFX6-NEXT: v_readfirstlane_b32 s13, v29564; GFX6-NEXT: s_add_u32 s8, s13, s89565; GFX6-NEXT: v_readfirstlane_b32 s9, v09566; GFX6-NEXT: s_mul_i32 s2, s4, s29567; GFX6-NEXT: s_addc_u32 s9, 0, s99568; GFX6-NEXT: v_readfirstlane_b32 s5, v39569; GFX6-NEXT: s_add_u32 s2, s8, s29570; GFX6-NEXT: s_addc_u32 s2, s9, s59571; GFX6-NEXT: v_readfirstlane_b32 s5, v19572; GFX6-NEXT: s_addc_u32 s5, s5, 09573; GFX6-NEXT: s_mul_i32 s3, s4, s39574; GFX6-NEXT: s_add_u32 s2, s2, s39575; GFX6-NEXT: s_addc_u32 s3, 0, s59576; GFX6-NEXT: s_add_u32 s12, s12, s29577; GFX6-NEXT: s_addc_u32 s13, s4, s39578; GFX6-NEXT: s_ashr_i32 s4, s11, 319579; GFX6-NEXT: s_add_u32 s2, s10, s49580; GFX6-NEXT: s_mov_b32 s5, s49581; GFX6-NEXT: s_addc_u32 s3, s11, s49582; GFX6-NEXT: s_xor_b64 s[8:9], s[2:3], s[4:5]9583; GFX6-NEXT: v_mov_b32_e32 v0, s139584; GFX6-NEXT: v_mul_hi_u32 v1, s8, v09585; GFX6-NEXT: v_mov_b32_e32 v2, s129586; GFX6-NEXT: v_mul_hi_u32 v3, s8, v29587; GFX6-NEXT: s_mul_i32 s2, s8, s139588; GFX6-NEXT: v_readfirstlane_b32 s10, v19589; GFX6-NEXT: v_mul_hi_u32 v1, s9, v29590; GFX6-NEXT: v_readfirstlane_b32 s11, v39591; GFX6-NEXT: v_mul_hi_u32 v0, s9, v09592; GFX6-NEXT: s_add_u32 s2, s11, s29593; GFX6-NEXT: s_addc_u32 s10, 0, s109594; GFX6-NEXT: s_mul_i32 s11, s9, s129595; GFX6-NEXT: v_readfirstlane_b32 s12, v19596; GFX6-NEXT: s_add_u32 s2, s2, s119597; GFX6-NEXT: s_addc_u32 s2, s10, s129598; GFX6-NEXT: v_readfirstlane_b32 s10, v09599; GFX6-NEXT: s_addc_u32 s10, s10, 09600; GFX6-NEXT: s_mul_i32 s11, s9, s139601; GFX6-NEXT: s_add_u32 s11, s2, s119602; GFX6-NEXT: v_mov_b32_e32 v0, s119603; GFX6-NEXT: v_mul_hi_u32 v0, s6, v09604; GFX6-NEXT: s_addc_u32 s10, 0, s109605; GFX6-NEXT: s_mul_i32 s10, s6, s109606; GFX6-NEXT: s_mov_b32 s3, 0xf0009607; GFX6-NEXT: v_readfirstlane_b32 s12, v09608; GFX6-NEXT: s_add_i32 s10, s12, s109609; GFX6-NEXT: s_mul_i32 s12, s7, s119610; GFX6-NEXT: s_add_i32 s16, s10, s129611; GFX6-NEXT: s_sub_i32 s12, s9, s169612; GFX6-NEXT: s_mul_i32 s10, s6, s119613; GFX6-NEXT: s_sub_u32 s8, s8, s109614; GFX6-NEXT: s_cselect_b64 s[10:11], -1, 09615; GFX6-NEXT: s_subb_u32 s17, s12, s79616; GFX6-NEXT: s_sub_u32 s18, s8, s69617; GFX6-NEXT: s_cselect_b64 s[12:13], -1, 09618; GFX6-NEXT: s_subb_u32 s19, s17, 09619; GFX6-NEXT: s_cmp_ge_u32 s19, s79620; GFX6-NEXT: s_cselect_b32 s20, -1, 09621; GFX6-NEXT: s_cmp_ge_u32 s18, s69622; GFX6-NEXT: s_cselect_b32 s21, -1, 09623; GFX6-NEXT: s_cmp_eq_u32 s19, s79624; GFX6-NEXT: s_cselect_b32 s20, s21, s209625; GFX6-NEXT: s_or_b32 s12, s12, s139626; GFX6-NEXT: s_subb_u32 s12, s17, s79627; GFX6-NEXT: s_sub_u32 s13, s18, s69628; GFX6-NEXT: s_subb_u32 s12, s12, 09629; GFX6-NEXT: s_cmp_lg_u32 s20, 09630; GFX6-NEXT: s_cselect_b32 s13, s13, s189631; GFX6-NEXT: s_cselect_b32 s12, s12, s199632; GFX6-NEXT: s_or_b32 s10, s10, s119633; GFX6-NEXT: s_subb_u32 s9, s9, s169634; GFX6-NEXT: s_cmp_ge_u32 s9, s79635; GFX6-NEXT: s_cselect_b32 s10, -1, 09636; GFX6-NEXT: s_cmp_ge_u32 s8, s69637; GFX6-NEXT: s_cselect_b32 s6, -1, 09638; GFX6-NEXT: s_cmp_eq_u32 s9, s79639; GFX6-NEXT: s_cselect_b32 s6, s6, s109640; GFX6-NEXT: s_cmp_lg_u32 s6, 09641; GFX6-NEXT: s_cselect_b32 s7, s12, s99642; GFX6-NEXT: s_cselect_b32 s6, s13, s89643; GFX6-NEXT: s_xor_b64 s[6:7], s[6:7], s[4:5]9644; GFX6-NEXT: s_sub_u32 s5, s6, s49645; GFX6-NEXT: s_subb_u32 s4, s7, s49646; GFX6-NEXT: s_mov_b32 s2, -19647; GFX6-NEXT: v_mov_b32_e32 v0, s149648; GFX6-NEXT: v_mov_b32_e32 v1, s159649; GFX6-NEXT: v_mov_b32_e32 v2, s59650; GFX6-NEXT: v_mov_b32_e32 v3, s49651; GFX6-NEXT: s_waitcnt lgkmcnt(0)9652; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 09653; GFX6-NEXT: s_endpgm9654;9655; GFX9-LABEL: srem_v2i64_pow2_shl_denom:9656; GFX9: ; %bb.0:9657; GFX9-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x349658; GFX9-NEXT: s_waitcnt lgkmcnt(0)9659; GFX9-NEXT: s_lshl_b64 s[2:3], 0x1000, s129660; GFX9-NEXT: s_lshl_b64 s[0:1], 0x1000, s149661; GFX9-NEXT: s_ashr_i32 s6, s3, 319662; GFX9-NEXT: s_add_u32 s2, s2, s69663; GFX9-NEXT: s_mov_b32 s7, s69664; GFX9-NEXT: s_addc_u32 s3, s3, s69665; GFX9-NEXT: s_xor_b64 s[2:3], s[2:3], s[6:7]9666; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s29667; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s39668; GFX9-NEXT: s_sub_u32 s6, 0, s29669; GFX9-NEXT: s_subb_u32 s7, 0, s39670; GFX9-NEXT: v_mac_f32_e32 v0, 0x4f800000, v19671; GFX9-NEXT: v_rcp_f32_e32 v0, v09672; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v09673; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v09674; GFX9-NEXT: v_trunc_f32_e32 v1, v19675; GFX9-NEXT: v_mac_f32_e32 v0, 0xcf800000, v19676; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v19677; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v09678; GFX9-NEXT: v_readfirstlane_b32 s12, v19679; GFX9-NEXT: v_readfirstlane_b32 s13, v09680; GFX9-NEXT: s_mul_i32 s14, s6, s129681; GFX9-NEXT: s_mul_hi_u32 s16, s6, s139682; GFX9-NEXT: s_mul_i32 s15, s7, s139683; GFX9-NEXT: s_add_i32 s14, s16, s149684; GFX9-NEXT: s_mul_i32 s17, s6, s139685; GFX9-NEXT: s_add_i32 s14, s14, s159686; GFX9-NEXT: s_mul_hi_u32 s16, s13, s179687; GFX9-NEXT: s_mul_i32 s18, s13, s149688; GFX9-NEXT: s_mul_hi_u32 s15, s13, s149689; GFX9-NEXT: s_add_u32 s16, s16, s189690; GFX9-NEXT: s_addc_u32 s15, 0, s159691; GFX9-NEXT: s_mul_hi_u32 s18, s12, s179692; GFX9-NEXT: s_mul_i32 s17, s12, s179693; GFX9-NEXT: s_add_u32 s16, s16, s179694; GFX9-NEXT: s_mul_hi_u32 s19, s12, s149695; GFX9-NEXT: s_addc_u32 s15, s15, s189696; GFX9-NEXT: s_addc_u32 s16, s19, 09697; GFX9-NEXT: s_mul_i32 s14, s12, s149698; GFX9-NEXT: s_add_u32 s14, s15, s149699; GFX9-NEXT: s_addc_u32 s15, 0, s169700; GFX9-NEXT: s_add_u32 s13, s13, s149701; GFX9-NEXT: s_addc_u32 s12, s12, s159702; GFX9-NEXT: s_mul_i32 s14, s6, s129703; GFX9-NEXT: s_mul_hi_u32 s15, s6, s139704; GFX9-NEXT: s_add_i32 s14, s15, s149705; GFX9-NEXT: s_mul_i32 s7, s7, s139706; GFX9-NEXT: s_add_i32 s14, s14, s79707; GFX9-NEXT: s_mul_i32 s6, s6, s139708; GFX9-NEXT: s_mul_hi_u32 s15, s12, s69709; GFX9-NEXT: s_mul_i32 s16, s12, s69710; GFX9-NEXT: s_mul_i32 s18, s13, s149711; GFX9-NEXT: s_mul_hi_u32 s6, s13, s69712; GFX9-NEXT: s_mul_hi_u32 s17, s13, s149713; GFX9-NEXT: s_add_u32 s6, s6, s189714; GFX9-NEXT: s_addc_u32 s17, 0, s179715; GFX9-NEXT: s_add_u32 s6, s6, s169716; GFX9-NEXT: s_mul_hi_u32 s7, s12, s149717; GFX9-NEXT: s_addc_u32 s6, s17, s159718; GFX9-NEXT: s_addc_u32 s7, s7, 09719; GFX9-NEXT: s_mul_i32 s14, s12, s149720; GFX9-NEXT: s_add_u32 s6, s6, s149721; GFX9-NEXT: s_addc_u32 s7, 0, s79722; GFX9-NEXT: s_add_u32 s13, s13, s69723; GFX9-NEXT: s_addc_u32 s12, s12, s79724; GFX9-NEXT: s_ashr_i32 s6, s9, 319725; GFX9-NEXT: s_add_u32 s8, s8, s69726; GFX9-NEXT: s_mov_b32 s7, s69727; GFX9-NEXT: s_addc_u32 s9, s9, s69728; GFX9-NEXT: s_xor_b64 s[8:9], s[8:9], s[6:7]9729; GFX9-NEXT: s_mul_i32 s15, s8, s129730; GFX9-NEXT: s_mul_hi_u32 s16, s8, s139731; GFX9-NEXT: s_mul_hi_u32 s14, s8, s129732; GFX9-NEXT: s_add_u32 s15, s16, s159733; GFX9-NEXT: s_addc_u32 s14, 0, s149734; GFX9-NEXT: s_mul_hi_u32 s17, s9, s139735; GFX9-NEXT: s_mul_i32 s13, s9, s139736; GFX9-NEXT: s_add_u32 s13, s15, s139737; GFX9-NEXT: s_mul_hi_u32 s16, s9, s129738; GFX9-NEXT: s_addc_u32 s13, s14, s179739; GFX9-NEXT: s_addc_u32 s14, s16, 09740; GFX9-NEXT: s_mul_i32 s12, s9, s129741; GFX9-NEXT: s_add_u32 s12, s13, s129742; GFX9-NEXT: s_addc_u32 s13, 0, s149743; GFX9-NEXT: s_mul_i32 s13, s2, s139744; GFX9-NEXT: s_mul_hi_u32 s14, s2, s129745; GFX9-NEXT: s_add_i32 s13, s14, s139746; GFX9-NEXT: s_mul_i32 s14, s3, s129747; GFX9-NEXT: s_add_i32 s16, s13, s149748; GFX9-NEXT: s_sub_i32 s14, s9, s169749; GFX9-NEXT: s_mul_i32 s12, s2, s129750; GFX9-NEXT: s_sub_u32 s8, s8, s129751; GFX9-NEXT: s_cselect_b64 s[12:13], -1, 09752; GFX9-NEXT: s_subb_u32 s17, s14, s39753; GFX9-NEXT: s_sub_u32 s18, s8, s29754; GFX9-NEXT: s_cselect_b64 s[14:15], -1, 09755; GFX9-NEXT: s_subb_u32 s19, s17, 09756; GFX9-NEXT: s_cmp_ge_u32 s19, s39757; GFX9-NEXT: s_cselect_b32 s20, -1, 09758; GFX9-NEXT: s_cmp_ge_u32 s18, s29759; GFX9-NEXT: s_cselect_b32 s21, -1, 09760; GFX9-NEXT: s_cmp_eq_u32 s19, s39761; GFX9-NEXT: s_cselect_b32 s20, s21, s209762; GFX9-NEXT: s_cmp_lg_u64 s[14:15], 09763; GFX9-NEXT: s_subb_u32 s14, s17, s39764; GFX9-NEXT: s_sub_u32 s15, s18, s29765; GFX9-NEXT: s_subb_u32 s14, s14, 09766; GFX9-NEXT: s_cmp_lg_u32 s20, 09767; GFX9-NEXT: s_cselect_b32 s15, s15, s189768; GFX9-NEXT: s_cselect_b32 s14, s14, s199769; GFX9-NEXT: s_cmp_lg_u64 s[12:13], 09770; GFX9-NEXT: s_subb_u32 s9, s9, s169771; GFX9-NEXT: s_cmp_ge_u32 s9, s39772; GFX9-NEXT: s_cselect_b32 s12, -1, 09773; GFX9-NEXT: s_cmp_ge_u32 s8, s29774; GFX9-NEXT: s_cselect_b32 s2, -1, 09775; GFX9-NEXT: s_cmp_eq_u32 s9, s39776; GFX9-NEXT: s_cselect_b32 s2, s2, s129777; GFX9-NEXT: s_cmp_lg_u32 s2, 09778; GFX9-NEXT: s_cselect_b32 s3, s14, s99779; GFX9-NEXT: s_cselect_b32 s2, s15, s89780; GFX9-NEXT: s_xor_b64 s[2:3], s[2:3], s[6:7]9781; GFX9-NEXT: s_sub_u32 s12, s2, s69782; GFX9-NEXT: s_subb_u32 s13, s3, s69783; GFX9-NEXT: s_ashr_i32 s2, s1, 319784; GFX9-NEXT: s_add_u32 s0, s0, s29785; GFX9-NEXT: s_mov_b32 s3, s29786; GFX9-NEXT: s_addc_u32 s1, s1, s29787; GFX9-NEXT: s_xor_b64 s[2:3], s[0:1], s[2:3]9788; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s29789; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s39790; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x249791; GFX9-NEXT: s_sub_u32 s4, 0, s29792; GFX9-NEXT: s_subb_u32 s5, 0, s39793; GFX9-NEXT: v_mac_f32_e32 v0, 0x4f800000, v19794; GFX9-NEXT: v_rcp_f32_e32 v1, v09795; GFX9-NEXT: v_mov_b32_e32 v0, 09796; GFX9-NEXT: v_mul_f32_e32 v1, 0x5f7ffffc, v19797; GFX9-NEXT: v_mul_f32_e32 v2, 0x2f800000, v19798; GFX9-NEXT: v_trunc_f32_e32 v2, v29799; GFX9-NEXT: v_mac_f32_e32 v1, 0xcf800000, v29800; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v19801; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v29802; GFX9-NEXT: v_readfirstlane_b32 s6, v19803; GFX9-NEXT: v_readfirstlane_b32 s9, v29804; GFX9-NEXT: s_mul_hi_u32 s8, s4, s69805; GFX9-NEXT: s_mul_i32 s14, s4, s99806; GFX9-NEXT: s_mul_i32 s7, s5, s69807; GFX9-NEXT: s_add_i32 s8, s8, s149808; GFX9-NEXT: s_add_i32 s8, s8, s79809; GFX9-NEXT: s_mul_i32 s15, s4, s69810; GFX9-NEXT: s_mul_i32 s14, s6, s89811; GFX9-NEXT: s_mul_hi_u32 s16, s6, s159812; GFX9-NEXT: s_mul_hi_u32 s7, s6, s89813; GFX9-NEXT: s_add_u32 s14, s16, s149814; GFX9-NEXT: s_addc_u32 s7, 0, s79815; GFX9-NEXT: s_mul_hi_u32 s17, s9, s159816; GFX9-NEXT: s_mul_i32 s15, s9, s159817; GFX9-NEXT: s_add_u32 s14, s14, s159818; GFX9-NEXT: s_mul_hi_u32 s16, s9, s89819; GFX9-NEXT: s_addc_u32 s7, s7, s179820; GFX9-NEXT: s_addc_u32 s14, s16, 09821; GFX9-NEXT: s_mul_i32 s8, s9, s89822; GFX9-NEXT: s_add_u32 s7, s7, s89823; GFX9-NEXT: s_addc_u32 s8, 0, s149824; GFX9-NEXT: s_add_u32 s6, s6, s79825; GFX9-NEXT: s_addc_u32 s7, s9, s89826; GFX9-NEXT: s_mul_i32 s8, s4, s79827; GFX9-NEXT: s_mul_hi_u32 s9, s4, s69828; GFX9-NEXT: s_add_i32 s8, s9, s89829; GFX9-NEXT: s_mul_i32 s5, s5, s69830; GFX9-NEXT: s_add_i32 s8, s8, s59831; GFX9-NEXT: s_mul_i32 s4, s4, s69832; GFX9-NEXT: s_mul_hi_u32 s9, s7, s49833; GFX9-NEXT: s_mul_i32 s14, s7, s49834; GFX9-NEXT: s_mul_i32 s16, s6, s89835; GFX9-NEXT: s_mul_hi_u32 s4, s6, s49836; GFX9-NEXT: s_mul_hi_u32 s15, s6, s89837; GFX9-NEXT: s_add_u32 s4, s4, s169838; GFX9-NEXT: s_addc_u32 s15, 0, s159839; GFX9-NEXT: s_add_u32 s4, s4, s149840; GFX9-NEXT: s_mul_hi_u32 s5, s7, s89841; GFX9-NEXT: s_addc_u32 s4, s15, s99842; GFX9-NEXT: s_addc_u32 s5, s5, 09843; GFX9-NEXT: s_mul_i32 s8, s7, s89844; GFX9-NEXT: s_add_u32 s4, s4, s89845; GFX9-NEXT: s_addc_u32 s5, 0, s59846; GFX9-NEXT: s_add_u32 s8, s6, s49847; GFX9-NEXT: s_addc_u32 s9, s7, s59848; GFX9-NEXT: s_ashr_i32 s4, s11, 319849; GFX9-NEXT: s_add_u32 s6, s10, s49850; GFX9-NEXT: s_mov_b32 s5, s49851; GFX9-NEXT: s_addc_u32 s7, s11, s49852; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[4:5]9853; GFX9-NEXT: s_mul_i32 s11, s6, s99854; GFX9-NEXT: s_mul_hi_u32 s14, s6, s89855; GFX9-NEXT: s_mul_hi_u32 s10, s6, s99856; GFX9-NEXT: s_add_u32 s11, s14, s119857; GFX9-NEXT: s_addc_u32 s10, 0, s109858; GFX9-NEXT: s_mul_hi_u32 s15, s7, s89859; GFX9-NEXT: s_mul_i32 s8, s7, s89860; GFX9-NEXT: s_add_u32 s8, s11, s89861; GFX9-NEXT: s_mul_hi_u32 s14, s7, s99862; GFX9-NEXT: s_addc_u32 s8, s10, s159863; GFX9-NEXT: s_addc_u32 s10, s14, 09864; GFX9-NEXT: s_mul_i32 s9, s7, s99865; GFX9-NEXT: s_add_u32 s8, s8, s99866; GFX9-NEXT: s_addc_u32 s9, 0, s109867; GFX9-NEXT: s_mul_i32 s9, s2, s99868; GFX9-NEXT: s_mul_hi_u32 s10, s2, s89869; GFX9-NEXT: s_add_i32 s9, s10, s99870; GFX9-NEXT: s_mul_i32 s10, s3, s89871; GFX9-NEXT: s_add_i32 s14, s9, s109872; GFX9-NEXT: s_sub_i32 s10, s7, s149873; GFX9-NEXT: s_mul_i32 s8, s2, s89874; GFX9-NEXT: s_sub_u32 s6, s6, s89875; GFX9-NEXT: s_cselect_b64 s[8:9], -1, 09876; GFX9-NEXT: s_subb_u32 s15, s10, s39877; GFX9-NEXT: s_sub_u32 s16, s6, s29878; GFX9-NEXT: s_cselect_b64 s[10:11], -1, 09879; GFX9-NEXT: s_subb_u32 s17, s15, 09880; GFX9-NEXT: s_cmp_ge_u32 s17, s39881; GFX9-NEXT: s_cselect_b32 s18, -1, 09882; GFX9-NEXT: s_cmp_ge_u32 s16, s29883; GFX9-NEXT: s_cselect_b32 s19, -1, 09884; GFX9-NEXT: s_cmp_eq_u32 s17, s39885; GFX9-NEXT: s_cselect_b32 s18, s19, s189886; GFX9-NEXT: s_cmp_lg_u64 s[10:11], 09887; GFX9-NEXT: s_subb_u32 s10, s15, s39888; GFX9-NEXT: s_sub_u32 s11, s16, s29889; GFX9-NEXT: s_subb_u32 s10, s10, 09890; GFX9-NEXT: s_cmp_lg_u32 s18, 09891; GFX9-NEXT: s_cselect_b32 s11, s11, s169892; GFX9-NEXT: s_cselect_b32 s10, s10, s179893; GFX9-NEXT: s_cmp_lg_u64 s[8:9], 09894; GFX9-NEXT: s_subb_u32 s7, s7, s149895; GFX9-NEXT: s_cmp_ge_u32 s7, s39896; GFX9-NEXT: s_cselect_b32 s8, -1, 09897; GFX9-NEXT: s_cmp_ge_u32 s6, s29898; GFX9-NEXT: s_cselect_b32 s2, -1, 09899; GFX9-NEXT: s_cmp_eq_u32 s7, s39900; GFX9-NEXT: s_cselect_b32 s2, s2, s89901; GFX9-NEXT: s_cmp_lg_u32 s2, 09902; GFX9-NEXT: s_cselect_b32 s3, s10, s79903; GFX9-NEXT: s_cselect_b32 s2, s11, s69904; GFX9-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5]9905; GFX9-NEXT: s_sub_u32 s2, s2, s49906; GFX9-NEXT: s_subb_u32 s3, s3, s49907; GFX9-NEXT: v_mov_b32_e32 v1, s129908; GFX9-NEXT: v_mov_b32_e32 v2, s139909; GFX9-NEXT: v_mov_b32_e32 v3, s29910; GFX9-NEXT: v_mov_b32_e32 v4, s39911; GFX9-NEXT: s_waitcnt lgkmcnt(0)9912; GFX9-NEXT: global_store_dwordx4 v0, v[1:4], s[0:1]9913; GFX9-NEXT: s_endpgm9914 %shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y9915 %r = srem <2 x i64> %x, %shl.y9916 store <2 x i64> %r, ptr addrspace(1) %out9917 ret void9918}9919 9920define <2 x i32> @v_sdiv_i32_exact(<2 x i32> %num) {9921; CHECK-LABEL: @v_sdiv_i32_exact(9922; CHECK: %1 = extractelement <2 x i32> %num, i64 09923; CHECK-NEXT: %2 = sdiv exact i32 %1, 40969924; CHECK-NEXT: %3 = insertelement <2 x i32> poison, i32 %2, i64 09925; CHECK-NEXT: %4 = extractelement <2 x i32> %num, i64 19926; CHECK-NEXT: %5 = sdiv exact i32 %4, 10249927; CHECK-NEXT: %6 = insertelement <2 x i32> %3, i32 %5, i64 19928; CHECK-NEXT: ret <2 x i32> %69929;9930; GFX6-LABEL: v_sdiv_i32_exact:9931; GFX6: ; %bb.0:9932; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9933; GFX6-NEXT: v_ashrrev_i32_e32 v0, 12, v09934; GFX6-NEXT: v_ashrrev_i32_e32 v1, 10, v19935; GFX6-NEXT: s_setpc_b64 s[30:31]9936;9937; GFX9-LABEL: v_sdiv_i32_exact:9938; GFX9: ; %bb.0:9939; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9940; GFX9-NEXT: v_ashrrev_i32_e32 v0, 12, v09941; GFX9-NEXT: v_ashrrev_i32_e32 v1, 10, v19942; GFX9-NEXT: s_setpc_b64 s[30:31]9943 %result = sdiv exact <2 x i32> %num, <i32 4096, i32 1024>9944 ret <2 x i32> %result9945}9946 9947define <2 x i64> @v_sdiv_i64_exact(<2 x i64> %num) {9948; CHECK-LABEL: @v_sdiv_i64_exact(9949; CHECK: %1 = extractelement <2 x i64> %num, i64 09950; CHECK-NEXT: %2 = sdiv exact i64 %1, 40969951; CHECK-NEXT: %3 = insertelement <2 x i64> poison, i64 %2, i64 09952; CHECK-NEXT: %4 = extractelement <2 x i64> %num, i64 19953; CHECK-NEXT: %5 = sdiv exact i64 %4, 10249954; CHECK-NEXT: %6 = insertelement <2 x i64> %3, i64 %5, i64 19955; CHECK-NEXT: ret <2 x i64> %69956;9957; GFX6-LABEL: v_sdiv_i64_exact:9958; GFX6: ; %bb.0:9959; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9960; GFX6-NEXT: v_ashr_i64 v[0:1], v[0:1], 129961; GFX6-NEXT: v_ashr_i64 v[2:3], v[2:3], 109962; GFX6-NEXT: s_setpc_b64 s[30:31]9963;9964; GFX9-LABEL: v_sdiv_i64_exact:9965; GFX9: ; %bb.0:9966; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9967; GFX9-NEXT: v_ashrrev_i64 v[0:1], 12, v[0:1]9968; GFX9-NEXT: v_ashrrev_i64 v[2:3], 10, v[2:3]9969; GFX9-NEXT: s_setpc_b64 s[30:31]9970 %result = sdiv exact <2 x i64> %num, <i64 4096, i64 1024>9971 ret <2 x i64> %result9972}9973 9974define <2 x i32> @v_udiv_i32_exact(<2 x i32> %num) {9975; CHECK-LABEL: @v_udiv_i32_exact(9976; CHECK: %1 = extractelement <2 x i32> %num, i64 09977; CHECK-NEXT: %2 = udiv exact i32 %1, 40969978; CHECK-NEXT: %3 = insertelement <2 x i32> poison, i32 %2, i64 09979; CHECK-NEXT: %4 = extractelement <2 x i32> %num, i64 19980; CHECK-NEXT: %5 = udiv exact i32 %4, 10249981; CHECK-NEXT: %6 = insertelement <2 x i32> %3, i32 %5, i64 19982; CHECK-NEXT: ret <2 x i32> %69983;9984; GFX6-LABEL: v_udiv_i32_exact:9985; GFX6: ; %bb.0:9986; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9987; GFX6-NEXT: v_lshrrev_b32_e32 v0, 12, v09988; GFX6-NEXT: v_lshrrev_b32_e32 v1, 10, v19989; GFX6-NEXT: s_setpc_b64 s[30:31]9990;9991; GFX9-LABEL: v_udiv_i32_exact:9992; GFX9: ; %bb.0:9993; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9994; GFX9-NEXT: v_lshrrev_b32_e32 v0, 12, v09995; GFX9-NEXT: v_lshrrev_b32_e32 v1, 10, v19996; GFX9-NEXT: s_setpc_b64 s[30:31]9997 %result = udiv exact <2 x i32> %num, <i32 4096, i32 1024>9998 ret <2 x i32> %result9999}10000 10001define <2 x i64> @v_udiv_i64_exact(<2 x i64> %num) {10002; CHECK-LABEL: @v_udiv_i64_exact(10003; CHECK: %1 = extractelement <2 x i64> %num, i64 010004; CHECK-NEXT: %2 = udiv exact i64 %1, 409610005; CHECK-NEXT: %3 = insertelement <2 x i64> poison, i64 %2, i64 010006; CHECK-NEXT: %4 = extractelement <2 x i64> %num, i64 110007; CHECK-NEXT: %5 = udiv exact i64 %4, 102410008; CHECK-NEXT: %6 = insertelement <2 x i64> %3, i64 %5, i64 110009; CHECK-NEXT: ret <2 x i64> %610010;10011; GFX6-LABEL: v_udiv_i64_exact:10012; GFX6: ; %bb.0:10013; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10014; GFX6-NEXT: v_lshr_b64 v[0:1], v[0:1], 1210015; GFX6-NEXT: v_lshr_b64 v[2:3], v[2:3], 1010016; GFX6-NEXT: s_setpc_b64 s[30:31]10017;10018; GFX9-LABEL: v_udiv_i64_exact:10019; GFX9: ; %bb.0:10020; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10021; GFX9-NEXT: v_lshrrev_b64 v[0:1], 12, v[0:1]10022; GFX9-NEXT: v_lshrrev_b64 v[2:3], 10, v[2:3]10023; GFX9-NEXT: s_setpc_b64 s[30:31]10024 %result = udiv exact <2 x i64> %num, <i64 4096, i64 1024>10025 ret <2 x i64> %result10026}10027 10028define i64 @udiv_i64_gt_smax(i8 %size) {10029; GFX6-LABEL: udiv_i64_gt_smax:10030; GFX6: ; %bb.0:10031; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10032; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 810033; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v010034; GFX6-NEXT: v_not_b32_e32 v1, v110035; GFX6-NEXT: v_not_b32_e32 v0, v010036; GFX6-NEXT: s_mov_b32 s4, 0xcccccccd10037; GFX6-NEXT: v_mul_lo_u32 v3, v1, s410038; GFX6-NEXT: v_mul_hi_u32 v4, v0, s410039; GFX6-NEXT: s_mov_b32 s6, 0xcccccccc10040; GFX6-NEXT: v_mul_hi_u32 v5, v1, s410041; GFX6-NEXT: v_mul_hi_u32 v2, v0, s610042; GFX6-NEXT: v_mul_lo_u32 v0, v0, s610043; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v410044; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc10045; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v310046; GFX6-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc10047; GFX6-NEXT: v_mul_lo_u32 v2, v1, s610048; GFX6-NEXT: v_mul_hi_u32 v1, v1, s610049; GFX6-NEXT: v_add_i32_e32 v0, vcc, v4, v010050; GFX6-NEXT: v_addc_u32_e64 v3, s[4:5], 0, 0, vcc10051; GFX6-NEXT: v_add_i32_e32 v0, vcc, v2, v010052; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc10053; GFX6-NEXT: v_alignbit_b32 v0, v1, v0, 310054; GFX6-NEXT: v_lshrrev_b32_e32 v1, 3, v110055; GFX6-NEXT: s_setpc_b64 s[30:31]10056;10057; GFX9-LABEL: udiv_i64_gt_smax:10058; GFX9: ; %bb.0:10059; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10060; GFX9-NEXT: v_not_b32_sdwa v5, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_010061; GFX9-NEXT: s_mov_b32 s4, 0xcccccccd10062; GFX9-NEXT: v_mul_hi_u32 v1, v5, s410063; GFX9-NEXT: v_mov_b32_e32 v3, 3110064; GFX9-NEXT: v_ashrrev_i32_sdwa v0, v3, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_010065; GFX9-NEXT: v_mov_b32_e32 v2, 010066; GFX9-NEXT: v_not_b32_e32 v6, v010067; GFX9-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v6, s4, v[1:2]10068; GFX9-NEXT: s_mov_b32 s6, 0xcccccccc10069; GFX9-NEXT: v_mov_b32_e32 v1, v310070; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v5, s6, v[1:2]10071; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v4, v110072; GFX9-NEXT: v_addc_co_u32_e64 v1, s[4:5], 0, 0, vcc10073; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v6, s6, v[0:1]10074; GFX9-NEXT: v_alignbit_b32 v0, v1, v0, 310075; GFX9-NEXT: v_lshrrev_b32_e32 v1, 3, v110076; GFX9-NEXT: s_setpc_b64 s[30:31]10077 %esize = sext i8 %size to i6410078 %minus = sub nuw nsw i64 -1, %esize10079 %div = udiv i64 %minus, 1010080 ret i64 %div10081}10082 10083define i64 @udiv_i64_9divbits(i8 %size) {10084; GFX6-LABEL: udiv_i64_9divbits:10085; GFX6: ; %bb.0:10086; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10087; GFX6-NEXT: v_and_b32_e32 v0, 0xff, v010088; GFX6-NEXT: v_add_i32_e32 v0, vcc, 1, v010089; GFX6-NEXT: v_cvt_f32_u32_e32 v0, v010090; GFX6-NEXT: s_mov_b32 s4, 0x4120000010091; GFX6-NEXT: v_mul_f32_e32 v1, 0x3dcccccd, v010092; GFX6-NEXT: v_trunc_f32_e32 v1, v110093; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v110094; GFX6-NEXT: v_mad_f32 v0, -v1, s4, v010095; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, s410096; GFX6-NEXT: v_mov_b32_e32 v1, 010097; GFX6-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc10098; GFX6-NEXT: v_and_b32_e32 v0, 0x1ff, v010099; GFX6-NEXT: s_setpc_b64 s[30:31]10100;10101; GFX9-LABEL: udiv_i64_9divbits:10102; GFX9: ; %bb.0:10103; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10104; GFX9-NEXT: v_mov_b32_e32 v1, 110105; GFX9-NEXT: v_add_u32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD10106; GFX9-NEXT: v_cvt_f32_u32_e32 v0, v010107; GFX9-NEXT: s_mov_b32 s4, 0x4120000010108; GFX9-NEXT: v_mul_f32_e32 v1, 0x3dcccccd, v010109; GFX9-NEXT: v_trunc_f32_e32 v1, v110110; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v110111; GFX9-NEXT: v_mad_f32 v0, -v1, s4, v010112; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, s410113; GFX9-NEXT: v_mov_b32_e32 v1, 010114; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, 0, v2, vcc10115; GFX9-NEXT: v_and_b32_e32 v0, 0x1ff, v010116; GFX9-NEXT: s_setpc_b64 s[30:31]10117 %zextend = zext i8 %size to i6410118 %num = add nuw nsw i64 1, %zextend10119 %div = udiv i64 %num, 1010120 ret i64 %div10121}10122 10123define <2 x i64> @srem_zero_zero() {10124; GFX6-LABEL: srem_zero_zero:10125; GFX6: ; %bb.0: ; %entry10126; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10127; GFX6-NEXT: s_setpc_b64 s[30:31]10128;10129; GFX9-LABEL: srem_zero_zero:10130; GFX9: ; %bb.0: ; %entry10131; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10132; GFX9-NEXT: s_setpc_b64 s[30:31]10133entry:10134 %B = srem <2 x i64> zeroinitializer, zeroinitializer10135 ret <2 x i64> %B10136}10137