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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 22; RUN: opt -S -mtriple=amdgcn-- -mcpu=hawaii -passes=amdgpu-codegenprepare -denormal-fp-math-f32=ieee %s | FileCheck -check-prefixes=CHECK,IEEE %s3; RUN: opt -S -mtriple=amdgcn-- -mcpu=hawaii -passes=amdgpu-codegenprepare -denormal-fp-math-f32=dynamic %s | FileCheck -check-prefixes=CHECK,IEEE %s4; RUN: opt -S -mtriple=amdgcn-- -mcpu=hawaii -passes=amdgpu-codegenprepare -denormal-fp-math-f32=preserve-sign %s | FileCheck -check-prefixes=CHECK,DAZ %s5 6define amdgpu_kernel void @noop_sqrt_fpmath(ptr addrspace(1) %out, float %x) #0 {7; CHECK-LABEL: define amdgpu_kernel void @noop_sqrt_fpmath8; CHECK-SAME: (ptr addrspace(1) [[OUT:%.*]], float [[X:%.*]]) #[[ATTR0:[0-9]+]] {9; CHECK-NEXT: [[MD_25ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !010; CHECK-NEXT: store volatile float [[MD_25ULP]], ptr addrspace(1) [[OUT]], align 411; CHECK-NEXT: ret void12;13 %md.25ulp = call float @llvm.sqrt.f32(float %x), !fpmath !314 store volatile float %md.25ulp, ptr addrspace(1) %out, align 415 ret void16}17 18define amdgpu_kernel void @sqrt_fpmath_f32(ptr addrspace(1) %out, float %x) {19; IEEE-LABEL: define amdgpu_kernel void @sqrt_fpmath_f3220; IEEE-SAME: (ptr addrspace(1) [[OUT:%.*]], float [[X:%.*]]) #[[ATTR1:[0-9]+]] {21; IEEE-NEXT: [[NO_MD:%.*]] = call float @llvm.sqrt.f32(float [[X]])22; IEEE-NEXT: store volatile float [[NO_MD]], ptr addrspace(1) [[OUT]], align 423; IEEE-NEXT: [[MD_HALF_ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !124; IEEE-NEXT: store volatile float [[MD_HALF_ULP]], ptr addrspace(1) [[OUT]], align 425; IEEE-NEXT: [[MD_1ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !226; IEEE-NEXT: store volatile float [[MD_1ULP]], ptr addrspace(1) [[OUT]], align 427; IEEE-NEXT: [[TMP1:%.*]] = fcmp olt float [[X]], 0x381000000000000028; IEEE-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 32, i32 029; IEEE-NEXT: [[TMP3:%.*]] = call float @llvm.ldexp.f32.i32(float [[X]], i32 [[TMP2]])30; IEEE-NEXT: [[TMP4:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP3]])31; IEEE-NEXT: [[TMP5:%.*]] = select i1 [[TMP1]], i32 -16, i32 032; IEEE-NEXT: [[MD_25ULP:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP4]], i32 [[TMP5]])33; IEEE-NEXT: store volatile float [[MD_25ULP]], ptr addrspace(1) [[OUT]], align 434; IEEE-NEXT: [[TMP6:%.*]] = fcmp olt float [[X]], 0x381000000000000035; IEEE-NEXT: [[TMP7:%.*]] = select i1 [[TMP6]], i32 32, i32 036; IEEE-NEXT: [[TMP8:%.*]] = call float @llvm.ldexp.f32.i32(float [[X]], i32 [[TMP7]])37; IEEE-NEXT: [[TMP9:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP8]])38; IEEE-NEXT: [[TMP10:%.*]] = select i1 [[TMP6]], i32 -16, i32 039; IEEE-NEXT: [[MD_3ULP:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP9]], i32 [[TMP10]])40; IEEE-NEXT: store volatile float [[MD_3ULP]], ptr addrspace(1) [[OUT]], align 441; IEEE-NEXT: [[TMP11:%.*]] = fcmp olt float [[X]], 0x381000000000000042; IEEE-NEXT: [[TMP12:%.*]] = select i1 [[TMP11]], i32 32, i32 043; IEEE-NEXT: [[TMP13:%.*]] = call float @llvm.ldexp.f32.i32(float [[X]], i32 [[TMP12]])44; IEEE-NEXT: [[TMP14:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP13]])45; IEEE-NEXT: [[TMP15:%.*]] = select i1 [[TMP11]], i32 -16, i32 046; IEEE-NEXT: [[MD_2ULP:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP14]], i32 [[TMP15]])47; IEEE-NEXT: store volatile float [[MD_2ULP]], ptr addrspace(1) [[OUT]], align 448; IEEE-NEXT: ret void49;50; DAZ-LABEL: define amdgpu_kernel void @sqrt_fpmath_f3251; DAZ-SAME: (ptr addrspace(1) [[OUT:%.*]], float [[X:%.*]]) #[[ATTR1:[0-9]+]] {52; DAZ-NEXT: [[NO_MD:%.*]] = call float @llvm.sqrt.f32(float [[X]])53; DAZ-NEXT: store volatile float [[NO_MD]], ptr addrspace(1) [[OUT]], align 454; DAZ-NEXT: [[MD_HALF_ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !155; DAZ-NEXT: store volatile float [[MD_HALF_ULP]], ptr addrspace(1) [[OUT]], align 456; DAZ-NEXT: [[MD_1ULP:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[X]])57; DAZ-NEXT: store volatile float [[MD_1ULP]], ptr addrspace(1) [[OUT]], align 458; DAZ-NEXT: [[MD_25ULP:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[X]])59; DAZ-NEXT: store volatile float [[MD_25ULP]], ptr addrspace(1) [[OUT]], align 460; DAZ-NEXT: [[MD_3ULP:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[X]])61; DAZ-NEXT: store volatile float [[MD_3ULP]], ptr addrspace(1) [[OUT]], align 462; DAZ-NEXT: [[MD_2ULP:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[X]])63; DAZ-NEXT: store volatile float [[MD_2ULP]], ptr addrspace(1) [[OUT]], align 464; DAZ-NEXT: ret void65;66 %no.md = call float @llvm.sqrt.f32(float %x)67 store volatile float %no.md, ptr addrspace(1) %out, align 468 69 %md.half.ulp = call float @llvm.sqrt.f32(float %x), !fpmath !170 store volatile float %md.half.ulp, ptr addrspace(1) %out, align 471 72 %md.1ulp = call float @llvm.sqrt.f32(float %x), !fpmath !273 store volatile float %md.1ulp, ptr addrspace(1) %out, align 474 75 %md.25ulp = call float @llvm.sqrt.f32(float %x), !fpmath !076 store volatile float %md.25ulp, ptr addrspace(1) %out, align 477 78 %md.3ulp = call float @llvm.sqrt.f32(float %x), !fpmath !379 store volatile float %md.3ulp, ptr addrspace(1) %out, align 480 81 %md.2ulp = call float @llvm.sqrt.f32(float %x), !fpmath !482 store volatile float %md.2ulp, ptr addrspace(1) %out, align 483 ret void84}85 86define amdgpu_kernel void @sqrt_fpmath_v2f32(ptr addrspace(1) %out, <2 x float> %x) {87; IEEE-LABEL: define amdgpu_kernel void @sqrt_fpmath_v2f3288; IEEE-SAME: (ptr addrspace(1) [[OUT:%.*]], <2 x float> [[X:%.*]]) #[[ATTR1]] {89; IEEE-NEXT: [[NO_MD:%.*]] = call <2 x float> @llvm.sqrt.v2f32(<2 x float> [[X]])90; IEEE-NEXT: store volatile <2 x float> [[NO_MD]], ptr addrspace(1) [[OUT]], align 491; IEEE-NEXT: [[MD_HALF_ULP:%.*]] = call <2 x float> @llvm.sqrt.v2f32(<2 x float> [[X]]), !fpmath !192; IEEE-NEXT: store volatile <2 x float> [[MD_HALF_ULP]], ptr addrspace(1) [[OUT]], align 493; IEEE-NEXT: [[MD_1ULP:%.*]] = call <2 x float> @llvm.sqrt.v2f32(<2 x float> [[X]]), !fpmath !294; IEEE-NEXT: store volatile <2 x float> [[MD_1ULP]], ptr addrspace(1) [[OUT]], align 495; IEEE-NEXT: [[TMP1:%.*]] = extractelement <2 x float> [[X]], i64 096; IEEE-NEXT: [[TMP2:%.*]] = extractelement <2 x float> [[X]], i64 197; IEEE-NEXT: [[TMP3:%.*]] = fcmp olt float [[TMP1]], 0x381000000000000098; IEEE-NEXT: [[TMP4:%.*]] = select i1 [[TMP3]], i32 32, i32 099; IEEE-NEXT: [[TMP5:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP1]], i32 [[TMP4]])100; IEEE-NEXT: [[TMP6:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP5]])101; IEEE-NEXT: [[TMP7:%.*]] = select i1 [[TMP3]], i32 -16, i32 0102; IEEE-NEXT: [[TMP8:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP6]], i32 [[TMP7]])103; IEEE-NEXT: [[TMP9:%.*]] = fcmp olt float [[TMP2]], 0x3810000000000000104; IEEE-NEXT: [[TMP10:%.*]] = select i1 [[TMP9]], i32 32, i32 0105; IEEE-NEXT: [[TMP11:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP2]], i32 [[TMP10]])106; IEEE-NEXT: [[TMP12:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP11]])107; IEEE-NEXT: [[TMP13:%.*]] = select i1 [[TMP9]], i32 -16, i32 0108; IEEE-NEXT: [[TMP14:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP12]], i32 [[TMP13]])109; IEEE-NEXT: [[TMP15:%.*]] = insertelement <2 x float> poison, float [[TMP8]], i64 0110; IEEE-NEXT: [[MD_25ULP:%.*]] = insertelement <2 x float> [[TMP15]], float [[TMP14]], i64 1111; IEEE-NEXT: store volatile <2 x float> [[MD_25ULP]], ptr addrspace(1) [[OUT]], align 4112; IEEE-NEXT: [[TMP16:%.*]] = extractelement <2 x float> [[X]], i64 0113; IEEE-NEXT: [[TMP17:%.*]] = extractelement <2 x float> [[X]], i64 1114; IEEE-NEXT: [[TMP18:%.*]] = fcmp olt float [[TMP16]], 0x3810000000000000115; IEEE-NEXT: [[TMP19:%.*]] = select i1 [[TMP18]], i32 32, i32 0116; IEEE-NEXT: [[TMP20:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP16]], i32 [[TMP19]])117; IEEE-NEXT: [[TMP21:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP20]])118; IEEE-NEXT: [[TMP22:%.*]] = select i1 [[TMP18]], i32 -16, i32 0119; IEEE-NEXT: [[TMP23:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP21]], i32 [[TMP22]])120; IEEE-NEXT: [[TMP24:%.*]] = fcmp olt float [[TMP17]], 0x3810000000000000121; IEEE-NEXT: [[TMP25:%.*]] = select i1 [[TMP24]], i32 32, i32 0122; IEEE-NEXT: [[TMP26:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP17]], i32 [[TMP25]])123; IEEE-NEXT: [[TMP27:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP26]])124; IEEE-NEXT: [[TMP28:%.*]] = select i1 [[TMP24]], i32 -16, i32 0125; IEEE-NEXT: [[TMP29:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP27]], i32 [[TMP28]])126; IEEE-NEXT: [[TMP30:%.*]] = insertelement <2 x float> poison, float [[TMP23]], i64 0127; IEEE-NEXT: [[MD_3ULP:%.*]] = insertelement <2 x float> [[TMP30]], float [[TMP29]], i64 1128; IEEE-NEXT: store volatile <2 x float> [[MD_3ULP]], ptr addrspace(1) [[OUT]], align 4129; IEEE-NEXT: [[TMP31:%.*]] = extractelement <2 x float> [[X]], i64 0130; IEEE-NEXT: [[TMP32:%.*]] = extractelement <2 x float> [[X]], i64 1131; IEEE-NEXT: [[TMP33:%.*]] = fcmp olt float [[TMP31]], 0x3810000000000000132; IEEE-NEXT: [[TMP34:%.*]] = select i1 [[TMP33]], i32 32, i32 0133; IEEE-NEXT: [[TMP35:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP31]], i32 [[TMP34]])134; IEEE-NEXT: [[TMP36:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP35]])135; IEEE-NEXT: [[TMP37:%.*]] = select i1 [[TMP33]], i32 -16, i32 0136; IEEE-NEXT: [[TMP38:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP36]], i32 [[TMP37]])137; IEEE-NEXT: [[TMP39:%.*]] = fcmp olt float [[TMP32]], 0x3810000000000000138; IEEE-NEXT: [[TMP40:%.*]] = select i1 [[TMP39]], i32 32, i32 0139; IEEE-NEXT: [[TMP41:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP32]], i32 [[TMP40]])140; IEEE-NEXT: [[TMP42:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP41]])141; IEEE-NEXT: [[TMP43:%.*]] = select i1 [[TMP39]], i32 -16, i32 0142; IEEE-NEXT: [[TMP44:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP42]], i32 [[TMP43]])143; IEEE-NEXT: [[TMP45:%.*]] = insertelement <2 x float> poison, float [[TMP38]], i64 0144; IEEE-NEXT: [[MD_2ULP:%.*]] = insertelement <2 x float> [[TMP45]], float [[TMP44]], i64 1145; IEEE-NEXT: store volatile <2 x float> [[MD_2ULP]], ptr addrspace(1) [[OUT]], align 4146; IEEE-NEXT: ret void147;148; DAZ-LABEL: define amdgpu_kernel void @sqrt_fpmath_v2f32149; DAZ-SAME: (ptr addrspace(1) [[OUT:%.*]], <2 x float> [[X:%.*]]) #[[ATTR1]] {150; DAZ-NEXT: [[NO_MD:%.*]] = call <2 x float> @llvm.sqrt.v2f32(<2 x float> [[X]])151; DAZ-NEXT: store volatile <2 x float> [[NO_MD]], ptr addrspace(1) [[OUT]], align 4152; DAZ-NEXT: [[MD_HALF_ULP:%.*]] = call <2 x float> @llvm.sqrt.v2f32(<2 x float> [[X]]), !fpmath !1153; DAZ-NEXT: store volatile <2 x float> [[MD_HALF_ULP]], ptr addrspace(1) [[OUT]], align 4154; DAZ-NEXT: [[TMP1:%.*]] = extractelement <2 x float> [[X]], i64 0155; DAZ-NEXT: [[TMP2:%.*]] = extractelement <2 x float> [[X]], i64 1156; DAZ-NEXT: [[TMP3:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP1]])157; DAZ-NEXT: [[TMP4:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP2]])158; DAZ-NEXT: [[TMP5:%.*]] = insertelement <2 x float> poison, float [[TMP3]], i64 0159; DAZ-NEXT: [[MD_1ULP:%.*]] = insertelement <2 x float> [[TMP5]], float [[TMP4]], i64 1160; DAZ-NEXT: store volatile <2 x float> [[MD_1ULP]], ptr addrspace(1) [[OUT]], align 4161; DAZ-NEXT: [[TMP6:%.*]] = extractelement <2 x float> [[X]], i64 0162; DAZ-NEXT: [[TMP7:%.*]] = extractelement <2 x float> [[X]], i64 1163; DAZ-NEXT: [[TMP8:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP6]])164; DAZ-NEXT: [[TMP9:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP7]])165; DAZ-NEXT: [[TMP10:%.*]] = insertelement <2 x float> poison, float [[TMP8]], i64 0166; DAZ-NEXT: [[MD_25ULP:%.*]] = insertelement <2 x float> [[TMP10]], float [[TMP9]], i64 1167; DAZ-NEXT: store volatile <2 x float> [[MD_25ULP]], ptr addrspace(1) [[OUT]], align 4168; DAZ-NEXT: [[TMP11:%.*]] = extractelement <2 x float> [[X]], i64 0169; DAZ-NEXT: [[TMP12:%.*]] = extractelement <2 x float> [[X]], i64 1170; DAZ-NEXT: [[TMP13:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP11]])171; DAZ-NEXT: [[TMP14:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP12]])172; DAZ-NEXT: [[TMP15:%.*]] = insertelement <2 x float> poison, float [[TMP13]], i64 0173; DAZ-NEXT: [[MD_3ULP:%.*]] = insertelement <2 x float> [[TMP15]], float [[TMP14]], i64 1174; DAZ-NEXT: store volatile <2 x float> [[MD_3ULP]], ptr addrspace(1) [[OUT]], align 4175; DAZ-NEXT: [[TMP16:%.*]] = extractelement <2 x float> [[X]], i64 0176; DAZ-NEXT: [[TMP17:%.*]] = extractelement <2 x float> [[X]], i64 1177; DAZ-NEXT: [[TMP18:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP16]])178; DAZ-NEXT: [[TMP19:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP17]])179; DAZ-NEXT: [[TMP20:%.*]] = insertelement <2 x float> poison, float [[TMP18]], i64 0180; DAZ-NEXT: [[MD_2ULP:%.*]] = insertelement <2 x float> [[TMP20]], float [[TMP19]], i64 1181; DAZ-NEXT: store volatile <2 x float> [[MD_2ULP]], ptr addrspace(1) [[OUT]], align 4182; DAZ-NEXT: ret void183;184 %no.md = call <2 x float> @llvm.sqrt.v2f32(<2 x float> %x)185 store volatile <2 x float> %no.md, ptr addrspace(1) %out, align 4186 187 %md.half.ulp = call <2 x float> @llvm.sqrt.v2f32(<2 x float> %x), !fpmath !1188 store volatile <2 x float> %md.half.ulp, ptr addrspace(1) %out, align 4189 190 %md.1ulp = call <2 x float> @llvm.sqrt.v2f32(<2 x float> %x), !fpmath !2191 store volatile <2 x float> %md.1ulp, ptr addrspace(1) %out, align 4192 193 %md.25ulp = call <2 x float> @llvm.sqrt.v2f32(<2 x float> %x), !fpmath !0194 store volatile <2 x float> %md.25ulp, ptr addrspace(1) %out, align 4195 196 %md.3ulp = call <2 x float> @llvm.sqrt.v2f32(<2 x float> %x), !fpmath !3197 store volatile <2 x float> %md.3ulp, ptr addrspace(1) %out, align 4198 199 %md.2ulp = call <2 x float> @llvm.sqrt.v2f32(<2 x float> %x), !fpmath !4200 store volatile <2 x float> %md.2ulp, ptr addrspace(1) %out, align 4201 ret void202}203 204define amdgpu_kernel void @sqrt_fpmath_f32_known_nosub(ptr addrspace(1) %out, float nofpclass(sub) %x) {205; CHECK-LABEL: define amdgpu_kernel void @sqrt_fpmath_f32_known_nosub206; CHECK-SAME: (ptr addrspace(1) [[OUT:%.*]], float nofpclass(sub) [[X:%.*]]) #[[ATTR1:[0-9]+]] {207; CHECK-NEXT: [[NO_MD:%.*]] = call float @llvm.sqrt.f32(float [[X]])208; CHECK-NEXT: store volatile float [[NO_MD]], ptr addrspace(1) [[OUT]], align 4209; CHECK-NEXT: [[MD_HALF_ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !1210; CHECK-NEXT: store volatile float [[MD_HALF_ULP]], ptr addrspace(1) [[OUT]], align 4211; CHECK-NEXT: [[MD_1ULP:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[X]])212; CHECK-NEXT: store volatile float [[MD_1ULP]], ptr addrspace(1) [[OUT]], align 4213; CHECK-NEXT: [[MD_25ULP:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[X]])214; CHECK-NEXT: store volatile float [[MD_25ULP]], ptr addrspace(1) [[OUT]], align 4215; CHECK-NEXT: [[MD_3ULP:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[X]])216; CHECK-NEXT: store volatile float [[MD_3ULP]], ptr addrspace(1) [[OUT]], align 4217; CHECK-NEXT: [[MD_2ULP:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[X]])218; CHECK-NEXT: store volatile float [[MD_2ULP]], ptr addrspace(1) [[OUT]], align 4219; CHECK-NEXT: ret void220;221 %no.md = call float @llvm.sqrt.f32(float %x)222 store volatile float %no.md, ptr addrspace(1) %out, align 4223 224 %md.half.ulp = call float @llvm.sqrt.f32(float %x), !fpmath !1225 store volatile float %md.half.ulp, ptr addrspace(1) %out, align 4226 227 %md.1ulp = call float @llvm.sqrt.f32(float %x), !fpmath !2228 store volatile float %md.1ulp, ptr addrspace(1) %out, align 4229 230 %md.25ulp = call float @llvm.sqrt.f32(float %x), !fpmath !0231 store volatile float %md.25ulp, ptr addrspace(1) %out, align 4232 233 %md.3ulp = call float @llvm.sqrt.f32(float %x), !fpmath !3234 store volatile float %md.3ulp, ptr addrspace(1) %out, align 4235 236 %md.2ulp = call float @llvm.sqrt.f32(float %x), !fpmath !4237 store volatile float %md.2ulp, ptr addrspace(1) %out, align 4238 ret void239}240 241define amdgpu_kernel void @sqrt_fpmath_f32_known_nonzero(ptr addrspace(1) %out, float nofpclass(nzero) %x) {242; IEEE-LABEL: define amdgpu_kernel void @sqrt_fpmath_f32_known_nonzero243; IEEE-SAME: (ptr addrspace(1) [[OUT:%.*]], float nofpclass(nzero) [[X:%.*]]) #[[ATTR1]] {244; IEEE-NEXT: [[NO_MD:%.*]] = call float @llvm.sqrt.f32(float [[X]])245; IEEE-NEXT: store volatile float [[NO_MD]], ptr addrspace(1) [[OUT]], align 4246; IEEE-NEXT: [[MD_HALF_ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !1247; IEEE-NEXT: store volatile float [[MD_HALF_ULP]], ptr addrspace(1) [[OUT]], align 4248; IEEE-NEXT: [[MD_1ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !2249; IEEE-NEXT: store volatile float [[MD_1ULP]], ptr addrspace(1) [[OUT]], align 4250; IEEE-NEXT: [[TMP1:%.*]] = fcmp olt float [[X]], 0x3810000000000000251; IEEE-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 32, i32 0252; IEEE-NEXT: [[TMP3:%.*]] = call float @llvm.ldexp.f32.i32(float [[X]], i32 [[TMP2]])253; IEEE-NEXT: [[TMP4:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP3]])254; IEEE-NEXT: [[TMP5:%.*]] = select i1 [[TMP1]], i32 -16, i32 0255; IEEE-NEXT: [[MD_25ULP:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP4]], i32 [[TMP5]])256; IEEE-NEXT: store volatile float [[MD_25ULP]], ptr addrspace(1) [[OUT]], align 4257; IEEE-NEXT: [[TMP6:%.*]] = fcmp olt float [[X]], 0x3810000000000000258; IEEE-NEXT: [[TMP7:%.*]] = select i1 [[TMP6]], i32 32, i32 0259; IEEE-NEXT: [[TMP8:%.*]] = call float @llvm.ldexp.f32.i32(float [[X]], i32 [[TMP7]])260; IEEE-NEXT: [[TMP9:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP8]])261; IEEE-NEXT: [[TMP10:%.*]] = select i1 [[TMP6]], i32 -16, i32 0262; IEEE-NEXT: [[MD_3ULP:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP9]], i32 [[TMP10]])263; IEEE-NEXT: store volatile float [[MD_3ULP]], ptr addrspace(1) [[OUT]], align 4264; IEEE-NEXT: [[TMP11:%.*]] = fcmp olt float [[X]], 0x3810000000000000265; IEEE-NEXT: [[TMP12:%.*]] = select i1 [[TMP11]], i32 32, i32 0266; IEEE-NEXT: [[TMP13:%.*]] = call float @llvm.ldexp.f32.i32(float [[X]], i32 [[TMP12]])267; IEEE-NEXT: [[TMP14:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP13]])268; IEEE-NEXT: [[TMP15:%.*]] = select i1 [[TMP11]], i32 -16, i32 0269; IEEE-NEXT: [[MD_2ULP:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP14]], i32 [[TMP15]])270; IEEE-NEXT: store volatile float [[MD_2ULP]], ptr addrspace(1) [[OUT]], align 4271; IEEE-NEXT: ret void272;273; DAZ-LABEL: define amdgpu_kernel void @sqrt_fpmath_f32_known_nonzero274; DAZ-SAME: (ptr addrspace(1) [[OUT:%.*]], float nofpclass(nzero) [[X:%.*]]) #[[ATTR1]] {275; DAZ-NEXT: [[NO_MD:%.*]] = call float @llvm.sqrt.f32(float [[X]])276; DAZ-NEXT: store volatile float [[NO_MD]], ptr addrspace(1) [[OUT]], align 4277; DAZ-NEXT: [[MD_HALF_ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !1278; DAZ-NEXT: store volatile float [[MD_HALF_ULP]], ptr addrspace(1) [[OUT]], align 4279; DAZ-NEXT: [[MD_1ULP:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[X]])280; DAZ-NEXT: store volatile float [[MD_1ULP]], ptr addrspace(1) [[OUT]], align 4281; DAZ-NEXT: [[MD_25ULP:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[X]])282; DAZ-NEXT: store volatile float [[MD_25ULP]], ptr addrspace(1) [[OUT]], align 4283; DAZ-NEXT: [[MD_3ULP:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[X]])284; DAZ-NEXT: store volatile float [[MD_3ULP]], ptr addrspace(1) [[OUT]], align 4285; DAZ-NEXT: [[MD_2ULP:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[X]])286; DAZ-NEXT: store volatile float [[MD_2ULP]], ptr addrspace(1) [[OUT]], align 4287; DAZ-NEXT: ret void288;289 %no.md = call float @llvm.sqrt.f32(float %x)290 store volatile float %no.md, ptr addrspace(1) %out, align 4291 292 %md.half.ulp = call float @llvm.sqrt.f32(float %x), !fpmath !1293 store volatile float %md.half.ulp, ptr addrspace(1) %out, align 4294 295 %md.1ulp = call float @llvm.sqrt.f32(float %x), !fpmath !2296 store volatile float %md.1ulp, ptr addrspace(1) %out, align 4297 298 %md.25ulp = call float @llvm.sqrt.f32(float %x), !fpmath !0299 store volatile float %md.25ulp, ptr addrspace(1) %out, align 4300 301 %md.3ulp = call float @llvm.sqrt.f32(float %x), !fpmath !3302 store volatile float %md.3ulp, ptr addrspace(1) %out, align 4303 304 %md.2ulp = call float @llvm.sqrt.f32(float %x), !fpmath !4305 store volatile float %md.2ulp, ptr addrspace(1) %out, align 4306 ret void307}308 309define amdgpu_kernel void @sqrt_fpmath_f32_known_nonzero_nonsub(ptr addrspace(1) %out, float nofpclass(nzero nsub) %x) {310; IEEE-LABEL: define amdgpu_kernel void @sqrt_fpmath_f32_known_nonzero_nonsub311; IEEE-SAME: (ptr addrspace(1) [[OUT:%.*]], float nofpclass(nzero nsub) [[X:%.*]]) #[[ATTR1]] {312; IEEE-NEXT: [[NO_MD:%.*]] = call float @llvm.sqrt.f32(float [[X]])313; IEEE-NEXT: store volatile float [[NO_MD]], ptr addrspace(1) [[OUT]], align 4314; IEEE-NEXT: [[MD_HALF_ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !1315; IEEE-NEXT: store volatile float [[MD_HALF_ULP]], ptr addrspace(1) [[OUT]], align 4316; IEEE-NEXT: [[MD_1ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !2317; IEEE-NEXT: store volatile float [[MD_1ULP]], ptr addrspace(1) [[OUT]], align 4318; IEEE-NEXT: [[TMP1:%.*]] = fcmp olt float [[X]], 0x3810000000000000319; IEEE-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 32, i32 0320; IEEE-NEXT: [[TMP3:%.*]] = call float @llvm.ldexp.f32.i32(float [[X]], i32 [[TMP2]])321; IEEE-NEXT: [[TMP4:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP3]])322; IEEE-NEXT: [[TMP5:%.*]] = select i1 [[TMP1]], i32 -16, i32 0323; IEEE-NEXT: [[MD_25ULP:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP4]], i32 [[TMP5]])324; IEEE-NEXT: store volatile float [[MD_25ULP]], ptr addrspace(1) [[OUT]], align 4325; IEEE-NEXT: [[TMP6:%.*]] = fcmp olt float [[X]], 0x3810000000000000326; IEEE-NEXT: [[TMP7:%.*]] = select i1 [[TMP6]], i32 32, i32 0327; IEEE-NEXT: [[TMP8:%.*]] = call float @llvm.ldexp.f32.i32(float [[X]], i32 [[TMP7]])328; IEEE-NEXT: [[TMP9:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP8]])329; IEEE-NEXT: [[TMP10:%.*]] = select i1 [[TMP6]], i32 -16, i32 0330; IEEE-NEXT: [[MD_3ULP:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP9]], i32 [[TMP10]])331; IEEE-NEXT: store volatile float [[MD_3ULP]], ptr addrspace(1) [[OUT]], align 4332; IEEE-NEXT: [[TMP11:%.*]] = fcmp olt float [[X]], 0x3810000000000000333; IEEE-NEXT: [[TMP12:%.*]] = select i1 [[TMP11]], i32 32, i32 0334; IEEE-NEXT: [[TMP13:%.*]] = call float @llvm.ldexp.f32.i32(float [[X]], i32 [[TMP12]])335; IEEE-NEXT: [[TMP14:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP13]])336; IEEE-NEXT: [[TMP15:%.*]] = select i1 [[TMP11]], i32 -16, i32 0337; IEEE-NEXT: [[MD_2ULP:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP14]], i32 [[TMP15]])338; IEEE-NEXT: store volatile float [[MD_2ULP]], ptr addrspace(1) [[OUT]], align 4339; IEEE-NEXT: ret void340;341; DAZ-LABEL: define amdgpu_kernel void @sqrt_fpmath_f32_known_nonzero_nonsub342; DAZ-SAME: (ptr addrspace(1) [[OUT:%.*]], float nofpclass(nzero nsub) [[X:%.*]]) #[[ATTR1]] {343; DAZ-NEXT: [[NO_MD:%.*]] = call float @llvm.sqrt.f32(float [[X]])344; DAZ-NEXT: store volatile float [[NO_MD]], ptr addrspace(1) [[OUT]], align 4345; DAZ-NEXT: [[MD_HALF_ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !1346; DAZ-NEXT: store volatile float [[MD_HALF_ULP]], ptr addrspace(1) [[OUT]], align 4347; DAZ-NEXT: [[MD_1ULP:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[X]])348; DAZ-NEXT: store volatile float [[MD_1ULP]], ptr addrspace(1) [[OUT]], align 4349; DAZ-NEXT: [[MD_25ULP:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[X]])350; DAZ-NEXT: store volatile float [[MD_25ULP]], ptr addrspace(1) [[OUT]], align 4351; DAZ-NEXT: [[MD_3ULP:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[X]])352; DAZ-NEXT: store volatile float [[MD_3ULP]], ptr addrspace(1) [[OUT]], align 4353; DAZ-NEXT: [[MD_2ULP:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[X]])354; DAZ-NEXT: store volatile float [[MD_2ULP]], ptr addrspace(1) [[OUT]], align 4355; DAZ-NEXT: ret void356;357 %no.md = call float @llvm.sqrt.f32(float %x)358 store volatile float %no.md, ptr addrspace(1) %out, align 4359 360 %md.half.ulp = call float @llvm.sqrt.f32(float %x), !fpmath !1361 store volatile float %md.half.ulp, ptr addrspace(1) %out, align 4362 363 %md.1ulp = call float @llvm.sqrt.f32(float %x), !fpmath !2364 store volatile float %md.1ulp, ptr addrspace(1) %out, align 4365 366 %md.25ulp = call float @llvm.sqrt.f32(float %x), !fpmath !0367 store volatile float %md.25ulp, ptr addrspace(1) %out, align 4368 369 %md.3ulp = call float @llvm.sqrt.f32(float %x), !fpmath !3370 store volatile float %md.3ulp, ptr addrspace(1) %out, align 4371 372 %md.2ulp = call float @llvm.sqrt.f32(float %x), !fpmath !4373 store volatile float %md.2ulp, ptr addrspace(1) %out, align 4374 ret void375}376 377define amdgpu_kernel void @sqrt_fpmath_f32_known_nonzero_nonsub_noinf(ptr addrspace(1) %out, float nofpclass(nzero nsub inf) %x) {378; IEEE-LABEL: define amdgpu_kernel void @sqrt_fpmath_f32_known_nonzero_nonsub_noinf379; IEEE-SAME: (ptr addrspace(1) [[OUT:%.*]], float nofpclass(inf nzero nsub) [[X:%.*]]) #[[ATTR1]] {380; IEEE-NEXT: [[NO_MD:%.*]] = call float @llvm.sqrt.f32(float [[X]])381; IEEE-NEXT: store volatile float [[NO_MD]], ptr addrspace(1) [[OUT]], align 4382; IEEE-NEXT: [[MD_HALF_ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !1383; IEEE-NEXT: store volatile float [[MD_HALF_ULP]], ptr addrspace(1) [[OUT]], align 4384; IEEE-NEXT: [[MD_1ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !2385; IEEE-NEXT: store volatile float [[MD_1ULP]], ptr addrspace(1) [[OUT]], align 4386; IEEE-NEXT: [[TMP1:%.*]] = fcmp olt float [[X]], 0x3810000000000000387; IEEE-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 32, i32 0388; IEEE-NEXT: [[TMP3:%.*]] = call float @llvm.ldexp.f32.i32(float [[X]], i32 [[TMP2]])389; IEEE-NEXT: [[TMP4:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP3]])390; IEEE-NEXT: [[TMP5:%.*]] = select i1 [[TMP1]], i32 -16, i32 0391; IEEE-NEXT: [[MD_25ULP:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP4]], i32 [[TMP5]])392; IEEE-NEXT: store volatile float [[MD_25ULP]], ptr addrspace(1) [[OUT]], align 4393; IEEE-NEXT: [[TMP6:%.*]] = fcmp olt float [[X]], 0x3810000000000000394; IEEE-NEXT: [[TMP7:%.*]] = select i1 [[TMP6]], i32 32, i32 0395; IEEE-NEXT: [[TMP8:%.*]] = call float @llvm.ldexp.f32.i32(float [[X]], i32 [[TMP7]])396; IEEE-NEXT: [[TMP9:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP8]])397; IEEE-NEXT: [[TMP10:%.*]] = select i1 [[TMP6]], i32 -16, i32 0398; IEEE-NEXT: [[MD_3ULP:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP9]], i32 [[TMP10]])399; IEEE-NEXT: store volatile float [[MD_3ULP]], ptr addrspace(1) [[OUT]], align 4400; IEEE-NEXT: [[TMP11:%.*]] = fcmp olt float [[X]], 0x3810000000000000401; IEEE-NEXT: [[TMP12:%.*]] = select i1 [[TMP11]], i32 32, i32 0402; IEEE-NEXT: [[TMP13:%.*]] = call float @llvm.ldexp.f32.i32(float [[X]], i32 [[TMP12]])403; IEEE-NEXT: [[TMP14:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP13]])404; IEEE-NEXT: [[TMP15:%.*]] = select i1 [[TMP11]], i32 -16, i32 0405; IEEE-NEXT: [[MD_2ULP:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP14]], i32 [[TMP15]])406; IEEE-NEXT: store volatile float [[MD_2ULP]], ptr addrspace(1) [[OUT]], align 4407; IEEE-NEXT: ret void408;409; DAZ-LABEL: define amdgpu_kernel void @sqrt_fpmath_f32_known_nonzero_nonsub_noinf410; DAZ-SAME: (ptr addrspace(1) [[OUT:%.*]], float nofpclass(inf nzero nsub) [[X:%.*]]) #[[ATTR1]] {411; DAZ-NEXT: [[NO_MD:%.*]] = call float @llvm.sqrt.f32(float [[X]])412; DAZ-NEXT: store volatile float [[NO_MD]], ptr addrspace(1) [[OUT]], align 4413; DAZ-NEXT: [[MD_HALF_ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !1414; DAZ-NEXT: store volatile float [[MD_HALF_ULP]], ptr addrspace(1) [[OUT]], align 4415; DAZ-NEXT: [[MD_1ULP:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[X]])416; DAZ-NEXT: store volatile float [[MD_1ULP]], ptr addrspace(1) [[OUT]], align 4417; DAZ-NEXT: [[MD_25ULP:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[X]])418; DAZ-NEXT: store volatile float [[MD_25ULP]], ptr addrspace(1) [[OUT]], align 4419; DAZ-NEXT: [[MD_3ULP:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[X]])420; DAZ-NEXT: store volatile float [[MD_3ULP]], ptr addrspace(1) [[OUT]], align 4421; DAZ-NEXT: [[MD_2ULP:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[X]])422; DAZ-NEXT: store volatile float [[MD_2ULP]], ptr addrspace(1) [[OUT]], align 4423; DAZ-NEXT: ret void424;425 %no.md = call float @llvm.sqrt.f32(float %x)426 store volatile float %no.md, ptr addrspace(1) %out, align 4427 428 %md.half.ulp = call float @llvm.sqrt.f32(float %x), !fpmath !1429 store volatile float %md.half.ulp, ptr addrspace(1) %out, align 4430 431 %md.1ulp = call float @llvm.sqrt.f32(float %x), !fpmath !2432 store volatile float %md.1ulp, ptr addrspace(1) %out, align 4433 434 %md.25ulp = call float @llvm.sqrt.f32(float %x), !fpmath !0435 store volatile float %md.25ulp, ptr addrspace(1) %out, align 4436 437 %md.3ulp = call float @llvm.sqrt.f32(float %x), !fpmath !3438 store volatile float %md.3ulp, ptr addrspace(1) %out, align 4439 440 %md.2ulp = call float @llvm.sqrt.f32(float %x), !fpmath !4441 store volatile float %md.2ulp, ptr addrspace(1) %out, align 4442 ret void443}444 445define amdgpu_kernel void @sqrt_fpmath_f32_known_nopsub(ptr addrspace(1) %out, float nofpclass(psub) %x) {446; IEEE-LABEL: define amdgpu_kernel void @sqrt_fpmath_f32_known_nopsub447; IEEE-SAME: (ptr addrspace(1) [[OUT:%.*]], float nofpclass(psub) [[X:%.*]]) #[[ATTR1]] {448; IEEE-NEXT: [[NO_MD:%.*]] = call float @llvm.sqrt.f32(float [[X]])449; IEEE-NEXT: store volatile float [[NO_MD]], ptr addrspace(1) [[OUT]], align 4450; IEEE-NEXT: [[MD_HALF_ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !1451; IEEE-NEXT: store volatile float [[MD_HALF_ULP]], ptr addrspace(1) [[OUT]], align 4452; IEEE-NEXT: [[MD_1ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !2453; IEEE-NEXT: store volatile float [[MD_1ULP]], ptr addrspace(1) [[OUT]], align 4454; IEEE-NEXT: [[TMP1:%.*]] = fcmp olt float [[X]], 0x3810000000000000455; IEEE-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 32, i32 0456; IEEE-NEXT: [[TMP3:%.*]] = call float @llvm.ldexp.f32.i32(float [[X]], i32 [[TMP2]])457; IEEE-NEXT: [[TMP4:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP3]])458; IEEE-NEXT: [[TMP5:%.*]] = select i1 [[TMP1]], i32 -16, i32 0459; IEEE-NEXT: [[MD_25ULP:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP4]], i32 [[TMP5]])460; IEEE-NEXT: store volatile float [[MD_25ULP]], ptr addrspace(1) [[OUT]], align 4461; IEEE-NEXT: [[TMP6:%.*]] = fcmp olt float [[X]], 0x3810000000000000462; IEEE-NEXT: [[TMP7:%.*]] = select i1 [[TMP6]], i32 32, i32 0463; IEEE-NEXT: [[TMP8:%.*]] = call float @llvm.ldexp.f32.i32(float [[X]], i32 [[TMP7]])464; IEEE-NEXT: [[TMP9:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP8]])465; IEEE-NEXT: [[TMP10:%.*]] = select i1 [[TMP6]], i32 -16, i32 0466; IEEE-NEXT: [[MD_3ULP:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP9]], i32 [[TMP10]])467; IEEE-NEXT: store volatile float [[MD_3ULP]], ptr addrspace(1) [[OUT]], align 4468; IEEE-NEXT: [[TMP11:%.*]] = fcmp olt float [[X]], 0x3810000000000000469; IEEE-NEXT: [[TMP12:%.*]] = select i1 [[TMP11]], i32 32, i32 0470; IEEE-NEXT: [[TMP13:%.*]] = call float @llvm.ldexp.f32.i32(float [[X]], i32 [[TMP12]])471; IEEE-NEXT: [[TMP14:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP13]])472; IEEE-NEXT: [[TMP15:%.*]] = select i1 [[TMP11]], i32 -16, i32 0473; IEEE-NEXT: [[MD_2ULP:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP14]], i32 [[TMP15]])474; IEEE-NEXT: store volatile float [[MD_2ULP]], ptr addrspace(1) [[OUT]], align 4475; IEEE-NEXT: ret void476;477; DAZ-LABEL: define amdgpu_kernel void @sqrt_fpmath_f32_known_nopsub478; DAZ-SAME: (ptr addrspace(1) [[OUT:%.*]], float nofpclass(psub) [[X:%.*]]) #[[ATTR1]] {479; DAZ-NEXT: [[NO_MD:%.*]] = call float @llvm.sqrt.f32(float [[X]])480; DAZ-NEXT: store volatile float [[NO_MD]], ptr addrspace(1) [[OUT]], align 4481; DAZ-NEXT: [[MD_HALF_ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !1482; DAZ-NEXT: store volatile float [[MD_HALF_ULP]], ptr addrspace(1) [[OUT]], align 4483; DAZ-NEXT: [[MD_1ULP:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[X]])484; DAZ-NEXT: store volatile float [[MD_1ULP]], ptr addrspace(1) [[OUT]], align 4485; DAZ-NEXT: [[MD_25ULP:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[X]])486; DAZ-NEXT: store volatile float [[MD_25ULP]], ptr addrspace(1) [[OUT]], align 4487; DAZ-NEXT: [[MD_3ULP:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[X]])488; DAZ-NEXT: store volatile float [[MD_3ULP]], ptr addrspace(1) [[OUT]], align 4489; DAZ-NEXT: [[MD_2ULP:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[X]])490; DAZ-NEXT: store volatile float [[MD_2ULP]], ptr addrspace(1) [[OUT]], align 4491; DAZ-NEXT: ret void492;493 %no.md = call float @llvm.sqrt.f32(float %x)494 store volatile float %no.md, ptr addrspace(1) %out, align 4495 496 %md.half.ulp = call float @llvm.sqrt.f32(float %x), !fpmath !1497 store volatile float %md.half.ulp, ptr addrspace(1) %out, align 4498 499 %md.1ulp = call float @llvm.sqrt.f32(float %x), !fpmath !2500 store volatile float %md.1ulp, ptr addrspace(1) %out, align 4501 502 %md.25ulp = call float @llvm.sqrt.f32(float %x), !fpmath !0503 store volatile float %md.25ulp, ptr addrspace(1) %out, align 4504 505 %md.3ulp = call float @llvm.sqrt.f32(float %x), !fpmath !3506 store volatile float %md.3ulp, ptr addrspace(1) %out, align 4507 508 %md.2ulp = call float @llvm.sqrt.f32(float %x), !fpmath !4509 store volatile float %md.2ulp, ptr addrspace(1) %out, align 4510 ret void511}512 513define amdgpu_kernel void @sqrt_fpmath_f32_afn(ptr addrspace(1) %out, float %x) {514; CHECK-LABEL: define amdgpu_kernel void @sqrt_fpmath_f32_afn515; CHECK-SAME: (ptr addrspace(1) [[OUT:%.*]], float [[X:%.*]]) #[[ATTR1]] {516; CHECK-NEXT: [[NO_MD:%.*]] = call afn float @llvm.sqrt.f32(float [[X]])517; CHECK-NEXT: store volatile float [[NO_MD]], ptr addrspace(1) [[OUT]], align 4518; CHECK-NEXT: [[MD_HALF_ULP:%.*]] = call afn float @llvm.sqrt.f32(float [[X]]), !fpmath !1519; CHECK-NEXT: store volatile float [[MD_HALF_ULP]], ptr addrspace(1) [[OUT]], align 4520; CHECK-NEXT: [[MD_1ULP:%.*]] = call afn float @llvm.sqrt.f32(float [[X]]), !fpmath !2521; CHECK-NEXT: store volatile float [[MD_1ULP]], ptr addrspace(1) [[OUT]], align 4522; CHECK-NEXT: [[MD_25ULP:%.*]] = call afn float @llvm.sqrt.f32(float [[X]]), !fpmath !3523; CHECK-NEXT: store volatile float [[MD_25ULP]], ptr addrspace(1) [[OUT]], align 4524; CHECK-NEXT: [[MD_3ULP:%.*]] = call afn float @llvm.sqrt.f32(float [[X]]), !fpmath !0525; CHECK-NEXT: store volatile float [[MD_3ULP]], ptr addrspace(1) [[OUT]], align 4526; CHECK-NEXT: [[MD_2ULP:%.*]] = call afn float @llvm.sqrt.f32(float [[X]]), !fpmath !4527; CHECK-NEXT: store volatile float [[MD_2ULP]], ptr addrspace(1) [[OUT]], align 4528; CHECK-NEXT: ret void529;530 %no.md = call afn float @llvm.sqrt.f32(float %x)531 store volatile float %no.md, ptr addrspace(1) %out, align 4532 533 %md.half.ulp = call afn float @llvm.sqrt.f32(float %x), !fpmath !1534 store volatile float %md.half.ulp, ptr addrspace(1) %out, align 4535 536 %md.1ulp = call afn float @llvm.sqrt.f32(float %x), !fpmath !2537 store volatile float %md.1ulp, ptr addrspace(1) %out, align 4538 539 %md.25ulp = call afn float @llvm.sqrt.f32(float %x), !fpmath !0540 store volatile float %md.25ulp, ptr addrspace(1) %out, align 4541 542 %md.3ulp = call afn float @llvm.sqrt.f32(float %x), !fpmath !3543 store volatile float %md.3ulp, ptr addrspace(1) %out, align 4544 545 %md.2ulp = call afn float @llvm.sqrt.f32(float %x), !fpmath !4546 store volatile float %md.2ulp, ptr addrspace(1) %out, align 4547 ret void548}549 550define amdgpu_kernel void @sqrt_fpmath_f32_assume_nosub(ptr addrspace(1) %out, float %x) {551; CHECK-LABEL: define amdgpu_kernel void @sqrt_fpmath_f32_assume_nosub552; CHECK-SAME: (ptr addrspace(1) [[OUT:%.*]], float [[X:%.*]]) #[[ATTR1]] {553; CHECK-NEXT: [[FABS_X:%.*]] = call float @llvm.fabs.f32(float [[X]])554; CHECK-NEXT: [[IS_NOT_SUBNORMAL:%.*]] = fcmp oge float [[FABS_X]], 0x3810000000000000555; CHECK-NEXT: call void @llvm.assume(i1 [[IS_NOT_SUBNORMAL]])556; CHECK-NEXT: [[NO_MD:%.*]] = call float @llvm.sqrt.f32(float [[X]])557; CHECK-NEXT: store volatile float [[NO_MD]], ptr addrspace(1) [[OUT]], align 4558; CHECK-NEXT: [[MD_HALF_ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !1559; CHECK-NEXT: store volatile float [[MD_HALF_ULP]], ptr addrspace(1) [[OUT]], align 4560; CHECK-NEXT: [[MD_1ULP:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[X]])561; CHECK-NEXT: store volatile float [[MD_1ULP]], ptr addrspace(1) [[OUT]], align 4562; CHECK-NEXT: [[MD_25ULP:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[X]])563; CHECK-NEXT: store volatile float [[MD_25ULP]], ptr addrspace(1) [[OUT]], align 4564; CHECK-NEXT: [[MD_3ULP:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[X]])565; CHECK-NEXT: store volatile float [[MD_3ULP]], ptr addrspace(1) [[OUT]], align 4566; CHECK-NEXT: [[MD_2ULP:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[X]])567; CHECK-NEXT: store volatile float [[MD_2ULP]], ptr addrspace(1) [[OUT]], align 4568; CHECK-NEXT: [[MD_3ULP_AFN:%.*]] = call afn float @llvm.sqrt.f32(float [[X]]), !fpmath !0569; CHECK-NEXT: store volatile float [[MD_3ULP]], ptr addrspace(1) [[OUT]], align 4570; CHECK-NEXT: [[NO_MD_AFN:%.*]] = call afn float @llvm.sqrt.f32(float [[X]])571; CHECK-NEXT: store volatile float [[NO_MD_AFN]], ptr addrspace(1) [[OUT]], align 4572; CHECK-NEXT: ret void573;574 %fabs.x = call float @llvm.fabs.f32(float %x)575 %is.not.subnormal = fcmp oge float %fabs.x, 0x3810000000000000576 call void @llvm.assume(i1 %is.not.subnormal)577 578 %no.md = call float @llvm.sqrt.f32(float %x)579 store volatile float %no.md, ptr addrspace(1) %out, align 4580 581 %md.half.ulp = call float @llvm.sqrt.f32(float %x), !fpmath !1582 store volatile float %md.half.ulp, ptr addrspace(1) %out, align 4583 584 %md.1ulp = call float @llvm.sqrt.f32(float %x), !fpmath !2585 store volatile float %md.1ulp, ptr addrspace(1) %out, align 4586 587 %md.25ulp = call float @llvm.sqrt.f32(float %x), !fpmath !0588 store volatile float %md.25ulp, ptr addrspace(1) %out, align 4589 590 %md.3ulp = call float @llvm.sqrt.f32(float %x), !fpmath !3591 store volatile float %md.3ulp, ptr addrspace(1) %out, align 4592 593 %md.2ulp = call float @llvm.sqrt.f32(float %x), !fpmath !4594 store volatile float %md.2ulp, ptr addrspace(1) %out, align 4595 596 %md.3ulp.afn = call afn float @llvm.sqrt.f32(float %x), !fpmath !3597 store volatile float %md.3ulp, ptr addrspace(1) %out, align 4598 599 %no.md.afn = call afn float @llvm.sqrt.f32(float %x)600 store volatile float %no.md.afn, ptr addrspace(1) %out, align 4601 602 ret void603}604 605declare float @llvm.sqrt.f32(float)606declare <2 x float> @llvm.sqrt.v2f32(<2 x float>)607declare float @llvm.fabs.f32(float)608declare void @llvm.assume(i1 noundef)609 610attributes #0 = { optnone noinline }611 612!0 = !{float 2.500000e+00}613!1 = !{float 5.000000e-01}614!2 = !{float 1.000000e+00}615!3 = !{float 3.000000e+00}616!4 = !{float 2.000000e+00}617