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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s 2>&1 | FileCheck -check-prefix=GFX12 %s3; RUN: llc -mtriple=amdgcn -mcpu=gfx942 < %s 2>&1 | FileCheck -check-prefix=GFX942 %s4 5; These situations are "special" in that they either have an alloca that is not6; in the entry block or that they have a dynamic alloca. Both situations affect7; prolog/epilog generation.8 9declare amdgpu_gfx void @foo()10 11define amdgpu_cs_chain void @test_alloca() {12; GFX12-LABEL: test_alloca:13; GFX12: ; %bb.0: ; %.entry14; GFX12-NEXT: s_wait_loadcnt_dscnt 0x015; GFX12-NEXT: s_wait_expcnt 0x016; GFX12-NEXT: s_wait_samplecnt 0x017; GFX12-NEXT: s_wait_bvhcnt 0x018; GFX12-NEXT: s_wait_kmcnt 0x019; GFX12-NEXT: v_mov_b32_e32 v0, 020; GFX12-NEXT: s_mov_b32 s32, 1621; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)22; GFX12-NEXT: s_mov_b32 s0, s3223; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)24; GFX12-NEXT: s_add_co_i32 s32, s0, 0x20025; GFX12-NEXT: scratch_store_b32 off, v0, s026; GFX12-NEXT: s_endpgm27;28; GFX942-LABEL: test_alloca:29; GFX942: ; %bb.0: ; %.entry30; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)31; GFX942-NEXT: s_mov_b32 s32, 1632; GFX942-NEXT: s_mov_b32 s0, s3233; GFX942-NEXT: v_mov_b32_e32 v0, 034; GFX942-NEXT: s_add_i32 s32, s0, 0x40035; GFX942-NEXT: scratch_store_dword off, v0, s036; GFX942-NEXT: s_endpgm37.entry:38 br label %SW_C39 40SW_C: ; preds = %.entry41 %v = alloca i32, i32 1, align 4, addrspace(5)42 store i32 0, ptr addrspace(5) %v, align 443 ret void44}45 46define amdgpu_cs_chain void @test_alloca_var_uniform(i32 inreg %count) {47; GFX12-LABEL: test_alloca_var_uniform:48; GFX12: ; %bb.0:49; GFX12-NEXT: s_wait_loadcnt_dscnt 0x050; GFX12-NEXT: s_wait_expcnt 0x051; GFX12-NEXT: s_wait_samplecnt 0x052; GFX12-NEXT: s_wait_bvhcnt 0x053; GFX12-NEXT: s_wait_kmcnt 0x054; GFX12-NEXT: s_lshl2_add_u32 s0, s0, 1555; GFX12-NEXT: v_mov_b32_e32 v0, 056; GFX12-NEXT: s_mov_b32 s32, 1657; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)58; GFX12-NEXT: s_and_b32 s0, s0, -1659; GFX12-NEXT: s_mov_b32 s1, s3260; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)61; GFX12-NEXT: s_lshl_b32 s0, s0, 562; GFX12-NEXT: scratch_store_b32 off, v0, s163; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)64; GFX12-NEXT: s_add_co_i32 s32, s1, s065; GFX12-NEXT: s_endpgm66;67; GFX942-LABEL: test_alloca_var_uniform:68; GFX942: ; %bb.0:69; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)70; GFX942-NEXT: s_lshl2_add_u32 s0, s0, 1571; GFX942-NEXT: s_mov_b32 s32, 1672; GFX942-NEXT: s_and_b32 s0, s0, -1673; GFX942-NEXT: v_mov_b32_e32 v0, 074; GFX942-NEXT: s_lshl_b32 s0, s0, 675; GFX942-NEXT: s_mov_b32 s1, s3276; GFX942-NEXT: s_add_i32 s32, s1, s077; GFX942-NEXT: scratch_store_dword off, v0, s178; GFX942-NEXT: s_endpgm79 %v = alloca i32, i32 %count, align 4, addrspace(5)80 store i32 0, ptr addrspace(5) %v, align 481 ret void82}83 84define amdgpu_cs_chain void @test_alloca_var(i32 %count) {85; GFX12-LABEL: test_alloca_var:86; GFX12: ; %bb.0:87; GFX12-NEXT: s_wait_loadcnt_dscnt 0x088; GFX12-NEXT: s_wait_expcnt 0x089; GFX12-NEXT: s_wait_samplecnt 0x090; GFX12-NEXT: s_wait_bvhcnt 0x091; GFX12-NEXT: s_wait_kmcnt 0x092; GFX12-NEXT: v_lshl_add_u32 v0, v8, 2, 1593; GFX12-NEXT: s_mov_b32 s1, exec_lo94; GFX12-NEXT: s_mov_b32 s0, 095; GFX12-NEXT: s_mov_b32 s32, 1696; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)97; GFX12-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_and_b32 v1, -16, v098; GFX12-NEXT: .LBB2_1: ; =>This Inner Loop Header: Depth=199; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)100; GFX12-NEXT: s_ctz_i32_b32 s2, s1101; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)102; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)103; GFX12-NEXT: v_readlane_b32 s3, v1, s2104; GFX12-NEXT: s_bitset0_b32 s1, s2105; GFX12-NEXT: s_max_u32 s0, s0, s3106; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)107; GFX12-NEXT: s_cmp_lg_u32 s1, 0108; GFX12-NEXT: s_cbranch_scc1 .LBB2_1109; GFX12-NEXT: ; %bb.2:110; GFX12-NEXT: s_mov_b32 s1, s32111; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)112; GFX12-NEXT: v_lshl_add_u32 v1, s0, 5, s1113; GFX12-NEXT: scratch_store_b32 off, v0, s1114; GFX12-NEXT: v_readfirstlane_b32 s32, v1115; GFX12-NEXT: s_endpgm116;117; GFX942-LABEL: test_alloca_var:118; GFX942: ; %bb.0:119; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)120; GFX942-NEXT: v_lshl_add_u32 v0, v8, 2, 15121; GFX942-NEXT: v_and_b32_e32 v1, -16, v0122; GFX942-NEXT: v_mov_b32_e32 v0, 0123; GFX942-NEXT: s_mov_b64 s[0:1], exec124; GFX942-NEXT: s_mov_b32 s2, 0125; GFX942-NEXT: s_mov_b32 s32, 16126; GFX942-NEXT: .LBB2_1: ; =>This Inner Loop Header: Depth=1127; GFX942-NEXT: s_ff1_i32_b64 s3, s[0:1]128; GFX942-NEXT: v_readlane_b32 s4, v1, s3129; GFX942-NEXT: s_bitset0_b64 s[0:1], s3130; GFX942-NEXT: s_max_u32 s2, s2, s4131; GFX942-NEXT: s_cmp_lg_u64 s[0:1], 0132; GFX942-NEXT: s_cbranch_scc1 .LBB2_1133; GFX942-NEXT: ; %bb.2:134; GFX942-NEXT: s_mov_b32 s0, s32135; GFX942-NEXT: v_mov_b32_e32 v1, s0136; GFX942-NEXT: v_lshl_add_u32 v1, s2, 6, v1137; GFX942-NEXT: scratch_store_dword off, v0, s0138; GFX942-NEXT: v_readfirstlane_b32 s32, v1139; GFX942-NEXT: s_endpgm140 %v = alloca i32, i32 %count, align 4, addrspace(5)141 store i32 0, ptr addrspace(5) %v, align 4142 ret void143}144 145define amdgpu_cs_chain void @test_alloca_and_call() {146; GFX12-LABEL: test_alloca_and_call:147; GFX12: ; %bb.0: ; %.entry148; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0149; GFX12-NEXT: s_wait_expcnt 0x0150; GFX12-NEXT: s_wait_samplecnt 0x0151; GFX12-NEXT: s_wait_bvhcnt 0x0152; GFX12-NEXT: s_wait_kmcnt 0x0153; GFX12-NEXT: s_getpc_b64 s[0:1]154; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)155; GFX12-NEXT: s_sext_i32_i16 s1, s1156; GFX12-NEXT: s_add_co_u32 s0, s0, foo@gotpcrel32@lo+12157; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)158; GFX12-NEXT: s_add_co_ci_u32 s1, s1, foo@gotpcrel32@hi+24159; GFX12-NEXT: v_mov_b32_e32 v0, 0160; GFX12-NEXT: s_load_b64 s[0:1], s[0:1], 0x0161; GFX12-NEXT: s_mov_b32 s32, 16162; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)163; GFX12-NEXT: s_mov_b32 s2, s32164; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)165; GFX12-NEXT: s_add_co_i32 s32, s2, 0x200166; GFX12-NEXT: scratch_store_b32 off, v0, s2167; GFX12-NEXT: s_wait_kmcnt 0x0168; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)169; GFX12-NEXT: s_swappc_b64 s[30:31], s[0:1]170; GFX12-NEXT: s_endpgm171;172; GFX942-LABEL: test_alloca_and_call:173; GFX942: ; %bb.0: ; %.entry174; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)175; GFX942-NEXT: s_getpc_b64 s[0:1]176; GFX942-NEXT: s_add_u32 s0, s0, foo@gotpcrel32@lo+4177; GFX942-NEXT: s_addc_u32 s1, s1, foo@gotpcrel32@hi+12178; GFX942-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0179; GFX942-NEXT: s_mov_b32 s32, 16180; GFX942-NEXT: s_mov_b32 s2, s32181; GFX942-NEXT: v_mov_b32_e32 v0, 0182; GFX942-NEXT: s_add_i32 s32, s2, 0x400183; GFX942-NEXT: scratch_store_dword off, v0, s2184; GFX942-NEXT: s_waitcnt lgkmcnt(0)185; GFX942-NEXT: s_swappc_b64 s[30:31], s[0:1]186; GFX942-NEXT: s_endpgm187.entry:188 br label %SW_C189 190SW_C: ; preds = %.entry191 %v = alloca i32, i32 1, align 4, addrspace(5)192 store i32 0, ptr addrspace(5) %v, align 4193 call amdgpu_gfx void @foo()194 ret void195}196 197define amdgpu_cs_chain void @test_alloca_and_call_var_uniform(i32 inreg %count) {198; GFX12-LABEL: test_alloca_and_call_var_uniform:199; GFX12: ; %bb.0:200; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0201; GFX12-NEXT: s_wait_expcnt 0x0202; GFX12-NEXT: s_wait_samplecnt 0x0203; GFX12-NEXT: s_wait_bvhcnt 0x0204; GFX12-NEXT: s_wait_kmcnt 0x0205; GFX12-NEXT: s_getpc_b64 s[2:3]206; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)207; GFX12-NEXT: s_sext_i32_i16 s3, s3208; GFX12-NEXT: s_add_co_u32 s2, s2, foo@gotpcrel32@lo+12209; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)210; GFX12-NEXT: s_add_co_ci_u32 s3, s3, foo@gotpcrel32@hi+24211; GFX12-NEXT: s_lshl2_add_u32 s0, s0, 15212; GFX12-NEXT: s_load_b64 s[2:3], s[2:3], 0x0213; GFX12-NEXT: v_mov_b32_e32 v0, 0214; GFX12-NEXT: s_mov_b32 s32, 16215; GFX12-NEXT: s_and_b32 s0, s0, -16216; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)217; GFX12-NEXT: s_mov_b32 s1, s32218; GFX12-NEXT: s_lshl_b32 s0, s0, 5219; GFX12-NEXT: scratch_store_b32 off, v0, s1220; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)221; GFX12-NEXT: s_add_co_i32 s32, s1, s0222; GFX12-NEXT: s_wait_kmcnt 0x0223; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)224; GFX12-NEXT: s_swappc_b64 s[30:31], s[2:3]225; GFX12-NEXT: s_endpgm226;227; GFX942-LABEL: test_alloca_and_call_var_uniform:228; GFX942: ; %bb.0:229; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)230; GFX942-NEXT: s_lshl2_add_u32 s0, s0, 15231; GFX942-NEXT: s_and_b32 s0, s0, -16232; GFX942-NEXT: s_lshl_b32 s2, s0, 6233; GFX942-NEXT: s_getpc_b64 s[0:1]234; GFX942-NEXT: s_add_u32 s0, s0, foo@gotpcrel32@lo+4235; GFX942-NEXT: s_addc_u32 s1, s1, foo@gotpcrel32@hi+12236; GFX942-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0237; GFX942-NEXT: s_mov_b32 s32, 16238; GFX942-NEXT: v_mov_b32_e32 v0, 0239; GFX942-NEXT: s_mov_b32 s3, s32240; GFX942-NEXT: s_add_i32 s32, s3, s2241; GFX942-NEXT: scratch_store_dword off, v0, s3242; GFX942-NEXT: s_waitcnt lgkmcnt(0)243; GFX942-NEXT: s_swappc_b64 s[30:31], s[0:1]244; GFX942-NEXT: s_endpgm245 %v = alloca i32, i32 %count, align 4, addrspace(5)246 store i32 0, ptr addrspace(5) %v, align 4247 call amdgpu_gfx void @foo()248 ret void249}250 251define amdgpu_cs_chain void @test_alloca_and_call_var(i32 %count) {252; GFX12-LABEL: test_alloca_and_call_var:253; GFX12: ; %bb.0:254; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0255; GFX12-NEXT: s_wait_expcnt 0x0256; GFX12-NEXT: s_wait_samplecnt 0x0257; GFX12-NEXT: s_wait_bvhcnt 0x0258; GFX12-NEXT: s_wait_kmcnt 0x0259; GFX12-NEXT: v_lshl_add_u32 v0, v8, 2, 15260; GFX12-NEXT: s_mov_b32 s1, exec_lo261; GFX12-NEXT: s_mov_b32 s0, 0262; GFX12-NEXT: s_mov_b32 s32, 16263; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)264; GFX12-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_and_b32 v1, -16, v0265; GFX12-NEXT: .LBB5_1: ; =>This Inner Loop Header: Depth=1266; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)267; GFX12-NEXT: s_ctz_i32_b32 s2, s1268; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)269; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)270; GFX12-NEXT: v_readlane_b32 s3, v1, s2271; GFX12-NEXT: s_bitset0_b32 s1, s2272; GFX12-NEXT: s_max_u32 s0, s0, s3273; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)274; GFX12-NEXT: s_cmp_lg_u32 s1, 0275; GFX12-NEXT: s_cbranch_scc1 .LBB5_1276; GFX12-NEXT: ; %bb.2:277; GFX12-NEXT: s_getpc_b64 s[2:3]278; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)279; GFX12-NEXT: s_sext_i32_i16 s3, s3280; GFX12-NEXT: s_add_co_u32 s2, s2, foo@gotpcrel32@lo+12281; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)282; GFX12-NEXT: s_add_co_ci_u32 s3, s3, foo@gotpcrel32@hi+24283; GFX12-NEXT: s_mov_b32 s1, s32284; GFX12-NEXT: s_load_b64 s[2:3], s[2:3], 0x0285; GFX12-NEXT: v_lshl_add_u32 v1, s0, 5, s1286; GFX12-NEXT: scratch_store_b32 off, v0, s1287; GFX12-NEXT: v_readfirstlane_b32 s32, v1288; GFX12-NEXT: s_wait_kmcnt 0x0289; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)290; GFX12-NEXT: s_swappc_b64 s[30:31], s[2:3]291; GFX12-NEXT: s_endpgm292;293; GFX942-LABEL: test_alloca_and_call_var:294; GFX942: ; %bb.0:295; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)296; GFX942-NEXT: v_lshl_add_u32 v0, v8, 2, 15297; GFX942-NEXT: v_and_b32_e32 v1, -16, v0298; GFX942-NEXT: v_mov_b32_e32 v0, 0299; GFX942-NEXT: s_mov_b64 s[0:1], exec300; GFX942-NEXT: s_mov_b32 s2, 0301; GFX942-NEXT: s_mov_b32 s32, 16302; GFX942-NEXT: .LBB5_1: ; =>This Inner Loop Header: Depth=1303; GFX942-NEXT: s_ff1_i32_b64 s3, s[0:1]304; GFX942-NEXT: v_readlane_b32 s4, v1, s3305; GFX942-NEXT: s_bitset0_b64 s[0:1], s3306; GFX942-NEXT: s_max_u32 s2, s2, s4307; GFX942-NEXT: s_cmp_lg_u64 s[0:1], 0308; GFX942-NEXT: s_cbranch_scc1 .LBB5_1309; GFX942-NEXT: ; %bb.2:310; GFX942-NEXT: s_getpc_b64 s[0:1]311; GFX942-NEXT: s_add_u32 s0, s0, foo@gotpcrel32@lo+4312; GFX942-NEXT: s_addc_u32 s1, s1, foo@gotpcrel32@hi+12313; GFX942-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0314; GFX942-NEXT: s_mov_b32 s3, s32315; GFX942-NEXT: v_mov_b32_e32 v1, s3316; GFX942-NEXT: v_lshl_add_u32 v1, s2, 6, v1317; GFX942-NEXT: scratch_store_dword off, v0, s3318; GFX942-NEXT: v_readfirstlane_b32 s32, v1319; GFX942-NEXT: s_waitcnt lgkmcnt(0)320; GFX942-NEXT: s_swappc_b64 s[30:31], s[0:1]321; GFX942-NEXT: s_endpgm322 %v = alloca i32, i32 %count, align 4, addrspace(5)323 store i32 0, ptr addrspace(5) %v, align 4324 call amdgpu_gfx void @foo()325 ret void326}327 328define amdgpu_cs_chain void @test_call_and_alloca() {329; GFX12-LABEL: test_call_and_alloca:330; GFX12: ; %bb.0: ; %.entry331; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0332; GFX12-NEXT: s_wait_expcnt 0x0333; GFX12-NEXT: s_wait_samplecnt 0x0334; GFX12-NEXT: s_wait_bvhcnt 0x0335; GFX12-NEXT: s_wait_kmcnt 0x0336; GFX12-NEXT: s_getpc_b64 s[0:1]337; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)338; GFX12-NEXT: s_sext_i32_i16 s1, s1339; GFX12-NEXT: s_add_co_u32 s0, s0, foo@gotpcrel32@lo+12340; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)341; GFX12-NEXT: s_add_co_ci_u32 s1, s1, foo@gotpcrel32@hi+24342; GFX12-NEXT: s_mov_b32 s32, 16343; GFX12-NEXT: s_load_b64 s[0:1], s[0:1], 0x0344; GFX12-NEXT: s_mov_b32 s4, s32345; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)346; GFX12-NEXT: s_add_co_i32 s32, s4, 0x200347; GFX12-NEXT: s_wait_kmcnt 0x0348; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)349; GFX12-NEXT: s_swappc_b64 s[30:31], s[0:1]350; GFX12-NEXT: v_mov_b32_e32 v0, 0351; GFX12-NEXT: scratch_store_b32 off, v0, s4352; GFX12-NEXT: s_endpgm353;354; GFX942-LABEL: test_call_and_alloca:355; GFX942: ; %bb.0: ; %.entry356; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)357; GFX942-NEXT: s_getpc_b64 s[0:1]358; GFX942-NEXT: s_add_u32 s0, s0, foo@gotpcrel32@lo+4359; GFX942-NEXT: s_addc_u32 s1, s1, foo@gotpcrel32@hi+12360; GFX942-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0361; GFX942-NEXT: s_mov_b32 s32, 16362; GFX942-NEXT: s_mov_b32 s4, s32363; GFX942-NEXT: s_add_i32 s32, s4, 0x400364; GFX942-NEXT: s_waitcnt lgkmcnt(0)365; GFX942-NEXT: s_swappc_b64 s[30:31], s[0:1]366; GFX942-NEXT: v_mov_b32_e32 v0, 0367; GFX942-NEXT: scratch_store_dword off, v0, s4368; GFX942-NEXT: s_endpgm369.entry:370 br label %SW_C371 372SW_C: ; preds = %.entry373 %v = alloca i32, i32 1, align 4, addrspace(5)374 call amdgpu_gfx void @foo()375 store i32 0, ptr addrspace(5) %v, align 4376 ret void377}378 379define amdgpu_cs_chain void @test_call_and_alloca_var_uniform(i32 inreg %count) {380; GFX12-LABEL: test_call_and_alloca_var_uniform:381; GFX12: ; %bb.0:382; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0383; GFX12-NEXT: s_wait_expcnt 0x0384; GFX12-NEXT: s_wait_samplecnt 0x0385; GFX12-NEXT: s_wait_bvhcnt 0x0386; GFX12-NEXT: s_wait_kmcnt 0x0387; GFX12-NEXT: s_getpc_b64 s[2:3]388; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)389; GFX12-NEXT: s_sext_i32_i16 s3, s3390; GFX12-NEXT: s_add_co_u32 s2, s2, foo@gotpcrel32@lo+12391; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)392; GFX12-NEXT: s_add_co_ci_u32 s3, s3, foo@gotpcrel32@hi+24393; GFX12-NEXT: s_lshl2_add_u32 s0, s0, 15394; GFX12-NEXT: s_load_b64 s[2:3], s[2:3], 0x0395; GFX12-NEXT: s_mov_b32 s32, 16396; GFX12-NEXT: s_and_b32 s0, s0, -16397; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)398; GFX12-NEXT: s_mov_b32 s4, s32399; GFX12-NEXT: s_lshl_b32 s0, s0, 5400; GFX12-NEXT: v_mov_b32_e32 v40, 0401; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)402; GFX12-NEXT: s_add_co_i32 s32, s4, s0403; GFX12-NEXT: s_wait_kmcnt 0x0404; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)405; GFX12-NEXT: s_swappc_b64 s[30:31], s[2:3]406; GFX12-NEXT: scratch_store_b32 off, v40, s4407; GFX12-NEXT: s_endpgm408;409; GFX942-LABEL: test_call_and_alloca_var_uniform:410; GFX942: ; %bb.0:411; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)412; GFX942-NEXT: s_lshl2_add_u32 s0, s0, 15413; GFX942-NEXT: s_and_b32 s0, s0, -16414; GFX942-NEXT: s_lshl_b32 s2, s0, 6415; GFX942-NEXT: s_getpc_b64 s[0:1]416; GFX942-NEXT: s_add_u32 s0, s0, foo@gotpcrel32@lo+4417; GFX942-NEXT: s_addc_u32 s1, s1, foo@gotpcrel32@hi+12418; GFX942-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0419; GFX942-NEXT: s_mov_b32 s32, 16420; GFX942-NEXT: s_mov_b32 s4, s32421; GFX942-NEXT: v_mov_b32_e32 v40, 0422; GFX942-NEXT: s_add_i32 s32, s4, s2423; GFX942-NEXT: s_waitcnt lgkmcnt(0)424; GFX942-NEXT: s_swappc_b64 s[30:31], s[0:1]425; GFX942-NEXT: scratch_store_dword off, v40, s4426; GFX942-NEXT: s_endpgm427 %v = alloca i32, i32 %count, align 4, addrspace(5)428 call amdgpu_gfx void @foo()429 store i32 0, ptr addrspace(5) %v, align 4430 ret void431}432 433define amdgpu_cs_chain void @test_call_and_alloca_var(i32 %count) {434; GFX12-LABEL: test_call_and_alloca_var:435; GFX12: ; %bb.0:436; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0437; GFX12-NEXT: s_wait_expcnt 0x0438; GFX12-NEXT: s_wait_samplecnt 0x0439; GFX12-NEXT: s_wait_bvhcnt 0x0440; GFX12-NEXT: s_wait_kmcnt 0x0441; GFX12-NEXT: v_lshl_add_u32 v0, v8, 2, 15442; GFX12-NEXT: v_mov_b32_e32 v40, 0443; GFX12-NEXT: s_mov_b32 s1, exec_lo444; GFX12-NEXT: s_mov_b32 s0, 0445; GFX12-NEXT: s_mov_b32 s32, 16446; GFX12-NEXT: v_and_b32_e32 v0, -16, v0447; GFX12-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1448; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)449; GFX12-NEXT: s_ctz_i32_b32 s2, s1450; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)451; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)452; GFX12-NEXT: v_readlane_b32 s3, v0, s2453; GFX12-NEXT: s_bitset0_b32 s1, s2454; GFX12-NEXT: s_max_u32 s0, s0, s3455; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)456; GFX12-NEXT: s_cmp_lg_u32 s1, 0457; GFX12-NEXT: s_cbranch_scc1 .LBB8_1458; GFX12-NEXT: ; %bb.2:459; GFX12-NEXT: s_getpc_b64 s[2:3]460; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)461; GFX12-NEXT: s_sext_i32_i16 s3, s3462; GFX12-NEXT: s_add_co_u32 s2, s2, foo@gotpcrel32@lo+12463; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)464; GFX12-NEXT: s_add_co_ci_u32 s3, s3, foo@gotpcrel32@hi+24465; GFX12-NEXT: s_mov_b32 s4, s32466; GFX12-NEXT: s_load_b64 s[2:3], s[2:3], 0x0467; GFX12-NEXT: v_lshl_add_u32 v0, s0, 5, s4468; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)469; GFX12-NEXT: v_readfirstlane_b32 s32, v0470; GFX12-NEXT: s_wait_kmcnt 0x0471; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)472; GFX12-NEXT: s_swappc_b64 s[30:31], s[2:3]473; GFX12-NEXT: scratch_store_b32 off, v40, s4474; GFX12-NEXT: s_endpgm475;476; GFX942-LABEL: test_call_and_alloca_var:477; GFX942: ; %bb.0:478; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)479; GFX942-NEXT: v_lshl_add_u32 v0, v8, 2, 15480; GFX942-NEXT: v_and_b32_e32 v0, -16, v0481; GFX942-NEXT: v_mov_b32_e32 v40, 0482; GFX942-NEXT: s_mov_b64 s[0:1], exec483; GFX942-NEXT: s_mov_b32 s2, 0484; GFX942-NEXT: s_mov_b32 s32, 16485; GFX942-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1486; GFX942-NEXT: s_ff1_i32_b64 s3, s[0:1]487; GFX942-NEXT: v_readlane_b32 s4, v0, s3488; GFX942-NEXT: s_bitset0_b64 s[0:1], s3489; GFX942-NEXT: s_max_u32 s2, s2, s4490; GFX942-NEXT: s_cmp_lg_u64 s[0:1], 0491; GFX942-NEXT: s_cbranch_scc1 .LBB8_1492; GFX942-NEXT: ; %bb.2:493; GFX942-NEXT: s_getpc_b64 s[0:1]494; GFX942-NEXT: s_add_u32 s0, s0, foo@gotpcrel32@lo+4495; GFX942-NEXT: s_addc_u32 s1, s1, foo@gotpcrel32@hi+12496; GFX942-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0497; GFX942-NEXT: s_mov_b32 s4, s32498; GFX942-NEXT: v_mov_b32_e32 v0, s4499; GFX942-NEXT: v_lshl_add_u32 v0, s2, 6, v0500; GFX942-NEXT: s_nop 0501; GFX942-NEXT: v_readfirstlane_b32 s32, v0502; GFX942-NEXT: s_waitcnt lgkmcnt(0)503; GFX942-NEXT: s_swappc_b64 s[30:31], s[0:1]504; GFX942-NEXT: scratch_store_dword off, v40, s4505; GFX942-NEXT: s_endpgm506 %v = alloca i32, i32 %count, align 4, addrspace(5)507 call amdgpu_gfx void @foo()508 store i32 0, ptr addrspace(5) %v, align 4509 ret void510}511