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1; RUN: opt -mtriple=amdgcn--amdhsa -data-layout=A5 -O3 -S -inline-threshold=1 < %s | FileCheck -check-prefixes=GCN,GCN-INL1,GCN-MAXBBDEF %s2; RUN: opt -mtriple=amdgcn--amdhsa -data-layout=A5 -O3 -S < %s | FileCheck -check-prefixes=GCN,GCN-INLDEF,GCN-MAXBBDEF %s3; RUN: opt -mtriple=amdgcn--amdhsa -data-layout=A5 -passes='default<O3>' -S -inline-threshold=1 < %s | FileCheck -check-prefixes=GCN,GCN-INL1,GCN-MAXBBDEF %s4; RUN: opt -mtriple=amdgcn--amdhsa -data-layout=A5 -passes='default<O3>' -S < %s | FileCheck -check-prefixes=GCN,GCN-INLDEF,GCN-MAXBBDEF %s5; RUN: opt -mtriple=amdgcn--amdhsa -data-layout=A5 -passes='default<O3>' -S -amdgpu-inline-max-bb=1 < %s | FileCheck -check-prefixes=GCN,GCN-MAXBB1 %s6 7define coldcc float @foo(float %x, float %y) {8entry:9 %cmp = fcmp ogt float %x, 0.000000e+0010 %div = fdiv float %y, %x11 %mul = fmul float %x, %y12 %cond = select i1 %cmp, float %div, float %mul13 ret float %cond14}15 16define coldcc void @foo_private_ptr(ptr addrspace(5) nocapture %p) {17entry:18 %tmp1 = load float, ptr addrspace(5) %p, align 419 %cmp = fcmp ogt float %tmp1, 1.000000e+0020 br i1 %cmp, label %if.then, label %if.end21 22if.then: ; preds = %entry23 %div = fdiv float 1.000000e+00, %tmp124 store float %div, ptr addrspace(5) %p, align 425 br label %if.end26 27if.end: ; preds = %if.then, %entry28 ret void29}30 31define coldcc void @foo_private_ptr2(ptr addrspace(5) nocapture %p1, ptr addrspace(5) nocapture %p2) {32entry:33 call void @forbid_sroa(ptr addrspace(5) %p1)34 call void @forbid_sroa(ptr addrspace(5) %p2)35 %tmp1 = load float, ptr addrspace(5) %p1, align 436 %cmp = fcmp ogt float %tmp1, 1.000000e+0037 br i1 %cmp, label %if.then, label %if.end38 39if.then:40 %div = fdiv float 2.000000e+00, %tmp141 store float %div, ptr addrspace(5) %p2, align 442 br label %if.end43 44if.end:45 ret void46}47 48define float @sin_wrapper(float %x) {49bb:50 %call = tail call float @_Z3sinf(float %x)51 ret float %call52}53 54define void @foo_noinline(ptr addrspace(5) nocapture %p) #0 {55entry:56 %tmp1 = load float, ptr addrspace(5) %p, align 457 %mul = fmul float %tmp1, 2.000000e+0058 store float %mul, ptr addrspace(5) %p, align 459 ret void60}61 62; GCN: define amdgpu_kernel void @test_inliner(63; GCN-INL1: %c1 = tail call coldcc float @foo(64; GCN-INLDEF: %cmp.i = fcmp ogt float %{{.+}}, 0.000000e+0065; GCN-MAXBBDEF: %div.i{{[0-9]*}} = fdiv float 1.000000e+00, %c66; GCN-MAXBBDEF: %div.i{{[0-9]*}} = fdiv float 2.000000e+00, %tmp1.i67; GCN-MAXBB1: call coldcc void @foo_private_ptr68; GCN-MAXBB1: call coldcc void @foo_private_ptr269; GCN: call void @foo_noinline(70; GCN: tail call float @_Z3sinf(71define amdgpu_kernel void @test_inliner(ptr addrspace(1) nocapture %a, i32 %n) {72entry:73 %pvt_arr = alloca [64 x float], align 4, addrspace(5)74 %tid = tail call i32 @llvm.amdgcn.workitem.id.x()75 %arrayidx = getelementptr inbounds float, ptr addrspace(1) %a, i32 %tid76 %tmp2 = load float, ptr addrspace(1) %arrayidx, align 477 %add = add i32 %tid, 178 %arrayidx2 = getelementptr inbounds float, ptr addrspace(1) %a, i32 %add79 %tmp5 = load float, ptr addrspace(1) %arrayidx2, align 480 %c1 = tail call coldcc float @foo(float %tmp2, float %tmp5)81 %or = or i32 %tid, %n82 %arrayidx5 = getelementptr inbounds [64 x float], ptr addrspace(5) %pvt_arr, i32 0, i32 %or83 store float %c1, ptr addrspace(5) %arrayidx5, align 484 %arrayidx7 = getelementptr inbounds [64 x float], ptr addrspace(5) %pvt_arr, i32 0, i32 %or85 call coldcc void @foo_private_ptr(ptr addrspace(5) %arrayidx7)86 %arrayidx8 = getelementptr inbounds [64 x float], ptr addrspace(5) %pvt_arr, i32 0, i32 187 %arrayidx9 = getelementptr inbounds [64 x float], ptr addrspace(5) %pvt_arr, i32 0, i32 288 call coldcc void @foo_private_ptr2(ptr addrspace(5) %arrayidx8, ptr addrspace(5) %arrayidx9)89 call void @foo_noinline(ptr addrspace(5) %arrayidx7)90 %and = and i32 %tid, %n91 %arrayidx11 = getelementptr inbounds [64 x float], ptr addrspace(5) %pvt_arr, i32 0, i32 %and92 %tmp12 = load float, ptr addrspace(5) %arrayidx11, align 493 %c2 = call float @sin_wrapper(float %tmp12)94 store float %c2, ptr addrspace(5) %arrayidx7, align 495 %xor = xor i32 %tid, %n96 %arrayidx16 = getelementptr inbounds [64 x float], ptr addrspace(5) %pvt_arr, i32 0, i32 %xor97 %tmp16 = load float, ptr addrspace(5) %arrayidx16, align 498 store float %tmp16, ptr addrspace(1) %arrayidx, align 499 ret void100}101 102; GCN: define amdgpu_kernel void @test_inliner_multi_pvt_ptr(103; GCN-MAXBBDEF: %div.i{{[0-9]*}} = fdiv float 2.000000e+00, %tmp1.i104; GCN-MAXBB1: call coldcc void @foo_private_ptr2105define amdgpu_kernel void @test_inliner_multi_pvt_ptr(ptr addrspace(1) nocapture %a, i32 %n, float %v) {106entry:107 %pvt_arr1 = alloca [32 x float], align 4, addrspace(5)108 %pvt_arr2 = alloca [32 x float], align 4, addrspace(5)109 %tid = tail call i32 @llvm.amdgcn.workitem.id.x()110 %arrayidx = getelementptr inbounds float, ptr addrspace(1) %a, i32 %tid111 %or = or i32 %tid, %n112 %arrayidx4 = getelementptr inbounds [32 x float], ptr addrspace(5) %pvt_arr1, i32 0, i32 %or113 %arrayidx5 = getelementptr inbounds [32 x float], ptr addrspace(5) %pvt_arr2, i32 0, i32 %or114 store float %v, ptr addrspace(5) %arrayidx4, align 4115 store float %v, ptr addrspace(5) %arrayidx5, align 4116 %arrayidx8 = getelementptr inbounds [32 x float], ptr addrspace(5) %pvt_arr1, i32 0, i32 1117 %arrayidx9 = getelementptr inbounds [32 x float], ptr addrspace(5) %pvt_arr2, i32 0, i32 2118 call coldcc void @foo_private_ptr2(ptr addrspace(5) %arrayidx8, ptr addrspace(5) %arrayidx9)119 %xor = xor i32 %tid, %n120 %arrayidx15 = getelementptr inbounds [32 x float], ptr addrspace(5) %pvt_arr1, i32 0, i32 %xor121 %arrayidx16 = getelementptr inbounds [32 x float], ptr addrspace(5) %pvt_arr2, i32 0, i32 %xor122 %tmp15 = load float, ptr addrspace(5) %arrayidx15, align 4123 %tmp16 = load float, ptr addrspace(5) %arrayidx16, align 4124 %tmp17 = fadd float %tmp15, %tmp16125 store float %tmp17, ptr addrspace(1) %arrayidx, align 4126 ret void127}128 129; GCN: define amdgpu_kernel void @test_inliner_multi_pvt_ptr_cutoff(130; GCN-INL1: call coldcc void @foo_private_ptr2131; GCN-INLDEF: %div.i{{[0-9]*}} = fdiv float 2.000000e+00, %tmp1.i132define amdgpu_kernel void @test_inliner_multi_pvt_ptr_cutoff(ptr addrspace(1) nocapture %a, i32 %n, float %v) {133entry:134 %pvt_arr1 = alloca [32 x float], align 4, addrspace(5)135 %pvt_arr2 = alloca [33 x float], align 4, addrspace(5)136 %tid = tail call i32 @llvm.amdgcn.workitem.id.x()137 %arrayidx = getelementptr inbounds float, ptr addrspace(1) %a, i32 %tid138 %or = or i32 %tid, %n139 %arrayidx4 = getelementptr inbounds [32 x float], ptr addrspace(5) %pvt_arr1, i32 0, i32 %or140 %arrayidx5 = getelementptr inbounds [33 x float], ptr addrspace(5) %pvt_arr2, i32 0, i32 %or141 store float %v, ptr addrspace(5) %arrayidx4, align 4142 store float %v, ptr addrspace(5) %arrayidx5, align 4143 %arrayidx8 = getelementptr inbounds [32 x float], ptr addrspace(5) %pvt_arr1, i32 0, i32 1144 %arrayidx9 = getelementptr inbounds [33 x float], ptr addrspace(5) %pvt_arr2, i32 0, i32 2145 call coldcc void @foo_private_ptr2(ptr addrspace(5) %arrayidx8, ptr addrspace(5) %arrayidx9)146 %xor = xor i32 %tid, %n147 %arrayidx15 = getelementptr inbounds [32 x float], ptr addrspace(5) %pvt_arr1, i32 0, i32 %xor148 %arrayidx16 = getelementptr inbounds [33 x float], ptr addrspace(5) %pvt_arr2, i32 0, i32 %xor149 %tmp15 = load float, ptr addrspace(5) %arrayidx15, align 4150 %tmp16 = load float, ptr addrspace(5) %arrayidx16, align 4151 %tmp17 = fadd float %tmp15, %tmp16152 store float %tmp17, ptr addrspace(1) %arrayidx, align 4153 ret void154}155 156; GCN: define amdgpu_kernel void @test_inliner_maxbb_singlebb(157; GCN: tail call float @_Z3sinf158define amdgpu_kernel void @test_inliner_maxbb_singlebb(ptr addrspace(1) nocapture %a, i32 %n) {159entry:160 %cmp = icmp eq i32 %n, 1161 br i1 %cmp, label %bb.1, label %bb.2162 br label %bb.1163 164bb.1:165 store float 1.0, ptr poison166 br label %bb.2167 168bb.2:169 %c = call float @sin_wrapper(float 1.0)170 store float %c, ptr addrspace(1) %a171 ret void172}173 174declare i32 @llvm.amdgcn.workitem.id.x() #1175declare float @_Z3sinf(float) #1176declare void @forbid_sroa(ptr addrspace(5) nocapture %p)177 178attributes #0 = { noinline }179attributes #1 = { nounwind readnone }180