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1; RUN: opt -S -mtriple=amdgcn-- -passes=amdgpu-lower-exec-sync,amdgpu-sw-lower-lds -amdgpu-asan-instrument-lds=false < %s 2>&1 | FileCheck %s2; RUN: llc < %s -enable-new-pm -stop-after=amdgpu-sw-lower-lds -amdgpu-asan-instrument-lds=false -mtriple=amdgcn-amd-amdhsa | FileCheck %s3 4; Test to ensure that LDS variables like named barriers are lowered correctly in asan scenario,5; where amdgpu-sw-lower-lds pass runs in pipeline after amdgpu-lower-exec-sync pass.6%class.ExpAmdWorkgroupWaveBarrier = type { target("amdgcn.named.barrier", 0) }7@bar2 = internal addrspace(3) global [2 x target("amdgcn.named.barrier", 0)] poison8@bar1 = internal addrspace(3) global [4 x %class.ExpAmdWorkgroupWaveBarrier] poison9@lds1 = internal addrspace(3) global [1 x i8] poison, align 410 11;.12; CHECK: @bar2 = internal addrspace(3) global [2 x target("amdgcn.named.barrier", 0)] poison, !absolute_symbol [[META0:![0-9]+]]13; CHECK: @bar1 = internal addrspace(3) global [4 x %class.ExpAmdWorkgroupWaveBarrier] poison, !absolute_symbol [[META1:![0-9]+]]14;15define void @bar() #0 {16; CHECK-LABEL: define void @bar(17; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {18; CHECK: call void @llvm.amdgcn.s.barrier.signal.var(ptr addrspace(3) @bar2, i32 7)19; CHECK: call void @llvm.amdgcn.s.barrier.join(ptr addrspace(3) @bar2)20; CHECK: call void @llvm.amdgcn.s.barrier.wait(i16 1)21; CHECK: store i8 7, ptr addrspace(1) {{.*}}, align 422;23 call void @llvm.amdgcn.s.barrier.signal.var(ptr addrspace(3) @bar2, i32 7)24 call void @llvm.amdgcn.s.barrier.join(ptr addrspace(3) @bar2)25 call void @llvm.amdgcn.s.barrier.wait(i16 1)26 store i8 7, ptr addrspace(3) @lds1, align 427 ret void28}29 30define amdgpu_kernel void @barkernel() #0 {31; CHECK-LABEL: define amdgpu_kernel void @barkernel(32; CHECK-SAME: ) #[[ATTR1:[0-9]+]] !llvm.amdgcn.lds.kernel.id [[META4:![0-9]+]] {33; CHECK: {{.*}} = call i64 @__asan_malloc_impl(i64 {{.*}}, i64 {{.*}})34; CHECK: call void @llvm.amdgcn.s.barrier()35; CHECK: call void @llvm.amdgcn.s.barrier.signal.var(ptr addrspace(3) @bar1, i32 9)36; CHECK: call void @llvm.amdgcn.s.barrier.join(ptr addrspace(3) @bar1)37; CHECK: call void @llvm.amdgcn.s.barrier.wait(i16 1)38; CHECK: call void @bar()39; CHECK: store i8 10, ptr addrspace(1) {{.*}}, align 440; CHECK: call void @__asan_free_impl(i64 {{.*}}, i64 {{.*}})41;42 call void @llvm.amdgcn.s.barrier.signal.var(ptr addrspace(3) @bar1, i32 9)43 call void @llvm.amdgcn.s.barrier.join(ptr addrspace(3) @bar1)44 call void @llvm.amdgcn.s.barrier.wait(i16 1)45 call void @bar()46 store i8 10, ptr addrspace(3) @lds1, align 447 ret void48}49 50declare void @llvm.amdgcn.s.barrier() #151declare void @llvm.amdgcn.s.barrier.wait(i16) #152declare void @llvm.amdgcn.s.barrier.signal(i32) #153declare void @llvm.amdgcn.s.barrier.signal.var(ptr addrspace(3), i32) #154declare i1 @llvm.amdgcn.s.barrier.signal.isfirst(i32) #155declare void @llvm.amdgcn.s.barrier.init(ptr addrspace(3), i32) #156declare void @llvm.amdgcn.s.barrier.join(ptr addrspace(3)) #157declare void @llvm.amdgcn.s.barrier.leave(i16) #158declare void @llvm.amdgcn.s.wakeup.barrier(ptr addrspace(3)) #159declare i32 @llvm.amdgcn.s.get.named.barrier.state(ptr addrspace(3)) #160 61attributes #0 = { nounwind sanitize_address }62attributes #1 = { convergent nounwind }63attributes #2 = { nounwind readnone }64 65!llvm.module.flags = !{!0}66!0 = !{i32 4, !"nosanitize_address", i32 1}67;.68; CHECK: attributes #[[ATTR0]] = { nounwind sanitize_address }69; CHECK: attributes #[[ATTR1]] = { nounwind sanitize_address "amdgpu-lds-size"="8" }70;.71; CHECK: [[META0]] = !{i32 8396880, i32 8396881}72; CHECK: [[META1]] = !{i32 8396816, i32 8396817}73;.74