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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -o - %s | FileCheck %s3define amdgpu_kernel void @readfirstlane_with_readfirstlane(ptr addrspace(1) %out) {4; CHECK-LABEL: readfirstlane_with_readfirstlane:5; CHECK: ; %bb.0:6; CHECK-NEXT: s_load_b64 s[0:1], s[4:5], 0x07; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 58; CHECK-NEXT: s_waitcnt lgkmcnt(0)9; CHECK-NEXT: global_store_b32 v0, v1, s[0:1]10; CHECK-NEXT: s_endpgm11 %v1 = call i32 @llvm.amdgcn.readfirstlane(i32 5)12 %v2 = call i32 @llvm.amdgcn.readfirstlane(i32 %v1)13 store i32 %v2, ptr addrspace(1) %out14 ret void15}16 17define amdgpu_kernel void @readfirstlane_with_readlane(ptr addrspace(1) %out) {18; CHECK-LABEL: readfirstlane_with_readlane:19; CHECK: ; %bb.0:20; CHECK-NEXT: s_load_b64 s[0:1], s[4:5], 0x021; CHECK-NEXT: v_bfe_u32 v1, v0, 10, 1022; CHECK-NEXT: v_and_b32_e32 v0, 0x3ff, v023; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)24; CHECK-NEXT: v_readfirstlane_b32 s2, v125; CHECK-NEXT: v_readlane_b32 s2, v0, s226; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)27; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s228; CHECK-NEXT: s_waitcnt lgkmcnt(0)29; CHECK-NEXT: global_store_b32 v0, v1, s[0:1]30; CHECK-NEXT: s_endpgm31 %tidx = call i32 @llvm.amdgcn.workitem.id.x()32 %tidy = call i32 @llvm.amdgcn.workitem.id.y()33 %v1 = call i32 @llvm.amdgcn.readlane(i32 %tidx, i32 %tidy)34 %v2 = call i32 @llvm.amdgcn.readfirstlane(i32 %v1)35 store i32 %v2, ptr addrspace(1) %out36 ret void37}38 39define amdgpu_kernel void @readlane_with_firstlane(ptr addrspace(1) %out) {40; CHECK-LABEL: readlane_with_firstlane:41; CHECK: ; %bb.0:42; CHECK-NEXT: s_load_b64 s[0:1], s[4:5], 0x043; CHECK-NEXT: v_and_b32_e32 v0, 0x3ff, v044; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)45; CHECK-NEXT: v_readfirstlane_b32 s2, v046; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s247; CHECK-NEXT: s_waitcnt lgkmcnt(0)48; CHECK-NEXT: global_store_b32 v0, v1, s[0:1]49; CHECK-NEXT: s_endpgm50 %tidx = call i32 @llvm.amdgcn.workitem.id.x()51 %v1 = call i32 @llvm.amdgcn.readfirstlane(i32 %tidx)52 %v2 = call i32 @llvm.amdgcn.readlane(i32 %v1, i32 3)53 store i32 %v2, ptr addrspace(1) %out54 ret void55}56 57define amdgpu_kernel void @readlane_readlane(ptr addrspace(1) %out) {58; CHECK-LABEL: readlane_readlane:59; CHECK: ; %bb.0:60; CHECK-NEXT: s_load_b64 s[0:1], s[4:5], 0x061; CHECK-NEXT: v_bfe_u32 v1, v0, 10, 1062; CHECK-NEXT: v_and_b32_e32 v0, 0x3ff, v063; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)64; CHECK-NEXT: v_readfirstlane_b32 s2, v165; CHECK-NEXT: v_readlane_b32 s2, v0, s266; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)67; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s268; CHECK-NEXT: s_waitcnt lgkmcnt(0)69; CHECK-NEXT: global_store_b32 v0, v1, s[0:1]70; CHECK-NEXT: s_endpgm71 %tidx = call i32 @llvm.amdgcn.workitem.id.x()72 %tidy = call i32 @llvm.amdgcn.workitem.id.y()73 %v1 = call i32 @llvm.amdgcn.readlane(i32 %tidx, i32 %tidy)74 %v2 = call i32 @llvm.amdgcn.readlane(i32 %v1, i32 2)75 store i32 %v2, ptr addrspace(1) %out76 ret void77}78 79define amdgpu_kernel void @permlane64_uniform(ptr addrspace(1) %out, i32 %src) {80; CHECK-LABEL: permlane64_uniform:81; CHECK: ; %bb.0:82; CHECK-NEXT: s_clause 0x183; CHECK-NEXT: s_load_b32 s2, s[4:5], 0x884; CHECK-NEXT: s_load_b64 s[0:1], s[4:5], 0x085; CHECK-NEXT: s_waitcnt lgkmcnt(0)86; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s287; CHECK-NEXT: global_store_b32 v0, v1, s[0:1]88; CHECK-NEXT: s_endpgm89 %v = call i32 @llvm.amdgcn.permlane64(i32 %src)90 store i32 %v, ptr addrspace(1) %out91 ret void92}93 94define amdgpu_kernel void @permlane64_nonuniform(i32 addrspace(1)* %out) {95; CHECK-LABEL: permlane64_nonuniform:96; CHECK: ; %bb.0:97; CHECK-NEXT: s_load_b64 s[0:1], s[4:5], 0x098; CHECK-NEXT: v_and_b32_e32 v0, 0x3ff, v099; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)100; CHECK-NEXT: v_permlane64_b32 v1, v0101; CHECK-NEXT: v_lshlrev_b32_e32 v0, 2, v0102; CHECK-NEXT: s_waitcnt lgkmcnt(0)103; CHECK-NEXT: global_store_b32 v0, v1, s[0:1]104; CHECK-NEXT: s_endpgm105 %tid = call i32 @llvm.amdgcn.workitem.id.x()106 %v = call i32 @llvm.amdgcn.permlane64(i32 %tid)107 %out_ptr = getelementptr i32, i32 addrspace(1)* %out, i32 %tid108 store i32 %v, i32 addrspace(1)* %out_ptr109 ret void110}111 112define amdgpu_kernel void @permlane64_nonuniform_expression(i32 addrspace(1)* %out) {113; CHECK-LABEL: permlane64_nonuniform_expression:114; CHECK: ; %bb.0:115; CHECK-NEXT: s_load_b64 s[0:1], s[4:5], 0x0116; CHECK-NEXT: v_and_b32_e32 v0, 0x3ff, v0117; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)118; CHECK-NEXT: v_add_nc_u32_e32 v1, 1, v0119; CHECK-NEXT: v_lshlrev_b32_e32 v0, 2, v0120; CHECK-NEXT: v_permlane64_b32 v1, v1121; CHECK-NEXT: s_waitcnt lgkmcnt(0)122; CHECK-NEXT: global_store_b32 v0, v1, s[0:1]123; CHECK-NEXT: s_endpgm124 %tid = call i32 @llvm.amdgcn.workitem.id.x()125 %tid2 = add i32 %tid, 1126 %v = call i32 @llvm.amdgcn.permlane64(i32 %tid2)127 %out_ptr = getelementptr i32, i32 addrspace(1)* %out, i32 %tid128 store i32 %v, i32 addrspace(1)* %out_ptr129 ret void130}131 132define protected amdgpu_kernel void @trivial_waterfall_eq_zero(ptr addrspace(1) %out) {133; CHECK-LABEL: trivial_waterfall_eq_zero:134; CHECK: ; %bb.0: ; %entry135; CHECK-NEXT: s_load_b64 s[0:1], s[4:5], 0x0136; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 5137; CHECK-NEXT: s_mov_b32 s2, 0138; CHECK-NEXT: s_branch .LBB7_2139; CHECK-NEXT: .LBB7_1: ; %Flow140; CHECK-NEXT: ; in Loop: Header=BB7_2 Depth=1141; CHECK-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s2142; CHECK-NEXT: s_mov_b32 s2, -1143; CHECK-NEXT: s_cbranch_vccz .LBB7_4144; CHECK-NEXT: .LBB7_2: ; %while145; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1146; CHECK-NEXT: s_and_b32 vcc_lo, exec_lo, s2147; CHECK-NEXT: s_mov_b32 s2, -1148; CHECK-NEXT: s_cbranch_vccnz .LBB7_1149; CHECK-NEXT: ; %bb.3: ; %if150; CHECK-NEXT: ; in Loop: Header=BB7_2 Depth=1151; CHECK-NEXT: s_mov_b32 s2, 0152; CHECK-NEXT: s_waitcnt lgkmcnt(0)153; CHECK-NEXT: global_store_b32 v0, v1, s[0:1]154; CHECK-NEXT: s_branch .LBB7_1155; CHECK-NEXT: .LBB7_4: ; %exit156; CHECK-NEXT: s_endpgm157entry:158 br label %while159 160while:161 %done = phi i1 [ 0, %entry ], [ 1, %if ]162 %not_done = xor i1 %done, true163 %ballot = tail call i64 @llvm.amdgcn.ballot.i64(i1 %not_done)164 %is_done = icmp eq i64 %ballot, 0 ; in this case is_done = !not_done165 br i1 %is_done, label %exit, label %if166 167if:168 store i32 5, ptr addrspace(1) %out169 br label %while170 171exit:172 ret void173}174