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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck --check-prefix=GCN %s3; RUN: llc -mtriple amdgcn-amd-amdhsa -mcpu=gfx900 -early-live-intervals < %s | FileCheck --check-prefix=GCN %s4 5define weak_odr amdgpu_kernel void @test_mul24_knownbits_kernel(ptr addrspace(1) %p) #4 {6; GCN-LABEL: test_mul24_knownbits_kernel:7; GCN: ; %bb.0: ; %entry8; GCN-NEXT: v_and_b32_e32 v0, 3, v09; GCN-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x010; GCN-NEXT: v_mul_i32_i24_e32 v0, -5, v011; GCN-NEXT: v_and_b32_e32 v0, 0xffffffe0, v012; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v013; GCN-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]14; GCN-NEXT: s_waitcnt lgkmcnt(0)15; GCN-NEXT: v_mov_b32_e32 v2, s116; GCN-NEXT: v_add_co_u32_e32 v0, vcc, s0, v017; GCN-NEXT: v_addc_co_u32_e32 v1, vcc, v2, v1, vcc18; GCN-NEXT: v_mov_b32_e32 v2, 019; GCN-NEXT: global_store_dword v[0:1], v2, off20; GCN-NEXT: s_endpgm21entry:22 %0 = tail call i32 @llvm.amdgcn.workitem.id.x() #28, !range !423 %tid = and i32 %0, 324 %1 = mul nsw i32 %tid, -525 %v1 = and i32 %1, -3226 %v2 = sext i32 %v1 to i6427 %v3 = getelementptr inbounds float, ptr addrspace(1) %p, i64 %v228 store float 0.000, ptr addrspace(1) %v3, align 429 ret void30}31 32define i32 @f(i32 %x, i32 %y) {33; GCN-LABEL: f:34; GCN: ; %bb.0:35; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)36; GCN-NEXT: v_or_b32_e32 v0, 0xffff80, v037; GCN-NEXT: v_or_b32_e32 v1, 0xffff80, v138; GCN-NEXT: v_mul_i32_i24_e32 v0, v0, v139; GCN-NEXT: v_lshrrev_b32_e32 v0, 14, v040; GCN-NEXT: s_setpc_b64 s[30:31]41 %xx = or i32 %x, -128 ; 0xffffff8042 %yy = or i32 %y, -128 ; 0xffffff8043 %r = mul i32 %xx, %yy44 %rr = lshr i32 %r, 1445 ret i32 %rr46}47 48; Function Attrs: nounwind readnone speculatable49declare i32 @llvm.amdgcn.workitem.id.x() #2050 51!4 = !{i32 0, i32 1024}52