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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 22; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-simplifylib,instcombine -amdgpu-prelink %s | FileCheck %s3 4declare float @_Z4pownfi(float, i32)5declare <2 x float> @_Z4pownDv2_fDv2_i(<2 x float>, <2 x i32>)6declare <3 x float> @_Z4pownDv3_fDv3_i(<3 x float>, <3 x i32>)7declare <4 x float> @_Z4pownDv4_fDv4_i(<4 x float>, <4 x i32>)8declare <8 x float> @_Z4pownDv8_fDv8_i(<8 x float>, <8 x i32>)9declare <16 x float> @_Z4pownDv16_fDv16_i(<16 x float>, <16 x i32>)10declare double @_Z4powndi(double, i32)11declare <2 x double> @_Z4pownDv2_dDv2_i(<2 x double>, <2 x i32>)12declare <3 x double> @_Z4pownDv3_dDv3_i(<3 x double>, <3 x i32>)13declare <4 x double> @_Z4pownDv4_dDv4_i(<4 x double>, <4 x i32>)14declare <8 x double> @_Z4pownDv8_dDv8_i(<8 x double>, <8 x i32>)15declare <16 x double> @_Z4pownDv16_dDv16_i(<16 x double>, <16 x i32>)16declare half @_Z4pownDhi(half, i32)17declare <2 x half> @_Z4pownDv2_DhDv2_i(<2 x half>, <2 x i32>)18declare <3 x half> @_Z4pownDv3_DhDv3_i(<3 x half>, <3 x i32>)19declare <4 x half> @_Z4pownDv4_DhDv4_i(<4 x half>, <4 x i32>)20declare <8 x half> @_Z4pownDv8_DhDv8_i(<8 x half>, <8 x i32>)21declare <16 x half> @_Z4pownDv16_DhDv16_i(<16 x half>, <16 x i32>)22 23define float @test_pown_f32(float %x, i32 %y) {24; CHECK-LABEL: define float @test_pown_f3225; CHECK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) {26; CHECK-NEXT: entry:27; CHECK-NEXT: [[CALL:%.*]] = tail call float @_Z4pownfi(float [[X]], i32 [[Y]])28; CHECK-NEXT: ret float [[CALL]]29;30entry:31 %call = tail call float @_Z4pownfi(float %x, i32 %y)32 ret float %call33}34 35define <2 x float> @test_pown_v2f32(<2 x float> %x, <2 x i32> %y) {36; CHECK-LABEL: define <2 x float> @test_pown_v2f3237; CHECK-SAME: (<2 x float> [[X:%.*]], <2 x i32> [[Y:%.*]]) {38; CHECK-NEXT: entry:39; CHECK-NEXT: [[CALL:%.*]] = tail call <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> [[X]], <2 x i32> [[Y]])40; CHECK-NEXT: ret <2 x float> [[CALL]]41;42entry:43 %call = tail call <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> %x, <2 x i32> %y)44 ret <2 x float> %call45}46 47define <3 x float> @test_pown_v3f32(<3 x float> %x, <3 x i32> %y) {48; CHECK-LABEL: define <3 x float> @test_pown_v3f3249; CHECK-SAME: (<3 x float> [[X:%.*]], <3 x i32> [[Y:%.*]]) {50; CHECK-NEXT: entry:51; CHECK-NEXT: [[CALL:%.*]] = tail call <3 x float> @_Z4pownDv3_fDv3_i(<3 x float> [[X]], <3 x i32> [[Y]])52; CHECK-NEXT: ret <3 x float> [[CALL]]53;54entry:55 %call = tail call <3 x float> @_Z4pownDv3_fDv3_i(<3 x float> %x, <3 x i32> %y)56 ret <3 x float> %call57}58 59define <4 x float> @test_pown_v4f32(<4 x float> %x, <4 x i32> %y) {60; CHECK-LABEL: define <4 x float> @test_pown_v4f3261; CHECK-SAME: (<4 x float> [[X:%.*]], <4 x i32> [[Y:%.*]]) {62; CHECK-NEXT: entry:63; CHECK-NEXT: [[CALL:%.*]] = tail call <4 x float> @_Z4pownDv4_fDv4_i(<4 x float> [[X]], <4 x i32> [[Y]])64; CHECK-NEXT: ret <4 x float> [[CALL]]65;66entry:67 %call = tail call <4 x float> @_Z4pownDv4_fDv4_i(<4 x float> %x, <4 x i32> %y)68 ret <4 x float> %call69}70 71define <8 x float> @test_pown_v8f32(<8 x float> %x, <8 x i32> %y) {72; CHECK-LABEL: define <8 x float> @test_pown_v8f3273; CHECK-SAME: (<8 x float> [[X:%.*]], <8 x i32> [[Y:%.*]]) {74; CHECK-NEXT: entry:75; CHECK-NEXT: [[CALL:%.*]] = tail call <8 x float> @_Z4pownDv8_fDv8_i(<8 x float> [[X]], <8 x i32> [[Y]])76; CHECK-NEXT: ret <8 x float> [[CALL]]77;78entry:79 %call = tail call <8 x float> @_Z4pownDv8_fDv8_i(<8 x float> %x, <8 x i32> %y)80 ret <8 x float> %call81}82 83define <16 x float> @test_pown_v16f32(<16 x float> %x, <16 x i32> %y) {84; CHECK-LABEL: define <16 x float> @test_pown_v16f3285; CHECK-SAME: (<16 x float> [[X:%.*]], <16 x i32> [[Y:%.*]]) {86; CHECK-NEXT: entry:87; CHECK-NEXT: [[CALL:%.*]] = tail call <16 x float> @_Z4pownDv16_fDv16_i(<16 x float> [[X]], <16 x i32> [[Y]])88; CHECK-NEXT: ret <16 x float> [[CALL]]89;90entry:91 %call = tail call <16 x float> @_Z4pownDv16_fDv16_i(<16 x float> %x, <16 x i32> %y)92 ret <16 x float> %call93}94 95define double @test_pown_f64(double %x, i32 %y) {96; CHECK-LABEL: define double @test_pown_f6497; CHECK-SAME: (double [[X:%.*]], i32 [[Y:%.*]]) {98; CHECK-NEXT: entry:99; CHECK-NEXT: [[CALL:%.*]] = tail call double @_Z4powndi(double [[X]], i32 [[Y]])100; CHECK-NEXT: ret double [[CALL]]101;102entry:103 %call = tail call double @_Z4powndi(double %x, i32 %y)104 ret double %call105}106 107define <2 x double> @test_pown_v2f64(<2 x double> %x, <2 x i32> %y) {108; CHECK-LABEL: define <2 x double> @test_pown_v2f64109; CHECK-SAME: (<2 x double> [[X:%.*]], <2 x i32> [[Y:%.*]]) {110; CHECK-NEXT: entry:111; CHECK-NEXT: [[CALL:%.*]] = tail call <2 x double> @_Z4pownDv2_dDv2_i(<2 x double> [[X]], <2 x i32> [[Y]])112; CHECK-NEXT: ret <2 x double> [[CALL]]113;114entry:115 %call = tail call <2 x double> @_Z4pownDv2_dDv2_i(<2 x double> %x, <2 x i32> %y)116 ret <2 x double> %call117}118 119define <3 x double> @test_pown_v3f64(<3 x double> %x, <3 x i32> %y) {120; CHECK-LABEL: define <3 x double> @test_pown_v3f64121; CHECK-SAME: (<3 x double> [[X:%.*]], <3 x i32> [[Y:%.*]]) {122; CHECK-NEXT: entry:123; CHECK-NEXT: [[CALL:%.*]] = tail call <3 x double> @_Z4pownDv3_dDv3_i(<3 x double> [[X]], <3 x i32> [[Y]])124; CHECK-NEXT: ret <3 x double> [[CALL]]125;126entry:127 %call = tail call <3 x double> @_Z4pownDv3_dDv3_i(<3 x double> %x, <3 x i32> %y)128 ret <3 x double> %call129}130 131define <4 x double> @test_pown_v4f64(<4 x double> %x, <4 x i32> %y) {132; CHECK-LABEL: define <4 x double> @test_pown_v4f64133; CHECK-SAME: (<4 x double> [[X:%.*]], <4 x i32> [[Y:%.*]]) {134; CHECK-NEXT: entry:135; CHECK-NEXT: [[CALL:%.*]] = tail call <4 x double> @_Z4pownDv4_dDv4_i(<4 x double> [[X]], <4 x i32> [[Y]])136; CHECK-NEXT: ret <4 x double> [[CALL]]137;138entry:139 %call = tail call <4 x double> @_Z4pownDv4_dDv4_i(<4 x double> %x, <4 x i32> %y)140 ret <4 x double> %call141}142 143define <8 x double> @test_pown_v8f64(<8 x double> %x, <8 x i32> %y) {144; CHECK-LABEL: define <8 x double> @test_pown_v8f64145; CHECK-SAME: (<8 x double> [[X:%.*]], <8 x i32> [[Y:%.*]]) {146; CHECK-NEXT: entry:147; CHECK-NEXT: [[CALL:%.*]] = tail call <8 x double> @_Z4pownDv8_dDv8_i(<8 x double> [[X]], <8 x i32> [[Y]])148; CHECK-NEXT: ret <8 x double> [[CALL]]149;150entry:151 %call = tail call <8 x double> @_Z4pownDv8_dDv8_i(<8 x double> %x, <8 x i32> %y)152 ret <8 x double> %call153}154 155define <16 x double> @test_pown_v16f64(<16 x double> %x, <16 x i32> %y) {156; CHECK-LABEL: define <16 x double> @test_pown_v16f64157; CHECK-SAME: (<16 x double> [[X:%.*]], <16 x i32> [[Y:%.*]]) {158; CHECK-NEXT: entry:159; CHECK-NEXT: [[CALL:%.*]] = tail call <16 x double> @_Z4pownDv16_dDv16_i(<16 x double> [[X]], <16 x i32> [[Y]])160; CHECK-NEXT: ret <16 x double> [[CALL]]161;162entry:163 %call = tail call <16 x double> @_Z4pownDv16_dDv16_i(<16 x double> %x, <16 x i32> %y)164 ret <16 x double> %call165}166 167define half @test_pown_f16(half %x, i32 %y) {168; CHECK-LABEL: define half @test_pown_f16169; CHECK-SAME: (half [[X:%.*]], i32 [[Y:%.*]]) {170; CHECK-NEXT: entry:171; CHECK-NEXT: [[CALL:%.*]] = tail call half @_Z4pownDhi(half [[X]], i32 [[Y]])172; CHECK-NEXT: ret half [[CALL]]173;174entry:175 %call = tail call half @_Z4pownDhi(half %x, i32 %y)176 ret half %call177}178 179define <2 x half> @test_pown_v2f16(<2 x half> %x, <2 x i32> %y) {180; CHECK-LABEL: define <2 x half> @test_pown_v2f16181; CHECK-SAME: (<2 x half> [[X:%.*]], <2 x i32> [[Y:%.*]]) {182; CHECK-NEXT: entry:183; CHECK-NEXT: [[CALL:%.*]] = tail call <2 x half> @_Z4pownDv2_DhDv2_i(<2 x half> [[X]], <2 x i32> [[Y]])184; CHECK-NEXT: ret <2 x half> [[CALL]]185;186entry:187 %call = tail call <2 x half> @_Z4pownDv2_DhDv2_i(<2 x half> %x, <2 x i32> %y)188 ret <2 x half> %call189}190 191define <3 x half> @test_pown_v3f16(<3 x half> %x, <3 x i32> %y) {192; CHECK-LABEL: define <3 x half> @test_pown_v3f16193; CHECK-SAME: (<3 x half> [[X:%.*]], <3 x i32> [[Y:%.*]]) {194; CHECK-NEXT: entry:195; CHECK-NEXT: [[CALL:%.*]] = tail call <3 x half> @_Z4pownDv3_DhDv3_i(<3 x half> [[X]], <3 x i32> [[Y]])196; CHECK-NEXT: ret <3 x half> [[CALL]]197;198entry:199 %call = tail call <3 x half> @_Z4pownDv3_DhDv3_i(<3 x half> %x, <3 x i32> %y)200 ret <3 x half> %call201}202 203define <4 x half> @test_pown_v4f16(<4 x half> %x, <4 x i32> %y) {204; CHECK-LABEL: define <4 x half> @test_pown_v4f16205; CHECK-SAME: (<4 x half> [[X:%.*]], <4 x i32> [[Y:%.*]]) {206; CHECK-NEXT: entry:207; CHECK-NEXT: [[CALL:%.*]] = tail call <4 x half> @_Z4pownDv4_DhDv4_i(<4 x half> [[X]], <4 x i32> [[Y]])208; CHECK-NEXT: ret <4 x half> [[CALL]]209;210entry:211 %call = tail call <4 x half> @_Z4pownDv4_DhDv4_i(<4 x half> %x, <4 x i32> %y)212 ret <4 x half> %call213}214 215define <8 x half> @test_pown_v8f16(<8 x half> %x, <8 x i32> %y) {216; CHECK-LABEL: define <8 x half> @test_pown_v8f16217; CHECK-SAME: (<8 x half> [[X:%.*]], <8 x i32> [[Y:%.*]]) {218; CHECK-NEXT: entry:219; CHECK-NEXT: [[CALL:%.*]] = tail call <8 x half> @_Z4pownDv8_DhDv8_i(<8 x half> [[X]], <8 x i32> [[Y]])220; CHECK-NEXT: ret <8 x half> [[CALL]]221;222entry:223 %call = tail call <8 x half> @_Z4pownDv8_DhDv8_i(<8 x half> %x, <8 x i32> %y)224 ret <8 x half> %call225}226 227define <16 x half> @test_pown_v16f16(<16 x half> %x, <16 x i32> %y) {228; CHECK-LABEL: define <16 x half> @test_pown_v16f16229; CHECK-SAME: (<16 x half> [[X:%.*]], <16 x i32> [[Y:%.*]]) {230; CHECK-NEXT: entry:231; CHECK-NEXT: [[CALL:%.*]] = tail call <16 x half> @_Z4pownDv16_DhDv16_i(<16 x half> [[X]], <16 x i32> [[Y]])232; CHECK-NEXT: ret <16 x half> [[CALL]]233;234entry:235 %call = tail call <16 x half> @_Z4pownDv16_DhDv16_i(<16 x half> %x, <16 x i32> %y)236 ret <16 x half> %call237}238 239define float @test_pown_f32__y_0(float %x) {240; CHECK-LABEL: define float @test_pown_f32__y_0241; CHECK-SAME: (float [[X:%.*]]) {242; CHECK-NEXT: entry:243; CHECK-NEXT: ret float 1.000000e+00244;245entry:246 %call = tail call float @_Z4pownfi(float %x, i32 0)247 ret float %call248}249 250define float @test_pown_f32__y_poison(float %x) {251; CHECK-LABEL: define float @test_pown_f32__y_poison252; CHECK-SAME: (float [[X:%.*]]) {253; CHECK-NEXT: entry:254; CHECK-NEXT: [[CALL:%.*]] = tail call float @_Z4pownfi(float [[X]], i32 poison)255; CHECK-NEXT: ret float [[CALL]]256;257entry:258 %call = tail call float @_Z4pownfi(float %x, i32 poison)259 ret float %call260}261 262define <2 x float> @test_pown_v2f32__y_poison(<2 x float> %x) {263; CHECK-LABEL: define <2 x float> @test_pown_v2f32__y_poison264; CHECK-SAME: (<2 x float> [[X:%.*]]) {265; CHECK-NEXT: entry:266; CHECK-NEXT: [[CALL:%.*]] = tail call <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> [[X]], <2 x i32> poison)267; CHECK-NEXT: ret <2 x float> [[CALL]]268;269entry:270 %call = tail call <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> %x, <2 x i32> poison)271 ret <2 x float> %call272}273 274define <2 x float> @test_pown_v2f32__y_0(<2 x float> %x) {275; CHECK-LABEL: define <2 x float> @test_pown_v2f32__y_0276; CHECK-SAME: (<2 x float> [[X:%.*]]) {277; CHECK-NEXT: entry:278; CHECK-NEXT: ret <2 x float> splat (float 1.000000e+00)279;280entry:281 %call = tail call <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> %x, <2 x i32> zeroinitializer)282 ret <2 x float> %call283}284 285define <2 x float> @test_pown_v2f32__y_0_undef(<2 x float> %x) {286; CHECK-LABEL: define <2 x float> @test_pown_v2f32__y_0_undef287; CHECK-SAME: (<2 x float> [[X:%.*]]) {288; CHECK-NEXT: entry:289; CHECK-NEXT: ret <2 x float> splat (float 1.000000e+00)290;291entry:292 %call = tail call <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> %x, <2 x i32> <i32 0, i32 poison>)293 ret <2 x float> %call294}295 296define <3 x float> @test_pown_v3f32__y_0(<3 x float> %x) {297; CHECK-LABEL: define <3 x float> @test_pown_v3f32__y_0298; CHECK-SAME: (<3 x float> [[X:%.*]]) {299; CHECK-NEXT: entry:300; CHECK-NEXT: ret <3 x float> splat (float 1.000000e+00)301;302entry:303 %call = tail call <3 x float> @_Z4pownDv3_fDv3_i(<3 x float> %x, <3 x i32> zeroinitializer)304 ret <3 x float> %call305}306 307define <4 x float> @test_pown_v4f32__y_0(<4 x float> %x) {308; CHECK-LABEL: define <4 x float> @test_pown_v4f32__y_0309; CHECK-SAME: (<4 x float> [[X:%.*]]) {310; CHECK-NEXT: entry:311; CHECK-NEXT: ret <4 x float> splat (float 1.000000e+00)312;313entry:314 %call = tail call <4 x float> @_Z4pownDv4_fDv4_i(<4 x float> %x, <4 x i32> zeroinitializer)315 ret <4 x float> %call316}317 318define <8 x float> @test_pown_v8f32__y_0(<8 x float> %x) {319; CHECK-LABEL: define <8 x float> @test_pown_v8f32__y_0320; CHECK-SAME: (<8 x float> [[X:%.*]]) {321; CHECK-NEXT: entry:322; CHECK-NEXT: ret <8 x float> splat (float 1.000000e+00)323;324entry:325 %call = tail call <8 x float> @_Z4pownDv8_fDv8_i(<8 x float> %x, <8 x i32> zeroinitializer)326 ret <8 x float> %call327}328 329define <16 x float> @test_pown_v16f32__y_0(<16 x float> %x) {330; CHECK-LABEL: define <16 x float> @test_pown_v16f32__y_0331; CHECK-SAME: (<16 x float> [[X:%.*]]) {332; CHECK-NEXT: entry:333; CHECK-NEXT: ret <16 x float> splat (float 1.000000e+00)334;335entry:336 %call = tail call <16 x float> @_Z4pownDv16_fDv16_i(<16 x float> %x, <16 x i32> zeroinitializer)337 ret <16 x float> %call338}339 340define float @test_pown_f32__y_1(float %x) {341; CHECK-LABEL: define float @test_pown_f32__y_1342; CHECK-SAME: (float [[X:%.*]]) {343; CHECK-NEXT: entry:344; CHECK-NEXT: ret float [[X]]345;346entry:347 %call = tail call float @_Z4pownfi(float %x, i32 1)348 ret float %call349}350 351define <2 x float> @test_pown_v2f32__y_1(<2 x float> %x) {352; CHECK-LABEL: define <2 x float> @test_pown_v2f32__y_1353; CHECK-SAME: (<2 x float> [[X:%.*]]) {354; CHECK-NEXT: entry:355; CHECK-NEXT: ret <2 x float> [[X]]356;357entry:358 %call = tail call <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> %x, <2 x i32> <i32 1, i32 1>)359 ret <2 x float> %call360}361 362define <2 x float> @test_pown_v2f32__y_1_undef(<2 x float> %x) {363; CHECK-LABEL: define <2 x float> @test_pown_v2f32__y_1_undef364; CHECK-SAME: (<2 x float> [[X:%.*]]) {365; CHECK-NEXT: entry:366; CHECK-NEXT: ret <2 x float> [[X]]367;368entry:369 %call = tail call <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> %x, <2 x i32> <i32 1, i32 poison>)370 ret <2 x float> %call371}372 373define <3 x float> @test_pown_v3f32__y_1(<3 x float> %x) {374; CHECK-LABEL: define <3 x float> @test_pown_v3f32__y_1375; CHECK-SAME: (<3 x float> [[X:%.*]]) {376; CHECK-NEXT: entry:377; CHECK-NEXT: ret <3 x float> [[X]]378;379entry:380 %call = tail call <3 x float> @_Z4pownDv3_fDv3_i(<3 x float> %x, <3 x i32> <i32 1, i32 1, i32 1>)381 ret <3 x float> %call382}383 384define <3 x float> @test_pown_v3f32__y_1_undef(<3 x float> %x) {385; CHECK-LABEL: define <3 x float> @test_pown_v3f32__y_1_undef386; CHECK-SAME: (<3 x float> [[X:%.*]]) {387; CHECK-NEXT: entry:388; CHECK-NEXT: ret <3 x float> [[X]]389;390entry:391 %call = tail call <3 x float> @_Z4pownDv3_fDv3_i(<3 x float> %x, <3 x i32> <i32 1, i32 1, i32 poison>)392 ret <3 x float> %call393}394 395define <4 x float> @test_pown_v4f32__y_1(<4 x float> %x) {396; CHECK-LABEL: define <4 x float> @test_pown_v4f32__y_1397; CHECK-SAME: (<4 x float> [[X:%.*]]) {398; CHECK-NEXT: entry:399; CHECK-NEXT: ret <4 x float> [[X]]400;401entry:402 %call = tail call <4 x float> @_Z4pownDv4_fDv4_i(<4 x float> %x, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)403 ret <4 x float> %call404}405 406define <8 x float> @test_pown_v8f32__y_1(<8 x float> %x) {407; CHECK-LABEL: define <8 x float> @test_pown_v8f32__y_1408; CHECK-SAME: (<8 x float> [[X:%.*]]) {409; CHECK-NEXT: entry:410; CHECK-NEXT: ret <8 x float> [[X]]411;412entry:413 %call = tail call <8 x float> @_Z4pownDv8_fDv8_i(<8 x float> %x, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>)414 ret <8 x float> %call415}416 417define <16 x float> @test_pown_v16f32__y_1(<16 x float> %x) {418; CHECK-LABEL: define <16 x float> @test_pown_v16f32__y_1419; CHECK-SAME: (<16 x float> [[X:%.*]]) {420; CHECK-NEXT: entry:421; CHECK-NEXT: ret <16 x float> [[X]]422;423entry:424 %call = tail call <16 x float> @_Z4pownDv16_fDv16_i(<16 x float> %x, <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>)425 ret <16 x float> %call426}427 428define float @test_pown_f32__y_2(float %x) {429; CHECK-LABEL: define float @test_pown_f32__y_2430; CHECK-SAME: (float [[X:%.*]]) {431; CHECK-NEXT: entry:432; CHECK-NEXT: [[__POW2:%.*]] = fmul float [[X]], [[X]]433; CHECK-NEXT: ret float [[__POW2]]434;435entry:436 %call = tail call float @_Z4pownfi(float %x, i32 2)437 ret float %call438}439 440define <2 x float> @test_pown_v2f32__y_2(<2 x float> %x) {441; CHECK-LABEL: define <2 x float> @test_pown_v2f32__y_2442; CHECK-SAME: (<2 x float> [[X:%.*]]) {443; CHECK-NEXT: entry:444; CHECK-NEXT: [[__POW2:%.*]] = fmul <2 x float> [[X]], [[X]]445; CHECK-NEXT: ret <2 x float> [[__POW2]]446;447entry:448 %call = tail call <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> %x, <2 x i32> <i32 2, i32 2>)449 ret <2 x float> %call450}451 452define <3 x float> @test_pown_v3f32__y_2(<3 x float> %x) {453; CHECK-LABEL: define <3 x float> @test_pown_v3f32__y_2454; CHECK-SAME: (<3 x float> [[X:%.*]]) {455; CHECK-NEXT: entry:456; CHECK-NEXT: [[__POW2:%.*]] = fmul <3 x float> [[X]], [[X]]457; CHECK-NEXT: ret <3 x float> [[__POW2]]458;459entry:460 %call = tail call <3 x float> @_Z4pownDv3_fDv3_i(<3 x float> %x, <3 x i32> <i32 2, i32 2, i32 2>)461 ret <3 x float> %call462}463 464define <3 x float> @test_pown_v3f32__y_2_undef(<3 x float> %x) {465; CHECK-LABEL: define <3 x float> @test_pown_v3f32__y_2_undef466; CHECK-SAME: (<3 x float> [[X:%.*]]) {467; CHECK-NEXT: entry:468; CHECK-NEXT: [[__POW2:%.*]] = fmul <3 x float> [[X]], [[X]]469; CHECK-NEXT: ret <3 x float> [[__POW2]]470;471entry:472 %call = tail call <3 x float> @_Z4pownDv3_fDv3_i(<3 x float> %x, <3 x i32> <i32 2, i32 poison, i32 2>)473 ret <3 x float> %call474}475 476define <4 x float> @test_pown_v4f32__y_2(<4 x float> %x) {477; CHECK-LABEL: define <4 x float> @test_pown_v4f32__y_2478; CHECK-SAME: (<4 x float> [[X:%.*]]) {479; CHECK-NEXT: entry:480; CHECK-NEXT: [[__POW2:%.*]] = fmul <4 x float> [[X]], [[X]]481; CHECK-NEXT: ret <4 x float> [[__POW2]]482;483entry:484 %call = tail call <4 x float> @_Z4pownDv4_fDv4_i(<4 x float> %x, <4 x i32> <i32 2, i32 2, i32 2, i32 2>)485 ret <4 x float> %call486}487 488define <8 x float> @test_pown_v8f32__y_2(<8 x float> %x) {489; CHECK-LABEL: define <8 x float> @test_pown_v8f32__y_2490; CHECK-SAME: (<8 x float> [[X:%.*]]) {491; CHECK-NEXT: entry:492; CHECK-NEXT: [[__POW2:%.*]] = fmul <8 x float> [[X]], [[X]]493; CHECK-NEXT: ret <8 x float> [[__POW2]]494;495entry:496 %call = tail call <8 x float> @_Z4pownDv8_fDv8_i(<8 x float> %x, <8 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>)497 ret <8 x float> %call498}499 500define <16 x float> @test_pown_v26f32__y_2(<16 x float> %x) {501; CHECK-LABEL: define <16 x float> @test_pown_v26f32__y_2502; CHECK-SAME: (<16 x float> [[X:%.*]]) {503; CHECK-NEXT: entry:504; CHECK-NEXT: [[__POW2:%.*]] = fmul <16 x float> [[X]], [[X]]505; CHECK-NEXT: ret <16 x float> [[__POW2]]506;507entry:508 %call = tail call <16 x float> @_Z4pownDv16_fDv16_i(<16 x float> %x, <16 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>)509 ret <16 x float> %call510}511 512define float @test_pown_f32__y_neg1(float %x) {513; CHECK-LABEL: define float @test_pown_f32__y_neg1514; CHECK-SAME: (float [[X:%.*]]) {515; CHECK-NEXT: entry:516; CHECK-NEXT: [[__POWRECIP:%.*]] = fdiv float 1.000000e+00, [[X]]517; CHECK-NEXT: ret float [[__POWRECIP]]518;519entry:520 %call = tail call float @_Z4pownfi(float %x, i32 -1)521 ret float %call522}523 524define <2 x float> @test_pown_v2f32__y_neg1(<2 x float> %x) {525; CHECK-LABEL: define <2 x float> @test_pown_v2f32__y_neg1526; CHECK-SAME: (<2 x float> [[X:%.*]]) {527; CHECK-NEXT: entry:528; CHECK-NEXT: [[__POWRECIP:%.*]] = fdiv <2 x float> splat (float 1.000000e+00), [[X]]529; CHECK-NEXT: ret <2 x float> [[__POWRECIP]]530;531entry:532 %call = tail call <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> %x, <2 x i32> <i32 -1, i32 -1>)533 ret <2 x float> %call534}535 536define <3 x float> @test_pown_v3f32__y_neg1(<3 x float> %x) {537; CHECK-LABEL: define <3 x float> @test_pown_v3f32__y_neg1538; CHECK-SAME: (<3 x float> [[X:%.*]]) {539; CHECK-NEXT: entry:540; CHECK-NEXT: [[__POWRECIP:%.*]] = fdiv <3 x float> splat (float 1.000000e+00), [[X]]541; CHECK-NEXT: ret <3 x float> [[__POWRECIP]]542;543entry:544 %call = tail call <3 x float> @_Z4pownDv3_fDv3_i(<3 x float> %x, <3 x i32> <i32 -1, i32 -1, i32 -1>)545 ret <3 x float> %call546}547 548define <3 x float> @test_pown_v3f32__y_neg1_undef(<3 x float> %x) {549; CHECK-LABEL: define <3 x float> @test_pown_v3f32__y_neg1_undef550; CHECK-SAME: (<3 x float> [[X:%.*]]) {551; CHECK-NEXT: entry:552; CHECK-NEXT: [[__POWRECIP:%.*]] = fdiv <3 x float> splat (float 1.000000e+00), [[X]]553; CHECK-NEXT: ret <3 x float> [[__POWRECIP]]554;555entry:556 %call = tail call <3 x float> @_Z4pownDv3_fDv3_i(<3 x float> %x, <3 x i32> <i32 -1, i32 -1, i32 poison>)557 ret <3 x float> %call558}559 560define <4 x float> @test_pown_v4f32__y_neg1(<4 x float> %x) {561; CHECK-LABEL: define <4 x float> @test_pown_v4f32__y_neg1562; CHECK-SAME: (<4 x float> [[X:%.*]]) {563; CHECK-NEXT: entry:564; CHECK-NEXT: [[__POWRECIP:%.*]] = fdiv <4 x float> splat (float 1.000000e+00), [[X]]565; CHECK-NEXT: ret <4 x float> [[__POWRECIP]]566;567entry:568 %call = tail call <4 x float> @_Z4pownDv4_fDv4_i(<4 x float> %x, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)569 ret <4 x float> %call570}571 572define <8 x float> @test_pown_v8f32__y_neg1(<8 x float> %x) {573; CHECK-LABEL: define <8 x float> @test_pown_v8f32__y_neg1574; CHECK-SAME: (<8 x float> [[X:%.*]]) {575; CHECK-NEXT: entry:576; CHECK-NEXT: [[__POWRECIP:%.*]] = fdiv <8 x float> splat (float 1.000000e+00), [[X]]577; CHECK-NEXT: ret <8 x float> [[__POWRECIP]]578;579entry:580 %call = tail call <8 x float> @_Z4pownDv8_fDv8_i(<8 x float> %x, <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>)581 ret <8 x float> %call582}583 584define <16 x float> @test_pown_v16f32__y_neg1(<16 x float> %x) {585; CHECK-LABEL: define <16 x float> @test_pown_v16f32__y_neg1586; CHECK-SAME: (<16 x float> [[X:%.*]]) {587; CHECK-NEXT: entry:588; CHECK-NEXT: [[__POWRECIP:%.*]] = fdiv <16 x float> splat (float 1.000000e+00), [[X]]589; CHECK-NEXT: ret <16 x float> [[__POWRECIP]]590;591entry:592 %call = tail call <16 x float> @_Z4pownDv16_fDv16_i(<16 x float> %x, <16 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>)593 ret <16 x float> %call594}595 596define float @test_pown_afn_f32(float %x, i32 %y) {597; CHECK-LABEL: define float @test_pown_afn_f32598; CHECK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) {599; CHECK-NEXT: entry:600; CHECK-NEXT: [[CALL:%.*]] = tail call afn float @_Z4pownfi(float [[X]], i32 [[Y]])601; CHECK-NEXT: ret float [[CALL]]602;603entry:604 %call = tail call afn float @_Z4pownfi(float %x, i32 %y)605 ret float %call606}607 608define <2 x float> @test_pown_afn_v2f32(<2 x float> %x, <2 x i32> %y) {609; CHECK-LABEL: define <2 x float> @test_pown_afn_v2f32610; CHECK-SAME: (<2 x float> [[X:%.*]], <2 x i32> [[Y:%.*]]) {611; CHECK-NEXT: entry:612; CHECK-NEXT: [[CALL:%.*]] = tail call afn <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> [[X]], <2 x i32> [[Y]])613; CHECK-NEXT: ret <2 x float> [[CALL]]614;615entry:616 %call = tail call afn <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> %x, <2 x i32> %y)617 ret <2 x float> %call618}619 620define double @test_pown_afn_f64(double %x, i32 %y) {621; CHECK-LABEL: define double @test_pown_afn_f64622; CHECK-SAME: (double [[X:%.*]], i32 [[Y:%.*]]) {623; CHECK-NEXT: entry:624; CHECK-NEXT: [[CALL:%.*]] = tail call afn double @_Z4powndi(double [[X]], i32 [[Y]])625; CHECK-NEXT: ret double [[CALL]]626;627entry:628 %call = tail call afn double @_Z4powndi(double %x, i32 %y)629 ret double %call630}631 632define <2 x double> @test_pown_afn_v2f64(<2 x double> %x, <2 x i32> %y) {633; CHECK-LABEL: define <2 x double> @test_pown_afn_v2f64634; CHECK-SAME: (<2 x double> [[X:%.*]], <2 x i32> [[Y:%.*]]) {635; CHECK-NEXT: entry:636; CHECK-NEXT: [[CALL:%.*]] = tail call afn <2 x double> @_Z4pownDv2_dDv2_i(<2 x double> [[X]], <2 x i32> [[Y]])637; CHECK-NEXT: ret <2 x double> [[CALL]]638;639entry:640 %call = tail call afn <2 x double> @_Z4pownDv2_dDv2_i(<2 x double> %x, <2 x i32> %y)641 ret <2 x double> %call642}643 644define half @test_pown_afn_f16(half %x, i32 %y) {645; CHECK-LABEL: define half @test_pown_afn_f16646; CHECK-SAME: (half [[X:%.*]], i32 [[Y:%.*]]) {647; CHECK-NEXT: entry:648; CHECK-NEXT: [[CALL:%.*]] = tail call afn half @_Z4pownDhi(half [[X]], i32 [[Y]])649; CHECK-NEXT: ret half [[CALL]]650;651entry:652 %call = tail call afn half @_Z4pownDhi(half %x, i32 %y)653 ret half %call654}655 656define <2 x half> @test_pown_afn_v2f16(<2 x half> %x, <2 x i32> %y) {657; CHECK-LABEL: define <2 x half> @test_pown_afn_v2f16658; CHECK-SAME: (<2 x half> [[X:%.*]], <2 x i32> [[Y:%.*]]) {659; CHECK-NEXT: entry:660; CHECK-NEXT: [[CALL:%.*]] = tail call afn <2 x half> @_Z4pownDv2_DhDv2_i(<2 x half> [[X]], <2 x i32> [[Y]])661; CHECK-NEXT: ret <2 x half> [[CALL]]662;663entry:664 %call = tail call afn <2 x half> @_Z4pownDv2_DhDv2_i(<2 x half> %x, <2 x i32> %y)665 ret <2 x half> %call666}667 668define float @test_pown_afn_nnan_ninf_f32(float %x, i32 %y) {669; CHECK-LABEL: define float @test_pown_afn_nnan_ninf_f32670; CHECK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) {671; CHECK-NEXT: entry:672; CHECK-NEXT: [[__FABS:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])673; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[__FABS]])674; CHECK-NEXT: [[POWNI2F:%.*]] = sitofp i32 [[Y]] to float675; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn float [[__LOG2]], [[POWNI2F]]676; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[__YLOGX]])677; CHECK-NEXT: [[__YEVEN:%.*]] = shl i32 [[Y]], 31678; CHECK-NEXT: [[TMP0:%.*]] = bitcast float [[X]] to i32679; CHECK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP0]]680; CHECK-NEXT: [[TMP1:%.*]] = bitcast float [[__EXP2]] to i32681; CHECK-NEXT: [[TMP2:%.*]] = or disjoint i32 [[__POW_SIGN]], [[TMP1]]682; CHECK-NEXT: [[TMP3:%.*]] = bitcast i32 [[TMP2]] to float683; CHECK-NEXT: ret float [[TMP3]]684;685entry:686 %call = tail call nnan ninf afn float @_Z4pownfi(float %x, i32 %y)687 ret float %call688}689 690define <2 x float> @test_pown_afn_nnan_ninf_v2f32(<2 x float> %x, <2 x i32> %y) {691; CHECK-LABEL: define <2 x float> @test_pown_afn_nnan_ninf_v2f32692; CHECK-SAME: (<2 x float> [[X:%.*]], <2 x i32> [[Y:%.*]]) {693; CHECK-NEXT: entry:694; CHECK-NEXT: [[__FABS:%.*]] = call nnan ninf afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])695; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn <2 x float> @llvm.log2.v2f32(<2 x float> [[__FABS]])696; CHECK-NEXT: [[POWNI2F:%.*]] = sitofp <2 x i32> [[Y]] to <2 x float>697; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn <2 x float> [[__LOG2]], [[POWNI2F]]698; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[__YLOGX]])699; CHECK-NEXT: [[__YEVEN:%.*]] = shl <2 x i32> [[Y]], splat (i32 31)700; CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[X]] to <2 x i32>701; CHECK-NEXT: [[__POW_SIGN:%.*]] = and <2 x i32> [[__YEVEN]], [[TMP0]]702; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x float> [[__EXP2]] to <2 x i32>703; CHECK-NEXT: [[TMP2:%.*]] = or disjoint <2 x i32> [[__POW_SIGN]], [[TMP1]]704; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to <2 x float>705; CHECK-NEXT: ret <2 x float> [[TMP3]]706;707entry:708 %call = tail call nnan ninf afn <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> %x, <2 x i32> %y)709 ret <2 x float> %call710}711 712define double @test_pown_afn_nnan_ninf_f64(double %x, i32 %y) {713; CHECK-LABEL: define double @test_pown_afn_nnan_ninf_f64714; CHECK-SAME: (double [[X:%.*]], i32 [[Y:%.*]]) {715; CHECK-NEXT: entry:716; CHECK-NEXT: [[__FABS:%.*]] = call nnan ninf afn double @llvm.fabs.f64(double [[X]])717; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn double @_Z4log2d(double [[__FABS]])718; CHECK-NEXT: [[POWNI2F:%.*]] = sitofp i32 [[Y]] to double719; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn double [[__LOG2]], [[POWNI2F]]720; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn double @_Z4exp2d(double [[__YLOGX]])721; CHECK-NEXT: [[__YTOU:%.*]] = zext i32 [[Y]] to i64722; CHECK-NEXT: [[__YEVEN:%.*]] = shl i64 [[__YTOU]], 63723; CHECK-NEXT: [[TMP0:%.*]] = bitcast double [[X]] to i64724; CHECK-NEXT: [[__POW_SIGN:%.*]] = and i64 [[__YEVEN]], [[TMP0]]725; CHECK-NEXT: [[TMP1:%.*]] = bitcast double [[__EXP2]] to i64726; CHECK-NEXT: [[TMP2:%.*]] = or i64 [[__POW_SIGN]], [[TMP1]]727; CHECK-NEXT: [[TMP3:%.*]] = bitcast i64 [[TMP2]] to double728; CHECK-NEXT: ret double [[TMP3]]729;730entry:731 %call = tail call nnan ninf afn double @_Z4powndi(double %x, i32 %y)732 ret double %call733}734 735define <2 x double> @test_pown_afn_nnan_ninf_v2f64(<2 x double> %x, <2 x i32> %y) {736; CHECK-LABEL: define <2 x double> @test_pown_afn_nnan_ninf_v2f64737; CHECK-SAME: (<2 x double> [[X:%.*]], <2 x i32> [[Y:%.*]]) {738; CHECK-NEXT: entry:739; CHECK-NEXT: [[__FABS:%.*]] = call nnan ninf afn <2 x double> @llvm.fabs.v2f64(<2 x double> [[X]])740; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn <2 x double> @_Z4log2Dv2_d(<2 x double> [[__FABS]])741; CHECK-NEXT: [[POWNI2F:%.*]] = sitofp <2 x i32> [[Y]] to <2 x double>742; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn <2 x double> [[__LOG2]], [[POWNI2F]]743; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn <2 x double> @_Z4exp2Dv2_d(<2 x double> [[__YLOGX]])744; CHECK-NEXT: [[__YTOU:%.*]] = zext <2 x i32> [[Y]] to <2 x i64>745; CHECK-NEXT: [[__YEVEN:%.*]] = shl <2 x i64> [[__YTOU]], splat (i64 63)746; CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x double> [[X]] to <2 x i64>747; CHECK-NEXT: [[__POW_SIGN:%.*]] = and <2 x i64> [[__YEVEN]], [[TMP0]]748; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x double> [[__EXP2]] to <2 x i64>749; CHECK-NEXT: [[TMP2:%.*]] = or <2 x i64> [[__POW_SIGN]], [[TMP1]]750; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP2]] to <2 x double>751; CHECK-NEXT: ret <2 x double> [[TMP3]]752;753entry:754 %call = tail call nnan ninf afn <2 x double> @_Z4pownDv2_dDv2_i(<2 x double> %x, <2 x i32> %y)755 ret <2 x double> %call756}757 758define half @test_pown_afn_nnan_ninf_f16(half %x, i32 %y) {759; CHECK-LABEL: define half @test_pown_afn_nnan_ninf_f16760; CHECK-SAME: (half [[X:%.*]], i32 [[Y:%.*]]) {761; CHECK-NEXT: entry:762; CHECK-NEXT: [[__FABS:%.*]] = call nnan ninf afn half @llvm.fabs.f16(half [[X]])763; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn half @llvm.log2.f16(half [[__FABS]])764; CHECK-NEXT: [[POWNI2F:%.*]] = sitofp i32 [[Y]] to half765; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn half [[__LOG2]], [[POWNI2F]]766; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn half @llvm.exp2.f16(half [[__YLOGX]])767; CHECK-NEXT: [[__YTOU:%.*]] = trunc i32 [[Y]] to i16768; CHECK-NEXT: [[__YEVEN:%.*]] = shl i16 [[__YTOU]], 15769; CHECK-NEXT: [[TMP0:%.*]] = bitcast half [[X]] to i16770; CHECK-NEXT: [[__POW_SIGN:%.*]] = and i16 [[__YEVEN]], [[TMP0]]771; CHECK-NEXT: [[TMP1:%.*]] = bitcast half [[__EXP2]] to i16772; CHECK-NEXT: [[TMP2:%.*]] = or disjoint i16 [[__POW_SIGN]], [[TMP1]]773; CHECK-NEXT: [[TMP3:%.*]] = bitcast i16 [[TMP2]] to half774; CHECK-NEXT: ret half [[TMP3]]775;776entry:777 %call = tail call nnan ninf afn half @_Z4pownDhi(half %x, i32 %y)778 ret half %call779}780 781define <2 x half> @test_pown_afn_nnan_ninf_v2f16(<2 x half> %x, <2 x i32> %y) {782; CHECK-LABEL: define <2 x half> @test_pown_afn_nnan_ninf_v2f16783; CHECK-SAME: (<2 x half> [[X:%.*]], <2 x i32> [[Y:%.*]]) {784; CHECK-NEXT: entry:785; CHECK-NEXT: [[__FABS:%.*]] = call nnan ninf afn <2 x half> @llvm.fabs.v2f16(<2 x half> [[X]])786; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn <2 x half> @llvm.log2.v2f16(<2 x half> [[__FABS]])787; CHECK-NEXT: [[POWNI2F:%.*]] = sitofp <2 x i32> [[Y]] to <2 x half>788; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn <2 x half> [[__LOG2]], [[POWNI2F]]789; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn <2 x half> @llvm.exp2.v2f16(<2 x half> [[__YLOGX]])790; CHECK-NEXT: [[__YTOU:%.*]] = trunc <2 x i32> [[Y]] to <2 x i16>791; CHECK-NEXT: [[__YEVEN:%.*]] = shl <2 x i16> [[__YTOU]], splat (i16 15)792; CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x half> [[X]] to <2 x i16>793; CHECK-NEXT: [[__POW_SIGN:%.*]] = and <2 x i16> [[__YEVEN]], [[TMP0]]794; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x half> [[__EXP2]] to <2 x i16>795; CHECK-NEXT: [[TMP2:%.*]] = or disjoint <2 x i16> [[__POW_SIGN]], [[TMP1]]796; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to <2 x half>797; CHECK-NEXT: ret <2 x half> [[TMP3]]798;799entry:800 %call = tail call nnan ninf afn <2 x half> @_Z4pownDv2_DhDv2_i(<2 x half> %x, <2 x i32> %y)801 ret <2 x half> %call802}803 804define float @test_pown_fast_f32_nobuiltin(float %x, i32 %y) {805; CHECK-LABEL: define float @test_pown_fast_f32_nobuiltin806; CHECK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) {807; CHECK-NEXT: entry:808; CHECK-NEXT: [[CALL:%.*]] = tail call fast float @_Z4pownfi(float [[X]], i32 [[Y]]) #[[ATTR4:[0-9]+]]809; CHECK-NEXT: ret float [[CALL]]810;811entry:812 %call = tail call fast float @_Z4pownfi(float %x, i32 %y) #0813 ret float %call814}815 816define float @test_pown_fast_f32_strictfp(float %x, i32 %y) #1 {817; CHECK-LABEL: define float @test_pown_fast_f32_strictfp818; CHECK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) #[[ATTR0:[0-9]+]] {819; CHECK-NEXT: entry:820; CHECK-NEXT: [[__FABS:%.*]] = call fast float @llvm.fabs.f32(float [[X]]) #[[ATTR0]]821; CHECK-NEXT: [[__LOG2:%.*]] = call fast float @llvm.log2.f32(float [[__FABS]]) #[[ATTR0]]822; CHECK-NEXT: [[POWNI2F:%.*]] = call fast float @llvm.experimental.constrained.sitofp.f32.i32(i32 [[Y]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR0]]823; CHECK-NEXT: [[__YLOGX:%.*]] = call fast float @llvm.experimental.constrained.fmul.f32(float [[POWNI2F]], float [[__LOG2]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR0]]824; CHECK-NEXT: [[__EXP2:%.*]] = call fast float @llvm.exp2.f32(float [[__YLOGX]]) #[[ATTR0]]825; CHECK-NEXT: [[__YEVEN:%.*]] = shl i32 [[Y]], 31826; CHECK-NEXT: [[TMP0:%.*]] = bitcast float [[X]] to i32827; CHECK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP0]]828; CHECK-NEXT: [[TMP1:%.*]] = bitcast float [[__EXP2]] to i32829; CHECK-NEXT: [[TMP2:%.*]] = or disjoint i32 [[__POW_SIGN]], [[TMP1]]830; CHECK-NEXT: [[TMP3:%.*]] = bitcast i32 [[TMP2]] to float831; CHECK-NEXT: ret float [[TMP3]]832;833entry:834 %call = tail call fast float @_Z4pownfi(float %x, i32 %y) #1835 ret float %call836}837 838define float @test_pown_fast_f32__y_poison(float %x) {839; CHECK-LABEL: define float @test_pown_fast_f32__y_poison840; CHECK-SAME: (float [[X:%.*]]) {841; CHECK-NEXT: ret float poison842;843 %call = tail call fast float @_Z4pownfi(float %x, i32 poison)844 ret float %call845}846 847define float @test_pown_afn_nnan_ninf_f32__y_3(float %x) {848; CHECK-LABEL: define float @test_pown_afn_nnan_ninf_f32__y_3849; CHECK-SAME: (float [[X:%.*]]) {850; CHECK-NEXT: [[__POWX2:%.*]] = fmul nnan ninf afn float [[X]], [[X]]851; CHECK-NEXT: [[__POWPROD:%.*]] = fmul nnan ninf afn float [[X]], [[__POWX2]]852; CHECK-NEXT: ret float [[__POWPROD]]853;854 %call = tail call nnan ninf afn float @_Z4pownfi(float %x, i32 3)855 ret float %call856}857 858define float @test_pown_afn_nnan_ninf_f32__y_neg3(float %x) {859; CHECK-LABEL: define float @test_pown_afn_nnan_ninf_f32__y_neg3860; CHECK-SAME: (float [[X:%.*]]) {861; CHECK-NEXT: [[__POWX2:%.*]] = fmul nnan ninf afn float [[X]], [[X]]862; CHECK-NEXT: [[__POWPROD:%.*]] = fmul nnan ninf afn float [[X]], [[__POWX2]]863; CHECK-NEXT: [[__1POWPROD:%.*]] = fdiv nnan ninf afn float 1.000000e+00, [[__POWPROD]]864; CHECK-NEXT: ret float [[__1POWPROD]]865;866 %call = tail call nnan ninf afn float @_Z4pownfi(float %x, i32 -3)867 ret float %call868}869 870define float @test_pown_afn_nnan_ninf_f32__y_4(float %x) {871; CHECK-LABEL: define float @test_pown_afn_nnan_ninf_f32__y_4872; CHECK-SAME: (float [[X:%.*]]) {873; CHECK-NEXT: [[__POWX2:%.*]] = fmul nnan ninf afn float [[X]], [[X]]874; CHECK-NEXT: [[__POWX21:%.*]] = fmul nnan ninf afn float [[__POWX2]], [[__POWX2]]875; CHECK-NEXT: ret float [[__POWX21]]876;877 %call = tail call nnan ninf afn float @_Z4pownfi(float %x, i32 4)878 ret float %call879}880 881define float @test_pown_afn_nnan_ninf_f32__y_neg4(float %x) {882; CHECK-LABEL: define float @test_pown_afn_nnan_ninf_f32__y_neg4883; CHECK-SAME: (float [[X:%.*]]) {884; CHECK-NEXT: [[__POWX2:%.*]] = fmul nnan ninf afn float [[X]], [[X]]885; CHECK-NEXT: [[__POWX21:%.*]] = fmul nnan ninf afn float [[__POWX2]], [[__POWX2]]886; CHECK-NEXT: [[__1POWPROD:%.*]] = fdiv nnan ninf afn float 1.000000e+00, [[__POWX21]]887; CHECK-NEXT: ret float [[__1POWPROD]]888;889 %call = tail call nnan ninf afn float @_Z4pownfi(float %x, i32 -4)890 ret float %call891}892 893define float @test_pown_afn_nnan_ninf_f32__y_5(float %x) {894; CHECK-LABEL: define float @test_pown_afn_nnan_ninf_f32__y_5895; CHECK-SAME: (float [[X:%.*]]) {896; CHECK-NEXT: [[__POWX2:%.*]] = fmul nnan ninf afn float [[X]], [[X]]897; CHECK-NEXT: [[__POWX21:%.*]] = fmul nnan ninf afn float [[__POWX2]], [[__POWX2]]898; CHECK-NEXT: [[__POWPROD:%.*]] = fmul nnan ninf afn float [[X]], [[__POWX21]]899; CHECK-NEXT: ret float [[__POWPROD]]900;901 %call = tail call nnan ninf afn float @_Z4pownfi(float %x, i32 5)902 ret float %call903}904 905define float @test_pown_afn_nnan_ninf_f32__y_neg5(float %x) {906; CHECK-LABEL: define float @test_pown_afn_nnan_ninf_f32__y_neg5907; CHECK-SAME: (float [[X:%.*]]) {908; CHECK-NEXT: [[__POWX2:%.*]] = fmul nnan ninf afn float [[X]], [[X]]909; CHECK-NEXT: [[__POWX21:%.*]] = fmul nnan ninf afn float [[__POWX2]], [[__POWX2]]910; CHECK-NEXT: [[__POWPROD:%.*]] = fmul nnan ninf afn float [[X]], [[__POWX21]]911; CHECK-NEXT: [[__1POWPROD:%.*]] = fdiv nnan ninf afn float 1.000000e+00, [[__POWPROD]]912; CHECK-NEXT: ret float [[__1POWPROD]]913;914 %call = tail call nnan ninf afn float @_Z4pownfi(float %x, i32 -5)915 ret float %call916}917 918define float @test_pown_afn_nnan_ninf_f32__y_7(float %x) {919; CHECK-LABEL: define float @test_pown_afn_nnan_ninf_f32__y_7920; CHECK-SAME: (float [[X:%.*]]) {921; CHECK-NEXT: [[__POWX2:%.*]] = fmul nnan ninf afn float [[X]], [[X]]922; CHECK-NEXT: [[__POWPROD:%.*]] = fmul nnan ninf afn float [[X]], [[__POWX2]]923; CHECK-NEXT: [[__POWX21:%.*]] = fmul nnan ninf afn float [[__POWX2]], [[__POWX2]]924; CHECK-NEXT: [[__POWPROD2:%.*]] = fmul nnan ninf afn float [[__POWPROD]], [[__POWX21]]925; CHECK-NEXT: ret float [[__POWPROD2]]926;927 %call = tail call nnan ninf afn float @_Z4pownfi(float %x, i32 7)928 ret float %call929}930 931define float @test_pown_afn_nnan_ninf_f32__y_neg7(float %x) {932; CHECK-LABEL: define float @test_pown_afn_nnan_ninf_f32__y_neg7933; CHECK-SAME: (float [[X:%.*]]) {934; CHECK-NEXT: [[__POWX2:%.*]] = fmul nnan ninf afn float [[X]], [[X]]935; CHECK-NEXT: [[__POWPROD:%.*]] = fmul nnan ninf afn float [[X]], [[__POWX2]]936; CHECK-NEXT: [[__POWX21:%.*]] = fmul nnan ninf afn float [[__POWX2]], [[__POWX2]]937; CHECK-NEXT: [[__POWPROD2:%.*]] = fmul nnan ninf afn float [[__POWPROD]], [[__POWX21]]938; CHECK-NEXT: [[__1POWPROD:%.*]] = fdiv nnan ninf afn float 1.000000e+00, [[__POWPROD2]]939; CHECK-NEXT: ret float [[__1POWPROD]]940;941 %call = tail call nnan ninf afn float @_Z4pownfi(float %x, i32 -7)942 ret float %call943}944 945define float @test_pown_afn_nnan_ninf_f32__y_8(float %x) {946; CHECK-LABEL: define float @test_pown_afn_nnan_ninf_f32__y_8947; CHECK-SAME: (float [[X:%.*]]) {948; CHECK-NEXT: [[__POWX2:%.*]] = fmul nnan ninf afn float [[X]], [[X]]949; CHECK-NEXT: [[__POWX21:%.*]] = fmul nnan ninf afn float [[__POWX2]], [[__POWX2]]950; CHECK-NEXT: [[__POWX22:%.*]] = fmul nnan ninf afn float [[__POWX21]], [[__POWX21]]951; CHECK-NEXT: ret float [[__POWX22]]952;953 %call = tail call nnan ninf afn float @_Z4pownfi(float %x, i32 8)954 ret float %call955}956 957define float @test_pown_afn_nnan_ninf_f32__y_neg8(float %x) {958; CHECK-LABEL: define float @test_pown_afn_nnan_ninf_f32__y_neg8959; CHECK-SAME: (float [[X:%.*]]) {960; CHECK-NEXT: [[__POWX2:%.*]] = fmul nnan ninf afn float [[X]], [[X]]961; CHECK-NEXT: [[__POWX21:%.*]] = fmul nnan ninf afn float [[__POWX2]], [[__POWX2]]962; CHECK-NEXT: [[__POWX22:%.*]] = fmul nnan ninf afn float [[__POWX21]], [[__POWX21]]963; CHECK-NEXT: [[__1POWPROD:%.*]] = fdiv nnan ninf afn float 1.000000e+00, [[__POWX22]]964; CHECK-NEXT: ret float [[__1POWPROD]]965;966 %call = tail call nnan ninf afn float @_Z4pownfi(float %x, i32 -8)967 ret float %call968}969 970define <2 x float> @test_pown_afn_nnan_ninf_v2f32__y_3(<2 x float> %x) {971; CHECK-LABEL: define <2 x float> @test_pown_afn_nnan_ninf_v2f32__y_3972; CHECK-SAME: (<2 x float> [[X:%.*]]) {973; CHECK-NEXT: entry:974; CHECK-NEXT: [[__POWX2:%.*]] = fmul nnan ninf afn <2 x float> [[X]], [[X]]975; CHECK-NEXT: [[__POWPROD:%.*]] = fmul nnan ninf afn <2 x float> [[X]], [[__POWX2]]976; CHECK-NEXT: ret <2 x float> [[__POWPROD]]977;978entry:979 %call = tail call afn nnan ninf <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> %x, <2 x i32> <i32 3, i32 3>)980 ret <2 x float> %call981}982 983define <2 x float> @test_pown_afn_nnan_ninf_v2f32__y_4(<2 x float> %x) {984; CHECK-LABEL: define <2 x float> @test_pown_afn_nnan_ninf_v2f32__y_4985; CHECK-SAME: (<2 x float> [[X:%.*]]) {986; CHECK-NEXT: entry:987; CHECK-NEXT: [[__POWX2:%.*]] = fmul nnan ninf afn <2 x float> [[X]], [[X]]988; CHECK-NEXT: [[__POWX21:%.*]] = fmul nnan ninf afn <2 x float> [[__POWX2]], [[__POWX2]]989; CHECK-NEXT: ret <2 x float> [[__POWX21]]990;991entry:992 %call = tail call afn nnan ninf <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> %x, <2 x i32> <i32 4, i32 4>)993 ret <2 x float> %call994}995 996define <2 x float> @test_pown_afn_nnan_ninf_v2f32__y_neg3(<2 x float> %x) {997; CHECK-LABEL: define <2 x float> @test_pown_afn_nnan_ninf_v2f32__y_neg3998; CHECK-SAME: (<2 x float> [[X:%.*]]) {999; CHECK-NEXT: entry:1000; CHECK-NEXT: [[__POWX2:%.*]] = fmul nnan ninf afn <2 x float> [[X]], [[X]]1001; CHECK-NEXT: [[__POWPROD:%.*]] = fmul nnan ninf afn <2 x float> [[X]], [[__POWX2]]1002; CHECK-NEXT: [[__1POWPROD:%.*]] = fdiv nnan ninf afn <2 x float> splat (float 1.000000e+00), [[__POWPROD]]1003; CHECK-NEXT: ret <2 x float> [[__1POWPROD]]1004;1005entry:1006 %call = tail call afn nnan ninf <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> %x, <2 x i32> <i32 -3, i32 -3>)1007 ret <2 x float> %call1008}1009 1010define <2 x float> @test_pown_afn_nnan_ninf_v2f32__y_neg4(<2 x float> %x) {1011; CHECK-LABEL: define <2 x float> @test_pown_afn_nnan_ninf_v2f32__y_neg41012; CHECK-SAME: (<2 x float> [[X:%.*]]) {1013; CHECK-NEXT: entry:1014; CHECK-NEXT: [[__POWX2:%.*]] = fmul nnan ninf afn <2 x float> [[X]], [[X]]1015; CHECK-NEXT: [[__POWX21:%.*]] = fmul nnan ninf afn <2 x float> [[__POWX2]], [[__POWX2]]1016; CHECK-NEXT: [[__1POWPROD:%.*]] = fdiv nnan ninf afn <2 x float> splat (float 1.000000e+00), [[__POWX21]]1017; CHECK-NEXT: ret <2 x float> [[__1POWPROD]]1018;1019entry:1020 %call = tail call afn nnan ninf <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> %x, <2 x i32> <i32 -4, i32 -4>)1021 ret <2 x float> %call1022}1023 1024define <2 x float> @test_pown_afn_nnan_ninf_v2f32__y_5(<2 x float> %x) {1025; CHECK-LABEL: define <2 x float> @test_pown_afn_nnan_ninf_v2f32__y_51026; CHECK-SAME: (<2 x float> [[X:%.*]]) {1027; CHECK-NEXT: entry:1028; CHECK-NEXT: [[__POWX2:%.*]] = fmul nnan ninf afn <2 x float> [[X]], [[X]]1029; CHECK-NEXT: [[__POWX21:%.*]] = fmul nnan ninf afn <2 x float> [[__POWX2]], [[__POWX2]]1030; CHECK-NEXT: [[__POWPROD:%.*]] = fmul nnan ninf afn <2 x float> [[X]], [[__POWX21]]1031; CHECK-NEXT: ret <2 x float> [[__POWPROD]]1032;1033entry:1034 %call = tail call afn nnan ninf <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> %x, <2 x i32> <i32 5, i32 5>)1035 ret <2 x float> %call1036}1037 1038define float @test_pown_f32__x_known_positive(float nofpclass(ninf nsub nnorm) %x, i32 %y) {1039; CHECK-LABEL: define float @test_pown_f32__x_known_positive1040; CHECK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]], i32 [[Y:%.*]]) {1041; CHECK-NEXT: entry:1042; CHECK-NEXT: [[CALL:%.*]] = tail call float @_Z4pownfi(float [[X]], i32 [[Y]])1043; CHECK-NEXT: ret float [[CALL]]1044;1045entry:1046 %call = tail call float @_Z4pownfi(float %x, i32 %y)1047 ret float %call1048}1049 1050define float @test_pown_afn_f32__x_known_positive(float nofpclass(ninf nsub nnorm) %x, i32 %y) {1051; CHECK-LABEL: define float @test_pown_afn_f32__x_known_positive1052; CHECK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]], i32 [[Y:%.*]]) {1053; CHECK-NEXT: entry:1054; CHECK-NEXT: [[CALL:%.*]] = tail call afn float @_Z4pownfi(float [[X]], i32 [[Y]])1055; CHECK-NEXT: ret float [[CALL]]1056;1057entry:1058 %call = tail call afn float @_Z4pownfi(float %x, i32 %y)1059 ret float %call1060}1061 1062define float @test_pown_afn_ninf_nnan_f32__x_known_positive(float nofpclass(ninf nsub nnorm) %x, i32 %y) {1063; CHECK-LABEL: define float @test_pown_afn_ninf_nnan_f32__x_known_positive1064; CHECK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]], i32 [[Y:%.*]]) {1065; CHECK-NEXT: entry:1066; CHECK-NEXT: [[__FABS:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])1067; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[__FABS]])1068; CHECK-NEXT: [[POWNI2F:%.*]] = sitofp i32 [[Y]] to float1069; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn float [[__LOG2]], [[POWNI2F]]1070; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[__YLOGX]])1071; CHECK-NEXT: [[__YEVEN:%.*]] = shl i32 [[Y]], 311072; CHECK-NEXT: [[TMP0:%.*]] = bitcast float [[X]] to i321073; CHECK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP0]]1074; CHECK-NEXT: [[TMP1:%.*]] = bitcast float [[__EXP2]] to i321075; CHECK-NEXT: [[TMP2:%.*]] = or disjoint i32 [[__POW_SIGN]], [[TMP1]]1076; CHECK-NEXT: [[TMP3:%.*]] = bitcast i32 [[TMP2]] to float1077; CHECK-NEXT: ret float [[TMP3]]1078;1079entry:1080 %call = tail call afn ninf nnan float @_Z4pownfi(float %x, i32 %y)1081 ret float %call1082}1083 1084define float @test_pown_afn_f32__x_known_positive__y_4(float nofpclass(ninf nsub nnorm) %x) {1085; CHECK-LABEL: define float @test_pown_afn_f32__x_known_positive__y_41086; CHECK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]]) {1087; CHECK-NEXT: entry:1088; CHECK-NEXT: [[CALL:%.*]] = tail call afn float @_Z4pownfi(float [[X]], i32 4)1089; CHECK-NEXT: ret float [[CALL]]1090;1091entry:1092 %call = tail call afn float @_Z4pownfi(float %x, i32 4)1093 ret float %call1094}1095 1096define float @test_pown_f32__x_known_positive__y_4(float nofpclass(ninf nsub nnorm) %x) {1097; CHECK-LABEL: define float @test_pown_f32__x_known_positive__y_41098; CHECK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]]) {1099; CHECK-NEXT: entry:1100; CHECK-NEXT: [[CALL:%.*]] = tail call float @_Z4pownfi(float [[X]], i32 4)1101; CHECK-NEXT: ret float [[CALL]]1102;1103entry:1104 %call = tail call float @_Z4pownfi(float %x, i32 4)1105 ret float %call1106}1107 1108define float @test_pown_f32_y_known_even(float %x, i32 %y.arg) {1109; CHECK-LABEL: define float @test_pown_f32_y_known_even1110; CHECK-SAME: (float [[X:%.*]], i32 [[Y_ARG:%.*]]) {1111; CHECK-NEXT: entry:1112; CHECK-NEXT: [[Y:%.*]] = shl i32 [[Y_ARG]], 11113; CHECK-NEXT: [[CALL:%.*]] = tail call float @_Z4pownfi(float [[X]], i32 [[Y]])1114; CHECK-NEXT: ret float [[CALL]]1115;1116entry:1117 %y = shl i32 %y.arg, 11118 %call = tail call float @_Z4pownfi(float %x, i32 %y)1119 ret float %call1120}1121 1122define float @test_fast_pown_f32_y_known_even(float %x, i32 %y.arg) {1123; CHECK-LABEL: define float @test_fast_pown_f32_y_known_even1124; CHECK-SAME: (float [[X:%.*]], i32 [[Y_ARG:%.*]]) {1125; CHECK-NEXT: entry:1126; CHECK-NEXT: [[Y:%.*]] = shl i32 [[Y_ARG]], 11127; CHECK-NEXT: [[__FABS:%.*]] = call fast float @llvm.fabs.f32(float [[X]])1128; CHECK-NEXT: [[__LOG2:%.*]] = call fast float @llvm.log2.f32(float [[__FABS]])1129; CHECK-NEXT: [[POWNI2F:%.*]] = sitofp i32 [[Y]] to float1130; CHECK-NEXT: [[__YLOGX:%.*]] = fmul fast float [[__LOG2]], [[POWNI2F]]1131; CHECK-NEXT: [[__EXP2:%.*]] = call fast float @llvm.exp2.f32(float [[__YLOGX]])1132; CHECK-NEXT: ret float [[__EXP2]]1133;1134entry:1135 %y = shl i32 %y.arg, 11136 %call = tail call fast float @_Z4pownfi(float %x, i32 %y)1137 ret float %call1138}1139 1140define float @test_fast_pown_f32_known_positive_y_known_even(float nofpclass(ninf nsub nnorm) %x, i32 %y.arg) {1141; CHECK-LABEL: define float @test_fast_pown_f32_known_positive_y_known_even1142; CHECK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]], i32 [[Y_ARG:%.*]]) {1143; CHECK-NEXT: entry:1144; CHECK-NEXT: [[Y:%.*]] = shl i32 [[Y_ARG]], 11145; CHECK-NEXT: [[__FABS:%.*]] = call fast float @llvm.fabs.f32(float [[X]])1146; CHECK-NEXT: [[__LOG2:%.*]] = call fast float @llvm.log2.f32(float [[__FABS]])1147; CHECK-NEXT: [[POWNI2F:%.*]] = sitofp i32 [[Y]] to float1148; CHECK-NEXT: [[__YLOGX:%.*]] = fmul fast float [[__LOG2]], [[POWNI2F]]1149; CHECK-NEXT: [[__EXP2:%.*]] = call fast float @llvm.exp2.f32(float [[__YLOGX]])1150; CHECK-NEXT: ret float [[__EXP2]]1151;1152entry:1153 %y = shl i32 %y.arg, 11154 %call = tail call fast float @_Z4pownfi(float %x, i32 %y)1155 ret float %call1156}1157 1158attributes #0 = { nobuiltin }1159attributes #1 = { strictfp }1160