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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals all --version 42; RUN: opt < %s -passes=amdgpu-sw-lower-lds -amdgpu-asan-instrument-lds=false -S -mtriple=amdgcn-amd-amdhsa | FileCheck %s3 4; Test to check if direct access of dynamic LDS in kernel is lowered correctly.5@lds_1 = external addrspace(3) global [0 x i8]6@lds_2 = external addrspace(3) global [0 x i8]7 8;.9; CHECK: @llvm.amdgcn.sw.lds.k0 = internal addrspace(3) global ptr poison, no_sanitize_address, align 1, !absolute_symbol [[META0:![0-9]+]]10; CHECK: @llvm.amdgcn.k0.dynlds = external addrspace(3) global [0 x i8], no_sanitize_address, align 1, !absolute_symbol [[META1:![0-9]+]]11; CHECK: @llvm.amdgcn.sw.lds.k0.md = internal addrspace(1) global %llvm.amdgcn.sw.lds.k0.md.type { %llvm.amdgcn.sw.lds.k0.md.item { i32 0, i32 8, i32 32 }, %llvm.amdgcn.sw.lds.k0.md.item { i32 32, i32 0, i32 32 } }, no_sanitize_address12;.13define amdgpu_kernel void @k0() sanitize_address {14; CHECK-LABEL: define amdgpu_kernel void @k0(15; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {16; CHECK-NEXT: WId:17; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()18; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.workitem.id.y()19; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.amdgcn.workitem.id.z()20; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP0]], [[TMP1]]21; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP3]], [[TMP2]]22; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 023; CHECK-NEXT: br i1 [[TMP5]], label [[MALLOC:%.*]], label [[TMP7:%.*]]24; CHECK: Malloc:25; CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, align 426; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE:%.*]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 0, i32 2), align 427; CHECK-NEXT: [[TMP24:%.*]] = add i32 [[TMP8]], [[TMP9]]28; CHECK-NEXT: [[TMP20:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()29; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds ptr addrspace(4), ptr addrspace(4) [[TMP20]], i64 1530; CHECK-NEXT: store i32 [[TMP24]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 0), align 431; CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr addrspace(4) [[TMP18]], align 432; CHECK-NEXT: store i32 [[TMP13]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 1), align 433; CHECK-NEXT: [[TMP14:%.*]] = add i32 [[TMP13]], 034; CHECK-NEXT: [[TMP15:%.*]] = udiv i32 [[TMP14]], 135; CHECK-NEXT: [[TMP16:%.*]] = mul i32 [[TMP15]], 136; CHECK-NEXT: store i32 [[TMP16]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 2), align 437; CHECK-NEXT: [[TMP17:%.*]] = add i32 [[TMP24]], [[TMP16]]38; CHECK-NEXT: [[TMP21:%.*]] = zext i32 [[TMP17]] to i6439; CHECK-NEXT: [[TMP22:%.*]] = call ptr @llvm.returnaddress(i32 0)40; CHECK-NEXT: [[TMP23:%.*]] = ptrtoint ptr [[TMP22]] to i6441; CHECK-NEXT: [[TMP19:%.*]] = call i64 @__asan_malloc_impl(i64 [[TMP21]], i64 [[TMP23]])42; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP19]] to ptr addrspace(1)43; CHECK-NEXT: store ptr addrspace(1) [[TMP6]], ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 844; CHECK-NEXT: [[TMP42:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP6]], i64 845; CHECK-NEXT: [[TMP44:%.*]] = ptrtoint ptr addrspace(1) [[TMP42]] to i6446; CHECK-NEXT: call void @__asan_poison_region(i64 [[TMP44]], i64 24)47; CHECK-NEXT: br label [[TMP7]]48; CHECK: 23:49; CHECK-NEXT: [[XYZCOND:%.*]] = phi i1 [ false, [[WID:%.*]] ], [ true, [[MALLOC]] ]50; CHECK-NEXT: call void @llvm.amdgcn.s.barrier()51; CHECK-NEXT: [[TMP28:%.*]] = load ptr addrspace(1), ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 852; CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 0), align 453; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds i8, ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, i32 [[TMP10]]54; CHECK-NEXT: call void @llvm.donothing() [ "ExplicitUse"(ptr addrspace(3) @llvm.amdgcn.k0.dynlds) ]55; CHECK-NEXT: [[TMP45:%.*]] = ptrtoint ptr addrspace(3) [[TMP11]] to i3256; CHECK-NEXT: [[TMP46:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP28]], i32 [[TMP45]]57; CHECK-NEXT: store i8 7, ptr addrspace(1) [[TMP46]], align 458; CHECK-NEXT: br label [[CONDFREE1:%.*]]59; CHECK: CondFree:60; CHECK-NEXT: call void @llvm.amdgcn.s.barrier()61; CHECK-NEXT: br i1 [[XYZCOND]], label [[FREE:%.*]], label [[END:%.*]]62; CHECK: Free:63; CHECK-NEXT: [[TMP25:%.*]] = call ptr @llvm.returnaddress(i32 0)64; CHECK-NEXT: [[TMP26:%.*]] = ptrtoint ptr [[TMP25]] to i6465; CHECK-NEXT: [[TMP27:%.*]] = ptrtoint ptr addrspace(1) [[TMP28]] to i6466; CHECK-NEXT: call void @__asan_free_impl(i64 [[TMP27]], i64 [[TMP26]])67; CHECK-NEXT: br label [[END]]68; CHECK: End:69; CHECK-NEXT: ret void70;71 store i8 7, ptr addrspace(3) @lds_1, align 472 ;store i8 8, ptr addrspace(3) @lds_2, align 873 ret void74}75 76!llvm.module.flags = !{!0}77!0 = !{i32 4, !"nosanitize_address", i32 1}78 79;.80; CHECK: attributes #[[ATTR0]] = { sanitize_address "amdgpu-lds-size"="8,8" }81; CHECK: attributes #[[ATTR1:[0-9]+]] = { nocallback nofree nosync nounwind willreturn memory(none) }82; CHECK: attributes #[[ATTR2:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }83; CHECK: attributes #[[ATTR3:[0-9]+]] = { convergent nocallback nofree nounwind willreturn }84;.85; CHECK: [[META0]] = !{i32 0, i32 1}86; CHECK: [[META1]] = !{i32 8, i32 9}87;.88