228 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 42; RUN: opt < %s -passes=amdgpu-sw-lower-lds -amdgpu-asan-instrument-lds=false -S -mtriple=amdgcn-amd-amdhsa | FileCheck %s3 4; Test to check when multiple kernels access the same non-kernel, LDS accesses are lowere correctly.5@lds_1 = internal addrspace(3) global [1 x i8] poison, align 16@lds_2 = internal addrspace(3) global [1 x i32] poison, align 27@lds_3 = external addrspace(3) global [0 x i8], align 48@lds_4 = external addrspace(3) global [0 x i8], align 89 10define void @use_variables_1() sanitize_address {11; CHECK-LABEL: define void @use_variables_1(12; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {13; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.lds.kernel.id()14; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr addrspace(3)], ptr addrspace(1) @llvm.amdgcn.sw.lds.base.table, i32 0, i32 [[TMP1]]15; CHECK-NEXT: [[TMP4:%.*]] = load ptr addrspace(3), ptr addrspace(1) [[TMP2]], align 416; CHECK-NEXT: [[TMP7:%.*]] = load ptr addrspace(1), ptr addrspace(3) [[TMP4]], align 817; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x [4 x ptr addrspace(1)]], ptr addrspace(1) @llvm.amdgcn.sw.lds.offset.table, i32 0, i32 [[TMP1]], i32 218; CHECK-NEXT: [[TMP5:%.*]] = load ptr addrspace(1), ptr addrspace(1) [[TMP6]], align 819; CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr addrspace(1) [[TMP5]], align 420; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i8, ptr addrspace(3) [[TMP4]], i32 [[TMP8]]21; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x [4 x ptr addrspace(1)]], ptr addrspace(1) @llvm.amdgcn.sw.lds.offset.table, i32 0, i32 [[TMP1]], i32 322; CHECK-NEXT: [[TMP12:%.*]] = load ptr addrspace(1), ptr addrspace(1) [[TMP11]], align 823; CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr addrspace(1) [[TMP12]], align 424; CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds i8, ptr addrspace(3) [[TMP4]], i32 [[TMP10]]25; CHECK-NEXT: [[TMP13:%.*]] = ptrtoint ptr addrspace(3) [[TMP9]] to i3226; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP7]], i32 [[TMP13]]27; CHECK-NEXT: store i8 3, ptr addrspace(1) [[TMP14]], align 428; CHECK-NEXT: [[TMP30:%.*]] = ptrtoint ptr addrspace(3) [[TMP15]] to i3229; CHECK-NEXT: [[TMP31:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP7]], i32 [[TMP30]]30; CHECK-NEXT: store i8 3, ptr addrspace(1) [[TMP31]], align 831; CHECK-NEXT: ret void32;33 store i8 3, ptr addrspace(3) @lds_3, align 434 store i8 3, ptr addrspace(3) @lds_4, align 835 ret void36}37 38define void @use_variables_2() sanitize_address {39; CHECK-LABEL: define void @use_variables_2(40; CHECK-SAME: ) #[[ATTR0]] {41; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.lds.kernel.id()42; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr addrspace(3)], ptr addrspace(1) @llvm.amdgcn.sw.lds.base.table, i32 0, i32 [[TMP1]]43; CHECK-NEXT: [[TMP4:%.*]] = load ptr addrspace(3), ptr addrspace(1) [[TMP2]], align 444; CHECK-NEXT: [[TMP7:%.*]] = load ptr addrspace(1), ptr addrspace(3) [[TMP4]], align 845; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x [4 x ptr addrspace(1)]], ptr addrspace(1) @llvm.amdgcn.sw.lds.offset.table, i32 0, i32 [[TMP1]], i32 046; CHECK-NEXT: [[TMP5:%.*]] = load ptr addrspace(1), ptr addrspace(1) [[TMP6]], align 847; CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr addrspace(1) [[TMP5]], align 448; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i8, ptr addrspace(3) [[TMP4]], i32 [[TMP8]]49; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x [4 x ptr addrspace(1)]], ptr addrspace(1) @llvm.amdgcn.sw.lds.offset.table, i32 0, i32 [[TMP1]], i32 150; CHECK-NEXT: [[TMP12:%.*]] = load ptr addrspace(1), ptr addrspace(1) [[TMP11]], align 851; CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr addrspace(1) [[TMP12]], align 452; CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds i8, ptr addrspace(3) [[TMP4]], i32 [[TMP10]]53; CHECK-NEXT: [[TMP13:%.*]] = ptrtoint ptr addrspace(3) [[TMP9]] to i3254; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP7]], i32 [[TMP13]]55; CHECK-NEXT: store i8 7, ptr addrspace(1) [[TMP14]], align 156; CHECK-NEXT: [[TMP30:%.*]] = ptrtoint ptr addrspace(3) [[TMP15]] to i3257; CHECK-NEXT: [[TMP31:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP7]], i32 [[TMP30]]58; CHECK-NEXT: store i32 8, ptr addrspace(1) [[TMP31]], align 259; CHECK-NEXT: ret void60;61 store i8 7, ptr addrspace(3) @lds_1, align 162 store i32 8, ptr addrspace(3) @lds_2, align 263 ret void64}65 66define amdgpu_kernel void @k0() sanitize_address {67; CHECK-LABEL: define amdgpu_kernel void @k0(68; CHECK-SAME: ) #[[ATTR1:[0-9]+]] !llvm.amdgcn.lds.kernel.id [[META2:![0-9]+]] {69; CHECK-NEXT: WId:70; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()71; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.workitem.id.y()72; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.amdgcn.workitem.id.z()73; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP0]], [[TMP1]]74; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP3]], [[TMP2]]75; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 076; CHECK-NEXT: br i1 [[TMP5]], label [[MALLOC:%.*]], label [[TMP21:%.*]]77; CHECK: Malloc:78; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE:%.*]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 0), align 479; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 2), align 480; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP9]], [[TMP7]]81; CHECK-NEXT: [[TMP6:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()82; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds ptr addrspace(4), ptr addrspace(4) [[TMP6]], i64 1583; CHECK-NEXT: store i32 [[TMP8]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 0), align 484; CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr addrspace(4) [[TMP10]], align 485; CHECK-NEXT: store i32 [[TMP11]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 1), align 486; CHECK-NEXT: [[TMP12:%.*]] = add i32 [[TMP11]], 787; CHECK-NEXT: [[TMP13:%.*]] = udiv i32 [[TMP12]], 888; CHECK-NEXT: [[TMP14:%.*]] = mul i32 [[TMP13]], 889; CHECK-NEXT: store i32 [[TMP14]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 2), align 490; CHECK-NEXT: [[TMP15:%.*]] = add i32 [[TMP8]], [[TMP14]]91; CHECK-NEXT: store i32 [[TMP15]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 0), align 492; CHECK-NEXT: [[TMP25:%.*]] = load i32, ptr addrspace(4) [[TMP10]], align 493; CHECK-NEXT: store i32 [[TMP25]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 1), align 494; CHECK-NEXT: [[TMP17:%.*]] = add i32 [[TMP25]], 795; CHECK-NEXT: [[TMP18:%.*]] = udiv i32 [[TMP17]], 896; CHECK-NEXT: [[TMP19:%.*]] = mul i32 [[TMP18]], 897; CHECK-NEXT: store i32 [[TMP19]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 2), align 498; CHECK-NEXT: [[TMP26:%.*]] = add i32 [[TMP15]], [[TMP19]]99; CHECK-NEXT: [[TMP27:%.*]] = zext i32 [[TMP26]] to i64100; CHECK-NEXT: [[TMP28:%.*]] = call ptr @llvm.returnaddress(i32 0)101; CHECK-NEXT: [[TMP33:%.*]] = ptrtoint ptr [[TMP28]] to i64102; CHECK-NEXT: [[TMP24:%.*]] = call i64 @__asan_malloc_impl(i64 [[TMP27]], i64 [[TMP33]])103; CHECK-NEXT: [[TMP20:%.*]] = inttoptr i64 [[TMP24]] to ptr addrspace(1)104; CHECK-NEXT: store ptr addrspace(1) [[TMP20]], ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 8105; CHECK-NEXT: [[TMP49:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP20]], i64 8106; CHECK-NEXT: [[TMP51:%.*]] = ptrtoint ptr addrspace(1) [[TMP49]] to i64107; CHECK-NEXT: call void @__asan_poison_region(i64 [[TMP51]], i64 24)108; CHECK-NEXT: [[TMP52:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP20]], i64 33109; CHECK-NEXT: [[TMP53:%.*]] = ptrtoint ptr addrspace(1) [[TMP52]] to i64110; CHECK-NEXT: call void @__asan_poison_region(i64 [[TMP53]], i64 31)111; CHECK-NEXT: br label [[TMP21]]112; CHECK: 30:113; CHECK-NEXT: [[XYZCOND:%.*]] = phi i1 [ false, [[WID:%.*]] ], [ true, [[MALLOC]] ]114; CHECK-NEXT: call void @llvm.amdgcn.s.barrier()115; CHECK-NEXT: [[TMP29:%.*]] = load ptr addrspace(1), ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 8116; CHECK-NEXT: [[TMP22:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 0), align 4117; CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds i8, ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, i32 [[TMP22]]118; CHECK-NEXT: call void @llvm.donothing() [ "ExplicitUse"(ptr addrspace(3) @llvm.amdgcn.k0.dynlds) ]119; CHECK-NEXT: call void @use_variables_1()120; CHECK-NEXT: [[TMP34:%.*]] = ptrtoint ptr addrspace(3) [[TMP23]] to i32121; CHECK-NEXT: [[TMP35:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP29]], i32 [[TMP34]]122; CHECK-NEXT: store i8 7, ptr addrspace(1) [[TMP35]], align 1123; CHECK-NEXT: br label [[CONDFREE1:%.*]]124; CHECK: CondFree:125; CHECK-NEXT: call void @llvm.amdgcn.s.barrier()126; CHECK-NEXT: br i1 [[XYZCOND]], label [[FREE:%.*]], label [[END:%.*]]127; CHECK: Free:128; CHECK-NEXT: [[TMP30:%.*]] = call ptr @llvm.returnaddress(i32 0)129; CHECK-NEXT: [[TMP31:%.*]] = ptrtoint ptr [[TMP30]] to i64130; CHECK-NEXT: [[TMP32:%.*]] = ptrtoint ptr addrspace(1) [[TMP29]] to i64131; CHECK-NEXT: call void @__asan_free_impl(i64 [[TMP32]], i64 [[TMP31]])132; CHECK-NEXT: br label [[END]]133; CHECK: End:134; CHECK-NEXT: ret void135;136 call void @use_variables_1()137 store i8 7, ptr addrspace(3) @lds_1, align 1138 ret void139}140 141define amdgpu_kernel void @k1() sanitize_address {142; CHECK-LABEL: define amdgpu_kernel void @k1(143; CHECK-SAME: ) #[[ATTR1]] !llvm.amdgcn.lds.kernel.id [[META3:![0-9]+]] {144; CHECK-NEXT: WId:145; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()146; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.workitem.id.y()147; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.amdgcn.workitem.id.z()148; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP0]], [[TMP1]]149; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP3]], [[TMP2]]150; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0151; CHECK-NEXT: br i1 [[TMP5]], label [[MALLOC:%.*]], label [[TMP14:%.*]]152; CHECK: Malloc:153; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K1_MD_TYPE:%.*]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 2, i32 0), align 4154; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K1_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 2, i32 2), align 4155; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP9]], [[TMP7]]156; CHECK-NEXT: [[TMP6:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()157; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds ptr addrspace(4), ptr addrspace(4) [[TMP6]], i64 15158; CHECK-NEXT: store i32 [[TMP8]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K1_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 3, i32 0), align 4159; CHECK-NEXT: [[TMP30:%.*]] = load i32, ptr addrspace(4) [[TMP10]], align 4160; CHECK-NEXT: store i32 [[TMP30]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K1_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 3, i32 1), align 4161; CHECK-NEXT: [[TMP33:%.*]] = add i32 [[TMP30]], 7162; CHECK-NEXT: [[TMP18:%.*]] = udiv i32 [[TMP33]], 8163; CHECK-NEXT: [[TMP19:%.*]] = mul i32 [[TMP18]], 8164; CHECK-NEXT: store i32 [[TMP19]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K1_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 3, i32 2), align 4165; CHECK-NEXT: [[TMP20:%.*]] = add i32 [[TMP8]], [[TMP19]]166; CHECK-NEXT: store i32 [[TMP20]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K1_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 4, i32 0), align 4167; CHECK-NEXT: [[TMP21:%.*]] = load i32, ptr addrspace(4) [[TMP10]], align 4168; CHECK-NEXT: store i32 [[TMP21]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K1_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 4, i32 1), align 4169; CHECK-NEXT: [[TMP22:%.*]] = add i32 [[TMP21]], 7170; CHECK-NEXT: [[TMP23:%.*]] = udiv i32 [[TMP22]], 8171; CHECK-NEXT: [[TMP24:%.*]] = mul i32 [[TMP23]], 8172; CHECK-NEXT: store i32 [[TMP24]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K1_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 4, i32 2), align 4173; CHECK-NEXT: [[TMP25:%.*]] = add i32 [[TMP20]], [[TMP24]]174; CHECK-NEXT: [[TMP26:%.*]] = zext i32 [[TMP25]] to i64175; CHECK-NEXT: [[TMP27:%.*]] = call ptr @llvm.returnaddress(i32 0)176; CHECK-NEXT: [[TMP28:%.*]] = ptrtoint ptr [[TMP27]] to i64177; CHECK-NEXT: [[TMP34:%.*]] = call i64 @__asan_malloc_impl(i64 [[TMP26]], i64 [[TMP28]])178; CHECK-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP34]] to ptr addrspace(1)179; CHECK-NEXT: store ptr addrspace(1) [[TMP13]], ptr addrspace(3) @llvm.amdgcn.sw.lds.k1, align 8180; CHECK-NEXT: [[TMP51:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP13]], i64 8181; CHECK-NEXT: [[TMP53:%.*]] = ptrtoint ptr addrspace(1) [[TMP51]] to i64182; CHECK-NEXT: call void @__asan_poison_region(i64 [[TMP53]], i64 24)183; CHECK-NEXT: [[TMP54:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP13]], i64 33184; CHECK-NEXT: [[TMP55:%.*]] = ptrtoint ptr addrspace(1) [[TMP54]] to i64185; CHECK-NEXT: call void @__asan_poison_region(i64 [[TMP55]], i64 31)186; CHECK-NEXT: [[TMP56:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP13]], i64 68187; CHECK-NEXT: [[TMP57:%.*]] = ptrtoint ptr addrspace(1) [[TMP56]] to i64188; CHECK-NEXT: call void @__asan_poison_region(i64 [[TMP57]], i64 28)189; CHECK-NEXT: br label [[TMP14]]190; CHECK: 32:191; CHECK-NEXT: [[XYZCOND:%.*]] = phi i1 [ false, [[WID:%.*]] ], [ true, [[MALLOC]] ]192; CHECK-NEXT: call void @llvm.amdgcn.s.barrier()193; CHECK-NEXT: [[TMP29:%.*]] = load ptr addrspace(1), ptr addrspace(3) @llvm.amdgcn.sw.lds.k1, align 8194; CHECK-NEXT: [[TMP31:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K1_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 3, i32 0), align 4195; CHECK-NEXT: [[TMP32:%.*]] = getelementptr inbounds i8, ptr addrspace(3) @llvm.amdgcn.sw.lds.k1, i32 [[TMP31]]196; CHECK-NEXT: call void @llvm.donothing() [ "ExplicitUse"(ptr addrspace(3) @llvm.amdgcn.k1.dynlds) ]197; CHECK-NEXT: call void @use_variables_1()198; CHECK-NEXT: call void @use_variables_2()199; CHECK-NEXT: [[TMP58:%.*]] = ptrtoint ptr addrspace(3) [[TMP32]] to i32200; CHECK-NEXT: [[TMP59:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP29]], i32 [[TMP58]]201; CHECK-NEXT: store i8 3, ptr addrspace(1) [[TMP59]], align 4202; CHECK-NEXT: br label [[CONDFREE1:%.*]]203; CHECK: CondFree:204; CHECK-NEXT: call void @llvm.amdgcn.s.barrier()205; CHECK-NEXT: br i1 [[XYZCOND]], label [[FREE:%.*]], label [[END:%.*]]206; CHECK: Free:207; CHECK-NEXT: [[TMP35:%.*]] = call ptr @llvm.returnaddress(i32 0)208; CHECK-NEXT: [[TMP36:%.*]] = ptrtoint ptr [[TMP35]] to i64209; CHECK-NEXT: [[TMP37:%.*]] = ptrtoint ptr addrspace(1) [[TMP29]] to i64210; CHECK-NEXT: call void @__asan_free_impl(i64 [[TMP37]], i64 [[TMP36]])211; CHECK-NEXT: br label [[END]]212; CHECK: End:213; CHECK-NEXT: ret void214;215 call void @use_variables_1()216 call void @use_variables_2()217 store i8 3, ptr addrspace(3) @lds_3, align 4218 ret void219}220 221!llvm.module.flags = !{!0}222!0 = !{i32 4, !"nosanitize_address", i32 1}223 224;.225; CHECK: [[META2]] = !{i32 0}226; CHECK: [[META3]] = !{i32 1}227;.228