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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals all --version 42; RUN: opt < %s -passes=amdgpu-sw-lower-lds -S -mtriple=amdgcn-amd-amdhsa | FileCheck %s3 4@lds_1 = internal addrspace(3) global [1 x i32] poison, align 45 6;.7; CHECK: @llvm.amdgcn.sw.lds.atomic_xchg_kernel = internal addrspace(3) global ptr poison, no_sanitize_address, align 4, !absolute_symbol [[META0:![0-9]+]]8; CHECK: @llvm.amdgcn.sw.lds.atomic_xchg_kernel.md = internal addrspace(1) global %llvm.amdgcn.sw.lds.atomic_xchg_kernel.md.type { %llvm.amdgcn.sw.lds.atomic_xchg_kernel.md.item { i32 0, i32 8, i32 32 }, %llvm.amdgcn.sw.lds.atomic_xchg_kernel.md.item { i32 32, i32 4, i32 32 } }, no_sanitize_address9;.10define amdgpu_kernel void @atomic_xchg_kernel(ptr addrspace(1) %out, [8 x i32], [8 x i32], i32 %swap) sanitize_address {11; CHECK-LABEL: define amdgpu_kernel void @atomic_xchg_kernel(12; CHECK-SAME: ptr addrspace(1) [[OUT:%.*]], [8 x i32] [[TMP0:%.*]], [8 x i32] [[TMP1:%.*]], i32 [[SWAP:%.*]]) #[[ATTR0:[0-9]+]] {13; CHECK-NEXT: WId:14; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()15; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.workitem.id.y()16; CHECK-NEXT: [[TMP4:%.*]] = call i32 @llvm.amdgcn.workitem.id.z()17; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP2]], [[TMP3]]18; CHECK-NEXT: [[TMP6:%.*]] = or i32 [[TMP5]], [[TMP4]]19; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[TMP6]], 020; CHECK-NEXT: br i1 [[TMP7]], label [[MALLOC:%.*]], label [[TMP20:%.*]]21; CHECK: Malloc:22; CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_ATOMIC_XCHG_KERNEL_MD_TYPE:%.*]], ptr addrspace(1) @llvm.amdgcn.sw.lds.atomic_xchg_kernel.md, i32 0, i32 1, i32 0), align 423; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_ATOMIC_XCHG_KERNEL_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.atomic_xchg_kernel.md, i32 0, i32 1, i32 2), align 424; CHECK-NEXT: [[TMP10:%.*]] = add i32 [[TMP8]], [[TMP9]]25; CHECK-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i6426; CHECK-NEXT: [[TMP12:%.*]] = call ptr @llvm.returnaddress(i32 0)27; CHECK-NEXT: [[TMP13:%.*]] = ptrtoint ptr [[TMP12]] to i6428; CHECK-NEXT: [[TMP14:%.*]] = call i64 @__asan_malloc_impl(i64 [[TMP11]], i64 [[TMP13]])29; CHECK-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP14]] to ptr addrspace(1)30; CHECK-NEXT: store ptr addrspace(1) [[TMP15]], ptr addrspace(3) @llvm.amdgcn.sw.lds.atomic_xchg_kernel, align 831; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP15]], i64 832; CHECK-NEXT: [[TMP17:%.*]] = ptrtoint ptr addrspace(1) [[TMP16]] to i6433; CHECK-NEXT: call void @__asan_poison_region(i64 [[TMP17]], i64 24)34; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP15]], i64 3635; CHECK-NEXT: [[TMP19:%.*]] = ptrtoint ptr addrspace(1) [[TMP18]] to i6436; CHECK-NEXT: call void @__asan_poison_region(i64 [[TMP19]], i64 28)37; CHECK-NEXT: br label [[TMP20]]38; CHECK: 20:39; CHECK-NEXT: [[XYZCOND:%.*]] = phi i1 [ false, [[WID:%.*]] ], [ true, [[MALLOC]] ]40; CHECK-NEXT: call void @llvm.amdgcn.s.barrier()41; CHECK-NEXT: [[TMP21:%.*]] = load ptr addrspace(1), ptr addrspace(3) @llvm.amdgcn.sw.lds.atomic_xchg_kernel, align 842; CHECK-NEXT: [[TMP22:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_ATOMIC_XCHG_KERNEL_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.atomic_xchg_kernel.md, i32 0, i32 1, i32 0), align 443; CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds i8, ptr addrspace(3) @llvm.amdgcn.sw.lds.atomic_xchg_kernel, i32 [[TMP22]]44; CHECK-NEXT: [[GEP:%.*]] = getelementptr i32, ptr addrspace(3) [[TMP23]], i32 445; CHECK-NEXT: [[TMP24:%.*]] = ptrtoint ptr addrspace(3) [[GEP]] to i3246; CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP21]], i32 [[TMP24]]47; CHECK-NEXT: [[TMP26:%.*]] = ptrtoint ptr addrspace(1) [[TMP25]] to i6448; CHECK-NEXT: [[TMP32:%.*]] = add i64 [[TMP26]], 349; CHECK-NEXT: [[TMP59:%.*]] = inttoptr i64 [[TMP32]] to ptr addrspace(1)50; CHECK-NEXT: [[TMP60:%.*]] = ptrtoint ptr addrspace(1) [[TMP25]] to i6451; CHECK-NEXT: [[TMP27:%.*]] = lshr i64 [[TMP60]], 352; CHECK-NEXT: [[TMP28:%.*]] = add i64 [[TMP27]], 214745088053; CHECK-NEXT: [[TMP29:%.*]] = inttoptr i64 [[TMP28]] to ptr54; CHECK-NEXT: [[TMP30:%.*]] = load i8, ptr [[TMP29]], align 155; CHECK-NEXT: [[TMP31:%.*]] = icmp ne i8 [[TMP30]], 056; CHECK-NEXT: [[TMP33:%.*]] = and i64 [[TMP60]], 757; CHECK-NEXT: [[TMP34:%.*]] = trunc i64 [[TMP33]] to i858; CHECK-NEXT: [[TMP35:%.*]] = icmp sge i8 [[TMP34]], [[TMP30]]59; CHECK-NEXT: [[TMP36:%.*]] = and i1 [[TMP31]], [[TMP35]]60; CHECK-NEXT: [[TMP37:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP36]])61; CHECK-NEXT: [[TMP38:%.*]] = icmp ne i64 [[TMP37]], 062; CHECK-NEXT: br i1 [[TMP38]], label [[ASAN_REPORT:%.*]], label [[TMP41:%.*]], !prof [[PROF2:![0-9]+]]63; CHECK: asan.report:64; CHECK-NEXT: br i1 [[TMP36]], label [[TMP39:%.*]], label [[TMP40:%.*]]65; CHECK: 41:66; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP60]]) #[[ATTR6:[0-9]+]]67; CHECK-NEXT: call void @llvm.amdgcn.unreachable()68; CHECK-NEXT: br label [[TMP40]]69; CHECK: 42:70; CHECK-NEXT: br label [[TMP41]]71; CHECK: 43:72; CHECK-NEXT: [[TMP61:%.*]] = ptrtoint ptr addrspace(1) [[TMP59]] to i6473; CHECK-NEXT: [[TMP62:%.*]] = lshr i64 [[TMP61]], 374; CHECK-NEXT: [[TMP46:%.*]] = add i64 [[TMP62]], 214745088075; CHECK-NEXT: [[TMP47:%.*]] = inttoptr i64 [[TMP46]] to ptr76; CHECK-NEXT: [[TMP48:%.*]] = load i8, ptr [[TMP47]], align 177; CHECK-NEXT: [[TMP49:%.*]] = icmp ne i8 [[TMP48]], 078; CHECK-NEXT: [[TMP50:%.*]] = and i64 [[TMP61]], 779; CHECK-NEXT: [[TMP51:%.*]] = trunc i64 [[TMP50]] to i880; CHECK-NEXT: [[TMP52:%.*]] = icmp sge i8 [[TMP51]], [[TMP48]]81; CHECK-NEXT: [[TMP53:%.*]] = and i1 [[TMP49]], [[TMP52]]82; CHECK-NEXT: [[TMP54:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP53]])83; CHECK-NEXT: [[TMP55:%.*]] = icmp ne i64 [[TMP54]], 084; CHECK-NEXT: br i1 [[TMP55]], label [[ASAN_REPORT1:%.*]], label [[TMP58:%.*]], !prof [[PROF2]]85; CHECK: asan.report1:86; CHECK-NEXT: br i1 [[TMP53]], label [[TMP56:%.*]], label [[TMP57:%.*]]87; CHECK: 56:88; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP61]]) #[[ATTR6]]89; CHECK-NEXT: call void @llvm.amdgcn.unreachable()90; CHECK-NEXT: br label [[TMP57]]91; CHECK: 57:92; CHECK-NEXT: br label [[TMP58]]93; CHECK: 58:94; CHECK-NEXT: [[TMP42:%.*]] = cmpxchg ptr addrspace(1) [[TMP25]], i32 7, i32 [[SWAP]] seq_cst monotonic, align 495; CHECK-NEXT: [[RESULT:%.*]] = extractvalue { i32, i1 } [[TMP42]], 096; CHECK-NEXT: store i32 [[RESULT]], ptr addrspace(1) [[OUT]], align 497; CHECK-NEXT: br label [[CONDFREE:%.*]]98; CHECK: CondFree:99; CHECK-NEXT: call void @llvm.amdgcn.s.barrier()100; CHECK-NEXT: br i1 [[XYZCOND]], label [[FREE:%.*]], label [[END:%.*]]101; CHECK: Free:102; CHECK-NEXT: [[TMP43:%.*]] = call ptr @llvm.returnaddress(i32 0)103; CHECK-NEXT: [[TMP44:%.*]] = ptrtoint ptr [[TMP43]] to i64104; CHECK-NEXT: [[TMP45:%.*]] = ptrtoint ptr addrspace(1) [[TMP21]] to i64105; CHECK-NEXT: call void @__asan_free_impl(i64 [[TMP45]], i64 [[TMP44]])106; CHECK-NEXT: br label [[END]]107; CHECK: End:108; CHECK-NEXT: ret void109;110 %gep = getelementptr i32, ptr addrspace(3) @lds_1, i32 4111 %pair = cmpxchg ptr addrspace(3) %gep, i32 7, i32 %swap seq_cst monotonic112 %result = extractvalue { i32, i1 } %pair, 0113 store i32 %result, ptr addrspace(1) %out, align 4114 ret void115}116 117!llvm.module.flags = !{!0}118!0 = !{i32 4, !"nosanitize_address", i32 1}119 120;.121; CHECK: attributes #[[ATTR0]] = { sanitize_address "amdgpu-lds-size"="8" }122; CHECK: attributes #[[ATTR1:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }123; CHECK: attributes #[[ATTR2:[0-9]+]] = { nocallback nofree nosync nounwind willreturn memory(none) }124; CHECK: attributes #[[ATTR3:[0-9]+]] = { convergent nocallback nofree nounwind willreturn }125; CHECK: attributes #[[ATTR4:[0-9]+]] = { convergent nocallback nofree nounwind willreturn memory(none) }126; CHECK: attributes #[[ATTR5:[0-9]+]] = { convergent nocallback nofree nounwind }127; CHECK: attributes #[[ATTR6]] = { nomerge }128;.129; CHECK: [[META0]] = !{i32 0, i32 1}130; CHECK: [[META1:![0-9]+]] = !{i32 4, !"nosanitize_address", i32 1}131; CHECK: [[PROF2]] = !{!"branch_weights", i32 1, i32 1048575}132;.133