87 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals all --version 42; RUN: opt < %s -passes=amdgpu-sw-lower-lds -S -amdgpu-asan-instrument-lds=false -mtriple=amdgcn-amd-amdhsa | FileCheck %s3; RUN: llc < %s -enable-new-pm -stop-after=amdgpu-sw-lower-lds -amdgpu-asan-instrument-lds=false -mtriple=amdgcn-amd-amdhsa | FileCheck %s4 5; Test to check if static LDS accesses in kernel are lowered correctly.6@lds_1 = internal addrspace(3) global [1 x i8] poison, align 47@lds_2 = internal addrspace(3) global [1 x i32] poison, align 88 9;.10; CHECK: @llvm.amdgcn.sw.lds.k0 = internal addrspace(3) global ptr poison, no_sanitize_address, align 8, !absolute_symbol [[META0:![0-9]+]]11; CHECK: @llvm.amdgcn.sw.lds.k0.md = internal addrspace(1) global %llvm.amdgcn.sw.lds.k0.md.type { %llvm.amdgcn.sw.lds.k0.md.item { i32 0, i32 8, i32 32 }, %llvm.amdgcn.sw.lds.k0.md.item { i32 32, i32 1, i32 32 }, %llvm.amdgcn.sw.lds.k0.md.item { i32 64, i32 4, i32 32 } }, no_sanitize_address12;.13define amdgpu_kernel void @k0() sanitize_address {14; CHECK-LABEL: define amdgpu_kernel void @k0(15; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {16; CHECK-NEXT: WId:17; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()18; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.workitem.id.y()19; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.amdgcn.workitem.id.z()20; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP0]], [[TMP1]]21; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP3]], [[TMP2]]22; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 023; CHECK-NEXT: br i1 [[TMP5]], label [[MALLOC:%.*]], label [[TMP7:%.*]]24; CHECK: Malloc:25; CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE:%.*]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 0), align 426; CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 2), align 427; CHECK-NEXT: [[TMP16:%.*]] = add i32 [[TMP13]], [[TMP14]]28; CHECK-NEXT: [[TMP15:%.*]] = zext i32 [[TMP16]] to i6429; CHECK-NEXT: [[TMP23:%.*]] = call ptr @llvm.returnaddress(i32 0)30; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[TMP23]] to i6431; CHECK-NEXT: [[TMP12:%.*]] = call i64 @__asan_malloc_impl(i64 [[TMP15]], i64 [[TMP11]])32; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP12]] to ptr addrspace(1)33; CHECK-NEXT: store ptr addrspace(1) [[TMP6]], ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 834; CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP6]], i64 835; CHECK-NEXT: [[TMP41:%.*]] = ptrtoint ptr addrspace(1) [[TMP25]] to i6436; CHECK-NEXT: call void @__asan_poison_region(i64 [[TMP41]], i64 24)37; CHECK-NEXT: [[TMP61:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP6]], i64 3338; CHECK-NEXT: [[TMP62:%.*]] = ptrtoint ptr addrspace(1) [[TMP61]] to i6439; CHECK-NEXT: call void @__asan_poison_region(i64 [[TMP62]], i64 31)40; CHECK-NEXT: [[TMP63:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP6]], i64 6841; CHECK-NEXT: [[TMP64:%.*]] = ptrtoint ptr addrspace(1) [[TMP63]] to i6442; CHECK-NEXT: call void @__asan_poison_region(i64 [[TMP64]], i64 28)43; CHECK-NEXT: br label [[TMP7]]44; CHECK: 20:45; CHECK-NEXT: [[XYZCOND:%.*]] = phi i1 [ false, [[WID:%.*]] ], [ true, [[MALLOC]] ]46; CHECK-NEXT: call void @llvm.amdgcn.s.barrier()47; CHECK-NEXT: [[TMP19:%.*]] = load ptr addrspace(1), ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 848; CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 0), align 449; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds i8, ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, i32 [[TMP10]]50; CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 0), align 451; CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds i8, ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, i32 [[TMP17]]52; CHECK-NEXT: [[TMP26:%.*]] = ptrtoint ptr addrspace(3) [[TMP18]] to i3253; CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP19]], i32 [[TMP26]]54; CHECK-NEXT: store i8 7, ptr addrspace(1) [[TMP27]], align 455; CHECK-NEXT: [[TMP43:%.*]] = ptrtoint ptr addrspace(3) [[TMP24]] to i3256; CHECK-NEXT: [[TMP44:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP19]], i32 [[TMP43]]57; CHECK-NEXT: store i32 8, ptr addrspace(1) [[TMP44]], align 258; CHECK-NEXT: br label [[CONDFREE1:%.*]]59; CHECK: CondFree:60; CHECK-NEXT: call void @llvm.amdgcn.s.barrier()61; CHECK-NEXT: br i1 [[XYZCOND]], label [[FREE:%.*]], label [[END:%.*]]62; CHECK: Free:63; CHECK-NEXT: [[TMP20:%.*]] = call ptr @llvm.returnaddress(i32 0)64; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i6465; CHECK-NEXT: [[TMP22:%.*]] = ptrtoint ptr addrspace(1) [[TMP19]] to i6466; CHECK-NEXT: call void @__asan_free_impl(i64 [[TMP22]], i64 [[TMP21]])67; CHECK-NEXT: br label [[END]]68; CHECK: End:69; CHECK-NEXT: ret void70;71 store i8 7, ptr addrspace(3) @lds_1, align 472 store i32 8, ptr addrspace(3) @lds_2, align 273 ret void74}75 76!llvm.module.flags = !{!0}77!0 = !{i32 4, !"nosanitize_address", i32 1}78 79;.80; CHECK: attributes #[[ATTR0]] = { sanitize_address "amdgpu-lds-size"="8" }81; CHECK: attributes #[[ATTR1:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }82; CHECK: attributes #[[ATTR2:[0-9]+]] = { nocallback nofree nosync nounwind willreturn memory(none) }83; CHECK: attributes #[[ATTR3:[0-9]+]] = { convergent nocallback nofree nounwind willreturn }84;.85; CHECK: [[META0]] = !{i32 0, i32 1}86;.87