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1; RUN: llc < %s -show-mc-encoding -mattr=+promote-alloca -disable-promote-alloca-to-vector -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -mtriple=amdgcn | FileCheck -enable-var-scope -check-prefix=SI-PROMOTE -check-prefix=SI -check-prefix=FUNC %s2; RUN: llc < %s -show-mc-encoding -mattr=+promote-alloca -disable-promote-alloca-to-vector -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -mtriple=amdgcn--amdhsa -mcpu=kaveri -mattr=-unaligned-access-mode | FileCheck -enable-var-scope -check-prefix=SI-PROMOTE -check-prefix=SI -check-prefix=FUNC -check-prefix=HSA-PROMOTE %s3; RUN: llc < %s -show-mc-encoding -mattr=-promote-alloca -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -mtriple=amdgcn | FileCheck %s -check-prefix=SI-ALLOCA -check-prefix=SI -check-prefix=FUNC4; RUN: llc < %s -show-mc-encoding -mattr=-promote-alloca -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -mtriple=amdgcn-amdhsa -mcpu=kaveri -mattr=-unaligned-access-mode | FileCheck -enable-var-scope -check-prefix=SI-ALLOCA -check-prefix=SI -check-prefix=FUNC -check-prefix=HSA-ALLOCA %s5; RUN: llc < %s -show-mc-encoding -mattr=+promote-alloca -disable-promote-alloca-to-vector -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -mtriple=amdgcn-amdhsa -mcpu=tonga -mattr=-unaligned-access-mode | FileCheck -enable-var-scope -check-prefix=SI-PROMOTE -check-prefix=SI -check-prefix=FUNC %s6; RUN: llc < %s -show-mc-encoding -mattr=+promote-alloca -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -mtriple=amdgcn-amdhsa -mcpu=tonga -mattr=-unaligned-access-mode | FileCheck -enable-var-scope -check-prefix=SI-PROMOTE-VECT -check-prefix=SI -check-prefix=FUNC %s7; RUN: llc < %s -show-mc-encoding -mattr=-promote-alloca -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -mtriple=amdgcn-amdhsa -mcpu=tonga -mattr=-unaligned-access-mode | FileCheck -enable-var-scope -check-prefix=SI-ALLOCA -check-prefix=SI -check-prefix=FUNC %s8 9; RUN: opt < %s -S -mtriple=amdgcn-unknown-amdhsa -data-layout=A5 -mcpu=kaveri -passes=amdgpu-promote-alloca -disable-promote-alloca-to-vector | FileCheck -enable-var-scope -check-prefix=HSAOPT -check-prefix=OPT %s10; RUN: opt < %s -S -mtriple=amdgcn-unknown-unknown -data-layout=A5 -mcpu=kaveri -passes=amdgpu-promote-alloca -disable-promote-alloca-to-vector | FileCheck -enable-var-scope -check-prefix=NOHSAOPT -check-prefix=OPT %s11 12; RUN: llc < %s -mtriple=r600 -mcpu=cypress -disable-promote-alloca-to-vector | FileCheck %s -check-prefix=R600 -check-prefix=FUNC13; RUN: llc < %s -mtriple=r600 -mcpu=cypress | FileCheck %s -check-prefix=R600-VECT -check-prefix=FUNC14 15; HSAOPT: @mova_same_clause.stack = internal unnamed_addr addrspace(3) global [256 x [5 x i32]] poison, align 416; HSAOPT: @high_alignment.stack = internal unnamed_addr addrspace(3) global [256 x [8 x i32]] poison, align 1617 18 19; FUNC-LABEL: {{^}}mova_same_clause:20; OPT-LABEL: @mova_same_clause(21 22; R600: LDS_WRITE23; R600: LDS_WRITE24; R600: LDS_READ25; R600: LDS_READ26 27; HSA-PROMOTE: .amdhsa_group_segment_fixed_size 512028 29; HSA-PROMOTE: s_load_dwordx2 s[{{[0-9:]+}}], s[4:5], 0x130 31; SI-PROMOTE: ds_write_b3232; SI-PROMOTE: ds_write_b3233; SI-PROMOTE: ds_read_b3234; SI-PROMOTE: ds_read_b3235 36; FIXME: Creating the emergency stack slots causes us to over-estimate scratch37; by 4 bytes.38; HSA-ALLOCA: .amdhsa_private_segment_fixed_size 2439 40; HSA-ALLOCA: s_add_i32 s12, s12, s1741; HSA-ALLOCA-DAG: s_mov_b32 flat_scratch_lo, s1342; HSA-ALLOCA-DAG: s_lshr_b32 flat_scratch_hi, s12, 843 44; SI-ALLOCA: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen ; encoding: [0x00,0x10,0x70,0xe045; SI-ALLOCA: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen ; encoding: [0x00,0x10,0x70,0xe046 47 48; HSAOPT: [[DISPATCH_PTR:%[0-9]+]] = call noalias nonnull dereferenceable(64) ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()49; HSAOPT: [[GEP0:%[0-9]+]] = getelementptr inbounds i32, ptr addrspace(4) [[DISPATCH_PTR]], i64 150; HSAOPT: [[LDXY:%[0-9]+]] = load i32, ptr addrspace(4) [[GEP0]], align 4, !invariant.load !151; HSAOPT: [[GEP1:%[0-9]+]] = getelementptr inbounds i32, ptr addrspace(4) [[DISPATCH_PTR]], i64 252; HSAOPT: [[LDZU:%[0-9]+]] = load i32, ptr addrspace(4) [[GEP1]], align 4, !range !2, !invariant.load !153; HSAOPT: [[EXTRACTY:%[0-9]+]] = lshr i32 [[LDXY]], 1654 55; HSAOPT: [[WORKITEM_ID_X:%[0-9]+]] = call range(i32 0, 256) i32 @llvm.amdgcn.workitem.id.x()56; HSAOPT: [[WORKITEM_ID_Y:%[0-9]+]] = call range(i32 0, 256) i32 @llvm.amdgcn.workitem.id.y()57; HSAOPT: [[WORKITEM_ID_Z:%[0-9]+]] = call range(i32 0, 256) i32 @llvm.amdgcn.workitem.id.z()58 59; HSAOPT: [[Y_SIZE_X_Z_SIZE:%[0-9]+]] = mul nuw nsw i32 [[EXTRACTY]], [[LDZU]]60; HSAOPT: [[YZ_X_XID:%[0-9]+]] = mul i32 [[Y_SIZE_X_Z_SIZE]], [[WORKITEM_ID_X]]61; HSAOPT: [[Y_X_Z_SIZE:%[0-9]+]] = mul nuw nsw i32 [[WORKITEM_ID_Y]], [[LDZU]]62; HSAOPT: [[ADD_YZ_X_X_YZ_SIZE:%[0-9]+]] = add i32 [[YZ_X_XID]], [[Y_X_Z_SIZE]]63; HSAOPT: [[ADD_ZID:%[0-9]+]] = add i32 [[ADD_YZ_X_X_YZ_SIZE]], [[WORKITEM_ID_Z]]64 65; HSAOPT: [[LOCAL_GEP:%[0-9]+]] = getelementptr inbounds [256 x [5 x i32]], ptr addrspace(3) @mova_same_clause.stack, i32 0, i32 [[ADD_ZID]]66; HSAOPT: %arrayidx1 = getelementptr inbounds [5 x i32], ptr addrspace(3) [[LOCAL_GEP]], i32 0, i32 {{%[0-9]+}}67; HSAOPT: %arrayidx3 = getelementptr inbounds [5 x i32], ptr addrspace(3) [[LOCAL_GEP]], i32 0, i32 {{%[0-9]+}}68; HSAOPT: %arrayidx12 = getelementptr inbounds [5 x i32], ptr addrspace(3) [[LOCAL_GEP]], i32 0, i32 169 70 71; NOHSAOPT: call range(i32 0, 257) i32 @llvm.r600.read.local.size.y()72; NOHSAOPT: call range(i32 0, 257) i32 @llvm.r600.read.local.size.z()73; NOHSAOPT: call range(i32 0, 256) i32 @llvm.amdgcn.workitem.id.x()74; NOHSAOPT: call range(i32 0, 256) i32 @llvm.amdgcn.workitem.id.y()75; NOHSAOPT: call range(i32 0, 256) i32 @llvm.amdgcn.workitem.id.z()76define amdgpu_kernel void @mova_same_clause(ptr addrspace(1) nocapture %out, ptr addrspace(1) nocapture %in) #0 {77entry:78 %stack = alloca [5 x i32], align 4, addrspace(5)79 %0 = load i32, ptr addrspace(1) %in, align 480 %arrayidx1 = getelementptr inbounds [5 x i32], ptr addrspace(5) %stack, i32 0, i32 %081 store i32 4, ptr addrspace(5) %arrayidx1, align 482 %arrayidx2 = getelementptr inbounds i32, ptr addrspace(1) %in, i32 183 %1 = load i32, ptr addrspace(1) %arrayidx2, align 484 %arrayidx3 = getelementptr inbounds [5 x i32], ptr addrspace(5) %stack, i32 0, i32 %185 store i32 5, ptr addrspace(5) %arrayidx3, align 486 %2 = load i32, ptr addrspace(5) %stack, align 487 store i32 %2, ptr addrspace(1) %out, align 488 %arrayidx12 = getelementptr inbounds [5 x i32], ptr addrspace(5) %stack, i32 0, i32 189 %3 = load i32, ptr addrspace(5) %arrayidx1290 %arrayidx13 = getelementptr inbounds i32, ptr addrspace(1) %out, i32 191 store i32 %3, ptr addrspace(1) %arrayidx1392 ret void93}94 95; OPT-LABEL: @high_alignment(96; OPT: getelementptr inbounds [256 x [8 x i32]], ptr addrspace(3) @high_alignment.stack, i32 0, i32 %{{[0-9]+}}97define amdgpu_kernel void @high_alignment(ptr addrspace(1) nocapture %out, ptr addrspace(1) nocapture %in) #0 {98entry:99 %stack = alloca [8 x i32], align 16, addrspace(5)100 %0 = load i32, ptr addrspace(1) %in, align 4101 %arrayidx1 = getelementptr inbounds [8 x i32], ptr addrspace(5) %stack, i32 0, i32 %0102 store i32 4, ptr addrspace(5) %arrayidx1, align 4103 %arrayidx2 = getelementptr inbounds i32, ptr addrspace(1) %in, i32 1104 %1 = load i32, ptr addrspace(1) %arrayidx2, align 4105 %arrayidx3 = getelementptr inbounds [8 x i32], ptr addrspace(5) %stack, i32 0, i32 %1106 store i32 5, ptr addrspace(5) %arrayidx3, align 4107 %2 = load i32, ptr addrspace(5) %stack, align 4108 store i32 %2, ptr addrspace(1) %out, align 4109 %arrayidx12 = getelementptr inbounds [8 x i32], ptr addrspace(5) %stack, i32 0, i32 1110 %3 = load i32, ptr addrspace(5) %arrayidx12111 %arrayidx13 = getelementptr inbounds i32, ptr addrspace(1) %out, i32 1112 store i32 %3, ptr addrspace(1) %arrayidx13113 ret void114}115 116; FUNC-LABEL: {{^}}no_replace_inbounds_gep:117; OPT-LABEL: @no_replace_inbounds_gep(118; OPT: alloca [5 x i32]119 120; SI-NOT: ds_write121define amdgpu_kernel void @no_replace_inbounds_gep(ptr addrspace(1) nocapture %out, ptr addrspace(1) nocapture %in) #0 {122entry:123 %stack = alloca [5 x i32], align 4, addrspace(5)124 %0 = load i32, ptr addrspace(1) %in, align 4125 %arrayidx1 = getelementptr [5 x i32], ptr addrspace(5) %stack, i32 0, i32 %0126 store i32 4, ptr addrspace(5) %arrayidx1, align 4127 %arrayidx2 = getelementptr inbounds i32, ptr addrspace(1) %in, i32 1128 %1 = load i32, ptr addrspace(1) %arrayidx2, align 4129 %arrayidx3 = getelementptr inbounds [5 x i32], ptr addrspace(5) %stack, i32 0, i32 %1130 store i32 5, ptr addrspace(5) %arrayidx3, align 4131 %2 = load i32, ptr addrspace(5) %stack, align 4132 store i32 %2, ptr addrspace(1) %out, align 4133 %arrayidx12 = getelementptr inbounds [5 x i32], ptr addrspace(5) %stack, i32 0, i32 1134 %3 = load i32, ptr addrspace(5) %arrayidx12135 %arrayidx13 = getelementptr inbounds i32, ptr addrspace(1) %out, i32 1136 store i32 %3, ptr addrspace(1) %arrayidx13137 ret void138}139 140; This test checks that the stack offset is calculated correctly for structs.141; All register loads/stores should be optimized away, so there shouldn't be142; any MOVA instructions.143;144; XXX: This generated code has unnecessary MOVs, we should be able to optimize145; this.146 147; FUNC-LABEL: {{^}}multiple_structs:148; OPT-LABEL: @multiple_structs(149 150; R600-NOT: MOVA_INT151; SI-NOT: v_movrel152; SI-NOT: v_movrel153%struct.point = type { i32, i32 }154 155define amdgpu_kernel void @multiple_structs(ptr addrspace(1) %out) #0 {156entry:157 %a = alloca %struct.point, addrspace(5)158 %b = alloca %struct.point, addrspace(5)159 %a.y.ptr = getelementptr %struct.point, ptr addrspace(5) %a, i32 0, i32 1160 %b.y.ptr = getelementptr %struct.point, ptr addrspace(5) %b, i32 0, i32 1161 store i32 0, ptr addrspace(5) %a162 store i32 1, ptr addrspace(5) %a.y.ptr163 store i32 2, ptr addrspace(5) %b164 store i32 3, ptr addrspace(5) %b.y.ptr165 %a.indirect = load i32, ptr addrspace(5) %a166 %b.indirect = load i32, ptr addrspace(5) %b167 %0 = add i32 %a.indirect, %b.indirect168 store i32 %0, ptr addrspace(1) %out169 ret void170}171 172; Test direct access of a private array inside a loop. The private array173; loads and stores should be lowered to copies, so there shouldn't be any174; MOVA instructions.175 176; FUNC-LABEL: {{^}}direct_loop:177; R600-NOT: MOVA_INT178; SI-NOT: v_movrel179 180define amdgpu_kernel void @direct_loop(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {181entry:182 %prv_array_const = alloca [2 x i32], addrspace(5)183 %prv_array = alloca [2 x i32], addrspace(5)184 %a = load i32, ptr addrspace(1) %in185 %b_src_ptr = getelementptr inbounds i32, ptr addrspace(1) %in, i32 1186 %b = load i32, ptr addrspace(1) %b_src_ptr187 store i32 %a, ptr addrspace(5) %prv_array_const188 %b_dst_ptr = getelementptr inbounds [2 x i32], ptr addrspace(5) %prv_array_const, i32 0, i32 1189 store i32 %b, ptr addrspace(5) %b_dst_ptr190 br label %for.body191 192for.body:193 %inc = phi i32 [0, %entry], [%count, %for.body]194 %x = load i32, ptr addrspace(5) %prv_array_const195 %y = load i32, ptr addrspace(5) %prv_array196 %xy = add i32 %x, %y197 store i32 %xy, ptr addrspace(5) %prv_array198 %count = add i32 %inc, 1199 %done = icmp eq i32 %count, 4095200 br i1 %done, label %for.end, label %for.body201 202for.end:203 %value = load i32, ptr addrspace(5) %prv_array204 store i32 %value, ptr addrspace(1) %out205 ret void206}207 208; FUNC-LABEL: {{^}}short_array:209 210; R600-VECT: MOVA_INT211 212; SI-ALLOCA-DAG: buffer_store_short v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], 0 offset:2 ; encoding: [0x02,0x00,0x68,0xe0213; SI-ALLOCA-DAG: buffer_store_short v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], 0 ; encoding: [0x00,0x00,0x68,0xe0214; Loaded value is 0 or 1, so sext will become zext, so we get buffer_load_ushort instead of buffer_load_sshort.215; SI-ALLOCA: buffer_load_sshort v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0216 217; SI-PROMOTE-VECT: s_load_dword [[IDX:s[0-9]+]]218; SI-PROMOTE-VECT: s_lshl_b32 [[SCALED_IDX:s[0-9]+]], [[IDX]], 4219; SI-PROMOTE-VECT: s_lshr_b32 [[SREG:s[0-9]+]], 0x10000, [[SCALED_IDX]]220; SI-PROMOTE-VECT: s_and_b32 s{{[0-9]+}}, [[SREG]], 1221define amdgpu_kernel void @short_array(ptr addrspace(1) %out, i32 %index) #0 {222entry:223 %0 = alloca [2 x i16], addrspace(5)224 %1 = getelementptr inbounds [2 x i16], ptr addrspace(5) %0, i32 0, i32 1225 store i16 0, ptr addrspace(5) %0226 store i16 1, ptr addrspace(5) %1227 %2 = getelementptr inbounds [2 x i16], ptr addrspace(5) %0, i32 0, i32 %index228 %3 = load i16, ptr addrspace(5) %2229 %4 = sext i16 %3 to i32230 store i32 %4, ptr addrspace(1) %out231 ret void232}233 234; FUNC-LABEL: {{^}}char_array:235 236; R600-VECT: MOVA_INT237 238; SI-PROMOTE-VECT-DAG: s_lshl_b32239; SI-PROMOTE-VECT-DAG: s_lshr_b32240 241; SI-ALLOCA-DAG: buffer_store_byte v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], 0 ; encoding: [0x00,0x00,0x60,0xe0242; SI-ALLOCA-DAG: buffer_store_byte v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], 0 offset:1 ; encoding: [0x01,0x00,0x60,0xe0243define amdgpu_kernel void @char_array(ptr addrspace(1) %out, i32 %index) #0 {244entry:245 %0 = alloca [2 x i8], addrspace(5)246 %1 = getelementptr inbounds [2 x i8], ptr addrspace(5) %0, i32 0, i32 1247 store i8 0, ptr addrspace(5) %0248 store i8 1, ptr addrspace(5) %1249 %2 = getelementptr inbounds [2 x i8], ptr addrspace(5) %0, i32 0, i32 %index250 %3 = load i8, ptr addrspace(5) %2251 %4 = sext i8 %3 to i32252 store i32 %4, ptr addrspace(1) %out253 ret void254}255 256; Test that two stack objects are not stored in the same register257; The second stack object should be in T3.X258; FUNC-LABEL: {{^}}no_overlap:259;260; A total of 5 bytes should be allocated and used.261; SI-ALLOCA: buffer_store_byte v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], 0 ;262define amdgpu_kernel void @no_overlap(ptr addrspace(1) %out, i32 %in) #0 {263entry:264 %0 = alloca [3 x i8], align 1, addrspace(5)265 %1 = alloca [2 x i8], align 1, addrspace(5)266 %2 = getelementptr [3 x i8], ptr addrspace(5) %0, i32 0, i32 1267 %3 = getelementptr [3 x i8], ptr addrspace(5) %0, i32 0, i32 2268 %4 = getelementptr [2 x i8], ptr addrspace(5) %1, i32 0, i32 1269 store i8 0, ptr addrspace(5) %0270 store i8 1, ptr addrspace(5) %2271 store i8 2, ptr addrspace(5) %3272 store i8 1, ptr addrspace(5) %1273 store i8 0, ptr addrspace(5) %4274 %5 = getelementptr [3 x i8], ptr addrspace(5) %0, i32 0, i32 %in275 %6 = getelementptr [2 x i8], ptr addrspace(5) %1, i32 0, i32 %in276 %7 = load i8, ptr addrspace(5) %5277 %8 = load i8, ptr addrspace(5) %6278 %9 = add i8 %7, %8279 %10 = sext i8 %9 to i32280 store i32 %10, ptr addrspace(1) %out281 ret void282}283 284; FUNC-LABEL: {{^}}char_array_array:285define amdgpu_kernel void @char_array_array(ptr addrspace(1) %out, i32 %index) #0 {286entry:287 %alloca = alloca [2 x [2 x i8]], addrspace(5)288 %gep1 = getelementptr [2 x [2 x i8]], ptr addrspace(5) %alloca, i32 0, i32 0, i32 1289 store i8 0, ptr addrspace(5) %alloca290 store i8 1, ptr addrspace(5) %gep1291 %gep2 = getelementptr [2 x [2 x i8]], ptr addrspace(5) %alloca, i32 0, i32 0, i32 %index292 %load = load i8, ptr addrspace(5) %gep2293 %sext = sext i8 %load to i32294 store i32 %sext, ptr addrspace(1) %out295 ret void296}297 298; FUNC-LABEL: {{^}}i32_array_array:299define amdgpu_kernel void @i32_array_array(ptr addrspace(1) %out, i32 %index) #0 {300entry:301 %alloca = alloca [2 x [2 x i32]], addrspace(5)302 %gep1 = getelementptr [2 x [2 x i32]], ptr addrspace(5) %alloca, i32 0, i32 0, i32 1303 store i32 0, ptr addrspace(5) %alloca304 store i32 1, ptr addrspace(5) %gep1305 %gep2 = getelementptr [2 x [2 x i32]], ptr addrspace(5) %alloca, i32 0, i32 0, i32 %index306 %load = load i32, ptr addrspace(5) %gep2307 store i32 %load, ptr addrspace(1) %out308 ret void309}310 311; FUNC-LABEL: {{^}}i64_array_array:312define amdgpu_kernel void @i64_array_array(ptr addrspace(1) %out, i32 %index) #0 {313entry:314 %alloca = alloca [2 x [2 x i64]], addrspace(5)315 %gep1 = getelementptr [2 x [2 x i64]], ptr addrspace(5) %alloca, i32 0, i32 0, i32 1316 store i64 0, ptr addrspace(5) %alloca317 store i64 1, ptr addrspace(5) %gep1318 %gep2 = getelementptr [2 x [2 x i64]], ptr addrspace(5) %alloca, i32 0, i32 0, i32 %index319 %load = load i64, ptr addrspace(5) %gep2320 store i64 %load, ptr addrspace(1) %out321 ret void322}323 324%struct.pair32 = type { i32, i32 }325; FUNC-LABEL: {{^}}struct_array_array:326define amdgpu_kernel void @struct_array_array(ptr addrspace(1) %out, i32 %index) #0 {327entry:328 %alloca = alloca [2 x [2 x %struct.pair32]], addrspace(5)329 %gep0 = getelementptr [2 x [2 x %struct.pair32]], ptr addrspace(5) %alloca, i32 0, i32 0, i32 0, i32 1330 %gep1 = getelementptr [2 x [2 x %struct.pair32]], ptr addrspace(5) %alloca, i32 0, i32 0, i32 1, i32 1331 store i32 0, ptr addrspace(5) %gep0332 store i32 1, ptr addrspace(5) %gep1333 %gep2 = getelementptr [2 x [2 x %struct.pair32]], ptr addrspace(5) %alloca, i32 0, i32 0, i32 %index, i32 0334 %load = load i32, ptr addrspace(5) %gep2335 store i32 %load, ptr addrspace(1) %out336 ret void337}338 339; FUNC-LABEL: {{^}}struct_pair32_array:340define amdgpu_kernel void @struct_pair32_array(ptr addrspace(1) %out, i32 %index) #0 {341entry:342 %alloca = alloca [2 x %struct.pair32], addrspace(5)343 %gep0 = getelementptr [2 x %struct.pair32], ptr addrspace(5) %alloca, i32 0, i32 0, i32 1344 %gep1 = getelementptr [2 x %struct.pair32], ptr addrspace(5) %alloca, i32 0, i32 1, i32 0345 store i32 0, ptr addrspace(5) %gep0346 store i32 1, ptr addrspace(5) %gep1347 %gep2 = getelementptr [2 x %struct.pair32], ptr addrspace(5) %alloca, i32 0, i32 %index, i32 0348 %load = load i32, ptr addrspace(5) %gep2349 store i32 %load, ptr addrspace(1) %out350 ret void351}352 353; FUNC-LABEL: {{^}}select_private:354define amdgpu_kernel void @select_private(ptr addrspace(1) %out, i32 %in) nounwind {355entry:356 %tmp = alloca [2 x i32], addrspace(5)357 %tmp2 = getelementptr [2 x i32], ptr addrspace(5) %tmp, i32 0, i32 1358 store i32 0, ptr addrspace(5) %tmp359 store i32 1, ptr addrspace(5) %tmp2360 %cmp = icmp eq i32 %in, 0361 %sel = select i1 %cmp, ptr addrspace(5) %tmp, ptr addrspace(5) %tmp2362 %load = load i32, ptr addrspace(5) %sel363 store i32 %load, ptr addrspace(1) %out364 ret void365}366 367; AMDGPUPromoteAlloca does not know how to handle ptrtoint. When it368; finds one, it should stop trying to promote.369 370; FUNC-LABEL: ptrtoint:371; SI-NOT: ds_write372; SI: s_add_i32 [[S_ADD_OFFSET:s[0-9]+]], s{{[0-9]+}}, 5373; SI: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen374; SI: v_mov_b32_e32 [[V_ADD_OFFSET:v[0-9]+]], [[S_ADD_OFFSET]]375; SI: buffer_load_dword v{{[0-9]+}}, [[V_ADD_OFFSET:v[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0 offen ;376define amdgpu_kernel void @ptrtoint(ptr addrspace(1) %out, i32 %a, i32 %b) #0 {377 %alloca = alloca [16 x i32], addrspace(5)378 %tmp0 = getelementptr [16 x i32], ptr addrspace(5) %alloca, i32 0, i32 %a379 store i32 5, ptr addrspace(5) %tmp0380 %tmp1 = ptrtoint ptr addrspace(5) %alloca to i32381 %tmp2 = add i32 %tmp1, 5382 %tmp3 = inttoptr i32 %tmp2 to ptr addrspace(5)383 %tmp4 = getelementptr i32, ptr addrspace(5) %tmp3, i32 %b384 %tmp5 = load i32, ptr addrspace(5) %tmp4385 store i32 %tmp5, ptr addrspace(1) %out386 ret void387}388 389; OPT-LABEL: @pointer_typed_alloca(390; OPT: getelementptr inbounds [256 x ptr addrspace(1)], ptr addrspace(3) @pointer_typed_alloca.A.addr, i32 0, i32 %{{[0-9]+}}391; OPT: load ptr addrspace(1), ptr addrspace(3) %{{[0-9]+}}, align 4392define amdgpu_kernel void @pointer_typed_alloca(ptr addrspace(1) %A) #1 {393entry:394 %A.addr = alloca ptr addrspace(1), align 4, addrspace(5)395 store ptr addrspace(1) %A, ptr addrspace(5) %A.addr, align 4396 %ld0 = load ptr addrspace(1), ptr addrspace(5) %A.addr, align 4397 store i32 1, ptr addrspace(1) %ld0, align 4398 %ld1 = load ptr addrspace(1), ptr addrspace(5) %A.addr, align 4399 %arrayidx1 = getelementptr inbounds i32, ptr addrspace(1) %ld1, i32 1400 store i32 2, ptr addrspace(1) %arrayidx1, align 4401 %ld2 = load ptr addrspace(1), ptr addrspace(5) %A.addr, align 4402 %arrayidx2 = getelementptr inbounds i32, ptr addrspace(1) %ld2, i32 2403 store i32 3, ptr addrspace(1) %arrayidx2, align 4404 ret void405}406 407; FUNC-LABEL: v16i32_stack:408 409; R600: MOVA_INT410; R600: MOVA_INT411; R600: MOVA_INT412; R600: MOVA_INT413; R600: MOVA_INT414; R600: MOVA_INT415; R600: MOVA_INT416; R600: MOVA_INT417; R600: MOVA_INT418; R600: MOVA_INT419; R600: MOVA_INT420; R600: MOVA_INT421; R600: MOVA_INT422; R600: MOVA_INT423; R600: MOVA_INT424; R600: MOVA_INT425 426; SI: buffer_load_dword427; SI: buffer_load_dword428; SI: buffer_load_dword429; SI: buffer_load_dword430; SI: buffer_load_dword431; SI: buffer_load_dword432; SI: buffer_load_dword433; SI: buffer_load_dword434; SI: buffer_load_dword435; SI: buffer_load_dword436; SI: buffer_load_dword437; SI: buffer_load_dword438; SI: buffer_load_dword439; SI: buffer_load_dword440; SI: buffer_load_dword441; SI: buffer_load_dword442 443define amdgpu_kernel void @v16i32_stack(ptr addrspace(1) %out, i32 %a) {444 %alloca = alloca [2 x <16 x i32>], addrspace(5)445 %tmp0 = getelementptr [2 x <16 x i32>], ptr addrspace(5) %alloca, i32 0, i32 %a446 %tmp5 = load <16 x i32>, ptr addrspace(5) %tmp0447 store <16 x i32> %tmp5, ptr addrspace(1) %out448 ret void449}450 451; FUNC-LABEL: v16float_stack:452 453; R600: MOVA_INT454; R600: MOVA_INT455; R600: MOVA_INT456; R600: MOVA_INT457; R600: MOVA_INT458; R600: MOVA_INT459; R600: MOVA_INT460; R600: MOVA_INT461; R600: MOVA_INT462; R600: MOVA_INT463; R600: MOVA_INT464; R600: MOVA_INT465; R600: MOVA_INT466; R600: MOVA_INT467; R600: MOVA_INT468; R600: MOVA_INT469 470; SI: buffer_load_dword471; SI: buffer_load_dword472; SI: buffer_load_dword473; SI: buffer_load_dword474; SI: buffer_load_dword475; SI: buffer_load_dword476; SI: buffer_load_dword477; SI: buffer_load_dword478; SI: buffer_load_dword479; SI: buffer_load_dword480; SI: buffer_load_dword481; SI: buffer_load_dword482; SI: buffer_load_dword483; SI: buffer_load_dword484; SI: buffer_load_dword485; SI: buffer_load_dword486 487define amdgpu_kernel void @v16float_stack(ptr addrspace(1) %out, i32 %a) {488 %alloca = alloca [2 x <16 x float>], addrspace(5)489 %tmp0 = getelementptr [2 x <16 x float>], ptr addrspace(5) %alloca, i32 0, i32 %a490 %tmp5 = load <16 x float>, ptr addrspace(5) %tmp0491 store <16 x float> %tmp5, ptr addrspace(1) %out492 ret void493}494 495; FUNC-LABEL: v2float_stack:496 497; R600: MOVA_INT498; R600: MOVA_INT499 500; SI: buffer_load_dword501; SI: buffer_load_dword502 503define amdgpu_kernel void @v2float_stack(ptr addrspace(1) %out, i32 %a) {504 %alloca = alloca [16 x <2 x float>], addrspace(5)505 %tmp0 = getelementptr [16 x <2 x float>], ptr addrspace(5) %alloca, i32 0, i32 %a506 %tmp5 = load <2 x float>, ptr addrspace(5) %tmp0507 store <2 x float> %tmp5, ptr addrspace(1) %out508 ret void509}510 511; OPT-LABEL: @direct_alloca_read_0xi32(512; OPT: store [0 x i32] poison, ptr addrspace(3)513; OPT: load [0 x i32], ptr addrspace(3)514define amdgpu_kernel void @direct_alloca_read_0xi32(ptr addrspace(1) %out, i32 %index) {515entry:516 %tmp = alloca [0 x i32], addrspace(5)517 store [0 x i32] [], ptr addrspace(5) %tmp518 %load = load [0 x i32], ptr addrspace(5) %tmp519 store [0 x i32] %load, ptr addrspace(1) %out520 ret void521}522 523; OPT-LABEL: @direct_alloca_read_1xi32(524; OPT: store [1 x i32] zeroinitializer, ptr addrspace(3)525; OPT: load [1 x i32], ptr addrspace(3)526define amdgpu_kernel void @direct_alloca_read_1xi32(ptr addrspace(1) %out, i32 %index) {527entry:528 %tmp = alloca [1 x i32], addrspace(5)529 store [1 x i32] [i32 0], ptr addrspace(5) %tmp530 %load = load [1 x i32], ptr addrspace(5) %tmp531 store [1 x i32] %load, ptr addrspace(1) %out532 ret void533}534 535attributes #0 = { nounwind "amdgpu-waves-per-eu"="1,2" "amdgpu-flat-work-group-size"="1,256" }536attributes #1 = { nounwind "amdgpu-flat-work-group-size"="1,256" }537 538!llvm.module.flags = !{!99}539!99 = !{i32 1, !"amdhsa_code_object_version", i32 400}540 541; HSAOPT: !1 = !{}542