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1; RUN: llc -mtriple=amdgcn < %s | FileCheck --check-prefixes=SI-NOHSA,GCN-NOHSA,FUNC %s2; RUN: llc -global-isel -mtriple=amdgcn < %s | FileCheck --check-prefixes=SI-NOHSA,GCN-NOHSA,FUNC %s3 4; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck --check-prefixes=VI-NOHSA,GCN-NOHSA,FUNC %s5; RUN: llc -global-isel -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck --check-prefixes=VI-NOHSA,GCN-NOHSA,FUNC %s6 7; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck --check-prefixes=EG,FUNC %s8 9; Legacy intrinsics that just read implicit parameters10 11; FUNC-LABEL: {{^}}ngroups_x:12; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[4:5], 0x013; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[4:5], 0x014; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]15; GCN-NOHSA: buffer_store_dword [[VVAL]]16 17; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]18; EG: MOV {{\*? *}}[[VAL]], KC0[0].X19define amdgpu_kernel void @ngroups_x (ptr addrspace(1) %out) {20entry:21 %0 = call i32 @llvm.r600.read.ngroups.x() #022 store i32 %0, ptr addrspace(1) %out23 ret void24}25 26; FUNC-LABEL: {{^}}ngroups_y:27; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[4:5], 0x128; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[4:5], 0x429; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]30; GCN-NOHSA: buffer_store_dword [[VVAL]]31 32; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]33; EG: MOV {{\*? *}}[[VAL]], KC0[0].Y34define amdgpu_kernel void @ngroups_y (ptr addrspace(1) %out) {35entry:36 %0 = call i32 @llvm.r600.read.ngroups.y() #037 store i32 %0, ptr addrspace(1) %out38 ret void39}40 41; FUNC-LABEL: {{^}}ngroups_z:42; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[4:5], 0x243; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[4:5], 0x844; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]45; GCN-NOHSA: buffer_store_dword [[VVAL]]46 47; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]48; EG: MOV {{\*? *}}[[VAL]], KC0[0].Z49define amdgpu_kernel void @ngroups_z (ptr addrspace(1) %out) {50entry:51 %0 = call i32 @llvm.r600.read.ngroups.z() #052 store i32 %0, ptr addrspace(1) %out53 ret void54}55 56; FUNC-LABEL: {{^}}local_size_x:57; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[4:5], 0x658; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[4:5], 0x1859; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]60; GCN-NOHSA: buffer_store_dword [[VVAL]]61 62; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]63; EG: MOV {{\*? *}}[[VAL]], KC0[1].Z64define amdgpu_kernel void @local_size_x (ptr addrspace(1) %out) {65entry:66 %0 = call i32 @llvm.r600.read.local.size.x() #067 store i32 %0, ptr addrspace(1) %out68 ret void69}70 71; FUNC-LABEL: {{^}}local_size_y:72; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[4:5], 0x773; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[4:5], 0x1c74; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]75; GCN-NOHSA: buffer_store_dword [[VVAL]]76 77; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]78; EG: MOV {{\*? *}}[[VAL]], KC0[1].W79define amdgpu_kernel void @local_size_y (ptr addrspace(1) %out) {80entry:81 %0 = call i32 @llvm.r600.read.local.size.y() #082 store i32 %0, ptr addrspace(1) %out83 ret void84}85 86; FUNC-LABEL: {{^}}local_size_z:87; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[4:5], 0x888; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[4:5], 0x2089; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]90; GCN-NOHSA: buffer_store_dword [[VVAL]]91 92; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]93; EG: MOV {{\*? *}}[[VAL]], KC0[2].X94define amdgpu_kernel void @local_size_z (ptr addrspace(1) %out) {95entry:96 %0 = call i32 @llvm.r600.read.local.size.z() #097 store i32 %0, ptr addrspace(1) %out98 ret void99}100 101declare i32 @llvm.r600.read.ngroups.x() #0102declare i32 @llvm.r600.read.ngroups.y() #0103declare i32 @llvm.r600.read.ngroups.z() #0104 105declare i32 @llvm.r600.read.local.size.x() #0106declare i32 @llvm.r600.read.local.size.y() #0107declare i32 @llvm.r600.read.local.size.z() #0108 109attributes #0 = { readnone }110