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1; RUN: llc -mtriple=amdgcn--amdpal < %s | FileCheck -check-prefix=GCN %s2; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga < %s | FileCheck -check-prefix=GCN %s3; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN -enable-var-scope %s4 5; This pixel shader does not use the result of its interpolation, so it would6; end up with an interpolation mode set in PSAddr but not PSEnable. This test tests7; the workaround that ensures that an interpolation mode is also set in PSEnable.8; GCN-LABEL: {{^}}amdpal_psenable:9; GCN: .amdgpu_pal_metadata10; GCN: '0xa1b3 (SPI_PS_INPUT_ENA)': 0x211; GCN: '0xa1b4 (SPI_PS_INPUT_ADDR)': 0x212define amdgpu_ps void @amdpal_psenable(i32 inreg, i32 inreg, i32 inreg, i32 inreg %m0, <2 x float> %pos) #6 {13 %inst23 = extractelement <2 x float> %pos, i32 014 %inst24 = extractelement <2 x float> %pos, i32 115 %inst25 = tail call float @llvm.amdgcn.interp.p1(float %inst23, i32 0, i32 0, i32 %m0)16 %inst26 = tail call float @llvm.amdgcn.interp.p2(float %inst25, float %inst24, i32 0, i32 0, i32 %m0)17 ret void18}19 20declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #221declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #222 23attributes #6 = { nounwind "InitialPSInputAddr"="2" }24 25; Force MsgPack format metadata26!amdgpu.pal.metadata.msgpack = !{!0}27!0 = !{!""}28