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1; RUN: llc -mtriple=amdgcn--amdpal < %s | FileCheck -check-prefix=GCN %s2; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga < %s | FileCheck -check-prefix=GCN %s3; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN -enable-var-scope %s4 5; This pixel shader does not use the result of its interpolation, so it would6; end up with an interpolation mode set in PSAddr but not PSEnable. This test tests7; the workaround that ensures that an interpolation mode is also set in PSEnable.8; GCN-LABEL: {{^}}amdpal_psenable:9; GCN: .amdgpu_pal_metadata10; GCN-NEXT: ---11; GCN-NEXT: amdpal.pipelines:12; GCN-NEXT: - .hardware_stages:13; GCN-NEXT: .ps:14; GCN-NEXT: .entry_point: _amdgpu_ps_main15; GCN-NEXT: .entry_point_symbol: amdpal_psenable16; GCN-NEXT: .scratch_memory_size: 017; GCN: .registers:18; GCN-NEXT: '0x2c0a (SPI_SHADER_PGM_RSRC1_PS)':19; GCN-NEXT: '0x2c0b (SPI_SHADER_PGM_RSRC2_PS)':20; GCN-NEXT: '0xa1b3 (SPI_PS_INPUT_ENA)': 0x221; GCN-NEXT: '0xa1b4 (SPI_PS_INPUT_ADDR)': 0x222; GCN-NEXT: ...23; GCN-NEXT: .end_amdgpu_pal_metadata24define amdgpu_ps void @amdpal_psenable(i32 inreg, i32 inreg, i32 inreg, i32 inreg %m0, <2 x float> %pos) #6 {25 %inst23 = extractelement <2 x float> %pos, i32 026 %inst24 = extractelement <2 x float> %pos, i32 127 %inst25 = tail call float @llvm.amdgcn.interp.p1(float %inst23, i32 0, i32 0, i32 %m0)28 %inst26 = tail call float @llvm.amdgcn.interp.p2(float %inst25, float %inst24, i32 0, i32 0, i32 %m0)29 ret void30}31 32declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #233declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #234 35attributes #6 = { nounwind "InitialPSInputAddr"="2" }36