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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG %s3 4 5define amdgpu_kernel void @test2(ptr addrspace(1) %out, ptr addrspace(1) %in) {6; EG-LABEL: test2:7; EG: ; %bb.0:8; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]9; EG-NEXT: TEX 0 @610; EG-NEXT: ALU 3, @9, KC0[CB0:0-32], KC1[]11; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 112; EG-NEXT: CF_END13; EG-NEXT: PAD14; EG-NEXT: Fetch clause starting at 6:15; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #116; EG-NEXT: ALU clause starting at 8:17; EG-NEXT: MOV * T0.X, KC0[2].Z,18; EG-NEXT: ALU clause starting at 9:19; EG-NEXT: AND_INT * T0.Y, T0.Y, T0.W,20; EG-NEXT: AND_INT T0.X, T0.X, T0.Z,21; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,22; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)23 %b_ptr = getelementptr <2 x i32>, ptr addrspace(1) %in, i32 124 %a = load <2 x i32>, ptr addrspace(1) %in25 %b = load <2 x i32>, ptr addrspace(1) %b_ptr26 %result = and <2 x i32> %a, %b27 store <2 x i32> %result, ptr addrspace(1) %out28 ret void29}30 31define amdgpu_kernel void @test4(ptr addrspace(1) %out, ptr addrspace(1) %in) {32; EG-LABEL: test4:33; EG: ; %bb.0:34; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[]35; EG-NEXT: TEX 1 @636; EG-NEXT: ALU 5, @11, KC0[CB0:0-32], KC1[]37; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 138; EG-NEXT: CF_END39; EG-NEXT: PAD40; EG-NEXT: Fetch clause starting at 6:41; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 16, #142; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #143; EG-NEXT: ALU clause starting at 10:44; EG-NEXT: MOV * T0.X, KC0[2].Z,45; EG-NEXT: ALU clause starting at 11:46; EG-NEXT: AND_INT * T0.W, T0.W, T1.W,47; EG-NEXT: AND_INT * T0.Z, T0.Z, T1.Z,48; EG-NEXT: AND_INT * T0.Y, T0.Y, T1.Y,49; EG-NEXT: AND_INT T0.X, T0.X, T1.X,50; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,51; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)52 %b_ptr = getelementptr <4 x i32>, ptr addrspace(1) %in, i32 153 %a = load <4 x i32>, ptr addrspace(1) %in54 %b = load <4 x i32>, ptr addrspace(1) %b_ptr55 %result = and <4 x i32> %a, %b56 store <4 x i32> %result, ptr addrspace(1) %out57 ret void58}59 60define amdgpu_kernel void @s_and_i32(ptr addrspace(1) %out, i32 %a, i32 %b) {61; EG-LABEL: s_and_i32:62; EG: ; %bb.0:63; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]64; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 165; EG-NEXT: CF_END66; EG-NEXT: PAD67; EG-NEXT: ALU clause starting at 4:68; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x,69; EG-NEXT: AND_INT * T1.X, KC0[2].Z, KC0[2].W,70; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)71 %and = and i32 %a, %b72 store i32 %and, ptr addrspace(1) %out, align 473 ret void74}75 76define amdgpu_kernel void @s_and_constant_i32(ptr addrspace(1) %out, i32 %a) {77; EG-LABEL: s_and_constant_i32:78; EG: ; %bb.0:79; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]80; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 181; EG-NEXT: CF_END82; EG-NEXT: PAD83; EG-NEXT: ALU clause starting at 4:84; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x,85; EG-NEXT: AND_INT * T1.X, KC0[2].Z, literal.y,86; EG-NEXT: 2(2.802597e-45), 1234567(1.729997e-39)87 %and = and i32 %a, 123456788 store i32 %and, ptr addrspace(1) %out, align 489 ret void90}91 92; FIXME: We should really duplicate the constant so that the SALU use93; can fold into the s_and_b32 and the VALU one is materialized94; directly without copying from the SGPR.95 96; Second use is a VGPR use of the constant.97 98define amdgpu_kernel void @s_and_multi_use_constant_i32_0(ptr addrspace(1) %out, i32 %a, i32 %b) {99; EG-LABEL: s_and_multi_use_constant_i32_0:100; EG: ; %bb.0:101; EG-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[]102; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T2.X, 0103; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T2.X, 1104; EG-NEXT: CF_END105; EG-NEXT: ALU clause starting at 4:106; EG-NEXT: MOV T0.X, literal.x,107; EG-NEXT: AND_INT * T0.W, KC0[2].Z, literal.x,108; EG-NEXT: 1234567(1.729997e-39), 0(0.000000e+00)109; EG-NEXT: ADD_INT T1.X, PV.W, KC0[2].W,110; EG-NEXT: LSHR * T2.X, KC0[2].Y, literal.x,111; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)112 %and = and i32 %a, 1234567113 114 ; Just to stop future replacement of copy to vgpr + store with VALU op.115 %foo = add i32 %and, %b116 store volatile i32 %foo, ptr addrspace(1) %out117 store volatile i32 1234567, ptr addrspace(1) %out118 ret void119}120 121; Second use is another SGPR use of the constant.122 123define amdgpu_kernel void @s_and_multi_use_constant_i32_1(ptr addrspace(1) %out, i32 %a, i32 %b) {124; EG-LABEL: s_and_multi_use_constant_i32_1:125; EG: ; %bb.0:126; EG-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[]127; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1128; EG-NEXT: CF_END129; EG-NEXT: PAD130; EG-NEXT: ALU clause starting at 4:131; EG-NEXT: AND_INT * T0.W, KC0[2].Z, literal.x,132; EG-NEXT: 1234567(1.729997e-39), 0(0.000000e+00)133; EG-NEXT: ADD_INT * T0.W, PV.W, KC0[2].W,134; EG-NEXT: ADD_INT T0.X, PV.W, literal.x,135; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,136; EG-NEXT: 1234567(1.729997e-39), 2(2.802597e-45)137 %and = and i32 %a, 1234567138 %foo = add i32 %and, 1234567139 %bar = add i32 %foo, %b140 store volatile i32 %bar, ptr addrspace(1) %out141 ret void142}143 144define amdgpu_kernel void @v_and_i32_vgpr_vgpr(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) {145; EG-LABEL: v_and_i32_vgpr_vgpr:146; EG: ; %bb.0:147; EG-NEXT: ALU 3, @10, KC0[CB0:0-32], KC1[]148; EG-NEXT: TEX 1 @6149; EG-NEXT: ALU 3, @14, KC0[CB0:0-32], KC1[]150; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1151; EG-NEXT: CF_END152; EG-NEXT: PAD153; EG-NEXT: Fetch clause starting at 6:154; EG-NEXT: VTX_READ_32 T1.X, T1.X, 0, #1155; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1156; EG-NEXT: ALU clause starting at 10:157; EG-NEXT: LSHL * T0.W, T0.X, literal.x,158; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)159; EG-NEXT: ADD_INT T0.X, KC0[2].Z, PV.W,160; EG-NEXT: ADD_INT * T1.X, KC0[2].W, PV.W,161; EG-NEXT: ALU clause starting at 14:162; EG-NEXT: AND_INT T0.X, T0.X, T1.X,163; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, T0.W,164; EG-NEXT: LSHR * T1.X, PV.W, literal.x,165; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)166 %tid = call i32 @llvm.amdgcn.workitem.id.x() #0167 %gep.a = getelementptr i32, ptr addrspace(1) %aptr, i32 %tid168 %gep.b = getelementptr i32, ptr addrspace(1) %bptr, i32 %tid169 %gep.out = getelementptr i32, ptr addrspace(1) %out, i32 %tid170 %a = load i32, ptr addrspace(1) %gep.a171 %b = load i32, ptr addrspace(1) %gep.b172 %and = and i32 %a, %b173 store i32 %and, ptr addrspace(1) %gep.out174 ret void175}176 177define amdgpu_kernel void @v_and_i32_sgpr_vgpr(ptr addrspace(1) %out, i32 %a, ptr addrspace(1) %bptr) {178; EG-LABEL: v_and_i32_sgpr_vgpr:179; EG: ; %bb.0:180; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]181; EG-NEXT: TEX 0 @6182; EG-NEXT: ALU 3, @11, KC0[CB0:0-32], KC1[]183; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1184; EG-NEXT: CF_END185; EG-NEXT: PAD186; EG-NEXT: Fetch clause starting at 6:187; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1188; EG-NEXT: ALU clause starting at 8:189; EG-NEXT: LSHL * T0.W, T0.X, literal.x,190; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)191; EG-NEXT: ADD_INT * T0.X, KC0[2].W, PV.W,192; EG-NEXT: ALU clause starting at 11:193; EG-NEXT: AND_INT T0.X, KC0[2].Z, T0.X,194; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, T0.W,195; EG-NEXT: LSHR * T1.X, PV.W, literal.x,196; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)197 %tid = call i32 @llvm.amdgcn.workitem.id.x() #0198 %gep.b = getelementptr i32, ptr addrspace(1) %bptr, i32 %tid199 %gep.out = getelementptr i32, ptr addrspace(1) %out, i32 %tid200 %b = load i32, ptr addrspace(1) %gep.b201 %and = and i32 %a, %b202 store i32 %and, ptr addrspace(1) %gep.out203 ret void204}205 206define amdgpu_kernel void @v_and_i32_vgpr_sgpr(ptr addrspace(1) %out, ptr addrspace(1) %aptr, i32 %b) {207; EG-LABEL: v_and_i32_vgpr_sgpr:208; EG: ; %bb.0:209; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]210; EG-NEXT: TEX 0 @6211; EG-NEXT: ALU 3, @11, KC0[CB0:0-32], KC1[]212; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1213; EG-NEXT: CF_END214; EG-NEXT: PAD215; EG-NEXT: Fetch clause starting at 6:216; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1217; EG-NEXT: ALU clause starting at 8:218; EG-NEXT: LSHL * T0.W, T0.X, literal.x,219; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)220; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,221; EG-NEXT: ALU clause starting at 11:222; EG-NEXT: AND_INT T0.X, T0.X, KC0[2].W,223; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, T0.W,224; EG-NEXT: LSHR * T1.X, PV.W, literal.x,225; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)226 %tid = call i32 @llvm.amdgcn.workitem.id.x() #0227 %gep.a = getelementptr i32, ptr addrspace(1) %aptr, i32 %tid228 %gep.out = getelementptr i32, ptr addrspace(1) %out, i32 %tid229 %a = load i32, ptr addrspace(1) %gep.a230 %and = and i32 %a, %b231 store i32 %and, ptr addrspace(1) %gep.out232 ret void233}234 235define amdgpu_kernel void @v_and_constant_i32(ptr addrspace(1) %out, ptr addrspace(1) %aptr) {236; EG-LABEL: v_and_constant_i32:237; EG: ; %bb.0:238; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]239; EG-NEXT: TEX 0 @6240; EG-NEXT: ALU 2, @11, KC0[CB0:0-32], KC1[]241; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1242; EG-NEXT: CF_END243; EG-NEXT: PAD244; EG-NEXT: Fetch clause starting at 6:245; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1246; EG-NEXT: ALU clause starting at 8:247; EG-NEXT: LSHL * T0.W, T0.X, literal.x,248; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)249; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,250; EG-NEXT: ALU clause starting at 11:251; EG-NEXT: AND_INT T0.X, T0.X, literal.x,252; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,253; EG-NEXT: 1234567(1.729997e-39), 2(2.802597e-45)254 %tid = call i32 @llvm.amdgcn.workitem.id.x() #0255 %gep = getelementptr i32, ptr addrspace(1) %aptr, i32 %tid256 %a = load i32, ptr addrspace(1) %gep, align 4257 %and = and i32 %a, 1234567258 store i32 %and, ptr addrspace(1) %out, align 4259 ret void260}261 262define amdgpu_kernel void @v_and_inline_imm_64_i32(ptr addrspace(1) %out, ptr addrspace(1) %aptr) {263; EG-LABEL: v_and_inline_imm_64_i32:264; EG: ; %bb.0:265; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]266; EG-NEXT: TEX 0 @6267; EG-NEXT: ALU 2, @11, KC0[CB0:0-32], KC1[]268; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1269; EG-NEXT: CF_END270; EG-NEXT: PAD271; EG-NEXT: Fetch clause starting at 6:272; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1273; EG-NEXT: ALU clause starting at 8:274; EG-NEXT: LSHL * T0.W, T0.X, literal.x,275; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)276; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,277; EG-NEXT: ALU clause starting at 11:278; EG-NEXT: AND_INT T0.X, T0.X, literal.x,279; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,280; EG-NEXT: 64(8.968310e-44), 2(2.802597e-45)281 %tid = call i32 @llvm.amdgcn.workitem.id.x() #0282 %gep = getelementptr i32, ptr addrspace(1) %aptr, i32 %tid283 %a = load i32, ptr addrspace(1) %gep, align 4284 %and = and i32 %a, 64285 store i32 %and, ptr addrspace(1) %out, align 4286 ret void287}288 289define amdgpu_kernel void @v_and_inline_imm_neg_16_i32(ptr addrspace(1) %out, ptr addrspace(1) %aptr) {290; EG-LABEL: v_and_inline_imm_neg_16_i32:291; EG: ; %bb.0:292; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]293; EG-NEXT: TEX 0 @6294; EG-NEXT: ALU 2, @11, KC0[CB0:0-32], KC1[]295; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1296; EG-NEXT: CF_END297; EG-NEXT: PAD298; EG-NEXT: Fetch clause starting at 6:299; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1300; EG-NEXT: ALU clause starting at 8:301; EG-NEXT: LSHL * T0.W, T0.X, literal.x,302; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)303; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,304; EG-NEXT: ALU clause starting at 11:305; EG-NEXT: AND_INT T0.X, T0.X, literal.x,306; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,307; EG-NEXT: -16(nan), 2(2.802597e-45)308 %tid = call i32 @llvm.amdgcn.workitem.id.x() #0309 %gep = getelementptr i32, ptr addrspace(1) %aptr, i32 %tid310 %a = load i32, ptr addrspace(1) %gep, align 4311 %and = and i32 %a, -16312 store i32 %and, ptr addrspace(1) %out, align 4313 ret void314}315 316define amdgpu_kernel void @s_and_i64(ptr addrspace(1) %out, i64 %a, i64 %b) {317; EG-LABEL: s_and_i64:318; EG: ; %bb.0:319; EG-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]320; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1321; EG-NEXT: CF_END322; EG-NEXT: PAD323; EG-NEXT: ALU clause starting at 4:324; EG-NEXT: AND_INT * T0.Y, KC0[3].X, KC0[3].Z,325; EG-NEXT: AND_INT * T0.X, KC0[2].W, KC0[3].Y,326; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,327; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)328 %and = and i64 %a, %b329 store i64 %and, ptr addrspace(1) %out, align 8330 ret void331}332 333define amdgpu_kernel void @s_and_i1(ptr addrspace(1) %out, i1 %a, i1 %b) {334; EG-LABEL: s_and_i1:335; EG: ; %bb.0:336; EG-NEXT: ALU 0, @10, KC0[], KC1[]337; EG-NEXT: TEX 1 @6338; EG-NEXT: ALU 12, @11, KC0[CB0:0-32], KC1[]339; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X340; EG-NEXT: CF_END341; EG-NEXT: PAD342; EG-NEXT: Fetch clause starting at 6:343; EG-NEXT: VTX_READ_8 T1.X, T0.X, 40, #3344; EG-NEXT: VTX_READ_8 T0.X, T0.X, 41, #3345; EG-NEXT: ALU clause starting at 10:346; EG-NEXT: MOV * T0.X, 0.0,347; EG-NEXT: ALU clause starting at 11:348; EG-NEXT: AND_INT T0.W, KC0[2].Y, literal.x,349; EG-NEXT: AND_INT * T1.W, T1.X, T0.X,350; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)351; EG-NEXT: AND_INT T1.W, PS, 1,352; EG-NEXT: LSHL * T0.W, PV.W, literal.x,353; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)354; EG-NEXT: LSHL T0.X, PV.W, PS,355; EG-NEXT: LSHL * T0.W, literal.x, PS,356; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)357; EG-NEXT: MOV T0.Y, 0.0,358; EG-NEXT: MOV * T0.Z, 0.0,359; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,360; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)361 %and = and i1 %a, %b362 store i1 %and, ptr addrspace(1) %out363 ret void364}365 366define amdgpu_kernel void @s_and_constant_i64(ptr addrspace(1) %out, i64 %a) {367; EG-LABEL: s_and_constant_i64:368; EG: ; %bb.0:369; EG-NEXT: ALU 4, @4, KC0[CB0:0-32], KC1[]370; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1371; EG-NEXT: CF_END372; EG-NEXT: PAD373; EG-NEXT: ALU clause starting at 4:374; EG-NEXT: AND_INT * T0.Y, KC0[3].X, literal.x,375; EG-NEXT: 128(1.793662e-43), 0(0.000000e+00)376; EG-NEXT: AND_INT T0.X, KC0[2].W, literal.x,377; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,378; EG-NEXT: 524288(7.346840e-40), 2(2.802597e-45)379 %and = and i64 %a, 549756338176380 store i64 %and, ptr addrspace(1) %out, align 8381 ret void382}383 384define amdgpu_kernel void @s_and_multi_use_constant_i64(ptr addrspace(1) %out, i64 %a, i64 %b) {385; EG-LABEL: s_and_multi_use_constant_i64:386; EG: ; %bb.0:387; EG-NEXT: ALU 10, @6, KC0[CB0:0-32], KC1[]388; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T5.X, T4.X, 0389; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T3.X, T2.X, 0390; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T2.X, 0391; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T4.X, 1392; EG-NEXT: CF_END393; EG-NEXT: ALU clause starting at 6:394; EG-NEXT: AND_INT T0.X, KC0[3].Y, literal.x,395; EG-NEXT: AND_INT * T1.X, KC0[3].Z, literal.y,396; EG-NEXT: 524288(7.346840e-40), 128(1.793662e-43)397; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,398; EG-NEXT: 4(5.605194e-45), 0(0.000000e+00)399; EG-NEXT: LSHR T2.X, PV.W, literal.x,400; EG-NEXT: AND_INT * T3.X, KC0[3].X, literal.y,401; EG-NEXT: 2(2.802597e-45), 128(1.793662e-43)402; EG-NEXT: LSHR T4.X, KC0[2].Y, literal.x,403; EG-NEXT: AND_INT * T5.X, KC0[2].W, literal.y,404; EG-NEXT: 2(2.802597e-45), 524288(7.346840e-40)405 %and0 = and i64 %a, 549756338176406 %and1 = and i64 %b, 549756338176407 store volatile i64 %and0, ptr addrspace(1) %out408 store volatile i64 %and1, ptr addrspace(1) %out409 ret void410}411 412define amdgpu_kernel void @s_and_32_bit_constant_i64(ptr addrspace(1) %out, i32, i64 %a) {413; EG-LABEL: s_and_32_bit_constant_i64:414; EG: ; %bb.0:415; EG-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]416; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1417; EG-NEXT: CF_END418; EG-NEXT: PAD419; EG-NEXT: ALU clause starting at 4:420; EG-NEXT: AND_INT T0.X, KC0[2].W, literal.x,421; EG-NEXT: MOV T0.Y, 0.0,422; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,423; EG-NEXT: 1234567(1.729997e-39), 2(2.802597e-45)424 %and = and i64 %a, 1234567425 store i64 %and, ptr addrspace(1) %out, align 8426 ret void427}428 429define amdgpu_kernel void @s_and_multi_use_inline_imm_i64(ptr addrspace(1) %out, i32, i64 %a, i32, i64 %b, i32, i64 %c) {430; EG-LABEL: s_and_multi_use_inline_imm_i64:431; EG: ; %bb.0:432; EG-NEXT: ALU 17, @6, KC0[CB0:0-32], KC1[]433; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.X, T5.X, 0434; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.X, T3.X, 0435; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T3.X, 0436; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T5.X, 1437; EG-NEXT: CF_END438; EG-NEXT: ALU clause starting at 6:439; EG-NEXT: LSHL T0.W, KC0[3].W, 1,440; EG-NEXT: LSHL * T1.W, KC0[2].W, 1,441; EG-NEXT: AND_INT * T0.W, PV.W, literal.x,442; EG-NEXT: 62(8.688050e-44), 0(0.000000e+00)443; EG-NEXT: ADD_INT T0.X, PV.W, KC0[4].W,444; EG-NEXT: AND_INT T1.W, T1.W, literal.x,445; EG-NEXT: ADDC_UINT * T0.W, PV.W, KC0[4].W,446; EG-NEXT: 62(8.688050e-44), 0(0.000000e+00)447; EG-NEXT: ADD_INT T1.X, KC0[5].X, PS,448; EG-NEXT: ADDC_UINT * T0.W, PV.W, KC0[4].W,449; EG-NEXT: ADD_INT T2.X, KC0[5].X, PV.W,450; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,451; EG-NEXT: 4(5.605194e-45), 0(0.000000e+00)452; EG-NEXT: LSHR T3.X, PV.W, literal.x,453; EG-NEXT: ADD_INT * T4.X, T1.W, KC0[4].W,454; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)455; EG-NEXT: LSHR * T5.X, KC0[2].Y, literal.x,456; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)457 %shl.a = shl i64 %a, 1458 %shl.b = shl i64 %b, 1459 %and0 = and i64 %shl.a, 62460 %and1 = and i64 %shl.b, 62461 %add0 = add i64 %and0, %c462 %add1 = add i64 %and1, %c463 store volatile i64 %add0, ptr addrspace(1) %out464 store volatile i64 %add1, ptr addrspace(1) %out465 ret void466}467 468define amdgpu_kernel void @v_and_i64(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) {469; EG-LABEL: v_and_i64:470; EG: ; %bb.0:471; EG-NEXT: ALU 3, @10, KC0[CB0:0-32], KC1[]472; EG-NEXT: TEX 1 @6473; EG-NEXT: ALU 3, @14, KC0[CB0:0-32], KC1[]474; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1475; EG-NEXT: CF_END476; EG-NEXT: PAD477; EG-NEXT: Fetch clause starting at 6:478; EG-NEXT: VTX_READ_64 T1.XY, T1.X, 0, #1479; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #1480; EG-NEXT: ALU clause starting at 10:481; EG-NEXT: LSHL * T0.W, T0.X, literal.x,482; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)483; EG-NEXT: ADD_INT T0.X, KC0[2].Z, PV.W,484; EG-NEXT: ADD_INT * T1.X, KC0[2].W, PV.W,485; EG-NEXT: ALU clause starting at 14:486; EG-NEXT: AND_INT * T0.Y, T0.Y, T1.Y,487; EG-NEXT: AND_INT T0.X, T0.X, T1.X,488; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,489; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)490 %tid = call i32 @llvm.amdgcn.workitem.id.x() #0491 %gep.a = getelementptr i64, ptr addrspace(1) %aptr, i32 %tid492 %a = load i64, ptr addrspace(1) %gep.a, align 8493 %gep.b = getelementptr i64, ptr addrspace(1) %bptr, i32 %tid494 %b = load i64, ptr addrspace(1) %gep.b, align 8495 %and = and i64 %a, %b496 store i64 %and, ptr addrspace(1) %out, align 8497 ret void498}499 500define amdgpu_kernel void @v_and_constant_i64(ptr addrspace(1) %out, ptr addrspace(1) %aptr) {501; EG-LABEL: v_and_constant_i64:502; EG: ; %bb.0:503; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]504; EG-NEXT: TEX 0 @6505; EG-NEXT: ALU 4, @11, KC0[CB0:0-32], KC1[]506; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1507; EG-NEXT: CF_END508; EG-NEXT: PAD509; EG-NEXT: Fetch clause starting at 6:510; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #1511; EG-NEXT: ALU clause starting at 8:512; EG-NEXT: LSHL * T0.W, T0.X, literal.x,513; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)514; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,515; EG-NEXT: ALU clause starting at 11:516; EG-NEXT: AND_INT * T0.Y, T0.Y, literal.x,517; EG-NEXT: 286(4.007714e-43), 0(0.000000e+00)518; EG-NEXT: AND_INT T0.X, T0.X, literal.x,519; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,520; EG-NEXT: -1424379385(-5.460358e-13), 2(2.802597e-45)521 %tid = call i32 @llvm.amdgcn.workitem.id.x() #0522 %gep.a = getelementptr i64, ptr addrspace(1) %aptr, i32 %tid523 %a = load i64, ptr addrspace(1) %gep.a, align 8524 %and = and i64 %a, 1231231234567525 store i64 %and, ptr addrspace(1) %out, align 8526 ret void527}528 529define amdgpu_kernel void @v_and_multi_use_constant_i64(ptr addrspace(1) %out, ptr addrspace(1) %aptr) {530; EG-LABEL: v_and_multi_use_constant_i64:531; EG: ; %bb.0:532; EG-NEXT: ALU 1, @20, KC0[CB0:0-32], KC1[]533; EG-NEXT: TEX 0 @12534; EG-NEXT: ALU 0, @22, KC0[], KC1[]535; EG-NEXT: TEX 0 @14536; EG-NEXT: ALU 0, @23, KC0[], KC1[]537; EG-NEXT: TEX 1 @16538; EG-NEXT: ALU 10, @24, KC0[CB0:0-32], KC1[]539; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T5.X, 0540; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.X, T4.X, 0541; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T3.X, T5.X, 0542; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T4.X, 1543; EG-NEXT: CF_END544; EG-NEXT: Fetch clause starting at 12:545; EG-NEXT: VTX_READ_32 T1.X, T1.X, 4, #1546; EG-NEXT: Fetch clause starting at 14:547; EG-NEXT: VTX_READ_32 T2.X, T2.X, 0, #1548; EG-NEXT: Fetch clause starting at 16:549; EG-NEXT: VTX_READ_32 T3.X, T3.X, 4, #1550; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1551; EG-NEXT: ALU clause starting at 20:552; EG-NEXT: MOV * T0.X, KC0[2].Z,553; EG-NEXT: MOV * T1.X, PV.X,554; EG-NEXT: ALU clause starting at 22:555; EG-NEXT: MOV * T2.X, T0.X,556; EG-NEXT: ALU clause starting at 23:557; EG-NEXT: MOV * T3.X, T0.X,558; EG-NEXT: ALU clause starting at 24:559; EG-NEXT: AND_INT T0.X, T0.X, literal.x,560; EG-NEXT: AND_INT * T3.X, T3.X, literal.y,561; EG-NEXT: -1424379385(-5.460358e-13), 286(4.007714e-43)562; EG-NEXT: AND_INT T2.X, T2.X, literal.x,563; EG-NEXT: LSHR * T4.X, KC0[2].Y, literal.y,564; EG-NEXT: -1424379385(-5.460358e-13), 2(2.802597e-45)565; EG-NEXT: AND_INT T1.X, T1.X, literal.x,566; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,567; EG-NEXT: 286(4.007714e-43), 4(5.605194e-45)568; EG-NEXT: LSHR * T5.X, PV.W, literal.x,569; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)570 %a = load volatile i64, ptr addrspace(1) %aptr571 %b = load volatile i64, ptr addrspace(1) %aptr572 %and0 = and i64 %a, 1231231234567573 %and1 = and i64 %b, 1231231234567574 store volatile i64 %and0, ptr addrspace(1) %out575 store volatile i64 %and1, ptr addrspace(1) %out576 ret void577}578 579define amdgpu_kernel void @v_and_multi_use_inline_imm_i64(ptr addrspace(1) %out, ptr addrspace(1) %aptr) {580; EG-LABEL: v_and_multi_use_inline_imm_i64:581; EG: ; %bb.0:582; EG-NEXT: ALU 1, @20, KC0[CB0:0-32], KC1[]583; EG-NEXT: TEX 0 @12584; EG-NEXT: ALU 0, @22, KC0[], KC1[]585; EG-NEXT: TEX 0 @14586; EG-NEXT: ALU 0, @23, KC0[], KC1[]587; EG-NEXT: TEX 1 @16588; EG-NEXT: ALU 8, @24, KC0[CB0:0-32], KC1[]589; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.X, T3.X, 0590; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T2.X, 0591; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.X, T3.X, 0592; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T2.X, 1593; EG-NEXT: CF_END594; EG-NEXT: Fetch clause starting at 12:595; EG-NEXT: VTX_READ_32 T1.X, T1.X, 4, #1596; EG-NEXT: Fetch clause starting at 14:597; EG-NEXT: VTX_READ_32 T1.X, T1.X, 0, #1598; EG-NEXT: Fetch clause starting at 16:599; EG-NEXT: VTX_READ_32 T2.X, T2.X, 4, #1600; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1601; EG-NEXT: ALU clause starting at 20:602; EG-NEXT: MOV * T0.X, KC0[2].Z,603; EG-NEXT: MOV * T1.X, PV.X,604; EG-NEXT: ALU clause starting at 22:605; EG-NEXT: MOV * T1.X, T0.X,606; EG-NEXT: ALU clause starting at 23:607; EG-NEXT: MOV * T2.X, T0.X,608; EG-NEXT: ALU clause starting at 24:609; EG-NEXT: AND_INT T0.X, T0.X, literal.x,610; EG-NEXT: AND_INT * T1.X, T1.X, literal.x,611; EG-NEXT: 63(8.828180e-44), 0(0.000000e+00)612; EG-NEXT: LSHR T2.X, KC0[2].Y, literal.x,613; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,614; EG-NEXT: 2(2.802597e-45), 4(5.605194e-45)615; EG-NEXT: LSHR T3.X, PV.W, literal.x,616; EG-NEXT: MOV * T4.X, literal.y,617; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)618 %a = load volatile i64, ptr addrspace(1) %aptr619 %b = load volatile i64, ptr addrspace(1) %aptr620 %and0 = and i64 %a, 63621 %and1 = and i64 %b, 63622 store volatile i64 %and0, ptr addrspace(1) %out623 store volatile i64 %and1, ptr addrspace(1) %out624 ret void625}626 627define amdgpu_kernel void @v_and_i64_32_bit_constant(ptr addrspace(1) %out, ptr addrspace(1) %aptr) {628; EG-LABEL: v_and_i64_32_bit_constant:629; EG: ; %bb.0:630; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]631; EG-NEXT: TEX 0 @6632; EG-NEXT: ALU 3, @11, KC0[CB0:0-32], KC1[]633; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1634; EG-NEXT: CF_END635; EG-NEXT: PAD636; EG-NEXT: Fetch clause starting at 6:637; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1638; EG-NEXT: ALU clause starting at 8:639; EG-NEXT: LSHL * T0.W, T0.X, literal.x,640; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)641; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,642; EG-NEXT: ALU clause starting at 11:643; EG-NEXT: AND_INT T0.X, T0.X, literal.x,644; EG-NEXT: MOV T0.Y, 0.0,645; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,646; EG-NEXT: 1234567(1.729997e-39), 2(2.802597e-45)647 %tid = call i32 @llvm.amdgcn.workitem.id.x() #0648 %gep.a = getelementptr i64, ptr addrspace(1) %aptr, i32 %tid649 %a = load i64, ptr addrspace(1) %gep.a, align 8650 %and = and i64 %a, 1234567651 store i64 %and, ptr addrspace(1) %out, align 8652 ret void653}654 655define amdgpu_kernel void @v_and_inline_imm_i64(ptr addrspace(1) %out, ptr addrspace(1) %aptr) {656; EG-LABEL: v_and_inline_imm_i64:657; EG: ; %bb.0:658; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]659; EG-NEXT: TEX 0 @6660; EG-NEXT: ALU 3, @11, KC0[CB0:0-32], KC1[]661; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1662; EG-NEXT: CF_END663; EG-NEXT: PAD664; EG-NEXT: Fetch clause starting at 6:665; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1666; EG-NEXT: ALU clause starting at 8:667; EG-NEXT: LSHL * T0.W, T0.X, literal.x,668; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)669; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,670; EG-NEXT: ALU clause starting at 11:671; EG-NEXT: AND_INT T0.X, T0.X, literal.x,672; EG-NEXT: MOV T0.Y, 0.0,673; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,674; EG-NEXT: 64(8.968310e-44), 2(2.802597e-45)675 %tid = call i32 @llvm.amdgcn.workitem.id.x() #0676 %gep.a = getelementptr i64, ptr addrspace(1) %aptr, i32 %tid677 %a = load i64, ptr addrspace(1) %gep.a, align 8678 %and = and i64 %a, 64679 store i64 %and, ptr addrspace(1) %out, align 8680 ret void681}682 683; FIXME: Should be able to reduce load width684 685define amdgpu_kernel void @v_and_inline_neg_imm_i64(ptr addrspace(1) %out, ptr addrspace(1) %aptr) {686; EG-LABEL: v_and_inline_neg_imm_i64:687; EG: ; %bb.0:688; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]689; EG-NEXT: TEX 0 @6690; EG-NEXT: ALU 2, @11, KC0[CB0:0-32], KC1[]691; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1692; EG-NEXT: CF_END693; EG-NEXT: PAD694; EG-NEXT: Fetch clause starting at 6:695; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #1696; EG-NEXT: ALU clause starting at 8:697; EG-NEXT: LSHL * T0.W, T0.X, literal.x,698; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)699; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,700; EG-NEXT: ALU clause starting at 11:701; EG-NEXT: AND_INT T0.X, T0.X, literal.x,702; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,703; EG-NEXT: -8(nan), 2(2.802597e-45)704 %tid = call i32 @llvm.amdgcn.workitem.id.x() #0705 %gep.a = getelementptr i64, ptr addrspace(1) %aptr, i32 %tid706 %a = load i64, ptr addrspace(1) %gep.a, align 8707 %and = and i64 %a, -8708 store i64 %and, ptr addrspace(1) %out, align 8709 ret void710}711 712define amdgpu_kernel void @s_and_inline_imm_64_i64(ptr addrspace(1) %out, ptr addrspace(1) %aptr, i64 %a) {713; EG-LABEL: s_and_inline_imm_64_i64:714; EG: ; %bb.0:715; EG-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]716; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1717; EG-NEXT: CF_END718; EG-NEXT: PAD719; EG-NEXT: ALU clause starting at 4:720; EG-NEXT: AND_INT T0.X, KC0[2].W, literal.x,721; EG-NEXT: MOV T0.Y, 0.0,722; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,723; EG-NEXT: 64(8.968310e-44), 2(2.802597e-45)724 %and = and i64 %a, 64725 store i64 %and, ptr addrspace(1) %out, align 8726 ret void727}728 729define amdgpu_kernel void @s_and_inline_imm_64_i64_noshrink(ptr addrspace(1) %out, ptr addrspace(1) %aptr, i64 %a, i32, i64 %b) {730; EG-LABEL: s_and_inline_imm_64_i64_noshrink:731; EG: ; %bb.0:732; EG-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[]733; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1734; EG-NEXT: CF_END735; EG-NEXT: PAD736; EG-NEXT: ALU clause starting at 4:737; EG-NEXT: LSHL * T0.W, KC0[2].W, 1,738; EG-NEXT: AND_INT * T0.W, PV.W, literal.x,739; EG-NEXT: 64(8.968310e-44), 0(0.000000e+00)740; EG-NEXT: ADD_INT T0.X, PV.W, KC0[3].W,741; EG-NEXT: ADDC_UINT T0.W, PV.W, KC0[3].W,742; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,743; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)744; EG-NEXT: ADD_INT * T0.Y, KC0[4].X, PV.W,745 %shl = shl i64 %a, 1746 %and = and i64 %shl, 64747 %add = add i64 %and, %b748 store i64 %add, ptr addrspace(1) %out, align 8749 ret void750}751 752define amdgpu_kernel void @s_and_inline_imm_1_i64(ptr addrspace(1) %out, ptr addrspace(1) %aptr, i64 %a) {753; EG-LABEL: s_and_inline_imm_1_i64:754; EG: ; %bb.0:755; EG-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]756; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1757; EG-NEXT: CF_END758; EG-NEXT: PAD759; EG-NEXT: ALU clause starting at 4:760; EG-NEXT: AND_INT T0.X, KC0[2].W, 1,761; EG-NEXT: MOV T0.Y, 0.0,762; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,763; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)764 %and = and i64 %a, 1765 store i64 %and, ptr addrspace(1) %out, align 8766 ret void767}768 769define amdgpu_kernel void @s_and_inline_imm_1.0_i64(ptr addrspace(1) %out, ptr addrspace(1) %aptr, i64 %a) {770; EG-LABEL: s_and_inline_imm_1.0_i64:771; EG: ; %bb.0:772; EG-NEXT: ALU 4, @4, KC0[CB0:0-32], KC1[]773; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1774; EG-NEXT: CF_END775; EG-NEXT: PAD776; EG-NEXT: ALU clause starting at 4:777; EG-NEXT: AND_INT * T0.Y, KC0[3].X, literal.x,778; EG-NEXT: 1072693248(1.875000e+00), 0(0.000000e+00)779; EG-NEXT: MOV T0.X, 0.0,780; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,781; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)782 %and = and i64 %a, 4607182418800017408783 store i64 %and, ptr addrspace(1) %out, align 8784 ret void785}786 787define amdgpu_kernel void @s_and_inline_imm_neg_1.0_i64(ptr addrspace(1) %out, ptr addrspace(1) %aptr, i64 %a) {788; EG-LABEL: s_and_inline_imm_neg_1.0_i64:789; EG: ; %bb.0:790; EG-NEXT: ALU 4, @4, KC0[CB0:0-32], KC1[]791; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1792; EG-NEXT: CF_END793; EG-NEXT: PAD794; EG-NEXT: ALU clause starting at 4:795; EG-NEXT: AND_INT * T0.Y, KC0[3].X, literal.x,796; EG-NEXT: -1074790400(-1.875000e+00), 0(0.000000e+00)797; EG-NEXT: MOV T0.X, 0.0,798; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,799; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)800 %and = and i64 %a, 13830554455654793216801 store i64 %and, ptr addrspace(1) %out, align 8802 ret void803}804 805define amdgpu_kernel void @s_and_inline_imm_0.5_i64(ptr addrspace(1) %out, ptr addrspace(1) %aptr, i64 %a) {806; EG-LABEL: s_and_inline_imm_0.5_i64:807; EG: ; %bb.0:808; EG-NEXT: ALU 4, @4, KC0[CB0:0-32], KC1[]809; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1810; EG-NEXT: CF_END811; EG-NEXT: PAD812; EG-NEXT: ALU clause starting at 4:813; EG-NEXT: AND_INT * T0.Y, KC0[3].X, literal.x,814; EG-NEXT: 1071644672(1.750000e+00), 0(0.000000e+00)815; EG-NEXT: MOV T0.X, 0.0,816; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,817; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)818 %and = and i64 %a, 4602678819172646912819 store i64 %and, ptr addrspace(1) %out, align 8820 ret void821}822 823define amdgpu_kernel void @s_and_inline_imm_neg_0.5_i64(ptr addrspace(1) %out, ptr addrspace(1) %aptr, i64 %a) {824; EG-LABEL: s_and_inline_imm_neg_0.5_i64:825; EG: ; %bb.0:826; EG-NEXT: ALU 4, @4, KC0[CB0:0-32], KC1[]827; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1828; EG-NEXT: CF_END829; EG-NEXT: PAD830; EG-NEXT: ALU clause starting at 4:831; EG-NEXT: AND_INT * T0.Y, KC0[3].X, literal.x,832; EG-NEXT: -1075838976(-1.750000e+00), 0(0.000000e+00)833; EG-NEXT: MOV T0.X, 0.0,834; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,835; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)836 %and = and i64 %a, 13826050856027422720837 store i64 %and, ptr addrspace(1) %out, align 8838 ret void839}840 841define amdgpu_kernel void @s_and_inline_imm_2.0_i64(ptr addrspace(1) %out, ptr addrspace(1) %aptr, i64 %a) {842; EG-LABEL: s_and_inline_imm_2.0_i64:843; EG: ; %bb.0:844; EG-NEXT: ALU 4, @4, KC0[CB0:0-32], KC1[]845; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1846; EG-NEXT: CF_END847; EG-NEXT: PAD848; EG-NEXT: ALU clause starting at 4:849; EG-NEXT: AND_INT * T0.Y, KC0[3].X, literal.x,850; EG-NEXT: 1073741824(2.000000e+00), 0(0.000000e+00)851; EG-NEXT: MOV T0.X, 0.0,852; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,853; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)854 %and = and i64 %a, 4611686018427387904855 store i64 %and, ptr addrspace(1) %out, align 8856 ret void857}858 859define amdgpu_kernel void @s_and_inline_imm_neg_2.0_i64(ptr addrspace(1) %out, ptr addrspace(1) %aptr, i64 %a) {860; EG-LABEL: s_and_inline_imm_neg_2.0_i64:861; EG: ; %bb.0:862; EG-NEXT: ALU 4, @4, KC0[CB0:0-32], KC1[]863; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1864; EG-NEXT: CF_END865; EG-NEXT: PAD866; EG-NEXT: ALU clause starting at 4:867; EG-NEXT: AND_INT * T0.Y, KC0[3].X, literal.x,868; EG-NEXT: -1073741824(-2.000000e+00), 0(0.000000e+00)869; EG-NEXT: MOV T0.X, 0.0,870; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,871; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)872 %and = and i64 %a, 13835058055282163712873 store i64 %and, ptr addrspace(1) %out, align 8874 ret void875}876 877define amdgpu_kernel void @s_and_inline_imm_4.0_i64(ptr addrspace(1) %out, ptr addrspace(1) %aptr, i64 %a) {878; EG-LABEL: s_and_inline_imm_4.0_i64:879; EG: ; %bb.0:880; EG-NEXT: ALU 4, @4, KC0[CB0:0-32], KC1[]881; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1882; EG-NEXT: CF_END883; EG-NEXT: PAD884; EG-NEXT: ALU clause starting at 4:885; EG-NEXT: AND_INT * T0.Y, KC0[3].X, literal.x,886; EG-NEXT: 1074790400(2.250000e+00), 0(0.000000e+00)887; EG-NEXT: MOV T0.X, 0.0,888; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,889; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)890 %and = and i64 %a, 4616189618054758400891 store i64 %and, ptr addrspace(1) %out, align 8892 ret void893}894 895define amdgpu_kernel void @s_and_inline_imm_neg_4.0_i64(ptr addrspace(1) %out, ptr addrspace(1) %aptr, i64 %a) {896; EG-LABEL: s_and_inline_imm_neg_4.0_i64:897; EG: ; %bb.0:898; EG-NEXT: ALU 4, @4, KC0[CB0:0-32], KC1[]899; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1900; EG-NEXT: CF_END901; EG-NEXT: PAD902; EG-NEXT: ALU clause starting at 4:903; EG-NEXT: AND_INT * T0.Y, KC0[3].X, literal.x,904; EG-NEXT: -1072693248(-2.250000e+00), 0(0.000000e+00)905; EG-NEXT: MOV T0.X, 0.0,906; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,907; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)908 %and = and i64 %a, 13839561654909534208909 store i64 %and, ptr addrspace(1) %out, align 8910 ret void911}912 913; Test with the 64-bit integer bitpattern for a 32-bit float in the914; low 32-bits, which is not a valid 64-bit inline immmediate.915 916define amdgpu_kernel void @s_and_inline_imm_f32_4.0_i64(ptr addrspace(1) %out, ptr addrspace(1) %aptr, i64 %a) {917; EG-LABEL: s_and_inline_imm_f32_4.0_i64:918; EG: ; %bb.0:919; EG-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]920; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1921; EG-NEXT: CF_END922; EG-NEXT: PAD923; EG-NEXT: ALU clause starting at 4:924; EG-NEXT: AND_INT T0.X, KC0[2].W, literal.x,925; EG-NEXT: MOV T0.Y, 0.0,926; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,927; EG-NEXT: 1082130432(4.000000e+00), 2(2.802597e-45)928 %and = and i64 %a, 1082130432929 store i64 %and, ptr addrspace(1) %out, align 8930 ret void931}932 933define amdgpu_kernel void @s_and_inline_imm_f32_neg_4.0_i64(ptr addrspace(1) %out, ptr addrspace(1) %aptr, i64 %a) {934; EG-LABEL: s_and_inline_imm_f32_neg_4.0_i64:935; EG: ; %bb.0:936; EG-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]937; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1938; EG-NEXT: CF_END939; EG-NEXT: PAD940; EG-NEXT: ALU clause starting at 4:941; EG-NEXT: MOV * T0.Y, KC0[3].X,942; EG-NEXT: AND_INT T0.X, KC0[2].W, literal.x,943; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,944; EG-NEXT: -1065353216(-4.000000e+00), 2(2.802597e-45)945 %and = and i64 %a, -1065353216946 store i64 %and, ptr addrspace(1) %out, align 8947 ret void948}949 950; Shift into upper 32-bits951 952define amdgpu_kernel void @s_and_inline_high_imm_f32_4.0_i64(ptr addrspace(1) %out, ptr addrspace(1) %aptr, i64 %a) {953; EG-LABEL: s_and_inline_high_imm_f32_4.0_i64:954; EG: ; %bb.0:955; EG-NEXT: ALU 4, @4, KC0[CB0:0-32], KC1[]956; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1957; EG-NEXT: CF_END958; EG-NEXT: PAD959; EG-NEXT: ALU clause starting at 4:960; EG-NEXT: AND_INT * T0.Y, KC0[3].X, literal.x,961; EG-NEXT: 1082130432(4.000000e+00), 0(0.000000e+00)962; EG-NEXT: MOV T0.X, 0.0,963; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,964; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)965 %and = and i64 %a, 4647714815446351872966 store i64 %and, ptr addrspace(1) %out, align 8967 ret void968}969 970define amdgpu_kernel void @s_and_inline_high_imm_f32_neg_4.0_i64(ptr addrspace(1) %out, ptr addrspace(1) %aptr, i64 %a) {971; EG-LABEL: s_and_inline_high_imm_f32_neg_4.0_i64:972; EG: ; %bb.0:973; EG-NEXT: ALU 4, @4, KC0[CB0:0-32], KC1[]974; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1975; EG-NEXT: CF_END976; EG-NEXT: PAD977; EG-NEXT: ALU clause starting at 4:978; EG-NEXT: AND_INT * T0.Y, KC0[3].X, literal.x,979; EG-NEXT: -1065353216(-4.000000e+00), 0(0.000000e+00)980; EG-NEXT: MOV T0.X, 0.0,981; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,982; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)983 %and = and i64 %a, 13871086852301127680984 store i64 %and, ptr addrspace(1) %out, align 8985 ret void986}987attributes #0 = { nounwind readnone }988