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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2;RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji | FileCheck -check-prefix=VI %s3;RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 | FileCheck -check-prefix=GFX9 %s4;RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 | FileCheck -check-prefix=GFX10 %s5;RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 | FileCheck -check-prefix=GFX10 %s6 7; ===================================================================================8; V_AND_OR_B329; ===================================================================================10 11define amdgpu_ps float @and_or(i32 %a, i32 %b, i32 %c) {12; VI-LABEL: and_or:13; VI: ; %bb.0:14; VI-NEXT: v_and_b32_e32 v0, v0, v115; VI-NEXT: v_or_b32_e32 v0, v0, v216; VI-NEXT: ; return to shader part epilog17;18; GFX9-LABEL: and_or:19; GFX9: ; %bb.0:20; GFX9-NEXT: v_and_or_b32 v0, v0, v1, v221; GFX9-NEXT: ; return to shader part epilog22;23; GFX10-LABEL: and_or:24; GFX10: ; %bb.0:25; GFX10-NEXT: v_and_or_b32 v0, v0, v1, v226; GFX10-NEXT: ; return to shader part epilog27 %x = and i32 %a, %b28 %result = or i32 %x, %c29 %bc = bitcast i32 %result to float30 ret float %bc31}32 33; ThreeOp instruction variant not used due to Constant Bus Limitations34define amdgpu_ps float @and_or_vgpr_b(i32 inreg %a, i32 %b, i32 inreg %c) {35; VI-LABEL: and_or_vgpr_b:36; VI: ; %bb.0:37; VI-NEXT: v_and_b32_e32 v0, s2, v038; VI-NEXT: v_or_b32_e32 v0, s3, v039; VI-NEXT: ; return to shader part epilog40;41; GFX9-LABEL: and_or_vgpr_b:42; GFX9: ; %bb.0:43; GFX9-NEXT: v_and_b32_e32 v0, s2, v044; GFX9-NEXT: v_or_b32_e32 v0, s3, v045; GFX9-NEXT: ; return to shader part epilog46;47; GFX10-LABEL: and_or_vgpr_b:48; GFX10: ; %bb.0:49; GFX10-NEXT: v_and_or_b32 v0, s2, v0, s350; GFX10-NEXT: ; return to shader part epilog51 %x = and i32 %a, %b52 %result = or i32 %x, %c53 %bc = bitcast i32 %result to float54 ret float %bc55}56 57define amdgpu_ps float @and_or_vgpr_ab(i32 %a, i32 %b, i32 inreg %c) {58; VI-LABEL: and_or_vgpr_ab:59; VI: ; %bb.0:60; VI-NEXT: v_and_b32_e32 v0, v0, v161; VI-NEXT: v_or_b32_e32 v0, s2, v062; VI-NEXT: ; return to shader part epilog63;64; GFX9-LABEL: and_or_vgpr_ab:65; GFX9: ; %bb.0:66; GFX9-NEXT: v_and_or_b32 v0, v0, v1, s267; GFX9-NEXT: ; return to shader part epilog68;69; GFX10-LABEL: and_or_vgpr_ab:70; GFX10: ; %bb.0:71; GFX10-NEXT: v_and_or_b32 v0, v0, v1, s272; GFX10-NEXT: ; return to shader part epilog73 %x = and i32 %a, %b74 %result = or i32 %x, %c75 %bc = bitcast i32 %result to float76 ret float %bc77}78 79define amdgpu_ps float @and_or_vgpr_const(i32 %a, i32 %b) {80; VI-LABEL: and_or_vgpr_const:81; VI: ; %bb.0:82; VI-NEXT: v_and_b32_e32 v0, 4, v083; VI-NEXT: v_or_b32_e32 v0, v0, v184; VI-NEXT: ; return to shader part epilog85;86; GFX9-LABEL: and_or_vgpr_const:87; GFX9: ; %bb.0:88; GFX9-NEXT: v_and_or_b32 v0, v0, 4, v189; GFX9-NEXT: ; return to shader part epilog90;91; GFX10-LABEL: and_or_vgpr_const:92; GFX10: ; %bb.0:93; GFX10-NEXT: v_and_or_b32 v0, v0, 4, v194; GFX10-NEXT: ; return to shader part epilog95 %x = and i32 4, %a96 %result = or i32 %x, %b97 %bc = bitcast i32 %result to float98 ret float %bc99}100 101define amdgpu_ps float @and_or_vgpr_const_inline_const(i32 %a) {102; VI-LABEL: and_or_vgpr_const_inline_const:103; VI: ; %bb.0:104; VI-NEXT: v_and_b32_e32 v0, 20, v0105; VI-NEXT: v_or_b32_e32 v0, 0x808, v0106; VI-NEXT: ; return to shader part epilog107;108; GFX9-LABEL: and_or_vgpr_const_inline_const:109; GFX9: ; %bb.0:110; GFX9-NEXT: v_mov_b32_e32 v1, 0x808111; GFX9-NEXT: v_and_or_b32 v0, v0, 20, v1112; GFX9-NEXT: ; return to shader part epilog113;114; GFX10-LABEL: and_or_vgpr_const_inline_const:115; GFX10: ; %bb.0:116; GFX10-NEXT: v_and_or_b32 v0, v0, 20, 0x808117; GFX10-NEXT: ; return to shader part epilog118 %x = and i32 20, %a119 %result = or i32 %x, 2056120 %bc = bitcast i32 %result to float121 ret float %bc122}123 124define amdgpu_ps float @and_or_vgpr_inline_const_x2(i32 %a) {125; VI-LABEL: and_or_vgpr_inline_const_x2:126; VI: ; %bb.0:127; VI-NEXT: v_and_b32_e32 v0, 4, v0128; VI-NEXT: v_or_b32_e32 v0, 1, v0129; VI-NEXT: ; return to shader part epilog130;131; GFX9-LABEL: and_or_vgpr_inline_const_x2:132; GFX9: ; %bb.0:133; GFX9-NEXT: v_and_or_b32 v0, v0, 4, 1134; GFX9-NEXT: ; return to shader part epilog135;136; GFX10-LABEL: and_or_vgpr_inline_const_x2:137; GFX10: ; %bb.0:138; GFX10-NEXT: v_and_or_b32 v0, v0, 4, 1139; GFX10-NEXT: ; return to shader part epilog140 %x = and i32 4, %a141 %result = or i32 %x, 1142 %bc = bitcast i32 %result to float143 ret float %bc144}145