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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn -mcpu=tahiti -mattr=-flat-for-global < %s | FileCheck -check-prefix=SI %s3 4define amdgpu_kernel void @s_or_to_orn2(ptr addrspace(1) %out, i32 %in) {5; SI-LABEL: s_or_to_orn2:6; SI: ; %bb.0:7; SI-NEXT: s_load_dword s6, s[4:5], 0xb8; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x99; SI-NEXT: s_mov_b32 s3, 0xf00010; SI-NEXT: s_mov_b32 s2, -111; SI-NEXT: s_waitcnt lgkmcnt(0)12; SI-NEXT: s_or_b32 s4, s6, 0xffffffcd13; SI-NEXT: v_mov_b32_e32 v0, s414; SI-NEXT: buffer_store_dword v0, off, s[0:3], 015; SI-NEXT: s_endpgm16 %x = or i32 %in, -5117 store i32 %x, ptr addrspace(1) %out18 ret void19}20 21define amdgpu_kernel void @s_or_to_orn2_imm0(ptr addrspace(1) %out, i32 %in) {22; SI-LABEL: s_or_to_orn2_imm0:23; SI: ; %bb.0:24; SI-NEXT: s_load_dword s6, s[4:5], 0xb25; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x926; SI-NEXT: s_mov_b32 s3, 0xf00027; SI-NEXT: s_mov_b32 s2, -128; SI-NEXT: s_waitcnt lgkmcnt(0)29; SI-NEXT: s_or_b32 s4, s6, 0xffffffcd30; SI-NEXT: v_mov_b32_e32 v0, s431; SI-NEXT: buffer_store_dword v0, off, s[0:3], 032; SI-NEXT: s_endpgm33 %x = or i32 -51, %in34 store i32 %x, ptr addrspace(1) %out35 ret void36}37 38define amdgpu_kernel void @s_and_to_andn2(ptr addrspace(1) %out, i32 %in) {39; SI-LABEL: s_and_to_andn2:40; SI: ; %bb.0:41; SI-NEXT: s_load_dword s6, s[4:5], 0xb42; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x943; SI-NEXT: s_mov_b32 s3, 0xf00044; SI-NEXT: s_mov_b32 s2, -145; SI-NEXT: s_waitcnt lgkmcnt(0)46; SI-NEXT: s_and_b32 s4, s6, 0xffffffcd47; SI-NEXT: v_mov_b32_e32 v0, s448; SI-NEXT: buffer_store_dword v0, off, s[0:3], 049; SI-NEXT: s_endpgm50 %x = and i32 %in, -5151 store i32 %x, ptr addrspace(1) %out52 ret void53}54 55define amdgpu_kernel void @s_and_to_andn2_imm0(ptr addrspace(1) %out, i32 %in) {56; SI-LABEL: s_and_to_andn2_imm0:57; SI: ; %bb.0:58; SI-NEXT: s_load_dword s6, s[4:5], 0xb59; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x960; SI-NEXT: s_mov_b32 s3, 0xf00061; SI-NEXT: s_mov_b32 s2, -162; SI-NEXT: s_waitcnt lgkmcnt(0)63; SI-NEXT: s_and_b32 s4, s6, 0xffffffcd64; SI-NEXT: v_mov_b32_e32 v0, s465; SI-NEXT: buffer_store_dword v0, off, s[0:3], 066; SI-NEXT: s_endpgm67 %x = and i32 -51, %in68 store i32 %x, ptr addrspace(1) %out69 ret void70}71 72define amdgpu_kernel void @s_xor_to_xnor(ptr addrspace(1) %out, i32 %in) {73; SI-LABEL: s_xor_to_xnor:74; SI: ; %bb.0:75; SI-NEXT: s_load_dword s6, s[4:5], 0xb76; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x977; SI-NEXT: s_mov_b32 s3, 0xf00078; SI-NEXT: s_mov_b32 s2, -179; SI-NEXT: s_waitcnt lgkmcnt(0)80; SI-NEXT: s_xor_b32 s4, s6, 0xffffffcd81; SI-NEXT: v_mov_b32_e32 v0, s482; SI-NEXT: buffer_store_dword v0, off, s[0:3], 083; SI-NEXT: s_endpgm84 %x = xor i32 %in, -5185 store i32 %x, ptr addrspace(1) %out86 ret void87}88 89define amdgpu_kernel void @s_xor_to_xnor_imm0(ptr addrspace(1) %out, i32 %in) {90; SI-LABEL: s_xor_to_xnor_imm0:91; SI: ; %bb.0:92; SI-NEXT: s_load_dword s6, s[4:5], 0xb93; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x994; SI-NEXT: s_mov_b32 s3, 0xf00095; SI-NEXT: s_mov_b32 s2, -196; SI-NEXT: s_waitcnt lgkmcnt(0)97; SI-NEXT: s_xor_b32 s4, s6, 0xffffffcd98; SI-NEXT: v_mov_b32_e32 v0, s499; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0100; SI-NEXT: s_endpgm101 %x = xor i32 -51, %in102 store i32 %x, ptr addrspace(1) %out103 ret void104}105