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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-globals2; RUN: opt -mtriple=amdgcn-unknown-amdhsa -S -passes=amdgpu-attributor < %s | FileCheck -check-prefix=HSA %s3 4declare i32 @llvm.amdgcn.workgroup.id.x() #05declare i32 @llvm.amdgcn.workgroup.id.y() #06declare i32 @llvm.amdgcn.workgroup.id.z() #07 8declare i32 @llvm.amdgcn.workitem.id.x() #09declare i32 @llvm.amdgcn.workitem.id.y() #010declare i32 @llvm.amdgcn.workitem.id.z() #011 12declare ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() #013declare ptr addrspace(4) @llvm.amdgcn.queue.ptr() #014declare ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr() #015declare ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() #016 17declare i1 @llvm.amdgcn.is.shared(ptr nocapture) #218declare i1 @llvm.amdgcn.is.private(ptr nocapture) #219 20define amdgpu_kernel void @use_tgid_x(ptr addrspace(1) %ptr) #1 {21; HSA-LABEL: define {{[^@]+}}@use_tgid_x22; HSA-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR1:[0-9]+]] {23; HSA-NEXT: [[VAL:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x()24; HSA-NEXT: store i32 [[VAL]], ptr addrspace(1) [[PTR]], align 425; HSA-NEXT: ret void26;27 %val = call i32 @llvm.amdgcn.workgroup.id.x()28 store i32 %val, ptr addrspace(1) %ptr29 ret void30}31 32define amdgpu_kernel void @use_tgid_y(ptr addrspace(1) %ptr) #1 {33; HSA-LABEL: define {{[^@]+}}@use_tgid_y34; HSA-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR2:[0-9]+]] {35; HSA-NEXT: [[VAL:%.*]] = call i32 @llvm.amdgcn.workgroup.id.y()36; HSA-NEXT: store i32 [[VAL]], ptr addrspace(1) [[PTR]], align 437; HSA-NEXT: ret void38;39 %val = call i32 @llvm.amdgcn.workgroup.id.y()40 store i32 %val, ptr addrspace(1) %ptr41 ret void42}43 44define amdgpu_kernel void @multi_use_tgid_y(ptr addrspace(1) %ptr) #1 {45; HSA-LABEL: define {{[^@]+}}@multi_use_tgid_y46; HSA-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR2]] {47; HSA-NEXT: [[VAL0:%.*]] = call i32 @llvm.amdgcn.workgroup.id.y()48; HSA-NEXT: store volatile i32 [[VAL0]], ptr addrspace(1) [[PTR]], align 449; HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workgroup.id.y()50; HSA-NEXT: store volatile i32 [[VAL1]], ptr addrspace(1) [[PTR]], align 451; HSA-NEXT: ret void52;53 %val0 = call i32 @llvm.amdgcn.workgroup.id.y()54 store volatile i32 %val0, ptr addrspace(1) %ptr55 %val1 = call i32 @llvm.amdgcn.workgroup.id.y()56 store volatile i32 %val1, ptr addrspace(1) %ptr57 ret void58}59 60define amdgpu_kernel void @use_tgid_x_y(ptr addrspace(1) %ptr) #1 {61; HSA-LABEL: define {{[^@]+}}@use_tgid_x_y62; HSA-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR2]] {63; HSA-NEXT: [[VAL0:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x()64; HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workgroup.id.y()65; HSA-NEXT: store volatile i32 [[VAL0]], ptr addrspace(1) [[PTR]], align 466; HSA-NEXT: store volatile i32 [[VAL1]], ptr addrspace(1) [[PTR]], align 467; HSA-NEXT: ret void68;69 %val0 = call i32 @llvm.amdgcn.workgroup.id.x()70 %val1 = call i32 @llvm.amdgcn.workgroup.id.y()71 store volatile i32 %val0, ptr addrspace(1) %ptr72 store volatile i32 %val1, ptr addrspace(1) %ptr73 ret void74}75 76define amdgpu_kernel void @use_tgid_z(ptr addrspace(1) %ptr) #1 {77; HSA-LABEL: define {{[^@]+}}@use_tgid_z78; HSA-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR3:[0-9]+]] {79; HSA-NEXT: [[VAL:%.*]] = call i32 @llvm.amdgcn.workgroup.id.z()80; HSA-NEXT: store i32 [[VAL]], ptr addrspace(1) [[PTR]], align 481; HSA-NEXT: ret void82;83 %val = call i32 @llvm.amdgcn.workgroup.id.z()84 store i32 %val, ptr addrspace(1) %ptr85 ret void86}87 88define amdgpu_kernel void @use_tgid_x_z(ptr addrspace(1) %ptr) #1 {89; HSA-LABEL: define {{[^@]+}}@use_tgid_x_z90; HSA-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR3]] {91; HSA-NEXT: [[VAL0:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x()92; HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workgroup.id.z()93; HSA-NEXT: store volatile i32 [[VAL0]], ptr addrspace(1) [[PTR]], align 494; HSA-NEXT: store volatile i32 [[VAL1]], ptr addrspace(1) [[PTR]], align 495; HSA-NEXT: ret void96;97 %val0 = call i32 @llvm.amdgcn.workgroup.id.x()98 %val1 = call i32 @llvm.amdgcn.workgroup.id.z()99 store volatile i32 %val0, ptr addrspace(1) %ptr100 store volatile i32 %val1, ptr addrspace(1) %ptr101 ret void102}103 104define amdgpu_kernel void @use_tgid_y_z(ptr addrspace(1) %ptr) #1 {105; HSA-LABEL: define {{[^@]+}}@use_tgid_y_z106; HSA-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR4:[0-9]+]] {107; HSA-NEXT: [[VAL0:%.*]] = call i32 @llvm.amdgcn.workgroup.id.y()108; HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workgroup.id.z()109; HSA-NEXT: store volatile i32 [[VAL0]], ptr addrspace(1) [[PTR]], align 4110; HSA-NEXT: store volatile i32 [[VAL1]], ptr addrspace(1) [[PTR]], align 4111; HSA-NEXT: ret void112;113 %val0 = call i32 @llvm.amdgcn.workgroup.id.y()114 %val1 = call i32 @llvm.amdgcn.workgroup.id.z()115 store volatile i32 %val0, ptr addrspace(1) %ptr116 store volatile i32 %val1, ptr addrspace(1) %ptr117 ret void118}119 120define amdgpu_kernel void @use_tgid_x_y_z(ptr addrspace(1) %ptr) #1 {121; HSA-LABEL: define {{[^@]+}}@use_tgid_x_y_z122; HSA-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR4]] {123; HSA-NEXT: [[VAL0:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x()124; HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workgroup.id.y()125; HSA-NEXT: [[VAL2:%.*]] = call i32 @llvm.amdgcn.workgroup.id.z()126; HSA-NEXT: store volatile i32 [[VAL0]], ptr addrspace(1) [[PTR]], align 4127; HSA-NEXT: store volatile i32 [[VAL1]], ptr addrspace(1) [[PTR]], align 4128; HSA-NEXT: store volatile i32 [[VAL2]], ptr addrspace(1) [[PTR]], align 4129; HSA-NEXT: ret void130;131 %val0 = call i32 @llvm.amdgcn.workgroup.id.x()132 %val1 = call i32 @llvm.amdgcn.workgroup.id.y()133 %val2 = call i32 @llvm.amdgcn.workgroup.id.z()134 store volatile i32 %val0, ptr addrspace(1) %ptr135 store volatile i32 %val1, ptr addrspace(1) %ptr136 store volatile i32 %val2, ptr addrspace(1) %ptr137 ret void138}139 140define amdgpu_kernel void @use_tidig_x(ptr addrspace(1) %ptr) #1 {141; HSA-LABEL: define {{[^@]+}}@use_tidig_x142; HSA-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR1]] {143; HSA-NEXT: [[VAL:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()144; HSA-NEXT: store i32 [[VAL]], ptr addrspace(1) [[PTR]], align 4145; HSA-NEXT: ret void146;147 %val = call i32 @llvm.amdgcn.workitem.id.x()148 store i32 %val, ptr addrspace(1) %ptr149 ret void150}151 152define amdgpu_kernel void @use_tidig_y(ptr addrspace(1) %ptr) #1 {153; HSA-LABEL: define {{[^@]+}}@use_tidig_y154; HSA-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR5:[0-9]+]] {155; HSA-NEXT: [[VAL:%.*]] = call i32 @llvm.amdgcn.workitem.id.y()156; HSA-NEXT: store i32 [[VAL]], ptr addrspace(1) [[PTR]], align 4157; HSA-NEXT: ret void158;159 %val = call i32 @llvm.amdgcn.workitem.id.y()160 store i32 %val, ptr addrspace(1) %ptr161 ret void162}163 164define amdgpu_kernel void @use_tidig_z(ptr addrspace(1) %ptr) #1 {165; HSA-LABEL: define {{[^@]+}}@use_tidig_z166; HSA-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR6:[0-9]+]] {167; HSA-NEXT: [[VAL:%.*]] = call i32 @llvm.amdgcn.workitem.id.z()168; HSA-NEXT: store i32 [[VAL]], ptr addrspace(1) [[PTR]], align 4169; HSA-NEXT: ret void170;171 %val = call i32 @llvm.amdgcn.workitem.id.z()172 store i32 %val, ptr addrspace(1) %ptr173 ret void174}175 176define amdgpu_kernel void @use_tidig_x_tgid_x(ptr addrspace(1) %ptr) #1 {177; HSA-LABEL: define {{[^@]+}}@use_tidig_x_tgid_x178; HSA-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR1]] {179; HSA-NEXT: [[VAL0:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()180; HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x()181; HSA-NEXT: store volatile i32 [[VAL0]], ptr addrspace(1) [[PTR]], align 4182; HSA-NEXT: store volatile i32 [[VAL1]], ptr addrspace(1) [[PTR]], align 4183; HSA-NEXT: ret void184;185 %val0 = call i32 @llvm.amdgcn.workitem.id.x()186 %val1 = call i32 @llvm.amdgcn.workgroup.id.x()187 store volatile i32 %val0, ptr addrspace(1) %ptr188 store volatile i32 %val1, ptr addrspace(1) %ptr189 ret void190}191 192define amdgpu_kernel void @use_tidig_y_tgid_y(ptr addrspace(1) %ptr) #1 {193; HSA-LABEL: define {{[^@]+}}@use_tidig_y_tgid_y194; HSA-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR7:[0-9]+]] {195; HSA-NEXT: [[VAL0:%.*]] = call i32 @llvm.amdgcn.workitem.id.y()196; HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workgroup.id.y()197; HSA-NEXT: store volatile i32 [[VAL0]], ptr addrspace(1) [[PTR]], align 4198; HSA-NEXT: store volatile i32 [[VAL1]], ptr addrspace(1) [[PTR]], align 4199; HSA-NEXT: ret void200;201 %val0 = call i32 @llvm.amdgcn.workitem.id.y()202 %val1 = call i32 @llvm.amdgcn.workgroup.id.y()203 store volatile i32 %val0, ptr addrspace(1) %ptr204 store volatile i32 %val1, ptr addrspace(1) %ptr205 ret void206}207 208define amdgpu_kernel void @use_tidig_x_y_z(ptr addrspace(1) %ptr) #1 {209; HSA-LABEL: define {{[^@]+}}@use_tidig_x_y_z210; HSA-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR8:[0-9]+]] {211; HSA-NEXT: [[VAL0:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()212; HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workitem.id.y()213; HSA-NEXT: [[VAL2:%.*]] = call i32 @llvm.amdgcn.workitem.id.z()214; HSA-NEXT: store volatile i32 [[VAL0]], ptr addrspace(1) [[PTR]], align 4215; HSA-NEXT: store volatile i32 [[VAL1]], ptr addrspace(1) [[PTR]], align 4216; HSA-NEXT: store volatile i32 [[VAL2]], ptr addrspace(1) [[PTR]], align 4217; HSA-NEXT: ret void218;219 %val0 = call i32 @llvm.amdgcn.workitem.id.x()220 %val1 = call i32 @llvm.amdgcn.workitem.id.y()221 %val2 = call i32 @llvm.amdgcn.workitem.id.z()222 store volatile i32 %val0, ptr addrspace(1) %ptr223 store volatile i32 %val1, ptr addrspace(1) %ptr224 store volatile i32 %val2, ptr addrspace(1) %ptr225 ret void226}227 228define amdgpu_kernel void @use_all_workitems(ptr addrspace(1) %ptr) #1 {229; HSA-LABEL: define {{[^@]+}}@use_all_workitems230; HSA-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR9:[0-9]+]] {231; HSA-NEXT: [[VAL0:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()232; HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workitem.id.y()233; HSA-NEXT: [[VAL2:%.*]] = call i32 @llvm.amdgcn.workitem.id.z()234; HSA-NEXT: [[VAL3:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x()235; HSA-NEXT: [[VAL4:%.*]] = call i32 @llvm.amdgcn.workgroup.id.y()236; HSA-NEXT: [[VAL5:%.*]] = call i32 @llvm.amdgcn.workgroup.id.z()237; HSA-NEXT: store volatile i32 [[VAL0]], ptr addrspace(1) [[PTR]], align 4238; HSA-NEXT: store volatile i32 [[VAL1]], ptr addrspace(1) [[PTR]], align 4239; HSA-NEXT: store volatile i32 [[VAL2]], ptr addrspace(1) [[PTR]], align 4240; HSA-NEXT: store volatile i32 [[VAL3]], ptr addrspace(1) [[PTR]], align 4241; HSA-NEXT: store volatile i32 [[VAL4]], ptr addrspace(1) [[PTR]], align 4242; HSA-NEXT: store volatile i32 [[VAL5]], ptr addrspace(1) [[PTR]], align 4243; HSA-NEXT: ret void244;245 %val0 = call i32 @llvm.amdgcn.workitem.id.x()246 %val1 = call i32 @llvm.amdgcn.workitem.id.y()247 %val2 = call i32 @llvm.amdgcn.workitem.id.z()248 %val3 = call i32 @llvm.amdgcn.workgroup.id.x()249 %val4 = call i32 @llvm.amdgcn.workgroup.id.y()250 %val5 = call i32 @llvm.amdgcn.workgroup.id.z()251 store volatile i32 %val0, ptr addrspace(1) %ptr252 store volatile i32 %val1, ptr addrspace(1) %ptr253 store volatile i32 %val2, ptr addrspace(1) %ptr254 store volatile i32 %val3, ptr addrspace(1) %ptr255 store volatile i32 %val4, ptr addrspace(1) %ptr256 store volatile i32 %val5, ptr addrspace(1) %ptr257 ret void258}259 260define amdgpu_kernel void @use_dispatch_ptr(ptr addrspace(1) %ptr) #1 {261; HSA-LABEL: define {{[^@]+}}@use_dispatch_ptr262; HSA-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR10:[0-9]+]] {263; HSA-NEXT: [[DISPATCH_PTR:%.*]] = call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()264; HSA-NEXT: [[VAL:%.*]] = load i32, ptr addrspace(4) [[DISPATCH_PTR]], align 4265; HSA-NEXT: store i32 [[VAL]], ptr addrspace(1) [[PTR]], align 4266; HSA-NEXT: ret void267;268 %dispatch.ptr = call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()269 %val = load i32, ptr addrspace(4) %dispatch.ptr270 store i32 %val, ptr addrspace(1) %ptr271 ret void272}273 274define amdgpu_kernel void @use_queue_ptr(ptr addrspace(1) %ptr) #1 {275; HSA-LABEL: define {{[^@]+}}@use_queue_ptr276; HSA-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR11:[0-9]+]] {277; HSA-NEXT: [[DISPATCH_PTR:%.*]] = call ptr addrspace(4) @llvm.amdgcn.queue.ptr()278; HSA-NEXT: [[VAL:%.*]] = load i32, ptr addrspace(4) [[DISPATCH_PTR]], align 4279; HSA-NEXT: store i32 [[VAL]], ptr addrspace(1) [[PTR]], align 4280; HSA-NEXT: ret void281;282 %dispatch.ptr = call ptr addrspace(4) @llvm.amdgcn.queue.ptr()283 %val = load i32, ptr addrspace(4) %dispatch.ptr284 store i32 %val, ptr addrspace(1) %ptr285 ret void286}287 288define amdgpu_kernel void @use_kernarg_segment_ptr(ptr addrspace(1) %ptr) #1 {289; HSA-LABEL: define {{[^@]+}}@use_kernarg_segment_ptr290; HSA-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR1]] {291; HSA-NEXT: [[DISPATCH_PTR:%.*]] = call ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()292; HSA-NEXT: [[VAL:%.*]] = load i32, ptr addrspace(4) [[DISPATCH_PTR]], align 4293; HSA-NEXT: store i32 [[VAL]], ptr addrspace(1) [[PTR]], align 4294; HSA-NEXT: ret void295;296 %dispatch.ptr = call ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()297 %val = load i32, ptr addrspace(4) %dispatch.ptr298 store i32 %val, ptr addrspace(1) %ptr299 ret void300}301 302define amdgpu_kernel void @use_group_to_flat_addrspacecast(ptr addrspace(3) %ptr) #1 {303; HSA-LABEL: define {{[^@]+}}@use_group_to_flat_addrspacecast304; HSA-SAME: (ptr addrspace(3) [[PTR:%.*]]) #[[ATTR12:[0-9]+]] {305; HSA-NEXT: [[STOF:%.*]] = addrspacecast ptr addrspace(3) [[PTR]] to ptr306; HSA-NEXT: store volatile i32 0, ptr [[STOF]], align 4, !noalias.addrspace [[META0:![0-9]+]]307; HSA-NEXT: ret void308;309 %stof = addrspacecast ptr addrspace(3) %ptr to ptr310 store volatile i32 0, ptr %stof311 ret void312}313 314define amdgpu_kernel void @use_private_to_flat_addrspacecast(ptr addrspace(5) %ptr) #1 {315; HSA-LABEL: define {{[^@]+}}@use_private_to_flat_addrspacecast316; HSA-SAME: (ptr addrspace(5) [[PTR:%.*]]) #[[ATTR13:[0-9]+]] {317; HSA-NEXT: [[STOF:%.*]] = addrspacecast ptr addrspace(5) [[PTR]] to ptr318; HSA-NEXT: store volatile i32 0, ptr [[STOF]], align 4, !noalias.addrspace [[META1:![0-9]+]]319; HSA-NEXT: ret void320;321 %stof = addrspacecast ptr addrspace(5) %ptr to ptr322 store volatile i32 0, ptr %stof323 ret void324}325 326define amdgpu_kernel void @use_flat_to_group_addrspacecast(ptr %ptr) #1 {327; HSA-LABEL: define {{[^@]+}}@use_flat_to_group_addrspacecast328; HSA-SAME: (ptr [[PTR:%.*]]) #[[ATTR1]] {329; HSA-NEXT: [[FTOS:%.*]] = addrspacecast ptr [[PTR]] to ptr addrspace(3)330; HSA-NEXT: store volatile i32 0, ptr addrspace(3) [[FTOS]], align 4331; HSA-NEXT: ret void332;333 %ftos = addrspacecast ptr %ptr to ptr addrspace(3)334 store volatile i32 0, ptr addrspace(3) %ftos335 ret void336}337 338define amdgpu_kernel void @use_flat_to_private_addrspacecast(ptr %ptr) #1 {339; HSA-LABEL: define {{[^@]+}}@use_flat_to_private_addrspacecast340; HSA-SAME: (ptr [[PTR:%.*]]) #[[ATTR1]] {341; HSA-NEXT: [[FTOS:%.*]] = addrspacecast ptr [[PTR]] to ptr addrspace(5)342; HSA-NEXT: store volatile i32 0, ptr addrspace(5) [[FTOS]], align 4343; HSA-NEXT: ret void344;345 %ftos = addrspacecast ptr %ptr to ptr addrspace(5)346 store volatile i32 0, ptr addrspace(5) %ftos347 ret void348}349 350; No-op addrspacecast should not use queue ptr351define amdgpu_kernel void @use_global_to_flat_addrspacecast(ptr addrspace(1) %ptr) #1 {352; HSA-LABEL: define {{[^@]+}}@use_global_to_flat_addrspacecast353; HSA-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR1]] {354; HSA-NEXT: [[STOF:%.*]] = addrspacecast ptr addrspace(1) [[PTR]] to ptr355; HSA-NEXT: store volatile i32 0, ptr [[STOF]], align 4, !noalias.addrspace [[META2:![0-9]+]]356; HSA-NEXT: ret void357;358 %stof = addrspacecast ptr addrspace(1) %ptr to ptr359 store volatile i32 0, ptr %stof360 ret void361}362 363define amdgpu_kernel void @use_constant_to_flat_addrspacecast(ptr addrspace(4) %ptr) #1 {364; HSA-LABEL: define {{[^@]+}}@use_constant_to_flat_addrspacecast365; HSA-SAME: (ptr addrspace(4) [[PTR:%.*]]) #[[ATTR1]] {366; HSA-NEXT: [[STOF:%.*]] = addrspacecast ptr addrspace(4) [[PTR]] to ptr367; HSA-NEXT: [[LD:%.*]] = load volatile i32, ptr [[STOF]], align 4, !noalias.addrspace [[META3:![0-9]+]]368; HSA-NEXT: ret void369;370 %stof = addrspacecast ptr addrspace(4) %ptr to ptr371 %ld = load volatile i32, ptr %stof372 ret void373}374 375define amdgpu_kernel void @use_flat_to_global_addrspacecast(ptr %ptr) #1 {376; HSA-LABEL: define {{[^@]+}}@use_flat_to_global_addrspacecast377; HSA-SAME: (ptr [[PTR:%.*]]) #[[ATTR1]] {378; HSA-NEXT: [[FTOS:%.*]] = addrspacecast ptr [[PTR]] to ptr addrspace(1)379; HSA-NEXT: store volatile i32 0, ptr addrspace(1) [[FTOS]], align 4380; HSA-NEXT: ret void381;382 %ftos = addrspacecast ptr %ptr to ptr addrspace(1)383 store volatile i32 0, ptr addrspace(1) %ftos384 ret void385}386 387define amdgpu_kernel void @use_flat_to_constant_addrspacecast(ptr %ptr) #1 {388; HSA-LABEL: define {{[^@]+}}@use_flat_to_constant_addrspacecast389; HSA-SAME: (ptr [[PTR:%.*]]) #[[ATTR1]] {390; HSA-NEXT: [[FTOS:%.*]] = addrspacecast ptr [[PTR]] to ptr addrspace(4)391; HSA-NEXT: [[LD:%.*]] = load volatile i32, ptr addrspace(4) [[FTOS]], align 4392; HSA-NEXT: ret void393;394 %ftos = addrspacecast ptr %ptr to ptr addrspace(4)395 %ld = load volatile i32, ptr addrspace(4) %ftos396 ret void397}398 399define amdgpu_kernel void @use_is_shared(ptr %ptr) #1 {400; HSA-LABEL: define {{[^@]+}}@use_is_shared401; HSA-SAME: (ptr [[PTR:%.*]]) #[[ATTR12]] {402; HSA-NEXT: [[IS_SHARED:%.*]] = call i1 @llvm.amdgcn.is.shared(ptr [[PTR]])403; HSA-NEXT: [[EXT:%.*]] = zext i1 [[IS_SHARED]] to i32404; HSA-NEXT: store i32 [[EXT]], ptr addrspace(1) poison, align 4405; HSA-NEXT: ret void406;407 %is.shared = call i1 @llvm.amdgcn.is.shared(ptr %ptr)408 %ext = zext i1 %is.shared to i32409 store i32 %ext, ptr addrspace(1) poison410 ret void411}412 413define amdgpu_kernel void @use_is_private(ptr %ptr) #1 {414; HSA-LABEL: define {{[^@]+}}@use_is_private415; HSA-SAME: (ptr [[PTR:%.*]]) #[[ATTR12]] {416; HSA-NEXT: [[IS_PRIVATE:%.*]] = call i1 @llvm.amdgcn.is.private(ptr [[PTR]])417; HSA-NEXT: [[EXT:%.*]] = zext i1 [[IS_PRIVATE]] to i32418; HSA-NEXT: store i32 [[EXT]], ptr addrspace(1) poison, align 4419; HSA-NEXT: ret void420;421 %is.private = call i1 @llvm.amdgcn.is.private(ptr %ptr)422 %ext = zext i1 %is.private to i32423 store i32 %ext, ptr addrspace(1) poison424 ret void425}426 427define amdgpu_kernel void @use_alloca() #1 {428; HSA-LABEL: define {{[^@]+}}@use_alloca429; HSA-SAME: () #[[ATTR1]] {430; HSA-NEXT: [[ALLOCA:%.*]] = alloca i32, align 4, addrspace(5)431; HSA-NEXT: store i32 0, ptr addrspace(5) [[ALLOCA]], align 4432; HSA-NEXT: ret void433;434 %alloca = alloca i32, addrspace(5)435 store i32 0, ptr addrspace(5) %alloca436 ret void437}438 439define amdgpu_kernel void @use_alloca_non_entry_block() #1 {440; HSA-LABEL: define {{[^@]+}}@use_alloca_non_entry_block441; HSA-SAME: () #[[ATTR1]] {442; HSA-NEXT: entry:443; HSA-NEXT: br label [[BB:%.*]]444; HSA: bb:445; HSA-NEXT: [[ALLOCA:%.*]] = alloca i32, align 4, addrspace(5)446; HSA-NEXT: store i32 0, ptr addrspace(5) [[ALLOCA]], align 4447; HSA-NEXT: ret void448;449entry:450 br label %bb451 452bb:453 %alloca = alloca i32, addrspace(5)454 store i32 0, ptr addrspace(5) %alloca455 ret void456}457 458define void @use_alloca_func() #1 {459; HSA-LABEL: define {{[^@]+}}@use_alloca_func460; HSA-SAME: () #[[ATTR1]] {461; HSA-NEXT: [[ALLOCA:%.*]] = alloca i32, align 4, addrspace(5)462; HSA-NEXT: store i32 0, ptr addrspace(5) [[ALLOCA]], align 4463; HSA-NEXT: ret void464;465 %alloca = alloca i32, addrspace(5)466 store i32 0, ptr addrspace(5) %alloca467 ret void468}469 470attributes #0 = { nounwind readnone speculatable }471attributes #1 = { nounwind }472 473 474; AKF_HSA: [[META0:![0-9]+]] = !{i32 1, !"amdhsa_code_object_version", i32 500}475;.476; HSA: attributes #[[ATTR0:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }477; HSA: attributes #[[ATTR1]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" }478; HSA: attributes #[[ATTR2]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" }479; HSA: attributes #[[ATTR3]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" }480; HSA: attributes #[[ATTR4]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" }481; HSA: attributes #[[ATTR5]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" }482; HSA: attributes #[[ATTR6]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "uniform-work-group-size"="false" }483; HSA: attributes #[[ATTR7]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" }484; HSA: attributes #[[ATTR8]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "uniform-work-group-size"="false" }485; HSA: attributes #[[ATTR9]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workitem-id-x" "uniform-work-group-size"="false" }486; HSA: attributes #[[ATTR10]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" }487; HSA: attributes #[[ATTR11]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" }488; HSA: attributes #[[ATTR12]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" }489; HSA: attributes #[[ATTR13]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" }490;.491; HSA: [[META0]] = !{i32 1, i32 3, i32 4, i32 10}492; HSA: [[META1]] = !{i32 1, i32 5, i32 6, i32 10}493; HSA: [[META2]] = !{i32 2, i32 10}494; HSA: [[META3]] = !{i32 1, i32 4, i32 5, i32 10}495;.496