307 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-globals2; RUN: opt -S -mtriple=amdgcn-unknown-unknown -passes=amdgpu-attributor < %s | FileCheck %s3 4declare i32 @llvm.r600.read.tgid.x() #05declare i32 @llvm.r600.read.tgid.y() #06declare i32 @llvm.r600.read.tgid.z() #07 8declare i32 @llvm.r600.read.tidig.x() #09declare i32 @llvm.r600.read.tidig.y() #010declare i32 @llvm.r600.read.tidig.z() #011 12declare i32 @llvm.r600.read.local.size.x() #013declare i32 @llvm.r600.read.local.size.y() #014declare i32 @llvm.r600.read.local.size.z() #015 16define amdgpu_kernel void @use_tgid_x(ptr addrspace(1) %ptr) #1 {17; CHECK-LABEL: define {{[^@]+}}@use_tgid_x18; CHECK-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR1:[0-9]+]] {19; CHECK-NEXT: [[VAL:%.*]] = call i32 @llvm.r600.read.tgid.x()20; CHECK-NEXT: store i32 [[VAL]], ptr addrspace(1) [[PTR]], align 421; CHECK-NEXT: ret void22;23 %val = call i32 @llvm.r600.read.tgid.x()24 store i32 %val, ptr addrspace(1) %ptr25 ret void26}27 28define amdgpu_kernel void @use_tgid_y(ptr addrspace(1) %ptr) #1 {29; CHECK-LABEL: define {{[^@]+}}@use_tgid_y30; CHECK-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR2:[0-9]+]] {31; CHECK-NEXT: [[VAL:%.*]] = call i32 @llvm.r600.read.tgid.y()32; CHECK-NEXT: store i32 [[VAL]], ptr addrspace(1) [[PTR]], align 433; CHECK-NEXT: ret void34;35 %val = call i32 @llvm.r600.read.tgid.y()36 store i32 %val, ptr addrspace(1) %ptr37 ret void38}39 40define amdgpu_kernel void @multi_use_tgid_y(ptr addrspace(1) %ptr) #1 {41; CHECK-LABEL: define {{[^@]+}}@multi_use_tgid_y42; CHECK-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR2]] {43; CHECK-NEXT: [[VAL0:%.*]] = call i32 @llvm.r600.read.tgid.y()44; CHECK-NEXT: store volatile i32 [[VAL0]], ptr addrspace(1) [[PTR]], align 445; CHECK-NEXT: [[VAL1:%.*]] = call i32 @llvm.r600.read.tgid.y()46; CHECK-NEXT: store volatile i32 [[VAL1]], ptr addrspace(1) [[PTR]], align 447; CHECK-NEXT: ret void48;49 %val0 = call i32 @llvm.r600.read.tgid.y()50 store volatile i32 %val0, ptr addrspace(1) %ptr51 %val1 = call i32 @llvm.r600.read.tgid.y()52 store volatile i32 %val1, ptr addrspace(1) %ptr53 ret void54}55 56define amdgpu_kernel void @use_tgid_x_y(ptr addrspace(1) %ptr) #1 {57; CHECK-LABEL: define {{[^@]+}}@use_tgid_x_y58; CHECK-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR2]] {59; CHECK-NEXT: [[VAL0:%.*]] = call i32 @llvm.r600.read.tgid.x()60; CHECK-NEXT: [[VAL1:%.*]] = call i32 @llvm.r600.read.tgid.y()61; CHECK-NEXT: store volatile i32 [[VAL0]], ptr addrspace(1) [[PTR]], align 462; CHECK-NEXT: store volatile i32 [[VAL1]], ptr addrspace(1) [[PTR]], align 463; CHECK-NEXT: ret void64;65 %val0 = call i32 @llvm.r600.read.tgid.x()66 %val1 = call i32 @llvm.r600.read.tgid.y()67 store volatile i32 %val0, ptr addrspace(1) %ptr68 store volatile i32 %val1, ptr addrspace(1) %ptr69 ret void70}71 72define amdgpu_kernel void @use_tgid_z(ptr addrspace(1) %ptr) #1 {73; CHECK-LABEL: define {{[^@]+}}@use_tgid_z74; CHECK-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR3:[0-9]+]] {75; CHECK-NEXT: [[VAL:%.*]] = call i32 @llvm.r600.read.tgid.z()76; CHECK-NEXT: store i32 [[VAL]], ptr addrspace(1) [[PTR]], align 477; CHECK-NEXT: ret void78;79 %val = call i32 @llvm.r600.read.tgid.z()80 store i32 %val, ptr addrspace(1) %ptr81 ret void82}83 84define amdgpu_kernel void @use_tgid_x_z(ptr addrspace(1) %ptr) #1 {85; CHECK-LABEL: define {{[^@]+}}@use_tgid_x_z86; CHECK-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR3]] {87; CHECK-NEXT: [[VAL0:%.*]] = call i32 @llvm.r600.read.tgid.x()88; CHECK-NEXT: [[VAL1:%.*]] = call i32 @llvm.r600.read.tgid.z()89; CHECK-NEXT: store volatile i32 [[VAL0]], ptr addrspace(1) [[PTR]], align 490; CHECK-NEXT: store volatile i32 [[VAL1]], ptr addrspace(1) [[PTR]], align 491; CHECK-NEXT: ret void92;93 %val0 = call i32 @llvm.r600.read.tgid.x()94 %val1 = call i32 @llvm.r600.read.tgid.z()95 store volatile i32 %val0, ptr addrspace(1) %ptr96 store volatile i32 %val1, ptr addrspace(1) %ptr97 ret void98}99 100define amdgpu_kernel void @use_tgid_y_z(ptr addrspace(1) %ptr) #1 {101; CHECK-LABEL: define {{[^@]+}}@use_tgid_y_z102; CHECK-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR4:[0-9]+]] {103; CHECK-NEXT: [[VAL0:%.*]] = call i32 @llvm.r600.read.tgid.y()104; CHECK-NEXT: [[VAL1:%.*]] = call i32 @llvm.r600.read.tgid.z()105; CHECK-NEXT: store volatile i32 [[VAL0]], ptr addrspace(1) [[PTR]], align 4106; CHECK-NEXT: store volatile i32 [[VAL1]], ptr addrspace(1) [[PTR]], align 4107; CHECK-NEXT: ret void108;109 %val0 = call i32 @llvm.r600.read.tgid.y()110 %val1 = call i32 @llvm.r600.read.tgid.z()111 store volatile i32 %val0, ptr addrspace(1) %ptr112 store volatile i32 %val1, ptr addrspace(1) %ptr113 ret void114}115 116define amdgpu_kernel void @use_tgid_x_y_z(ptr addrspace(1) %ptr) #1 {117; CHECK-LABEL: define {{[^@]+}}@use_tgid_x_y_z118; CHECK-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR4]] {119; CHECK-NEXT: [[VAL0:%.*]] = call i32 @llvm.r600.read.tgid.x()120; CHECK-NEXT: [[VAL1:%.*]] = call i32 @llvm.r600.read.tgid.y()121; CHECK-NEXT: [[VAL2:%.*]] = call i32 @llvm.r600.read.tgid.z()122; CHECK-NEXT: store volatile i32 [[VAL0]], ptr addrspace(1) [[PTR]], align 4123; CHECK-NEXT: store volatile i32 [[VAL1]], ptr addrspace(1) [[PTR]], align 4124; CHECK-NEXT: store volatile i32 [[VAL2]], ptr addrspace(1) [[PTR]], align 4125; CHECK-NEXT: ret void126;127 %val0 = call i32 @llvm.r600.read.tgid.x()128 %val1 = call i32 @llvm.r600.read.tgid.y()129 %val2 = call i32 @llvm.r600.read.tgid.z()130 store volatile i32 %val0, ptr addrspace(1) %ptr131 store volatile i32 %val1, ptr addrspace(1) %ptr132 store volatile i32 %val2, ptr addrspace(1) %ptr133 ret void134}135 136define amdgpu_kernel void @use_tidig_x(ptr addrspace(1) %ptr) #1 {137; CHECK-LABEL: define {{[^@]+}}@use_tidig_x138; CHECK-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR1]] {139; CHECK-NEXT: [[VAL:%.*]] = call i32 @llvm.r600.read.tidig.x()140; CHECK-NEXT: store i32 [[VAL]], ptr addrspace(1) [[PTR]], align 4141; CHECK-NEXT: ret void142;143 %val = call i32 @llvm.r600.read.tidig.x()144 store i32 %val, ptr addrspace(1) %ptr145 ret void146}147 148define amdgpu_kernel void @use_tidig_y(ptr addrspace(1) %ptr) #1 {149; CHECK-LABEL: define {{[^@]+}}@use_tidig_y150; CHECK-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR5:[0-9]+]] {151; CHECK-NEXT: [[VAL:%.*]] = call i32 @llvm.r600.read.tidig.y()152; CHECK-NEXT: store i32 [[VAL]], ptr addrspace(1) [[PTR]], align 4153; CHECK-NEXT: ret void154;155 %val = call i32 @llvm.r600.read.tidig.y()156 store i32 %val, ptr addrspace(1) %ptr157 ret void158}159 160define amdgpu_kernel void @use_tidig_z(ptr addrspace(1) %ptr) #1 {161; CHECK-LABEL: define {{[^@]+}}@use_tidig_z162; CHECK-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR6:[0-9]+]] {163; CHECK-NEXT: [[VAL:%.*]] = call i32 @llvm.r600.read.tidig.z()164; CHECK-NEXT: store i32 [[VAL]], ptr addrspace(1) [[PTR]], align 4165; CHECK-NEXT: ret void166;167 %val = call i32 @llvm.r600.read.tidig.z()168 store i32 %val, ptr addrspace(1) %ptr169 ret void170}171 172define amdgpu_kernel void @use_tidig_x_tgid_x(ptr addrspace(1) %ptr) #1 {173; CHECK-LABEL: define {{[^@]+}}@use_tidig_x_tgid_x174; CHECK-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR1]] {175; CHECK-NEXT: [[VAL0:%.*]] = call i32 @llvm.r600.read.tidig.x()176; CHECK-NEXT: [[VAL1:%.*]] = call i32 @llvm.r600.read.tgid.x()177; CHECK-NEXT: store volatile i32 [[VAL0]], ptr addrspace(1) [[PTR]], align 4178; CHECK-NEXT: store volatile i32 [[VAL1]], ptr addrspace(1) [[PTR]], align 4179; CHECK-NEXT: ret void180;181 %val0 = call i32 @llvm.r600.read.tidig.x()182 %val1 = call i32 @llvm.r600.read.tgid.x()183 store volatile i32 %val0, ptr addrspace(1) %ptr184 store volatile i32 %val1, ptr addrspace(1) %ptr185 ret void186}187 188define amdgpu_kernel void @use_tidig_y_tgid_y(ptr addrspace(1) %ptr) #1 {189; CHECK-LABEL: define {{[^@]+}}@use_tidig_y_tgid_y190; CHECK-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR7:[0-9]+]] {191; CHECK-NEXT: [[VAL0:%.*]] = call i32 @llvm.r600.read.tidig.y()192; CHECK-NEXT: [[VAL1:%.*]] = call i32 @llvm.r600.read.tgid.y()193; CHECK-NEXT: store volatile i32 [[VAL0]], ptr addrspace(1) [[PTR]], align 4194; CHECK-NEXT: store volatile i32 [[VAL1]], ptr addrspace(1) [[PTR]], align 4195; CHECK-NEXT: ret void196;197 %val0 = call i32 @llvm.r600.read.tidig.y()198 %val1 = call i32 @llvm.r600.read.tgid.y()199 store volatile i32 %val0, ptr addrspace(1) %ptr200 store volatile i32 %val1, ptr addrspace(1) %ptr201 ret void202}203 204define amdgpu_kernel void @use_tidig_x_y_z(ptr addrspace(1) %ptr) #1 {205; CHECK-LABEL: define {{[^@]+}}@use_tidig_x_y_z206; CHECK-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR8:[0-9]+]] {207; CHECK-NEXT: [[VAL0:%.*]] = call i32 @llvm.r600.read.tidig.x()208; CHECK-NEXT: [[VAL1:%.*]] = call i32 @llvm.r600.read.tidig.y()209; CHECK-NEXT: [[VAL2:%.*]] = call i32 @llvm.r600.read.tidig.z()210; CHECK-NEXT: store volatile i32 [[VAL0]], ptr addrspace(1) [[PTR]], align 4211; CHECK-NEXT: store volatile i32 [[VAL1]], ptr addrspace(1) [[PTR]], align 4212; CHECK-NEXT: store volatile i32 [[VAL2]], ptr addrspace(1) [[PTR]], align 4213; CHECK-NEXT: ret void214;215 %val0 = call i32 @llvm.r600.read.tidig.x()216 %val1 = call i32 @llvm.r600.read.tidig.y()217 %val2 = call i32 @llvm.r600.read.tidig.z()218 store volatile i32 %val0, ptr addrspace(1) %ptr219 store volatile i32 %val1, ptr addrspace(1) %ptr220 store volatile i32 %val2, ptr addrspace(1) %ptr221 ret void222}223 224define amdgpu_kernel void @use_all_workitems(ptr addrspace(1) %ptr) #1 {225; CHECK-LABEL: define {{[^@]+}}@use_all_workitems226; CHECK-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR9:[0-9]+]] {227; CHECK-NEXT: [[VAL0:%.*]] = call i32 @llvm.r600.read.tidig.x()228; CHECK-NEXT: [[VAL1:%.*]] = call i32 @llvm.r600.read.tidig.y()229; CHECK-NEXT: [[VAL2:%.*]] = call i32 @llvm.r600.read.tidig.z()230; CHECK-NEXT: [[VAL3:%.*]] = call i32 @llvm.r600.read.tgid.x()231; CHECK-NEXT: [[VAL4:%.*]] = call i32 @llvm.r600.read.tgid.y()232; CHECK-NEXT: [[VAL5:%.*]] = call i32 @llvm.r600.read.tgid.z()233; CHECK-NEXT: store volatile i32 [[VAL0]], ptr addrspace(1) [[PTR]], align 4234; CHECK-NEXT: store volatile i32 [[VAL1]], ptr addrspace(1) [[PTR]], align 4235; CHECK-NEXT: store volatile i32 [[VAL2]], ptr addrspace(1) [[PTR]], align 4236; CHECK-NEXT: store volatile i32 [[VAL3]], ptr addrspace(1) [[PTR]], align 4237; CHECK-NEXT: store volatile i32 [[VAL4]], ptr addrspace(1) [[PTR]], align 4238; CHECK-NEXT: store volatile i32 [[VAL5]], ptr addrspace(1) [[PTR]], align 4239; CHECK-NEXT: ret void240;241 %val0 = call i32 @llvm.r600.read.tidig.x()242 %val1 = call i32 @llvm.r600.read.tidig.y()243 %val2 = call i32 @llvm.r600.read.tidig.z()244 %val3 = call i32 @llvm.r600.read.tgid.x()245 %val4 = call i32 @llvm.r600.read.tgid.y()246 %val5 = call i32 @llvm.r600.read.tgid.z()247 store volatile i32 %val0, ptr addrspace(1) %ptr248 store volatile i32 %val1, ptr addrspace(1) %ptr249 store volatile i32 %val2, ptr addrspace(1) %ptr250 store volatile i32 %val3, ptr addrspace(1) %ptr251 store volatile i32 %val4, ptr addrspace(1) %ptr252 store volatile i32 %val5, ptr addrspace(1) %ptr253 ret void254}255 256define amdgpu_kernel void @use_get_local_size_x(ptr addrspace(1) %ptr) #1 {257; CHECK-LABEL: define {{[^@]+}}@use_get_local_size_x258; CHECK-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR1]] {259; CHECK-NEXT: [[VAL:%.*]] = call i32 @llvm.r600.read.local.size.x()260; CHECK-NEXT: store i32 [[VAL]], ptr addrspace(1) [[PTR]], align 4261; CHECK-NEXT: ret void262;263 %val = call i32 @llvm.r600.read.local.size.x()264 store i32 %val, ptr addrspace(1) %ptr265 ret void266}267 268define amdgpu_kernel void @use_get_local_size_y(ptr addrspace(1) %ptr) #1 {269; CHECK-LABEL: define {{[^@]+}}@use_get_local_size_y270; CHECK-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR1]] {271; CHECK-NEXT: [[VAL:%.*]] = call i32 @llvm.r600.read.local.size.y()272; CHECK-NEXT: store i32 [[VAL]], ptr addrspace(1) [[PTR]], align 4273; CHECK-NEXT: ret void274;275 %val = call i32 @llvm.r600.read.local.size.y()276 store i32 %val, ptr addrspace(1) %ptr277 ret void278}279 280define amdgpu_kernel void @use_get_local_size_z(ptr addrspace(1) %ptr) #1 {281; CHECK-LABEL: define {{[^@]+}}@use_get_local_size_z282; CHECK-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR1]] {283; CHECK-NEXT: [[VAL:%.*]] = call i32 @llvm.r600.read.local.size.z()284; CHECK-NEXT: store i32 [[VAL]], ptr addrspace(1) [[PTR]], align 4285; CHECK-NEXT: ret void286;287 %val = call i32 @llvm.r600.read.local.size.z()288 store i32 %val, ptr addrspace(1) %ptr289 ret void290}291 292attributes #0 = { nounwind readnone }293attributes #1 = { nounwind }294 295;.296; CHECK: attributes #[[ATTR0:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }297; CHECK: attributes #[[ATTR1]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" }298; CHECK: attributes #[[ATTR2]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" }299; CHECK: attributes #[[ATTR3]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" }300; CHECK: attributes #[[ATTR4]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" }301; CHECK: attributes #[[ATTR5]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" }302; CHECK: attributes #[[ATTR6]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "uniform-work-group-size"="false" }303; CHECK: attributes #[[ATTR7]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" }304; CHECK: attributes #[[ATTR8]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "uniform-work-group-size"="false" }305; CHECK: attributes #[[ATTR9]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workitem-id-x" "uniform-work-group-size"="false" }306;.307