128 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs -run-pass=machine-sink -o - %s | FileCheck %s3 4---5name: func06tracksRegLiveness: true7machineFunctionInfo:8 isEntryFunction: true9 scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'10 frameOffsetReg: '$sgpr7'11body: |12 ; CHECK-LABEL: name: func013 ; CHECK: bb.0:14 ; CHECK-NEXT: successors: %bb.1(0x80000000)15 ; CHECK-NEXT: liveins: $vgpr4, $vgpr616 ; CHECK-NEXT: {{ $}}17 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr618 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr419 ; CHECK-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY1]], [[COPY]], 0, implicit $exec20 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 3121 ; CHECK-NEXT: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 killed [[S_MOV_B32_]], [[V_ADD_U32_e64_]], implicit $exec22 ; CHECK-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[V_ADD_U32_e64_]], killed [[V_LSHRREV_B32_e64_]], 0, implicit $exec23 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 124 ; CHECK-NEXT: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[S_MOV_B32_1]], killed [[V_ADD_U32_e64_1]], implicit $exec25 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 3026 ; CHECK-NEXT: [[V_LSHRREV_B32_e64_1:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 killed [[S_MOV_B32_2]], [[V_ASHRREV_I32_e64_]], implicit $exec27 ; CHECK-NEXT: [[V_ADD_U32_e64_2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[V_ASHRREV_I32_e64_]], killed [[V_LSHRREV_B32_e64_1]], 0, implicit $exec28 ; CHECK-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 -429 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_3]]30 ; CHECK-NEXT: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 killed [[V_ADD_U32_e64_2]], killed [[COPY2]], implicit $exec31 ; CHECK-NEXT: [[V_SUB_U32_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[V_ASHRREV_I32_e64_]], killed [[V_AND_B32_e32_]], 0, implicit $exec32 ; CHECK-NEXT: [[S_MOV_B32_4:%[0-9]+]]:sreg_32 = S_MOV_B32 433 ; CHECK-NEXT: [[V_ADD_U32_e64_3:%[0-9]+]]:vgpr_32 = nsw V_ADD_U32_e64 killed [[V_SUB_U32_e64_]], killed [[S_MOV_B32_4]], 0, implicit $exec34 ; CHECK-NEXT: S_BRANCH %bb.135 ; CHECK-NEXT: {{ $}}36 ; CHECK-NEXT: bb.1:37 ; CHECK-NEXT: successors: %bb.5(0x30000000), %bb.2(0x50000000)38 ; CHECK-NEXT: {{ $}}39 ; CHECK-NEXT: [[V_CMP_LT_I32_e64_:%[0-9]+]]:sreg_32 = V_CMP_LT_I32_e64 [[V_ADD_U32_e64_3]], [[S_MOV_B32_1]], implicit $exec40 ; CHECK-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 $exec_lo, [[V_CMP_LT_I32_e64_]], implicit-def $scc41 ; CHECK-NEXT: $exec_lo = S_MOV_B32_term [[S_XOR_B32_]]42 ; CHECK-NEXT: S_CBRANCH_EXECNZ %bb.2, implicit $exec43 ; CHECK-NEXT: {{ $}}44 ; CHECK-NEXT: bb.5:45 ; CHECK-NEXT: successors: %bb.4(0x80000000)46 ; CHECK-NEXT: {{ $}}47 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[V_CMP_LT_I32_e64_]]48 ; CHECK-NEXT: S_BRANCH %bb.449 ; CHECK-NEXT: {{ $}}50 ; CHECK-NEXT: bb.2:51 ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.3(0x40000000)52 ; CHECK-NEXT: {{ $}}53 ; CHECK-NEXT: [[S_MOV_B32_5:%[0-9]+]]:sreg_32 = S_MOV_B32 154 ; CHECK-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_EQ_U32_e64 [[V_ADD_U32_e64_3]], killed [[S_MOV_B32_5]], implicit $exec55 ; CHECK-NEXT: [[S_XOR_B32_1:%[0-9]+]]:sreg_32 = S_XOR_B32 $exec_lo, [[V_CMP_EQ_U32_e64_]], implicit-def $scc56 ; CHECK-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[V_CMP_LT_I32_e64_]], [[V_CMP_EQ_U32_e64_]], implicit-def $scc57 ; CHECK-NEXT: $exec_lo = S_MOV_B32_term [[S_XOR_B32_1]]58 ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.4, implicit $exec59 ; CHECK-NEXT: S_BRANCH %bb.360 ; CHECK-NEXT: {{ $}}61 ; CHECK-NEXT: bb.3:62 ; CHECK-NEXT: successors: %bb.4(0x80000000)63 ; CHECK-NEXT: {{ $}}64 ; CHECK-NEXT: S_BRANCH %bb.465 ; CHECK-NEXT: {{ $}}66 ; CHECK-NEXT: bb.4:67 ; CHECK-NEXT: [[PHI:%[0-9]+]]:sreg_32 = PHI [[COPY3]], %bb.5, [[S_OR_B32_]], %bb.2, [[S_OR_B32_]], %bb.368 ; CHECK-NEXT: $exec_lo = S_OR_B32 $exec_lo, [[PHI]], implicit-def $scc69 ; CHECK-NEXT: S_ENDPGM 070 bb.0:71 successors: %bb.1(0x80000000); %bb.1(100.00%)72 liveins: $vgpr4, $vgpr673 %7:vgpr_32 = COPY $vgpr674 %5:vgpr_32 = COPY $vgpr475 %9:vgpr_32 = V_ADD_U32_e64 %5:vgpr_32, %7:vgpr_32, 0, implicit $exec76 %11:sreg_32 = S_MOV_B32 3177 %12:vgpr_32 = V_LSHRREV_B32_e64 killed %11:sreg_32, %9:vgpr_32, implicit $exec78 %13:vgpr_32 = V_ADD_U32_e64 %9:vgpr_32, killed %12:vgpr_32, 0, implicit $exec79 %14:sreg_32 = S_MOV_B32 180 %15:vgpr_32 = V_ASHRREV_I32_e64 %14:sreg_32, killed %13:vgpr_32, implicit $exec81 %16:sreg_32 = S_MOV_B32 3082 %17:vgpr_32 = V_LSHRREV_B32_e64 killed %16:sreg_32, %15:vgpr_32, implicit $exec83 %18:vgpr_32 = V_ADD_U32_e64 %15:vgpr_32, killed %17:vgpr_32, 0, implicit $exec84 %19:sreg_32 = S_MOV_B32 -485 %21:vgpr_32 = COPY %19:sreg_3286 %20:vgpr_32 = V_AND_B32_e32 killed %18:vgpr_32, killed %21:vgpr_32, implicit $exec87 %22:vgpr_32 = V_SUB_U32_e64 %15:vgpr_32, killed %20:vgpr_32, 0, implicit $exec88 %23:sreg_32 = S_MOV_B32 489 %0:vgpr_32 = nsw V_ADD_U32_e64 killed %22:vgpr_32, killed %23:sreg_32, 0, implicit $exec90 S_BRANCH %bb.191 92 bb.1:93 ; predecessors: %bb.094 successors: %bb.4(0x30000000), %bb.2(0x50000000); %bb.4(37.50%), %bb.2(62.50%)95 96 %25:sreg_32 = V_CMP_LT_I32_e64 %0:vgpr_32, %14:sreg_32, implicit $exec97 %28:sreg_32 = S_XOR_B32 $exec_lo, %25:sreg_32, implicit-def $scc98 %33:sreg_32 = COPY %25:sreg_3299 $exec_lo = S_MOV_B32_term %28:sreg_32100 S_CBRANCH_EXECZ %bb.4, implicit $exec101 S_BRANCH %bb.2102 103 bb.2:104 ; predecessors: %bb.1105 successors: %bb.4(0x40000000), %bb.3(0x40000000); %bb.4(50.00%), %bb.3(50.00%)106 107 %26:sreg_32 = S_MOV_B32 1108 %27:sreg_32 = V_CMP_EQ_U32_e64 %0:vgpr_32, killed %26:sreg_32, implicit $exec109 %31:sreg_32 = S_XOR_B32 $exec_lo, %27:sreg_32, implicit-def $scc110 %34:sreg_32 = S_OR_B32 %25:sreg_32, %27:sreg_32, implicit-def $scc111 $exec_lo = S_MOV_B32_term %31:sreg_32112 S_CBRANCH_EXECZ %bb.4, implicit $exec113 S_BRANCH %bb.3114 115 bb.3:116 ; predecessors: %bb.2117 successors: %bb.4(0x80000000); %bb.4(100.00%)118 119 S_BRANCH %bb.4120 121 bb.4:122 ; predecessors: %bb.1, %bb.2, %bb.3123 124 %35:sreg_32 = PHI %33:sreg_32, %bb.1, %34:sreg_32, %bb.2, %34:sreg_32, %bb.3125 $exec_lo = S_OR_B32 $exec_lo, %35:sreg_32, implicit-def $scc126 S_ENDPGM 0127...128