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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52;; Test reduction of:3;;4;; DST = ashr i64 X, Y5;;6;; where Y is in the range [63-32] to:7;;8;; DST = [ashr i32 HI(X), (Y & 0x1F), ashr i32 HI(X), 31]9 10; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck %s11 12;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;13; Test range with metadata14;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;15 16define i64 @ashr_metadata(i64 %arg0, ptr %arg1.ptr) {17; CHECK-LABEL: ashr_metadata:18; CHECK: ; %bb.0:19; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)20; CHECK-NEXT: flat_load_dword v0, v[2:3]21; CHECK-NEXT: v_ashrrev_i32_e32 v2, 31, v122; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)23; CHECK-NEXT: v_ashrrev_i32_e32 v0, v0, v124; CHECK-NEXT: v_mov_b32_e32 v1, v225; CHECK-NEXT: s_setpc_b64 s[30:31]26 %shift.amt = load i64, ptr %arg1.ptr, !range !0, !noundef !{}27 %ashr = ashr i64 %arg0, %shift.amt28 ret i64 %ashr29}30 31define amdgpu_ps i64 @ashr_metadata_sgpr_return(i64 inreg %arg0, ptr addrspace(1) inreg %arg1.ptr) {32; CHECK-LABEL: ashr_metadata_sgpr_return:33; CHECK: ; %bb.0:34; CHECK-NEXT: s_load_dword s0, s[2:3], 0x035; CHECK-NEXT: s_ashr_i32 s2, s1, 3136; CHECK-NEXT: s_waitcnt lgkmcnt(0)37; CHECK-NEXT: s_ashr_i32 s0, s1, s038; CHECK-NEXT: s_mov_b32 s1, s239; CHECK-NEXT: ; return to shader part epilog40 %shift.amt = load i64, ptr addrspace(1) %arg1.ptr, !range !0, !noundef !{}41 %ashr = ashr i64 %arg0, %shift.amt42 ret i64 %ashr43}44 45; Exact attribute does not inhibit reduction46define i64 @ashr_exact_metadata(i64 %arg0, ptr %arg1.ptr) {47; CHECK-LABEL: ashr_exact_metadata:48; CHECK: ; %bb.0:49; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)50; CHECK-NEXT: flat_load_dword v0, v[2:3]51; CHECK-NEXT: v_ashrrev_i32_e32 v2, 31, v152; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)53; CHECK-NEXT: v_ashrrev_i32_e32 v0, v0, v154; CHECK-NEXT: v_mov_b32_e32 v1, v255; CHECK-NEXT: s_setpc_b64 s[30:31]56 %shift.amt = load i64, ptr %arg1.ptr, !range !0, !noundef !{}57 %ashr = ashr exact i64 %arg0, %shift.amt58 ret i64 %ashr59}60 61define i64 @ashr_metadata_two_ranges(i64 %arg0, ptr %arg1.ptr) {62; CHECK-LABEL: ashr_metadata_two_ranges:63; CHECK: ; %bb.0:64; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)65; CHECK-NEXT: flat_load_dword v0, v[2:3]66; CHECK-NEXT: v_ashrrev_i32_e32 v2, 31, v167; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)68; CHECK-NEXT: v_ashrrev_i32_e32 v0, v0, v169; CHECK-NEXT: v_mov_b32_e32 v1, v270; CHECK-NEXT: s_setpc_b64 s[30:31]71 %shift.amt = load i64, ptr %arg1.ptr, !range !1, !noundef !{}72 %ashr = ashr i64 %arg0, %shift.amt73 ret i64 %ashr74}75 76; Known minimum is too low. Reduction must not be done.77define i64 @ashr_metadata_out_of_range(i64 %arg0, ptr %arg1.ptr) {78; CHECK-LABEL: ashr_metadata_out_of_range:79; CHECK: ; %bb.0:80; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)81; CHECK-NEXT: flat_load_dword v2, v[2:3]82; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)83; CHECK-NEXT: v_ashrrev_i64 v[0:1], v2, v[0:1]84; CHECK-NEXT: s_setpc_b64 s[30:31]85 %shift.amt = load i64, ptr %arg1.ptr, !range !2, !noundef !{}86 %ashr = ashr i64 %arg0, %shift.amt87 ret i64 %ashr88}89 90; Bounds cannot be truncated to i32 when load is narrowed to i32.91; Reduction must not be done.92; Bounds were chosen so that if bounds were truncated to i32 the93; known minimum would be 32 and the ashr would be erroneously reduced.94define i64 @ashr_metadata_cant_be_narrowed_to_i32(i64 %arg0, ptr %arg1.ptr) {95; CHECK-LABEL: ashr_metadata_cant_be_narrowed_to_i32:96; CHECK: ; %bb.0:97; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)98; CHECK-NEXT: flat_load_dword v2, v[2:3]99; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)100; CHECK-NEXT: v_ashrrev_i64 v[0:1], v2, v[0:1]101; CHECK-NEXT: s_setpc_b64 s[30:31]102 %shift.amt = load i64, ptr %arg1.ptr, !range !3, !noundef !{}103 %ashr = ashr i64 %arg0, %shift.amt104 ret i64 %ashr105}106 107define <2 x i64> @ashr_v2_metadata(<2 x i64> %arg0, ptr %arg1.ptr) {108; CHECK-LABEL: ashr_v2_metadata:109; CHECK: ; %bb.0:110; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)111; CHECK-NEXT: flat_load_dwordx4 v[6:9], v[4:5]112; CHECK-NEXT: v_ashrrev_i32_e32 v5, 31, v1113; CHECK-NEXT: v_ashrrev_i32_e32 v4, 31, v3114; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)115; CHECK-NEXT: v_ashrrev_i32_e32 v0, v6, v1116; CHECK-NEXT: v_ashrrev_i32_e32 v2, v8, v3117; CHECK-NEXT: v_mov_b32_e32 v1, v5118; CHECK-NEXT: v_mov_b32_e32 v3, v4119; CHECK-NEXT: s_setpc_b64 s[30:31]120 %shift.amt = load <2 x i64>, ptr %arg1.ptr, !range !0, !noundef !{}121 %ashr = ashr <2 x i64> %arg0, %shift.amt122 ret <2 x i64> %ashr123}124 125define <2 x i64> @ashr_v2_metadata_63(<2 x i64> %arg0, ptr %arg1.ptr) {126; CHECK-LABEL: ashr_v2_metadata_63:127; CHECK: ; %bb.0:128; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)129; CHECK-NEXT: v_ashrrev_i32_e32 v0, 31, v1130; CHECK-NEXT: v_ashrrev_i32_e32 v2, 31, v3131; CHECK-NEXT: v_mov_b32_e32 v1, v0132; CHECK-NEXT: v_mov_b32_e32 v3, v2133; CHECK-NEXT: s_setpc_b64 s[30:31]134 %shift.amt = load <2 x i64>, ptr %arg1.ptr, !range !4, !noundef !{}135 %ashr = ashr <2 x i64> %arg0, %shift.amt136 ret <2 x i64> %ashr137}138 139; Exact attribute does not inhibit reduction140define <2 x i64> @ashr_exact_v2_metadata(<2 x i64> %arg0, ptr %arg1.ptr) {141; CHECK-LABEL: ashr_exact_v2_metadata:142; CHECK: ; %bb.0:143; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)144; CHECK-NEXT: flat_load_dwordx4 v[6:9], v[4:5]145; CHECK-NEXT: v_ashrrev_i32_e32 v5, 31, v1146; CHECK-NEXT: v_ashrrev_i32_e32 v4, 31, v3147; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)148; CHECK-NEXT: v_ashrrev_i32_e32 v0, v6, v1149; CHECK-NEXT: v_ashrrev_i32_e32 v2, v8, v3150; CHECK-NEXT: v_mov_b32_e32 v1, v5151; CHECK-NEXT: v_mov_b32_e32 v3, v4152; CHECK-NEXT: s_setpc_b64 s[30:31]153 %shift.amt = load <2 x i64>, ptr %arg1.ptr, !range !0, !noundef !{}154 %ashr = ashr exact <2 x i64> %arg0, %shift.amt155 ret <2 x i64> %ashr156}157 158define <3 x i64> @ashr_v3_metadata(<3 x i64> %arg0, ptr %arg1.ptr) {159; CHECK-LABEL: ashr_v3_metadata:160; CHECK: ; %bb.0:161; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)162; CHECK-NEXT: flat_load_dword v0, v[6:7] offset:16163; CHECK-NEXT: flat_load_dwordx4 v[9:12], v[6:7]164; CHECK-NEXT: v_ashrrev_i32_e32 v7, 31, v1165; CHECK-NEXT: v_ashrrev_i32_e32 v8, 31, v3166; CHECK-NEXT: v_ashrrev_i32_e32 v6, 31, v5167; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)168; CHECK-NEXT: v_ashrrev_i32_e32 v4, v0, v5169; CHECK-NEXT: v_ashrrev_i32_e32 v0, v9, v1170; CHECK-NEXT: v_ashrrev_i32_e32 v2, v11, v3171; CHECK-NEXT: v_mov_b32_e32 v1, v7172; CHECK-NEXT: v_mov_b32_e32 v3, v8173; CHECK-NEXT: v_mov_b32_e32 v5, v6174; CHECK-NEXT: s_setpc_b64 s[30:31]175 %shift.amt = load <3 x i64>, ptr %arg1.ptr, !range !0, !noundef !{}176 %ashr = ashr <3 x i64> %arg0, %shift.amt177 ret <3 x i64> %ashr178}179 180define <4 x i64> @ashr_v4_metadata(<4 x i64> %arg0, ptr %arg1.ptr) {181; CHECK-LABEL: ashr_v4_metadata:182; CHECK: ; %bb.0:183; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)184; CHECK-NEXT: flat_load_dwordx4 v[12:15], v[8:9]185; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)186; CHECK-NEXT: flat_load_dwordx4 v[15:18], v[8:9] offset:16187; CHECK-NEXT: ; kill: killed $vgpr8 killed $vgpr9188; CHECK-NEXT: v_ashrrev_i32_e32 v11, 31, v1189; CHECK-NEXT: v_ashrrev_i32_e32 v9, 31, v3190; CHECK-NEXT: v_ashrrev_i32_e32 v10, 31, v5191; CHECK-NEXT: v_ashrrev_i32_e32 v8, 31, v7192; CHECK-NEXT: v_ashrrev_i32_e32 v0, v12, v1193; CHECK-NEXT: v_ashrrev_i32_e32 v2, v14, v3194; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)195; CHECK-NEXT: v_ashrrev_i32_e32 v4, v15, v5196; CHECK-NEXT: v_ashrrev_i32_e32 v6, v17, v7197; CHECK-NEXT: v_mov_b32_e32 v1, v11198; CHECK-NEXT: v_mov_b32_e32 v3, v9199; CHECK-NEXT: v_mov_b32_e32 v5, v10200; CHECK-NEXT: v_mov_b32_e32 v7, v8201; CHECK-NEXT: s_setpc_b64 s[30:31]202 %shift.amt = load <4 x i64>, ptr %arg1.ptr, !range !0, !noundef !{}203 %ashr = ashr <4 x i64> %arg0, %shift.amt204 ret <4 x i64> %ashr205}206 207!0 = !{i64 32, i64 64}208!1 = !{i64 32, i64 38, i64 42, i64 48}209!2 = !{i64 31, i64 38, i64 42, i64 48}210!3 = !{i64 32, i64 38, i64 2147483680, i64 2147483681}211!4 = !{i64 63, i64 64}212 213;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;214; Test range with an "or X, 16"215;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;216 217; These cases must not be reduced because the known minimum, 16, is not in range.218 219define i64 @ashr_or16(i64 %arg0, i64 %shift_amt) {220; CHECK-LABEL: ashr_or16:221; CHECK: ; %bb.0:222; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)223; CHECK-NEXT: v_or_b32_e32 v2, 16, v2224; CHECK-NEXT: v_ashrrev_i64 v[0:1], v2, v[0:1]225; CHECK-NEXT: s_setpc_b64 s[30:31]226 %or = or i64 %shift_amt, 16227 %ashr = ashr i64 %arg0, %or228 ret i64 %ashr229}230 231define <2 x i64> @ashr_v2_or16(<2 x i64> %arg0, <2 x i64> %shift_amt) {232; CHECK-LABEL: ashr_v2_or16:233; CHECK: ; %bb.0:234; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)235; CHECK-NEXT: v_or_b32_e32 v5, 16, v6236; CHECK-NEXT: v_or_b32_e32 v4, 16, v4237; CHECK-NEXT: v_ashrrev_i64 v[0:1], v4, v[0:1]238; CHECK-NEXT: v_ashrrev_i64 v[2:3], v5, v[2:3]239; CHECK-NEXT: s_setpc_b64 s[30:31]240 %or = or <2 x i64> %shift_amt, splat (i64 16)241 %ashr = ashr <2 x i64> %arg0, %or242 ret <2 x i64> %ashr243}244 245define <3 x i64> @ashr_v3_or16(<3 x i64> %arg0, <3 x i64> %shift_amt) {246; CHECK-LABEL: ashr_v3_or16:247; CHECK: ; %bb.0:248; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)249; CHECK-NEXT: v_or_b32_e32 v7, 16, v10250; CHECK-NEXT: v_or_b32_e32 v8, 16, v8251; CHECK-NEXT: v_or_b32_e32 v6, 16, v6252; CHECK-NEXT: v_ashrrev_i64 v[0:1], v6, v[0:1]253; CHECK-NEXT: v_ashrrev_i64 v[2:3], v8, v[2:3]254; CHECK-NEXT: v_ashrrev_i64 v[4:5], v7, v[4:5]255; CHECK-NEXT: s_setpc_b64 s[30:31]256 %or = or <3 x i64> %shift_amt, splat (i64 16)257 %ashr = ashr <3 x i64> %arg0, %or258 ret <3 x i64> %ashr259}260 261define <4 x i64> @ashr_v4_or16(<4 x i64> %arg0, <4 x i64> %shift_amt) {262; CHECK-LABEL: ashr_v4_or16:263; CHECK: ; %bb.0:264; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)265; CHECK-NEXT: v_or_b32_e32 v9, 16, v14266; CHECK-NEXT: v_or_b32_e32 v11, 16, v12267; CHECK-NEXT: v_or_b32_e32 v10, 16, v10268; CHECK-NEXT: v_or_b32_e32 v8, 16, v8269; CHECK-NEXT: v_ashrrev_i64 v[0:1], v8, v[0:1]270; CHECK-NEXT: v_ashrrev_i64 v[2:3], v10, v[2:3]271; CHECK-NEXT: v_ashrrev_i64 v[4:5], v11, v[4:5]272; CHECK-NEXT: v_ashrrev_i64 v[6:7], v9, v[6:7]273; CHECK-NEXT: s_setpc_b64 s[30:31]274 %or = or <4 x i64> %shift_amt, splat (i64 16)275 %ashr = ashr <4 x i64> %arg0, %or276 ret <4 x i64> %ashr277}278 279; test SGPR280 281define i64 @ashr_or16_sgpr(i64 inreg %arg0, i64 inreg %shift_amt) {282; CHECK-LABEL: ashr_or16_sgpr:283; CHECK: ; %bb.0:284; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)285; CHECK-NEXT: s_or_b32 s4, s18, 16286; CHECK-NEXT: s_ashr_i64 s[4:5], s[16:17], s4287; CHECK-NEXT: v_mov_b32_e32 v0, s4288; CHECK-NEXT: v_mov_b32_e32 v1, s5289; CHECK-NEXT: s_setpc_b64 s[30:31]290 %or = or i64 %shift_amt, 16291 %ashr = ashr i64 %arg0, %or292 ret i64 %ashr293}294 295define amdgpu_ps i64 @ashr_or16_sgpr_return(i64 inreg %arg0, i64 inreg %shift_amt) {296; CHECK-LABEL: ashr_or16_sgpr_return:297; CHECK: ; %bb.0:298; CHECK-NEXT: s_or_b32 s2, s2, 16299; CHECK-NEXT: s_ashr_i64 s[0:1], s[0:1], s2300; CHECK-NEXT: ; return to shader part epilog301 %or = or i64 %shift_amt, 16302 %ashr = ashr i64 %arg0, %or303 ret i64 %ashr304}305 306define <2 x i64> @ashr_v2_or16_sgpr(<2 x i64> inreg %arg0, <2 x i64> inreg %shift_amt) {307; CHECK-LABEL: ashr_v2_or16_sgpr:308; CHECK: ; %bb.0:309; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)310; CHECK-NEXT: s_or_b32 s6, s22, 16311; CHECK-NEXT: s_or_b32 s4, s20, 16312; CHECK-NEXT: s_ashr_i64 s[4:5], s[16:17], s4313; CHECK-NEXT: s_ashr_i64 s[6:7], s[18:19], s6314; CHECK-NEXT: v_mov_b32_e32 v0, s4315; CHECK-NEXT: v_mov_b32_e32 v1, s5316; CHECK-NEXT: v_mov_b32_e32 v2, s6317; CHECK-NEXT: v_mov_b32_e32 v3, s7318; CHECK-NEXT: s_setpc_b64 s[30:31]319 %or = or <2 x i64> %shift_amt, splat (i64 16)320 %ashr = ashr <2 x i64> %arg0, %or321 ret <2 x i64> %ashr322}323 324define <3 x i64> @ashr_v3_or16_sgpr(<3 x i64> inreg %arg0, <3 x i64> inreg %shift_amt) {325; CHECK-LABEL: ashr_v3_or16_sgpr:326; CHECK: ; %bb.0:327; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)328; CHECK-NEXT: s_or_b32 s8, s26, 16329; CHECK-NEXT: s_or_b32 s6, s24, 16330; CHECK-NEXT: s_or_b32 s4, s22, 16331; CHECK-NEXT: s_ashr_i64 s[4:5], s[16:17], s4332; CHECK-NEXT: s_ashr_i64 s[6:7], s[18:19], s6333; CHECK-NEXT: s_ashr_i64 s[8:9], s[20:21], s8334; CHECK-NEXT: v_mov_b32_e32 v0, s4335; CHECK-NEXT: v_mov_b32_e32 v1, s5336; CHECK-NEXT: v_mov_b32_e32 v2, s6337; CHECK-NEXT: v_mov_b32_e32 v3, s7338; CHECK-NEXT: v_mov_b32_e32 v4, s8339; CHECK-NEXT: v_mov_b32_e32 v5, s9340; CHECK-NEXT: s_setpc_b64 s[30:31]341 %or = or <3 x i64> %shift_amt, splat (i64 16)342 %ashr = ashr <3 x i64> %arg0, %or343 ret <3 x i64> %ashr344}345 346define <4 x i64> @ashr_v4_or16_sgpr(<4 x i64> inreg %arg0, <4 x i64> inreg %shift_amt) {347; CHECK-LABEL: ashr_v4_or16_sgpr:348; CHECK: ; %bb.0:349; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)350; CHECK-NEXT: v_or_b32_e32 v0, 16, v0351; CHECK-NEXT: s_or_b32 s8, s28, 16352; CHECK-NEXT: s_or_b32 s6, s26, 16353; CHECK-NEXT: s_or_b32 s4, s24, 16354; CHECK-NEXT: s_ashr_i64 s[4:5], s[16:17], s4355; CHECK-NEXT: s_ashr_i64 s[6:7], s[18:19], s6356; CHECK-NEXT: s_ashr_i64 s[8:9], s[20:21], s8357; CHECK-NEXT: v_ashrrev_i64 v[6:7], v0, s[22:23]358; CHECK-NEXT: v_mov_b32_e32 v0, s4359; CHECK-NEXT: v_mov_b32_e32 v1, s5360; CHECK-NEXT: v_mov_b32_e32 v2, s6361; CHECK-NEXT: v_mov_b32_e32 v3, s7362; CHECK-NEXT: v_mov_b32_e32 v4, s8363; CHECK-NEXT: v_mov_b32_e32 v5, s9364; CHECK-NEXT: s_setpc_b64 s[30:31]365 %or = or <4 x i64> %shift_amt, splat (i64 16)366 %ashr = ashr <4 x i64> %arg0, %or367 ret <4 x i64> %ashr368}369 370;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;371; Test range with an "or X, 32"372;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;373 374; These cases are reduced because computeKnownBits() can calculate a minimum of 32375; based on the OR with 32.376 377define i64 @ashr_or32(i64 %arg0, i64 %shift_amt) {378; CHECK-LABEL: ashr_or32:379; CHECK: ; %bb.0:380; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)381; CHECK-NEXT: v_ashrrev_i32_e32 v0, v2, v1382; CHECK-NEXT: v_ashrrev_i32_e32 v1, 31, v1383; CHECK-NEXT: s_setpc_b64 s[30:31]384 %or = or i64 %shift_amt, 32385 %ashr = ashr i64 %arg0, %or386 ret i64 %ashr387}388 389define <2 x i64> @ashr_v2_or32(<2 x i64> %arg0, <2 x i64> %shift_amt) {390; CHECK-LABEL: ashr_v2_or32:391; CHECK: ; %bb.0:392; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)393; CHECK-NEXT: v_ashrrev_i32_e32 v0, v4, v1394; CHECK-NEXT: v_ashrrev_i32_e32 v1, 31, v1395; CHECK-NEXT: v_ashrrev_i32_e32 v2, v6, v3396; CHECK-NEXT: v_ashrrev_i32_e32 v3, 31, v3397; CHECK-NEXT: s_setpc_b64 s[30:31]398 %or = or <2 x i64> %shift_amt, splat (i64 32)399 %ashr = ashr <2 x i64> %arg0, %or400 ret <2 x i64> %ashr401}402 403define <3 x i64> @ashr_v3_or32(<3 x i64> %arg0, <3 x i64> %shift_amt) {404; CHECK-LABEL: ashr_v3_or32:405; CHECK: ; %bb.0:406; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)407; CHECK-NEXT: v_ashrrev_i32_e32 v0, v6, v1408; CHECK-NEXT: v_ashrrev_i32_e32 v1, 31, v1409; CHECK-NEXT: v_ashrrev_i32_e32 v2, v8, v3410; CHECK-NEXT: v_ashrrev_i32_e32 v3, 31, v3411; CHECK-NEXT: v_ashrrev_i32_e32 v4, v10, v5412; CHECK-NEXT: v_ashrrev_i32_e32 v5, 31, v5413; CHECK-NEXT: s_setpc_b64 s[30:31]414 %or = or <3 x i64> %shift_amt, splat (i64 32)415 %ashr = ashr <3 x i64> %arg0, %or416 ret <3 x i64> %ashr417}418 419define <4 x i64> @ashr_v4_or32(<4 x i64> %arg0, <4 x i64> %shift_amt) {420; CHECK-LABEL: ashr_v4_or32:421; CHECK: ; %bb.0:422; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)423; CHECK-NEXT: v_ashrrev_i32_e32 v0, v8, v1424; CHECK-NEXT: v_ashrrev_i32_e32 v1, 31, v1425; CHECK-NEXT: v_ashrrev_i32_e32 v2, v10, v3426; CHECK-NEXT: v_ashrrev_i32_e32 v3, 31, v3427; CHECK-NEXT: v_ashrrev_i32_e32 v4, v12, v5428; CHECK-NEXT: v_ashrrev_i32_e32 v5, 31, v5429; CHECK-NEXT: v_ashrrev_i32_e32 v6, v14, v7430; CHECK-NEXT: v_ashrrev_i32_e32 v7, 31, v7431; CHECK-NEXT: s_setpc_b64 s[30:31]432 %or = or <4 x i64> %shift_amt, splat (i64 32)433 %ashr = ashr <4 x i64> %arg0, %or434 ret <4 x i64> %ashr435}436 437; test SGPR438 439define i64 @ashr_or32_sgpr(i64 inreg %arg0, i64 inreg %shift_amt) {440; CHECK-LABEL: ashr_or32_sgpr:441; CHECK: ; %bb.0:442; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)443; CHECK-NEXT: s_ashr_i32 s4, s17, s18444; CHECK-NEXT: s_ashr_i32 s5, s17, 31445; CHECK-NEXT: v_mov_b32_e32 v0, s4446; CHECK-NEXT: v_mov_b32_e32 v1, s5447; CHECK-NEXT: s_setpc_b64 s[30:31]448 %or = or i64 %shift_amt, 32449 %ashr = ashr i64 %arg0, %or450 ret i64 %ashr451}452 453define amdgpu_ps i64 @ashr_or32_sgpr_return(i64 inreg %arg0, i64 inreg %shift_amt) {454; CHECK-LABEL: ashr_or32_sgpr_return:455; CHECK: ; %bb.0:456; CHECK-NEXT: s_ashr_i32 s0, s1, s2457; CHECK-NEXT: s_ashr_i32 s1, s1, 31458; CHECK-NEXT: ; return to shader part epilog459 %or = or i64 %shift_amt, 32460 %ashr = ashr i64 %arg0, %or461 ret i64 %ashr462}463 464define <2 x i64> @ashr_v2_or32_sgpr(<2 x i64> inreg %arg0, <2 x i64> inreg %shift_amt) {465; CHECK-LABEL: ashr_v2_or32_sgpr:466; CHECK: ; %bb.0:467; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)468; CHECK-NEXT: s_ashr_i32 s4, s17, s20469; CHECK-NEXT: s_ashr_i32 s5, s17, 31470; CHECK-NEXT: s_ashr_i32 s6, s19, s22471; CHECK-NEXT: s_ashr_i32 s7, s19, 31472; CHECK-NEXT: v_mov_b32_e32 v0, s4473; CHECK-NEXT: v_mov_b32_e32 v1, s5474; CHECK-NEXT: v_mov_b32_e32 v2, s6475; CHECK-NEXT: v_mov_b32_e32 v3, s7476; CHECK-NEXT: s_setpc_b64 s[30:31]477 %or = or <2 x i64> %shift_amt, splat (i64 32)478 %ashr = ashr <2 x i64> %arg0, %or479 ret <2 x i64> %ashr480}481 482define <3 x i64> @ashr_v3_or32_sgpr(<3 x i64> inreg %arg0, <3 x i64> inreg %shift_amt) {483; CHECK-LABEL: ashr_v3_or32_sgpr:484; CHECK: ; %bb.0:485; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)486; CHECK-NEXT: s_ashr_i32 s4, s17, s22487; CHECK-NEXT: s_ashr_i32 s5, s17, 31488; CHECK-NEXT: s_ashr_i32 s6, s19, s24489; CHECK-NEXT: s_ashr_i32 s7, s19, 31490; CHECK-NEXT: s_ashr_i32 s8, s21, s26491; CHECK-NEXT: s_ashr_i32 s9, s21, 31492; CHECK-NEXT: v_mov_b32_e32 v0, s4493; CHECK-NEXT: v_mov_b32_e32 v1, s5494; CHECK-NEXT: v_mov_b32_e32 v2, s6495; CHECK-NEXT: v_mov_b32_e32 v3, s7496; CHECK-NEXT: v_mov_b32_e32 v4, s8497; CHECK-NEXT: v_mov_b32_e32 v5, s9498; CHECK-NEXT: s_setpc_b64 s[30:31]499 %or = or <3 x i64> %shift_amt, splat (i64 32)500 %ashr = ashr <3 x i64> %arg0, %or501 ret <3 x i64> %ashr502}503 504define <4 x i64> @ashr_v4_or32_sgpr(<4 x i64> inreg %arg0, <4 x i64> inreg %shift_amt) {505; CHECK-LABEL: ashr_v4_or32_sgpr:506; CHECK: ; %bb.0:507; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)508; CHECK-NEXT: s_ashr_i32 s4, s17, s24509; CHECK-NEXT: s_ashr_i32 s5, s17, 31510; CHECK-NEXT: s_ashr_i32 s6, s19, s26511; CHECK-NEXT: s_ashr_i32 s7, s19, 31512; CHECK-NEXT: s_ashr_i32 s8, s21, s28513; CHECK-NEXT: s_ashr_i32 s9, s21, 31514; CHECK-NEXT: s_ashr_i32 s10, s23, 31515; CHECK-NEXT: v_ashrrev_i32_e64 v6, v0, s23516; CHECK-NEXT: v_mov_b32_e32 v0, s4517; CHECK-NEXT: v_mov_b32_e32 v1, s5518; CHECK-NEXT: v_mov_b32_e32 v2, s6519; CHECK-NEXT: v_mov_b32_e32 v3, s7520; CHECK-NEXT: v_mov_b32_e32 v4, s8521; CHECK-NEXT: v_mov_b32_e32 v5, s9522; CHECK-NEXT: v_mov_b32_e32 v7, s10523; CHECK-NEXT: s_setpc_b64 s[30:31]524 %or = or <4 x i64> %shift_amt, splat (i64 32)525 %ashr = ashr <4 x i64> %arg0, %or526 ret <4 x i64> %ashr527}528 529;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;530; Test range from max/min531;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;532 533; FIXME: This case should be reduced too, but computeKnownBits() cannot534; determine the range. Match current results for now.535 536define i64 @ashr_maxmin(i64 %arg0, i64 noundef %arg1) {537; CHECK-LABEL: ashr_maxmin:538; CHECK: ; %bb.0:539; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)540; CHECK-NEXT: v_cmp_lt_u64_e32 vcc, 32, v[2:3]541; CHECK-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc542; CHECK-NEXT: v_cndmask_b32_e32 v2, 32, v2, vcc543; CHECK-NEXT: v_cmp_gt_u64_e32 vcc, 63, v[2:3]544; CHECK-NEXT: v_cndmask_b32_e32 v2, 63, v2, vcc545; CHECK-NEXT: v_ashrrev_i64 v[0:1], v2, v[0:1]546; CHECK-NEXT: s_setpc_b64 s[30:31]547 %max = call i64 @llvm.umax.i64(i64 %arg1, i64 32)548 %min = call i64 @llvm.umin.i64(i64 %max, i64 63)549 %ashr = ashr i64 %arg0, %min550 ret i64 %ashr551}552 553define <2 x i64> @ashr_v2_maxmin(<2 x i64> %arg0, <2 x i64> noundef %arg1) {554; CHECK-LABEL: ashr_v2_maxmin:555; CHECK: ; %bb.0:556; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)557; CHECK-NEXT: v_cmp_lt_u64_e32 vcc, 32, v[4:5]558; CHECK-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc559; CHECK-NEXT: v_cndmask_b32_e32 v4, 32, v4, vcc560; CHECK-NEXT: v_cmp_lt_u64_e32 vcc, 32, v[6:7]561; CHECK-NEXT: v_cndmask_b32_e32 v7, 0, v7, vcc562; CHECK-NEXT: v_cndmask_b32_e32 v6, 32, v6, vcc563; CHECK-NEXT: v_cmp_gt_u64_e32 vcc, 63, v[6:7]564; CHECK-NEXT: v_cndmask_b32_e32 v6, 63, v6, vcc565; CHECK-NEXT: v_cmp_gt_u64_e32 vcc, 63, v[4:5]566; CHECK-NEXT: v_ashrrev_i64 v[2:3], v6, v[2:3]567; CHECK-NEXT: v_cndmask_b32_e32 v4, 63, v4, vcc568; CHECK-NEXT: v_ashrrev_i64 v[0:1], v4, v[0:1]569; CHECK-NEXT: s_setpc_b64 s[30:31]570 %max = call <2 x i64> @llvm.umax.i64(<2 x i64> %arg1, <2 x i64> splat (i64 32))571 %min = call <2 x i64> @llvm.umin.i64(<2 x i64> %max, <2 x i64> splat (i64 63))572 %ashr = ashr <2 x i64> %arg0, %min573 ret <2 x i64> %ashr574}575 576define <3 x i64> @ashr_v3_maxmin(<3 x i64> %arg0, <3 x i64> noundef %arg1) {577; CHECK-LABEL: ashr_v3_maxmin:578; CHECK: ; %bb.0:579; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)580; CHECK-NEXT: v_cmp_lt_u64_e32 vcc, 32, v[6:7]581; CHECK-NEXT: v_cndmask_b32_e32 v7, 0, v7, vcc582; CHECK-NEXT: v_cndmask_b32_e32 v6, 32, v6, vcc583; CHECK-NEXT: v_cmp_lt_u64_e32 vcc, 32, v[8:9]584; CHECK-NEXT: v_cndmask_b32_e32 v9, 0, v9, vcc585; CHECK-NEXT: v_cndmask_b32_e32 v8, 32, v8, vcc586; CHECK-NEXT: v_cmp_lt_u64_e32 vcc, 32, v[10:11]587; CHECK-NEXT: v_cndmask_b32_e32 v11, 0, v11, vcc588; CHECK-NEXT: v_cndmask_b32_e32 v10, 32, v10, vcc589; CHECK-NEXT: v_cmp_gt_u64_e32 vcc, 63, v[10:11]590; CHECK-NEXT: v_cndmask_b32_e32 v10, 63, v10, vcc591; CHECK-NEXT: v_cmp_gt_u64_e32 vcc, 63, v[8:9]592; CHECK-NEXT: v_ashrrev_i64 v[4:5], v10, v[4:5]593; CHECK-NEXT: v_cndmask_b32_e32 v8, 63, v8, vcc594; CHECK-NEXT: v_cmp_gt_u64_e32 vcc, 63, v[6:7]595; CHECK-NEXT: v_ashrrev_i64 v[2:3], v8, v[2:3]596; CHECK-NEXT: v_cndmask_b32_e32 v6, 63, v6, vcc597; CHECK-NEXT: v_ashrrev_i64 v[0:1], v6, v[0:1]598; CHECK-NEXT: s_setpc_b64 s[30:31]599 %max = call <3 x i64> @llvm.umax.i64(<3 x i64> %arg1, <3 x i64> splat (i64 32))600 %min = call <3 x i64> @llvm.umin.i64(<3 x i64> %max, <3 x i64> splat (i64 63))601 %ashr = ashr <3 x i64> %arg0, %min602 ret <3 x i64> %ashr603}604 605define <4 x i64> @ashr_v4_maxmin(<4 x i64> %arg0, <4 x i64> noundef %arg1) {606; CHECK-LABEL: ashr_v4_maxmin:607; CHECK: ; %bb.0:608; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)609; CHECK-NEXT: v_cmp_lt_u64_e32 vcc, 32, v[8:9]610; CHECK-NEXT: v_cndmask_b32_e32 v9, 0, v9, vcc611; CHECK-NEXT: v_cndmask_b32_e32 v8, 32, v8, vcc612; CHECK-NEXT: v_cmp_lt_u64_e32 vcc, 32, v[10:11]613; CHECK-NEXT: v_cndmask_b32_e32 v11, 0, v11, vcc614; CHECK-NEXT: v_cndmask_b32_e32 v10, 32, v10, vcc615; CHECK-NEXT: v_cmp_lt_u64_e32 vcc, 32, v[12:13]616; CHECK-NEXT: v_cndmask_b32_e32 v13, 0, v13, vcc617; CHECK-NEXT: v_cndmask_b32_e32 v12, 32, v12, vcc618; CHECK-NEXT: v_cmp_lt_u64_e32 vcc, 32, v[14:15]619; CHECK-NEXT: v_cndmask_b32_e32 v15, 0, v15, vcc620; CHECK-NEXT: v_cndmask_b32_e32 v14, 32, v14, vcc621; CHECK-NEXT: v_cmp_gt_u64_e32 vcc, 63, v[14:15]622; CHECK-NEXT: v_cndmask_b32_e32 v14, 63, v14, vcc623; CHECK-NEXT: v_cmp_gt_u64_e32 vcc, 63, v[12:13]624; CHECK-NEXT: v_ashrrev_i64 v[6:7], v14, v[6:7]625; CHECK-NEXT: v_cndmask_b32_e32 v12, 63, v12, vcc626; CHECK-NEXT: v_cmp_gt_u64_e32 vcc, 63, v[10:11]627; CHECK-NEXT: v_ashrrev_i64 v[4:5], v12, v[4:5]628; CHECK-NEXT: v_cndmask_b32_e32 v10, 63, v10, vcc629; CHECK-NEXT: v_cmp_gt_u64_e32 vcc, 63, v[8:9]630; CHECK-NEXT: v_ashrrev_i64 v[2:3], v10, v[2:3]631; CHECK-NEXT: v_cndmask_b32_e32 v8, 63, v8, vcc632; CHECK-NEXT: v_ashrrev_i64 v[0:1], v8, v[0:1]633; CHECK-NEXT: s_setpc_b64 s[30:31]634 %max = call <4 x i64> @llvm.umax.i64(<4 x i64> %arg1, <4 x i64> splat (i64 32))635 %min = call <4 x i64> @llvm.umin.i64(<4 x i64> %max, <4 x i64> splat (i64 63))636 %ashr = ashr <4 x i64> %arg0, %min637 ret <4 x i64> %ashr638}639