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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck %s -check-prefixes=GFX103 4declare void @llvm.amdgcn.exp.f32(i32 immarg, i32 immarg, float, float, float, float, i1 immarg, i1 immarg)5declare i32 @llvm.amdgcn.raw.ptr.buffer.atomic.and.i32(i32, ptr addrspace(8), i32, i32, i32 immarg)6declare float @llvm.amdgcn.strict.wqm.f32(float)7 8define amdgpu_ps void @main(i32 %arg) {9; GFX10-LABEL: main:10; GFX10: ; %bb.0: ; %bb11; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v012; GFX10-NEXT: v_mov_b32_e32 v0, 013; GFX10-NEXT: s_mov_b32 s1, exec_lo14; GFX10-NEXT: s_mov_b32 s4, 015; GFX10-NEXT: s_mov_b32 s2, 016; GFX10-NEXT: s_branch .LBB0_217; GFX10-NEXT: .LBB0_1: ; in Loop: Header=BB0_2 Depth=118; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)19; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s320; GFX10-NEXT: s_and_b32 s0, exec_lo, vcc_lo21; GFX10-NEXT: s_or_b32 s2, s0, s222; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s223; GFX10-NEXT: s_cbranch_execz .LBB0_524; GFX10-NEXT: .LBB0_2: ; %bb425; GFX10-NEXT: ; =>This Inner Loop Header: Depth=126; GFX10-NEXT: s_and_saveexec_b32 s3, s127; GFX10-NEXT: s_cbranch_execz .LBB0_128; GFX10-NEXT: ; %bb.3: ; in Loop: Header=BB0_2 Depth=129; GFX10-NEXT: v_mbcnt_lo_u32_b32 v1, exec_lo, 030; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 0, v131; GFX10-NEXT: s_and_b32 exec_lo, exec_lo, s032; GFX10-NEXT: s_cbranch_execz .LBB0_133; GFX10-NEXT: ; %bb.4: ; in Loop: Header=BB0_2 Depth=134; GFX10-NEXT: s_mov_b32 s5, s435; GFX10-NEXT: s_mov_b32 s6, s436; GFX10-NEXT: s_mov_b32 s7, s437; GFX10-NEXT: buffer_atomic_and v0, off, s[4:7], 038; GFX10-NEXT: s_branch .LBB0_139; GFX10-NEXT: .LBB0_5: ; %bb840; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s241; GFX10-NEXT: s_mov_b32 s0, 042; GFX10-NEXT: v_mov_b32_e32 v1, 043; GFX10-NEXT: v_mov_b32_e32 v0, s044; GFX10-NEXT: exp mrt0 off, off, off, off45; GFX10-NEXT: s_endpgm46bb:47 br label %bb448 49bb4:50 %i5 = call i32 @llvm.amdgcn.raw.ptr.buffer.atomic.and.i32(i32 0, ptr addrspace(8) null, i32 0, i32 0, i32 0)51 %i7 = icmp eq i32 %arg, 152 br i1 %i7, label %bb8, label %bb453 54bb8:55 %i9 = call float @llvm.amdgcn.strict.wqm.f32(float 0.0)56 call void @llvm.amdgcn.exp.f32(i32 0, i32 0, float %i9, float 0.0, float 0.0, float 0.0, i1 false, i1 false)57 ret void58}59