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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 42; RUN: opt -mtriple=amdgcn-- -mcpu=gfx908 -passes="amdgpu-atomic-optimizer,verify<domtree>" %s -S -o - | FileCheck %s3 4; Check we're properly adding an edge from ComputeEnd to the "End" block added by5; SplitBlockAndInsertIfThen6;7; If the edge is not added, domtree verification will fail.8 9declare i32 @quux()10 11define amdgpu_kernel void @ham(ptr addrspace(4) %arg) {12; CHECK-LABEL: define amdgpu_kernel void @ham(13; CHECK-SAME: ptr addrspace(4) [[ARG:%.*]]) #[[ATTR0:[0-9]+]] {14; CHECK-NEXT: bb:15; CHECK-NEXT: [[CALL:%.*]] = tail call i32 @quux()16; CHECK-NEXT: [[ICMP:%.*]] = icmp eq i32 [[CALL]], 017; CHECK-NEXT: br i1 [[ICMP]], label [[BB1:%.*]], label [[BB3:%.*]]18; CHECK: bb1:19; CHECK-NEXT: [[CALL2:%.*]] = tail call i32 @quux()20; CHECK-NEXT: br label [[BB3]]21; CHECK: bb3:22; CHECK-NEXT: [[PHI:%.*]] = phi i32 [ [[CALL2]], [[BB1]] ], [ [[CALL]], [[BB:%.*]] ]23; CHECK-NEXT: br label [[BB4:%.*]]24; CHECK: bb4:25; CHECK-NEXT: [[CALL5:%.*]] = tail call i32 @quux()26; CHECK-NEXT: [[ICMP6:%.*]] = icmp eq i32 [[CALL5]], 027; CHECK-NEXT: br i1 [[ICMP6]], label [[BB8:%.*]], label [[BB7:%.*]]28; CHECK: bb7:29; CHECK-NEXT: [[LOAD:%.*]] = load ptr, ptr addrspace(4) [[ARG]], align 830; CHECK-NEXT: [[ADDRSPACECAST:%.*]] = addrspacecast ptr [[LOAD]] to ptr addrspace(1)31; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true)32; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i3233; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP0]], 3234; CHECK-NEXT: [[TMP3:%.*]] = trunc i64 [[TMP2]] to i3235; CHECK-NEXT: [[TMP4:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP1]], i32 0)36; CHECK-NEXT: [[TMP5:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP3]], i32 [[TMP4]])37; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true)38; CHECK-NEXT: br label [[COMPUTELOOP:%.*]]39; CHECK: 7:40; CHECK-NEXT: [[TMP8:%.*]] = atomicrmw add ptr addrspace(1) [[ADDRSPACECAST]], i32 [[TMP13:%.*]] syncscope("agent-one-as") monotonic, align 441; CHECK-NEXT: br label [[TMP9:%.*]]42; CHECK: 9:43; CHECK-NEXT: br label [[BB8]]44; CHECK: bb8:45; CHECK-NEXT: br label [[BB4]]46; CHECK: ComputeLoop:47; CHECK-NEXT: [[ACCUMULATOR:%.*]] = phi i32 [ 0, [[BB7]] ], [ [[TMP13]], [[COMPUTELOOP]] ]48; CHECK-NEXT: [[ACTIVEBITS:%.*]] = phi i64 [ [[TMP6]], [[BB7]] ], [ [[TMP16:%.*]], [[COMPUTELOOP]] ]49; CHECK-NEXT: [[TMP10:%.*]] = call i64 @llvm.cttz.i64(i64 [[ACTIVEBITS]], i1 true)50; CHECK-NEXT: [[TMP11:%.*]] = trunc i64 [[TMP10]] to i3251; CHECK-NEXT: [[TMP12:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[PHI]], i32 [[TMP11]])52; CHECK-NEXT: [[TMP13]] = add i32 [[ACCUMULATOR]], [[TMP12]]53; CHECK-NEXT: [[TMP14:%.*]] = shl i64 1, [[TMP10]]54; CHECK-NEXT: [[TMP15:%.*]] = xor i64 [[TMP14]], -155; CHECK-NEXT: [[TMP16]] = and i64 [[ACTIVEBITS]], [[TMP15]]56; CHECK-NEXT: [[TMP17:%.*]] = icmp eq i64 [[TMP16]], 057; CHECK-NEXT: br i1 [[TMP17]], label [[COMPUTEEND:%.*]], label [[COMPUTELOOP]]58; CHECK: ComputeEnd:59; CHECK-NEXT: [[TMP18:%.*]] = icmp eq i32 [[TMP5]], 060; CHECK-NEXT: br i1 [[TMP18]], label [[TMP7:%.*]], label [[TMP9]]61;62bb:63 %call = tail call i32 @quux()64 %icmp = icmp eq i32 %call, 065 br i1 %icmp, label %bb1, label %bb366 67bb1: ; preds = %bb68 %call2 = tail call i32 @quux()69 br label %bb370 71bb3: ; preds = %bb1, %bb72 %phi = phi i32 [ %call2, %bb1 ], [ %call, %bb ]73 br label %bb474 75bb4: ; preds = %bb8, %bb376 %call5 = tail call i32 @quux()77 %icmp6 = icmp eq i32 %call5, 078 br i1 %icmp6, label %bb8, label %bb779 80bb7: ; preds = %bb481 %load = load ptr, ptr addrspace(4) %arg, align 882 %addrspacecast = addrspacecast ptr %load to ptr addrspace(1)83 %atomicrmw = atomicrmw add ptr addrspace(1) %addrspacecast, i32 %phi syncscope("agent-one-as") monotonic, align 484 br label %bb885 86bb8: ; preds = %bb7, %bb487 br label %bb488}89