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1; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji < %s | FileCheck -check-prefix=ALL %s2 3; FIXME: Vectorization can increase required SGPR count beyond limit.4 5; ALL-LABEL: {{^}}max_10_sgprs:6 7; ALL: SGPRBlocks: 28; ALL: NumSGPRsForWavesPerEU: 249define amdgpu_kernel void @max_10_sgprs() #0 {10 %one = load volatile i32, ptr addrspace(4) poison11 %two = load volatile i32, ptr addrspace(4) poison12 %three = load volatile i32, ptr addrspace(4) poison13 %four = load volatile i32, ptr addrspace(4) poison14 %five = load volatile i32, ptr addrspace(4) poison15 %six = load volatile i32, ptr addrspace(4) poison16 %seven = load volatile i32, ptr addrspace(4) poison17 %eight = load volatile i32, ptr addrspace(4) poison18 %nine = load volatile i32, ptr addrspace(4) poison19 %ten = load volatile i32, ptr addrspace(4) poison20 %eleven = load volatile i32, ptr addrspace(4) poison21 call void asm sideeffect "", "s,s,s,s,s,s,s,s,s,s"(i32 %one, i32 %two, i32 %three, i32 %four, i32 %five, i32 %six, i32 %seven, i32 %eight, i32 %nine, i32 %ten)22 store volatile i32 %one, ptr addrspace(1) poison23 store volatile i32 %two, ptr addrspace(1) poison24 store volatile i32 %three, ptr addrspace(1) poison25 store volatile i32 %four, ptr addrspace(1) poison26 store volatile i32 %five, ptr addrspace(1) poison27 store volatile i32 %six, ptr addrspace(1) poison28 store volatile i32 %seven, ptr addrspace(1) poison29 store volatile i32 %eight, ptr addrspace(1) poison30 store volatile i32 %nine, ptr addrspace(1) poison31 store volatile i32 %ten, ptr addrspace(1) poison32 store volatile i32 %eleven, ptr addrspace(1) poison33 ret void34}35 36; private resource: 437; scratch wave offset: 138; workgroup ids: 339; dispatch id: 240; queue ptr: 241; flat scratch init: 242; ---------------------43; total: 1444 45; + reserved vcc = 1646 47; Because we can't handle re-using the last few input registers as the48; special vcc etc. registers (as well as decide to not use the unused49; features when the number of registers is frozen), this ends up using50; more than expected.51 52; XALL-LABEL: {{^}}max_12_sgprs_14_input_sgprs:53; XTOSGPR: SGPRBlocks: 154; XTOSGPR: NumSGPRsForWavesPerEU: 1655 56; This test case is disabled: When calculating the spillslot addresses AMDGPU57; creates an extra vreg to save/restore m0 which in a point of maximum register58; pressure would trigger an endless loop; the compiler aborts earlier with59; "Incomplete scavenging after 2nd pass" in practice.60;define amdgpu_kernel void @max_12_sgprs_14_input_sgprs(ptr addrspace(1) %out1,61; ptr addrspace(1) %out2,62; ptr addrspace(1) %out3,63; ptr addrspace(1) %out4,64; i32 %one, i32 %two, i32 %three, i32 %four) #2 {65; %x.0 = call i32 @llvm.amdgcn.workgroup.id.x()66; %x.1 = call i32 @llvm.amdgcn.workgroup.id.y()67; %x.2 = call i32 @llvm.amdgcn.workgroup.id.z()68; %x.3 = call i64 @llvm.amdgcn.dispatch.id()69; %x.4 = call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()70; %x.5 = call ptr addrspace(4) @llvm.amdgcn.queue.ptr()71; store volatile i32 0, ptr poison72; br label %stores73;74;stores:75; store volatile i32 %x.0, ptr addrspace(1) poison76; store volatile i32 %x.0, ptr addrspace(1) poison77; store volatile i32 %x.0, ptr addrspace(1) poison78; store volatile i64 %x.3, ptr addrspace(1) poison79; store volatile ptr addrspace(4) %x.4, ptr addrspace(1) poison80; store volatile ptr addrspace(4) %x.5, ptr addrspace(1) poison81;82; store i32 %one, ptr addrspace(1) %out183; store i32 %two, ptr addrspace(1) %out284; store i32 %three, ptr addrspace(1) %out385; store i32 %four, ptr addrspace(1) %out486; ret void87;}88 89; The following test is commented out for now; http://llvm.org/PR3123090; XALL-LABEL: max_12_sgprs_12_input_sgprs{{$}}91; ; Make sure copies for input buffer are not clobbered. This requires92; ; swapping the order the registers are copied from what normally93; ; happens.94 95; XALL: SGPRBlocks: 296; XALL: NumSGPRsForWavesPerEU: 1897;define amdgpu_kernel void @max_12_sgprs_12_input_sgprs(ptr addrspace(1) %out1,98; ptr addrspace(1) %out2,99; ptr addrspace(1) %out3,100; ptr addrspace(1) %out4,101; i32 %one, i32 %two, i32 %three, i32 %four) #2 {102; store volatile i32 0, ptr poison103; %x.0 = call i32 @llvm.amdgcn.workgroup.id.x()104; store volatile i32 %x.0, ptr addrspace(1) poison105; %x.1 = call i32 @llvm.amdgcn.workgroup.id.y()106; store volatile i32 %x.0, ptr addrspace(1) poison107; %x.2 = call i32 @llvm.amdgcn.workgroup.id.z()108; store volatile i32 %x.0, ptr addrspace(1) poison109; %x.3 = call i64 @llvm.amdgcn.dispatch.id()110; store volatile i64 %x.3, ptr addrspace(1) poison111; %x.4 = call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()112; store volatile ptr addrspace(4) %x.4, ptr addrspace(1) poison113;114; store i32 %one, ptr addrspace(1) %out1115; store i32 %two, ptr addrspace(1) %out2116; store i32 %three, ptr addrspace(1) %out3117; store i32 %four, ptr addrspace(1) %out4118; ret void119;}120 121declare i32 @llvm.amdgcn.workgroup.id.x() #1122declare i32 @llvm.amdgcn.workgroup.id.y() #1123declare i32 @llvm.amdgcn.workgroup.id.z() #1124declare i64 @llvm.amdgcn.dispatch.id() #1125declare ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() #1126declare ptr addrspace(4) @llvm.amdgcn.queue.ptr() #1127 128attributes #0 = { nounwind "amdgpu-num-sgpr"="14" }129attributes #1 = { nounwind readnone }130attributes #2 = { nounwind "amdgpu-num-sgpr"="12" }131attributes #3 = { nounwind "amdgpu-num-sgpr"="11" }132