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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-attributor %s | FileCheck %s3 4@gptr = addrspace(1) externally_initialized global i32 0, align 45@gptr2 = addrspace(4) externally_initialized global i32 0, align 46@gptr3 = addrspace(3) externally_initialized global i32 0, align 47 8define amdgpu_kernel void @no_alias_addr_space_select(ptr addrspace(3) %sptr, i1 %cond1, i1 %cond2, i32 %val, i32 %offset) #0 {9; CHECK-LABEL: define amdgpu_kernel void @no_alias_addr_space_select(10; CHECK-SAME: ptr addrspace(3) [[SPTR:%.*]], i1 [[COND1:%.*]], i1 [[COND2:%.*]], i32 [[VAL:%.*]], i32 [[OFFSET:%.*]]) #[[ATTR0:[0-9]+]] {11; CHECK-NEXT: [[LPTR:%.*]] = alloca i32, align 4, addrspace(5)12; CHECK-NEXT: [[B:%.*]] = addrspacecast ptr addrspace(5) [[LPTR]] to ptr13; CHECK-NEXT: [[C:%.*]] = addrspacecast ptr addrspace(3) [[SPTR]] to ptr14; CHECK-NEXT: [[ADD_A:%.*]] = getelementptr inbounds i8, ptr addrspacecast (ptr addrspace(1) @gptr to ptr), i32 [[OFFSET]]15; CHECK-NEXT: [[PTR:%.*]] = select i1 [[COND1]], ptr [[ADD_A]], ptr [[B]]16; CHECK-NEXT: [[PTR2:%.*]] = select i1 [[COND2]], ptr [[PTR]], ptr [[C]]17; CHECK-NEXT: store i32 [[VAL]], ptr [[PTR2]], align 4, !noalias.addrspace [[META0:![0-9]+]]18; CHECK-NEXT: ret void19;20 %lptr = alloca i32, align 4, addrspace(5)21 %a = addrspacecast ptr addrspace(1) @gptr to ptr22 %b = addrspacecast ptr addrspace(5) %lptr to ptr23 %c = addrspacecast ptr addrspace(3) %sptr to ptr24 %add_a = getelementptr inbounds i8, ptr %a, i32 %offset25 %ptr = select i1 %cond1, ptr %add_a, ptr %b26 %ptr2 = select i1 %cond2, ptr %ptr, ptr %c27 store i32 %val, ptr %ptr228 ret void29}30 31define amdgpu_kernel void @no_alias_addr_space_branch(ptr addrspace(3) %sptr, i1 %cond1, i1 %cond2, i32 %val, i32 %offset) #0 {32; CHECK-LABEL: define amdgpu_kernel void @no_alias_addr_space_branch(33; CHECK-SAME: ptr addrspace(3) [[SPTR:%.*]], i1 [[COND1:%.*]], i1 [[COND2:%.*]], i32 [[VAL:%.*]], i32 [[OFFSET:%.*]]) #[[ATTR0]] {34; CHECK-NEXT: br i1 [[COND1]], label %[[BB_1_TRUE:.*]], label %[[BB_1_FALSE:.*]]35; CHECK: [[BB_1_TRUE]]:36; CHECK-NEXT: [[A:%.*]] = addrspacecast ptr addrspace(1) @gptr to ptr37; CHECK-NEXT: br label %[[BB_1_END:.*]]38; CHECK: [[BB_1_FALSE]]:39; CHECK-NEXT: [[LPTR:%.*]] = alloca i32, align 4, addrspace(5)40; CHECK-NEXT: [[B:%.*]] = addrspacecast ptr addrspace(5) [[LPTR]] to ptr41; CHECK-NEXT: br label %[[BB_1_END]]42; CHECK: [[BB_1_END]]:43; CHECK-NEXT: [[PTR1:%.*]] = phi ptr [ [[A]], %[[BB_1_TRUE]] ], [ [[B]], %[[BB_1_FALSE]] ]44; CHECK-NEXT: br i1 [[COND2]], label %[[BB_2_TRUE:.*]], label %[[BB_2_END:.*]]45; CHECK: [[BB_2_TRUE]]:46; CHECK-NEXT: [[C:%.*]] = addrspacecast ptr addrspace(3) [[SPTR]] to ptr47; CHECK-NEXT: br label %[[BB_2_END]]48; CHECK: [[BB_2_END]]:49; CHECK-NEXT: [[PTR2:%.*]] = phi ptr [ [[PTR1]], %[[BB_1_END]] ], [ [[C]], %[[BB_2_TRUE]] ]50; CHECK-NEXT: store i32 [[VAL]], ptr [[PTR2]], align 4, !noalias.addrspace [[META0]]51; CHECK-NEXT: ret void52;53 br i1 %cond1, label %bb.1.true, label %bb.1.false54bb.1.true:55 %a = addrspacecast ptr addrspace(1) @gptr to ptr56 br label %bb.1.end57 58bb.1.false:59 %lptr = alloca i32, align 4, addrspace(5)60 %b = addrspacecast ptr addrspace(5) %lptr to ptr61 br label %bb.1.end62 63bb.1.end:64 %ptr1 = phi ptr [ %a, %bb.1.true ], [ %b, %bb.1.false ]65 br i1 %cond2, label %bb.2.true, label %bb.2.end66 67bb.2.true:68 %c = addrspacecast ptr addrspace(3) %sptr to ptr69 br label %bb.2.end70 71bb.2.end:72 %ptr2 = phi ptr [ %ptr1, %bb.1.end ], [ %c, %bb.2.true ]73 store i32 %val, ptr %ptr274 ret void75}76 77define amdgpu_kernel void @no_alias_addr_space_select_cmpxchg(ptr addrspace(3) %sptr, i1 %cond1, i1 %cond2, i32 %val, i32 %offset) #0 {78; CHECK-LABEL: define amdgpu_kernel void @no_alias_addr_space_select_cmpxchg(79; CHECK-SAME: ptr addrspace(3) [[SPTR:%.*]], i1 [[COND1:%.*]], i1 [[COND2:%.*]], i32 [[VAL:%.*]], i32 [[OFFSET:%.*]]) #[[ATTR0]] {80; CHECK-NEXT: [[LPTR:%.*]] = alloca i32, align 4, addrspace(5)81; CHECK-NEXT: [[B:%.*]] = addrspacecast ptr addrspace(5) [[LPTR]] to ptr82; CHECK-NEXT: [[C:%.*]] = addrspacecast ptr addrspace(3) [[SPTR]] to ptr83; CHECK-NEXT: [[ADD_A:%.*]] = getelementptr inbounds i8, ptr addrspacecast (ptr addrspace(1) @gptr to ptr), i32 [[OFFSET]]84; CHECK-NEXT: [[PTR:%.*]] = select i1 [[COND1]], ptr [[ADD_A]], ptr [[B]]85; CHECK-NEXT: [[PTR2:%.*]] = select i1 [[COND2]], ptr [[PTR]], ptr [[C]]86; CHECK-NEXT: [[CMPXCHG_0:%.*]] = cmpxchg ptr [[PTR2]], i32 0, i32 4 monotonic monotonic, align 4, !noalias.addrspace [[META0]]87; CHECK-NEXT: [[CMPXCHG_1:%.*]] = cmpxchg ptr [[PTR2]], i32 0, i32 5 acq_rel monotonic, align 4, !noalias.addrspace [[META0]]88; CHECK-NEXT: [[CMPXCHG_2:%.*]] = cmpxchg ptr [[PTR2]], i32 0, i32 6 acquire monotonic, align 4, !noalias.addrspace [[META0]]89; CHECK-NEXT: [[CMPXCHG_3:%.*]] = cmpxchg ptr [[PTR2]], i32 0, i32 7 release monotonic, align 4, !noalias.addrspace [[META0]]90; CHECK-NEXT: [[CMPXCHG_4:%.*]] = cmpxchg ptr [[PTR2]], i32 0, i32 8 seq_cst monotonic, align 4, !noalias.addrspace [[META0]]91; CHECK-NEXT: [[CMPXCHG_5:%.*]] = cmpxchg weak ptr [[PTR2]], i32 0, i32 9 seq_cst monotonic, align 4, !noalias.addrspace [[META0]]92; CHECK-NEXT: [[CMPXCHG_6:%.*]] = cmpxchg volatile ptr [[PTR2]], i32 0, i32 10 seq_cst monotonic, align 4, !noalias.addrspace [[META0]]93; CHECK-NEXT: [[CMPXCHG_7:%.*]] = cmpxchg weak volatile ptr [[PTR2]], i32 0, i32 11 syncscope("singlethread") seq_cst monotonic, align 4, !noalias.addrspace [[META0]]94; CHECK-NEXT: ret void95;96 %lptr = alloca i32, align 4, addrspace(5)97 %a = addrspacecast ptr addrspace(1) @gptr to ptr98 %b = addrspacecast ptr addrspace(5) %lptr to ptr99 %c = addrspacecast ptr addrspace(3) %sptr to ptr100 %add_a = getelementptr inbounds i8, ptr %a, i32 %offset101 %ptr = select i1 %cond1, ptr %add_a, ptr %b102 %ptr2 = select i1 %cond2, ptr %ptr, ptr %c103 %cmpxchg.0 = cmpxchg ptr %ptr2, i32 0, i32 4 monotonic monotonic, align 4104 %cmpxchg.1 = cmpxchg ptr %ptr2, i32 0, i32 5 acq_rel monotonic, align 4105 %cmpxchg.2 = cmpxchg ptr %ptr2, i32 0, i32 6 acquire monotonic, align 4106 %cmpxchg.3 = cmpxchg ptr %ptr2, i32 0, i32 7 release monotonic, align 4107 %cmpxchg.4 = cmpxchg ptr %ptr2, i32 0, i32 8 seq_cst monotonic, align 4108 %cmpxchg.5 = cmpxchg weak ptr %ptr2, i32 0, i32 9 seq_cst monotonic, align 4109 %cmpxchg.6 = cmpxchg volatile ptr %ptr2, i32 0, i32 10 seq_cst monotonic, align 4110 %cmpxchg.7 = cmpxchg weak volatile ptr %ptr2, i32 0, i32 11 syncscope("singlethread") seq_cst monotonic, align 4111 ret void112}113 114define amdgpu_kernel void @no_alias_addr_space_branch_cmpxchg(ptr addrspace(3) %sptr, i1 %cond1, i1 %cond2, i32 %val, i32 %offset) #0 {115; CHECK-LABEL: define amdgpu_kernel void @no_alias_addr_space_branch_cmpxchg(116; CHECK-SAME: ptr addrspace(3) [[SPTR:%.*]], i1 [[COND1:%.*]], i1 [[COND2:%.*]], i32 [[VAL:%.*]], i32 [[OFFSET:%.*]]) #[[ATTR0]] {117; CHECK-NEXT: br i1 [[COND1]], label %[[BB_1_TRUE:.*]], label %[[BB_1_FALSE:.*]]118; CHECK: [[BB_1_TRUE]]:119; CHECK-NEXT: [[A:%.*]] = addrspacecast ptr addrspace(1) @gptr to ptr120; CHECK-NEXT: br label %[[BB_1_END:.*]]121; CHECK: [[BB_1_FALSE]]:122; CHECK-NEXT: [[LPTR:%.*]] = alloca i32, align 4, addrspace(5)123; CHECK-NEXT: [[B:%.*]] = addrspacecast ptr addrspace(5) [[LPTR]] to ptr124; CHECK-NEXT: br label %[[BB_1_END]]125; CHECK: [[BB_1_END]]:126; CHECK-NEXT: [[PTR1:%.*]] = phi ptr [ [[A]], %[[BB_1_TRUE]] ], [ [[B]], %[[BB_1_FALSE]] ]127; CHECK-NEXT: br i1 [[COND2]], label %[[BB_2_TRUE:.*]], label %[[BB_2_END:.*]]128; CHECK: [[BB_2_TRUE]]:129; CHECK-NEXT: [[C:%.*]] = addrspacecast ptr addrspace(3) [[SPTR]] to ptr130; CHECK-NEXT: br label %[[BB_2_END]]131; CHECK: [[BB_2_END]]:132; CHECK-NEXT: [[PTR2:%.*]] = phi ptr [ [[PTR1]], %[[BB_1_END]] ], [ [[C]], %[[BB_2_TRUE]] ]133; CHECK-NEXT: [[CMPXCHG_0:%.*]] = cmpxchg ptr [[PTR2]], i32 0, i32 4 monotonic monotonic, align 4, !noalias.addrspace [[META0]]134; CHECK-NEXT: [[CMPXCHG_1:%.*]] = cmpxchg ptr [[PTR2]], i32 0, i32 5 acq_rel monotonic, align 4, !noalias.addrspace [[META0]]135; CHECK-NEXT: [[CMPXCHG_2:%.*]] = cmpxchg ptr [[PTR2]], i32 0, i32 6 acquire monotonic, align 4, !noalias.addrspace [[META0]]136; CHECK-NEXT: [[CMPXCHG_3:%.*]] = cmpxchg ptr [[PTR2]], i32 0, i32 7 release monotonic, align 4, !noalias.addrspace [[META0]]137; CHECK-NEXT: [[CMPXCHG_4:%.*]] = cmpxchg ptr [[PTR2]], i32 0, i32 8 seq_cst monotonic, align 4, !noalias.addrspace [[META0]]138; CHECK-NEXT: [[CMPXCHG_5:%.*]] = cmpxchg weak ptr [[PTR2]], i32 0, i32 9 seq_cst monotonic, align 4, !noalias.addrspace [[META0]]139; CHECK-NEXT: [[CMPXCHG_6:%.*]] = cmpxchg volatile ptr [[PTR2]], i32 0, i32 10 seq_cst monotonic, align 4, !noalias.addrspace [[META0]]140; CHECK-NEXT: [[CMPXCHG_7:%.*]] = cmpxchg weak volatile ptr [[PTR2]], i32 0, i32 11 syncscope("singlethread") seq_cst monotonic, align 4, !noalias.addrspace [[META0]]141; CHECK-NEXT: ret void142;143 br i1 %cond1, label %bb.1.true, label %bb.1.false144bb.1.true:145 %a = addrspacecast ptr addrspace(1) @gptr to ptr146 br label %bb.1.end147 148bb.1.false:149 %lptr = alloca i32, align 4, addrspace(5)150 %b = addrspacecast ptr addrspace(5) %lptr to ptr151 br label %bb.1.end152 153bb.1.end:154 %ptr1 = phi ptr [ %a, %bb.1.true ], [ %b, %bb.1.false ]155 br i1 %cond2, label %bb.2.true, label %bb.2.end156 157bb.2.true:158 %c = addrspacecast ptr addrspace(3) %sptr to ptr159 br label %bb.2.end160 161bb.2.end:162 %ptr2 = phi ptr [ %ptr1, %bb.1.end ], [ %c, %bb.2.true ]163 %cmpxchg.0 = cmpxchg ptr %ptr2, i32 0, i32 4 monotonic monotonic, align 4164 %cmpxchg.1 = cmpxchg ptr %ptr2, i32 0, i32 5 acq_rel monotonic, align 4165 %cmpxchg.2 = cmpxchg ptr %ptr2, i32 0, i32 6 acquire monotonic, align 4166 %cmpxchg.3 = cmpxchg ptr %ptr2, i32 0, i32 7 release monotonic, align 4167 %cmpxchg.4 = cmpxchg ptr %ptr2, i32 0, i32 8 seq_cst monotonic, align 4168 %cmpxchg.5 = cmpxchg weak ptr %ptr2, i32 0, i32 9 seq_cst monotonic, align 4169 %cmpxchg.6 = cmpxchg volatile ptr %ptr2, i32 0, i32 10 seq_cst monotonic, align 4170 %cmpxchg.7 = cmpxchg weak volatile ptr %ptr2, i32 0, i32 11 syncscope("singlethread") seq_cst monotonic, align 4171 ret void172}173 174define amdgpu_kernel void @no_alias_addr_space_select_atomicrmw(ptr addrspace(3) %sptr, i1 %cond1, i1 %cond2, i32 %val, i32 %offset) #0 {175; CHECK-LABEL: define amdgpu_kernel void @no_alias_addr_space_select_atomicrmw(176; CHECK-SAME: ptr addrspace(3) [[SPTR:%.*]], i1 [[COND1:%.*]], i1 [[COND2:%.*]], i32 [[VAL:%.*]], i32 [[OFFSET:%.*]]) #[[ATTR0]] {177; CHECK-NEXT: [[LPTR:%.*]] = alloca i32, align 4, addrspace(5)178; CHECK-NEXT: [[B:%.*]] = addrspacecast ptr addrspace(5) [[LPTR]] to ptr179; CHECK-NEXT: [[C:%.*]] = addrspacecast ptr addrspace(3) [[SPTR]] to ptr180; CHECK-NEXT: [[ADD_A:%.*]] = getelementptr inbounds i8, ptr addrspacecast (ptr addrspace(1) @gptr to ptr), i32 [[OFFSET]]181; CHECK-NEXT: [[PTR:%.*]] = select i1 [[COND1]], ptr [[ADD_A]], ptr [[B]]182; CHECK-NEXT: [[PTR2:%.*]] = select i1 [[COND2]], ptr [[PTR]], ptr [[C]]183; CHECK-NEXT: [[ATOMICRMW_XCHG:%.*]] = atomicrmw xchg ptr [[PTR2]], i32 12 monotonic, align 4, !noalias.addrspace [[META0]]184; CHECK-NEXT: [[ATOMICRMW_ADD:%.*]] = atomicrmw add ptr [[PTR2]], i32 13 monotonic, align 4, !noalias.addrspace [[META0]]185; CHECK-NEXT: [[ATOMICRMW_SUB:%.*]] = atomicrmw sub ptr [[PTR2]], i32 14 monotonic, align 4, !noalias.addrspace [[META0]]186; CHECK-NEXT: [[ATOMICRMW_AND:%.*]] = atomicrmw and ptr [[PTR2]], i32 15 monotonic, align 4, !noalias.addrspace [[META0]]187; CHECK-NEXT: [[ATOMICRMW_NAND:%.*]] = atomicrmw nand ptr [[PTR2]], i32 16 monotonic, align 4, !noalias.addrspace [[META0]]188; CHECK-NEXT: [[ATOMICRMW_OR:%.*]] = atomicrmw or ptr [[PTR2]], i32 17 monotonic, align 4, !noalias.addrspace [[META0]]189; CHECK-NEXT: [[ATOMICRMW_XOR:%.*]] = atomicrmw xor ptr [[PTR2]], i32 18 monotonic, align 4, !noalias.addrspace [[META0]]190; CHECK-NEXT: [[ATOMICRMW_MAX:%.*]] = atomicrmw max ptr [[PTR2]], i32 19 monotonic, align 4, !noalias.addrspace [[META0]]191; CHECK-NEXT: [[ATOMICRMW_MIN:%.*]] = atomicrmw volatile min ptr [[PTR2]], i32 20 monotonic, align 4, !noalias.addrspace [[META0]]192; CHECK-NEXT: [[ATOMICRMW_UMAX:%.*]] = atomicrmw umax ptr [[PTR2]], i32 21 syncscope("singlethread") monotonic, align 4, !noalias.addrspace [[META0]]193; CHECK-NEXT: [[ATOMICRMW_UMIN:%.*]] = atomicrmw volatile umin ptr [[PTR2]], i32 22 syncscope("singlethread") monotonic, align 4, !noalias.addrspace [[META0]]194; CHECK-NEXT: ret void195;196 %lptr = alloca i32, align 4, addrspace(5)197 %a = addrspacecast ptr addrspace(1) @gptr to ptr198 %b = addrspacecast ptr addrspace(5) %lptr to ptr199 %c = addrspacecast ptr addrspace(3) %sptr to ptr200 %add_a = getelementptr inbounds i8, ptr %a, i32 %offset201 %ptr = select i1 %cond1, ptr %add_a, ptr %b202 %ptr2 = select i1 %cond2, ptr %ptr, ptr %c203 %atomicrmw.xchg = atomicrmw xchg ptr %ptr2, i32 12 monotonic, align 4204 %atomicrmw.add = atomicrmw add ptr %ptr2, i32 13 monotonic, align 4205 %atomicrmw.sub = atomicrmw sub ptr %ptr2, i32 14 monotonic, align 4206 %atomicrmw.and = atomicrmw and ptr %ptr2, i32 15 monotonic, align 4207 %atomicrmw.nand = atomicrmw nand ptr %ptr2, i32 16 monotonic, align 4208 %atomicrmw.or = atomicrmw or ptr %ptr2, i32 17 monotonic, align 4209 %atomicrmw.xor = atomicrmw xor ptr %ptr2, i32 18 monotonic, align 4210 %atomicrmw.max = atomicrmw max ptr %ptr2, i32 19 monotonic, align 4211 %atomicrmw.min = atomicrmw volatile min ptr %ptr2, i32 20 monotonic, align 4212 %atomicrmw.umax = atomicrmw umax ptr %ptr2, i32 21 syncscope("singlethread") monotonic, align 4213 %atomicrmw.umin = atomicrmw volatile umin ptr %ptr2, i32 22 syncscope("singlethread") monotonic, align 4214 ret void215}216 217define amdgpu_kernel void @no_alias_addr_space_branch_atomicrmw(ptr addrspace(3) %sptr, i1 %cond1, i1 %cond2, i32 %val, i32 %offset) #0 {218; CHECK-LABEL: define amdgpu_kernel void @no_alias_addr_space_branch_atomicrmw(219; CHECK-SAME: ptr addrspace(3) [[SPTR:%.*]], i1 [[COND1:%.*]], i1 [[COND2:%.*]], i32 [[VAL:%.*]], i32 [[OFFSET:%.*]]) #[[ATTR0]] {220; CHECK-NEXT: br i1 [[COND1]], label %[[BB_1_TRUE:.*]], label %[[BB_1_FALSE:.*]]221; CHECK: [[BB_1_TRUE]]:222; CHECK-NEXT: [[A:%.*]] = addrspacecast ptr addrspace(1) @gptr to ptr223; CHECK-NEXT: br label %[[BB_1_END:.*]]224; CHECK: [[BB_1_FALSE]]:225; CHECK-NEXT: [[LPTR:%.*]] = alloca i32, align 4, addrspace(5)226; CHECK-NEXT: [[B:%.*]] = addrspacecast ptr addrspace(5) [[LPTR]] to ptr227; CHECK-NEXT: br label %[[BB_1_END]]228; CHECK: [[BB_1_END]]:229; CHECK-NEXT: [[PTR1:%.*]] = phi ptr [ [[A]], %[[BB_1_TRUE]] ], [ [[B]], %[[BB_1_FALSE]] ]230; CHECK-NEXT: br i1 [[COND2]], label %[[BB_2_TRUE:.*]], label %[[BB_2_END:.*]]231; CHECK: [[BB_2_TRUE]]:232; CHECK-NEXT: [[C:%.*]] = addrspacecast ptr addrspace(3) [[SPTR]] to ptr233; CHECK-NEXT: br label %[[BB_2_END]]234; CHECK: [[BB_2_END]]:235; CHECK-NEXT: [[PTR2:%.*]] = phi ptr [ [[PTR1]], %[[BB_1_END]] ], [ [[C]], %[[BB_2_TRUE]] ]236; CHECK-NEXT: [[ATOMICRMW_XCHG:%.*]] = atomicrmw xchg ptr [[PTR2]], i32 12 monotonic, align 4, !noalias.addrspace [[META0]]237; CHECK-NEXT: [[ATOMICRMW_ADD:%.*]] = atomicrmw add ptr [[PTR2]], i32 13 monotonic, align 4, !noalias.addrspace [[META0]]238; CHECK-NEXT: [[ATOMICRMW_SUB:%.*]] = atomicrmw sub ptr [[PTR2]], i32 14 monotonic, align 4, !noalias.addrspace [[META0]]239; CHECK-NEXT: [[ATOMICRMW_AND:%.*]] = atomicrmw and ptr [[PTR2]], i32 15 monotonic, align 4, !noalias.addrspace [[META0]]240; CHECK-NEXT: [[ATOMICRMW_NAND:%.*]] = atomicrmw nand ptr [[PTR2]], i32 16 monotonic, align 4, !noalias.addrspace [[META0]]241; CHECK-NEXT: [[ATOMICRMW_OR:%.*]] = atomicrmw or ptr [[PTR2]], i32 17 monotonic, align 4, !noalias.addrspace [[META0]]242; CHECK-NEXT: [[ATOMICRMW_XOR:%.*]] = atomicrmw xor ptr [[PTR2]], i32 18 monotonic, align 4, !noalias.addrspace [[META0]]243; CHECK-NEXT: [[ATOMICRMW_MAX:%.*]] = atomicrmw max ptr [[PTR2]], i32 19 monotonic, align 4, !noalias.addrspace [[META0]]244; CHECK-NEXT: [[ATOMICRMW_MIN:%.*]] = atomicrmw volatile min ptr [[PTR2]], i32 20 monotonic, align 4, !noalias.addrspace [[META0]]245; CHECK-NEXT: [[ATOMICRMW_UMAX:%.*]] = atomicrmw umax ptr [[PTR2]], i32 21 syncscope("singlethread") monotonic, align 4, !noalias.addrspace [[META0]]246; CHECK-NEXT: [[ATOMICRMW_UMIN:%.*]] = atomicrmw volatile umin ptr [[PTR2]], i32 22 syncscope("singlethread") monotonic, align 4, !noalias.addrspace [[META0]]247; CHECK-NEXT: ret void248;249 br i1 %cond1, label %bb.1.true, label %bb.1.false250bb.1.true:251 %a = addrspacecast ptr addrspace(1) @gptr to ptr252 br label %bb.1.end253 254bb.1.false:255 %lptr = alloca i32, align 4, addrspace(5)256 %b = addrspacecast ptr addrspace(5) %lptr to ptr257 br label %bb.1.end258 259bb.1.end:260 %ptr1 = phi ptr [ %a, %bb.1.true ], [ %b, %bb.1.false ]261 br i1 %cond2, label %bb.2.true, label %bb.2.end262 263bb.2.true:264 %c = addrspacecast ptr addrspace(3) %sptr to ptr265 br label %bb.2.end266 267bb.2.end:268 %ptr2 = phi ptr [ %ptr1, %bb.1.end ], [ %c, %bb.2.true ]269 %atomicrmw.xchg = atomicrmw xchg ptr %ptr2, i32 12 monotonic, align 4270 %atomicrmw.add = atomicrmw add ptr %ptr2, i32 13 monotonic, align 4271 %atomicrmw.sub = atomicrmw sub ptr %ptr2, i32 14 monotonic, align 4272 %atomicrmw.and = atomicrmw and ptr %ptr2, i32 15 monotonic, align 4273 %atomicrmw.nand = atomicrmw nand ptr %ptr2, i32 16 monotonic, align 4274 %atomicrmw.or = atomicrmw or ptr %ptr2, i32 17 monotonic, align 4275 %atomicrmw.xor = atomicrmw xor ptr %ptr2, i32 18 monotonic, align 4276 %atomicrmw.max = atomicrmw max ptr %ptr2, i32 19 monotonic, align 4277 %atomicrmw.min = atomicrmw volatile min ptr %ptr2, i32 20 monotonic, align 4278 %atomicrmw.umax = atomicrmw umax ptr %ptr2, i32 21 syncscope("singlethread") monotonic, align 4279 %atomicrmw.umin = atomicrmw volatile umin ptr %ptr2, i32 22 syncscope("singlethread") monotonic, align 4280 ret void281}282 283define amdgpu_kernel void @no_alias_addr_space_select_cmpxchg_flat(ptr %c, i1 %cond1, i1 %cond2, i32 %val, i32 %offset) #0 {284; CHECK-LABEL: define amdgpu_kernel void @no_alias_addr_space_select_cmpxchg_flat(285; CHECK-SAME: ptr [[C:%.*]], i1 [[COND1:%.*]], i1 [[COND2:%.*]], i32 [[VAL:%.*]], i32 [[OFFSET:%.*]]) #[[ATTR0]] {286; CHECK-NEXT: [[LPTR:%.*]] = alloca i32, align 4, addrspace(5)287; CHECK-NEXT: [[B:%.*]] = addrspacecast ptr addrspace(5) [[LPTR]] to ptr288; CHECK-NEXT: [[ADD_A:%.*]] = getelementptr inbounds i8, ptr addrspacecast (ptr addrspace(1) @gptr to ptr), i32 [[OFFSET]]289; CHECK-NEXT: [[PTR:%.*]] = select i1 [[COND1]], ptr [[ADD_A]], ptr [[B]]290; CHECK-NEXT: [[PTR2:%.*]] = select i1 [[COND2]], ptr [[PTR]], ptr [[C]]291; CHECK-NEXT: [[CMPXCHG_0:%.*]] = cmpxchg ptr [[PTR2]], i32 0, i32 4 monotonic monotonic, align 4292; CHECK-NEXT: [[CMPXCHG_1:%.*]] = cmpxchg ptr [[PTR2]], i32 0, i32 5 acq_rel monotonic, align 4293; CHECK-NEXT: [[CMPXCHG_2:%.*]] = cmpxchg ptr [[PTR2]], i32 0, i32 6 acquire monotonic, align 4294; CHECK-NEXT: [[CMPXCHG_3:%.*]] = cmpxchg ptr [[PTR2]], i32 0, i32 7 release monotonic, align 4295; CHECK-NEXT: [[CMPXCHG_4:%.*]] = cmpxchg ptr [[PTR2]], i32 0, i32 8 seq_cst monotonic, align 4296; CHECK-NEXT: [[CMPXCHG_5:%.*]] = cmpxchg weak ptr [[PTR2]], i32 0, i32 9 seq_cst monotonic, align 4297; CHECK-NEXT: [[CMPXCHG_6:%.*]] = cmpxchg volatile ptr [[PTR2]], i32 0, i32 10 seq_cst monotonic, align 4298; CHECK-NEXT: [[CMPXCHG_7:%.*]] = cmpxchg weak volatile ptr [[PTR2]], i32 0, i32 11 syncscope("singlethread") seq_cst monotonic, align 4299; CHECK-NEXT: ret void300;301 %lptr = alloca i32, align 4, addrspace(5)302 %a = addrspacecast ptr addrspace(1) @gptr to ptr303 %b = addrspacecast ptr addrspace(5) %lptr to ptr304 %add_a = getelementptr inbounds i8, ptr %a, i32 %offset305 %ptr = select i1 %cond1, ptr %add_a, ptr %b306 %ptr2 = select i1 %cond2, ptr %ptr, ptr %c307 %cmpxchg.0 = cmpxchg ptr %ptr2, i32 0, i32 4 monotonic monotonic, align 4308 %cmpxchg.1 = cmpxchg ptr %ptr2, i32 0, i32 5 acq_rel monotonic, align 4309 %cmpxchg.2 = cmpxchg ptr %ptr2, i32 0, i32 6 acquire monotonic, align 4310 %cmpxchg.3 = cmpxchg ptr %ptr2, i32 0, i32 7 release monotonic, align 4311 %cmpxchg.4 = cmpxchg ptr %ptr2, i32 0, i32 8 seq_cst monotonic, align 4312 %cmpxchg.5 = cmpxchg weak ptr %ptr2, i32 0, i32 9 seq_cst monotonic, align 4313 %cmpxchg.6 = cmpxchg volatile ptr %ptr2, i32 0, i32 10 seq_cst monotonic, align 4314 %cmpxchg.7 = cmpxchg weak volatile ptr %ptr2, i32 0, i32 11 syncscope("singlethread") seq_cst monotonic, align 4315 ret void316}317 318define amdgpu_kernel void @no_alias_addr_space_branch_cmpxchg_flat(ptr %c, i1 %cond1, i1 %cond2, i32 %val, i32 %offset) #0 {319; CHECK-LABEL: define amdgpu_kernel void @no_alias_addr_space_branch_cmpxchg_flat(320; CHECK-SAME: ptr [[C:%.*]], i1 [[COND1:%.*]], i1 [[COND2:%.*]], i32 [[VAL:%.*]], i32 [[OFFSET:%.*]]) #[[ATTR0]] {321; CHECK-NEXT: br i1 [[COND1]], label %[[BB_1_TRUE:.*]], label %[[BB_1_FALSE:.*]]322; CHECK: [[BB_1_TRUE]]:323; CHECK-NEXT: [[A:%.*]] = addrspacecast ptr addrspace(1) @gptr to ptr324; CHECK-NEXT: br label %[[BB_1_END:.*]]325; CHECK: [[BB_1_FALSE]]:326; CHECK-NEXT: [[LPTR:%.*]] = alloca i32, align 4, addrspace(5)327; CHECK-NEXT: [[B:%.*]] = addrspacecast ptr addrspace(5) [[LPTR]] to ptr328; CHECK-NEXT: br label %[[BB_1_END]]329; CHECK: [[BB_1_END]]:330; CHECK-NEXT: [[PTR1:%.*]] = phi ptr [ [[A]], %[[BB_1_TRUE]] ], [ [[B]], %[[BB_1_FALSE]] ]331; CHECK-NEXT: br i1 [[COND2]], label %[[BB_2_TRUE:.*]], label %[[BB_2_END:.*]]332; CHECK: [[BB_2_TRUE]]:333; CHECK-NEXT: br label %[[BB_2_END]]334; CHECK: [[BB_2_END]]:335; CHECK-NEXT: [[PTR2:%.*]] = phi ptr [ [[PTR1]], %[[BB_1_END]] ], [ [[C]], %[[BB_2_TRUE]] ]336; CHECK-NEXT: [[CMPXCHG_0:%.*]] = cmpxchg ptr [[PTR2]], i32 0, i32 4 monotonic monotonic, align 4337; CHECK-NEXT: [[CMPXCHG_1:%.*]] = cmpxchg ptr [[PTR2]], i32 0, i32 5 acq_rel monotonic, align 4338; CHECK-NEXT: [[CMPXCHG_2:%.*]] = cmpxchg ptr [[PTR2]], i32 0, i32 6 acquire monotonic, align 4339; CHECK-NEXT: [[CMPXCHG_3:%.*]] = cmpxchg ptr [[PTR2]], i32 0, i32 7 release monotonic, align 4340; CHECK-NEXT: [[CMPXCHG_4:%.*]] = cmpxchg ptr [[PTR2]], i32 0, i32 8 seq_cst monotonic, align 4341; CHECK-NEXT: [[CMPXCHG_5:%.*]] = cmpxchg weak ptr [[PTR2]], i32 0, i32 9 seq_cst monotonic, align 4342; CHECK-NEXT: [[CMPXCHG_6:%.*]] = cmpxchg volatile ptr [[PTR2]], i32 0, i32 10 seq_cst monotonic, align 4343; CHECK-NEXT: [[CMPXCHG_7:%.*]] = cmpxchg weak volatile ptr [[PTR2]], i32 0, i32 11 syncscope("singlethread") seq_cst monotonic, align 4344; CHECK-NEXT: ret void345;346 br i1 %cond1, label %bb.1.true, label %bb.1.false347bb.1.true:348 %a = addrspacecast ptr addrspace(1) @gptr to ptr349 br label %bb.1.end350 351bb.1.false:352 %lptr = alloca i32, align 4, addrspace(5)353 %b = addrspacecast ptr addrspace(5) %lptr to ptr354 br label %bb.1.end355 356bb.1.end:357 %ptr1 = phi ptr [ %a, %bb.1.true ], [ %b, %bb.1.false ]358 br i1 %cond2, label %bb.2.true, label %bb.2.end359 360bb.2.true:361 br label %bb.2.end362 363bb.2.end:364 %ptr2 = phi ptr [ %ptr1, %bb.1.end ], [ %c, %bb.2.true ]365 %cmpxchg.0 = cmpxchg ptr %ptr2, i32 0, i32 4 monotonic monotonic, align 4366 %cmpxchg.1 = cmpxchg ptr %ptr2, i32 0, i32 5 acq_rel monotonic, align 4367 %cmpxchg.2 = cmpxchg ptr %ptr2, i32 0, i32 6 acquire monotonic, align 4368 %cmpxchg.3 = cmpxchg ptr %ptr2, i32 0, i32 7 release monotonic, align 4369 %cmpxchg.4 = cmpxchg ptr %ptr2, i32 0, i32 8 seq_cst monotonic, align 4370 %cmpxchg.5 = cmpxchg weak ptr %ptr2, i32 0, i32 9 seq_cst monotonic, align 4371 %cmpxchg.6 = cmpxchg volatile ptr %ptr2, i32 0, i32 10 seq_cst monotonic, align 4372 %cmpxchg.7 = cmpxchg weak volatile ptr %ptr2, i32 0, i32 11 syncscope("singlethread") seq_cst monotonic, align 4373 ret void374}375 376define amdgpu_kernel void @no_alias_addr_space_select_atomicrmw_flat(ptr %c, i1 %cond1, i1 %cond2, i32 %val, i32 %offset) #0 {377; CHECK-LABEL: define amdgpu_kernel void @no_alias_addr_space_select_atomicrmw_flat(378; CHECK-SAME: ptr [[C:%.*]], i1 [[COND1:%.*]], i1 [[COND2:%.*]], i32 [[VAL:%.*]], i32 [[OFFSET:%.*]]) #[[ATTR0]] {379; CHECK-NEXT: [[LPTR:%.*]] = alloca i32, align 4, addrspace(5)380; CHECK-NEXT: [[B:%.*]] = addrspacecast ptr addrspace(5) [[LPTR]] to ptr381; CHECK-NEXT: [[ADD_A:%.*]] = getelementptr inbounds i8, ptr addrspacecast (ptr addrspace(1) @gptr to ptr), i32 [[OFFSET]]382; CHECK-NEXT: [[PTR:%.*]] = select i1 [[COND1]], ptr [[ADD_A]], ptr [[B]]383; CHECK-NEXT: [[PTR2:%.*]] = select i1 [[COND2]], ptr [[PTR]], ptr [[C]]384; CHECK-NEXT: [[ATOMICRMW_XCHG:%.*]] = atomicrmw xchg ptr [[PTR2]], i32 12 monotonic, align 4385; CHECK-NEXT: [[ATOMICRMW_ADD:%.*]] = atomicrmw add ptr [[PTR2]], i32 13 monotonic, align 4386; CHECK-NEXT: [[ATOMICRMW_SUB:%.*]] = atomicrmw sub ptr [[PTR2]], i32 14 monotonic, align 4387; CHECK-NEXT: [[ATOMICRMW_AND:%.*]] = atomicrmw and ptr [[PTR2]], i32 15 monotonic, align 4388; CHECK-NEXT: [[ATOMICRMW_NAND:%.*]] = atomicrmw nand ptr [[PTR2]], i32 16 monotonic, align 4389; CHECK-NEXT: [[ATOMICRMW_OR:%.*]] = atomicrmw or ptr [[PTR2]], i32 17 monotonic, align 4390; CHECK-NEXT: [[ATOMICRMW_XOR:%.*]] = atomicrmw xor ptr [[PTR2]], i32 18 monotonic, align 4391; CHECK-NEXT: [[ATOMICRMW_MAX:%.*]] = atomicrmw max ptr [[PTR2]], i32 19 monotonic, align 4392; CHECK-NEXT: [[ATOMICRMW_MIN:%.*]] = atomicrmw volatile min ptr [[PTR2]], i32 20 monotonic, align 4393; CHECK-NEXT: [[ATOMICRMW_UMAX:%.*]] = atomicrmw umax ptr [[PTR2]], i32 21 syncscope("singlethread") monotonic, align 4394; CHECK-NEXT: [[ATOMICRMW_UMIN:%.*]] = atomicrmw volatile umin ptr [[PTR2]], i32 22 syncscope("singlethread") monotonic, align 4395; CHECK-NEXT: ret void396;397 %lptr = alloca i32, align 4, addrspace(5)398 %a = addrspacecast ptr addrspace(1) @gptr to ptr399 %b = addrspacecast ptr addrspace(5) %lptr to ptr400 %add_a = getelementptr inbounds i8, ptr %a, i32 %offset401 %ptr = select i1 %cond1, ptr %add_a, ptr %b402 %ptr2 = select i1 %cond2, ptr %ptr, ptr %c403 %atomicrmw.xchg = atomicrmw xchg ptr %ptr2, i32 12 monotonic, align 4404 %atomicrmw.add = atomicrmw add ptr %ptr2, i32 13 monotonic, align 4405 %atomicrmw.sub = atomicrmw sub ptr %ptr2, i32 14 monotonic, align 4406 %atomicrmw.and = atomicrmw and ptr %ptr2, i32 15 monotonic, align 4407 %atomicrmw.nand = atomicrmw nand ptr %ptr2, i32 16 monotonic, align 4408 %atomicrmw.or = atomicrmw or ptr %ptr2, i32 17 monotonic, align 4409 %atomicrmw.xor = atomicrmw xor ptr %ptr2, i32 18 monotonic, align 4410 %atomicrmw.max = atomicrmw max ptr %ptr2, i32 19 monotonic, align 4411 %atomicrmw.min = atomicrmw volatile min ptr %ptr2, i32 20 monotonic, align 4412 %atomicrmw.umax = atomicrmw umax ptr %ptr2, i32 21 syncscope("singlethread") monotonic, align 4413 %atomicrmw.umin = atomicrmw volatile umin ptr %ptr2, i32 22 syncscope("singlethread") monotonic, align 4414 ret void415}416 417define amdgpu_kernel void @no_alias_addr_space_branch_atomicrmw_flat(ptr %c, i1 %cond1, i1 %cond2, i32 %val, i32 %offset) #0 {418; CHECK-LABEL: define amdgpu_kernel void @no_alias_addr_space_branch_atomicrmw_flat(419; CHECK-SAME: ptr [[C:%.*]], i1 [[COND1:%.*]], i1 [[COND2:%.*]], i32 [[VAL:%.*]], i32 [[OFFSET:%.*]]) #[[ATTR0]] {420; CHECK-NEXT: br i1 [[COND1]], label %[[BB_1_TRUE:.*]], label %[[BB_1_FALSE:.*]]421; CHECK: [[BB_1_TRUE]]:422; CHECK-NEXT: [[A:%.*]] = addrspacecast ptr addrspace(1) @gptr to ptr423; CHECK-NEXT: br label %[[BB_1_END:.*]]424; CHECK: [[BB_1_FALSE]]:425; CHECK-NEXT: [[LPTR:%.*]] = alloca i32, align 4, addrspace(5)426; CHECK-NEXT: [[B:%.*]] = addrspacecast ptr addrspace(5) [[LPTR]] to ptr427; CHECK-NEXT: br label %[[BB_1_END]]428; CHECK: [[BB_1_END]]:429; CHECK-NEXT: [[PTR1:%.*]] = phi ptr [ [[A]], %[[BB_1_TRUE]] ], [ [[B]], %[[BB_1_FALSE]] ]430; CHECK-NEXT: br i1 [[COND2]], label %[[BB_2_TRUE:.*]], label %[[BB_2_END:.*]]431; CHECK: [[BB_2_TRUE]]:432; CHECK-NEXT: br label %[[BB_2_END]]433; CHECK: [[BB_2_END]]:434; CHECK-NEXT: [[PTR2:%.*]] = phi ptr [ [[PTR1]], %[[BB_1_END]] ], [ [[C]], %[[BB_2_TRUE]] ]435; CHECK-NEXT: [[ATOMICRMW_XCHG:%.*]] = atomicrmw xchg ptr [[PTR2]], i32 12 monotonic, align 4436; CHECK-NEXT: [[ATOMICRMW_ADD:%.*]] = atomicrmw add ptr [[PTR2]], i32 13 monotonic, align 4437; CHECK-NEXT: [[ATOMICRMW_SUB:%.*]] = atomicrmw sub ptr [[PTR2]], i32 14 monotonic, align 4438; CHECK-NEXT: [[ATOMICRMW_AND:%.*]] = atomicrmw and ptr [[PTR2]], i32 15 monotonic, align 4439; CHECK-NEXT: [[ATOMICRMW_NAND:%.*]] = atomicrmw nand ptr [[PTR2]], i32 16 monotonic, align 4440; CHECK-NEXT: [[ATOMICRMW_OR:%.*]] = atomicrmw or ptr [[PTR2]], i32 17 monotonic, align 4441; CHECK-NEXT: [[ATOMICRMW_XOR:%.*]] = atomicrmw xor ptr [[PTR2]], i32 18 monotonic, align 4442; CHECK-NEXT: [[ATOMICRMW_MAX:%.*]] = atomicrmw max ptr [[PTR2]], i32 19 monotonic, align 4443; CHECK-NEXT: [[ATOMICRMW_MIN:%.*]] = atomicrmw volatile min ptr [[PTR2]], i32 20 monotonic, align 4444; CHECK-NEXT: [[ATOMICRMW_UMAX:%.*]] = atomicrmw umax ptr [[PTR2]], i32 21 syncscope("singlethread") monotonic, align 4445; CHECK-NEXT: [[ATOMICRMW_UMIN:%.*]] = atomicrmw volatile umin ptr [[PTR2]], i32 22 syncscope("singlethread") monotonic, align 4446; CHECK-NEXT: ret void447;448 br i1 %cond1, label %bb.1.true, label %bb.1.false449bb.1.true:450 %a = addrspacecast ptr addrspace(1) @gptr to ptr451 br label %bb.1.end452 453bb.1.false:454 %lptr = alloca i32, align 4, addrspace(5)455 %b = addrspacecast ptr addrspace(5) %lptr to ptr456 br label %bb.1.end457 458bb.1.end:459 %ptr1 = phi ptr [ %a, %bb.1.true ], [ %b, %bb.1.false ]460 br i1 %cond2, label %bb.2.true, label %bb.2.end461 462bb.2.true:463 br label %bb.2.end464 465bb.2.end:466 %ptr2 = phi ptr [ %ptr1, %bb.1.end ], [ %c, %bb.2.true ]467 %atomicrmw.xchg = atomicrmw xchg ptr %ptr2, i32 12 monotonic, align 4468 %atomicrmw.add = atomicrmw add ptr %ptr2, i32 13 monotonic, align 4469 %atomicrmw.sub = atomicrmw sub ptr %ptr2, i32 14 monotonic, align 4470 %atomicrmw.and = atomicrmw and ptr %ptr2, i32 15 monotonic, align 4471 %atomicrmw.nand = atomicrmw nand ptr %ptr2, i32 16 monotonic, align 4472 %atomicrmw.or = atomicrmw or ptr %ptr2, i32 17 monotonic, align 4473 %atomicrmw.xor = atomicrmw xor ptr %ptr2, i32 18 monotonic, align 4474 %atomicrmw.max = atomicrmw max ptr %ptr2, i32 19 monotonic, align 4475 %atomicrmw.min = atomicrmw volatile min ptr %ptr2, i32 20 monotonic, align 4476 %atomicrmw.umax = atomicrmw umax ptr %ptr2, i32 21 syncscope("singlethread") monotonic, align 4477 %atomicrmw.umin = atomicrmw volatile umin ptr %ptr2, i32 22 syncscope("singlethread") monotonic, align 4478 ret void479}480 481define internal void @callee_no_alias_addr_space_select(ptr %ptr1, ptr %ptr2, ptr %ptr3, i1 %cond1, i1 %cond2, i32 %val) #0 {482; CHECK-LABEL: define internal void @callee_no_alias_addr_space_select(483; CHECK-SAME: ptr [[PTR1:%.*]], ptr [[PTR2:%.*]], ptr [[PTR3:%.*]], i1 [[COND1:%.*]], i1 [[COND2:%.*]], i32 [[VAL:%.*]]) #[[ATTR1:[0-9]+]] {484; CHECK-NEXT: [[PTR4:%.*]] = select i1 [[COND1]], ptr addrspacecast (ptr addrspace(1) @gptr to ptr), ptr addrspacecast (ptr addrspace(4) @gptr2 to ptr)485; CHECK-NEXT: [[PTR5:%.*]] = select i1 [[COND2]], ptr [[PTR4]], ptr addrspacecast (ptr addrspace(3) @gptr3 to ptr)486; CHECK-NEXT: store i32 [[VAL]], ptr [[PTR5]], align 4, !noalias.addrspace [[META1:![0-9]+]]487; CHECK-NEXT: [[ATOMICRMW_XCHG:%.*]] = atomicrmw xchg ptr [[PTR5]], i32 12 monotonic, align 4, !noalias.addrspace [[META1]]488; CHECK-NEXT: [[ATOMICRMW_ADD:%.*]] = atomicrmw add ptr [[PTR5]], i32 13 monotonic, align 4, !noalias.addrspace [[META1]]489; CHECK-NEXT: [[ATOMICRMW_SUB:%.*]] = atomicrmw sub ptr [[PTR5]], i32 14 monotonic, align 4, !noalias.addrspace [[META1]]490; CHECK-NEXT: [[ATOMICRMW_AND:%.*]] = atomicrmw and ptr [[PTR5]], i32 15 monotonic, align 4, !noalias.addrspace [[META1]]491; CHECK-NEXT: [[ATOMICRMW_NAND:%.*]] = atomicrmw nand ptr [[PTR5]], i32 16 monotonic, align 4, !noalias.addrspace [[META1]]492; CHECK-NEXT: [[ATOMICRMW_OR:%.*]] = atomicrmw or ptr [[PTR5]], i32 17 monotonic, align 4, !noalias.addrspace [[META1]]493; CHECK-NEXT: [[ATOMICRMW_XOR:%.*]] = atomicrmw xor ptr [[PTR5]], i32 18 monotonic, align 4, !noalias.addrspace [[META1]]494; CHECK-NEXT: [[ATOMICRMW_MAX:%.*]] = atomicrmw max ptr [[PTR5]], i32 19 monotonic, align 4, !noalias.addrspace [[META1]]495; CHECK-NEXT: [[ATOMICRMW_MIN:%.*]] = atomicrmw volatile min ptr [[PTR5]], i32 20 monotonic, align 4, !noalias.addrspace [[META1]]496; CHECK-NEXT: [[ATOMICRMW_UMAX:%.*]] = atomicrmw umax ptr [[PTR5]], i32 21 syncscope("singlethread") monotonic, align 4, !noalias.addrspace [[META1]]497; CHECK-NEXT: [[ATOMICRMW_UMIN:%.*]] = atomicrmw volatile umin ptr [[PTR5]], i32 22 syncscope("singlethread") monotonic, align 4, !noalias.addrspace [[META1]]498; CHECK-NEXT: ret void499;500 %ptr4 = select i1 %cond1, ptr %ptr1, ptr %ptr2501 %ptr5 = select i1 %cond2, ptr %ptr4, ptr %ptr3502 store i32 %val, ptr %ptr5503 %atomicrmw.xchg = atomicrmw xchg ptr %ptr5, i32 12 monotonic, align 4504 %atomicrmw.add = atomicrmw add ptr %ptr5, i32 13 monotonic, align 4505 %atomicrmw.sub = atomicrmw sub ptr %ptr5, i32 14 monotonic, align 4506 %atomicrmw.and = atomicrmw and ptr %ptr5, i32 15 monotonic, align 4507 %atomicrmw.nand = atomicrmw nand ptr %ptr5, i32 16 monotonic, align 4508 %atomicrmw.or = atomicrmw or ptr %ptr5, i32 17 monotonic, align 4509 %atomicrmw.xor = atomicrmw xor ptr %ptr5, i32 18 monotonic, align 4510 %atomicrmw.max = atomicrmw max ptr %ptr5, i32 19 monotonic, align 4511 %atomicrmw.min = atomicrmw volatile min ptr %ptr5, i32 20 monotonic, align 4512 %atomicrmw.umax = atomicrmw umax ptr %ptr5, i32 21 syncscope("singlethread") monotonic, align 4513 %atomicrmw.umin = atomicrmw volatile umin ptr %ptr5, i32 22 syncscope("singlethread") monotonic, align 4514 ret void515}516 517define internal void @callee_alias_addr_space_branch(ptr %ptr1, ptr %ptr2, ptr %ptr3, i1 %cond1, i1 %cond2, i32 %val) #0 {518; CHECK-LABEL: define internal void @callee_alias_addr_space_branch(519; CHECK-SAME: ptr [[PTR1:%.*]], ptr [[PTR2:%.*]], ptr [[PTR3:%.*]], i1 [[COND1:%.*]], i1 [[COND2:%.*]], i32 [[VAL:%.*]]) #[[ATTR1]] {520; CHECK-NEXT: br i1 [[COND1]], label %[[BB_1_TRUE:.*]], label %[[BB_1_FALSE:.*]]521; CHECK: [[BB_1_TRUE]]:522; CHECK-NEXT: br label %[[BB_1_END:.*]]523; CHECK: [[BB_1_FALSE]]:524; CHECK-NEXT: br label %[[BB_1_END]]525; CHECK: [[BB_1_END]]:526; CHECK-NEXT: [[PTR4:%.*]] = phi ptr [ addrspacecast (ptr addrspace(1) @gptr to ptr), %[[BB_1_TRUE]] ], [ addrspacecast (ptr addrspace(4) @gptr2 to ptr), %[[BB_1_FALSE]] ]527; CHECK-NEXT: br i1 [[COND2]], label %[[BB_2_TRUE:.*]], label %[[BB_2_END:.*]]528; CHECK: [[BB_2_TRUE]]:529; CHECK-NEXT: br label %[[BB_2_END]]530; CHECK: [[BB_2_END]]:531; CHECK-NEXT: [[PTR5:%.*]] = phi ptr [ [[PTR4]], %[[BB_1_END]] ], [ addrspacecast (ptr addrspace(3) @gptr3 to ptr), %[[BB_2_TRUE]] ]532; CHECK-NEXT: store i32 [[VAL]], ptr [[PTR5]], align 4, !noalias.addrspace [[META1]]533; CHECK-NEXT: [[ATOMICRMW_XCHG:%.*]] = atomicrmw xchg ptr [[PTR5]], i32 12 monotonic, align 4, !noalias.addrspace [[META1]]534; CHECK-NEXT: [[ATOMICRMW_ADD:%.*]] = atomicrmw add ptr [[PTR5]], i32 13 monotonic, align 4, !noalias.addrspace [[META1]]535; CHECK-NEXT: [[ATOMICRMW_SUB:%.*]] = atomicrmw sub ptr [[PTR5]], i32 14 monotonic, align 4, !noalias.addrspace [[META1]]536; CHECK-NEXT: [[ATOMICRMW_AND:%.*]] = atomicrmw and ptr [[PTR5]], i32 15 monotonic, align 4, !noalias.addrspace [[META1]]537; CHECK-NEXT: [[ATOMICRMW_NAND:%.*]] = atomicrmw nand ptr [[PTR5]], i32 16 monotonic, align 4, !noalias.addrspace [[META1]]538; CHECK-NEXT: [[ATOMICRMW_OR:%.*]] = atomicrmw or ptr [[PTR5]], i32 17 monotonic, align 4, !noalias.addrspace [[META1]]539; CHECK-NEXT: [[ATOMICRMW_XOR:%.*]] = atomicrmw xor ptr [[PTR5]], i32 18 monotonic, align 4, !noalias.addrspace [[META1]]540; CHECK-NEXT: [[ATOMICRMW_MAX:%.*]] = atomicrmw max ptr [[PTR5]], i32 19 monotonic, align 4, !noalias.addrspace [[META1]]541; CHECK-NEXT: [[ATOMICRMW_MIN:%.*]] = atomicrmw volatile min ptr [[PTR5]], i32 20 monotonic, align 4, !noalias.addrspace [[META1]]542; CHECK-NEXT: [[ATOMICRMW_UMAX:%.*]] = atomicrmw umax ptr [[PTR5]], i32 21 syncscope("singlethread") monotonic, align 4, !noalias.addrspace [[META1]]543; CHECK-NEXT: [[ATOMICRMW_UMIN:%.*]] = atomicrmw volatile umin ptr [[PTR5]], i32 22 syncscope("singlethread") monotonic, align 4, !noalias.addrspace [[META1]]544; CHECK-NEXT: ret void545;546 br i1 %cond1, label %bb.1.true, label %bb.1.false547bb.1.true:548 br label %bb.1.end549 550bb.1.false:551 br label %bb.1.end552 553bb.1.end:554 %ptr4 = phi ptr [ %ptr1, %bb.1.true ], [ %ptr2, %bb.1.false ]555 br i1 %cond2, label %bb.2.true, label %bb.2.end556 557bb.2.true:558 br label %bb.2.end559 560bb.2.end:561 %ptr5 = phi ptr [ %ptr4, %bb.1.end ], [ %ptr3, %bb.2.true ]562 store i32 %val, ptr %ptr5563 %atomicrmw.xchg = atomicrmw xchg ptr %ptr5, i32 12 monotonic, align 4564 %atomicrmw.add = atomicrmw add ptr %ptr5, i32 13 monotonic, align 4565 %atomicrmw.sub = atomicrmw sub ptr %ptr5, i32 14 monotonic, align 4566 %atomicrmw.and = atomicrmw and ptr %ptr5, i32 15 monotonic, align 4567 %atomicrmw.nand = atomicrmw nand ptr %ptr5, i32 16 monotonic, align 4568 %atomicrmw.or = atomicrmw or ptr %ptr5, i32 17 monotonic, align 4569 %atomicrmw.xor = atomicrmw xor ptr %ptr5, i32 18 monotonic, align 4570 %atomicrmw.max = atomicrmw max ptr %ptr5, i32 19 monotonic, align 4571 %atomicrmw.min = atomicrmw volatile min ptr %ptr5, i32 20 monotonic, align 4572 %atomicrmw.umax = atomicrmw umax ptr %ptr5, i32 21 syncscope("singlethread") monotonic, align 4573 %atomicrmw.umin = atomicrmw volatile umin ptr %ptr5, i32 22 syncscope("singlethread") monotonic, align 4574 ret void575}576 577define amdgpu_kernel void @kernal_call_func(i1 %cond1, i1 %cond2, i32 %val) #0 {578; CHECK-LABEL: define amdgpu_kernel void @kernal_call_func(579; CHECK-SAME: i1 [[COND1:%.*]], i1 [[COND2:%.*]], i32 [[VAL:%.*]]) #[[ATTR2:[0-9]+]] {580; CHECK-NEXT: [[LPTR:%.*]] = alloca i32, align 4, addrspace(5)581; CHECK-NEXT: call void @callee_no_alias_addr_space_select(ptr addrspacecast (ptr addrspace(1) @gptr to ptr), ptr addrspacecast (ptr addrspace(4) @gptr2 to ptr), ptr addrspacecast (ptr addrspace(3) @gptr3 to ptr), i1 [[COND1]], i1 [[COND2]], i32 [[VAL]])582; CHECK-NEXT: call void @callee_alias_addr_space_branch(ptr addrspacecast (ptr addrspace(1) @gptr to ptr), ptr addrspacecast (ptr addrspace(4) @gptr2 to ptr), ptr addrspacecast (ptr addrspace(3) @gptr3 to ptr), i1 [[COND1]], i1 [[COND2]], i32 [[VAL]])583; CHECK-NEXT: ret void584;585 %lptr = alloca i32, align 4, addrspace(5)586 %a = addrspacecast ptr addrspace(1) @gptr to ptr587 %b = addrspacecast ptr addrspace(4) @gptr2 to ptr588 %c = addrspacecast ptr addrspace(3) @gptr3 to ptr589 call void @callee_no_alias_addr_space_select(ptr %a, ptr %b, ptr %c, i1 %cond1, i1 %cond2, i32 %val)590 call void @callee_alias_addr_space_branch(ptr %a, ptr %b, ptr %c, i1 %cond1, i1 %cond2, i32 %val)591 ret void592}593 594define amdgpu_kernel void @no_alias_addr_space_unhandled(ptr addrspace(3) %sptr, i1 %cond1, i1 %cond2, i32 %val, i32 %offset) #0 {595; CHECK-LABEL: define amdgpu_kernel void @no_alias_addr_space_unhandled(596; CHECK-SAME: ptr addrspace(3) [[SPTR:%.*]], i1 [[COND1:%.*]], i1 [[COND2:%.*]], i32 [[VAL:%.*]], i32 [[OFFSET:%.*]]) #[[ATTR1]] {597; CHECK-NEXT: [[LPTR:%.*]] = alloca i32, align 4, addrspace(5)598; CHECK-NEXT: store i32 [[VAL]], ptr addrspace(3) [[SPTR]], align 4599; CHECK-NEXT: store i32 [[VAL]], ptr addrspace(5) [[LPTR]], align 4600; CHECK-NEXT: store i32 [[VAL]], ptr addrspace(1) @gptr, align 4601; CHECK-NEXT: ret void602;603 %lptr = alloca i32, align 4, addrspace(5)604 store i32 %val, ptr addrspace(3) %sptr605 store i32 %val, ptr addrspace(5) %lptr606 store i32 %val, ptr addrspace(1) @gptr607 ret void608}609 610define amdgpu_kernel void @no_alias_addr_space_has_meta(ptr addrspace(3) %sptr, i1 %cond1, i1 %cond2, i32 %val, i32 %offset) #0 {611; CHECK-LABEL: define amdgpu_kernel void @no_alias_addr_space_has_meta(612; CHECK-SAME: ptr addrspace(3) [[SPTR:%.*]], i1 [[COND1:%.*]], i1 [[COND2:%.*]], i32 [[VAL:%.*]], i32 [[OFFSET:%.*]]) #[[ATTR0]] {613; CHECK-NEXT: [[LPTR:%.*]] = alloca i32, align 4, addrspace(5)614; CHECK-NEXT: [[B:%.*]] = addrspacecast ptr addrspace(5) [[LPTR]] to ptr615; CHECK-NEXT: [[C:%.*]] = addrspacecast ptr addrspace(3) [[SPTR]] to ptr616; CHECK-NEXT: [[ADD_A:%.*]] = getelementptr inbounds i8, ptr addrspacecast (ptr addrspace(1) @gptr to ptr), i32 [[OFFSET]]617; CHECK-NEXT: [[PTR:%.*]] = select i1 [[COND1]], ptr [[ADD_A]], ptr [[B]]618; CHECK-NEXT: [[PTR2:%.*]] = select i1 [[COND2]], ptr [[PTR]], ptr [[C]]619; CHECK-NEXT: store i32 [[VAL]], ptr [[PTR2]], align 4, !noalias.addrspace [[META2:![0-9]+]]620; CHECK-NEXT: ret void621;622 %lptr = alloca i32, align 4, addrspace(5)623 %a = addrspacecast ptr addrspace(1) @gptr to ptr624 %b = addrspacecast ptr addrspace(5) %lptr to ptr625 %c = addrspacecast ptr addrspace(3) %sptr to ptr626 %add_a = getelementptr inbounds i8, ptr %a, i32 %offset627 %ptr = select i1 %cond1, ptr %add_a, ptr %b628 %ptr2 = select i1 %cond2, ptr %ptr, ptr %c629 store i32 %val, ptr %ptr2, !noalias.addrspace !0630 ret void631}632 633!0 = !{i32 2, i32 3, i32 4, i32 10}634 635;.636; CHECK: [[META0]] = !{i32 2, i32 3, i32 4, i32 5, i32 6, i32 10}637; CHECK: [[META1]] = !{i32 2, i32 3, i32 5, i32 10}638; CHECK: [[META2]] = !{i32 2, i32 3, i32 4, i32 10}639;.640