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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn < %s | FileCheck -enable-var-scope -check-prefixes=SI %s3; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -enable-var-scope -check-prefixes=VI %s4 5define amdgpu_kernel void @v_ubfe_sub_i32(ptr addrspace(1) %out, ptr addrspace(1) %in0, ptr addrspace(1) %in1) #1 {6; SI-LABEL: v_ubfe_sub_i32:7; SI: ; %bb.0:8; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x99; SI-NEXT: s_mov_b32 s7, 0xf00010; SI-NEXT: s_mov_b32 s6, 011; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v012; SI-NEXT: v_mov_b32_e32 v1, 013; SI-NEXT: s_waitcnt lgkmcnt(0)14; SI-NEXT: s_mov_b64 s[4:5], s[2:3]15; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 glc16; SI-NEXT: s_waitcnt vmcnt(0)17; SI-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 glc18; SI-NEXT: s_waitcnt vmcnt(0)19; SI-NEXT: s_mov_b64 s[2:3], s[6:7]20; SI-NEXT: v_sub_i32_e32 v3, vcc, 32, v321; SI-NEXT: v_lshlrev_b32_e32 v2, v3, v222; SI-NEXT: v_lshrrev_b32_e32 v2, v3, v223; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr6424; SI-NEXT: s_endpgm25;26; VI-LABEL: v_ubfe_sub_i32:27; VI: ; %bb.0:28; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2429; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v030; VI-NEXT: s_waitcnt lgkmcnt(0)31; VI-NEXT: v_mov_b32_e32 v1, s332; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v233; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc34; VI-NEXT: flat_load_dword v3, v[0:1] glc35; VI-NEXT: s_waitcnt vmcnt(0)36; VI-NEXT: flat_load_dword v4, v[0:1] glc37; VI-NEXT: s_waitcnt vmcnt(0)38; VI-NEXT: v_mov_b32_e32 v1, s139; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v240; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc41; VI-NEXT: v_sub_u32_e32 v2, vcc, 32, v442; VI-NEXT: v_lshlrev_b32_e32 v3, v2, v343; VI-NEXT: v_lshrrev_b32_e32 v2, v2, v344; VI-NEXT: flat_store_dword v[0:1], v245; VI-NEXT: s_endpgm46 %id.x = tail call i32 @llvm.amdgcn.workitem.id.x()47 %in0.gep = getelementptr i32, ptr addrspace(1) %in0, i32 %id.x48 %in1.gep = getelementptr i32, ptr addrspace(1) %in1, i32 %id.x49 %out.gep = getelementptr i32, ptr addrspace(1) %out, i32 %id.x50 %src = load volatile i32, ptr addrspace(1) %in0.gep51 %width = load volatile i32, ptr addrspace(1) %in0.gep52 %sub = sub i32 32, %width53 %shl = shl i32 %src, %sub54 %bfe = lshr i32 %shl, %sub55 store i32 %bfe, ptr addrspace(1) %out.gep56 ret void57}58 59define amdgpu_kernel void @v_ubfe_sub_multi_use_shl_i32(ptr addrspace(1) %out, ptr addrspace(1) %in0, ptr addrspace(1) %in1) #1 {60; SI-LABEL: v_ubfe_sub_multi_use_shl_i32:61; SI: ; %bb.0:62; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x963; SI-NEXT: s_mov_b32 s6, 064; SI-NEXT: s_mov_b32 s7, 0xf00065; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v066; SI-NEXT: v_mov_b32_e32 v1, 067; SI-NEXT: s_waitcnt lgkmcnt(0)68; SI-NEXT: s_mov_b64 s[4:5], s[2:3]69; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 glc70; SI-NEXT: s_waitcnt vmcnt(0)71; SI-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 glc72; SI-NEXT: s_waitcnt vmcnt(0)73; SI-NEXT: s_mov_b64 s[2:3], s[6:7]74; SI-NEXT: s_mov_b32 s6, -175; SI-NEXT: v_sub_i32_e32 v3, vcc, 32, v376; SI-NEXT: v_lshlrev_b32_e32 v2, v3, v277; SI-NEXT: v_lshrrev_b32_e32 v3, v3, v278; SI-NEXT: buffer_store_dword v3, v[0:1], s[0:3], 0 addr6479; SI-NEXT: buffer_store_dword v2, off, s[4:7], 080; SI-NEXT: s_waitcnt vmcnt(0)81; SI-NEXT: s_endpgm82;83; VI-LABEL: v_ubfe_sub_multi_use_shl_i32:84; VI: ; %bb.0:85; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2486; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v087; VI-NEXT: s_waitcnt lgkmcnt(0)88; VI-NEXT: v_mov_b32_e32 v1, s389; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v290; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc91; VI-NEXT: flat_load_dword v3, v[0:1] glc92; VI-NEXT: s_waitcnt vmcnt(0)93; VI-NEXT: flat_load_dword v4, v[0:1] glc94; VI-NEXT: s_waitcnt vmcnt(0)95; VI-NEXT: v_mov_b32_e32 v1, s196; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v297; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc98; VI-NEXT: v_sub_u32_e32 v2, vcc, 32, v499; VI-NEXT: v_lshlrev_b32_e32 v3, v2, v3100; VI-NEXT: v_lshrrev_b32_e32 v2, v2, v3101; VI-NEXT: flat_store_dword v[0:1], v2102; VI-NEXT: flat_store_dword v[0:1], v3103; VI-NEXT: s_waitcnt vmcnt(0)104; VI-NEXT: s_endpgm105 %id.x = tail call i32 @llvm.amdgcn.workitem.id.x()106 %in0.gep = getelementptr i32, ptr addrspace(1) %in0, i32 %id.x107 %in1.gep = getelementptr i32, ptr addrspace(1) %in1, i32 %id.x108 %out.gep = getelementptr i32, ptr addrspace(1) %out, i32 %id.x109 %src = load volatile i32, ptr addrspace(1) %in0.gep110 %width = load volatile i32, ptr addrspace(1) %in0.gep111 %sub = sub i32 32, %width112 %shl = shl i32 %src, %sub113 %bfe = lshr i32 %shl, %sub114 store i32 %bfe, ptr addrspace(1) %out.gep115 store volatile i32 %shl, ptr addrspace(1) poison116 ret void117}118 119define amdgpu_kernel void @s_ubfe_sub_i32(ptr addrspace(1) %out, i32 %src, i32 %width) #1 {120; SI-LABEL: s_ubfe_sub_i32:121; SI: ; %bb.0:122; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9123; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0124; SI-NEXT: v_mov_b32_e32 v1, 0125; SI-NEXT: s_waitcnt lgkmcnt(0)126; SI-NEXT: s_mov_b64 s[4:5], s[2:3]127; SI-NEXT: s_mov_b32 s3, 0xf000128; SI-NEXT: s_sub_i32 s2, 32, s5129; SI-NEXT: s_lshl_b32 s4, s4, s2130; SI-NEXT: s_lshr_b32 s4, s4, s2131; SI-NEXT: s_mov_b32 s2, 0132; SI-NEXT: v_mov_b32_e32 v2, s4133; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64134; SI-NEXT: s_endpgm135;136; VI-LABEL: s_ubfe_sub_i32:137; VI: ; %bb.0:138; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24139; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0140; VI-NEXT: s_waitcnt lgkmcnt(0)141; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0142; VI-NEXT: s_sub_i32 s0, 32, s3143; VI-NEXT: v_mov_b32_e32 v1, s1144; VI-NEXT: s_lshl_b32 s1, s2, s0145; VI-NEXT: s_lshr_b32 s0, s1, s0146; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc147; VI-NEXT: v_mov_b32_e32 v2, s0148; VI-NEXT: flat_store_dword v[0:1], v2149; VI-NEXT: s_endpgm150 %id.x = tail call i32 @llvm.amdgcn.workitem.id.x()151 %out.gep = getelementptr i32, ptr addrspace(1) %out, i32 %id.x152 %sub = sub i32 32, %width153 %shl = shl i32 %src, %sub154 %bfe = lshr i32 %shl, %sub155 store i32 %bfe, ptr addrspace(1) %out.gep156 ret void157}158 159define amdgpu_kernel void @s_ubfe_sub_multi_use_shl_i32(ptr addrspace(1) %out, i32 %src, i32 %width) #1 {160; SI-LABEL: s_ubfe_sub_multi_use_shl_i32:161; SI: ; %bb.0:162; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9163; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0164; SI-NEXT: v_mov_b32_e32 v1, 0165; SI-NEXT: s_waitcnt lgkmcnt(0)166; SI-NEXT: s_mov_b64 s[4:5], s[2:3]167; SI-NEXT: s_mov_b32 s2, 0168; SI-NEXT: s_sub_i32 s3, 32, s5169; SI-NEXT: s_lshl_b32 s4, s4, s3170; SI-NEXT: s_lshr_b32 s5, s4, s3171; SI-NEXT: s_mov_b32 s3, 0xf000172; SI-NEXT: v_mov_b32_e32 v2, s5173; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64174; SI-NEXT: s_mov_b32 s2, -1175; SI-NEXT: v_mov_b32_e32 v0, s4176; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0177; SI-NEXT: s_waitcnt vmcnt(0)178; SI-NEXT: s_endpgm179;180; VI-LABEL: s_ubfe_sub_multi_use_shl_i32:181; VI: ; %bb.0:182; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24183; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0184; VI-NEXT: s_waitcnt lgkmcnt(0)185; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0186; VI-NEXT: s_sub_i32 s0, 32, s3187; VI-NEXT: v_mov_b32_e32 v1, s1188; VI-NEXT: s_lshl_b32 s1, s2, s0189; VI-NEXT: s_lshr_b32 s0, s1, s0190; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc191; VI-NEXT: v_mov_b32_e32 v2, s0192; VI-NEXT: flat_store_dword v[0:1], v2193; VI-NEXT: v_mov_b32_e32 v0, s1194; VI-NEXT: flat_store_dword v[0:1], v0195; VI-NEXT: s_waitcnt vmcnt(0)196; VI-NEXT: s_endpgm197 %id.x = tail call i32 @llvm.amdgcn.workitem.id.x()198 %out.gep = getelementptr i32, ptr addrspace(1) %out, i32 %id.x199 %sub = sub i32 32, %width200 %shl = shl i32 %src, %sub201 %bfe = lshr i32 %shl, %sub202 store i32 %bfe, ptr addrspace(1) %out.gep203 store volatile i32 %shl, ptr addrspace(1) poison204 ret void205}206 207define amdgpu_kernel void @v_sbfe_sub_i32(ptr addrspace(1) %out, ptr addrspace(1) %in0, ptr addrspace(1) %in1) #1 {208; SI-LABEL: v_sbfe_sub_i32:209; SI: ; %bb.0:210; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9211; SI-NEXT: s_mov_b32 s7, 0xf000212; SI-NEXT: s_mov_b32 s6, 0213; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0214; SI-NEXT: v_mov_b32_e32 v1, 0215; SI-NEXT: s_waitcnt lgkmcnt(0)216; SI-NEXT: s_mov_b64 s[4:5], s[2:3]217; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 glc218; SI-NEXT: s_waitcnt vmcnt(0)219; SI-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 glc220; SI-NEXT: s_waitcnt vmcnt(0)221; SI-NEXT: s_mov_b64 s[2:3], s[6:7]222; SI-NEXT: v_sub_i32_e32 v3, vcc, 32, v3223; SI-NEXT: v_lshlrev_b32_e32 v2, v3, v2224; SI-NEXT: v_ashrrev_i32_e32 v2, v3, v2225; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64226; SI-NEXT: s_endpgm227;228; VI-LABEL: v_sbfe_sub_i32:229; VI: ; %bb.0:230; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24231; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0232; VI-NEXT: s_waitcnt lgkmcnt(0)233; VI-NEXT: v_mov_b32_e32 v1, s3234; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2235; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc236; VI-NEXT: flat_load_dword v3, v[0:1] glc237; VI-NEXT: s_waitcnt vmcnt(0)238; VI-NEXT: flat_load_dword v4, v[0:1] glc239; VI-NEXT: s_waitcnt vmcnt(0)240; VI-NEXT: v_mov_b32_e32 v1, s1241; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2242; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc243; VI-NEXT: v_sub_u32_e32 v2, vcc, 32, v4244; VI-NEXT: v_lshlrev_b32_e32 v3, v2, v3245; VI-NEXT: v_ashrrev_i32_e32 v2, v2, v3246; VI-NEXT: flat_store_dword v[0:1], v2247; VI-NEXT: s_endpgm248 %id.x = tail call i32 @llvm.amdgcn.workitem.id.x()249 %in0.gep = getelementptr i32, ptr addrspace(1) %in0, i32 %id.x250 %in1.gep = getelementptr i32, ptr addrspace(1) %in1, i32 %id.x251 %out.gep = getelementptr i32, ptr addrspace(1) %out, i32 %id.x252 %src = load volatile i32, ptr addrspace(1) %in0.gep253 %width = load volatile i32, ptr addrspace(1) %in0.gep254 %sub = sub i32 32, %width255 %shl = shl i32 %src, %sub256 %bfe = ashr i32 %shl, %sub257 store i32 %bfe, ptr addrspace(1) %out.gep258 ret void259}260 261define amdgpu_kernel void @v_sbfe_sub_multi_use_shl_i32(ptr addrspace(1) %out, ptr addrspace(1) %in0, ptr addrspace(1) %in1) #1 {262; SI-LABEL: v_sbfe_sub_multi_use_shl_i32:263; SI: ; %bb.0:264; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9265; SI-NEXT: s_mov_b32 s6, 0266; SI-NEXT: s_mov_b32 s7, 0xf000267; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0268; SI-NEXT: v_mov_b32_e32 v1, 0269; SI-NEXT: s_waitcnt lgkmcnt(0)270; SI-NEXT: s_mov_b64 s[4:5], s[2:3]271; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 glc272; SI-NEXT: s_waitcnt vmcnt(0)273; SI-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 glc274; SI-NEXT: s_waitcnt vmcnt(0)275; SI-NEXT: s_mov_b64 s[2:3], s[6:7]276; SI-NEXT: s_mov_b32 s6, -1277; SI-NEXT: v_sub_i32_e32 v3, vcc, 32, v3278; SI-NEXT: v_lshlrev_b32_e32 v2, v3, v2279; SI-NEXT: v_ashrrev_i32_e32 v3, v3, v2280; SI-NEXT: buffer_store_dword v3, v[0:1], s[0:3], 0 addr64281; SI-NEXT: buffer_store_dword v2, off, s[4:7], 0282; SI-NEXT: s_waitcnt vmcnt(0)283; SI-NEXT: s_endpgm284;285; VI-LABEL: v_sbfe_sub_multi_use_shl_i32:286; VI: ; %bb.0:287; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24288; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0289; VI-NEXT: s_waitcnt lgkmcnt(0)290; VI-NEXT: v_mov_b32_e32 v1, s3291; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2292; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc293; VI-NEXT: flat_load_dword v3, v[0:1] glc294; VI-NEXT: s_waitcnt vmcnt(0)295; VI-NEXT: flat_load_dword v4, v[0:1] glc296; VI-NEXT: s_waitcnt vmcnt(0)297; VI-NEXT: v_mov_b32_e32 v1, s1298; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2299; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc300; VI-NEXT: v_sub_u32_e32 v2, vcc, 32, v4301; VI-NEXT: v_lshlrev_b32_e32 v3, v2, v3302; VI-NEXT: v_ashrrev_i32_e32 v2, v2, v3303; VI-NEXT: flat_store_dword v[0:1], v2304; VI-NEXT: flat_store_dword v[0:1], v3305; VI-NEXT: s_waitcnt vmcnt(0)306; VI-NEXT: s_endpgm307 %id.x = tail call i32 @llvm.amdgcn.workitem.id.x()308 %in0.gep = getelementptr i32, ptr addrspace(1) %in0, i32 %id.x309 %in1.gep = getelementptr i32, ptr addrspace(1) %in1, i32 %id.x310 %out.gep = getelementptr i32, ptr addrspace(1) %out, i32 %id.x311 %src = load volatile i32, ptr addrspace(1) %in0.gep312 %width = load volatile i32, ptr addrspace(1) %in0.gep313 %sub = sub i32 32, %width314 %shl = shl i32 %src, %sub315 %bfe = ashr i32 %shl, %sub316 store i32 %bfe, ptr addrspace(1) %out.gep317 store volatile i32 %shl, ptr addrspace(1) poison318 ret void319}320 321define amdgpu_kernel void @s_sbfe_sub_i32(ptr addrspace(1) %out, i32 %src, i32 %width) #1 {322; SI-LABEL: s_sbfe_sub_i32:323; SI: ; %bb.0:324; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9325; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0326; SI-NEXT: v_mov_b32_e32 v1, 0327; SI-NEXT: s_waitcnt lgkmcnt(0)328; SI-NEXT: s_mov_b64 s[4:5], s[2:3]329; SI-NEXT: s_mov_b32 s3, 0xf000330; SI-NEXT: s_sub_i32 s2, 32, s5331; SI-NEXT: s_lshl_b32 s4, s4, s2332; SI-NEXT: s_ashr_i32 s4, s4, s2333; SI-NEXT: s_mov_b32 s2, 0334; SI-NEXT: v_mov_b32_e32 v2, s4335; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64336; SI-NEXT: s_endpgm337;338; VI-LABEL: s_sbfe_sub_i32:339; VI: ; %bb.0:340; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24341; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0342; VI-NEXT: s_waitcnt lgkmcnt(0)343; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0344; VI-NEXT: s_sub_i32 s0, 32, s3345; VI-NEXT: v_mov_b32_e32 v1, s1346; VI-NEXT: s_lshl_b32 s1, s2, s0347; VI-NEXT: s_ashr_i32 s0, s1, s0348; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc349; VI-NEXT: v_mov_b32_e32 v2, s0350; VI-NEXT: flat_store_dword v[0:1], v2351; VI-NEXT: s_endpgm352 %id.x = tail call i32 @llvm.amdgcn.workitem.id.x()353 %out.gep = getelementptr i32, ptr addrspace(1) %out, i32 %id.x354 %sub = sub i32 32, %width355 %shl = shl i32 %src, %sub356 %bfe = ashr i32 %shl, %sub357 store i32 %bfe, ptr addrspace(1) %out.gep358 ret void359}360 361define amdgpu_kernel void @s_sbfe_sub_multi_use_shl_i32(ptr addrspace(1) %out, i32 %src, i32 %width) #1 {362; SI-LABEL: s_sbfe_sub_multi_use_shl_i32:363; SI: ; %bb.0:364; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9365; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0366; SI-NEXT: v_mov_b32_e32 v1, 0367; SI-NEXT: s_waitcnt lgkmcnt(0)368; SI-NEXT: s_mov_b64 s[4:5], s[2:3]369; SI-NEXT: s_mov_b32 s2, 0370; SI-NEXT: s_sub_i32 s3, 32, s5371; SI-NEXT: s_lshl_b32 s4, s4, s3372; SI-NEXT: s_ashr_i32 s5, s4, s3373; SI-NEXT: s_mov_b32 s3, 0xf000374; SI-NEXT: v_mov_b32_e32 v2, s5375; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64376; SI-NEXT: s_mov_b32 s2, -1377; SI-NEXT: v_mov_b32_e32 v0, s4378; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0379; SI-NEXT: s_waitcnt vmcnt(0)380; SI-NEXT: s_endpgm381;382; VI-LABEL: s_sbfe_sub_multi_use_shl_i32:383; VI: ; %bb.0:384; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24385; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0386; VI-NEXT: s_waitcnt lgkmcnt(0)387; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0388; VI-NEXT: s_sub_i32 s0, 32, s3389; VI-NEXT: v_mov_b32_e32 v1, s1390; VI-NEXT: s_lshl_b32 s1, s2, s0391; VI-NEXT: s_ashr_i32 s0, s1, s0392; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc393; VI-NEXT: v_mov_b32_e32 v2, s0394; VI-NEXT: flat_store_dword v[0:1], v2395; VI-NEXT: v_mov_b32_e32 v0, s1396; VI-NEXT: flat_store_dword v[0:1], v0397; VI-NEXT: s_waitcnt vmcnt(0)398; VI-NEXT: s_endpgm399 %id.x = tail call i32 @llvm.amdgcn.workitem.id.x()400 %out.gep = getelementptr i32, ptr addrspace(1) %out, i32 %id.x401 %sub = sub i32 32, %width402 %shl = shl i32 %src, %sub403 %bfe = ashr i32 %shl, %sub404 store i32 %bfe, ptr addrspace(1) %out.gep405 store volatile i32 %shl, ptr addrspace(1) poison406 ret void407}408 409define amdgpu_kernel void @s_sbfe_or_shl_shl_uniform_i32(ptr addrspace(1) %out, ptr addrspace(1) %in0, ptr addrspace(1) %in1) {410; SI-LABEL: s_sbfe_or_shl_shl_uniform_i32:411; SI: ; %bb.0:412; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9413; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd414; SI-NEXT: s_waitcnt lgkmcnt(0)415; SI-NEXT: s_load_dword s2, s[2:3], 0x0416; SI-NEXT: s_load_dword s4, s[4:5], 0x0417; SI-NEXT: s_mov_b32 s3, 0xf000418; SI-NEXT: s_waitcnt lgkmcnt(0)419; SI-NEXT: s_or_b32 s2, s2, s4420; SI-NEXT: s_bfe_i32 s4, s2, 0xf0000421; SI-NEXT: s_mov_b32 s2, -1422; SI-NEXT: v_mov_b32_e32 v0, s4423; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0424; SI-NEXT: s_endpgm425;426; VI-LABEL: s_sbfe_or_shl_shl_uniform_i32:427; VI: ; %bb.0:428; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24429; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34430; VI-NEXT: s_waitcnt lgkmcnt(0)431; VI-NEXT: s_load_dword s2, s[2:3], 0x0432; VI-NEXT: s_load_dword s3, s[4:5], 0x0433; VI-NEXT: v_mov_b32_e32 v0, s0434; VI-NEXT: v_mov_b32_e32 v1, s1435; VI-NEXT: s_waitcnt lgkmcnt(0)436; VI-NEXT: s_or_b32 s0, s2, s3437; VI-NEXT: s_bfe_i32 s0, s0, 0xf0000438; VI-NEXT: v_mov_b32_e32 v2, s0439; VI-NEXT: flat_store_dword v[0:1], v2440; VI-NEXT: s_endpgm441 %a0 = load i32, ptr addrspace(1) %in0442 %b0 = load i32, ptr addrspace(1) %in1443 %a1 = shl i32 %a0, 17444 %b1 = shl i32 %b0, 17445 %or = or i32 %a1, %b1446 %result = ashr i32 %or, 17447 store i32 %result, ptr addrspace(1) %out448 ret void449}450 451; TODO ashr(or(shl(x,c1),shl(y,c2)),c1) -> sign_extend_inreg(or(x,shl(y,c2-c1))) iff c2 >= c1452define amdgpu_kernel void @s_sbfe_or_shl_shl_nonuniform_i32(ptr addrspace(1) %out, ptr addrspace(1) %x, ptr addrspace(1) %y) {453; SI-LABEL: s_sbfe_or_shl_shl_nonuniform_i32:454; SI: ; %bb.0:455; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9456; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd457; SI-NEXT: s_waitcnt lgkmcnt(0)458; SI-NEXT: s_load_dword s2, s[2:3], 0x0459; SI-NEXT: s_load_dword s4, s[4:5], 0x0460; SI-NEXT: s_mov_b32 s3, 0xf000461; SI-NEXT: s_waitcnt lgkmcnt(0)462; SI-NEXT: s_lshl_b32 s2, s2, 17463; SI-NEXT: s_lshl_b32 s4, s4, 19464; SI-NEXT: s_or_b32 s2, s2, s4465; SI-NEXT: s_ashr_i32 s4, s2, 17466; SI-NEXT: s_mov_b32 s2, -1467; SI-NEXT: v_mov_b32_e32 v0, s4468; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0469; SI-NEXT: s_endpgm470;471; VI-LABEL: s_sbfe_or_shl_shl_nonuniform_i32:472; VI: ; %bb.0:473; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24474; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34475; VI-NEXT: s_waitcnt lgkmcnt(0)476; VI-NEXT: s_load_dword s2, s[2:3], 0x0477; VI-NEXT: s_load_dword s3, s[4:5], 0x0478; VI-NEXT: v_mov_b32_e32 v0, s0479; VI-NEXT: v_mov_b32_e32 v1, s1480; VI-NEXT: s_waitcnt lgkmcnt(0)481; VI-NEXT: s_lshl_b32 s0, s2, 17482; VI-NEXT: s_lshl_b32 s1, s3, 19483; VI-NEXT: s_or_b32 s0, s0, s1484; VI-NEXT: s_ashr_i32 s0, s0, 17485; VI-NEXT: v_mov_b32_e32 v2, s0486; VI-NEXT: flat_store_dword v[0:1], v2487; VI-NEXT: s_endpgm488 %a0 = load i32, ptr addrspace(1) %x489 %b0 = load i32, ptr addrspace(1) %y490 %a1 = shl i32 %a0, 17491 %b1 = shl i32 %b0, 19492 %or = or i32 %a1, %b1493 %result = ashr i32 %or, 17494 store i32 %result, ptr addrspace(1) %out495 ret void496}497 498; Don't fold as 'other shl' amount is less than the sign_extend_inreg type.499define amdgpu_kernel void @s_sbfe_or_shl_shl_toosmall_i32(ptr addrspace(1) %out, ptr addrspace(1) %x, ptr addrspace(1) %y) {500; SI-LABEL: s_sbfe_or_shl_shl_toosmall_i32:501; SI: ; %bb.0:502; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9503; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd504; SI-NEXT: s_waitcnt lgkmcnt(0)505; SI-NEXT: s_load_dword s2, s[2:3], 0x0506; SI-NEXT: s_load_dword s4, s[4:5], 0x0507; SI-NEXT: s_mov_b32 s3, 0xf000508; SI-NEXT: s_waitcnt lgkmcnt(0)509; SI-NEXT: s_lshl_b32 s2, s2, 17510; SI-NEXT: s_lshl_b32 s4, s4, 16511; SI-NEXT: s_or_b32 s2, s2, s4512; SI-NEXT: s_ashr_i32 s4, s2, 17513; SI-NEXT: s_mov_b32 s2, -1514; SI-NEXT: v_mov_b32_e32 v0, s4515; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0516; SI-NEXT: s_endpgm517;518; VI-LABEL: s_sbfe_or_shl_shl_toosmall_i32:519; VI: ; %bb.0:520; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24521; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34522; VI-NEXT: s_waitcnt lgkmcnt(0)523; VI-NEXT: s_load_dword s2, s[2:3], 0x0524; VI-NEXT: s_load_dword s3, s[4:5], 0x0525; VI-NEXT: v_mov_b32_e32 v0, s0526; VI-NEXT: v_mov_b32_e32 v1, s1527; VI-NEXT: s_waitcnt lgkmcnt(0)528; VI-NEXT: s_lshl_b32 s0, s2, 17529; VI-NEXT: s_lshl_b32 s1, s3, 16530; VI-NEXT: s_or_b32 s0, s0, s1531; VI-NEXT: s_ashr_i32 s0, s0, 17532; VI-NEXT: v_mov_b32_e32 v2, s0533; VI-NEXT: flat_store_dword v[0:1], v2534; VI-NEXT: s_endpgm535 %a0 = load i32, ptr addrspace(1) %x536 %b0 = load i32, ptr addrspace(1) %y537 %a1 = shl i32 %a0, 17538 %b1 = shl i32 %b0, 16539 %or = or i32 %a1, %b1540 %result = ashr i32 %or, 17541 store i32 %result, ptr addrspace(1) %out542 ret void543}544 545declare i32 @llvm.amdgcn.workitem.id.x() #0546 547attributes #0 = { nounwind readnone }548attributes #1 = { nounwind }549