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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -enable-var-scope -check-prefix=GFX7 %s3; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -enable-var-scope -check-prefix=GFX8 %s4; RUN: llc -mtriple=amdgcn -mcpu=gfx1031 < %s | FileCheck -enable-var-scope -check-prefix=GFX10 %s5; RUN: llc -global-isel -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -enable-var-scope -check-prefix=GFX8-GISEL %s6; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1031 < %s | FileCheck -enable-var-scope -check-prefix=GFX10-GISEL %s7 8; BFI_INT Definition pattern from ISA docs9; (y & x) | (z & ~x)10;11define amdgpu_kernel void @s_bfi_def_i32(ptr addrspace(1) %out, i32 %x, i32 %y, i32 %z) {12; GFX7-LABEL: s_bfi_def_i32:13; GFX7: ; %bb.0: ; %entry14; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb15; GFX7-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x916; GFX7-NEXT: s_mov_b32 s7, 0xf00017; GFX7-NEXT: s_mov_b32 s6, -118; GFX7-NEXT: s_waitcnt lgkmcnt(0)19; GFX7-NEXT: s_xor_b32 s1, s1, s220; GFX7-NEXT: s_and_b32 s0, s1, s021; GFX7-NEXT: s_xor_b32 s0, s0, s222; GFX7-NEXT: v_mov_b32_e32 v0, s023; GFX7-NEXT: buffer_store_dword v0, off, s[4:7], 024; GFX7-NEXT: s_endpgm25;26; GFX8-LABEL: s_bfi_def_i32:27; GFX8: ; %bb.0: ; %entry28; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c29; GFX8-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x2430; GFX8-NEXT: s_waitcnt lgkmcnt(0)31; GFX8-NEXT: s_xor_b32 s1, s1, s232; GFX8-NEXT: s_and_b32 s0, s1, s033; GFX8-NEXT: s_xor_b32 s0, s0, s234; GFX8-NEXT: v_mov_b32_e32 v0, s435; GFX8-NEXT: v_mov_b32_e32 v1, s536; GFX8-NEXT: v_mov_b32_e32 v2, s037; GFX8-NEXT: flat_store_dword v[0:1], v238; GFX8-NEXT: s_endpgm39;40; GFX10-LABEL: s_bfi_def_i32:41; GFX10: ; %bb.0: ; %entry42; GFX10-NEXT: s_clause 0x143; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c44; GFX10-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x2445; GFX10-NEXT: v_mov_b32_e32 v0, 046; GFX10-NEXT: s_waitcnt lgkmcnt(0)47; GFX10-NEXT: s_xor_b32 s1, s1, s248; GFX10-NEXT: s_and_b32 s0, s1, s049; GFX10-NEXT: s_xor_b32 s0, s0, s250; GFX10-NEXT: v_mov_b32_e32 v1, s051; GFX10-NEXT: global_store_dword v0, v1, s[4:5]52; GFX10-NEXT: s_endpgm53;54; GFX8-GISEL-LABEL: s_bfi_def_i32:55; GFX8-GISEL: ; %bb.0: ; %entry56; GFX8-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2457; GFX8-GISEL-NEXT: s_load_dword s4, s[4:5], 0x3458; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)59; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, s060; GFX8-GISEL-NEXT: s_andn2_b32 s4, s4, s261; GFX8-GISEL-NEXT: s_and_b32 s2, s3, s262; GFX8-GISEL-NEXT: s_or_b32 s2, s4, s263; GFX8-GISEL-NEXT: v_mov_b32_e32 v2, s264; GFX8-GISEL-NEXT: v_mov_b32_e32 v1, s165; GFX8-GISEL-NEXT: flat_store_dword v[0:1], v266; GFX8-GISEL-NEXT: s_endpgm67;68; GFX10-GISEL-LABEL: s_bfi_def_i32:69; GFX10-GISEL: ; %bb.0: ; %entry70; GFX10-GISEL-NEXT: s_clause 0x171; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2472; GFX10-GISEL-NEXT: s_load_dword s4, s[4:5], 0x3473; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, 074; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)75; GFX10-GISEL-NEXT: s_andn2_b32 s4, s4, s276; GFX10-GISEL-NEXT: s_and_b32 s2, s3, s277; GFX10-GISEL-NEXT: s_or_b32 s2, s4, s278; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s279; GFX10-GISEL-NEXT: global_store_dword v1, v0, s[0:1]80; GFX10-GISEL-NEXT: s_endpgm81entry:82 %0 = xor i32 %x, -183 %1 = and i32 %z, %084 %2 = and i32 %y, %x85 %3 = or i32 %1, %286 store i32 %3, ptr addrspace(1) %out87 ret void88}89 90define i32 @v_bfi_def_i32(i32 %x, i32 %y, i32 %z) {91; GFX7-LABEL: v_bfi_def_i32:92; GFX7: ; %bb.0: ; %entry93; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)94; GFX7-NEXT: v_bfi_b32 v0, v0, v1, v295; GFX7-NEXT: s_setpc_b64 s[30:31]96;97; GFX8-LABEL: v_bfi_def_i32:98; GFX8: ; %bb.0: ; %entry99; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)100; GFX8-NEXT: v_bfi_b32 v0, v0, v1, v2101; GFX8-NEXT: s_setpc_b64 s[30:31]102;103; GFX10-LABEL: v_bfi_def_i32:104; GFX10: ; %bb.0: ; %entry105; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)106; GFX10-NEXT: v_bfi_b32 v0, v0, v1, v2107; GFX10-NEXT: s_setpc_b64 s[30:31]108;109; GFX8-GISEL-LABEL: v_bfi_def_i32:110; GFX8-GISEL: ; %bb.0: ; %entry111; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)112; GFX8-GISEL-NEXT: v_bfi_b32 v0, v0, v1, v2113; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]114;115; GFX10-GISEL-LABEL: v_bfi_def_i32:116; GFX10-GISEL: ; %bb.0: ; %entry117; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)118; GFX10-GISEL-NEXT: v_bfi_b32 v0, v0, v1, v2119; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]120entry:121 %0 = xor i32 %x, -1122 %1 = and i32 %z, %0123 %2 = and i32 %y, %x124 %3 = or i32 %1, %2125 ret i32 %3126}127 128; SHA-256 Ch function129; z ^ (x & (y ^ z))130define amdgpu_kernel void @s_bfi_sha256_ch(ptr addrspace(1) %out, i32 %x, i32 %y, i32 %z) {131; GFX7-LABEL: s_bfi_sha256_ch:132; GFX7: ; %bb.0: ; %entry133; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb134; GFX7-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9135; GFX7-NEXT: s_mov_b32 s7, 0xf000136; GFX7-NEXT: s_mov_b32 s6, -1137; GFX7-NEXT: s_waitcnt lgkmcnt(0)138; GFX7-NEXT: s_xor_b32 s1, s1, s2139; GFX7-NEXT: s_and_b32 s0, s0, s1140; GFX7-NEXT: s_xor_b32 s0, s2, s0141; GFX7-NEXT: v_mov_b32_e32 v0, s0142; GFX7-NEXT: buffer_store_dword v0, off, s[4:7], 0143; GFX7-NEXT: s_endpgm144;145; GFX8-LABEL: s_bfi_sha256_ch:146; GFX8: ; %bb.0: ; %entry147; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c148; GFX8-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24149; GFX8-NEXT: s_waitcnt lgkmcnt(0)150; GFX8-NEXT: s_xor_b32 s1, s1, s2151; GFX8-NEXT: s_and_b32 s0, s0, s1152; GFX8-NEXT: s_xor_b32 s0, s2, s0153; GFX8-NEXT: v_mov_b32_e32 v0, s4154; GFX8-NEXT: v_mov_b32_e32 v1, s5155; GFX8-NEXT: v_mov_b32_e32 v2, s0156; GFX8-NEXT: flat_store_dword v[0:1], v2157; GFX8-NEXT: s_endpgm158;159; GFX10-LABEL: s_bfi_sha256_ch:160; GFX10: ; %bb.0: ; %entry161; GFX10-NEXT: s_clause 0x1162; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c163; GFX10-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24164; GFX10-NEXT: v_mov_b32_e32 v0, 0165; GFX10-NEXT: s_waitcnt lgkmcnt(0)166; GFX10-NEXT: s_xor_b32 s1, s1, s2167; GFX10-NEXT: s_and_b32 s0, s0, s1168; GFX10-NEXT: s_xor_b32 s0, s2, s0169; GFX10-NEXT: v_mov_b32_e32 v1, s0170; GFX10-NEXT: global_store_dword v0, v1, s[4:5]171; GFX10-NEXT: s_endpgm172;173; GFX8-GISEL-LABEL: s_bfi_sha256_ch:174; GFX8-GISEL: ; %bb.0: ; %entry175; GFX8-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24176; GFX8-GISEL-NEXT: s_load_dword s4, s[4:5], 0x34177; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)178; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, s0179; GFX8-GISEL-NEXT: s_xor_b32 s3, s3, s4180; GFX8-GISEL-NEXT: s_and_b32 s2, s2, s3181; GFX8-GISEL-NEXT: s_xor_b32 s2, s4, s2182; GFX8-GISEL-NEXT: v_mov_b32_e32 v2, s2183; GFX8-GISEL-NEXT: v_mov_b32_e32 v1, s1184; GFX8-GISEL-NEXT: flat_store_dword v[0:1], v2185; GFX8-GISEL-NEXT: s_endpgm186;187; GFX10-GISEL-LABEL: s_bfi_sha256_ch:188; GFX10-GISEL: ; %bb.0: ; %entry189; GFX10-GISEL-NEXT: s_clause 0x1190; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24191; GFX10-GISEL-NEXT: s_load_dword s4, s[4:5], 0x34192; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, 0193; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)194; GFX10-GISEL-NEXT: s_xor_b32 s3, s3, s4195; GFX10-GISEL-NEXT: s_and_b32 s2, s2, s3196; GFX10-GISEL-NEXT: s_xor_b32 s2, s4, s2197; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s2198; GFX10-GISEL-NEXT: global_store_dword v1, v0, s[0:1]199; GFX10-GISEL-NEXT: s_endpgm200entry:201 %0 = xor i32 %y, %z202 %1 = and i32 %x, %0203 %2 = xor i32 %z, %1204 store i32 %2, ptr addrspace(1) %out205 ret void206}207 208define i32 @v_bfi_sha256_ch(i32 %x, i32 %y, i32 %z) {209; GFX7-LABEL: v_bfi_sha256_ch:210; GFX7: ; %bb.0: ; %entry211; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)212; GFX7-NEXT: v_bfi_b32 v0, v0, v1, v2213; GFX7-NEXT: s_setpc_b64 s[30:31]214;215; GFX8-LABEL: v_bfi_sha256_ch:216; GFX8: ; %bb.0: ; %entry217; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)218; GFX8-NEXT: v_bfi_b32 v0, v0, v1, v2219; GFX8-NEXT: s_setpc_b64 s[30:31]220;221; GFX10-LABEL: v_bfi_sha256_ch:222; GFX10: ; %bb.0: ; %entry223; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)224; GFX10-NEXT: v_bfi_b32 v0, v0, v1, v2225; GFX10-NEXT: s_setpc_b64 s[30:31]226;227; GFX8-GISEL-LABEL: v_bfi_sha256_ch:228; GFX8-GISEL: ; %bb.0: ; %entry229; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)230; GFX8-GISEL-NEXT: v_bfi_b32 v0, v0, v1, v2231; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]232;233; GFX10-GISEL-LABEL: v_bfi_sha256_ch:234; GFX10-GISEL: ; %bb.0: ; %entry235; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)236; GFX10-GISEL-NEXT: v_bfi_b32 v0, v0, v1, v2237; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]238entry:239 %0 = xor i32 %y, %z240 %1 = and i32 %x, %0241 %2 = xor i32 %z, %1242 ret i32 %2243}244 245define amdgpu_ps float @v_s_s_bfi_sha256_ch(i32 %x, i32 inreg %y, i32 inreg %z) {246; GFX7-LABEL: v_s_s_bfi_sha256_ch:247; GFX7: ; %bb.0: ; %entry248; GFX7-NEXT: v_mov_b32_e32 v1, s0249; GFX7-NEXT: v_bfi_b32 v0, v0, v1, s1250; GFX7-NEXT: ; return to shader part epilog251;252; GFX8-LABEL: v_s_s_bfi_sha256_ch:253; GFX8: ; %bb.0: ; %entry254; GFX8-NEXT: v_mov_b32_e32 v1, s0255; GFX8-NEXT: v_bfi_b32 v0, v0, v1, s1256; GFX8-NEXT: ; return to shader part epilog257;258; GFX10-LABEL: v_s_s_bfi_sha256_ch:259; GFX10: ; %bb.0: ; %entry260; GFX10-NEXT: v_bfi_b32 v0, v0, s0, s1261; GFX10-NEXT: ; return to shader part epilog262;263; GFX8-GISEL-LABEL: v_s_s_bfi_sha256_ch:264; GFX8-GISEL: ; %bb.0: ; %entry265; GFX8-GISEL-NEXT: v_mov_b32_e32 v1, s0266; GFX8-GISEL-NEXT: v_bfi_b32 v0, v0, v1, s1267; GFX8-GISEL-NEXT: ; return to shader part epilog268;269; GFX10-GISEL-LABEL: v_s_s_bfi_sha256_ch:270; GFX10-GISEL: ; %bb.0: ; %entry271; GFX10-GISEL-NEXT: v_bfi_b32 v0, v0, s0, s1272; GFX10-GISEL-NEXT: ; return to shader part epilog273entry:274 %xor0 = xor i32 %y, %z275 %and = and i32 %x, %xor0276 %xor1 = xor i32 %z, %and277 %cast = bitcast i32 %xor1 to float278 ret float %cast279}280 281define amdgpu_ps float @s_v_s_bfi_sha256_ch(i32 inreg %x, i32 %y, i32 inreg %z) {282; GFX7-LABEL: s_v_s_bfi_sha256_ch:283; GFX7: ; %bb.0: ; %entry284; GFX7-NEXT: v_mov_b32_e32 v1, s0285; GFX7-NEXT: v_bfi_b32 v0, v1, v0, s1286; GFX7-NEXT: ; return to shader part epilog287;288; GFX8-LABEL: s_v_s_bfi_sha256_ch:289; GFX8: ; %bb.0: ; %entry290; GFX8-NEXT: v_mov_b32_e32 v1, s0291; GFX8-NEXT: v_bfi_b32 v0, v1, v0, s1292; GFX8-NEXT: ; return to shader part epilog293;294; GFX10-LABEL: s_v_s_bfi_sha256_ch:295; GFX10: ; %bb.0: ; %entry296; GFX10-NEXT: v_bfi_b32 v0, s0, v0, s1297; GFX10-NEXT: ; return to shader part epilog298;299; GFX8-GISEL-LABEL: s_v_s_bfi_sha256_ch:300; GFX8-GISEL: ; %bb.0: ; %entry301; GFX8-GISEL-NEXT: v_mov_b32_e32 v1, s1302; GFX8-GISEL-NEXT: v_bfi_b32 v0, s0, v0, v1303; GFX8-GISEL-NEXT: ; return to shader part epilog304;305; GFX10-GISEL-LABEL: s_v_s_bfi_sha256_ch:306; GFX10-GISEL: ; %bb.0: ; %entry307; GFX10-GISEL-NEXT: v_bfi_b32 v0, s0, v0, s1308; GFX10-GISEL-NEXT: ; return to shader part epilog309entry:310 %xor0 = xor i32 %y, %z311 %and = and i32 %x, %xor0312 %xor1 = xor i32 %z, %and313 %cast = bitcast i32 %xor1 to float314 ret float %cast315}316 317define amdgpu_ps float @s_s_v_bfi_sha256_ch(i32 inreg %x, i32 inreg %y, i32 %z) {318; GFX7-LABEL: s_s_v_bfi_sha256_ch:319; GFX7: ; %bb.0: ; %entry320; GFX7-NEXT: v_mov_b32_e32 v1, s0321; GFX7-NEXT: v_bfi_b32 v0, v1, s1, v0322; GFX7-NEXT: ; return to shader part epilog323;324; GFX8-LABEL: s_s_v_bfi_sha256_ch:325; GFX8: ; %bb.0: ; %entry326; GFX8-NEXT: v_mov_b32_e32 v1, s0327; GFX8-NEXT: v_bfi_b32 v0, v1, s1, v0328; GFX8-NEXT: ; return to shader part epilog329;330; GFX10-LABEL: s_s_v_bfi_sha256_ch:331; GFX10: ; %bb.0: ; %entry332; GFX10-NEXT: v_bfi_b32 v0, s0, s1, v0333; GFX10-NEXT: ; return to shader part epilog334;335; GFX8-GISEL-LABEL: s_s_v_bfi_sha256_ch:336; GFX8-GISEL: ; %bb.0: ; %entry337; GFX8-GISEL-NEXT: v_mov_b32_e32 v1, s0338; GFX8-GISEL-NEXT: v_bfi_b32 v0, v1, s1, v0339; GFX8-GISEL-NEXT: ; return to shader part epilog340;341; GFX10-GISEL-LABEL: s_s_v_bfi_sha256_ch:342; GFX10-GISEL: ; %bb.0: ; %entry343; GFX10-GISEL-NEXT: v_bfi_b32 v0, s0, s1, v0344; GFX10-GISEL-NEXT: ; return to shader part epilog345entry:346 %xor0 = xor i32 %y, %z347 %and = and i32 %x, %xor0348 %xor1 = xor i32 %z, %and349 %cast = bitcast i32 %xor1 to float350 ret float %cast351}352 353define amdgpu_ps float @s_v_v_bfi_sha256_ch(i32 inreg %x, i32 %y, i32 %z) {354; GFX7-LABEL: s_v_v_bfi_sha256_ch:355; GFX7: ; %bb.0: ; %entry356; GFX7-NEXT: v_bfi_b32 v0, s0, v0, v1357; GFX7-NEXT: ; return to shader part epilog358;359; GFX8-LABEL: s_v_v_bfi_sha256_ch:360; GFX8: ; %bb.0: ; %entry361; GFX8-NEXT: v_bfi_b32 v0, s0, v0, v1362; GFX8-NEXT: ; return to shader part epilog363;364; GFX10-LABEL: s_v_v_bfi_sha256_ch:365; GFX10: ; %bb.0: ; %entry366; GFX10-NEXT: v_bfi_b32 v0, s0, v0, v1367; GFX10-NEXT: ; return to shader part epilog368;369; GFX8-GISEL-LABEL: s_v_v_bfi_sha256_ch:370; GFX8-GISEL: ; %bb.0: ; %entry371; GFX8-GISEL-NEXT: v_bfi_b32 v0, s0, v0, v1372; GFX8-GISEL-NEXT: ; return to shader part epilog373;374; GFX10-GISEL-LABEL: s_v_v_bfi_sha256_ch:375; GFX10-GISEL: ; %bb.0: ; %entry376; GFX10-GISEL-NEXT: v_bfi_b32 v0, s0, v0, v1377; GFX10-GISEL-NEXT: ; return to shader part epilog378entry:379 %xor0 = xor i32 %y, %z380 %and = and i32 %x, %xor0381 %xor1 = xor i32 %z, %and382 %cast = bitcast i32 %xor1 to float383 ret float %cast384}385 386define amdgpu_ps float @v_s_v_bfi_sha256_ch(i32 %x, i32 inreg %y, i32 %z) {387; GFX7-LABEL: v_s_v_bfi_sha256_ch:388; GFX7: ; %bb.0: ; %entry389; GFX7-NEXT: v_bfi_b32 v0, v0, s0, v1390; GFX7-NEXT: ; return to shader part epilog391;392; GFX8-LABEL: v_s_v_bfi_sha256_ch:393; GFX8: ; %bb.0: ; %entry394; GFX8-NEXT: v_bfi_b32 v0, v0, s0, v1395; GFX8-NEXT: ; return to shader part epilog396;397; GFX10-LABEL: v_s_v_bfi_sha256_ch:398; GFX10: ; %bb.0: ; %entry399; GFX10-NEXT: v_bfi_b32 v0, v0, s0, v1400; GFX10-NEXT: ; return to shader part epilog401;402; GFX8-GISEL-LABEL: v_s_v_bfi_sha256_ch:403; GFX8-GISEL: ; %bb.0: ; %entry404; GFX8-GISEL-NEXT: v_bfi_b32 v0, v0, s0, v1405; GFX8-GISEL-NEXT: ; return to shader part epilog406;407; GFX10-GISEL-LABEL: v_s_v_bfi_sha256_ch:408; GFX10-GISEL: ; %bb.0: ; %entry409; GFX10-GISEL-NEXT: v_bfi_b32 v0, v0, s0, v1410; GFX10-GISEL-NEXT: ; return to shader part epilog411entry:412 %xor0 = xor i32 %y, %z413 %and = and i32 %x, %xor0414 %xor1 = xor i32 %z, %and415 %cast = bitcast i32 %xor1 to float416 ret float %cast417}418 419define amdgpu_ps float @v_v_s_bfi_sha256_ch(i32 %x, i32 %y, i32 inreg %z) {420; GFX7-LABEL: v_v_s_bfi_sha256_ch:421; GFX7: ; %bb.0: ; %entry422; GFX7-NEXT: v_bfi_b32 v0, v0, v1, s0423; GFX7-NEXT: ; return to shader part epilog424;425; GFX8-LABEL: v_v_s_bfi_sha256_ch:426; GFX8: ; %bb.0: ; %entry427; GFX8-NEXT: v_bfi_b32 v0, v0, v1, s0428; GFX8-NEXT: ; return to shader part epilog429;430; GFX10-LABEL: v_v_s_bfi_sha256_ch:431; GFX10: ; %bb.0: ; %entry432; GFX10-NEXT: v_bfi_b32 v0, v0, v1, s0433; GFX10-NEXT: ; return to shader part epilog434;435; GFX8-GISEL-LABEL: v_v_s_bfi_sha256_ch:436; GFX8-GISEL: ; %bb.0: ; %entry437; GFX8-GISEL-NEXT: v_bfi_b32 v0, v0, v1, s0438; GFX8-GISEL-NEXT: ; return to shader part epilog439;440; GFX10-GISEL-LABEL: v_v_s_bfi_sha256_ch:441; GFX10-GISEL: ; %bb.0: ; %entry442; GFX10-GISEL-NEXT: v_bfi_b32 v0, v0, v1, s0443; GFX10-GISEL-NEXT: ; return to shader part epilog444entry:445 %xor0 = xor i32 %y, %z446 %and = and i32 %x, %xor0447 %xor1 = xor i32 %z, %and448 %cast = bitcast i32 %xor1 to float449 ret float %cast450}451 452; SHA-256 Ma function453; ((x & z) | (y & (x | z)))454define amdgpu_kernel void @s_bfi_sha256_ma(ptr addrspace(1) %out, i32 %x, i32 %y, i32 %z) {455; GFX7-LABEL: s_bfi_sha256_ma:456; GFX7: ; %bb.0: ; %entry457; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb458; GFX7-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9459; GFX7-NEXT: s_mov_b32 s7, 0xf000460; GFX7-NEXT: s_mov_b32 s6, -1461; GFX7-NEXT: s_waitcnt lgkmcnt(0)462; GFX7-NEXT: s_and_b32 s3, s0, s2463; GFX7-NEXT: s_or_b32 s0, s0, s2464; GFX7-NEXT: s_and_b32 s0, s1, s0465; GFX7-NEXT: s_or_b32 s0, s3, s0466; GFX7-NEXT: v_mov_b32_e32 v0, s0467; GFX7-NEXT: buffer_store_dword v0, off, s[4:7], 0468; GFX7-NEXT: s_endpgm469;470; GFX8-LABEL: s_bfi_sha256_ma:471; GFX8: ; %bb.0: ; %entry472; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c473; GFX8-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24474; GFX8-NEXT: s_waitcnt lgkmcnt(0)475; GFX8-NEXT: s_and_b32 s3, s0, s2476; GFX8-NEXT: s_or_b32 s0, s0, s2477; GFX8-NEXT: s_and_b32 s0, s1, s0478; GFX8-NEXT: s_or_b32 s0, s3, s0479; GFX8-NEXT: v_mov_b32_e32 v0, s4480; GFX8-NEXT: v_mov_b32_e32 v1, s5481; GFX8-NEXT: v_mov_b32_e32 v2, s0482; GFX8-NEXT: flat_store_dword v[0:1], v2483; GFX8-NEXT: s_endpgm484;485; GFX10-LABEL: s_bfi_sha256_ma:486; GFX10: ; %bb.0: ; %entry487; GFX10-NEXT: s_clause 0x1488; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c489; GFX10-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24490; GFX10-NEXT: v_mov_b32_e32 v0, 0491; GFX10-NEXT: s_waitcnt lgkmcnt(0)492; GFX10-NEXT: s_or_b32 s3, s0, s2493; GFX10-NEXT: s_and_b32 s0, s0, s2494; GFX10-NEXT: s_and_b32 s1, s1, s3495; GFX10-NEXT: s_or_b32 s0, s0, s1496; GFX10-NEXT: v_mov_b32_e32 v1, s0497; GFX10-NEXT: global_store_dword v0, v1, s[4:5]498; GFX10-NEXT: s_endpgm499;500; GFX8-GISEL-LABEL: s_bfi_sha256_ma:501; GFX8-GISEL: ; %bb.0: ; %entry502; GFX8-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24503; GFX8-GISEL-NEXT: s_load_dword s4, s[4:5], 0x34504; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)505; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, s0506; GFX8-GISEL-NEXT: s_and_b32 s5, s2, s4507; GFX8-GISEL-NEXT: s_or_b32 s2, s2, s4508; GFX8-GISEL-NEXT: s_and_b32 s2, s3, s2509; GFX8-GISEL-NEXT: s_or_b32 s2, s5, s2510; GFX8-GISEL-NEXT: v_mov_b32_e32 v2, s2511; GFX8-GISEL-NEXT: v_mov_b32_e32 v1, s1512; GFX8-GISEL-NEXT: flat_store_dword v[0:1], v2513; GFX8-GISEL-NEXT: s_endpgm514;515; GFX10-GISEL-LABEL: s_bfi_sha256_ma:516; GFX10-GISEL: ; %bb.0: ; %entry517; GFX10-GISEL-NEXT: s_clause 0x1518; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24519; GFX10-GISEL-NEXT: s_load_dword s4, s[4:5], 0x34520; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, 0521; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)522; GFX10-GISEL-NEXT: s_or_b32 s5, s2, s4523; GFX10-GISEL-NEXT: s_and_b32 s2, s2, s4524; GFX10-GISEL-NEXT: s_and_b32 s3, s3, s5525; GFX10-GISEL-NEXT: s_or_b32 s2, s2, s3526; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s2527; GFX10-GISEL-NEXT: global_store_dword v1, v0, s[0:1]528; GFX10-GISEL-NEXT: s_endpgm529entry:530 %0 = and i32 %x, %z531 %1 = or i32 %x, %z532 %2 = and i32 %y, %1533 %3 = or i32 %0, %2534 store i32 %3, ptr addrspace(1) %out535 ret void536}537 538define i32 @v_bfi_sha256_ma(i32 %x, i32 %y, i32 %z) {539; GFX7-LABEL: v_bfi_sha256_ma:540; GFX7: ; %bb.0: ; %entry541; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)542; GFX7-NEXT: v_xor_b32_e32 v0, v0, v1543; GFX7-NEXT: v_bfi_b32 v0, v0, v2, v1544; GFX7-NEXT: s_setpc_b64 s[30:31]545;546; GFX8-LABEL: v_bfi_sha256_ma:547; GFX8: ; %bb.0: ; %entry548; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)549; GFX8-NEXT: v_xor_b32_e32 v0, v0, v1550; GFX8-NEXT: v_bfi_b32 v0, v0, v2, v1551; GFX8-NEXT: s_setpc_b64 s[30:31]552;553; GFX10-LABEL: v_bfi_sha256_ma:554; GFX10: ; %bb.0: ; %entry555; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)556; GFX10-NEXT: v_xor_b32_e32 v0, v0, v1557; GFX10-NEXT: v_bfi_b32 v0, v0, v2, v1558; GFX10-NEXT: s_setpc_b64 s[30:31]559;560; GFX8-GISEL-LABEL: v_bfi_sha256_ma:561; GFX8-GISEL: ; %bb.0: ; %entry562; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)563; GFX8-GISEL-NEXT: v_xor_b32_e32 v0, v0, v1564; GFX8-GISEL-NEXT: v_bfi_b32 v0, v0, v2, v1565; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]566;567; GFX10-GISEL-LABEL: v_bfi_sha256_ma:568; GFX10-GISEL: ; %bb.0: ; %entry569; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)570; GFX10-GISEL-NEXT: v_xor_b32_e32 v0, v0, v1571; GFX10-GISEL-NEXT: v_bfi_b32 v0, v0, v2, v1572; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]573entry:574 %0 = and i32 %x, %z575 %1 = or i32 %x, %z576 %2 = and i32 %y, %1577 %3 = or i32 %0, %2578 ret i32 %3579}580 581define <2 x i32> @v_bitselect_v2i32_pat1(<2 x i32> %a, <2 x i32> %b, <2 x i32> %mask) {582; GFX7-LABEL: v_bitselect_v2i32_pat1:583; GFX7: ; %bb.0:584; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)585; GFX7-NEXT: v_bfi_b32 v1, v3, v1, v5586; GFX7-NEXT: v_bfi_b32 v0, v2, v0, v4587; GFX7-NEXT: s_setpc_b64 s[30:31]588;589; GFX8-LABEL: v_bitselect_v2i32_pat1:590; GFX8: ; %bb.0:591; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)592; GFX8-NEXT: v_bfi_b32 v1, v3, v1, v5593; GFX8-NEXT: v_bfi_b32 v0, v2, v0, v4594; GFX8-NEXT: s_setpc_b64 s[30:31]595;596; GFX10-LABEL: v_bitselect_v2i32_pat1:597; GFX10: ; %bb.0:598; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)599; GFX10-NEXT: v_bfi_b32 v0, v2, v0, v4600; GFX10-NEXT: v_bfi_b32 v1, v3, v1, v5601; GFX10-NEXT: s_setpc_b64 s[30:31]602;603; GFX8-GISEL-LABEL: v_bitselect_v2i32_pat1:604; GFX8-GISEL: ; %bb.0:605; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)606; GFX8-GISEL-NEXT: v_bfi_b32 v0, v2, v0, v4607; GFX8-GISEL-NEXT: v_bfi_b32 v1, v3, v1, v5608; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]609;610; GFX10-GISEL-LABEL: v_bitselect_v2i32_pat1:611; GFX10-GISEL: ; %bb.0:612; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)613; GFX10-GISEL-NEXT: v_bfi_b32 v0, v2, v0, v4614; GFX10-GISEL-NEXT: v_bfi_b32 v1, v3, v1, v5615; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]616 %xor.0 = xor <2 x i32> %a, %mask617 %and = and <2 x i32> %xor.0, %b618 %bitselect = xor <2 x i32> %and, %mask619 ret <2 x i32> %bitselect620}621 622define i64 @v_bitselect_i64_pat_0(i64 %a, i64 %b, i64 %mask) {623; GFX7-LABEL: v_bitselect_i64_pat_0:624; GFX7: ; %bb.0:625; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)626; GFX7-NEXT: v_bfi_b32 v1, v1, v3, v5627; GFX7-NEXT: v_bfi_b32 v0, v0, v2, v4628; GFX7-NEXT: s_setpc_b64 s[30:31]629;630; GFX8-LABEL: v_bitselect_i64_pat_0:631; GFX8: ; %bb.0:632; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)633; GFX8-NEXT: v_bfi_b32 v1, v1, v3, v5634; GFX8-NEXT: v_bfi_b32 v0, v0, v2, v4635; GFX8-NEXT: s_setpc_b64 s[30:31]636;637; GFX10-LABEL: v_bitselect_i64_pat_0:638; GFX10: ; %bb.0:639; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)640; GFX10-NEXT: v_bfi_b32 v0, v0, v2, v4641; GFX10-NEXT: v_bfi_b32 v1, v1, v3, v5642; GFX10-NEXT: s_setpc_b64 s[30:31]643;644; GFX8-GISEL-LABEL: v_bitselect_i64_pat_0:645; GFX8-GISEL: ; %bb.0:646; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)647; GFX8-GISEL-NEXT: v_bfi_b32 v0, v0, v2, v4648; GFX8-GISEL-NEXT: v_bfi_b32 v1, v1, v3, v5649; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]650;651; GFX10-GISEL-LABEL: v_bitselect_i64_pat_0:652; GFX10-GISEL: ; %bb.0:653; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)654; GFX10-GISEL-NEXT: v_bfi_b32 v0, v0, v2, v4655; GFX10-GISEL-NEXT: v_bfi_b32 v1, v1, v3, v5656; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]657 %and0 = and i64 %a, %b658 %not.a = xor i64 %a, -1659 %and1 = and i64 %not.a, %mask660 %bitselect = or i64 %and0, %and1661 ret i64 %bitselect662}663 664define amdgpu_ps <2 x float> @v_s_s_bitselect_i64_pat_0(i64 %a, i64 inreg %b, i64 inreg %mask) {665; GFX7-LABEL: v_s_s_bitselect_i64_pat_0:666; GFX7: ; %bb.0:667; GFX7-NEXT: v_mov_b32_e32 v2, s3668; GFX7-NEXT: v_bfi_b32 v1, v1, s1, v2669; GFX7-NEXT: v_mov_b32_e32 v2, s2670; GFX7-NEXT: v_bfi_b32 v0, v0, s0, v2671; GFX7-NEXT: ; return to shader part epilog672;673; GFX8-LABEL: v_s_s_bitselect_i64_pat_0:674; GFX8: ; %bb.0:675; GFX8-NEXT: v_mov_b32_e32 v2, s3676; GFX8-NEXT: v_bfi_b32 v1, v1, s1, v2677; GFX8-NEXT: v_mov_b32_e32 v2, s2678; GFX8-NEXT: v_bfi_b32 v0, v0, s0, v2679; GFX8-NEXT: ; return to shader part epilog680;681; GFX10-LABEL: v_s_s_bitselect_i64_pat_0:682; GFX10: ; %bb.0:683; GFX10-NEXT: v_bfi_b32 v0, v0, s0, s2684; GFX10-NEXT: v_bfi_b32 v1, v1, s1, s3685; GFX10-NEXT: ; return to shader part epilog686;687; GFX8-GISEL-LABEL: v_s_s_bitselect_i64_pat_0:688; GFX8-GISEL: ; %bb.0:689; GFX8-GISEL-NEXT: v_mov_b32_e32 v2, s0690; GFX8-GISEL-NEXT: v_bfi_b32 v0, v0, v2, s2691; GFX8-GISEL-NEXT: v_mov_b32_e32 v2, s1692; GFX8-GISEL-NEXT: v_bfi_b32 v1, v1, v2, s3693; GFX8-GISEL-NEXT: ; return to shader part epilog694;695; GFX10-GISEL-LABEL: v_s_s_bitselect_i64_pat_0:696; GFX10-GISEL: ; %bb.0:697; GFX10-GISEL-NEXT: v_bfi_b32 v0, v0, s0, s2698; GFX10-GISEL-NEXT: v_bfi_b32 v1, v1, s1, s3699; GFX10-GISEL-NEXT: ; return to shader part epilog700 %and0 = and i64 %a, %b701 %not.a = xor i64 %a, -1702 %and1 = and i64 %not.a, %mask703 %bitselect = or i64 %and0, %and1704 %cast = bitcast i64 %bitselect to <2 x float>705 ret <2 x float> %cast706}707 708define amdgpu_ps <2 x float> @s_v_s_bitselect_i64_pat_0(i64 inreg %a, i64 %b, i64 inreg %mask) {709; GFX7-LABEL: s_v_s_bitselect_i64_pat_0:710; GFX7: ; %bb.0:711; GFX7-NEXT: v_mov_b32_e32 v2, s3712; GFX7-NEXT: v_bfi_b32 v1, s1, v1, v2713; GFX7-NEXT: v_mov_b32_e32 v2, s2714; GFX7-NEXT: v_bfi_b32 v0, s0, v0, v2715; GFX7-NEXT: ; return to shader part epilog716;717; GFX8-LABEL: s_v_s_bitselect_i64_pat_0:718; GFX8: ; %bb.0:719; GFX8-NEXT: v_mov_b32_e32 v2, s3720; GFX8-NEXT: v_bfi_b32 v1, s1, v1, v2721; GFX8-NEXT: v_mov_b32_e32 v2, s2722; GFX8-NEXT: v_bfi_b32 v0, s0, v0, v2723; GFX8-NEXT: ; return to shader part epilog724;725; GFX10-LABEL: s_v_s_bitselect_i64_pat_0:726; GFX10: ; %bb.0:727; GFX10-NEXT: v_bfi_b32 v0, s0, v0, s2728; GFX10-NEXT: v_bfi_b32 v1, s1, v1, s3729; GFX10-NEXT: ; return to shader part epilog730;731; GFX8-GISEL-LABEL: s_v_s_bitselect_i64_pat_0:732; GFX8-GISEL: ; %bb.0:733; GFX8-GISEL-NEXT: v_and_b32_e32 v0, s0, v0734; GFX8-GISEL-NEXT: v_and_b32_e32 v1, s1, v1735; GFX8-GISEL-NEXT: s_andn2_b64 s[0:1], s[2:3], s[0:1]736; GFX8-GISEL-NEXT: v_or_b32_e32 v0, s0, v0737; GFX8-GISEL-NEXT: v_or_b32_e32 v1, s1, v1738; GFX8-GISEL-NEXT: ; return to shader part epilog739;740; GFX10-GISEL-LABEL: s_v_s_bitselect_i64_pat_0:741; GFX10-GISEL: ; %bb.0:742; GFX10-GISEL-NEXT: s_andn2_b64 s[2:3], s[2:3], s[0:1]743; GFX10-GISEL-NEXT: v_and_or_b32 v0, s0, v0, s2744; GFX10-GISEL-NEXT: v_and_or_b32 v1, s1, v1, s3745; GFX10-GISEL-NEXT: ; return to shader part epilog746 %and0 = and i64 %a, %b747 %not.a = xor i64 %a, -1748 %and1 = and i64 %not.a, %mask749 %bitselect = or i64 %and0, %and1750 %cast = bitcast i64 %bitselect to <2 x float>751 ret <2 x float> %cast752}753 754define amdgpu_ps <2 x float> @s_s_v_bitselect_i64_pat_0(i64 inreg %a, i64 inreg %b, i64 %mask) {755; GFX7-LABEL: s_s_v_bitselect_i64_pat_0:756; GFX7: ; %bb.0:757; GFX7-NEXT: v_mov_b32_e32 v2, s3758; GFX7-NEXT: v_bfi_b32 v1, s1, v2, v1759; GFX7-NEXT: v_mov_b32_e32 v2, s2760; GFX7-NEXT: v_bfi_b32 v0, s0, v2, v0761; GFX7-NEXT: ; return to shader part epilog762;763; GFX8-LABEL: s_s_v_bitselect_i64_pat_0:764; GFX8: ; %bb.0:765; GFX8-NEXT: v_mov_b32_e32 v2, s3766; GFX8-NEXT: v_bfi_b32 v1, s1, v2, v1767; GFX8-NEXT: v_mov_b32_e32 v2, s2768; GFX8-NEXT: v_bfi_b32 v0, s0, v2, v0769; GFX8-NEXT: ; return to shader part epilog770;771; GFX10-LABEL: s_s_v_bitselect_i64_pat_0:772; GFX10: ; %bb.0:773; GFX10-NEXT: v_bfi_b32 v0, s0, s2, v0774; GFX10-NEXT: v_bfi_b32 v1, s1, s3, v1775; GFX10-NEXT: ; return to shader part epilog776;777; GFX8-GISEL-LABEL: s_s_v_bitselect_i64_pat_0:778; GFX8-GISEL: ; %bb.0:779; GFX8-GISEL-NEXT: s_and_b64 s[2:3], s[0:1], s[2:3]780; GFX8-GISEL-NEXT: s_not_b64 s[0:1], s[0:1]781; GFX8-GISEL-NEXT: v_and_b32_e32 v0, s0, v0782; GFX8-GISEL-NEXT: v_and_b32_e32 v1, s1, v1783; GFX8-GISEL-NEXT: v_or_b32_e32 v0, s2, v0784; GFX8-GISEL-NEXT: v_or_b32_e32 v1, s3, v1785; GFX8-GISEL-NEXT: ; return to shader part epilog786;787; GFX10-GISEL-LABEL: s_s_v_bitselect_i64_pat_0:788; GFX10-GISEL: ; %bb.0:789; GFX10-GISEL-NEXT: s_and_b64 s[2:3], s[0:1], s[2:3]790; GFX10-GISEL-NEXT: s_not_b64 s[0:1], s[0:1]791; GFX10-GISEL-NEXT: v_and_or_b32 v0, s0, v0, s2792; GFX10-GISEL-NEXT: v_and_or_b32 v1, s1, v1, s3793; GFX10-GISEL-NEXT: ; return to shader part epilog794 %and0 = and i64 %a, %b795 %not.a = xor i64 %a, -1796 %and1 = and i64 %not.a, %mask797 %bitselect = or i64 %and0, %and1798 %cast = bitcast i64 %bitselect to <2 x float>799 ret <2 x float> %cast800}801 802define amdgpu_ps <2 x float> @v_v_s_bitselect_i64_pat_0(i64 %a, i64 %b, i64 inreg %mask) {803; GFX7-LABEL: v_v_s_bitselect_i64_pat_0:804; GFX7: ; %bb.0:805; GFX7-NEXT: v_bfi_b32 v1, v1, v3, s1806; GFX7-NEXT: v_bfi_b32 v0, v0, v2, s0807; GFX7-NEXT: ; return to shader part epilog808;809; GFX8-LABEL: v_v_s_bitselect_i64_pat_0:810; GFX8: ; %bb.0:811; GFX8-NEXT: v_bfi_b32 v1, v1, v3, s1812; GFX8-NEXT: v_bfi_b32 v0, v0, v2, s0813; GFX8-NEXT: ; return to shader part epilog814;815; GFX10-LABEL: v_v_s_bitselect_i64_pat_0:816; GFX10: ; %bb.0:817; GFX10-NEXT: v_bfi_b32 v0, v0, v2, s0818; GFX10-NEXT: v_bfi_b32 v1, v1, v3, s1819; GFX10-NEXT: ; return to shader part epilog820;821; GFX8-GISEL-LABEL: v_v_s_bitselect_i64_pat_0:822; GFX8-GISEL: ; %bb.0:823; GFX8-GISEL-NEXT: v_bfi_b32 v0, v0, v2, s0824; GFX8-GISEL-NEXT: v_bfi_b32 v1, v1, v3, s1825; GFX8-GISEL-NEXT: ; return to shader part epilog826;827; GFX10-GISEL-LABEL: v_v_s_bitselect_i64_pat_0:828; GFX10-GISEL: ; %bb.0:829; GFX10-GISEL-NEXT: v_bfi_b32 v0, v0, v2, s0830; GFX10-GISEL-NEXT: v_bfi_b32 v1, v1, v3, s1831; GFX10-GISEL-NEXT: ; return to shader part epilog832 %and0 = and i64 %a, %b833 %not.a = xor i64 %a, -1834 %and1 = and i64 %not.a, %mask835 %bitselect = or i64 %and0, %and1836 %cast = bitcast i64 %bitselect to <2 x float>837 ret <2 x float> %cast838}839 840define amdgpu_ps <2 x float> @v_s_v_bitselect_i64_pat_0(i64 %a, i64 inreg %b, i64 %mask) {841; GFX7-LABEL: v_s_v_bitselect_i64_pat_0:842; GFX7: ; %bb.0:843; GFX7-NEXT: v_bfi_b32 v1, v1, s1, v3844; GFX7-NEXT: v_bfi_b32 v0, v0, s0, v2845; GFX7-NEXT: ; return to shader part epilog846;847; GFX8-LABEL: v_s_v_bitselect_i64_pat_0:848; GFX8: ; %bb.0:849; GFX8-NEXT: v_bfi_b32 v1, v1, s1, v3850; GFX8-NEXT: v_bfi_b32 v0, v0, s0, v2851; GFX8-NEXT: ; return to shader part epilog852;853; GFX10-LABEL: v_s_v_bitselect_i64_pat_0:854; GFX10: ; %bb.0:855; GFX10-NEXT: v_bfi_b32 v0, v0, s0, v2856; GFX10-NEXT: v_bfi_b32 v1, v1, s1, v3857; GFX10-NEXT: ; return to shader part epilog858;859; GFX8-GISEL-LABEL: v_s_v_bitselect_i64_pat_0:860; GFX8-GISEL: ; %bb.0:861; GFX8-GISEL-NEXT: v_bfi_b32 v0, v0, s0, v2862; GFX8-GISEL-NEXT: v_bfi_b32 v1, v1, s1, v3863; GFX8-GISEL-NEXT: ; return to shader part epilog864;865; GFX10-GISEL-LABEL: v_s_v_bitselect_i64_pat_0:866; GFX10-GISEL: ; %bb.0:867; GFX10-GISEL-NEXT: v_bfi_b32 v0, v0, s0, v2868; GFX10-GISEL-NEXT: v_bfi_b32 v1, v1, s1, v3869; GFX10-GISEL-NEXT: ; return to shader part epilog870 %and0 = and i64 %a, %b871 %not.a = xor i64 %a, -1872 %and1 = and i64 %not.a, %mask873 %bitselect = or i64 %and0, %and1874 %cast = bitcast i64 %bitselect to <2 x float>875 ret <2 x float> %cast876}877 878define amdgpu_ps <2 x float> @s_v_v_bitselect_i64_pat_0(i64 inreg %a, i64 %b, i64 %mask) {879; GFX7-LABEL: s_v_v_bitselect_i64_pat_0:880; GFX7: ; %bb.0:881; GFX7-NEXT: v_bfi_b32 v1, s1, v1, v3882; GFX7-NEXT: v_bfi_b32 v0, s0, v0, v2883; GFX7-NEXT: ; return to shader part epilog884;885; GFX8-LABEL: s_v_v_bitselect_i64_pat_0:886; GFX8: ; %bb.0:887; GFX8-NEXT: v_bfi_b32 v1, s1, v1, v3888; GFX8-NEXT: v_bfi_b32 v0, s0, v0, v2889; GFX8-NEXT: ; return to shader part epilog890;891; GFX10-LABEL: s_v_v_bitselect_i64_pat_0:892; GFX10: ; %bb.0:893; GFX10-NEXT: v_bfi_b32 v0, s0, v0, v2894; GFX10-NEXT: v_bfi_b32 v1, s1, v1, v3895; GFX10-NEXT: ; return to shader part epilog896;897; GFX8-GISEL-LABEL: s_v_v_bitselect_i64_pat_0:898; GFX8-GISEL: ; %bb.0:899; GFX8-GISEL-NEXT: v_and_b32_e32 v0, s0, v0900; GFX8-GISEL-NEXT: v_and_b32_e32 v1, s1, v1901; GFX8-GISEL-NEXT: s_not_b64 s[0:1], s[0:1]902; GFX8-GISEL-NEXT: v_and_b32_e32 v2, s0, v2903; GFX8-GISEL-NEXT: v_and_b32_e32 v3, s1, v3904; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v0, v2905; GFX8-GISEL-NEXT: v_or_b32_e32 v1, v1, v3906; GFX8-GISEL-NEXT: ; return to shader part epilog907;908; GFX10-GISEL-LABEL: s_v_v_bitselect_i64_pat_0:909; GFX10-GISEL: ; %bb.0:910; GFX10-GISEL-NEXT: s_not_b64 s[2:3], s[0:1]911; GFX10-GISEL-NEXT: v_and_b32_e32 v2, s2, v2912; GFX10-GISEL-NEXT: v_and_b32_e32 v3, s3, v3913; GFX10-GISEL-NEXT: v_and_or_b32 v0, s0, v0, v2914; GFX10-GISEL-NEXT: v_and_or_b32 v1, s1, v1, v3915; GFX10-GISEL-NEXT: ; return to shader part epilog916 %and0 = and i64 %a, %b917 %not.a = xor i64 %a, -1918 %and1 = and i64 %not.a, %mask919 %bitselect = or i64 %and0, %and1920 %cast = bitcast i64 %bitselect to <2 x float>921 ret <2 x float> %cast922}923 924define i64 @v_bitselect_i64_pat_1(i64 %a, i64 %b, i64 %mask) {925; GFX7-LABEL: v_bitselect_i64_pat_1:926; GFX7: ; %bb.0:927; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)928; GFX7-NEXT: v_bfi_b32 v1, v3, v1, v5929; GFX7-NEXT: v_bfi_b32 v0, v2, v0, v4930; GFX7-NEXT: s_setpc_b64 s[30:31]931;932; GFX8-LABEL: v_bitselect_i64_pat_1:933; GFX8: ; %bb.0:934; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)935; GFX8-NEXT: v_bfi_b32 v1, v3, v1, v5936; GFX8-NEXT: v_bfi_b32 v0, v2, v0, v4937; GFX8-NEXT: s_setpc_b64 s[30:31]938;939; GFX10-LABEL: v_bitselect_i64_pat_1:940; GFX10: ; %bb.0:941; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)942; GFX10-NEXT: v_bfi_b32 v0, v2, v0, v4943; GFX10-NEXT: v_bfi_b32 v1, v3, v1, v5944; GFX10-NEXT: s_setpc_b64 s[30:31]945;946; GFX8-GISEL-LABEL: v_bitselect_i64_pat_1:947; GFX8-GISEL: ; %bb.0:948; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)949; GFX8-GISEL-NEXT: v_bfi_b32 v0, v2, v0, v4950; GFX8-GISEL-NEXT: v_bfi_b32 v1, v3, v1, v5951; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]952;953; GFX10-GISEL-LABEL: v_bitselect_i64_pat_1:954; GFX10-GISEL: ; %bb.0:955; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)956; GFX10-GISEL-NEXT: v_bfi_b32 v0, v2, v0, v4957; GFX10-GISEL-NEXT: v_bfi_b32 v1, v3, v1, v5958; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]959 %xor.0 = xor i64 %a, %mask960 %and = and i64 %xor.0, %b961 %bitselect = xor i64 %and, %mask962 ret i64 %bitselect963}964 965define amdgpu_ps <2 x float> @v_s_s_bitselect_i64_pat_1(i64 %a, i64 inreg %b, i64 inreg %mask) {966; GFX7-LABEL: v_s_s_bitselect_i64_pat_1:967; GFX7: ; %bb.0:968; GFX7-NEXT: v_mov_b32_e32 v2, s3969; GFX7-NEXT: v_bfi_b32 v1, s1, v1, v2970; GFX7-NEXT: v_mov_b32_e32 v2, s2971; GFX7-NEXT: v_bfi_b32 v0, s0, v0, v2972; GFX7-NEXT: ; return to shader part epilog973;974; GFX8-LABEL: v_s_s_bitselect_i64_pat_1:975; GFX8: ; %bb.0:976; GFX8-NEXT: v_mov_b32_e32 v2, s3977; GFX8-NEXT: v_bfi_b32 v1, s1, v1, v2978; GFX8-NEXT: v_mov_b32_e32 v2, s2979; GFX8-NEXT: v_bfi_b32 v0, s0, v0, v2980; GFX8-NEXT: ; return to shader part epilog981;982; GFX10-LABEL: v_s_s_bitselect_i64_pat_1:983; GFX10: ; %bb.0:984; GFX10-NEXT: v_bfi_b32 v0, s0, v0, s2985; GFX10-NEXT: v_bfi_b32 v1, s1, v1, s3986; GFX10-NEXT: ; return to shader part epilog987;988; GFX8-GISEL-LABEL: v_s_s_bitselect_i64_pat_1:989; GFX8-GISEL: ; %bb.0:990; GFX8-GISEL-NEXT: v_mov_b32_e32 v2, s0991; GFX8-GISEL-NEXT: v_bfi_b32 v0, v2, v0, s2992; GFX8-GISEL-NEXT: v_mov_b32_e32 v2, s1993; GFX8-GISEL-NEXT: v_bfi_b32 v1, v2, v1, s3994; GFX8-GISEL-NEXT: ; return to shader part epilog995;996; GFX10-GISEL-LABEL: v_s_s_bitselect_i64_pat_1:997; GFX10-GISEL: ; %bb.0:998; GFX10-GISEL-NEXT: v_bfi_b32 v0, s0, v0, s2999; GFX10-GISEL-NEXT: v_bfi_b32 v1, s1, v1, s31000; GFX10-GISEL-NEXT: ; return to shader part epilog1001 %xor.0 = xor i64 %a, %mask1002 %and = and i64 %xor.0, %b1003 %bitselect = xor i64 %and, %mask1004 %cast = bitcast i64 %bitselect to <2 x float>1005 ret <2 x float> %cast1006}1007 1008define amdgpu_ps <2 x float> @s_s_v_bitselect_i64_pat_1(i64 inreg %a, i64 inreg %b, i64 %mask) {1009; GFX7-LABEL: s_s_v_bitselect_i64_pat_1:1010; GFX7: ; %bb.0:1011; GFX7-NEXT: v_mov_b32_e32 v2, s11012; GFX7-NEXT: v_bfi_b32 v1, s3, v2, v11013; GFX7-NEXT: v_mov_b32_e32 v2, s01014; GFX7-NEXT: v_bfi_b32 v0, s2, v2, v01015; GFX7-NEXT: ; return to shader part epilog1016;1017; GFX8-LABEL: s_s_v_bitselect_i64_pat_1:1018; GFX8: ; %bb.0:1019; GFX8-NEXT: v_mov_b32_e32 v2, s11020; GFX8-NEXT: v_bfi_b32 v1, s3, v2, v11021; GFX8-NEXT: v_mov_b32_e32 v2, s01022; GFX8-NEXT: v_bfi_b32 v0, s2, v2, v01023; GFX8-NEXT: ; return to shader part epilog1024;1025; GFX10-LABEL: s_s_v_bitselect_i64_pat_1:1026; GFX10: ; %bb.0:1027; GFX10-NEXT: v_bfi_b32 v0, s2, s0, v01028; GFX10-NEXT: v_bfi_b32 v1, s3, s1, v11029; GFX10-NEXT: ; return to shader part epilog1030;1031; GFX8-GISEL-LABEL: s_s_v_bitselect_i64_pat_1:1032; GFX8-GISEL: ; %bb.0:1033; GFX8-GISEL-NEXT: v_mov_b32_e32 v2, s21034; GFX8-GISEL-NEXT: v_bfi_b32 v0, v2, s0, v01035; GFX8-GISEL-NEXT: v_mov_b32_e32 v2, s31036; GFX8-GISEL-NEXT: v_bfi_b32 v1, v2, s1, v11037; GFX8-GISEL-NEXT: ; return to shader part epilog1038;1039; GFX10-GISEL-LABEL: s_s_v_bitselect_i64_pat_1:1040; GFX10-GISEL: ; %bb.0:1041; GFX10-GISEL-NEXT: v_bfi_b32 v0, s2, s0, v01042; GFX10-GISEL-NEXT: v_bfi_b32 v1, s3, s1, v11043; GFX10-GISEL-NEXT: ; return to shader part epilog1044 %xor.0 = xor i64 %a, %mask1045 %and = and i64 %xor.0, %b1046 %bitselect = xor i64 %and, %mask1047 %cast = bitcast i64 %bitselect to <2 x float>1048 ret <2 x float> %cast1049}1050 1051define amdgpu_ps <2 x float> @s_v_s_bitselect_i64_pat_1(i64 inreg %a, i64 %b, i64 inreg %mask) {1052; GFX7-LABEL: s_v_s_bitselect_i64_pat_1:1053; GFX7: ; %bb.0:1054; GFX7-NEXT: v_mov_b32_e32 v2, s31055; GFX7-NEXT: v_bfi_b32 v1, v1, s1, v21056; GFX7-NEXT: v_mov_b32_e32 v2, s21057; GFX7-NEXT: v_bfi_b32 v0, v0, s0, v21058; GFX7-NEXT: ; return to shader part epilog1059;1060; GFX8-LABEL: s_v_s_bitselect_i64_pat_1:1061; GFX8: ; %bb.0:1062; GFX8-NEXT: v_mov_b32_e32 v2, s31063; GFX8-NEXT: v_bfi_b32 v1, v1, s1, v21064; GFX8-NEXT: v_mov_b32_e32 v2, s21065; GFX8-NEXT: v_bfi_b32 v0, v0, s0, v21066; GFX8-NEXT: ; return to shader part epilog1067;1068; GFX10-LABEL: s_v_s_bitselect_i64_pat_1:1069; GFX10: ; %bb.0:1070; GFX10-NEXT: v_bfi_b32 v0, v0, s0, s21071; GFX10-NEXT: v_bfi_b32 v1, v1, s1, s31072; GFX10-NEXT: ; return to shader part epilog1073;1074; GFX8-GISEL-LABEL: s_v_s_bitselect_i64_pat_1:1075; GFX8-GISEL: ; %bb.0:1076; GFX8-GISEL-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]1077; GFX8-GISEL-NEXT: v_and_b32_e32 v0, s0, v01078; GFX8-GISEL-NEXT: v_and_b32_e32 v1, s1, v11079; GFX8-GISEL-NEXT: v_xor_b32_e32 v0, s2, v01080; GFX8-GISEL-NEXT: v_xor_b32_e32 v1, s3, v11081; GFX8-GISEL-NEXT: ; return to shader part epilog1082;1083; GFX10-GISEL-LABEL: s_v_s_bitselect_i64_pat_1:1084; GFX10-GISEL: ; %bb.0:1085; GFX10-GISEL-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]1086; GFX10-GISEL-NEXT: v_and_b32_e32 v0, s0, v01087; GFX10-GISEL-NEXT: v_and_b32_e32 v1, s1, v11088; GFX10-GISEL-NEXT: v_xor_b32_e32 v0, s2, v01089; GFX10-GISEL-NEXT: v_xor_b32_e32 v1, s3, v11090; GFX10-GISEL-NEXT: ; return to shader part epilog1091 %xor.0 = xor i64 %a, %mask1092 %and = and i64 %xor.0, %b1093 %bitselect = xor i64 %and, %mask1094 %cast = bitcast i64 %bitselect to <2 x float>1095 ret <2 x float> %cast1096}1097 1098define i64 @v_bitselect_i64_pat_2(i64 %a, i64 %b, i64 %mask) {1099; GFX7-LABEL: v_bitselect_i64_pat_2:1100; GFX7: ; %bb.0:1101; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1102; GFX7-NEXT: v_bfi_b32 v1, v3, v1, v51103; GFX7-NEXT: v_bfi_b32 v0, v2, v0, v41104; GFX7-NEXT: s_setpc_b64 s[30:31]1105;1106; GFX8-LABEL: v_bitselect_i64_pat_2:1107; GFX8: ; %bb.0:1108; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1109; GFX8-NEXT: v_bfi_b32 v1, v3, v1, v51110; GFX8-NEXT: v_bfi_b32 v0, v2, v0, v41111; GFX8-NEXT: s_setpc_b64 s[30:31]1112;1113; GFX10-LABEL: v_bitselect_i64_pat_2:1114; GFX10: ; %bb.0:1115; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1116; GFX10-NEXT: v_bfi_b32 v0, v2, v0, v41117; GFX10-NEXT: v_bfi_b32 v1, v3, v1, v51118; GFX10-NEXT: s_setpc_b64 s[30:31]1119;1120; GFX8-GISEL-LABEL: v_bitselect_i64_pat_2:1121; GFX8-GISEL: ; %bb.0:1122; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1123; GFX8-GISEL-NEXT: v_bfi_b32 v0, v2, v0, v41124; GFX8-GISEL-NEXT: v_bfi_b32 v1, v3, v1, v51125; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]1126;1127; GFX10-GISEL-LABEL: v_bitselect_i64_pat_2:1128; GFX10-GISEL: ; %bb.0:1129; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1130; GFX10-GISEL-NEXT: v_bfi_b32 v0, v2, v0, v41131; GFX10-GISEL-NEXT: v_bfi_b32 v1, v3, v1, v51132; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]1133 %xor.0 = xor i64 %a, %mask1134 %and = and i64 %xor.0, %b1135 %bitselect = xor i64 %and, %mask1136 ret i64 %bitselect1137}1138 1139define i64 @v_bfi_sha256_ma_i64(i64 %x, i64 %y, i64 %z) {1140; GFX7-LABEL: v_bfi_sha256_ma_i64:1141; GFX7: ; %bb.0: ; %entry1142; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1143; GFX7-NEXT: v_xor_b32_e32 v1, v1, v31144; GFX7-NEXT: v_xor_b32_e32 v0, v0, v21145; GFX7-NEXT: v_bfi_b32 v1, v1, v5, v31146; GFX7-NEXT: v_bfi_b32 v0, v0, v4, v21147; GFX7-NEXT: s_setpc_b64 s[30:31]1148;1149; GFX8-LABEL: v_bfi_sha256_ma_i64:1150; GFX8: ; %bb.0: ; %entry1151; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1152; GFX8-NEXT: v_xor_b32_e32 v1, v1, v31153; GFX8-NEXT: v_xor_b32_e32 v0, v0, v21154; GFX8-NEXT: v_bfi_b32 v1, v1, v5, v31155; GFX8-NEXT: v_bfi_b32 v0, v0, v4, v21156; GFX8-NEXT: s_setpc_b64 s[30:31]1157;1158; GFX10-LABEL: v_bfi_sha256_ma_i64:1159; GFX10: ; %bb.0: ; %entry1160; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1161; GFX10-NEXT: v_xor_b32_e32 v0, v0, v21162; GFX10-NEXT: v_xor_b32_e32 v1, v1, v31163; GFX10-NEXT: v_bfi_b32 v0, v0, v4, v21164; GFX10-NEXT: v_bfi_b32 v1, v1, v5, v31165; GFX10-NEXT: s_setpc_b64 s[30:31]1166;1167; GFX8-GISEL-LABEL: v_bfi_sha256_ma_i64:1168; GFX8-GISEL: ; %bb.0: ; %entry1169; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1170; GFX8-GISEL-NEXT: v_xor_b32_e32 v0, v0, v21171; GFX8-GISEL-NEXT: v_xor_b32_e32 v1, v1, v31172; GFX8-GISEL-NEXT: v_bfi_b32 v0, v0, v4, v21173; GFX8-GISEL-NEXT: v_bfi_b32 v1, v1, v5, v31174; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]1175;1176; GFX10-GISEL-LABEL: v_bfi_sha256_ma_i64:1177; GFX10-GISEL: ; %bb.0: ; %entry1178; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1179; GFX10-GISEL-NEXT: v_xor_b32_e32 v0, v0, v21180; GFX10-GISEL-NEXT: v_xor_b32_e32 v1, v1, v31181; GFX10-GISEL-NEXT: v_bfi_b32 v0, v0, v4, v21182; GFX10-GISEL-NEXT: v_bfi_b32 v1, v1, v5, v31183; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]1184entry:1185 %and0 = and i64 %x, %z1186 %or0 = or i64 %x, %z1187 %and1 = and i64 %y, %or01188 %or1 = or i64 %and0, %and11189 ret i64 %or11190}1191 1192define amdgpu_ps <2 x float> @v_s_s_bfi_sha256_ma_i64(i64 %x, i64 inreg %y, i64 inreg %z) {1193; GFX7-LABEL: v_s_s_bfi_sha256_ma_i64:1194; GFX7: ; %bb.0: ; %entry1195; GFX7-NEXT: v_xor_b32_e32 v1, s1, v11196; GFX7-NEXT: v_mov_b32_e32 v2, s11197; GFX7-NEXT: v_bfi_b32 v1, v1, s3, v21198; GFX7-NEXT: v_xor_b32_e32 v0, s0, v01199; GFX7-NEXT: v_mov_b32_e32 v2, s01200; GFX7-NEXT: v_bfi_b32 v0, v0, s2, v21201; GFX7-NEXT: ; return to shader part epilog1202;1203; GFX8-LABEL: v_s_s_bfi_sha256_ma_i64:1204; GFX8: ; %bb.0: ; %entry1205; GFX8-NEXT: v_xor_b32_e32 v1, s1, v11206; GFX8-NEXT: v_mov_b32_e32 v2, s11207; GFX8-NEXT: v_bfi_b32 v1, v1, s3, v21208; GFX8-NEXT: v_xor_b32_e32 v0, s0, v01209; GFX8-NEXT: v_mov_b32_e32 v2, s01210; GFX8-NEXT: v_bfi_b32 v0, v0, s2, v21211; GFX8-NEXT: ; return to shader part epilog1212;1213; GFX10-LABEL: v_s_s_bfi_sha256_ma_i64:1214; GFX10: ; %bb.0: ; %entry1215; GFX10-NEXT: v_xor_b32_e32 v0, s0, v01216; GFX10-NEXT: v_xor_b32_e32 v1, s1, v11217; GFX10-NEXT: v_bfi_b32 v0, v0, s2, s01218; GFX10-NEXT: v_bfi_b32 v1, v1, s3, s11219; GFX10-NEXT: ; return to shader part epilog1220;1221; GFX8-GISEL-LABEL: v_s_s_bfi_sha256_ma_i64:1222; GFX8-GISEL: ; %bb.0: ; %entry1223; GFX8-GISEL-NEXT: v_mov_b32_e32 v2, s21224; GFX8-GISEL-NEXT: v_xor_b32_e32 v0, s0, v01225; GFX8-GISEL-NEXT: v_bfi_b32 v0, v0, v2, s01226; GFX8-GISEL-NEXT: v_mov_b32_e32 v2, s31227; GFX8-GISEL-NEXT: v_xor_b32_e32 v1, s1, v11228; GFX8-GISEL-NEXT: v_bfi_b32 v1, v1, v2, s11229; GFX8-GISEL-NEXT: ; return to shader part epilog1230;1231; GFX10-GISEL-LABEL: v_s_s_bfi_sha256_ma_i64:1232; GFX10-GISEL: ; %bb.0: ; %entry1233; GFX10-GISEL-NEXT: v_xor_b32_e32 v0, s0, v01234; GFX10-GISEL-NEXT: v_xor_b32_e32 v1, s1, v11235; GFX10-GISEL-NEXT: v_bfi_b32 v0, v0, s2, s01236; GFX10-GISEL-NEXT: v_bfi_b32 v1, v1, s3, s11237; GFX10-GISEL-NEXT: ; return to shader part epilog1238entry:1239 %and0 = and i64 %x, %z1240 %or0 = or i64 %x, %z1241 %and1 = and i64 %y, %or01242 %or1 = or i64 %and0, %and11243 %cast = bitcast i64 %or1 to <2 x float>1244 ret <2 x float> %cast1245}1246 1247define amdgpu_ps <2 x float> @s_v_s_bfi_sha256_ma_i64(i64 inreg %x, i64 %y, i64 inreg %z) {1248; GFX7-LABEL: s_v_s_bfi_sha256_ma_i64:1249; GFX7: ; %bb.0: ; %entry1250; GFX7-NEXT: v_xor_b32_e32 v2, s1, v11251; GFX7-NEXT: v_bfi_b32 v1, v2, s3, v11252; GFX7-NEXT: v_xor_b32_e32 v2, s0, v01253; GFX7-NEXT: v_bfi_b32 v0, v2, s2, v01254; GFX7-NEXT: ; return to shader part epilog1255;1256; GFX8-LABEL: s_v_s_bfi_sha256_ma_i64:1257; GFX8: ; %bb.0: ; %entry1258; GFX8-NEXT: v_xor_b32_e32 v2, s1, v11259; GFX8-NEXT: v_bfi_b32 v1, v2, s3, v11260; GFX8-NEXT: v_xor_b32_e32 v2, s0, v01261; GFX8-NEXT: v_bfi_b32 v0, v2, s2, v01262; GFX8-NEXT: ; return to shader part epilog1263;1264; GFX10-LABEL: s_v_s_bfi_sha256_ma_i64:1265; GFX10: ; %bb.0: ; %entry1266; GFX10-NEXT: v_xor_b32_e32 v2, s0, v01267; GFX10-NEXT: v_xor_b32_e32 v3, s1, v11268; GFX10-NEXT: v_bfi_b32 v0, v2, s2, v01269; GFX10-NEXT: v_bfi_b32 v1, v3, s3, v11270; GFX10-NEXT: ; return to shader part epilog1271;1272; GFX8-GISEL-LABEL: s_v_s_bfi_sha256_ma_i64:1273; GFX8-GISEL: ; %bb.0: ; %entry1274; GFX8-GISEL-NEXT: s_and_b64 s[4:5], s[0:1], s[2:3]1275; GFX8-GISEL-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]1276; GFX8-GISEL-NEXT: v_and_b32_e32 v0, s0, v01277; GFX8-GISEL-NEXT: v_and_b32_e32 v1, s1, v11278; GFX8-GISEL-NEXT: v_or_b32_e32 v0, s4, v01279; GFX8-GISEL-NEXT: v_or_b32_e32 v1, s5, v11280; GFX8-GISEL-NEXT: ; return to shader part epilog1281;1282; GFX10-GISEL-LABEL: s_v_s_bfi_sha256_ma_i64:1283; GFX10-GISEL: ; %bb.0: ; %entry1284; GFX10-GISEL-NEXT: s_and_b64 s[4:5], s[0:1], s[2:3]1285; GFX10-GISEL-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]1286; GFX10-GISEL-NEXT: v_and_or_b32 v0, v0, s0, s41287; GFX10-GISEL-NEXT: v_and_or_b32 v1, v1, s1, s51288; GFX10-GISEL-NEXT: ; return to shader part epilog1289entry:1290 %and0 = and i64 %x, %z1291 %or0 = or i64 %x, %z1292 %and1 = and i64 %y, %or01293 %or1 = or i64 %and0, %and11294 %cast = bitcast i64 %or1 to <2 x float>1295 ret <2 x float> %cast1296}1297 1298define amdgpu_ps <2 x float> @s_s_v_bfi_sha256_ma_i64(i64 inreg %x, i64 inreg %y, i64 %z) {1299; GFX7-LABEL: s_s_v_bfi_sha256_ma_i64:1300; GFX7: ; %bb.0: ; %entry1301; GFX7-NEXT: v_mov_b32_e32 v2, s31302; GFX7-NEXT: v_xor_b32_e32 v2, s1, v21303; GFX7-NEXT: v_bfi_b32 v1, v2, v1, s31304; GFX7-NEXT: v_mov_b32_e32 v2, s21305; GFX7-NEXT: v_xor_b32_e32 v2, s0, v21306; GFX7-NEXT: v_bfi_b32 v0, v2, v0, s21307; GFX7-NEXT: ; return to shader part epilog1308;1309; GFX8-LABEL: s_s_v_bfi_sha256_ma_i64:1310; GFX8: ; %bb.0: ; %entry1311; GFX8-NEXT: v_mov_b32_e32 v2, s31312; GFX8-NEXT: v_xor_b32_e32 v2, s1, v21313; GFX8-NEXT: v_bfi_b32 v1, v2, v1, s31314; GFX8-NEXT: v_mov_b32_e32 v2, s21315; GFX8-NEXT: v_xor_b32_e32 v2, s0, v21316; GFX8-NEXT: v_bfi_b32 v0, v2, v0, s21317; GFX8-NEXT: ; return to shader part epilog1318;1319; GFX10-LABEL: s_s_v_bfi_sha256_ma_i64:1320; GFX10: ; %bb.0: ; %entry1321; GFX10-NEXT: v_xor_b32_e64 v2, s0, s21322; GFX10-NEXT: v_xor_b32_e64 v3, s1, s31323; GFX10-NEXT: v_bfi_b32 v0, v2, v0, s21324; GFX10-NEXT: v_bfi_b32 v1, v3, v1, s31325; GFX10-NEXT: ; return to shader part epilog1326;1327; GFX8-GISEL-LABEL: s_s_v_bfi_sha256_ma_i64:1328; GFX8-GISEL: ; %bb.0: ; %entry1329; GFX8-GISEL-NEXT: v_mov_b32_e32 v2, s01330; GFX8-GISEL-NEXT: v_xor_b32_e32 v2, s2, v21331; GFX8-GISEL-NEXT: v_bfi_b32 v0, v2, v0, s21332; GFX8-GISEL-NEXT: v_mov_b32_e32 v2, s11333; GFX8-GISEL-NEXT: v_xor_b32_e32 v2, s3, v21334; GFX8-GISEL-NEXT: v_bfi_b32 v1, v2, v1, s31335; GFX8-GISEL-NEXT: ; return to shader part epilog1336;1337; GFX10-GISEL-LABEL: s_s_v_bfi_sha256_ma_i64:1338; GFX10-GISEL: ; %bb.0: ; %entry1339; GFX10-GISEL-NEXT: v_xor_b32_e64 v2, s0, s21340; GFX10-GISEL-NEXT: v_xor_b32_e64 v3, s1, s31341; GFX10-GISEL-NEXT: v_bfi_b32 v0, v2, v0, s21342; GFX10-GISEL-NEXT: v_bfi_b32 v1, v3, v1, s31343; GFX10-GISEL-NEXT: ; return to shader part epilog1344entry:1345 %and0 = and i64 %x, %z1346 %or0 = or i64 %x, %z1347 %and1 = and i64 %y, %or01348 %or1 = or i64 %and0, %and11349 %cast = bitcast i64 %or1 to <2 x float>1350 ret <2 x float> %cast1351}1352 1353define amdgpu_ps <2 x float> @v_s_v_bfi_sha256_ma_i64(i64 %x, i64 inreg %y, i64 %z) {1354; GFX7-LABEL: v_s_v_bfi_sha256_ma_i64:1355; GFX7: ; %bb.0: ; %entry1356; GFX7-NEXT: v_xor_b32_e32 v1, s1, v11357; GFX7-NEXT: v_xor_b32_e32 v0, s0, v01358; GFX7-NEXT: v_bfi_b32 v1, v1, v3, s11359; GFX7-NEXT: v_bfi_b32 v0, v0, v2, s01360; GFX7-NEXT: ; return to shader part epilog1361;1362; GFX8-LABEL: v_s_v_bfi_sha256_ma_i64:1363; GFX8: ; %bb.0: ; %entry1364; GFX8-NEXT: v_xor_b32_e32 v1, s1, v11365; GFX8-NEXT: v_xor_b32_e32 v0, s0, v01366; GFX8-NEXT: v_bfi_b32 v1, v1, v3, s11367; GFX8-NEXT: v_bfi_b32 v0, v0, v2, s01368; GFX8-NEXT: ; return to shader part epilog1369;1370; GFX10-LABEL: v_s_v_bfi_sha256_ma_i64:1371; GFX10: ; %bb.0: ; %entry1372; GFX10-NEXT: v_xor_b32_e32 v0, s0, v01373; GFX10-NEXT: v_xor_b32_e32 v1, s1, v11374; GFX10-NEXT: v_bfi_b32 v0, v0, v2, s01375; GFX10-NEXT: v_bfi_b32 v1, v1, v3, s11376; GFX10-NEXT: ; return to shader part epilog1377;1378; GFX8-GISEL-LABEL: v_s_v_bfi_sha256_ma_i64:1379; GFX8-GISEL: ; %bb.0: ; %entry1380; GFX8-GISEL-NEXT: v_xor_b32_e32 v0, s0, v01381; GFX8-GISEL-NEXT: v_xor_b32_e32 v1, s1, v11382; GFX8-GISEL-NEXT: v_bfi_b32 v0, v0, v2, s01383; GFX8-GISEL-NEXT: v_bfi_b32 v1, v1, v3, s11384; GFX8-GISEL-NEXT: ; return to shader part epilog1385;1386; GFX10-GISEL-LABEL: v_s_v_bfi_sha256_ma_i64:1387; GFX10-GISEL: ; %bb.0: ; %entry1388; GFX10-GISEL-NEXT: v_xor_b32_e32 v0, s0, v01389; GFX10-GISEL-NEXT: v_xor_b32_e32 v1, s1, v11390; GFX10-GISEL-NEXT: v_bfi_b32 v0, v0, v2, s01391; GFX10-GISEL-NEXT: v_bfi_b32 v1, v1, v3, s11392; GFX10-GISEL-NEXT: ; return to shader part epilog1393entry:1394 %and0 = and i64 %x, %z1395 %or0 = or i64 %x, %z1396 %and1 = and i64 %y, %or01397 %or1 = or i64 %and0, %and11398 %cast = bitcast i64 %or1 to <2 x float>1399 ret <2 x float> %cast1400}1401 1402define amdgpu_kernel void @s_bitselect_i64_pat_0(i64 %a, i64 %b, i64 %mask) {1403; GFX7-LABEL: s_bitselect_i64_pat_0:1404; GFX7: ; %bb.0:1405; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91406; GFX7-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd1407; GFX7-NEXT: s_mov_b32 s7, 0xf0001408; GFX7-NEXT: s_mov_b32 s6, -11409; GFX7-NEXT: s_waitcnt lgkmcnt(0)1410; GFX7-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5]1411; GFX7-NEXT: s_and_b64 s[0:1], s[2:3], s[0:1]1412; GFX7-NEXT: s_xor_b64 s[0:1], s[0:1], s[4:5]1413; GFX7-NEXT: s_add_u32 s0, s0, 101414; GFX7-NEXT: s_addc_u32 s1, s1, 01415; GFX7-NEXT: v_mov_b32_e32 v0, s01416; GFX7-NEXT: v_mov_b32_e32 v1, s11417; GFX7-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 01418; GFX7-NEXT: s_endpgm1419;1420; GFX8-LABEL: s_bitselect_i64_pat_0:1421; GFX8: ; %bb.0:1422; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241423; GFX8-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x341424; GFX8-NEXT: s_waitcnt lgkmcnt(0)1425; GFX8-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5]1426; GFX8-NEXT: s_and_b64 s[0:1], s[2:3], s[0:1]1427; GFX8-NEXT: s_xor_b64 s[0:1], s[0:1], s[4:5]1428; GFX8-NEXT: s_add_u32 s0, s0, 101429; GFX8-NEXT: s_addc_u32 s1, s1, 01430; GFX8-NEXT: v_mov_b32_e32 v0, s01431; GFX8-NEXT: v_mov_b32_e32 v1, s11432; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[0:1]1433; GFX8-NEXT: s_endpgm1434;1435; GFX10-LABEL: s_bitselect_i64_pat_0:1436; GFX10: ; %bb.0:1437; GFX10-NEXT: s_clause 0x11438; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241439; GFX10-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x341440; GFX10-NEXT: s_waitcnt lgkmcnt(0)1441; GFX10-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5]1442; GFX10-NEXT: s_and_b64 s[0:1], s[2:3], s[0:1]1443; GFX10-NEXT: s_xor_b64 s[0:1], s[0:1], s[4:5]1444; GFX10-NEXT: s_add_u32 s0, s0, 101445; GFX10-NEXT: s_addc_u32 s1, s1, 01446; GFX10-NEXT: v_mov_b32_e32 v0, s01447; GFX10-NEXT: v_mov_b32_e32 v1, s11448; GFX10-NEXT: global_store_dwordx2 v[0:1], v[0:1], off1449; GFX10-NEXT: s_endpgm1450;1451; GFX8-GISEL-LABEL: s_bitselect_i64_pat_0:1452; GFX8-GISEL: ; %bb.0:1453; GFX8-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241454; GFX8-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x341455; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)1456; GFX8-GISEL-NEXT: s_and_b64 s[2:3], s[0:1], s[2:3]1457; GFX8-GISEL-NEXT: s_andn2_b64 s[0:1], s[4:5], s[0:1]1458; GFX8-GISEL-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1]1459; GFX8-GISEL-NEXT: s_add_u32 s0, s0, 101460; GFX8-GISEL-NEXT: s_addc_u32 s1, s1, 01461; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, s01462; GFX8-GISEL-NEXT: v_mov_b32_e32 v1, s11463; GFX8-GISEL-NEXT: flat_store_dwordx2 v[0:1], v[0:1]1464; GFX8-GISEL-NEXT: s_endpgm1465;1466; GFX10-GISEL-LABEL: s_bitselect_i64_pat_0:1467; GFX10-GISEL: ; %bb.0:1468; GFX10-GISEL-NEXT: s_clause 0x11469; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241470; GFX10-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x341471; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)1472; GFX10-GISEL-NEXT: s_and_b64 s[2:3], s[0:1], s[2:3]1473; GFX10-GISEL-NEXT: s_andn2_b64 s[0:1], s[4:5], s[0:1]1474; GFX10-GISEL-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1]1475; GFX10-GISEL-NEXT: s_add_u32 s0, s0, 101476; GFX10-GISEL-NEXT: s_addc_u32 s1, s1, 01477; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s01478; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s11479; GFX10-GISEL-NEXT: global_store_dwordx2 v[0:1], v[0:1], off1480; GFX10-GISEL-NEXT: s_endpgm1481 %and0 = and i64 %a, %b1482 %not.a = xor i64 %a, -11483 %and1 = and i64 %not.a, %mask1484 %bitselect = or i64 %and0, %and11485 %scalar.use = add i64 %bitselect, 101486 store i64 %scalar.use, ptr addrspace(1) poison1487 ret void1488}1489 1490define amdgpu_kernel void @s_bitselect_i64_pat_1(i64 %a, i64 %b, i64 %mask) {1491; GFX7-LABEL: s_bitselect_i64_pat_1:1492; GFX7: ; %bb.0:1493; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91494; GFX7-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd1495; GFX7-NEXT: s_mov_b32 s7, 0xf0001496; GFX7-NEXT: s_mov_b32 s6, -11497; GFX7-NEXT: s_waitcnt lgkmcnt(0)1498; GFX7-NEXT: s_xor_b64 s[0:1], s[0:1], s[4:5]1499; GFX7-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3]1500; GFX7-NEXT: s_xor_b64 s[0:1], s[0:1], s[4:5]1501; GFX7-NEXT: s_add_u32 s0, s0, 101502; GFX7-NEXT: s_addc_u32 s1, s1, 01503; GFX7-NEXT: v_mov_b32_e32 v0, s01504; GFX7-NEXT: v_mov_b32_e32 v1, s11505; GFX7-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 01506; GFX7-NEXT: s_endpgm1507;1508; GFX8-LABEL: s_bitselect_i64_pat_1:1509; GFX8: ; %bb.0:1510; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241511; GFX8-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x341512; GFX8-NEXT: s_waitcnt lgkmcnt(0)1513; GFX8-NEXT: s_xor_b64 s[0:1], s[0:1], s[4:5]1514; GFX8-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3]1515; GFX8-NEXT: s_xor_b64 s[0:1], s[0:1], s[4:5]1516; GFX8-NEXT: s_add_u32 s0, s0, 101517; GFX8-NEXT: s_addc_u32 s1, s1, 01518; GFX8-NEXT: v_mov_b32_e32 v0, s01519; GFX8-NEXT: v_mov_b32_e32 v1, s11520; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[0:1]1521; GFX8-NEXT: s_endpgm1522;1523; GFX10-LABEL: s_bitselect_i64_pat_1:1524; GFX10: ; %bb.0:1525; GFX10-NEXT: s_clause 0x11526; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241527; GFX10-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x341528; GFX10-NEXT: s_waitcnt lgkmcnt(0)1529; GFX10-NEXT: s_xor_b64 s[0:1], s[0:1], s[4:5]1530; GFX10-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3]1531; GFX10-NEXT: s_xor_b64 s[0:1], s[0:1], s[4:5]1532; GFX10-NEXT: s_add_u32 s0, s0, 101533; GFX10-NEXT: s_addc_u32 s1, s1, 01534; GFX10-NEXT: v_mov_b32_e32 v0, s01535; GFX10-NEXT: v_mov_b32_e32 v1, s11536; GFX10-NEXT: global_store_dwordx2 v[0:1], v[0:1], off1537; GFX10-NEXT: s_endpgm1538;1539; GFX8-GISEL-LABEL: s_bitselect_i64_pat_1:1540; GFX8-GISEL: ; %bb.0:1541; GFX8-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241542; GFX8-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x341543; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)1544; GFX8-GISEL-NEXT: s_xor_b64 s[0:1], s[0:1], s[4:5]1545; GFX8-GISEL-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3]1546; GFX8-GISEL-NEXT: s_xor_b64 s[0:1], s[0:1], s[4:5]1547; GFX8-GISEL-NEXT: s_add_u32 s0, s0, 101548; GFX8-GISEL-NEXT: s_addc_u32 s1, s1, 01549; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, s01550; GFX8-GISEL-NEXT: v_mov_b32_e32 v1, s11551; GFX8-GISEL-NEXT: flat_store_dwordx2 v[0:1], v[0:1]1552; GFX8-GISEL-NEXT: s_endpgm1553;1554; GFX10-GISEL-LABEL: s_bitselect_i64_pat_1:1555; GFX10-GISEL: ; %bb.0:1556; GFX10-GISEL-NEXT: s_clause 0x11557; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241558; GFX10-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x341559; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)1560; GFX10-GISEL-NEXT: s_xor_b64 s[0:1], s[0:1], s[4:5]1561; GFX10-GISEL-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3]1562; GFX10-GISEL-NEXT: s_xor_b64 s[0:1], s[0:1], s[4:5]1563; GFX10-GISEL-NEXT: s_add_u32 s0, s0, 101564; GFX10-GISEL-NEXT: s_addc_u32 s1, s1, 01565; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s01566; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s11567; GFX10-GISEL-NEXT: global_store_dwordx2 v[0:1], v[0:1], off1568; GFX10-GISEL-NEXT: s_endpgm1569 %xor.0 = xor i64 %a, %mask1570 %and = and i64 %xor.0, %b1571 %bitselect = xor i64 %and, %mask1572 1573 %scalar.use = add i64 %bitselect, 101574 store i64 %scalar.use, ptr addrspace(1) poison1575 ret void1576}1577 1578define amdgpu_kernel void @s_bitselect_i64_pat_2(i64 %a, i64 %b, i64 %mask) {1579; GFX7-LABEL: s_bitselect_i64_pat_2:1580; GFX7: ; %bb.0:1581; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91582; GFX7-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd1583; GFX7-NEXT: s_mov_b32 s7, 0xf0001584; GFX7-NEXT: s_mov_b32 s6, -11585; GFX7-NEXT: s_waitcnt lgkmcnt(0)1586; GFX7-NEXT: s_xor_b64 s[0:1], s[0:1], s[4:5]1587; GFX7-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3]1588; GFX7-NEXT: s_xor_b64 s[0:1], s[0:1], s[4:5]1589; GFX7-NEXT: s_add_u32 s0, s0, 101590; GFX7-NEXT: s_addc_u32 s1, s1, 01591; GFX7-NEXT: v_mov_b32_e32 v0, s01592; GFX7-NEXT: v_mov_b32_e32 v1, s11593; GFX7-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 01594; GFX7-NEXT: s_endpgm1595;1596; GFX8-LABEL: s_bitselect_i64_pat_2:1597; GFX8: ; %bb.0:1598; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241599; GFX8-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x341600; GFX8-NEXT: s_waitcnt lgkmcnt(0)1601; GFX8-NEXT: s_xor_b64 s[0:1], s[0:1], s[4:5]1602; GFX8-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3]1603; GFX8-NEXT: s_xor_b64 s[0:1], s[0:1], s[4:5]1604; GFX8-NEXT: s_add_u32 s0, s0, 101605; GFX8-NEXT: s_addc_u32 s1, s1, 01606; GFX8-NEXT: v_mov_b32_e32 v0, s01607; GFX8-NEXT: v_mov_b32_e32 v1, s11608; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[0:1]1609; GFX8-NEXT: s_endpgm1610;1611; GFX10-LABEL: s_bitselect_i64_pat_2:1612; GFX10: ; %bb.0:1613; GFX10-NEXT: s_clause 0x11614; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241615; GFX10-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x341616; GFX10-NEXT: s_waitcnt lgkmcnt(0)1617; GFX10-NEXT: s_xor_b64 s[0:1], s[0:1], s[4:5]1618; GFX10-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3]1619; GFX10-NEXT: s_xor_b64 s[0:1], s[0:1], s[4:5]1620; GFX10-NEXT: s_add_u32 s0, s0, 101621; GFX10-NEXT: s_addc_u32 s1, s1, 01622; GFX10-NEXT: v_mov_b32_e32 v0, s01623; GFX10-NEXT: v_mov_b32_e32 v1, s11624; GFX10-NEXT: global_store_dwordx2 v[0:1], v[0:1], off1625; GFX10-NEXT: s_endpgm1626;1627; GFX8-GISEL-LABEL: s_bitselect_i64_pat_2:1628; GFX8-GISEL: ; %bb.0:1629; GFX8-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241630; GFX8-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x341631; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)1632; GFX8-GISEL-NEXT: s_xor_b64 s[0:1], s[0:1], s[4:5]1633; GFX8-GISEL-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3]1634; GFX8-GISEL-NEXT: s_xor_b64 s[0:1], s[0:1], s[4:5]1635; GFX8-GISEL-NEXT: s_add_u32 s0, s0, 101636; GFX8-GISEL-NEXT: s_addc_u32 s1, s1, 01637; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, s01638; GFX8-GISEL-NEXT: v_mov_b32_e32 v1, s11639; GFX8-GISEL-NEXT: flat_store_dwordx2 v[0:1], v[0:1]1640; GFX8-GISEL-NEXT: s_endpgm1641;1642; GFX10-GISEL-LABEL: s_bitselect_i64_pat_2:1643; GFX10-GISEL: ; %bb.0:1644; GFX10-GISEL-NEXT: s_clause 0x11645; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241646; GFX10-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x341647; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)1648; GFX10-GISEL-NEXT: s_xor_b64 s[0:1], s[0:1], s[4:5]1649; GFX10-GISEL-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3]1650; GFX10-GISEL-NEXT: s_xor_b64 s[0:1], s[0:1], s[4:5]1651; GFX10-GISEL-NEXT: s_add_u32 s0, s0, 101652; GFX10-GISEL-NEXT: s_addc_u32 s1, s1, 01653; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s01654; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s11655; GFX10-GISEL-NEXT: global_store_dwordx2 v[0:1], v[0:1], off1656; GFX10-GISEL-NEXT: s_endpgm1657 %xor.0 = xor i64 %a, %mask1658 %and = and i64 %xor.0, %b1659 %bitselect = xor i64 %and, %mask1660 1661 %scalar.use = add i64 %bitselect, 101662 store i64 %scalar.use, ptr addrspace(1) poison1663 ret void1664}1665 1666define amdgpu_kernel void @s_bfi_sha256_ma_i64(i64 %x, i64 %y, i64 %z) {1667; GFX7-LABEL: s_bfi_sha256_ma_i64:1668; GFX7: ; %bb.0: ; %entry1669; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91670; GFX7-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd1671; GFX7-NEXT: s_mov_b32 s7, 0xf0001672; GFX7-NEXT: s_mov_b32 s6, -11673; GFX7-NEXT: s_waitcnt lgkmcnt(0)1674; GFX7-NEXT: s_and_b64 s[8:9], s[0:1], s[4:5]1675; GFX7-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5]1676; GFX7-NEXT: s_and_b64 s[0:1], s[2:3], s[0:1]1677; GFX7-NEXT: s_or_b64 s[0:1], s[8:9], s[0:1]1678; GFX7-NEXT: s_add_u32 s0, s0, 101679; GFX7-NEXT: s_addc_u32 s1, s1, 01680; GFX7-NEXT: v_mov_b32_e32 v0, s01681; GFX7-NEXT: v_mov_b32_e32 v1, s11682; GFX7-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 01683; GFX7-NEXT: s_endpgm1684;1685; GFX8-LABEL: s_bfi_sha256_ma_i64:1686; GFX8: ; %bb.0: ; %entry1687; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241688; GFX8-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x341689; GFX8-NEXT: s_waitcnt lgkmcnt(0)1690; GFX8-NEXT: s_and_b64 s[6:7], s[0:1], s[4:5]1691; GFX8-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5]1692; GFX8-NEXT: s_and_b64 s[0:1], s[2:3], s[0:1]1693; GFX8-NEXT: s_or_b64 s[0:1], s[6:7], s[0:1]1694; GFX8-NEXT: s_add_u32 s0, s0, 101695; GFX8-NEXT: s_addc_u32 s1, s1, 01696; GFX8-NEXT: v_mov_b32_e32 v0, s01697; GFX8-NEXT: v_mov_b32_e32 v1, s11698; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[0:1]1699; GFX8-NEXT: s_endpgm1700;1701; GFX10-LABEL: s_bfi_sha256_ma_i64:1702; GFX10: ; %bb.0: ; %entry1703; GFX10-NEXT: s_clause 0x11704; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241705; GFX10-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x341706; GFX10-NEXT: s_waitcnt lgkmcnt(0)1707; GFX10-NEXT: s_or_b64 s[6:7], s[0:1], s[4:5]1708; GFX10-NEXT: s_and_b64 s[0:1], s[0:1], s[4:5]1709; GFX10-NEXT: s_and_b64 s[2:3], s[2:3], s[6:7]1710; GFX10-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]1711; GFX10-NEXT: s_add_u32 s0, s0, 101712; GFX10-NEXT: s_addc_u32 s1, s1, 01713; GFX10-NEXT: v_mov_b32_e32 v0, s01714; GFX10-NEXT: v_mov_b32_e32 v1, s11715; GFX10-NEXT: global_store_dwordx2 v[0:1], v[0:1], off1716; GFX10-NEXT: s_endpgm1717;1718; GFX8-GISEL-LABEL: s_bfi_sha256_ma_i64:1719; GFX8-GISEL: ; %bb.0: ; %entry1720; GFX8-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241721; GFX8-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x341722; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)1723; GFX8-GISEL-NEXT: s_and_b64 s[6:7], s[0:1], s[4:5]1724; GFX8-GISEL-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5]1725; GFX8-GISEL-NEXT: s_and_b64 s[0:1], s[2:3], s[0:1]1726; GFX8-GISEL-NEXT: s_or_b64 s[0:1], s[6:7], s[0:1]1727; GFX8-GISEL-NEXT: s_add_u32 s0, s0, 101728; GFX8-GISEL-NEXT: s_addc_u32 s1, s1, 01729; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, s01730; GFX8-GISEL-NEXT: v_mov_b32_e32 v1, s11731; GFX8-GISEL-NEXT: flat_store_dwordx2 v[0:1], v[0:1]1732; GFX8-GISEL-NEXT: s_endpgm1733;1734; GFX10-GISEL-LABEL: s_bfi_sha256_ma_i64:1735; GFX10-GISEL: ; %bb.0: ; %entry1736; GFX10-GISEL-NEXT: s_clause 0x11737; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241738; GFX10-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x341739; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)1740; GFX10-GISEL-NEXT: s_or_b64 s[6:7], s[0:1], s[4:5]1741; GFX10-GISEL-NEXT: s_and_b64 s[0:1], s[0:1], s[4:5]1742; GFX10-GISEL-NEXT: s_and_b64 s[2:3], s[2:3], s[6:7]1743; GFX10-GISEL-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]1744; GFX10-GISEL-NEXT: s_add_u32 s0, s0, 101745; GFX10-GISEL-NEXT: s_addc_u32 s1, s1, 01746; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s01747; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s11748; GFX10-GISEL-NEXT: global_store_dwordx2 v[0:1], v[0:1], off1749; GFX10-GISEL-NEXT: s_endpgm1750entry:1751 %and0 = and i64 %x, %z1752 %or0 = or i64 %x, %z1753 %and1 = and i64 %y, %or01754 %or1 = or i64 %and0, %and11755 1756 %scalar.use = add i64 %or1, 101757 store i64 %scalar.use, ptr addrspace(1) poison1758 ret void1759}1760