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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn < %s | FileCheck -enable-var-scope -check-prefix=GCN %s3 4define float @v_bfi_single_nesting_level(float %x, float %y, float %z) {5; GCN-LABEL: v_bfi_single_nesting_level:6; GCN: ; %bb.0: ; %.entry7; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8; GCN-NEXT: v_mul_f32_e32 v2, 0x447fc000, v29; GCN-NEXT: v_cvt_u32_f32_e32 v1, v110; GCN-NEXT: v_mul_f32_e32 v0, 0x447fc000, v011; GCN-NEXT: v_cvt_u32_f32_e32 v2, v212; GCN-NEXT: v_lshlrev_b32_e32 v1, 10, v113; GCN-NEXT: v_cvt_u32_f32_e32 v0, v014; GCN-NEXT: v_and_b32_e32 v1, 0xffc00, v115; GCN-NEXT: v_and_b32_e32 v2, 0xc00003ff, v216; GCN-NEXT: v_lshlrev_b32_e32 v0, 20, v017; GCN-NEXT: v_or_b32_e32 v1, v1, v218; GCN-NEXT: v_and_b32_e32 v0, 0x3ff00000, v019; GCN-NEXT: v_or_b32_e32 v0, v1, v020; GCN-NEXT: s_setpc_b64 s[30:31]21.entry:22 %mul.base = fmul reassoc nnan nsz arcp contract afn float %z, 1.023000e+0323 %mul.base.i32 = fptoui float %mul.base to i3224 %y.i32 = fptoui float %y to i3225 %shl.inner.insert = shl i32 %y.i32, 1026 %bfi1.and = and i32 %shl.inner.insert, 104755227 %bfi1.andnot = and i32 %mul.base.i32, -107374080128 %bfi1.or = or i32 %bfi1.and, %bfi1.andnot29 %mul.outer.insert = fmul reassoc nnan nsz arcp contract afn float %x, 1.023000e+0330 %mul.outer.insert.i32 = fptoui float %mul.outer.insert to i3231 %shl.outer.insert = shl i32 %mul.outer.insert.i32, 2032 %and.outer = and i32 %shl.outer.insert, 107269324833 %or.outer = or i32 %bfi1.or, %and.outer34 %result = bitcast i32 %or.outer to float35 ret float %result36}37 38define float @v_bfi_single_nesting_level_swapped_operands(float %x, float %y, float %z) {39; GCN-LABEL: v_bfi_single_nesting_level_swapped_operands:40; GCN: ; %bb.0: ; %.entry41; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)42; GCN-NEXT: v_mul_f32_e32 v2, 0x447fc000, v243; GCN-NEXT: v_cvt_u32_f32_e32 v1, v144; GCN-NEXT: v_mul_f32_e32 v0, 0x447fc000, v045; GCN-NEXT: v_cvt_u32_f32_e32 v2, v246; GCN-NEXT: v_lshlrev_b32_e32 v1, 10, v147; GCN-NEXT: v_cvt_u32_f32_e32 v0, v048; GCN-NEXT: v_and_b32_e32 v1, 0xffc00, v149; GCN-NEXT: v_and_b32_e32 v2, 0xc00003ff, v250; GCN-NEXT: v_lshlrev_b32_e32 v0, 20, v051; GCN-NEXT: v_or_b32_e32 v1, v1, v252; GCN-NEXT: v_and_b32_e32 v0, 0x3ff00000, v053; GCN-NEXT: v_or_b32_e32 v0, v0, v154; GCN-NEXT: s_setpc_b64 s[30:31]55.entry:56 %mul.base = fmul reassoc nnan nsz arcp contract afn float %z, 1.023000e+0357 %mul.base.i32 = fptoui float %mul.base to i3258 %y.i32 = fptoui float %y to i3259 %shl.inner.insert = shl i32 %y.i32, 1060 %bfi1.and = and i32 1047552, %shl.inner.insert61 %bfi1.andnot = and i32 -1073740801, %mul.base.i3262 %bfi1.or = or i32 %bfi1.and, %bfi1.andnot63 %mul.outer.insert = fmul reassoc nnan nsz arcp contract afn float %x, 1.023000e+0364 %mul.outer.insert.i32 = fptoui float %mul.outer.insert to i3265 %shl.outer.insert = shl i32 %mul.outer.insert.i32, 2066 %and.outer = and i32 %shl.outer.insert, 107269324867 %or.outer = or i32 %and.outer, %bfi1.or68 %result = bitcast i32 %or.outer to float69 ret float %result70}71 72define float @v_bfi_single_nesting_level_unbalanced_subtree(float %x, float %y, float %z) {73; GCN-LABEL: v_bfi_single_nesting_level_unbalanced_subtree:74; GCN: ; %bb.0: ; %.entry75; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)76; GCN-NEXT: v_mul_f32_e32 v2, 0x447fc000, v277; GCN-NEXT: v_cvt_u32_f32_e32 v1, v178; GCN-NEXT: v_mul_f32_e32 v0, 0x447fc000, v079; GCN-NEXT: v_cvt_u32_f32_e32 v2, v280; GCN-NEXT: v_lshlrev_b32_e32 v1, 10, v181; GCN-NEXT: v_cvt_u32_f32_e32 v0, v082; GCN-NEXT: v_and_b32_e32 v1, 0xffc00, v183; GCN-NEXT: v_and_b32_e32 v3, 0x3e0, v284; GCN-NEXT: v_lshlrev_b32_e32 v0, 20, v085; GCN-NEXT: v_or_b32_e32 v1, v1, v386; GCN-NEXT: v_and_b32_e32 v0, 0x3ff00000, v087; GCN-NEXT: v_and_b32_e32 v2, 0xc000001f, v288; GCN-NEXT: v_or_b32_e32 v1, v2, v189; GCN-NEXT: v_or_b32_e32 v0, v0, v190; GCN-NEXT: s_setpc_b64 s[30:31]91.entry:92 %mul.base = fmul reassoc nnan nsz arcp contract afn float %z, 1.023000e+0393 %mul.base.i32 = fptoui float %mul.base to i3294 %y.i32 = fptoui float %y to i3295 %shl.inner.2.insert = shl i32 %y.i32, 1096 %bfi.inner.2.and.1 = and i32 %shl.inner.2.insert, 104755297 %bfi.inner.2.and.2 = and i32 %mul.base.i32, 99298 %bfi.inner.2 = or i32 %bfi.inner.2.and.1, %bfi.inner.2.and.299 %mul.inner.1.insert = fmul reassoc nnan nsz arcp contract afn float %x, 1.023000e+03100 %mul.inner.1.insert.1.i32 = fptoui float %mul.inner.1.insert to i32101 %shl.inner.1.insert.1 = shl i32 %mul.inner.1.insert.1.i32, 20102 %bfi.inner.1.and.1 = and i32 %shl.inner.1.insert.1, 1072693248103 %bfi.inner.1.and.2 = and i32 %mul.base.i32, -1073741793104 %bfi.inner.1 = or i32 %bfi.inner.1.and.2, %bfi.inner.2105 %bfi.outer = or i32 %bfi.inner.1.and.1, %bfi.inner.1106 %result = bitcast i32 %bfi.outer to float107 ret float %result108}109 110define float @v_bfi_single_nesting_level_inner_use(float %x, float %y, float %z) {111; GCN-LABEL: v_bfi_single_nesting_level_inner_use:112; GCN: ; %bb.0: ; %.entry113; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)114; GCN-NEXT: v_mul_f32_e32 v0, 0x447fc000, v2115; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1116; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0117; GCN-NEXT: v_lshlrev_b32_e32 v1, 10, v1118; GCN-NEXT: v_and_b32_e32 v1, 0xffc00, v1119; GCN-NEXT: v_and_b32_e32 v0, 0x400003ff, v0120; GCN-NEXT: v_or_b32_e32 v0, v1, v0121; GCN-NEXT: v_lshlrev_b32_e32 v0, 1, v0122; GCN-NEXT: s_setpc_b64 s[30:31]123.entry:124 %mul.base = fmul reassoc nnan nsz arcp contract afn float %z, 1.023000e+03125 %mul.base.i32 = fptoui float %mul.base to i32126 %y.i32 = fptoui float %y to i32127 %shl.inner.insert = shl i32 %y.i32, 10128 %bfi1.and = and i32 %shl.inner.insert, 1047552129 %bfi1.andnot = and i32 %mul.base.i32, -1073740801130 %bfi1.or = or i32 %bfi1.and, %bfi1.andnot131 %mul.outer.insert = fmul reassoc nnan nsz arcp contract afn float %x, 1.023000e+03132 %mul.outer.insert.i32 = fptoui float %mul.outer.insert to i32133 %shl.outer.insert = shl i32 %mul.outer.insert.i32, 20134 %and.outer = and i32 %shl.outer.insert, 1072693248135 %or.outer = or i32 %bfi1.or, %and.outer136 %bfi1.or.seconduse = mul i32 %bfi1.or, 2137 %result = bitcast i32 %bfi1.or.seconduse to float138 ret float %result139}140 141define float @v_bfi_no_nesting(float %x, float %y, float %z) {142; GCN-LABEL: v_bfi_no_nesting:143; GCN: ; %bb.0: ; %.entry144; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)145; GCN-NEXT: v_mul_f32_e32 v2, 0x447fc000, v2146; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1147; GCN-NEXT: v_mul_f32_e32 v0, 0x447fc000, v0148; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2149; GCN-NEXT: v_lshlrev_b32_e32 v1, 10, v1150; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0151; GCN-NEXT: v_and_b32_e32 v1, 0xffc00, v1152; GCN-NEXT: v_and_b32_e32 v2, 0xc0000400, v2153; GCN-NEXT: v_lshlrev_b32_e32 v0, 20, v0154; GCN-NEXT: v_or_b32_e32 v1, v1, v2155; GCN-NEXT: v_and_b32_e32 v0, 0x3ff00000, v0156; GCN-NEXT: v_or_b32_e32 v0, v1, v0157; GCN-NEXT: s_setpc_b64 s[30:31]158.entry:159 %mul.base = fmul reassoc nnan nsz arcp contract afn float %z, 1.023000e+03160 %mul.base.i32 = fptoui float %mul.base to i32161 %y.i32 = fptoui float %y to i32162 %shl.inner.insert = shl i32 %y.i32, 10163 %inner.and = and i32 %shl.inner.insert, 1047552164 %inner.and2 = and i32 %mul.base.i32, -1073740800165 %inner.or = or i32 %inner.and, %inner.and2166 %mul.outer.insert = fmul reassoc nnan nsz arcp contract afn float %x, 1.023000e+03167 %mul.outer.insert.i32 = fptoui float %mul.outer.insert to i32168 %shl.outer.insert = shl i32 %mul.outer.insert.i32, 20169 %and.outer = and i32 %shl.outer.insert, 1072693248170 %or.outer = or i32 %inner.or, %and.outer171 %result = bitcast i32 %or.outer to float172 ret float %result173}174 175define float @v_bfi_two_levels(float %x, float %y, float %z) {176; GCN-LABEL: v_bfi_two_levels:177; GCN: ; %bb.0: ; %.entry178; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)179; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1180; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2181; GCN-NEXT: v_mul_f32_e32 v0, 0x447fc000, v0182; GCN-NEXT: v_lshlrev_b32_e32 v3, 5, v1183; GCN-NEXT: v_and_b32_e32 v2, 0xc000001f, v2184; GCN-NEXT: v_lshlrev_b32_e32 v1, 10, v1185; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0186; GCN-NEXT: v_and_b32_e32 v3, 0x3e0, v3187; GCN-NEXT: v_and_b32_e32 v1, 0xffc00, v1188; GCN-NEXT: v_lshlrev_b32_e32 v0, 20, v0189; GCN-NEXT: v_or_b32_e32 v2, v3, v2190; GCN-NEXT: v_or_b32_e32 v1, v2, v1191; GCN-NEXT: v_and_b32_e32 v0, 0x3ff00000, v0192; GCN-NEXT: v_or_b32_e32 v0, v1, v0193; GCN-NEXT: s_setpc_b64 s[30:31]194.entry:195 %y.i32 = fptoui float %y to i32196 %shl.insert.inner = shl i32 %y.i32, 5197 %and.insert.inner = and i32 %shl.insert.inner, 992198 %z.i32 = fptoui float %z to i32199 %base.inner = and i32 %z.i32, -1073741793200 %or.inner = or i32 %and.insert.inner , %base.inner201 %shl.insert.mid = shl i32 %y.i32, 10202 %and.insert.mid = and i32 %shl.insert.mid, 1047552203 %or.mid = or i32 %or.inner, %and.insert.mid204 %fmul.insert.outer = fmul reassoc nnan nsz arcp contract afn float %x, 1.023000e+03205 %cast.insert.outer = fptoui float %fmul.insert.outer to i32206 %shl.insert.outer = shl i32 %cast.insert.outer, 20207 %and.insert.outer = and i32 %shl.insert.outer, 1072693248208 %or.outer = or i32 %or.mid, %and.insert.outer209 %result = bitcast i32 %or.outer to float210 ret float %result211}212 213define float @v_bfi_two_levels_inner_or_multiple_uses(float %x, float %y, float %z) {214; GCN-LABEL: v_bfi_two_levels_inner_or_multiple_uses:215; GCN: ; %bb.0: ; %.entry216; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)217; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1218; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2219; GCN-NEXT: v_mul_f32_e32 v0, 0x447fc000, v0220; GCN-NEXT: v_lshlrev_b32_e32 v3, 5, v1221; GCN-NEXT: v_and_b32_e32 v2, 0xc000001f, v2222; GCN-NEXT: v_lshlrev_b32_e32 v1, 10, v1223; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0224; GCN-NEXT: v_and_b32_e32 v3, 0x3e0, v3225; GCN-NEXT: v_and_b32_e32 v1, 0xffc00, v1226; GCN-NEXT: v_lshlrev_b32_e32 v0, 20, v0227; GCN-NEXT: v_or_b32_e32 v2, v3, v2228; GCN-NEXT: v_or_b32_e32 v1, v2, v1229; GCN-NEXT: v_and_b32_e32 v0, 0x3ff00000, v0230; GCN-NEXT: v_or_b32_e32 v0, v1, v0231; GCN-NEXT: v_mul_f32_e32 v0, v0, v2232; GCN-NEXT: s_setpc_b64 s[30:31]233.entry:234 %y.i32 = fptoui float %y to i32235 %shl.insert.inner = shl i32 %y.i32, 5236 %and.insert.inner = and i32 %shl.insert.inner, 992237 %z.i32 = fptoui float %z to i32238 %base.inner = and i32 %z.i32, -1073741793239 %or.inner = or i32 %and.insert.inner , %base.inner240 %shl.insert.mid = shl i32 %y.i32, 10241 %and.insert.mid = and i32 %shl.insert.mid, 1047552242 %or.mid = or i32 %or.inner, %and.insert.mid243 %fmul.insert.outer = fmul reassoc nnan nsz arcp contract afn float %x, 1.023000e+03244 %cast.insert.outer = fptoui float %fmul.insert.outer to i32245 %shl.insert.outer = shl i32 %cast.insert.outer, 20246 %and.insert.outer = and i32 %shl.insert.outer, 1072693248247 %or.outer = or i32 %or.mid, %and.insert.outer248 %result = bitcast i32 %or.outer to float249 %or.inner.float = bitcast i32 %or.inner to float250 %result2 = fmul float %result, %or.inner.float251 ret float %result2252}253 254define float @v_bfi_single_constant_as_partition(float %x, float %y, float %z) {255; GCN-LABEL: v_bfi_single_constant_as_partition:256; GCN: ; %bb.0: ; %.entry257; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)258; GCN-NEXT: v_mul_f32_e32 v2, 0x447fc000, v2259; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1260; GCN-NEXT: v_mul_f32_e32 v0, 0x447fc000, v0261; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2262; GCN-NEXT: v_lshlrev_b32_e32 v1, 10, v1263; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0264; GCN-NEXT: v_or_b32_e32 v1, v1, v2265; GCN-NEXT: v_lshlrev_b32_e32 v0, 20, v0266; GCN-NEXT: v_or_b32_e32 v0, v1, v0267; GCN-NEXT: s_setpc_b64 s[30:31]268.entry:269 %mul.base = fmul reassoc nnan nsz arcp contract afn float %z, 1.023000e+03270 %mul.base.i32 = fptoui float %mul.base to i32271 %y.i32 = fptoui float %y to i32272 %shl.inner.insert = shl i32 %y.i32, 10273 %bfi1.or = or i32 %shl.inner.insert, %mul.base.i32274 %mul.outer.insert = fmul reassoc nnan nsz arcp contract afn float %x, 1.023000e+03275 %mul.outer.insert.i32 = fptoui float %mul.outer.insert to i32276 %shl.outer.insert = shl i32 %mul.outer.insert.i32, 20277 %and.outer = and i32 %shl.outer.insert, -1278 %or.outer = or i32 %bfi1.or, %and.outer279 %result = bitcast i32 %or.outer to float280 ret float %result281}282 283define amdgpu_kernel void @v_bfi_dont_applied_for_scalar_ops(ptr addrspace(1) %out, i16 %a, i32 %b) {284; GCN-LABEL: v_bfi_dont_applied_for_scalar_ops:285; GCN: ; %bb.0:286; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9287; GCN-NEXT: s_waitcnt lgkmcnt(0)288; GCN-NEXT: s_mov_b64 s[4:5], s[2:3]289; GCN-NEXT: s_mov_b32 s3, 0xf000290; GCN-NEXT: s_and_b32 s2, s5, 0xffff0000291; GCN-NEXT: s_and_b32 s4, s4, 0xffff292; GCN-NEXT: s_or_b32 s4, s4, s2293; GCN-NEXT: s_mov_b32 s2, -1294; GCN-NEXT: v_mov_b32_e32 v0, s4295; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0296; GCN-NEXT: s_endpgm297 %shift = lshr i32 %b, 16298 %tr = trunc i32 %shift to i16299 %tmp = insertelement <2 x i16> poison, i16 %a, i32 0300 %vec = insertelement <2 x i16> %tmp, i16 %tr, i32 1301 %val = bitcast <2 x i16> %vec to i32302 store i32 %val, ptr addrspace(1) %out, align 4303 ret void304}305