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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn < %s | FileCheck --check-prefix=SI %s3; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck --check-prefix=VI %s4 5define amdgpu_kernel void @s_bfm_pattern(ptr addrspace(1) %out, i32 %x, i32 %y) #0 {6; SI-LABEL: s_bfm_pattern:7; SI: ; %bb.0:8; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x99; SI-NEXT: s_waitcnt lgkmcnt(0)10; SI-NEXT: s_mov_b64 s[4:5], s[2:3]11; SI-NEXT: s_mov_b32 s3, 0xf00012; SI-NEXT: s_bfm_b32 s4, s4, s513; SI-NEXT: s_mov_b32 s2, -114; SI-NEXT: v_mov_b32_e32 v0, s415; SI-NEXT: buffer_store_dword v0, off, s[0:3], 016; SI-NEXT: s_endpgm17;18; VI-LABEL: s_bfm_pattern:19; VI: ; %bb.0:20; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2421; VI-NEXT: s_waitcnt lgkmcnt(0)22; VI-NEXT: s_bfm_b32 s2, s2, s323; VI-NEXT: v_mov_b32_e32 v0, s024; VI-NEXT: v_mov_b32_e32 v1, s125; VI-NEXT: v_mov_b32_e32 v2, s226; VI-NEXT: flat_store_dword v[0:1], v227; VI-NEXT: s_endpgm28 %a = shl i32 1, %x29 %b = sub i32 %a, 130 %c = shl i32 %b, %y31 store i32 %c, ptr addrspace(1) %out32 ret void33}34 35define amdgpu_kernel void @s_bfm_pattern_simple(ptr addrspace(1) %out, i32 %x) #0 {36; SI-LABEL: s_bfm_pattern_simple:37; SI: ; %bb.0:38; SI-NEXT: s_load_dword s2, s[4:5], 0xb39; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x940; SI-NEXT: s_mov_b32 s3, 0xf00041; SI-NEXT: s_waitcnt lgkmcnt(0)42; SI-NEXT: s_bfm_b32 s4, s2, 043; SI-NEXT: s_mov_b32 s2, -144; SI-NEXT: v_mov_b32_e32 v0, s445; SI-NEXT: buffer_store_dword v0, off, s[0:3], 046; SI-NEXT: s_endpgm47;48; VI-LABEL: s_bfm_pattern_simple:49; VI: ; %bb.0:50; VI-NEXT: s_load_dword s2, s[4:5], 0x2c51; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2452; VI-NEXT: s_waitcnt lgkmcnt(0)53; VI-NEXT: s_bfm_b32 s2, s2, 054; VI-NEXT: v_mov_b32_e32 v0, s055; VI-NEXT: v_mov_b32_e32 v1, s156; VI-NEXT: v_mov_b32_e32 v2, s257; VI-NEXT: flat_store_dword v[0:1], v258; VI-NEXT: s_endpgm59 %a = shl i32 1, %x60 %b = sub i32 %a, 161 store i32 %b, ptr addrspace(1) %out62 ret void63}64 65define void @v_bfm_pattern(ptr addrspace(1) %out, i32 %x, i32 %y) #0 {66; SI-LABEL: v_bfm_pattern:67; SI: ; %bb.0:68; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)69; SI-NEXT: s_mov_b32 s7, 0xf00070; SI-NEXT: s_mov_b32 s6, 071; SI-NEXT: v_bfm_b32_e32 v2, v2, v372; SI-NEXT: s_mov_b32 s4, s673; SI-NEXT: s_mov_b32 s5, s674; SI-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr6475; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)76; SI-NEXT: s_setpc_b64 s[30:31]77;78; VI-LABEL: v_bfm_pattern:79; VI: ; %bb.0:80; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)81; VI-NEXT: v_bfm_b32 v2, v2, v382; VI-NEXT: flat_store_dword v[0:1], v283; VI-NEXT: s_waitcnt vmcnt(0)84; VI-NEXT: s_setpc_b64 s[30:31]85 %a = shl i32 1, %x86 %b = sub i32 %a, 187 %c = shl i32 %b, %y88 store i32 %c, ptr addrspace(1) %out89 ret void90}91 92define void @v_bfm_pattern_simple(ptr addrspace(1) %out, i32 %x) #0 {93; SI-LABEL: v_bfm_pattern_simple:94; SI: ; %bb.0:95; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)96; SI-NEXT: s_mov_b32 s7, 0xf00097; SI-NEXT: s_mov_b32 s6, 098; SI-NEXT: v_bfm_b32_e64 v2, v2, 099; SI-NEXT: s_mov_b32 s4, s6100; SI-NEXT: s_mov_b32 s5, s6101; SI-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64102; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)103; SI-NEXT: s_setpc_b64 s[30:31]104;105; VI-LABEL: v_bfm_pattern_simple:106; VI: ; %bb.0:107; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)108; VI-NEXT: v_bfm_b32 v2, v2, 0109; VI-NEXT: flat_store_dword v[0:1], v2110; VI-NEXT: s_waitcnt vmcnt(0)111; VI-NEXT: s_setpc_b64 s[30:31]112 %a = shl i32 1, %x113 %b = sub i32 %a, 1114 store i32 %b, ptr addrspace(1) %out115 ret void116}117 118attributes #0 = { nounwind }119