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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck %s3 4; Check for situations where we could reduce the width of bitwise5; operations.6 7 8; Should be able to reduce this to a 32-bit or plus a copy9; https://alive2.llvm.org/ce/z/9LddFX10define i64 @v_xor_i64_known_hi_i32_from_arg_range(i64 range(i64 0, 4294967296) %arg0, i64 %arg1) {11; CHECK-LABEL: v_xor_i64_known_hi_i32_from_arg_range:12; CHECK: ; %bb.0:13; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14; CHECK-NEXT: v_xor_b32_e32 v1, v1, v315; CHECK-NEXT: v_xor_b32_e32 v0, v0, v216; CHECK-NEXT: s_setpc_b64 s[30:31]17 %xor = xor i64 %arg0, %arg118 ret i64 %xor19}20 21; Should be able to reduce this to a 32-bit or plus a copy22; https://alive2.llvm.org/ce/z/HaXnBJ23define i64 @v_or_i64_known_hi_i32_from_arg_range(i64 range(i64 0, 4294967296) %arg0, i64 %arg1) {24; CHECK-LABEL: v_or_i64_known_hi_i32_from_arg_range:25; CHECK: ; %bb.0:26; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)27; CHECK-NEXT: v_or_b32_e32 v1, v1, v328; CHECK-NEXT: v_or_b32_e32 v0, v0, v229; CHECK-NEXT: s_setpc_b64 s[30:31]30 %or = or i64 %arg0, %arg131 ret i64 %or32}33 34; https://alive2.llvm.org/ce/z/M96Ror35; Should be able to reduce this to a 32-bit plus a copy36define i64 @v_and_i64_known_i32_from_arg_range(i64 range(i64 -4294967296, 0) %arg0, i64 %arg1) {37; CHECK-LABEL: v_and_i64_known_i32_from_arg_range:38; CHECK: ; %bb.0:39; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)40; CHECK-NEXT: v_and_b32_e32 v1, v1, v341; CHECK-NEXT: v_and_b32_e32 v0, v0, v242; CHECK-NEXT: s_setpc_b64 s[30:31]43 %and = and i64 %arg0, %arg144 ret i64 %and45}46 47define i64 @s_xor_i64_known_i32_from_arg_range(i64 range(i64 0, 65) inreg %arg) {48; CHECK-LABEL: s_xor_i64_known_i32_from_arg_range:49; CHECK: ; %bb.0:50; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)51; CHECK-NEXT: s_not_b64 s[4:5], s[16:17]52; CHECK-NEXT: v_mov_b32_e32 v0, s453; CHECK-NEXT: v_mov_b32_e32 v1, s554; CHECK-NEXT: s_setpc_b64 s[30:31]55 %xor = xor i64 %arg, -156 ret i64 %xor57}58 59define i64 @v_xor_i64_known_i32_from_call_range() {60; CHECK-LABEL: v_xor_i64_known_i32_from_call_range:61; CHECK: ; %bb.0:62; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)63; CHECK-NEXT: ;;#ASMSTART64; CHECK-NEXT: ; def v[0:1]65; CHECK-NEXT: ;;#ASMEND66; CHECK-NEXT: v_not_b32_e32 v1, v167; CHECK-NEXT: v_not_b32_e32 v0, v068; CHECK-NEXT: s_setpc_b64 s[30:31]69 %call = call range(i64 0, 65) i64 asm "; def $0", "=v"()70 %xor = xor i64 %call, -171 ret i64 %xor72}73 74define i64 @s_xor_i64_known_i32_from_call_range() {75; CHECK-LABEL: s_xor_i64_known_i32_from_call_range:76; CHECK: ; %bb.0:77; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)78; CHECK-NEXT: ;;#ASMSTART79; CHECK-NEXT: ; def s[4:5]80; CHECK-NEXT: ;;#ASMEND81; CHECK-NEXT: s_not_b64 s[4:5], s[4:5]82; CHECK-NEXT: v_mov_b32_e32 v0, s483; CHECK-NEXT: v_mov_b32_e32 v1, s584; CHECK-NEXT: s_setpc_b64 s[30:31]85 %call = call range(i64 0, 65) i64 asm "; def $0", "=s"()86 %xor = xor i64 %call, -187 ret i64 %xor88}89 90; Reduced from -amdgpu-codegenprepare-expand-div64 output, produces a91; not of 0 which ideally would fold out.92; FIXME: Produces not of constant 093define i64 @v_xor_i64_known_i32_from_range_use_out_of_block(i64 %x) {94; CHECK-LABEL: v_xor_i64_known_i32_from_range_use_out_of_block:95; CHECK: ; %bb.0: ; %entry96; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)97; CHECK-NEXT: v_ffbh_u32_e32 v2, v098; CHECK-NEXT: v_add_u32_e32 v2, 32, v299; CHECK-NEXT: v_ffbh_u32_e32 v3, v1100; CHECK-NEXT: v_min_u32_e32 v4, v2, v3101; CHECK-NEXT: v_mov_b32_e32 v5, 0102; CHECK-NEXT: v_cmp_eq_u64_e32 vcc, v[4:5], v[0:1]103; CHECK-NEXT: v_mov_b32_e32 v2, 0104; CHECK-NEXT: v_mov_b32_e32 v3, 0105; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc106; CHECK-NEXT: ; %bb.1: ; %inc107; CHECK-NEXT: v_not_b32_e32 v2, v4108; CHECK-NEXT: v_add_co_u32_e32 v2, vcc, v0, v2109; CHECK-NEXT: v_addc_co_u32_e32 v3, vcc, -1, v1, vcc110; CHECK-NEXT: ; %bb.2: ; %UnifiedReturnBlock111; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]112; CHECK-NEXT: v_mov_b32_e32 v0, v2113; CHECK-NEXT: v_mov_b32_e32 v1, v3114; CHECK-NEXT: s_setpc_b64 s[30:31]115entry:116 %ctlz = tail call range(i64 0, 65) i64 @llvm.ctlz.i64(i64 %x, i1 true)117 %cmp.entry.not = icmp eq i64 %ctlz, %x118 br i1 %cmp.entry.not, label %inc, label %ret119 120inc: ; preds = %entry121 %i1 = xor i64 %ctlz, -1122 %i2 = add i64 %x, %i1123 ret i64 %i2124 125ret: ; preds = %loop, %entry126 ret i64 0127}128 129define i64 @s_xor_i64_known_i32_from_range_use_out_of_block(i64 inreg %x) {130; CHECK-LABEL: s_xor_i64_known_i32_from_range_use_out_of_block:131; CHECK: ; %bb.0: ; %entry132; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)133; CHECK-NEXT: s_flbit_i32_b64 s4, s[16:17]134; CHECK-NEXT: s_mov_b32 s5, 0135; CHECK-NEXT: s_cmp_lg_u64 s[4:5], s[16:17]136; CHECK-NEXT: s_cbranch_scc1 .LBB7_2137; CHECK-NEXT: ; %bb.1: ; %inc138; CHECK-NEXT: s_not_b64 s[4:5], s[4:5]139; CHECK-NEXT: s_add_u32 s4, s16, s4140; CHECK-NEXT: s_addc_u32 s5, s17, s5141; CHECK-NEXT: v_mov_b32_e32 v0, s4142; CHECK-NEXT: v_mov_b32_e32 v1, s5143; CHECK-NEXT: s_setpc_b64 s[30:31]144; CHECK-NEXT: .LBB7_2: ; %ret145; CHECK-NEXT: v_mov_b32_e32 v0, 0146; CHECK-NEXT: v_mov_b32_e32 v1, 0147; CHECK-NEXT: s_setpc_b64 s[30:31]148entry:149 %ctlz = tail call range(i64 0, 65) i64 @llvm.ctlz.i64(i64 %x, i1 true)150 %cmp.entry.not = icmp eq i64 %ctlz, %x151 br i1 %cmp.entry.not, label %inc, label %ret152 153inc: ; preds = %entry154 %i1 = xor i64 %ctlz, -1155 %i2 = add i64 %x, %i1156 ret i64 %i2157 158ret: ; preds = %loop, %entry159 ret i64 0160}161 162