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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel=0 -mtriple=amdgcn-- -mcpu=gfx950 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX950,GFX950-SDAG %s3; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-- -mcpu=gfx950 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX950,GFX950-GISEL %s4; RUN: llc -global-isel=0 -mtriple=amdgcn-- -mcpu=gfx1250 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX1250,GFX1250-SDAG,GFX1250-SDAG-FAKE16,GFX1250-FAKE16 %s5; RUN: llc -global-isel=0 -mtriple=amdgcn-- -mcpu=gfx1250 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX1250,GFX1250-SDAG,GFX1250-SDAG-TRUE16,GFX1250-TRUE16 %s6; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-- -mcpu=gfx1250 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX1250,GFX1250-GISEL,GFX1250-GISEL-FAKE16,GFX1250-FAKE16 %s7; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-- -mcpu=gfx1250 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX1250,GFX1250-GISEL,GFX1250-GISEL-TRUE16,GFX1250-TRUE16 %s8 9; ========= Single bit functions =========10 11define amdgpu_ps float @not_and_not_and_not_and(i32 %a, i32 %b, i32 %c) {12; GFX950-LABEL: not_and_not_and_not_and:13; GFX950: ; %bb.0:14; GFX950-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:115; GFX950-NEXT: ; return to shader part epilog16;17; GFX1250-LABEL: not_and_not_and_not_and:18; GFX1250: ; %bb.0:19; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 120; GFX1250-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:121; GFX1250-NEXT: ; return to shader part epilog22 %nota = xor i32 %a, -123 %notb = xor i32 %b, -124 %notc = xor i32 %c, -125 %and1 = and i32 %nota, %notc26 %and2 = and i32 %and1, %notb27 %ret_cast = bitcast i32 %and2 to float28 ret float %ret_cast29}30 31define amdgpu_ps float @not_and_not_and_and(i32 %a, i32 %b, i32 %c) {32; GFX950-LABEL: not_and_not_and_and:33; GFX950: ; %bb.0:34; GFX950-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:235; GFX950-NEXT: ; return to shader part epilog36;37; GFX1250-LABEL: not_and_not_and_and:38; GFX1250: ; %bb.0:39; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 140; GFX1250-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:241; GFX1250-NEXT: ; return to shader part epilog42 %nota = xor i32 %a, -143 %notb = xor i32 %b, -144 %and1 = and i32 %nota, %c45 %and2 = and i32 %and1, %notb46 %ret_cast = bitcast i32 %and2 to float47 ret float %ret_cast48}49 50define amdgpu_ps float @not_and_and_not_and(i32 %a, i32 %b, i32 %c) {51; GFX950-LABEL: not_and_and_not_and:52; GFX950: ; %bb.0:53; GFX950-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:454; GFX950-NEXT: ; return to shader part epilog55;56; GFX1250-LABEL: not_and_and_not_and:57; GFX1250: ; %bb.0:58; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 159; GFX1250-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:460; GFX1250-NEXT: ; return to shader part epilog61 %nota = xor i32 %a, -162 %notc = xor i32 %c, -163 %and1 = and i32 %nota, %notc64 %and2 = and i32 %and1, %b65 %ret_cast = bitcast i32 %and2 to float66 ret float %ret_cast67}68 69define amdgpu_ps float @not_and_and_and(i32 %a, i32 %b, i32 %c) {70; GFX950-SDAG-LABEL: not_and_and_and:71; GFX950-SDAG: ; %bb.0:72; GFX950-SDAG-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:873; GFX950-SDAG-NEXT: ; return to shader part epilog74;75; GFX950-GISEL-LABEL: not_and_and_and:76; GFX950-GISEL: ; %bb.0:77; GFX950-GISEL-NEXT: v_bitop3_b32 v0, v0, v2, v0 bitop3:0xc78; GFX950-GISEL-NEXT: v_and_b32_e32 v0, v0, v179; GFX950-GISEL-NEXT: ; return to shader part epilog80;81; GFX1250-SDAG-LABEL: not_and_and_and:82; GFX1250-SDAG: ; %bb.0:83; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 184; GFX1250-SDAG-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:885; GFX1250-SDAG-NEXT: ; return to shader part epilog86;87; GFX1250-GISEL-LABEL: not_and_and_and:88; GFX1250-GISEL: ; %bb.0:89; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 190; GFX1250-GISEL-NEXT: v_bitop3_b32 v0, v0, v2, v0 bitop3:0xc91; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)92; GFX1250-GISEL-NEXT: v_and_b32_e32 v0, v0, v193; GFX1250-GISEL-NEXT: ; return to shader part epilog94 %nota = xor i32 %a, -195 %and1 = and i32 %nota, %c96 %and2 = and i32 %and1, %b97 %ret_cast = bitcast i32 %and2 to float98 ret float %ret_cast99}100 101define amdgpu_ps float @and_not_and_not_and(i32 %a, i32 %b, i32 %c) {102; GFX950-LABEL: and_not_and_not_and:103; GFX950: ; %bb.0:104; GFX950-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:0x10105; GFX950-NEXT: ; return to shader part epilog106;107; GFX1250-LABEL: and_not_and_not_and:108; GFX1250: ; %bb.0:109; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1110; GFX1250-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:0x10111; GFX1250-NEXT: ; return to shader part epilog112 %notb = xor i32 %b, -1113 %notc = xor i32 %c, -1114 %and1 = and i32 %a, %notc115 %and2 = and i32 %and1, %notb116 %ret_cast = bitcast i32 %and2 to float117 ret float %ret_cast118}119 120define amdgpu_ps float @and_not_and_and(i32 %a, i32 %b, i32 %c) {121; GFX950-SDAG-LABEL: and_not_and_and:122; GFX950-SDAG: ; %bb.0:123; GFX950-SDAG-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:0x20124; GFX950-SDAG-NEXT: ; return to shader part epilog125;126; GFX950-GISEL-LABEL: and_not_and_and:127; GFX950-GISEL: ; %bb.0:128; GFX950-GISEL-NEXT: v_and_b32_e32 v0, v0, v2129; GFX950-GISEL-NEXT: v_bfi_b32 v0, v1, 0, v0130; GFX950-GISEL-NEXT: ; return to shader part epilog131;132; GFX1250-SDAG-LABEL: and_not_and_and:133; GFX1250-SDAG: ; %bb.0:134; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1135; GFX1250-SDAG-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:0x20136; GFX1250-SDAG-NEXT: ; return to shader part epilog137;138; GFX1250-GISEL-LABEL: and_not_and_and:139; GFX1250-GISEL: ; %bb.0:140; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1141; GFX1250-GISEL-NEXT: v_and_b32_e32 v0, v0, v2142; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)143; GFX1250-GISEL-NEXT: v_bfi_b32 v0, v1, 0, v0144; GFX1250-GISEL-NEXT: ; return to shader part epilog145 %notb = xor i32 %b, -1146 %and1 = and i32 %a, %c147 %and2 = and i32 %and1, %notb148 %ret_cast = bitcast i32 %and2 to float149 ret float %ret_cast150}151 152define amdgpu_ps float @and_and_not_and(i32 %a, i32 %b, i32 %c) {153; GFX950-SDAG-LABEL: and_and_not_and:154; GFX950-SDAG: ; %bb.0:155; GFX950-SDAG-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:0x40156; GFX950-SDAG-NEXT: ; return to shader part epilog157;158; GFX950-GISEL-LABEL: and_and_not_and:159; GFX950-GISEL: ; %bb.0:160; GFX950-GISEL-NEXT: v_bitop3_b32 v0, v0, v2, v0 bitop3:0x30161; GFX950-GISEL-NEXT: v_and_b32_e32 v0, v0, v1162; GFX950-GISEL-NEXT: ; return to shader part epilog163;164; GFX1250-SDAG-LABEL: and_and_not_and:165; GFX1250-SDAG: ; %bb.0:166; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1167; GFX1250-SDAG-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:0x40168; GFX1250-SDAG-NEXT: ; return to shader part epilog169;170; GFX1250-GISEL-LABEL: and_and_not_and:171; GFX1250-GISEL: ; %bb.0:172; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1173; GFX1250-GISEL-NEXT: v_bitop3_b32 v0, v0, v2, v0 bitop3:0x30174; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)175; GFX1250-GISEL-NEXT: v_and_b32_e32 v0, v0, v1176; GFX1250-GISEL-NEXT: ; return to shader part epilog177 %notc = xor i32 %c, -1178 %and1 = and i32 %a, %notc179 %and2 = and i32 %and1, %b180 %ret_cast = bitcast i32 %and2 to float181 ret float %ret_cast182}183 184define amdgpu_ps float @and_and_and(i32 %a, i32 %b, i32 %c) {185; GFX950-LABEL: and_and_and:186; GFX950: ; %bb.0:187; GFX950-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:0x80188; GFX950-NEXT: ; return to shader part epilog189;190; GFX1250-LABEL: and_and_and:191; GFX1250: ; %bb.0:192; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1193; GFX1250-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:0x80194; GFX1250-NEXT: ; return to shader part epilog195 %and1 = and i32 %a, %c196 %and2 = and i32 %and1, %b197 %ret_cast = bitcast i32 %and2 to float198 ret float %ret_cast199}200 201; ========= Multi bit functions =========202 203define amdgpu_ps float @test_12(i32 %a, i32 %b) {204; GFX950-LABEL: test_12:205; GFX950: ; %bb.0:206; GFX950-NEXT: v_bitop3_b32 v0, v0, v1, v0 bitop3:0xc207; GFX950-NEXT: ; return to shader part epilog208;209; GFX1250-LABEL: test_12:210; GFX1250: ; %bb.0:211; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1212; GFX1250-NEXT: v_bitop3_b32 v0, v0, v1, v0 bitop3:0xc213; GFX1250-NEXT: ; return to shader part epilog214 %nota = xor i32 %a, -1215 %and1 = and i32 %nota, %b216 %ret_cast = bitcast i32 %and1 to float217 ret float %ret_cast218}219 220define amdgpu_ps float @test_63(i32 %a, i32 %b) {221; GFX950-SDAG-LABEL: test_63:222; GFX950-SDAG: ; %bb.0:223; GFX950-SDAG-NEXT: v_bitop3_b32 v0, v0, v1, v0 bitop3:0x3f224; GFX950-SDAG-NEXT: ; return to shader part epilog225;226; GFX950-GISEL-LABEL: test_63:227; GFX950-GISEL: ; %bb.0:228; GFX950-GISEL-NEXT: v_not_b32_e32 v1, v1229; GFX950-GISEL-NEXT: v_bfi_b32 v0, v0, v1, -1230; GFX950-GISEL-NEXT: ; return to shader part epilog231;232; GFX1250-SDAG-LABEL: test_63:233; GFX1250-SDAG: ; %bb.0:234; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1235; GFX1250-SDAG-NEXT: v_bitop3_b32 v0, v0, v1, v0 bitop3:0x3f236; GFX1250-SDAG-NEXT: ; return to shader part epilog237;238; GFX1250-GISEL-LABEL: test_63:239; GFX1250-GISEL: ; %bb.0:240; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1241; GFX1250-GISEL-NEXT: v_not_b32_e32 v1, v1242; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)243; GFX1250-GISEL-NEXT: v_bfi_b32 v0, v0, v1, -1244; GFX1250-GISEL-NEXT: ; return to shader part epilog245 %nota = xor i32 %a, -1246 %notb = xor i32 %b, -1247 %or = or i32 %nota, %notb248 %ret_cast = bitcast i32 %or to float249 ret float %ret_cast250}251 252define amdgpu_ps float @test_59(i32 %a, i32 %b, i32 %c) {253; GFX950-LABEL: test_59:254; GFX950: ; %bb.0:255; GFX950-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:0x3b256; GFX950-NEXT: ; return to shader part epilog257;258; GFX1250-LABEL: test_59:259; GFX1250: ; %bb.0:260; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1261; GFX1250-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:0x3b262; GFX1250-NEXT: ; return to shader part epilog263 %nota = xor i32 %a, -1264 %notb = xor i32 %b, -1265 %and1 = and i32 %nota, %c266 %or = or i32 %and1, %notb267 %ret_cast = bitcast i32 %or to float268 ret float %ret_cast269}270 271define amdgpu_ps float @test_126(i32 %a, i32 %b, i32 %c) {272; GFX950-SDAG-LABEL: test_126:273; GFX950-SDAG: ; %bb.0:274; GFX950-SDAG-NEXT: v_bitop3_b32 v0, v0, v2, v1 bitop3:0x7e275; GFX950-SDAG-NEXT: ; return to shader part epilog276;277; GFX950-GISEL-LABEL: test_126:278; GFX950-GISEL: ; %bb.0:279; GFX950-GISEL-NEXT: v_xor_b32_e32 v1, v0, v1280; GFX950-GISEL-NEXT: v_xor_b32_e32 v0, v0, v2281; GFX950-GISEL-NEXT: v_or_b32_e32 v0, v1, v0282; GFX950-GISEL-NEXT: ; return to shader part epilog283;284; GFX1250-SDAG-LABEL: test_126:285; GFX1250-SDAG: ; %bb.0:286; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1287; GFX1250-SDAG-NEXT: v_bitop3_b32 v0, v0, v2, v1 bitop3:0x7e288; GFX1250-SDAG-NEXT: ; return to shader part epilog289;290; GFX1250-GISEL-LABEL: test_126:291; GFX1250-GISEL: ; %bb.0:292; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1293; GFX1250-GISEL-NEXT: v_xor_b32_e32 v1, v0, v1294; GFX1250-GISEL-NEXT: v_xor_b32_e32 v0, v0, v2295; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)296; GFX1250-GISEL-NEXT: v_or_b32_e32 v0, v1, v0297; GFX1250-GISEL-NEXT: ; return to shader part epilog298 %xor1 = xor i32 %a, %b299 %xor2 = xor i32 %a, %c300 %or = or i32 %xor1, %xor2301 %ret_cast = bitcast i32 %or to float302 ret float %ret_cast303}304 305; Src vector exhausted during search but recovered using 'not' lookahead.306; GlobalISel has slightly different input, so it does not happen.307 308; FIXME: Improve global isel code.309 310define amdgpu_ps float @test_12_src_overflow(i32 %a, i32 %b, i32 %c) {311; GFX950-SDAG-LABEL: test_12_src_overflow:312; GFX950-SDAG: ; %bb.0:313; GFX950-SDAG-NEXT: v_bitop3_b32 v0, v0, v1, v0 bitop3:0xc314; GFX950-SDAG-NEXT: ; return to shader part epilog315;316; GFX950-GISEL-LABEL: test_12_src_overflow:317; GFX950-GISEL: ; %bb.0:318; GFX950-GISEL-NEXT: v_not_b32_e32 v3, v0319; GFX950-GISEL-NEXT: v_bitop3_b32 v0, v0, v2, v0 bitop3:0xc320; GFX950-GISEL-NEXT: v_bfi_b32 v2, v2, 0, v3321; GFX950-GISEL-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:0xc8322; GFX950-GISEL-NEXT: ; return to shader part epilog323;324; GFX1250-SDAG-LABEL: test_12_src_overflow:325; GFX1250-SDAG: ; %bb.0:326; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1327; GFX1250-SDAG-NEXT: v_bitop3_b32 v0, v0, v1, v0 bitop3:0xc328; GFX1250-SDAG-NEXT: ; return to shader part epilog329;330; GFX1250-GISEL-LABEL: test_12_src_overflow:331; GFX1250-GISEL: ; %bb.0:332; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1333; GFX1250-GISEL-NEXT: v_not_b32_e32 v3, v0334; GFX1250-GISEL-NEXT: v_bitop3_b32 v0, v0, v2, v0 bitop3:0xc335; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)336; GFX1250-GISEL-NEXT: v_bfi_b32 v2, v2, 0, v3337; GFX1250-GISEL-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:0xc8338; GFX1250-GISEL-NEXT: ; return to shader part epilog339 %nota = xor i32 %a, -1340 %notc = xor i32 %c, -1341 %and1 = and i32 %nota, %c342 %and2 = and i32 %and1, %b343 %and3 = and i32 %nota, %notc344 %and4 = and i32 %and3, %b345 %or = or i32 %and2, %and4346 %ret_cast = bitcast i32 %or to float347 ret float %ret_cast348}349 350; This could be a single LOP3 operation with tbl = 100, but Src vector exhausted during search.351 352define amdgpu_ps float @test_100_src_overflow(i32 %a, i32 %b, i32 %c) {353; GFX950-SDAG-LABEL: test_100_src_overflow:354; GFX950-SDAG: ; %bb.0:355; GFX950-SDAG-NEXT: v_bitop3_b32 v3, v1, v2, v0 bitop3:0x10356; GFX950-SDAG-NEXT: v_bitop3_b32 v4, v0, v2, v1 bitop3:0x40357; GFX950-SDAG-NEXT: v_bitop3_b32 v0, v1, v2, v0 bitop3:0x20358; GFX950-SDAG-NEXT: v_or3_b32 v0, v3, v4, v0359; GFX950-SDAG-NEXT: ; return to shader part epilog360;361; GFX950-GISEL-LABEL: test_100_src_overflow:362; GFX950-GISEL: ; %bb.0:363; GFX950-GISEL-NEXT: v_or_b32_e32 v3, v2, v0364; GFX950-GISEL-NEXT: v_bitop3_b32 v4, v0, v1, v0 bitop3:0x30365; GFX950-GISEL-NEXT: v_and_b32_e32 v0, v1, v0366; GFX950-GISEL-NEXT: v_bfi_b32 v3, v3, 0, v1367; GFX950-GISEL-NEXT: v_and_b32_e32 v4, v4, v2368; GFX950-GISEL-NEXT: v_bfi_b32 v0, v2, 0, v0369; GFX950-GISEL-NEXT: v_or3_b32 v0, v3, v4, v0370; GFX950-GISEL-NEXT: ; return to shader part epilog371;372; GFX1250-SDAG-LABEL: test_100_src_overflow:373; GFX1250-SDAG: ; %bb.0:374; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1375; GFX1250-SDAG-NEXT: v_bitop3_b32 v3, v1, v2, v0 bitop3:0x10376; GFX1250-SDAG-NEXT: v_bitop3_b32 v4, v0, v2, v1 bitop3:0x40377; GFX1250-SDAG-NEXT: v_bitop3_b32 v0, v1, v2, v0 bitop3:0x20378; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)379; GFX1250-SDAG-NEXT: v_or3_b32 v0, v3, v4, v0380; GFX1250-SDAG-NEXT: ; return to shader part epilog381;382; GFX1250-GISEL-LABEL: test_100_src_overflow:383; GFX1250-GISEL: ; %bb.0:384; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1385; GFX1250-GISEL-NEXT: v_or_b32_e32 v3, v2, v0386; GFX1250-GISEL-NEXT: v_bitop3_b32 v4, v0, v1, v0 bitop3:0x30387; GFX1250-GISEL-NEXT: v_and_b32_e32 v0, v1, v0388; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)389; GFX1250-GISEL-NEXT: v_bfi_b32 v1, v3, 0, v1390; GFX1250-GISEL-NEXT: v_and_b32_e32 v3, v4, v2391; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)392; GFX1250-GISEL-NEXT: v_bfi_b32 v0, v2, 0, v0393; GFX1250-GISEL-NEXT: v_or3_b32 v0, v1, v3, v0394; GFX1250-GISEL-NEXT: ; return to shader part epilog395 %or1 = or i32 %c, %a396 %not1 = xor i32 %or1, -1397 %and1 = and i32 %b, %not1398 %not2 = xor i32 %b, -1399 %and2 = and i32 %a, %not2400 %and3 = and i32 %and2, %c401 %and4 = and i32 %b, %a402 %not3 = xor i32 %c, -1403 %and5 = and i32 %and4, %not3404 %or2 = or i32 %and1, %and3405 %or3 = or i32 %or2, %and5406 %ret_cast = bitcast i32 %or3 to float407 ret float %ret_cast408}409 410; ========= Ternary logical operations take precedence =========411 412define amdgpu_ps float @test_xor3(i32 %a, i32 %b, i32 %c) {413; GFX950-LABEL: test_xor3:414; GFX950: ; %bb.0:415; GFX950-NEXT: v_xor_b32_e32 v0, v0, v1416; GFX950-NEXT: v_xor_b32_e32 v0, v0, v2417; GFX950-NEXT: ; return to shader part epilog418;419; GFX1250-LABEL: test_xor3:420; GFX1250: ; %bb.0:421; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1422; GFX1250-NEXT: v_xor3_b32 v0, v0, v1, v2423; GFX1250-NEXT: ; return to shader part epilog424 %xor1 = xor i32 %a, %b425 %xor2 = xor i32 %xor1, %c426 %ret_cast = bitcast i32 %xor2 to float427 ret float %ret_cast428}429 430define amdgpu_ps float @test_or3(i32 %a, i32 %b, i32 %c) {431; GFX950-LABEL: test_or3:432; GFX950: ; %bb.0:433; GFX950-NEXT: v_or3_b32 v0, v0, v1, v2434; GFX950-NEXT: ; return to shader part epilog435;436; GFX1250-LABEL: test_or3:437; GFX1250: ; %bb.0:438; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1439; GFX1250-NEXT: v_or3_b32 v0, v0, v1, v2440; GFX1250-NEXT: ; return to shader part epilog441 %or1 = or i32 %a, %b442 %or2 = or i32 %or1, %c443 %ret_cast = bitcast i32 %or2 to float444 ret float %ret_cast445}446 447define amdgpu_ps float @test_and_or(i32 %a, i32 %b, i32 %c) {448; GFX950-LABEL: test_and_or:449; GFX950: ; %bb.0:450; GFX950-NEXT: v_and_or_b32 v0, v0, v1, v2451; GFX950-NEXT: ; return to shader part epilog452;453; GFX1250-LABEL: test_and_or:454; GFX1250: ; %bb.0:455; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1456; GFX1250-NEXT: v_and_or_b32 v0, v0, v1, v2457; GFX1250-NEXT: ; return to shader part epilog458 %and1 = and i32 %a, %b459 %or1 = or i32 %and1, %c460 %ret_cast = bitcast i32 %or1 to float461 ret float %ret_cast462}463 464; ========= Uniform cases =========465 466define amdgpu_ps float @uniform_3_op(i32 inreg %a, i32 inreg %b, i32 inreg %c) {467; GFX950-LABEL: uniform_3_op:468; GFX950: ; %bb.0:469; GFX950-NEXT: s_andn2_b32 s0, s2, s0470; GFX950-NEXT: s_and_b32 s0, s0, s1471; GFX950-NEXT: v_mov_b32_e32 v0, s0472; GFX950-NEXT: ; return to shader part epilog473;474; GFX1250-LABEL: uniform_3_op:475; GFX1250: ; %bb.0:476; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1477; GFX1250-NEXT: s_and_not1_b32 s0, s2, s0478; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)479; GFX1250-NEXT: s_and_b32 s0, s0, s1480; GFX1250-NEXT: v_mov_b32_e32 v0, s0481; GFX1250-NEXT: ; return to shader part epilog482 %nota = xor i32 %a, -1483 %and1 = and i32 %nota, %c484 %and2 = and i32 %and1, %b485 %ret_cast = bitcast i32 %and2 to float486 ret float %ret_cast487}488 489define amdgpu_ps float @uniform_4_op(i32 inreg %a, i32 inreg %b, i32 inreg %c) {490; GFX950-SDAG-LABEL: uniform_4_op:491; GFX950-SDAG: ; %bb.0:492; GFX950-SDAG-NEXT: v_mov_b32_e32 v0, s1493; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, s2494; GFX950-SDAG-NEXT: v_bitop3_b32 v0, s0, v0, v1 bitop3:2495; GFX950-SDAG-NEXT: ; return to shader part epilog496;497; GFX950-GISEL-LABEL: uniform_4_op:498; GFX950-GISEL: ; %bb.0:499; GFX950-GISEL-NEXT: s_andn2_b32 s0, s2, s0500; GFX950-GISEL-NEXT: s_andn2_b32 s0, s0, s1501; GFX950-GISEL-NEXT: v_mov_b32_e32 v0, s0502; GFX950-GISEL-NEXT: ; return to shader part epilog503;504; GFX1250-SDAG-LABEL: uniform_4_op:505; GFX1250-SDAG: ; %bb.0:506; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1507; GFX1250-SDAG-NEXT: v_mov_b32_e32 v0, s2508; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)509; GFX1250-SDAG-NEXT: v_bitop3_b32 v0, s0, s1, v0 bitop3:2510; GFX1250-SDAG-NEXT: ; return to shader part epilog511;512; GFX1250-GISEL-LABEL: uniform_4_op:513; GFX1250-GISEL: ; %bb.0:514; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1515; GFX1250-GISEL-NEXT: s_and_not1_b32 s0, s2, s0516; GFX1250-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)517; GFX1250-GISEL-NEXT: s_and_not1_b32 s0, s0, s1518; GFX1250-GISEL-NEXT: v_mov_b32_e32 v0, s0519; GFX1250-GISEL-NEXT: ; return to shader part epilog520 %nota = xor i32 %a, -1521 %notb = xor i32 %b, -1522 %and1 = and i32 %nota, %c523 %and2 = and i32 %and1, %notb524 %ret_cast = bitcast i32 %and2 to float525 ret float %ret_cast526}527 528; ========= 16 bit tests =========529 530define amdgpu_ps half @not_and_not_and_not_and_b16(i16 %a, i16 %b, i16 %c) {531; GFX950-LABEL: not_and_not_and_not_and_b16:532; GFX950: ; %bb.0:533; GFX950-NEXT: v_bitop3_b16 v0, v0, v1, v2 bitop3:1534; GFX950-NEXT: ; return to shader part epilog535;536; GFX1250-SDAG-FAKE16-LABEL: not_and_not_and_not_and_b16:537; GFX1250-SDAG-FAKE16: ; %bb.0:538; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1539; GFX1250-SDAG-FAKE16-NEXT: v_bitop3_b16 v0, v0, v1, v2 bitop3:1540; GFX1250-SDAG-FAKE16-NEXT: ; return to shader part epilog541;542; GFX1250-SDAG-TRUE16-LABEL: not_and_not_and_not_and_b16:543; GFX1250-SDAG-TRUE16: ; %bb.0:544; GFX1250-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1545; GFX1250-SDAG-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v1.l, v2.l bitop3:1546; GFX1250-SDAG-TRUE16-NEXT: ; return to shader part epilog547;548; GFX1250-GISEL-FAKE16-LABEL: not_and_not_and_not_and_b16:549; GFX1250-GISEL-FAKE16: ; %bb.0:550; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1551; GFX1250-GISEL-FAKE16-NEXT: v_bitop3_b16 v0, v0, v1, v2 bitop3:1552; GFX1250-GISEL-FAKE16-NEXT: ; return to shader part epilog553;554; GFX1250-GISEL-TRUE16-LABEL: not_and_not_and_not_and_b16:555; GFX1250-GISEL-TRUE16: ; %bb.0:556; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1557; GFX1250-GISEL-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v1.l, v2.l bitop3:1558; GFX1250-GISEL-TRUE16-NEXT: ; return to shader part epilog559 %nota = xor i16 %a, -1560 %notb = xor i16 %b, -1561 %notc = xor i16 %c, -1562 %and1 = and i16 %nota, %notc563 %and2 = and i16 %and1, %notb564 %ret_cast = bitcast i16 %and2 to half565 ret half %ret_cast566}567 568define amdgpu_ps half @not_and_not_and_and_b16(i16 %a, i16 %b, i16 %c) {569; GFX950-LABEL: not_and_not_and_and_b16:570; GFX950: ; %bb.0:571; GFX950-NEXT: v_bitop3_b16 v0, v0, v1, v2 bitop3:2572; GFX950-NEXT: ; return to shader part epilog573;574; GFX1250-SDAG-FAKE16-LABEL: not_and_not_and_and_b16:575; GFX1250-SDAG-FAKE16: ; %bb.0:576; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1577; GFX1250-SDAG-FAKE16-NEXT: v_bitop3_b16 v0, v0, v1, v2 bitop3:2578; GFX1250-SDAG-FAKE16-NEXT: ; return to shader part epilog579;580; GFX1250-SDAG-TRUE16-LABEL: not_and_not_and_and_b16:581; GFX1250-SDAG-TRUE16: ; %bb.0:582; GFX1250-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1583; GFX1250-SDAG-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v1.l, v2.l bitop3:2584; GFX1250-SDAG-TRUE16-NEXT: ; return to shader part epilog585;586; GFX1250-GISEL-FAKE16-LABEL: not_and_not_and_and_b16:587; GFX1250-GISEL-FAKE16: ; %bb.0:588; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1589; GFX1250-GISEL-FAKE16-NEXT: v_bitop3_b16 v0, v0, v1, v2 bitop3:2590; GFX1250-GISEL-FAKE16-NEXT: ; return to shader part epilog591;592; GFX1250-GISEL-TRUE16-LABEL: not_and_not_and_and_b16:593; GFX1250-GISEL-TRUE16: ; %bb.0:594; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1595; GFX1250-GISEL-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v1.l, v2.l bitop3:2596; GFX1250-GISEL-TRUE16-NEXT: ; return to shader part epilog597 %nota = xor i16 %a, -1598 %notb = xor i16 %b, -1599 %and1 = and i16 %nota, %c600 %and2 = and i16 %and1, %notb601 %ret_cast = bitcast i16 %and2 to half602 ret half %ret_cast603}604 605define amdgpu_ps half @not_and_and_not_and_b16(i16 %a, i16 %b, i16 %c) {606; GFX950-LABEL: not_and_and_not_and_b16:607; GFX950: ; %bb.0:608; GFX950-NEXT: v_bitop3_b16 v0, v0, v1, v2 bitop3:4609; GFX950-NEXT: ; return to shader part epilog610;611; GFX1250-SDAG-FAKE16-LABEL: not_and_and_not_and_b16:612; GFX1250-SDAG-FAKE16: ; %bb.0:613; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1614; GFX1250-SDAG-FAKE16-NEXT: v_bitop3_b16 v0, v0, v1, v2 bitop3:4615; GFX1250-SDAG-FAKE16-NEXT: ; return to shader part epilog616;617; GFX1250-SDAG-TRUE16-LABEL: not_and_and_not_and_b16:618; GFX1250-SDAG-TRUE16: ; %bb.0:619; GFX1250-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1620; GFX1250-SDAG-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v1.l, v2.l bitop3:4621; GFX1250-SDAG-TRUE16-NEXT: ; return to shader part epilog622;623; GFX1250-GISEL-FAKE16-LABEL: not_and_and_not_and_b16:624; GFX1250-GISEL-FAKE16: ; %bb.0:625; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1626; GFX1250-GISEL-FAKE16-NEXT: v_bitop3_b16 v0, v0, v1, v2 bitop3:4627; GFX1250-GISEL-FAKE16-NEXT: ; return to shader part epilog628;629; GFX1250-GISEL-TRUE16-LABEL: not_and_and_not_and_b16:630; GFX1250-GISEL-TRUE16: ; %bb.0:631; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1632; GFX1250-GISEL-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v1.l, v2.l bitop3:4633; GFX1250-GISEL-TRUE16-NEXT: ; return to shader part epilog634 %nota = xor i16 %a, -1635 %notc = xor i16 %c, -1636 %and1 = and i16 %nota, %notc637 %and2 = and i16 %and1, %b638 %ret_cast = bitcast i16 %and2 to half639 ret half %ret_cast640}641 642define amdgpu_ps half @test_xor3_b16(i16 %a, i16 %b, i16 %c) {643; GFX950-SDAG-LABEL: test_xor3_b16:644; GFX950-SDAG: ; %bb.0:645; GFX950-SDAG-NEXT: v_bitop3_b16 v0, v0, v2, v1 bitop3:0x96646; GFX950-SDAG-NEXT: ; return to shader part epilog647;648; GFX950-GISEL-LABEL: test_xor3_b16:649; GFX950-GISEL: ; %bb.0:650; GFX950-GISEL-NEXT: v_xor_b32_e32 v0, v0, v1651; GFX950-GISEL-NEXT: v_xor_b32_e32 v0, v0, v2652; GFX950-GISEL-NEXT: ; return to shader part epilog653;654; GFX1250-SDAG-FAKE16-LABEL: test_xor3_b16:655; GFX1250-SDAG-FAKE16: ; %bb.0:656; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1657; GFX1250-SDAG-FAKE16-NEXT: v_bitop3_b16 v0, v0, v2, v1 bitop3:0x96658; GFX1250-SDAG-FAKE16-NEXT: ; return to shader part epilog659;660; GFX1250-SDAG-TRUE16-LABEL: test_xor3_b16:661; GFX1250-SDAG-TRUE16: ; %bb.0:662; GFX1250-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1663; GFX1250-SDAG-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v2.l, v1.l bitop3:0x96664; GFX1250-SDAG-TRUE16-NEXT: ; return to shader part epilog665;666; GFX1250-GISEL-LABEL: test_xor3_b16:667; GFX1250-GISEL: ; %bb.0:668; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1669; GFX1250-GISEL-NEXT: v_xor3_b32 v0, v0, v1, v2670; GFX1250-GISEL-NEXT: ; return to shader part epilog671 %xor1 = xor i16 %a, %b672 %xor2 = xor i16 %xor1, %c673 %ret_cast = bitcast i16 %xor2 to half674 ret half %ret_cast675}676 677define amdgpu_ps half @test_or3_b16(i16 %a, i16 %b, i16 %c) {678; GFX950-SDAG-LABEL: test_or3_b16:679; GFX950-SDAG: ; %bb.0:680; GFX950-SDAG-NEXT: v_bitop3_b16 v0, v0, v2, v1 bitop3:0xfe681; GFX950-SDAG-NEXT: ; return to shader part epilog682;683; GFX950-GISEL-LABEL: test_or3_b16:684; GFX950-GISEL: ; %bb.0:685; GFX950-GISEL-NEXT: v_or3_b32 v0, v0, v1, v2686; GFX950-GISEL-NEXT: ; return to shader part epilog687;688; GFX1250-SDAG-FAKE16-LABEL: test_or3_b16:689; GFX1250-SDAG-FAKE16: ; %bb.0:690; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1691; GFX1250-SDAG-FAKE16-NEXT: v_bitop3_b16 v0, v0, v2, v1 bitop3:0xfe692; GFX1250-SDAG-FAKE16-NEXT: ; return to shader part epilog693;694; GFX1250-SDAG-TRUE16-LABEL: test_or3_b16:695; GFX1250-SDAG-TRUE16: ; %bb.0:696; GFX1250-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1697; GFX1250-SDAG-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v2.l, v1.l bitop3:0xfe698; GFX1250-SDAG-TRUE16-NEXT: ; return to shader part epilog699;700; GFX1250-GISEL-LABEL: test_or3_b16:701; GFX1250-GISEL: ; %bb.0:702; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1703; GFX1250-GISEL-NEXT: v_or3_b32 v0, v0, v1, v2704; GFX1250-GISEL-NEXT: ; return to shader part epilog705 %or1 = or i16 %a, %b706 %or2 = or i16 %or1, %c707 %ret_cast = bitcast i16 %or2 to half708 ret half %ret_cast709}710 711define amdgpu_ps half @test_and_or_b16(i16 %a, i16 %b, i16 %c) {712; GFX950-SDAG-LABEL: test_and_or_b16:713; GFX950-SDAG: ; %bb.0:714; GFX950-SDAG-NEXT: v_bitop3_b16 v0, v0, v2, v1 bitop3:0xec715; GFX950-SDAG-NEXT: ; return to shader part epilog716;717; GFX950-GISEL-LABEL: test_and_or_b16:718; GFX950-GISEL: ; %bb.0:719; GFX950-GISEL-NEXT: v_and_or_b32 v0, v0, v1, v2720; GFX950-GISEL-NEXT: ; return to shader part epilog721;722; GFX1250-SDAG-FAKE16-LABEL: test_and_or_b16:723; GFX1250-SDAG-FAKE16: ; %bb.0:724; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1725; GFX1250-SDAG-FAKE16-NEXT: v_bitop3_b16 v0, v0, v2, v1 bitop3:0xec726; GFX1250-SDAG-FAKE16-NEXT: ; return to shader part epilog727;728; GFX1250-SDAG-TRUE16-LABEL: test_and_or_b16:729; GFX1250-SDAG-TRUE16: ; %bb.0:730; GFX1250-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1731; GFX1250-SDAG-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v2.l, v1.l bitop3:0xec732; GFX1250-SDAG-TRUE16-NEXT: ; return to shader part epilog733;734; GFX1250-GISEL-LABEL: test_and_or_b16:735; GFX1250-GISEL: ; %bb.0:736; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1737; GFX1250-GISEL-NEXT: v_and_or_b32 v0, v0, v1, v2738; GFX1250-GISEL-NEXT: ; return to shader part epilog739 %and1 = and i16 %a, %b740 %or1 = or i16 %and1, %c741 %ret_cast = bitcast i16 %or1 to half742 ret half %ret_cast743}744;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:745; GCN: {{.*}}746; GFX1250-FAKE16: {{.*}}747; GFX1250-TRUE16: {{.*}}748