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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 22# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1031 -run-pass=register-coalescer -verify-coalescing -o - %s | FileCheck %s3# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1031 -passes=register-coalescer -verify-coalescing -o - %s | FileCheck %s4 5# Testcase variants from6# liveout-implicit-def-subreg-redef-blender-verifier-error.mir which7# hit other verifier errors after coalescing.8 9# Same as previous, except the initial value isn't an implicit_def10---11name: liveout_defined_register_redefine_sub0_implicit_def12tracksRegLiveness: true13body: |14 ; CHECK-LABEL: name: liveout_defined_register_redefine_sub0_implicit_def15 ; CHECK: bb.0:16 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)17 ; CHECK-NEXT: {{ $}}18 ; CHECK-NEXT: S_CBRANCH_SCC0 %bb.2, implicit undef $scc19 ; CHECK-NEXT: {{ $}}20 ; CHECK-NEXT: bb.1:21 ; CHECK-NEXT: successors: %bb.3(0x80000000)22 ; CHECK-NEXT: {{ $}}23 ; CHECK-NEXT: S_NOP 0, implicit-def %024 ; CHECK-NEXT: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_128 = S_MOV_B32 025 ; CHECK-NEXT: S_BRANCH %bb.326 ; CHECK-NEXT: {{ $}}27 ; CHECK-NEXT: bb.2:28 ; CHECK-NEXT: successors: %bb.3(0x80000000)29 ; CHECK-NEXT: {{ $}}30 ; CHECK-NEXT: undef [[DEF:%[0-9]+]].sub0:sgpr_128 = IMPLICIT_DEF31 ; CHECK-NEXT: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_128 = IMPLICIT_DEF32 ; CHECK-NEXT: {{ $}}33 ; CHECK-NEXT: bb.3:34 ; CHECK-NEXT: S_NOP 0, implicit [[DEF]]35 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]].sub036 ; CHECK-NEXT: S_ENDPGM 037 bb.0:38 S_CBRANCH_SCC0 %bb.2, implicit undef $scc39 40 bb.1:41 S_NOP 0, implicit-def %0:sgpr_12842 %1:sgpr_32 = S_MOV_B32 043 S_BRANCH %bb.344 45 bb.2:46 undef %0.sub0:sgpr_128 = IMPLICIT_DEF47 %1:sgpr_32 = COPY %0.sub048 49 bb.3:50 S_NOP 0, implicit %051 S_NOP 0, implicit %152 S_ENDPGM 053 54...55 56# Compare with first57---58name: second_def_is_real59tracksRegLiveness: true60body: |61 ; CHECK-LABEL: name: second_def_is_real62 ; CHECK: bb.0:63 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)64 ; CHECK-NEXT: {{ $}}65 ; CHECK-NEXT: S_CBRANCH_SCC0 %bb.2, implicit undef $scc66 ; CHECK-NEXT: {{ $}}67 ; CHECK-NEXT: bb.1:68 ; CHECK-NEXT: successors: %bb.3(0x80000000)69 ; CHECK-NEXT: {{ $}}70 ; CHECK-NEXT: S_NOP 0, implicit-def %071 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 072 ; CHECK-NEXT: S_BRANCH %bb.373 ; CHECK-NEXT: {{ $}}74 ; CHECK-NEXT: bb.2:75 ; CHECK-NEXT: successors: %bb.3(0x80000000)76 ; CHECK-NEXT: {{ $}}77 ; CHECK-NEXT: undef [[S_MOV_B32_1:%[0-9]+]].sub0:sgpr_128 = S_MOV_B32 12378 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 12379 ; CHECK-NEXT: {{ $}}80 ; CHECK-NEXT: bb.3:81 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]82 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]83 ; CHECK-NEXT: S_ENDPGM 084 bb.0:85 S_CBRANCH_SCC0 %bb.2, implicit undef $scc86 87 bb.1:88 S_NOP 0, implicit-def %0:sgpr_12889 %1:sgpr_32 = S_MOV_B32 090 S_BRANCH %bb.391 92 bb.2:93 undef %0.sub0:sgpr_128 = S_MOV_B32 12394 %1:sgpr_32 = COPY %0.sub095 96 bb.3:97 S_NOP 0, implicit %098 S_NOP 0, implicit %199 S_ENDPGM 0100 101...102