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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn -mcpu=tahiti -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=GCN %s3; RUN: llc -mtriple=amdgcn -mcpu=tonga -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=GCN %s4 5; This used to crash because during intermediate control flow lowering, there6; was a sequence7; s_mov_b64 s[0:1], exec8; s_and_b64 s[2:3], s[0:1], s[2:3] ; def & use of the same register pair9; ...10; s_mov_b64_term exec, s[2:3]11; that was not treated correctly.12;13define amdgpu_ps void @ham(float %arg, float %arg1) #0 {14; GCN-LABEL: ham:15; GCN: ; %bb.0: ; %bb16; GCN-NEXT: v_cmp_lt_f32_e32 vcc, 0, v017; GCN-NEXT: v_cmp_lt_f32_e64 s[0:1], 0, v118; GCN-NEXT: s_and_b64 s[0:1], vcc, s[0:1]19; GCN-NEXT: s_and_saveexec_b64 s[2:3], s[0:1]20; GCN-NEXT: ; %bb.1: ; %bb421; GCN-NEXT: v_mov_b32_e32 v0, 422; GCN-NEXT: s_mov_b32 m0, -123; GCN-NEXT: ds_write_b32 v0, v024; GCN-NEXT: ; divergent unreachable25; GCN-NEXT: ; %bb.2: ; %UnifiedReturnBlock26; GCN-NEXT: s_endpgm27bb:28 %tmp = fcmp ogt float %arg, 0.000000e+0029 %tmp2 = fcmp ogt float %arg1, 0.000000e+0030 %tmp3 = and i1 %tmp, %tmp231 br i1 %tmp3, label %bb4, label %bb532 33bb4: ; preds = %bb34 store volatile i32 4, ptr addrspace(3) poison35 unreachable36 37bb5: ; preds = %bb38 ret void39}40 41attributes #0 = { nounwind readonly "InitialPSInputAddr"="36983" }42attributes #1 = { nounwind readnone }43