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1; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -amdgpu-s-branch-bits=7 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX1030 %s2; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -amdgpu-s-branch-bits=7 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX1010 %s3; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-s-branch-bits=7 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX1030 %s4 5; For gfx1010, overestimate the branch size in case we need to insert6; a nop for the buggy offset.7 8; GCN-LABEL: long_forward_scc_branch_3f_offset_bug:9; GFX1030: s_cmp_lg_u3210; GFX1030: s_cbranch_scc1 [[ENDBB:.LBB[0-9]+_[0-9]+]]11 12; GFX1010: s_cmp_lg_u3213; GFX1010-NEXT: s_cbranch_scc0 [[RELAX_BB:.LBB[0-9]+_[0-9]+]]14; GFX1010: s_getpc_b6415; GFX1010-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}}16; GFX1010-NEXT: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, ([[ENDBB:.LBB[0-9]+_[0-9]+]]-[[POST_GETPC]])&429496729517; GFX1010-NEXT: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, ([[ENDBB:.LBB[0-9]+_[0-9]+]]-[[POST_GETPC]])>>3218; GFX1010: [[RELAX_BB]]:19 20; GCN: v_nop21; GCN: s_sleep22; GCN: s_cbranch_scc123 24; GCN: [[ENDBB]]:25; GCN: global_store_{{dword|b32}}26define amdgpu_kernel void @long_forward_scc_branch_3f_offset_bug(ptr addrspace(1) %arg, i32 %cnd0) #0 {27bb0:28 %cmp0 = icmp eq i32 %cnd0, 029 br i1 %cmp0, label %bb2, label %bb330 31bb2:32 %val = call i32 asm sideeffect33 "s_mov_b32 $0, 034 v_nop_e6435 v_nop_e6436 v_nop_e6437 v_nop_e6438 v_nop_e6439 v_nop_e6440 v_nop_e6441 v_nop_e6442 v_nop_e6443 v_nop_e6444 v_nop_e64", "=s"() ; 20 * 12 = 24045 call void @llvm.amdgcn.s.sleep(i32 0) ; +4 = 24446 %cmp1 = icmp eq i32 %val, 0 ; +4 = 24847 br i1 %cmp1, label %bb2, label %bb3 ; +4 (gfx1030), +8 with workaround (gfx1010)48 49bb3:50 store volatile i32 %cnd0, ptr addrspace(1) %arg51 ret void52}53 54; GCN-LABEL: {{^}}long_forward_exec_branch_3f_offset_bug:55; GFX1030: s_mov_b3256; GFX1030: v_cmpx_eq_u3257; GFX1030: s_cbranch_execnz [[RELAX_BB:.LBB[0-9]+_[0-9]+]]58 59; GFX1010: v_cmp_eq_u3260; GFX1010: s_and_saveexec_b3261; GFX1010-NEXT: s_cbranch_execnz [[RELAX_BB:.LBB[0-9]+_[0-9]+]]62 63; GCN: s_getpc_b6464; GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}}65; GCN-NEXT: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, ([[ENDBB:.LBB[0-9]+_[0-9]+]]-[[POST_GETPC]])&429496729566; GCN-NEXT: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, ([[ENDBB:.LBB[0-9]+_[0-9]+]]-[[POST_GETPC]])>>3267; GCN: [[RELAX_BB]]:68 69; GCN: v_nop70; GCN: s_sleep71; GCN: s_cbranch_execz72 73; GCN: [[ENDBB]]:74; GCN: global_store_{{dword|b32}}75define void @long_forward_exec_branch_3f_offset_bug(ptr addrspace(1) %arg, i32 %cnd0) #0 {76bb0:77 %cmp0 = icmp eq i32 %cnd0, 078 br i1 %cmp0, label %bb2, label %bb379 80bb2:81 %val = call i32 asm sideeffect82 "v_mov_b32 $0, 083 v_nop_e6484 v_nop_e6485 v_nop_e6486 v_nop_e6487 v_nop_e6488 v_nop_e6489 v_nop_e6490 v_nop_e6491 v_nop_e6492 v_nop_e6493 v_nop_e64", "=v"() ; 20 * 12 = 24094 call void @llvm.amdgcn.s.sleep(i32 0) ; +4 = 24495 %cmp1 = icmp eq i32 %val, 0 ; +4 = 24896 br i1 %cmp1, label %bb2, label %bb3 ; +4 (gfx1030), +8 with workaround (gfx1010)97 98bb3:99 store volatile i32 %cnd0, ptr addrspace(1) %arg100 ret void101}102 103declare void @llvm.amdgcn.s.sleep(i32 immarg)104