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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -amdgpu-s-branch-bits=4 -simplifycfg-require-and-preserve-domtree=1 -amdgpu-long-branch-factor=0 < %s | FileCheck -enable-var-scope -check-prefix=GCN %s3 4 5; FIXME: We should use llvm-mc for this, but we can't even parse our own output.6; See PR33579.7; RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -amdgpu-s-branch-bits=4 -amdgpu-long-branch-factor=0 -o %t.o -filetype=obj -simplifycfg-require-and-preserve-domtree=1 %s8; RUN: llvm-readobj -r %t.o | FileCheck --check-prefix=OBJ %s9 10; OBJ: Relocations [11; OBJ-NEXT: ]12 13; Restrict maximum branch to between +7 and -8 dwords14 15; Used to emit an always 4 byte instruction. Inline asm always assumes16; each instruction is the maximum size, 12 bytes in case of gfx1250.17declare void @llvm.amdgcn.s.sleep(i32) #018 19declare i32 @llvm.amdgcn.workitem.id.x() #120 21 22define amdgpu_kernel void @uniform_conditional_max_short_forward_branch(ptr addrspace(1) %arg, i32 %cnd) #0 {23; GCN-LABEL: uniform_conditional_max_short_forward_branch:24; GCN: ; %bb.0: ; %bb25; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 126; GCN-NEXT: s_load_b32 s0, s[4:5], 0x2c27; GCN-NEXT: s_wait_kmcnt 0x028; GCN-NEXT: s_cmp_eq_u32 s0, 029; GCN-NEXT: s_cbranch_scc0 .LBB0_130; GCN-NEXT: ; %bb.3: ; %bb31; GCN-NEXT: s_add_pc_i64 .LBB0_2-.Lpost_addpc032; GCN-NEXT: .Lpost_addpc0:33; GCN-NEXT: .LBB0_1: ; %bb234; GCN-NEXT: ;;#ASMSTART35; GCN-NEXT: v_nop_e6436; GCN-NEXT: v_nop_e6437; GCN-NEXT: ;;#ASMEND38; GCN-NEXT: s_sleep 039; GCN-NEXT: .LBB0_2: ; %bb340; GCN-NEXT: s_load_b64 s[2:3], s[4:5], 0x2441; GCN-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s042; GCN-NEXT: s_wait_kmcnt 0x043; GCN-NEXT: global_store_b32 v0, v1, s[2:3] scope:SCOPE_SYS44; GCN-NEXT: s_wait_storecnt 0x045; GCN-NEXT: s_endpgm46bb:47 %cmp = icmp eq i32 %cnd, 048 br i1 %cmp, label %bb3, label %bb2 ; +8 dword branch49 50bb2:51; 24 bytes52 call void asm sideeffect53 "v_nop_e6454 v_nop_e64", ""() #055 call void @llvm.amdgcn.s.sleep(i32 0)56 br label %bb357 58bb3:59 store volatile i32 %cnd, ptr addrspace(1) %arg60 ret void61}62 63define amdgpu_kernel void @uniform_conditional_min_long_forward_branch(ptr addrspace(1) %arg, i32 %cnd) #0 {64; GCN-LABEL: uniform_conditional_min_long_forward_branch:65; GCN: ; %bb.0: ; %bb066; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 167; GCN-NEXT: s_load_b32 s0, s[4:5], 0x2c68; GCN-NEXT: s_wait_kmcnt 0x069; GCN-NEXT: s_cmp_eq_u32 s0, 070; GCN-NEXT: s_cbranch_scc0 .LBB1_171; GCN-NEXT: ; %bb.3: ; %bb072; GCN-NEXT: s_add_pc_i64 .LBB1_2-.Lpost_addpc173; GCN-NEXT: .Lpost_addpc1:74; GCN-NEXT: .LBB1_1: ; %bb275; GCN-NEXT: ;;#ASMSTART76; GCN-NEXT: v_nop_e6477; GCN-NEXT: v_nop_e6478; GCN-NEXT: ;;#ASMEND79; GCN-NEXT: s_sleep 080; GCN-NEXT: s_sleep 081; GCN-NEXT: .LBB1_2: ; %bb382; GCN-NEXT: s_load_b64 s[2:3], s[4:5], 0x2483; GCN-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s084; GCN-NEXT: s_wait_kmcnt 0x085; GCN-NEXT: global_store_b32 v0, v1, s[2:3] scope:SCOPE_SYS86; GCN-NEXT: s_wait_storecnt 0x087; GCN-NEXT: s_endpgm88bb0:89 %cmp = icmp eq i32 %cnd, 090 br i1 %cmp, label %bb3, label %bb2 ; +9 dword branch91 92bb2:93; 32 bytes94 call void asm sideeffect95 "v_nop_e6496 v_nop_e64", ""() #097 call void @llvm.amdgcn.s.sleep(i32 0)98 call void @llvm.amdgcn.s.sleep(i32 0)99 br label %bb3100 101bb3:102 store volatile i32 %cnd, ptr addrspace(1) %arg103 ret void104}105 106define amdgpu_kernel void @uniform_conditional_min_long_forward_vcnd_branch(ptr addrspace(1) %arg, float %cnd) #0 {107; GCN-LABEL: uniform_conditional_min_long_forward_vcnd_branch:108; GCN: ; %bb.0: ; %bb0109; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1110; GCN-NEXT: s_load_b32 s0, s[4:5], 0x2c111; GCN-NEXT: s_wait_kmcnt 0x0112; GCN-NEXT: s_cmp_eq_f32 s0, 0113; GCN-NEXT: s_cbranch_scc0 .LBB2_1114; GCN-NEXT: ; %bb.3: ; %bb0115; GCN-NEXT: s_add_pc_i64 .LBB2_2-.Lpost_addpc2116; GCN-NEXT: .Lpost_addpc2:117; GCN-NEXT: .LBB2_1: ; %bb2118; GCN-NEXT: ;;#ASMSTART119; GCN-NEXT: ; 32 bytes120; GCN-NEXT: v_nop_e64121; GCN-NEXT: v_nop_e64122; GCN-NEXT: ;;#ASMEND123; GCN-NEXT: s_sleep 0124; GCN-NEXT: s_sleep 0125; GCN-NEXT: .LBB2_2: ; %bb3126; GCN-NEXT: s_load_b64 s[2:3], s[4:5], 0x24127; GCN-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0128; GCN-NEXT: s_wait_kmcnt 0x0129; GCN-NEXT: global_store_b32 v0, v1, s[2:3] scope:SCOPE_SYS130; GCN-NEXT: s_wait_storecnt 0x0131; GCN-NEXT: s_endpgm132bb0:133 %cmp = fcmp oeq float %cnd, 0.0134 br i1 %cmp, label %bb3, label %bb2 ; + 8 dword branch135 136bb2:137 call void asm sideeffect " ; 32 bytes138 v_nop_e64139 v_nop_e64", ""() #0140 call void @llvm.amdgcn.s.sleep(i32 0)141 call void @llvm.amdgcn.s.sleep(i32 0)142 br label %bb3143 144bb3:145 store volatile float %cnd, ptr addrspace(1) %arg146 ret void147}148 149define amdgpu_kernel void @min_long_forward_vbranch(ptr addrspace(1) %arg) #0 {150; GCN-LABEL: min_long_forward_vbranch:151; GCN: ; %bb.0: ; %bb152; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1153; GCN-NEXT: s_load_b64 s[0:1], s[4:5], 0x24154; GCN-NEXT: v_and_b32_e32 v0, 0x3ff, v0155; GCN-NEXT: v_mov_b32_e32 v1, 0156; GCN-NEXT: s_wait_kmcnt 0x0157; GCN-NEXT: global_load_b32 v2, v0, s[0:1] scale_offset scope:SCOPE_SYS158; GCN-NEXT: s_wait_loadcnt 0x0159; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v0160; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)161; GCN-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1]162; GCN-NEXT: s_mov_b32 s0, exec_lo163; GCN-NEXT: v_cmpx_ne_u32_e32 0, v2164; GCN-NEXT: s_cbranch_execnz .LBB3_1165; GCN-NEXT: ; %bb.3: ; %bb166; GCN-NEXT: s_add_pc_i64 .LBB3_2-.Lpost_addpc3167; GCN-NEXT: .Lpost_addpc3:168; GCN-NEXT: .LBB3_1: ; %bb2169; GCN-NEXT: ;;#ASMSTART170; GCN-NEXT: ; 32 bytes171; GCN-NEXT: v_nop_e64172; GCN-NEXT: v_nop_e64173; GCN-NEXT: ;;#ASMEND174; GCN-NEXT: s_sleep 0175; GCN-NEXT: s_sleep 0176; GCN-NEXT: .LBB3_2: ; %bb3177; GCN-NEXT: s_or_b32 exec_lo, exec_lo, s0178; GCN-NEXT: global_store_b32 v[0:1], v2, off scope:SCOPE_SYS179; GCN-NEXT: s_wait_storecnt 0x0180; GCN-NEXT: s_endpgm181bb:182 %tid = call i32 @llvm.amdgcn.workitem.id.x()183 %tid.ext = zext i32 %tid to i64184 %gep = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 %tid.ext185 %load = load volatile i32, ptr addrspace(1) %gep186 %cmp = icmp eq i32 %load, 0187 br i1 %cmp, label %bb3, label %bb2 ; + 8 dword branch188 189bb2:190 call void asm sideeffect " ; 32 bytes191 v_nop_e64192 v_nop_e64", ""() #0193 call void @llvm.amdgcn.s.sleep(i32 0)194 call void @llvm.amdgcn.s.sleep(i32 0)195 br label %bb3196 197bb3:198 store volatile i32 %load, ptr addrspace(1) %gep199 ret void200}201 202define amdgpu_kernel void @long_backward_sbranch(ptr addrspace(1) %arg) #0 {203; GCN-LABEL: long_backward_sbranch:204; GCN: ; %bb.0: ; %bb205; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1206; GCN-NEXT: s_mov_b32 s0, 0207; GCN-NEXT: .LBB4_1: ; %bb2208; GCN-NEXT: ; =>This Inner Loop Header: Depth=1209; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)210; GCN-NEXT: s_add_co_i32 s0, s0, 1211; GCN-NEXT: ;;#ASMSTART212; GCN-NEXT: v_nop_e64213; GCN-NEXT: v_nop_e64214; GCN-NEXT: ;;#ASMEND215; GCN-NEXT: s_cmp_lt_i32 s0, 10216; GCN-NEXT: s_cbranch_scc0 .LBB4_2217; GCN-NEXT: ; %bb.3: ; %bb2218; GCN-NEXT: ; in Loop: Header=BB4_1 Depth=1219; GCN-NEXT: s_add_pc_i64 .LBB4_1-.Lpost_addpc4220; GCN-NEXT: .Lpost_addpc4:221; GCN-NEXT: .LBB4_2: ; %bb3222; GCN-NEXT: s_endpgm223bb:224 br label %bb2225 226bb2:227 %loop.idx = phi i32 [ 0, %bb ], [ %inc, %bb2 ]228 ; 24 bytes229 call void asm sideeffect230 "v_nop_e64231 v_nop_e64", ""() #0232 %inc = add nsw i32 %loop.idx, 1 ; add cost 4233 %cmp = icmp slt i32 %inc, 10 ; condition cost = 8234 br i1 %cmp, label %bb2, label %bb3 ; -235 236bb3:237 ret void238}239 240; Requires expansion of unconditional branch from %bb2 to %bb4 (and241; expansion of conditional branch from %bb to %bb3.242 243define amdgpu_kernel void @uniform_unconditional_min_long_forward_branch(ptr addrspace(1) %arg, i32 %arg1) {244; GCN-LABEL: uniform_unconditional_min_long_forward_branch:245; GCN: ; %bb.0: ; %bb0246; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1247; GCN-NEXT: s_load_b32 s0, s[4:5], 0x2c248; GCN-NEXT: s_wait_kmcnt 0x0249; GCN-NEXT: s_cmp_eq_u32 s0, 0250; GCN-NEXT: s_mov_b32 s0, -1251; GCN-NEXT: s_cbranch_scc0 .LBB5_1252; GCN-NEXT: ; %bb.7: ; %bb0253; GCN-NEXT: s_add_pc_i64 .LBB5_4-.Lpost_addpc6254; GCN-NEXT: .Lpost_addpc6:255; GCN-NEXT: .LBB5_1: ; %Flow256; GCN-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0257; GCN-NEXT: s_cbranch_vccnz .LBB5_3258; GCN-NEXT: .LBB5_2: ; %bb2259; GCN-NEXT: v_mov_b32_e32 v0, 17260; GCN-NEXT: global_store_b32 v[0:1], v0, off scope:SCOPE_SYS261; GCN-NEXT: s_wait_storecnt 0x0262; GCN-NEXT: .LBB5_3: ; %bb4263; GCN-NEXT: s_load_b64 s[0:1], s[4:5], 0x24264; GCN-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 63265; GCN-NEXT: s_wait_kmcnt 0x0266; GCN-NEXT: global_store_b32 v0, v1, s[0:1] scope:SCOPE_SYS267; GCN-NEXT: s_wait_storecnt 0x0268; GCN-NEXT: s_endpgm269; GCN-NEXT: .LBB5_4: ; %bb3270; GCN-NEXT: ;;#ASMSTART271; GCN-NEXT: v_nop_e64272; GCN-NEXT: v_nop_e64273; GCN-NEXT: ;;#ASMEND274; GCN-NEXT: s_sleep 0275; GCN-NEXT: s_sleep 0276; GCN-NEXT: s_cbranch_execnz .LBB5_5277; GCN-NEXT: ; %bb.9: ; %bb3278; GCN-NEXT: s_add_pc_i64 .LBB5_2-.Lpost_addpc7279; GCN-NEXT: .Lpost_addpc7:280; GCN-NEXT: .LBB5_5: ; %bb3281; GCN-NEXT: s_add_pc_i64 .LBB5_3-.Lpost_addpc5282; GCN-NEXT: .Lpost_addpc5:283bb0:284 %tmp = icmp ne i32 %arg1, 0285 br i1 %tmp, label %bb2, label %bb3286 287bb2:288 store volatile i32 17, ptr addrspace(1) poison289 br label %bb4290 291bb3:292 ; 32 byte asm293 call void asm sideeffect294 "v_nop_e64295 v_nop_e64", ""() #0296 call void @llvm.amdgcn.s.sleep(i32 0)297 call void @llvm.amdgcn.s.sleep(i32 0)298 br label %bb4299 300bb4:301 store volatile i32 63, ptr addrspace(1) %arg302 ret void303}304 305define amdgpu_kernel void @uniform_unconditional_min_long_backward_branch(ptr addrspace(1) %arg, i32 %arg1) {306; GCN-LABEL: uniform_unconditional_min_long_backward_branch:307; GCN: ; %bb.0: ; %entry308; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1309; GCN-NEXT: s_mov_b32 vcc_lo, exec_lo310; GCN-NEXT: .LBB6_1: ; %loop311; GCN-NEXT: ; =>This Inner Loop Header: Depth=1312; GCN-NEXT: ;;#ASMSTART313; GCN-NEXT: v_nop_e64314; GCN-NEXT: v_nop_e64315; GCN-NEXT: ;;#ASMEND316; GCN-NEXT: s_sleep 0317; GCN-NEXT: s_sleep 0318; GCN-NEXT: s_cbranch_vccz .LBB6_2319; GCN-NEXT: ; %bb.3: ; %loop320; GCN-NEXT: ; in Loop: Header=BB6_1 Depth=1321; GCN-NEXT: s_add_pc_i64 .LBB6_1-.Lpost_addpc8322; GCN-NEXT: .Lpost_addpc8:323; GCN-NEXT: .LBB6_2: ; %DummyReturnBlock324; GCN-NEXT: s_endpgm325entry:326 br label %loop327 328loop:329 ; 32 byte asm330 call void asm sideeffect331 "v_nop_e64332 v_nop_e64", ""() #0333 call void @llvm.amdgcn.s.sleep(i32 0)334 call void @llvm.amdgcn.s.sleep(i32 0)335 br label %loop336}337 338; Expansion of branch from %bb1 to %bb3 introduces need to expand339; branch from %bb0 to %bb2340 341define amdgpu_kernel void @expand_requires_expand(i32 %cond0) #0 {342; GCN-LABEL: expand_requires_expand:343; GCN: ; %bb.0: ; %bb0344; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1345; GCN-NEXT: s_load_b32 s0, s[4:5], 0x24346; GCN-NEXT: s_wait_kmcnt 0x0347; GCN-NEXT: s_cmp_lt_i32 s0, 0348; GCN-NEXT: s_cselect_b32 s0, -1, 0349; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)350; GCN-NEXT: s_and_b32 vcc_lo, exec_lo, s0351; GCN-NEXT: s_cbranch_vccnz .LBB7_2352; GCN-NEXT: ; %bb.1: ; %bb1353; GCN-NEXT: s_load_b32 s0, s[0:1], 0x0354; GCN-NEXT: s_wait_kmcnt 0x0355; GCN-NEXT: s_cmp_lg_u32 s0, 3356; GCN-NEXT: s_cselect_b32 s0, -1, 0357; GCN-NEXT: .LBB7_2: ; %Flow358; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)359; GCN-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0360; GCN-NEXT: s_cbranch_vccz .LBB7_3361; GCN-NEXT: ; %bb.5: ; %Flow362; GCN-NEXT: s_add_pc_i64 .LBB7_4-.Lpost_addpc9363; GCN-NEXT: .Lpost_addpc9:364; GCN-NEXT: .LBB7_3: ; %bb2365; GCN-NEXT: ;;#ASMSTART366; GCN-NEXT: v_nop_e64367; GCN-NEXT: v_nop_e64368; GCN-NEXT: ;;#ASMEND369; GCN-NEXT: s_sleep 0370; GCN-NEXT: s_sleep 0371; GCN-NEXT: .LBB7_4: ; %bb3372; GCN-NEXT: ;;#ASMSTART373; GCN-NEXT: v_nop_e64374; GCN-NEXT: ;;#ASMEND375; GCN-NEXT: ;;#ASMSTART376; GCN-NEXT: v_nop_e64377; GCN-NEXT: ;;#ASMEND378; GCN-NEXT: s_endpgm379bb0:380 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() #0381 %cmp0 = icmp slt i32 %cond0, 0382 br i1 %cmp0, label %bb2, label %bb1383 384bb1:385 %val = load volatile i32, ptr addrspace(4) poison386 %cmp1 = icmp eq i32 %val, 3387 br i1 %cmp1, label %bb3, label %bb2388 389bb2:390 call void asm sideeffect391 "v_nop_e64392 v_nop_e64", ""() #0393 call void @llvm.amdgcn.s.sleep(i32 0)394 call void @llvm.amdgcn.s.sleep(i32 0)395 br label %bb3396 397bb3:398; These NOPs prevent tail-duplication-based outlining399; from firing, which defeats the need to expand the branches and this test.400 call void asm sideeffect401 "v_nop_e64", ""() #0402 call void asm sideeffect403 "v_nop_e64", ""() #0404 ret void405}406 407; Requires expanding of required skip branch.408 409define amdgpu_kernel void @uniform_inside_divergent(ptr addrspace(1) %out, i32 %cond) #0 {410; GCN-LABEL: uniform_inside_divergent:411; GCN: ; %bb.0: ; %entry412; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1413; GCN-NEXT: v_and_b32_e32 v0, 0x3ff, v0414; GCN-NEXT: s_mov_b32 s3, exec_lo415; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)416; GCN-NEXT: v_cmpx_gt_u32_e32 16, v0417; GCN-NEXT: s_cbranch_execnz .LBB8_1418; GCN-NEXT: ; %bb.4: ; %entry419; GCN-NEXT: s_add_pc_i64 .LBB8_3-.Lpost_addpc10420; GCN-NEXT: .Lpost_addpc10:421; GCN-NEXT: .LBB8_1: ; %if422; GCN-NEXT: s_load_b96 s[0:2], s[4:5], 0x24423; GCN-NEXT: v_mov_b32_e32 v0, 0424; GCN-NEXT: s_wait_kmcnt 0x0425; GCN-NEXT: s_cmp_lg_u32 s2, 0426; GCN-NEXT: global_store_b32 v0, v0, s[0:1]427; GCN-NEXT: s_cbranch_scc1 .LBB8_3428; GCN-NEXT: ; %bb.2: ; %if_uniform429; GCN-NEXT: v_mov_b32_e32 v1, 1430; GCN-NEXT: global_store_b32 v0, v1, s[0:1]431; GCN-NEXT: .LBB8_3: ; %endif432; GCN-NEXT: s_wait_xcnt 0x0433; GCN-NEXT: s_or_b32 exec_lo, exec_lo, s3434; GCN-NEXT: s_sleep 5435; GCN-NEXT: s_endpgm436entry:437 %tid = call i32 @llvm.amdgcn.workitem.id.x()438 %d_cmp = icmp ult i32 %tid, 16439 br i1 %d_cmp, label %if, label %endif440 441if:442 store i32 0, ptr addrspace(1) %out443 %u_cmp = icmp eq i32 %cond, 0444 br i1 %u_cmp, label %if_uniform, label %endif445 446if_uniform:447 store i32 1, ptr addrspace(1) %out448 br label %endif449 450endif:451 ; layout can remove the split branch if it can copy the return block.452 ; This call makes the return block long enough that it doesn't get copied.453 call void @llvm.amdgcn.s.sleep(i32 5);454 ret void455}456 457; si_mask_branch458 459define amdgpu_kernel void @analyze_mask_branch() #0 {460; GCN-LABEL: analyze_mask_branch:461; GCN: ; %bb.0: ; %entry462; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1463; GCN-NEXT: s_mov_b32 s0, exec_lo464; GCN-NEXT: ;;#ASMSTART465; GCN-NEXT: v_mov_b32_e64 v0, 0466; GCN-NEXT: ;;#ASMEND467; GCN-NEXT: v_cmpx_nlt_f32_e32 0, v0468; GCN-NEXT: s_xor_b32 s0, exec_lo, s0469; GCN-NEXT: s_cbranch_execz .LBB9_2470; GCN-NEXT: ; %bb.1: ; %ret471; GCN-NEXT: v_mov_b32_e32 v0, 7472; GCN-NEXT: global_store_b32 v[0:1], v0, off scope:SCOPE_SYS473; GCN-NEXT: s_wait_storecnt 0x0474; GCN-NEXT: .LBB9_2: ; %Flow1475; GCN-NEXT: s_wait_xcnt 0x0476; GCN-NEXT: s_and_not1_saveexec_b32 s0, s0477; GCN-NEXT: s_cbranch_execnz .LBB9_3478; GCN-NEXT: ; %bb.6: ; %Flow1479; GCN-NEXT: s_add_pc_i64 .LBB9_5-.Lpost_addpc11480; GCN-NEXT: .Lpost_addpc11:481; GCN-NEXT: .LBB9_3: ; %loop.preheader482; GCN-NEXT: s_mov_b32 vcc_lo, 0483; GCN-NEXT: .LBB9_4: ; %loop484; GCN-NEXT: ; =>This Inner Loop Header: Depth=1485; GCN-NEXT: ;;#ASMSTART486; GCN-NEXT: v_nop_e64487; GCN-NEXT: ;;#ASMEND488; GCN-NEXT: s_sleep 0489; GCN-NEXT: ;;#ASMSTART490; GCN-NEXT: v_nop_e64491; GCN-NEXT: v_nop_e64492; GCN-NEXT: ;;#ASMEND493; GCN-NEXT: s_sleep 0494; GCN-NEXT: s_sleep 0495; GCN-NEXT: s_cbranch_vccnz .LBB9_5496; GCN-NEXT: ; %bb.8: ; %loop497; GCN-NEXT: ; in Loop: Header=BB9_4 Depth=1498; GCN-NEXT: s_add_pc_i64 .LBB9_4-.Lpost_addpc12499; GCN-NEXT: .Lpost_addpc12:500; GCN-NEXT: .LBB9_5: ; %UnifiedReturnBlock501; GCN-NEXT: s_endpgm502entry:503 %reg = call float asm sideeffect "v_mov_b32_e64 $0, 0", "=v"()504 %cmp0 = fcmp ogt float %reg, 0.000000e+00505 br i1 %cmp0, label %loop, label %ret506 507loop:508 %phi = phi float [ 0.000000e+00, %loop_body ], [ 1.000000e+00, %entry ]509 call void asm sideeffect510 "v_nop_e64", ""() #0511 call void @llvm.amdgcn.s.sleep(i32 0)512 %cmp1 = fcmp olt float %phi, 8.0513 br i1 %cmp1, label %loop_body, label %ret514 515loop_body:516 call void asm sideeffect517 "v_nop_e64518 v_nop_e64", ""() #0519 call void @llvm.amdgcn.s.sleep(i32 0)520 call void @llvm.amdgcn.s.sleep(i32 0)521 br label %loop522 523ret:524 store volatile i32 7, ptr addrspace(1) poison525 ret void526}527 528define amdgpu_kernel void @long_branch_hang(ptr addrspace(1) nocapture %arg, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i64 %arg5) #0 {529; GCN-LABEL: long_branch_hang:530; GCN: ; %bb.0: ; %bb531; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1532; GCN-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c533; GCN-NEXT: s_mov_b32 s7, -1534; GCN-NEXT: s_wait_kmcnt 0x0535; GCN-NEXT: s_cmp_eq_u32 s0, 0536; GCN-NEXT: s_cselect_b32 s6, -1, 0537; GCN-NEXT: s_cmp_lg_u32 s0, 0538; GCN-NEXT: s_mov_b32 s0, 0539; GCN-NEXT: s_cselect_b32 s8, -1, 0540; GCN-NEXT: s_cmp_lt_i32 s3, 6541; GCN-NEXT: s_cbranch_scc0 .LBB10_1542; GCN-NEXT: ; %bb.10: ; %bb543; GCN-NEXT: s_add_pc_i64 .LBB10_4-.Lpost_addpc14544; GCN-NEXT: .Lpost_addpc14:545; GCN-NEXT: .LBB10_1: ; %Flow546; GCN-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s7547; GCN-NEXT: s_cbranch_vccnz .LBB10_2548; GCN-NEXT: ; %bb.12: ; %Flow549; GCN-NEXT: s_add_pc_i64 .LBB10_5-.Lpost_addpc15550; GCN-NEXT: .Lpost_addpc15:551; GCN-NEXT: .LBB10_2: ; %Flow5552; GCN-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0553; GCN-NEXT: s_cbranch_vccz .LBB10_3554; GCN-NEXT: ; %bb.14: ; %Flow5555; GCN-NEXT: s_add_pc_i64 .LBB10_6-.Lpost_addpc16556; GCN-NEXT: .Lpost_addpc16:557; GCN-NEXT: .LBB10_3: ; %bb14558; GCN-NEXT: s_cmp_lt_i32 s1, 9559; GCN-NEXT: s_cselect_b32 s0, -1, 0560; GCN-NEXT: s_cmp_lt_i32 s2, s3561; GCN-NEXT: s_cselect_b32 s1, -1, 0562; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)563; GCN-NEXT: s_or_b32 s0, s1, s0564; GCN-NEXT: s_and_b32 s0, s6, s0565; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)566; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0567; GCN-NEXT: ; %bb.8: ; %bb14568; GCN-NEXT: s_add_pc_i64 .LBB10_7-.Lpost_addpc13569; GCN-NEXT: .Lpost_addpc13:570; GCN-NEXT: .LBB10_4: ; %bb13571; GCN-NEXT: ;;#ASMSTART572; GCN-NEXT: v_nop_e64573; GCN-NEXT: v_nop_e64574; GCN-NEXT: ;;#ASMEND575; GCN-NEXT: s_sleep 0576; GCN-NEXT: s_mov_b32 s0, s8577; GCN-NEXT: s_sleep 0578; GCN-NEXT: s_cbranch_execz .LBB10_5579; GCN-NEXT: ; %bb.16: ; %bb13580; GCN-NEXT: s_add_pc_i64 .LBB10_2-.Lpost_addpc17581; GCN-NEXT: .Lpost_addpc17:582; GCN-NEXT: .LBB10_5: ; %bb9583; GCN-NEXT: s_cmp_lt_i32 s3, 11584; GCN-NEXT: s_cselect_b32 s0, -1, 0585; GCN-NEXT: s_cmp_ge_i32 s2, s3586; GCN-NEXT: s_cselect_b32 s7, -1, 0587; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)588; GCN-NEXT: s_and_b32 s0, s7, s0589; GCN-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0590; GCN-NEXT: s_cbranch_vccnz .LBB10_6591; GCN-NEXT: ; %bb.18: ; %bb9592; GCN-NEXT: s_add_pc_i64 .LBB10_3-.Lpost_addpc18593; GCN-NEXT: .Lpost_addpc18:594; GCN-NEXT: .LBB10_6:595; GCN-NEXT: ; implicit-def: $vgpr0596; GCN-NEXT: .LBB10_7: ; %bb19597; GCN-NEXT: s_clause 0x1598; GCN-NEXT: s_load_b64 s[0:1], s[4:5], 0x3c599; GCN-NEXT: s_load_b64 s[2:3], s[4:5], 0x24600; GCN-NEXT: v_mov_b32_e32 v1, 0601; GCN-NEXT: s_wait_kmcnt 0x0602; GCN-NEXT: s_lshl_b64 s[0:1], s[0:1], 2603; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)604; GCN-NEXT: s_add_nc_u64 s[0:1], s[2:3], s[0:1]605; GCN-NEXT: global_store_b32 v1, v0, s[0:1]606; GCN-NEXT: s_endpgm607bb:608 %tmp = icmp slt i32 %arg2, 9609 %tmp6 = icmp eq i32 %arg1, 0610 %tmp8 = icmp sgt i32 %arg4, 5611 br i1 %tmp8, label %bb9, label %bb13612 613bb9: ; preds = %bb614 %tmp7 = icmp sgt i32 %arg4, 10 ; avoid being optimized away through the domination615 %tmp11 = icmp slt i32 %arg3, %arg4616 %tmp12 = or i1 %tmp11, %tmp7617 br i1 %tmp12, label %bb19, label %bb14618 619bb13: ; preds = %bb620 call void asm sideeffect621 "v_nop_e64622 v_nop_e64", ""() #0623 call void @llvm.amdgcn.s.sleep(i32 0)624 call void @llvm.amdgcn.s.sleep(i32 0)625 br i1 %tmp6, label %bb19, label %bb14626 627bb14: ; preds = %bb13, %bb9628 %tmp15 = icmp slt i32 %arg3, %arg4629 %tmp16 = or i1 %tmp15, %tmp630 %tmp17 = and i1 %tmp6, %tmp16631 %tmp18 = zext i1 %tmp17 to i32632 br label %bb19633 634bb19: ; preds = %bb14, %bb13, %bb9635 %tmp20 = phi i32 [ poison, %bb9 ], [ poison, %bb13 ], [ %tmp18, %bb14 ]636 %tmp21 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 %arg5637 store i32 %tmp20, ptr addrspace(1) %tmp21, align 4638 ret void639}640 641attributes #0 = { nounwind }642attributes #1 = { nounwind readnone }643