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1; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -amdgpu-s-branch-bits=4 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX10 %s2; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -amdgpu-s-branch-bits=4 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s3; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-s-branch-bits=4 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX10 %s4 5; Make sure the code size estimate for inline asm is 12-bytes per6; instruction, rather than 8 in previous generations.7 8; GCN-LABEL: {{^}}long_forward_branch_gfx10only:9; GFX9: s_cmp_eq_u3210; GFX9-NEXT: s_cbranch_scc111 12; GFX10: s_cmp_eq_u3213; GFX10-NEXT: s_cbranch_scc014; GFX10: s_getpc_b6415; GFX10: s_add_u3216; GFX10: s_addc_u3217; GFX10: s_setpc_b6418define amdgpu_kernel void @long_forward_branch_gfx10only(ptr addrspace(1) %arg, i32 %cnd) #0 {19bb0:20 %cmp = icmp eq i32 %cnd, 021 br i1 %cmp, label %bb3, label %bb2 ; +9 dword branch22 23bb2:24 ; Estimated as 40-bytes on gfx10 (requiring a long branch), but25 ; 16-bytes on gfx9 (allowing a short branch)26 call void asm sideeffect27 "v_nop_e6428 v_nop_e64", ""() #029 br label %bb330 31bb3:32 store volatile i32 %cnd, ptr addrspace(1) %arg33 ret void34}35