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1; RUN: llc -mtriple=amdgcn < %s | FileCheck %s2 3; The branch instruction in LOOP49 has a uniform condition, but PHI instructions4; introduced by the structurizecfg pass previously caused a false divergence5; which ended up in an assertion (or incorrect code) because6; SIAnnotateControlFlow and structurizecfg had different ideas about which7; branches are uniform.8;9; CHECK-LABEL: {{^}}main:10; CHECK: ; %LOOP4911; CHECK: s_cmp_{{lg|eq}}_u32 s{{[0-9]+}}, 012; CHECK: s_cbranch_scc{{[0-1]}}13; CHECK: ; %ENDIF5314define amdgpu_vs float @main(i32 %in) {15main_body:16 %cmp = mul i32 %in, 217 br label %LOOP18 19LOOP: ; preds = %ENDLOOP48, %main_body20 %counter = phi i32 [ 0, %main_body ], [ %counter.next, %ENDLOOP48 ]21 %v.LOOP = phi i32 [ 0, %main_body ], [ %v.ENDLOOP48, %ENDLOOP48 ]22 %tmp7 = icmp slt i32 %cmp, %counter23 br i1 %tmp7, label %IF, label %LOOP4924 25IF: ; preds = %LOOP26 %r = bitcast i32 %v.LOOP to float27 ret float %r28 29LOOP49: ; preds = %LOOP30 %tmp8 = icmp ne i32 %counter, 031 br i1 %tmp8, label %ENDLOOP48, label %ENDIF5332 33ENDLOOP48: ; preds = %ENDIF53, %LOOP4934 %v.ENDLOOP48 = phi i32 [ %v.LOOP, %LOOP49 ], [ %v.ENDIF53, %ENDIF53 ]35 %counter.next = add i32 %counter, 136 br label %LOOP37 38ENDIF53: ; preds = %LOOP4939 %v.ENDIF53 = add i32 %v.LOOP, %counter40 br label %ENDLOOP4841}42