765 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=amdgcn-- | FileCheck %s --check-prefix=SI3; RUN: llc < %s -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global | FileCheck %s --check-prefix=VI4; RUN: llc < %s -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=-flat-for-global,+real-true16 | FileCheck %s --check-prefixes=GFX11,GFX11-REAL165; RUN: llc < %s -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=-flat-for-global,-real-true16 | FileCheck %s --check-prefixes=GFX11,GFX11-FAKE166 7declare i16 @llvm.bswap.i16(i16) nounwind readnone8declare <2 x i16> @llvm.bswap.v2i16(<2 x i16>) nounwind readnone9declare <3 x i16> @llvm.bswap.v3i16(<3 x i16>) nounwind readnone10declare <4 x i16> @llvm.bswap.v4i16(<4 x i16>) nounwind readnone11declare i32 @llvm.bswap.i32(i32) nounwind readnone12declare <2 x i32> @llvm.bswap.v2i32(<2 x i32>) nounwind readnone13declare <4 x i32> @llvm.bswap.v4i32(<4 x i32>) nounwind readnone14declare <8 x i32> @llvm.bswap.v8i32(<8 x i32>) nounwind readnone15declare i64 @llvm.bswap.i64(i64) nounwind readnone16declare <2 x i64> @llvm.bswap.v2i64(<2 x i64>) nounwind readnone17declare <4 x i64> @llvm.bswap.v4i64(<4 x i64>) nounwind readnone18declare i48 @llvm.bswap.i48(i48) #119 20define amdgpu_kernel void @test_bswap_i32(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind {21; SI-LABEL: test_bswap_i32:22; SI: ; %bb.0:23; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x924; SI-NEXT: s_waitcnt lgkmcnt(0)25; SI-NEXT: s_load_dword s4, s[2:3], 0x026; SI-NEXT: s_mov_b32 s3, 0xf00027; SI-NEXT: s_mov_b32 s2, -128; SI-NEXT: s_waitcnt lgkmcnt(0)29; SI-NEXT: v_alignbit_b32 v0, s4, s4, 830; SI-NEXT: v_alignbit_b32 v1, s4, s4, 2431; SI-NEXT: s_mov_b32 s4, 0xff00ff32; SI-NEXT: v_bfi_b32 v0, s4, v1, v033; SI-NEXT: buffer_store_dword v0, off, s[0:3], 034; SI-NEXT: s_endpgm35;36; VI-LABEL: test_bswap_i32:37; VI: ; %bb.0:38; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2439; VI-NEXT: v_mov_b32_e32 v0, 0x1020340; VI-NEXT: s_mov_b32 s7, 0xf00041; VI-NEXT: s_mov_b32 s6, -142; VI-NEXT: s_waitcnt lgkmcnt(0)43; VI-NEXT: s_load_dword s2, s[2:3], 0x044; VI-NEXT: s_mov_b32 s4, s045; VI-NEXT: s_mov_b32 s5, s146; VI-NEXT: s_waitcnt lgkmcnt(0)47; VI-NEXT: v_perm_b32 v0, 0, s2, v048; VI-NEXT: buffer_store_dword v0, off, s[4:7], 049; VI-NEXT: s_endpgm50;51; GFX11-LABEL: test_bswap_i32:52; GFX11: ; %bb.0:53; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x2454; GFX11-NEXT: s_waitcnt lgkmcnt(0)55; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x056; GFX11-NEXT: s_mov_b32 s3, 0x3101600057; GFX11-NEXT: s_waitcnt lgkmcnt(0)58; GFX11-NEXT: v_perm_b32 v0, 0, s2, 0x1020359; GFX11-NEXT: s_mov_b32 s2, -160; GFX11-NEXT: buffer_store_b32 v0, off, s[0:3], 061; GFX11-NEXT: s_endpgm62 %val = load i32, ptr addrspace(1) %in, align 463 %bswap = call i32 @llvm.bswap.i32(i32 %val) nounwind readnone64 store i32 %bswap, ptr addrspace(1) %out, align 465 ret void66}67 68define amdgpu_kernel void @test_bswap_v2i32(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind {69; SI-LABEL: test_bswap_v2i32:70; SI: ; %bb.0:71; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x972; SI-NEXT: s_waitcnt lgkmcnt(0)73; SI-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x074; SI-NEXT: s_mov_b32 s3, 0xf00075; SI-NEXT: s_mov_b32 s2, -176; SI-NEXT: s_mov_b32 s6, 0xff00ff77; SI-NEXT: s_waitcnt lgkmcnt(0)78; SI-NEXT: v_alignbit_b32 v0, s5, s5, 879; SI-NEXT: v_alignbit_b32 v1, s5, s5, 2480; SI-NEXT: v_alignbit_b32 v2, s4, s4, 881; SI-NEXT: v_alignbit_b32 v3, s4, s4, 2482; SI-NEXT: v_bfi_b32 v1, s6, v1, v083; SI-NEXT: v_bfi_b32 v0, s6, v3, v284; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 085; SI-NEXT: s_endpgm86;87; VI-LABEL: test_bswap_v2i32:88; VI: ; %bb.0:89; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2490; VI-NEXT: v_mov_b32_e32 v0, 0x1020391; VI-NEXT: s_mov_b32 s7, 0xf00092; VI-NEXT: s_mov_b32 s6, -193; VI-NEXT: s_waitcnt lgkmcnt(0)94; VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x095; VI-NEXT: s_mov_b32 s4, s096; VI-NEXT: s_mov_b32 s5, s197; VI-NEXT: s_waitcnt lgkmcnt(0)98; VI-NEXT: v_perm_b32 v1, 0, s3, v099; VI-NEXT: v_perm_b32 v0, 0, s2, v0100; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0101; VI-NEXT: s_endpgm102;103; GFX11-LABEL: test_bswap_v2i32:104; GFX11: ; %bb.0:105; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24106; GFX11-NEXT: s_waitcnt lgkmcnt(0)107; GFX11-NEXT: s_load_b64 s[4:5], s[2:3], 0x0108; GFX11-NEXT: s_mov_b32 s3, 0x31016000109; GFX11-NEXT: s_mov_b32 s2, -1110; GFX11-NEXT: s_waitcnt lgkmcnt(0)111; GFX11-NEXT: v_perm_b32 v1, 0, s5, 0x10203112; GFX11-NEXT: v_perm_b32 v0, 0, s4, 0x10203113; GFX11-NEXT: buffer_store_b64 v[0:1], off, s[0:3], 0114; GFX11-NEXT: s_endpgm115 %val = load <2 x i32>, ptr addrspace(1) %in, align 8116 %bswap = call <2 x i32> @llvm.bswap.v2i32(<2 x i32> %val) nounwind readnone117 store <2 x i32> %bswap, ptr addrspace(1) %out, align 8118 ret void119}120 121define amdgpu_kernel void @test_bswap_v4i32(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind {122; SI-LABEL: test_bswap_v4i32:123; SI: ; %bb.0:124; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9125; SI-NEXT: s_waitcnt lgkmcnt(0)126; SI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0127; SI-NEXT: s_mov_b32 s3, 0xf000128; SI-NEXT: s_mov_b32 s2, -1129; SI-NEXT: s_mov_b32 s8, 0xff00ff130; SI-NEXT: s_waitcnt lgkmcnt(0)131; SI-NEXT: v_alignbit_b32 v0, s7, s7, 8132; SI-NEXT: v_alignbit_b32 v1, s7, s7, 24133; SI-NEXT: v_alignbit_b32 v2, s6, s6, 8134; SI-NEXT: v_alignbit_b32 v4, s6, s6, 24135; SI-NEXT: v_alignbit_b32 v5, s5, s5, 8136; SI-NEXT: v_alignbit_b32 v6, s5, s5, 24137; SI-NEXT: v_alignbit_b32 v7, s4, s4, 8138; SI-NEXT: v_alignbit_b32 v8, s4, s4, 24139; SI-NEXT: v_bfi_b32 v3, s8, v1, v0140; SI-NEXT: v_bfi_b32 v2, s8, v4, v2141; SI-NEXT: v_bfi_b32 v1, s8, v6, v5142; SI-NEXT: v_bfi_b32 v0, s8, v8, v7143; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0144; SI-NEXT: s_endpgm145;146; VI-LABEL: test_bswap_v4i32:147; VI: ; %bb.0:148; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24149; VI-NEXT: v_mov_b32_e32 v0, 0x10203150; VI-NEXT: s_mov_b32 s7, 0xf000151; VI-NEXT: s_mov_b32 s6, -1152; VI-NEXT: s_waitcnt lgkmcnt(0)153; VI-NEXT: s_load_dwordx4 s[8:11], s[2:3], 0x0154; VI-NEXT: s_mov_b32 s4, s0155; VI-NEXT: s_mov_b32 s5, s1156; VI-NEXT: s_waitcnt lgkmcnt(0)157; VI-NEXT: v_perm_b32 v3, 0, s11, v0158; VI-NEXT: v_perm_b32 v2, 0, s10, v0159; VI-NEXT: v_perm_b32 v1, 0, s9, v0160; VI-NEXT: v_perm_b32 v0, 0, s8, v0161; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0162; VI-NEXT: s_endpgm163;164; GFX11-LABEL: test_bswap_v4i32:165; GFX11: ; %bb.0:166; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24167; GFX11-NEXT: s_waitcnt lgkmcnt(0)168; GFX11-NEXT: s_load_b128 s[4:7], s[2:3], 0x0169; GFX11-NEXT: s_mov_b32 s3, 0x31016000170; GFX11-NEXT: s_mov_b32 s2, -1171; GFX11-NEXT: s_waitcnt lgkmcnt(0)172; GFX11-NEXT: v_perm_b32 v3, 0, s7, 0x10203173; GFX11-NEXT: v_perm_b32 v2, 0, s6, 0x10203174; GFX11-NEXT: v_perm_b32 v1, 0, s5, 0x10203175; GFX11-NEXT: v_perm_b32 v0, 0, s4, 0x10203176; GFX11-NEXT: buffer_store_b128 v[0:3], off, s[0:3], 0177; GFX11-NEXT: s_endpgm178 %val = load <4 x i32>, ptr addrspace(1) %in, align 16179 %bswap = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %val) nounwind readnone180 store <4 x i32> %bswap, ptr addrspace(1) %out, align 16181 ret void182}183 184define amdgpu_kernel void @test_bswap_v8i32(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind {185; SI-LABEL: test_bswap_v8i32:186; SI: ; %bb.0:187; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9188; SI-NEXT: s_waitcnt lgkmcnt(0)189; SI-NEXT: s_load_dwordx8 s[4:11], s[2:3], 0x0190; SI-NEXT: s_mov_b32 s3, 0xf000191; SI-NEXT: s_mov_b32 s2, -1192; SI-NEXT: s_mov_b32 s12, 0xff00ff193; SI-NEXT: s_waitcnt lgkmcnt(0)194; SI-NEXT: v_alignbit_b32 v0, s7, s7, 8195; SI-NEXT: v_alignbit_b32 v1, s7, s7, 24196; SI-NEXT: v_alignbit_b32 v2, s6, s6, 8197; SI-NEXT: v_alignbit_b32 v4, s6, s6, 24198; SI-NEXT: v_alignbit_b32 v5, s5, s5, 8199; SI-NEXT: v_alignbit_b32 v6, s5, s5, 24200; SI-NEXT: v_alignbit_b32 v7, s4, s4, 8201; SI-NEXT: v_alignbit_b32 v8, s4, s4, 24202; SI-NEXT: v_alignbit_b32 v9, s11, s11, 8203; SI-NEXT: v_alignbit_b32 v10, s11, s11, 24204; SI-NEXT: v_alignbit_b32 v11, s10, s10, 8205; SI-NEXT: v_alignbit_b32 v12, s10, s10, 24206; SI-NEXT: v_alignbit_b32 v13, s9, s9, 8207; SI-NEXT: v_alignbit_b32 v14, s9, s9, 24208; SI-NEXT: v_alignbit_b32 v15, s8, s8, 8209; SI-NEXT: v_alignbit_b32 v16, s8, s8, 24210; SI-NEXT: v_bfi_b32 v3, s12, v1, v0211; SI-NEXT: v_bfi_b32 v2, s12, v4, v2212; SI-NEXT: v_bfi_b32 v1, s12, v6, v5213; SI-NEXT: v_bfi_b32 v0, s12, v8, v7214; SI-NEXT: v_bfi_b32 v7, s12, v10, v9215; SI-NEXT: v_bfi_b32 v6, s12, v12, v11216; SI-NEXT: v_bfi_b32 v5, s12, v14, v13217; SI-NEXT: v_bfi_b32 v4, s12, v16, v15218; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16219; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0220; SI-NEXT: s_endpgm221;222; VI-LABEL: test_bswap_v8i32:223; VI: ; %bb.0:224; VI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x24225; VI-NEXT: v_mov_b32_e32 v4, 0x10203226; VI-NEXT: s_mov_b32 s15, 0xf000227; VI-NEXT: s_mov_b32 s14, -1228; VI-NEXT: s_waitcnt lgkmcnt(0)229; VI-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0230; VI-NEXT: s_mov_b32 s12, s8231; VI-NEXT: s_mov_b32 s13, s9232; VI-NEXT: s_waitcnt lgkmcnt(0)233; VI-NEXT: v_perm_b32 v3, 0, s3, v4234; VI-NEXT: v_perm_b32 v2, 0, s2, v4235; VI-NEXT: v_perm_b32 v1, 0, s1, v4236; VI-NEXT: v_perm_b32 v0, 0, s0, v4237; VI-NEXT: v_perm_b32 v7, 0, s7, v4238; VI-NEXT: v_perm_b32 v6, 0, s6, v4239; VI-NEXT: v_perm_b32 v5, 0, s5, v4240; VI-NEXT: v_perm_b32 v4, 0, s4, v4241; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[12:15], 0 offset:16242; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[12:15], 0243; VI-NEXT: s_endpgm244;245; GFX11-LABEL: test_bswap_v8i32:246; GFX11: ; %bb.0:247; GFX11-NEXT: s_load_b128 s[8:11], s[4:5], 0x24248; GFX11-NEXT: s_waitcnt lgkmcnt(0)249; GFX11-NEXT: s_load_b256 s[0:7], s[10:11], 0x0250; GFX11-NEXT: s_mov_b32 s11, 0x31016000251; GFX11-NEXT: s_mov_b32 s10, -1252; GFX11-NEXT: s_waitcnt lgkmcnt(0)253; GFX11-NEXT: v_perm_b32 v7, 0, s7, 0x10203254; GFX11-NEXT: v_perm_b32 v6, 0, s6, 0x10203255; GFX11-NEXT: v_perm_b32 v5, 0, s5, 0x10203256; GFX11-NEXT: v_perm_b32 v4, 0, s4, 0x10203257; GFX11-NEXT: v_perm_b32 v3, 0, s3, 0x10203258; GFX11-NEXT: v_perm_b32 v2, 0, s2, 0x10203259; GFX11-NEXT: v_perm_b32 v1, 0, s1, 0x10203260; GFX11-NEXT: v_perm_b32 v0, 0, s0, 0x10203261; GFX11-NEXT: s_clause 0x1262; GFX11-NEXT: buffer_store_b128 v[4:7], off, s[8:11], 0 offset:16263; GFX11-NEXT: buffer_store_b128 v[0:3], off, s[8:11], 0264; GFX11-NEXT: s_endpgm265 %val = load <8 x i32>, ptr addrspace(1) %in, align 32266 %bswap = call <8 x i32> @llvm.bswap.v8i32(<8 x i32> %val) nounwind readnone267 store <8 x i32> %bswap, ptr addrspace(1) %out, align 32268 ret void269}270 271define amdgpu_kernel void @test_bswap_i64(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind {272; SI-LABEL: test_bswap_i64:273; SI: ; %bb.0:274; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9275; SI-NEXT: s_waitcnt lgkmcnt(0)276; SI-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0277; SI-NEXT: s_mov_b32 s3, 0xf000278; SI-NEXT: s_mov_b32 s2, -1279; SI-NEXT: s_mov_b32 s6, 0xff00ff280; SI-NEXT: s_waitcnt lgkmcnt(0)281; SI-NEXT: v_alignbit_b32 v0, s4, s4, 8282; SI-NEXT: v_alignbit_b32 v1, s4, s4, 24283; SI-NEXT: v_alignbit_b32 v2, s5, s5, 8284; SI-NEXT: v_alignbit_b32 v3, s5, s5, 24285; SI-NEXT: v_bfi_b32 v1, s6, v1, v0286; SI-NEXT: v_bfi_b32 v0, s6, v3, v2287; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0288; SI-NEXT: s_endpgm289;290; VI-LABEL: test_bswap_i64:291; VI: ; %bb.0:292; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24293; VI-NEXT: v_mov_b32_e32 v0, 0x10203294; VI-NEXT: s_mov_b32 s7, 0xf000295; VI-NEXT: s_mov_b32 s6, -1296; VI-NEXT: s_waitcnt lgkmcnt(0)297; VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0298; VI-NEXT: s_mov_b32 s4, s0299; VI-NEXT: s_mov_b32 s5, s1300; VI-NEXT: s_waitcnt lgkmcnt(0)301; VI-NEXT: v_perm_b32 v1, 0, s2, v0302; VI-NEXT: v_perm_b32 v0, 0, s3, v0303; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0304; VI-NEXT: s_endpgm305;306; GFX11-LABEL: test_bswap_i64:307; GFX11: ; %bb.0:308; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24309; GFX11-NEXT: s_waitcnt lgkmcnt(0)310; GFX11-NEXT: s_load_b64 s[4:5], s[2:3], 0x0311; GFX11-NEXT: s_mov_b32 s3, 0x31016000312; GFX11-NEXT: s_mov_b32 s2, -1313; GFX11-NEXT: s_waitcnt lgkmcnt(0)314; GFX11-NEXT: v_perm_b32 v1, 0, s4, 0x10203315; GFX11-NEXT: v_perm_b32 v0, 0, s5, 0x10203316; GFX11-NEXT: buffer_store_b64 v[0:1], off, s[0:3], 0317; GFX11-NEXT: s_endpgm318 %val = load i64, ptr addrspace(1) %in, align 8319 %bswap = call i64 @llvm.bswap.i64(i64 %val) nounwind readnone320 store i64 %bswap, ptr addrspace(1) %out, align 8321 ret void322}323 324define amdgpu_kernel void @test_bswap_v2i64(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind {325; SI-LABEL: test_bswap_v2i64:326; SI: ; %bb.0:327; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9328; SI-NEXT: s_waitcnt lgkmcnt(0)329; SI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0330; SI-NEXT: s_mov_b32 s3, 0xf000331; SI-NEXT: s_mov_b32 s2, -1332; SI-NEXT: s_mov_b32 s8, 0xff00ff333; SI-NEXT: s_waitcnt lgkmcnt(0)334; SI-NEXT: v_alignbit_b32 v0, s6, s6, 8335; SI-NEXT: v_alignbit_b32 v1, s6, s6, 24336; SI-NEXT: v_alignbit_b32 v2, s7, s7, 8337; SI-NEXT: v_alignbit_b32 v4, s7, s7, 24338; SI-NEXT: v_alignbit_b32 v5, s4, s4, 8339; SI-NEXT: v_alignbit_b32 v6, s4, s4, 24340; SI-NEXT: v_alignbit_b32 v7, s5, s5, 8341; SI-NEXT: v_alignbit_b32 v8, s5, s5, 24342; SI-NEXT: v_bfi_b32 v3, s8, v1, v0343; SI-NEXT: v_bfi_b32 v2, s8, v4, v2344; SI-NEXT: v_bfi_b32 v1, s8, v6, v5345; SI-NEXT: v_bfi_b32 v0, s8, v8, v7346; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0347; SI-NEXT: s_endpgm348;349; VI-LABEL: test_bswap_v2i64:350; VI: ; %bb.0:351; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24352; VI-NEXT: v_mov_b32_e32 v0, 0x10203353; VI-NEXT: s_mov_b32 s7, 0xf000354; VI-NEXT: s_mov_b32 s6, -1355; VI-NEXT: s_waitcnt lgkmcnt(0)356; VI-NEXT: s_load_dwordx4 s[8:11], s[2:3], 0x0357; VI-NEXT: s_mov_b32 s4, s0358; VI-NEXT: s_mov_b32 s5, s1359; VI-NEXT: s_waitcnt lgkmcnt(0)360; VI-NEXT: v_perm_b32 v3, 0, s10, v0361; VI-NEXT: v_perm_b32 v2, 0, s11, v0362; VI-NEXT: v_perm_b32 v1, 0, s8, v0363; VI-NEXT: v_perm_b32 v0, 0, s9, v0364; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0365; VI-NEXT: s_endpgm366;367; GFX11-LABEL: test_bswap_v2i64:368; GFX11: ; %bb.0:369; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24370; GFX11-NEXT: s_waitcnt lgkmcnt(0)371; GFX11-NEXT: s_load_b128 s[4:7], s[2:3], 0x0372; GFX11-NEXT: s_mov_b32 s3, 0x31016000373; GFX11-NEXT: s_mov_b32 s2, -1374; GFX11-NEXT: s_waitcnt lgkmcnt(0)375; GFX11-NEXT: v_perm_b32 v3, 0, s6, 0x10203376; GFX11-NEXT: v_perm_b32 v2, 0, s7, 0x10203377; GFX11-NEXT: v_perm_b32 v1, 0, s4, 0x10203378; GFX11-NEXT: v_perm_b32 v0, 0, s5, 0x10203379; GFX11-NEXT: buffer_store_b128 v[0:3], off, s[0:3], 0380; GFX11-NEXT: s_endpgm381 %val = load <2 x i64>, ptr addrspace(1) %in, align 16382 %bswap = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %val) nounwind readnone383 store <2 x i64> %bswap, ptr addrspace(1) %out, align 16384 ret void385}386 387define amdgpu_kernel void @test_bswap_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind {388; SI-LABEL: test_bswap_v4i64:389; SI: ; %bb.0:390; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9391; SI-NEXT: s_waitcnt lgkmcnt(0)392; SI-NEXT: s_load_dwordx8 s[4:11], s[2:3], 0x0393; SI-NEXT: s_mov_b32 s3, 0xf000394; SI-NEXT: s_mov_b32 s2, -1395; SI-NEXT: s_mov_b32 s12, 0xff00ff396; SI-NEXT: s_waitcnt lgkmcnt(0)397; SI-NEXT: v_alignbit_b32 v0, s6, s6, 8398; SI-NEXT: v_alignbit_b32 v1, s6, s6, 24399; SI-NEXT: v_alignbit_b32 v2, s7, s7, 8400; SI-NEXT: v_alignbit_b32 v4, s7, s7, 24401; SI-NEXT: v_alignbit_b32 v5, s4, s4, 8402; SI-NEXT: v_alignbit_b32 v6, s4, s4, 24403; SI-NEXT: v_alignbit_b32 v7, s5, s5, 8404; SI-NEXT: v_alignbit_b32 v8, s5, s5, 24405; SI-NEXT: v_alignbit_b32 v9, s10, s10, 8406; SI-NEXT: v_alignbit_b32 v10, s10, s10, 24407; SI-NEXT: v_alignbit_b32 v11, s11, s11, 8408; SI-NEXT: v_alignbit_b32 v12, s11, s11, 24409; SI-NEXT: v_alignbit_b32 v13, s8, s8, 8410; SI-NEXT: v_alignbit_b32 v14, s8, s8, 24411; SI-NEXT: v_alignbit_b32 v15, s9, s9, 8412; SI-NEXT: v_alignbit_b32 v16, s9, s9, 24413; SI-NEXT: v_bfi_b32 v3, s12, v1, v0414; SI-NEXT: v_bfi_b32 v2, s12, v4, v2415; SI-NEXT: v_bfi_b32 v1, s12, v6, v5416; SI-NEXT: v_bfi_b32 v0, s12, v8, v7417; SI-NEXT: v_bfi_b32 v7, s12, v10, v9418; SI-NEXT: v_bfi_b32 v6, s12, v12, v11419; SI-NEXT: v_bfi_b32 v5, s12, v14, v13420; SI-NEXT: v_bfi_b32 v4, s12, v16, v15421; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16422; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0423; SI-NEXT: s_endpgm424;425; VI-LABEL: test_bswap_v4i64:426; VI: ; %bb.0:427; VI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x24428; VI-NEXT: v_mov_b32_e32 v4, 0x10203429; VI-NEXT: s_mov_b32 s15, 0xf000430; VI-NEXT: s_mov_b32 s14, -1431; VI-NEXT: s_waitcnt lgkmcnt(0)432; VI-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0433; VI-NEXT: s_mov_b32 s12, s8434; VI-NEXT: s_mov_b32 s13, s9435; VI-NEXT: s_waitcnt lgkmcnt(0)436; VI-NEXT: v_perm_b32 v3, 0, s2, v4437; VI-NEXT: v_perm_b32 v2, 0, s3, v4438; VI-NEXT: v_perm_b32 v1, 0, s0, v4439; VI-NEXT: v_perm_b32 v0, 0, s1, v4440; VI-NEXT: v_perm_b32 v7, 0, s6, v4441; VI-NEXT: v_perm_b32 v6, 0, s7, v4442; VI-NEXT: v_perm_b32 v5, 0, s4, v4443; VI-NEXT: v_perm_b32 v4, 0, s5, v4444; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[12:15], 0 offset:16445; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[12:15], 0446; VI-NEXT: s_endpgm447;448; GFX11-LABEL: test_bswap_v4i64:449; GFX11: ; %bb.0:450; GFX11-NEXT: s_load_b128 s[8:11], s[4:5], 0x24451; GFX11-NEXT: s_waitcnt lgkmcnt(0)452; GFX11-NEXT: s_load_b256 s[0:7], s[10:11], 0x0453; GFX11-NEXT: s_mov_b32 s11, 0x31016000454; GFX11-NEXT: s_mov_b32 s10, -1455; GFX11-NEXT: s_waitcnt lgkmcnt(0)456; GFX11-NEXT: v_perm_b32 v7, 0, s6, 0x10203457; GFX11-NEXT: v_perm_b32 v6, 0, s7, 0x10203458; GFX11-NEXT: v_perm_b32 v5, 0, s4, 0x10203459; GFX11-NEXT: v_perm_b32 v4, 0, s5, 0x10203460; GFX11-NEXT: v_perm_b32 v3, 0, s2, 0x10203461; GFX11-NEXT: v_perm_b32 v2, 0, s3, 0x10203462; GFX11-NEXT: v_perm_b32 v1, 0, s0, 0x10203463; GFX11-NEXT: v_perm_b32 v0, 0, s1, 0x10203464; GFX11-NEXT: s_clause 0x1465; GFX11-NEXT: buffer_store_b128 v[4:7], off, s[8:11], 0 offset:16466; GFX11-NEXT: buffer_store_b128 v[0:3], off, s[8:11], 0467; GFX11-NEXT: s_endpgm468 %val = load <4 x i64>, ptr addrspace(1) %in, align 32469 %bswap = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> %val) nounwind readnone470 store <4 x i64> %bswap, ptr addrspace(1) %out, align 32471 ret void472}473 474define float @missing_truncate_promote_bswap(i32 %arg) {475; SI-LABEL: missing_truncate_promote_bswap:476; SI: ; %bb.0: ; %bb477; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)478; SI-NEXT: v_alignbit_b32 v1, v0, v0, 8479; SI-NEXT: v_alignbit_b32 v0, v0, v0, 24480; SI-NEXT: s_mov_b32 s4, 0xff00ff481; SI-NEXT: v_bfi_b32 v0, s4, v0, v1482; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0483; SI-NEXT: v_cvt_f32_f16_e32 v0, v0484; SI-NEXT: s_setpc_b64 s[30:31]485;486; VI-LABEL: missing_truncate_promote_bswap:487; VI: ; %bb.0: ; %bb488; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)489; VI-NEXT: s_mov_b32 s4, 0xc0c0001490; VI-NEXT: v_perm_b32 v0, 0, v0, s4491; VI-NEXT: v_cvt_f32_f16_e32 v0, v0492; VI-NEXT: s_setpc_b64 s[30:31]493;494; GFX11-REAL16-LABEL: missing_truncate_promote_bswap:495; GFX11-REAL16: ; %bb.0: ; %bb496; GFX11-REAL16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)497; GFX11-REAL16-NEXT: v_perm_b32 v0, 0, v0, 0xc0c0001498; GFX11-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)499; GFX11-REAL16-NEXT: v_cvt_f32_f16_e32 v0, v0.l500; GFX11-REAL16-NEXT: s_setpc_b64 s[30:31]501;502; GFX11-FAKE16-LABEL: missing_truncate_promote_bswap:503; GFX11-FAKE16: ; %bb.0: ; %bb504; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)505; GFX11-FAKE16-NEXT: v_perm_b32 v0, 0, v0, 0xc0c0001506; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)507; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0508; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]509bb:510 %tmp = trunc i32 %arg to i16511 %tmp1 = call i16 @llvm.bswap.i16(i16 %tmp)512 %tmp2 = bitcast i16 %tmp1 to half513 %tmp3 = fpext half %tmp2 to float514 ret float %tmp3515}516 517define i16 @v_bswap_i16(i16 %src) {518; SI-LABEL: v_bswap_i16:519; SI: ; %bb.0:520; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)521; SI-NEXT: v_alignbit_b32 v1, v0, v0, 8522; SI-NEXT: v_alignbit_b32 v0, v0, v0, 24523; SI-NEXT: s_mov_b32 s4, 0xff00ff524; SI-NEXT: v_bfi_b32 v0, s4, v0, v1525; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0526; SI-NEXT: s_setpc_b64 s[30:31]527;528; VI-LABEL: v_bswap_i16:529; VI: ; %bb.0:530; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)531; VI-NEXT: s_mov_b32 s4, 0xc0c0001532; VI-NEXT: v_perm_b32 v0, 0, v0, s4533; VI-NEXT: s_setpc_b64 s[30:31]534;535; GFX11-LABEL: v_bswap_i16:536; GFX11: ; %bb.0:537; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)538; GFX11-NEXT: v_perm_b32 v0, 0, v0, 0xc0c0001539; GFX11-NEXT: s_setpc_b64 s[30:31]540 %bswap = call i16 @llvm.bswap.i16(i16 %src)541 ret i16 %bswap542}543 544define i32 @v_bswap_i16_zext_to_i32(i16 %src) {545; SI-LABEL: v_bswap_i16_zext_to_i32:546; SI: ; %bb.0:547; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)548; SI-NEXT: v_alignbit_b32 v1, v0, v0, 8549; SI-NEXT: v_alignbit_b32 v0, v0, v0, 24550; SI-NEXT: s_mov_b32 s4, 0xff00ff551; SI-NEXT: v_bfi_b32 v0, s4, v0, v1552; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0553; SI-NEXT: s_setpc_b64 s[30:31]554;555; VI-LABEL: v_bswap_i16_zext_to_i32:556; VI: ; %bb.0:557; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)558; VI-NEXT: s_mov_b32 s4, 0xc0c0001559; VI-NEXT: v_perm_b32 v0, 0, v0, s4560; VI-NEXT: s_setpc_b64 s[30:31]561;562; GFX11-LABEL: v_bswap_i16_zext_to_i32:563; GFX11: ; %bb.0:564; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)565; GFX11-NEXT: v_perm_b32 v0, 0, v0, 0xc0c0001566; GFX11-NEXT: s_setpc_b64 s[30:31]567 %bswap = call i16 @llvm.bswap.i16(i16 %src)568 %zext = zext i16 %bswap to i32569 ret i32 %zext570}571 572define i32 @v_bswap_i16_sext_to_i32(i16 %src) {573; SI-LABEL: v_bswap_i16_sext_to_i32:574; SI: ; %bb.0:575; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)576; SI-NEXT: v_alignbit_b32 v1, v0, v0, 8577; SI-NEXT: v_alignbit_b32 v0, v0, v0, 24578; SI-NEXT: s_mov_b32 s4, 0xff00ff579; SI-NEXT: v_bfi_b32 v0, s4, v0, v1580; SI-NEXT: v_ashrrev_i32_e32 v0, 16, v0581; SI-NEXT: s_setpc_b64 s[30:31]582;583; VI-LABEL: v_bswap_i16_sext_to_i32:584; VI: ; %bb.0:585; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)586; VI-NEXT: s_mov_b32 s4, 0xc0c0001587; VI-NEXT: v_perm_b32 v0, 0, v0, s4588; VI-NEXT: v_bfe_i32 v0, v0, 0, 16589; VI-NEXT: s_setpc_b64 s[30:31]590;591; GFX11-LABEL: v_bswap_i16_sext_to_i32:592; GFX11: ; %bb.0:593; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)594; GFX11-NEXT: v_perm_b32 v0, 0, v0, 0xc0c0001595; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)596; GFX11-NEXT: v_bfe_i32 v0, v0, 0, 16597; GFX11-NEXT: s_setpc_b64 s[30:31]598 %bswap = call i16 @llvm.bswap.i16(i16 %src)599 %zext = sext i16 %bswap to i32600 ret i32 %zext601}602 603define <2 x i16> @v_bswap_v2i16(<2 x i16> %src) {604; SI-LABEL: v_bswap_v2i16:605; SI: ; %bb.0:606; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)607; SI-NEXT: v_alignbit_b32 v2, v0, v0, 8608; SI-NEXT: v_alignbit_b32 v0, v0, v0, 24609; SI-NEXT: s_mov_b32 s4, 0xff00ff610; SI-NEXT: v_alignbit_b32 v3, v1, v1, 8611; SI-NEXT: v_alignbit_b32 v1, v1, v1, 24612; SI-NEXT: v_bfi_b32 v0, s4, v0, v2613; SI-NEXT: v_bfi_b32 v1, s4, v1, v3614; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1615; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16616; SI-NEXT: s_setpc_b64 s[30:31]617;618; VI-LABEL: v_bswap_v2i16:619; VI: ; %bb.0:620; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)621; VI-NEXT: s_mov_b32 s4, 0x2030001622; VI-NEXT: v_perm_b32 v0, 0, v0, s4623; VI-NEXT: s_setpc_b64 s[30:31]624;625; GFX11-LABEL: v_bswap_v2i16:626; GFX11: ; %bb.0:627; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)628; GFX11-NEXT: v_perm_b32 v0, 0, v0, 0x2030001629; GFX11-NEXT: s_setpc_b64 s[30:31]630 %bswap = call <2 x i16> @llvm.bswap.v2i16(<2 x i16> %src)631 ret <2 x i16> %bswap632}633 634define <3 x i16> @v_bswap_v3i16(<3 x i16> %src) {635; SI-LABEL: v_bswap_v3i16:636; SI: ; %bb.0:637; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)638; SI-NEXT: v_alignbit_b32 v3, v0, v0, 8639; SI-NEXT: v_alignbit_b32 v0, v0, v0, 24640; SI-NEXT: s_mov_b32 s4, 0xff00ff641; SI-NEXT: v_alignbit_b32 v4, v1, v1, 8642; SI-NEXT: v_alignbit_b32 v1, v1, v1, 24643; SI-NEXT: v_alignbit_b32 v5, v2, v2, 8644; SI-NEXT: v_alignbit_b32 v2, v2, v2, 24645; SI-NEXT: v_bfi_b32 v0, s4, v0, v3646; SI-NEXT: v_bfi_b32 v1, s4, v1, v4647; SI-NEXT: v_bfi_b32 v2, s4, v2, v5648; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1649; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16650; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2651; SI-NEXT: v_alignbit_b32 v1, v2, v0, 16652; SI-NEXT: s_setpc_b64 s[30:31]653;654; VI-LABEL: v_bswap_v3i16:655; VI: ; %bb.0:656; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)657; VI-NEXT: s_mov_b32 s4, 0x2030001658; VI-NEXT: v_perm_b32 v0, 0, v0, s4659; VI-NEXT: v_perm_b32 v1, 0, v1, s4660; VI-NEXT: s_setpc_b64 s[30:31]661;662; GFX11-LABEL: v_bswap_v3i16:663; GFX11: ; %bb.0:664; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)665; GFX11-NEXT: v_perm_b32 v0, 0, v0, 0x2030001666; GFX11-NEXT: v_perm_b32 v1, 0, v1, 0x2030001667; GFX11-NEXT: s_setpc_b64 s[30:31]668 %bswap = call <3 x i16> @llvm.bswap.v3i16(<3 x i16> %src)669 ret <3 x i16> %bswap670}671 672define <4 x i16> @v_bswap_v4i16(<4 x i16> %src) {673; SI-LABEL: v_bswap_v4i16:674; SI: ; %bb.0:675; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)676; SI-NEXT: v_alignbit_b32 v4, v2, v2, 8677; SI-NEXT: v_alignbit_b32 v2, v2, v2, 24678; SI-NEXT: s_mov_b32 s4, 0xff00ff679; SI-NEXT: v_alignbit_b32 v5, v3, v3, 8680; SI-NEXT: v_alignbit_b32 v3, v3, v3, 24681; SI-NEXT: v_alignbit_b32 v6, v0, v0, 8682; SI-NEXT: v_alignbit_b32 v0, v0, v0, 24683; SI-NEXT: v_alignbit_b32 v7, v1, v1, 8684; SI-NEXT: v_alignbit_b32 v1, v1, v1, 24685; SI-NEXT: v_bfi_b32 v2, s4, v2, v4686; SI-NEXT: v_bfi_b32 v3, s4, v3, v5687; SI-NEXT: v_bfi_b32 v0, s4, v0, v6688; SI-NEXT: v_bfi_b32 v1, s4, v1, v7689; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3690; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1691; SI-NEXT: v_alignbit_b32 v2, v3, v2, 16692; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16693; SI-NEXT: v_alignbit_b32 v1, v2, v0, 16694; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v2695; SI-NEXT: s_setpc_b64 s[30:31]696;697; VI-LABEL: v_bswap_v4i16:698; VI: ; %bb.0:699; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)700; VI-NEXT: s_mov_b32 s4, 0x2030001701; VI-NEXT: v_perm_b32 v0, 0, v0, s4702; VI-NEXT: v_perm_b32 v1, 0, v1, s4703; VI-NEXT: s_setpc_b64 s[30:31]704;705; GFX11-LABEL: v_bswap_v4i16:706; GFX11: ; %bb.0:707; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)708; GFX11-NEXT: v_perm_b32 v0, 0, v0, 0x2030001709; GFX11-NEXT: v_perm_b32 v1, 0, v1, 0x2030001710; GFX11-NEXT: s_setpc_b64 s[30:31]711 %bswap = call <4 x i16> @llvm.bswap.v4i16(<4 x i16> %src)712 ret <4 x i16> %bswap713}714 715define i64 @v_bswap_i48(i64 %src) {716; SI-LABEL: v_bswap_i48:717; SI: ; %bb.0:718; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)719; SI-NEXT: v_alignbit_b32 v2, v0, v0, 8720; SI-NEXT: v_alignbit_b32 v0, v0, v0, 24721; SI-NEXT: s_mov_b32 s4, 0xff00ff722; SI-NEXT: v_alignbit_b32 v3, v1, v1, 8723; SI-NEXT: v_alignbit_b32 v1, v1, v1, 24724; SI-NEXT: v_bfi_b32 v2, s4, v0, v2725; SI-NEXT: v_bfi_b32 v0, s4, v1, v3726; SI-NEXT: v_alignbit_b32 v0, v2, v0, 16727; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v2728; SI-NEXT: s_setpc_b64 s[30:31]729;730; VI-LABEL: v_bswap_i48:731; VI: ; %bb.0:732; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)733; VI-NEXT: s_mov_b32 s4, 0x10203734; VI-NEXT: v_perm_b32 v2, 0, v0, s4735; VI-NEXT: v_perm_b32 v0, 0, v1, s4736; VI-NEXT: v_alignbit_b32 v0, v2, v0, 16737; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v2738; VI-NEXT: s_setpc_b64 s[30:31]739;740; GFX11-REAL16-LABEL: v_bswap_i48:741; GFX11-REAL16: ; %bb.0:742; GFX11-REAL16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)743; GFX11-REAL16-NEXT: v_perm_b32 v2, 0, v0, 0x10203744; GFX11-REAL16-NEXT: v_perm_b32 v0, 0, v1, 0x10203745; GFX11-REAL16-NEXT: v_mov_b16_e32 v1.h, 0746; GFX11-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)747; GFX11-REAL16-NEXT: v_mov_b16_e32 v1.l, v2.h748; GFX11-REAL16-NEXT: v_alignbit_b32 v0, v2, v0, 16749; GFX11-REAL16-NEXT: s_setpc_b64 s[30:31]750;751; GFX11-FAKE16-LABEL: v_bswap_i48:752; GFX11-FAKE16: ; %bb.0:753; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)754; GFX11-FAKE16-NEXT: v_perm_b32 v2, 0, v0, 0x10203755; GFX11-FAKE16-NEXT: v_perm_b32 v0, 0, v1, 0x10203756; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)757; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2758; GFX11-FAKE16-NEXT: v_alignbit_b32 v0, v2, v0, 16759; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]760 %trunc = trunc i64 %src to i48761 %bswap = call i48 @llvm.bswap.i48(i48 %trunc)762 %zext = zext i48 %bswap to i64763 ret i64 %zext764}765