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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 32; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 < %s | FileCheck %s3 4define amdgpu_cs <2 x i32> @f() {5; CHECK-LABEL: f:6; CHECK: ; %bb.0: ; %bb7; CHECK-NEXT: s_mov_b32 s4, 08; CHECK-NEXT: s_mov_b32 s1, 09; CHECK-NEXT: s_mov_b32 s5, s410; CHECK-NEXT: s_mov_b32 s6, s411; CHECK-NEXT: s_mov_b32 s7, s412; CHECK-NEXT: buffer_load_dwordx2 v[0:1], off, s[4:7], 013; CHECK-NEXT: s_waitcnt vmcnt(0)14; CHECK-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]15; CHECK-NEXT: v_mov_b32_e32 v1, s416; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo17; CHECK-NEXT: v_readfirstlane_b32 s0, v018; CHECK-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 019; CHECK-NEXT: ; return to shader part epilog20bb:21 %i = call <2 x i32> @llvm.amdgcn.raw.buffer.load.v2i32(<4 x i32> zeroinitializer, i32 0, i32 0, i32 0)22 %i1 = bitcast <2 x i32> %i to i6423 %i2 = insertelement <3 x i64> zeroinitializer, i64 %i1, i64 224 %i3 = icmp ne <3 x i64> %i2, zeroinitializer25 %i4 = zext <3 x i1> %i3 to <3 x i64>26 %i5 = bitcast <3 x i64> %i4 to <6 x i32>27 %i6 = shufflevector <6 x i32> %i5, <6 x i32> zeroinitializer, <2 x i32> <i32 4, i32 5>28 call void @llvm.amdgcn.raw.buffer.store.v2i32(<2 x i32> %i6, <4 x i32> zeroinitializer, i32 0, i32 0, i32 0)29 ret <2 x i32> %i630}31 32declare <2 x i32> @llvm.amdgcn.raw.buffer.load.v2i32(<4 x i32>, i32, i32, i32 immarg)33declare void @llvm.amdgcn.raw.buffer.store.v2i32(<2 x i32>, <4 x i32>, i32, i32, i32 immarg)34