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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn -mcpu=verde < %s | FileCheck -check-prefix=GFX6 %s3; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=GFX8 %s4 5; Test for compilation only. This generated an invalid machine instruction6; by trying to commute the operands of a V_CMP_EQ_i32_e32 instruction, both7; of which were in SGPRs.8define amdgpu_vs float @main(i32 %v) {9; GFX6-LABEL: main:10; GFX6: ; %bb.0: ; %main_body11; GFX6-NEXT: s_cbranch_scc1 .LBB0_212; GFX6-NEXT: ; %bb.1: ; %IF5713; GFX6-NEXT: v_lshlrev_b32_e32 v0, 1, v014; GFX6-NEXT: .LBB0_2: ; %ENDIF5615; GFX6-NEXT: s_buffer_load_dword s0, s[0:3], 0xf016; GFX6-NEXT: s_waitcnt lgkmcnt(0)17; GFX6-NEXT: s_cmp_eq_u32 s0, 018; GFX6-NEXT: s_cbranch_scc1 .LBB0_419; GFX6-NEXT: ; %bb.3: ; %IF6020; GFX6-NEXT: v_lshlrev_b32_e32 v0, 1, v021; GFX6-NEXT: .LBB0_4: ; %ENDIF5922; GFX6-NEXT: s_buffer_load_dword s0, s[0:3], 0xf423; GFX6-NEXT: s_waitcnt lgkmcnt(0)24; GFX6-NEXT: s_cmp_eq_u32 s0, 025; GFX6-NEXT: s_cbranch_scc0 .LBB0_626; GFX6-NEXT: ; %bb.5: ; %ENDIF6227; GFX6-NEXT: s_branch .LBB0_728; GFX6-NEXT: .LBB0_6: ; %IF6329; GFX6-NEXT: .LBB0_7:30;31; GFX8-LABEL: main:32; GFX8: ; %bb.0: ; %main_body33; GFX8-NEXT: s_cbranch_scc1 .LBB0_234; GFX8-NEXT: ; %bb.1: ; %IF5735; GFX8-NEXT: v_lshlrev_b32_e32 v0, 1, v036; GFX8-NEXT: .LBB0_2: ; %ENDIF5637; GFX8-NEXT: s_buffer_load_dword s0, s[0:3], 0x3c038; GFX8-NEXT: s_waitcnt lgkmcnt(0)39; GFX8-NEXT: s_cmp_eq_u32 s0, 040; GFX8-NEXT: s_cbranch_scc1 .LBB0_441; GFX8-NEXT: ; %bb.3: ; %IF6042; GFX8-NEXT: v_lshlrev_b32_e32 v0, 1, v043; GFX8-NEXT: .LBB0_4: ; %ENDIF5944; GFX8-NEXT: s_buffer_load_dword s0, s[0:3], 0x3d045; GFX8-NEXT: s_waitcnt lgkmcnt(0)46; GFX8-NEXT: s_cmp_eq_u32 s0, 047; GFX8-NEXT: s_cbranch_scc0 .LBB0_648; GFX8-NEXT: ; %bb.5: ; %ENDIF6249; GFX8-NEXT: s_branch .LBB0_750; GFX8-NEXT: .LBB0_6: ; %IF6351; GFX8-NEXT: .LBB0_7:52main_body:53 %d1 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> poison, i32 960, i32 0)54 %d2 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> poison, i32 976, i32 0)55 br i1 poison, label %ENDIF56, label %IF5756 57IF57: ; preds = %ENDIF58 %v.1 = mul i32 %v, 259 br label %ENDIF5660 61ENDIF56: ; preds = %IF57, %ENDIF62 %v.2 = phi i32 [ %v, %main_body ], [ %v.1, %IF57 ]63 %d1.i = bitcast float %d1 to i3264 %cc1 = icmp eq i32 %d1.i, 065 br i1 %cc1, label %ENDIF59, label %IF6066 67IF60: ; preds = %ENDIF5668 %v.3 = mul i32 %v.2, 269 br label %ENDIF5970 71ENDIF59: ; preds = %IF60, %ENDIF5672 %v.4 = phi i32 [ %v.2, %ENDIF56 ], [ %v.3, %IF60 ]73 %d2.i = bitcast float %d2 to i3274 %cc2 = icmp eq i32 %d2.i, 075 br i1 %cc2, label %ENDIF62, label %IF6376 77IF63: ; preds = %ENDIF5978 unreachable79 80ENDIF62: ; preds = %ENDIF5981 %r = bitcast i32 %v.4 to float82 ret float %r83}84 85declare float @llvm.amdgcn.s.buffer.load.f32(<4 x i32>, i32, i32) #086 87attributes #0 = { nounwind readnone }88attributes #1 = { readnone }89