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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -mtriple=r600-- -mcpu=redwood | FileCheck %s --check-prefixes=R6003 4define amdgpu_kernel void @build_vector2 (ptr addrspace(1) %out) {5; R600-LABEL: build_vector2:6; R600: ; %bb.0: ; %entry7; R600-NEXT: ALU 4, @4, KC0[CB0:0-32], KC1[]8; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 19; R600-NEXT: CF_END10; R600-NEXT: PAD11; R600-NEXT: ALU clause starting at 4:12; R600-NEXT: MOV * T0.Y, literal.x,13; R600-NEXT: 6(8.407791e-45), 0(0.000000e+00)14; R600-NEXT: MOV T0.X, literal.x,15; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,16; R600-NEXT: 5(7.006492e-45), 2(2.802597e-45)17entry:18 store <2 x i32> <i32 5, i32 6>, ptr addrspace(1) %out19 ret void20}21 22define amdgpu_kernel void @build_vector4 (ptr addrspace(1) %out) {23; R600-LABEL: build_vector4:24; R600: ; %bb.0: ; %entry25; R600-NEXT: ALU 8, @4, KC0[CB0:0-32], KC1[]26; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 127; R600-NEXT: CF_END28; R600-NEXT: PAD29; R600-NEXT: ALU clause starting at 4:30; R600-NEXT: MOV * T0.W, literal.x,31; R600-NEXT: 8(1.121039e-44), 0(0.000000e+00)32; R600-NEXT: MOV * T0.Z, literal.x,33; R600-NEXT: 7(9.809089e-45), 0(0.000000e+00)34; R600-NEXT: MOV * T0.Y, literal.x,35; R600-NEXT: 6(8.407791e-45), 0(0.000000e+00)36; R600-NEXT: MOV T0.X, literal.x,37; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,38; R600-NEXT: 5(7.006492e-45), 2(2.802597e-45)39entry:40 store <4 x i32> <i32 5, i32 6, i32 7, i32 8>, ptr addrspace(1) %out41 ret void42}43 44define amdgpu_kernel void @build_vector_v2i16 (ptr addrspace(1) %out) {45; R600-LABEL: build_vector_v2i16:46; R600: ; %bb.0: ; %entry47; R600-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]48; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.X, T5.X, 149; R600-NEXT: CF_END50; R600-NEXT: PAD51; R600-NEXT: ALU clause starting at 4:52; R600-NEXT: MOV T4.X, literal.x,53; R600-NEXT: LSHR * T5.X, KC0[2].Y, literal.y,54; R600-NEXT: 393221(5.510200e-40), 2(2.802597e-45)55entry:56 store <2 x i16> <i16 5, i16 6>, ptr addrspace(1) %out57 ret void58}59 60define amdgpu_kernel void @build_vector_v2i16_trunc (ptr addrspace(1) %out, i32 %a) {61; R600-LABEL: build_vector_v2i16_trunc:62; R600: ; %bb.0:63; R600-NEXT: ALU 4, @4, KC0[CB0:0-32], KC1[]64; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.X, T5.X, 165; R600-NEXT: CF_END66; R600-NEXT: PAD67; R600-NEXT: ALU clause starting at 4:68; R600-NEXT: LSHR * T0.W, KC0[2].Z, literal.x,69; R600-NEXT: 16(2.242078e-44), 0(0.000000e+00)70; R600-NEXT: OR_INT T4.X, PV.W, literal.x,71; R600-NEXT: LSHR * T5.X, KC0[2].Y, literal.y,72; R600-NEXT: 327680(4.591775e-40), 2(2.802597e-45)73 %srl = lshr i32 %a, 1674 %trunc = trunc i32 %srl to i1675 %ins.0 = insertelement <2 x i16> poison, i16 %trunc, i32 076 %ins.1 = insertelement <2 x i16> %ins.0, i16 5, i32 177 store <2 x i16> %ins.1, ptr addrspace(1) %out78 ret void79}80 81define amdgpu_kernel void @build_v2i32_from_v4i16_shuffle(ptr addrspace(1) %out, <4 x i16> %in) {82; R600-LABEL: build_v2i32_from_v4i16_shuffle:83; R600: ; %bb.0: ; %entry84; R600-NEXT: ALU 0, @10, KC0[], KC1[]85; R600-NEXT: TEX 1 @686; R600-NEXT: ALU 4, @11, KC0[CB0:0-32], KC1[]87; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 188; R600-NEXT: CF_END89; R600-NEXT: PAD90; R600-NEXT: Fetch clause starting at 6:91; R600-NEXT: VTX_READ_16 T1.X, T0.X, 48, #392; R600-NEXT: VTX_READ_16 T0.X, T0.X, 44, #393; R600-NEXT: ALU clause starting at 10:94; R600-NEXT: MOV * T0.X, 0.0,95; R600-NEXT: ALU clause starting at 11:96; R600-NEXT: LSHL * T0.Y, T1.X, literal.x,97; R600-NEXT: 16(2.242078e-44), 0(0.000000e+00)98; R600-NEXT: LSHL T0.X, T0.X, literal.x,99; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,100; R600-NEXT: 16(2.242078e-44), 2(2.802597e-45)101entry:102 %shuf = shufflevector <4 x i16> %in, <4 x i16> zeroinitializer, <2 x i32> <i32 0, i32 2>103 %zextended = zext <2 x i16> %shuf to <2 x i32>104 %shifted = shl <2 x i32> %zextended, <i32 16, i32 16>105 store <2 x i32> %shifted, ptr addrspace(1) %out106 ret void107}108