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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s3 4; 64-bit divides and rems should be split into a fast and slow path5; where the fast path uses a 32-bit operation.6 7define i64 @sdiv64(i64 %a, i64 %b) {8; GFX9-LABEL: sdiv64:9; GFX9: ; %bb.0:10; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)11; GFX9-NEXT: v_or_b32_e32 v5, v1, v312; GFX9-NEXT: v_mov_b32_e32 v4, 013; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]14; GFX9-NEXT: ; implicit-def: $vgpr4_vgpr515; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc16; GFX9-NEXT: s_xor_b64 s[6:7], exec, s[4:5]17; GFX9-NEXT: s_cbranch_execz .LBB0_218; GFX9-NEXT: ; %bb.1:19; GFX9-NEXT: v_ashrrev_i32_e32 v9, 31, v320; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v921; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v9, vcc22; GFX9-NEXT: v_xor_b32_e32 v10, v3, v923; GFX9-NEXT: v_xor_b32_e32 v11, v2, v924; GFX9-NEXT: v_cvt_f32_u32_e32 v2, v1125; GFX9-NEXT: v_cvt_f32_u32_e32 v3, v1026; GFX9-NEXT: v_sub_co_u32_e32 v7, vcc, 0, v1127; GFX9-NEXT: v_subb_co_u32_e32 v8, vcc, 0, v10, vcc28; GFX9-NEXT: v_madmk_f32 v2, v3, 0x4f800000, v229; GFX9-NEXT: v_rcp_f32_e32 v2, v230; GFX9-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v231; GFX9-NEXT: v_mul_f32_e32 v3, 0x2f800000, v232; GFX9-NEXT: v_trunc_f32_e32 v3, v333; GFX9-NEXT: v_madmk_f32 v2, v3, 0xcf800000, v234; GFX9-NEXT: v_cvt_u32_f32_e32 v6, v235; GFX9-NEXT: v_cvt_u32_f32_e32 v12, v336; GFX9-NEXT: v_mul_lo_u32 v4, v8, v637; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v7, v6, 038; GFX9-NEXT: v_mul_lo_u32 v5, v7, v1239; GFX9-NEXT: v_mul_hi_u32 v13, v6, v240; GFX9-NEXT: v_add3_u32 v5, v3, v5, v441; GFX9-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v6, v5, 042; GFX9-NEXT: v_add_co_u32_e32 v13, vcc, v13, v343; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v12, v2, 044; GFX9-NEXT: v_addc_co_u32_e32 v14, vcc, 0, v4, vcc45; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v12, v5, 046; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v13, v247; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v14, v3, vcc48; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v5, vcc49; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v450; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc51; GFX9-NEXT: v_add_co_u32_e32 v13, vcc, v6, v252; GFX9-NEXT: v_addc_co_u32_e32 v12, vcc, v12, v3, vcc53; GFX9-NEXT: v_mul_lo_u32 v4, v7, v1254; GFX9-NEXT: v_mul_lo_u32 v5, v8, v1355; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v7, v13, 056; GFX9-NEXT: v_add3_u32 v5, v3, v4, v557; GFX9-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v12, v5, 058; GFX9-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v13, v5, 059; GFX9-NEXT: v_mul_hi_u32 v14, v13, v260; GFX9-NEXT: v_mad_u64_u32 v[7:8], s[4:5], v12, v2, 061; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v14, v562; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v6, vcc63; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v764; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v5, v8, vcc65; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v4, vcc66; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v367; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc68; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v13, v269; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v12, v3, vcc70; GFX9-NEXT: v_ashrrev_i32_e32 v4, 31, v171; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v472; GFX9-NEXT: v_xor_b32_e32 v6, v0, v473; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v1, v4, vcc74; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v6, v3, 075; GFX9-NEXT: v_mul_hi_u32 v7, v6, v276; GFX9-NEXT: v_xor_b32_e32 v5, v5, v477; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v7, v078; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v1, vcc79; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v5, v2, 080; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v5, v3, 081; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v7, v082; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v8, v1, vcc83; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc84; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v0, v285; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v1, vcc86; GFX9-NEXT: v_mul_lo_u32 v7, v10, v287; GFX9-NEXT: v_mul_lo_u32 v8, v11, v388; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v11, v2, 089; GFX9-NEXT: v_add3_u32 v1, v1, v8, v790; GFX9-NEXT: v_sub_u32_e32 v7, v5, v191; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, v6, v092; GFX9-NEXT: v_subb_co_u32_e64 v6, s[4:5], v7, v10, vcc93; GFX9-NEXT: v_sub_co_u32_e64 v7, s[4:5], v0, v1194; GFX9-NEXT: v_subbrev_co_u32_e64 v6, s[4:5], 0, v6, s[4:5]95; GFX9-NEXT: v_cmp_ge_u32_e64 s[4:5], v6, v1096; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[4:5]97; GFX9-NEXT: v_cmp_ge_u32_e64 s[4:5], v7, v1198; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5]99; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], v6, v10100; GFX9-NEXT: v_cndmask_b32_e64 v6, v8, v7, s[4:5]101; GFX9-NEXT: v_add_co_u32_e64 v7, s[4:5], 2, v2102; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v5, v1, vcc103; GFX9-NEXT: v_addc_co_u32_e64 v8, s[4:5], 0, v3, s[4:5]104; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v1, v10105; GFX9-NEXT: v_add_co_u32_e64 v12, s[4:5], 1, v2106; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc107; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v11108; GFX9-NEXT: v_addc_co_u32_e64 v13, s[4:5], 0, v3, s[4:5]109; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc110; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v10111; GFX9-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v6112; GFX9-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc113; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0114; GFX9-NEXT: v_cndmask_b32_e64 v1, v12, v7, s[4:5]115; GFX9-NEXT: v_cndmask_b32_e64 v6, v13, v8, s[4:5]116; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc117; GFX9-NEXT: v_xor_b32_e32 v2, v4, v9118; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v6, vcc119; GFX9-NEXT: v_xor_b32_e32 v1, v1, v2120; GFX9-NEXT: v_xor_b32_e32 v0, v0, v2121; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, v1, v2122; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, v0, v2, vcc123; GFX9-NEXT: ; implicit-def: $vgpr2_vgpr3124; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1125; GFX9-NEXT: .LBB0_2: ; %Flow126; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[6:7]127; GFX9-NEXT: s_cbranch_execz .LBB0_4128; GFX9-NEXT: ; %bb.3:129; GFX9-NEXT: v_cvt_f32_u32_e32 v1, v2130; GFX9-NEXT: v_sub_u32_e32 v3, 0, v2131; GFX9-NEXT: v_mov_b32_e32 v5, 0132; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1133; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1134; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1135; GFX9-NEXT: v_mul_lo_u32 v3, v3, v1136; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3137; GFX9-NEXT: v_add_u32_e32 v1, v1, v3138; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1139; GFX9-NEXT: v_mul_lo_u32 v3, v1, v2140; GFX9-NEXT: v_add_u32_e32 v4, 1, v1141; GFX9-NEXT: v_sub_u32_e32 v0, v0, v3142; GFX9-NEXT: v_sub_u32_e32 v3, v0, v2143; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2144; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc145; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc146; GFX9-NEXT: v_add_u32_e32 v3, 1, v1147; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2148; GFX9-NEXT: v_cndmask_b32_e32 v4, v1, v3, vcc149; GFX9-NEXT: .LBB0_4:150; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]151; GFX9-NEXT: v_mov_b32_e32 v0, v4152; GFX9-NEXT: v_mov_b32_e32 v1, v5153; GFX9-NEXT: s_setpc_b64 s[30:31]154 %d = sdiv i64 %a, %b155 ret i64 %d156}157 158define i64 @udiv64(i64 %a, i64 %b) {159; GFX9-LABEL: udiv64:160; GFX9: ; %bb.0:161; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)162; GFX9-NEXT: v_or_b32_e32 v5, v1, v3163; GFX9-NEXT: v_mov_b32_e32 v4, 0164; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]165; GFX9-NEXT: ; implicit-def: $vgpr4_vgpr5166; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc167; GFX9-NEXT: s_xor_b64 s[6:7], exec, s[4:5]168; GFX9-NEXT: s_cbranch_execz .LBB1_2169; GFX9-NEXT: ; %bb.1:170; GFX9-NEXT: v_cvt_f32_u32_e32 v4, v2171; GFX9-NEXT: v_cvt_f32_u32_e32 v5, v3172; GFX9-NEXT: v_sub_co_u32_e32 v10, vcc, 0, v2173; GFX9-NEXT: v_subb_co_u32_e32 v11, vcc, 0, v3, vcc174; GFX9-NEXT: v_madmk_f32 v4, v5, 0x4f800000, v4175; GFX9-NEXT: v_rcp_f32_e32 v4, v4176; GFX9-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4177; GFX9-NEXT: v_mul_f32_e32 v5, 0x2f800000, v4178; GFX9-NEXT: v_trunc_f32_e32 v5, v5179; GFX9-NEXT: v_madmk_f32 v4, v5, 0xcf800000, v4180; GFX9-NEXT: v_cvt_u32_f32_e32 v8, v5181; GFX9-NEXT: v_cvt_u32_f32_e32 v9, v4182; GFX9-NEXT: v_mul_lo_u32 v6, v10, v8183; GFX9-NEXT: v_mul_lo_u32 v7, v11, v9184; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v10, v9, 0185; GFX9-NEXT: v_add3_u32 v7, v5, v6, v7186; GFX9-NEXT: v_mul_hi_u32 v12, v9, v4187; GFX9-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v9, v7, 0188; GFX9-NEXT: v_add_co_u32_e32 v12, vcc, v12, v5189; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v8, v4, 0190; GFX9-NEXT: v_addc_co_u32_e32 v13, vcc, 0, v6, vcc191; GFX9-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v8, v7, 0192; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v12, v4193; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v13, v5, vcc194; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v7, vcc195; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v6196; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc197; GFX9-NEXT: v_add_co_u32_e32 v12, vcc, v9, v4198; GFX9-NEXT: v_addc_co_u32_e32 v13, vcc, v8, v5, vcc199; GFX9-NEXT: v_mul_lo_u32 v6, v10, v13200; GFX9-NEXT: v_mul_lo_u32 v7, v11, v12201; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v10, v12, 0202; GFX9-NEXT: v_add3_u32 v7, v5, v6, v7203; GFX9-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v13, v7, 0204; GFX9-NEXT: v_mad_u64_u32 v[7:8], s[4:5], v12, v7, 0205; GFX9-NEXT: v_mul_hi_u32 v11, v12, v4206; GFX9-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v13, v4, 0207; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v11, v7208; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v8, vcc209; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v9210; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v7, v10, vcc211; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v6, vcc212; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v5213; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v6, vcc214; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v12, v4215; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v13, v5, vcc216; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v0, v7, 0217; GFX9-NEXT: v_mul_hi_u32 v8, v0, v6218; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v8, v4219; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v5, vcc220; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v1, v6, 0221; GFX9-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v1, v7, 0222; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v8, v4223; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v9, v5, vcc224; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v7, vcc225; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v4, v6226; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v5, vcc227; GFX9-NEXT: v_mul_lo_u32 v8, v3, v6228; GFX9-NEXT: v_mul_lo_u32 v9, v2, v7229; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v2, v6, 0230; GFX9-NEXT: v_add3_u32 v5, v5, v9, v8231; GFX9-NEXT: v_sub_u32_e32 v8, v1, v5232; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v4233; GFX9-NEXT: v_subb_co_u32_e64 v4, s[4:5], v8, v3, vcc234; GFX9-NEXT: v_sub_co_u32_e64 v8, s[4:5], v0, v2235; GFX9-NEXT: v_subbrev_co_u32_e64 v4, s[4:5], 0, v4, s[4:5]236; GFX9-NEXT: v_cmp_ge_u32_e64 s[4:5], v4, v3237; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5]238; GFX9-NEXT: v_cmp_ge_u32_e64 s[4:5], v8, v2239; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[4:5]240; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], v4, v3241; GFX9-NEXT: v_cndmask_b32_e64 v4, v9, v8, s[4:5]242; GFX9-NEXT: v_add_co_u32_e64 v8, s[4:5], 2, v6243; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v5, vcc244; GFX9-NEXT: v_addc_co_u32_e64 v9, s[4:5], 0, v7, s[4:5]245; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3246; GFX9-NEXT: v_add_co_u32_e64 v10, s[4:5], 1, v6247; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc248; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2249; GFX9-NEXT: v_addc_co_u32_e64 v11, s[4:5], 0, v7, s[4:5]250; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc251; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3252; GFX9-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v4253; GFX9-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc254; GFX9-NEXT: v_cndmask_b32_e64 v4, v11, v9, s[4:5]255; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0256; GFX9-NEXT: v_cndmask_b32_e64 v0, v10, v8, s[4:5]257; GFX9-NEXT: v_cndmask_b32_e32 v5, v7, v4, vcc258; GFX9-NEXT: v_cndmask_b32_e32 v4, v6, v0, vcc259; GFX9-NEXT: ; implicit-def: $vgpr2_vgpr3260; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1261; GFX9-NEXT: .LBB1_2: ; %Flow262; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[6:7]263; GFX9-NEXT: s_cbranch_execz .LBB1_4264; GFX9-NEXT: ; %bb.3:265; GFX9-NEXT: v_cvt_f32_u32_e32 v1, v2266; GFX9-NEXT: v_sub_u32_e32 v3, 0, v2267; GFX9-NEXT: v_mov_b32_e32 v5, 0268; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1269; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1270; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1271; GFX9-NEXT: v_mul_lo_u32 v3, v3, v1272; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3273; GFX9-NEXT: v_add_u32_e32 v1, v1, v3274; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1275; GFX9-NEXT: v_mul_lo_u32 v3, v1, v2276; GFX9-NEXT: v_add_u32_e32 v4, 1, v1277; GFX9-NEXT: v_sub_u32_e32 v0, v0, v3278; GFX9-NEXT: v_sub_u32_e32 v3, v0, v2279; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2280; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc281; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc282; GFX9-NEXT: v_add_u32_e32 v3, 1, v1283; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2284; GFX9-NEXT: v_cndmask_b32_e32 v4, v1, v3, vcc285; GFX9-NEXT: .LBB1_4:286; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]287; GFX9-NEXT: v_mov_b32_e32 v0, v4288; GFX9-NEXT: v_mov_b32_e32 v1, v5289; GFX9-NEXT: s_setpc_b64 s[30:31]290 %d = udiv i64 %a, %b291 ret i64 %d292}293 294define i64 @srem64(i64 %a, i64 %b) {295; GFX9-LABEL: srem64:296; GFX9: ; %bb.0:297; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)298; GFX9-NEXT: v_or_b32_e32 v5, v1, v3299; GFX9-NEXT: v_mov_b32_e32 v4, 0300; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]301; GFX9-NEXT: ; implicit-def: $vgpr4_vgpr5302; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc303; GFX9-NEXT: s_xor_b64 s[8:9], exec, s[4:5]304; GFX9-NEXT: s_cbranch_execz .LBB2_2305; GFX9-NEXT: ; %bb.1:306; GFX9-NEXT: v_ashrrev_i32_e32 v4, 31, v3307; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4308; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v4, vcc309; GFX9-NEXT: v_xor_b32_e32 v9, v3, v4310; GFX9-NEXT: v_xor_b32_e32 v10, v2, v4311; GFX9-NEXT: v_cvt_f32_u32_e32 v2, v10312; GFX9-NEXT: v_cvt_f32_u32_e32 v3, v9313; GFX9-NEXT: v_sub_co_u32_e32 v7, vcc, 0, v10314; GFX9-NEXT: v_subb_co_u32_e32 v8, vcc, 0, v9, vcc315; GFX9-NEXT: v_madmk_f32 v2, v3, 0x4f800000, v2316; GFX9-NEXT: v_rcp_f32_e32 v2, v2317; GFX9-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2318; GFX9-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2319; GFX9-NEXT: v_trunc_f32_e32 v3, v3320; GFX9-NEXT: v_madmk_f32 v2, v3, 0xcf800000, v2321; GFX9-NEXT: v_cvt_u32_f32_e32 v6, v2322; GFX9-NEXT: v_cvt_u32_f32_e32 v11, v3323; GFX9-NEXT: v_mul_lo_u32 v4, v8, v6324; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v7, v6, 0325; GFX9-NEXT: v_mul_lo_u32 v5, v7, v11326; GFX9-NEXT: v_mul_hi_u32 v12, v6, v2327; GFX9-NEXT: v_add3_u32 v5, v3, v5, v4328; GFX9-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v6, v5, 0329; GFX9-NEXT: v_add_co_u32_e32 v12, vcc, v12, v3330; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v11, v2, 0331; GFX9-NEXT: v_addc_co_u32_e32 v13, vcc, 0, v4, vcc332; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v11, v5, 0333; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v12, v2334; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v13, v3, vcc335; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v5, vcc336; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4337; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc338; GFX9-NEXT: v_add_co_u32_e32 v12, vcc, v6, v2339; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, v11, v3, vcc340; GFX9-NEXT: v_mul_lo_u32 v4, v7, v11341; GFX9-NEXT: v_mul_lo_u32 v5, v8, v12342; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v7, v12, 0343; GFX9-NEXT: v_add3_u32 v5, v3, v4, v5344; GFX9-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v11, v5, 0345; GFX9-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v12, v5, 0346; GFX9-NEXT: v_mul_hi_u32 v13, v12, v2347; GFX9-NEXT: v_mad_u64_u32 v[7:8], s[4:5], v11, v2, 0348; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v13, v5349; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v6, vcc350; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v7351; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v5, v8, vcc352; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v4, vcc353; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v3354; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc355; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v12, v2356; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v11, v3, vcc357; GFX9-NEXT: v_ashrrev_i32_e32 v5, 31, v1358; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v5359; GFX9-NEXT: v_xor_b32_e32 v6, v0, v5360; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v1, v5, vcc361; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v6, v3, 0362; GFX9-NEXT: v_mul_hi_u32 v7, v6, v2363; GFX9-NEXT: v_xor_b32_e32 v4, v4, v5364; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v7, v0365; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v1, vcc366; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v4, v2, 0367; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v4, v3, 0368; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v7, v0369; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v8, v1, vcc370; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc371; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2372; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc373; GFX9-NEXT: v_mul_lo_u32 v2, v9, v0374; GFX9-NEXT: v_mul_lo_u32 v3, v10, v1375; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v10, v0, 0376; GFX9-NEXT: v_add3_u32 v1, v1, v3, v2377; GFX9-NEXT: v_sub_u32_e32 v2, v4, v1378; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, v6, v0379; GFX9-NEXT: v_subb_co_u32_e64 v2, s[4:5], v2, v9, vcc380; GFX9-NEXT: v_sub_co_u32_e64 v3, s[4:5], v0, v10381; GFX9-NEXT: v_subbrev_co_u32_e64 v6, s[6:7], 0, v2, s[4:5]382; GFX9-NEXT: v_cmp_ge_u32_e64 s[6:7], v6, v9383; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[6:7]384; GFX9-NEXT: v_cmp_ge_u32_e64 s[6:7], v3, v10385; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[6:7]386; GFX9-NEXT: v_cmp_eq_u32_e64 s[6:7], v6, v9387; GFX9-NEXT: v_subb_co_u32_e64 v2, s[4:5], v2, v9, s[4:5]388; GFX9-NEXT: v_cndmask_b32_e64 v7, v7, v8, s[6:7]389; GFX9-NEXT: v_sub_co_u32_e64 v8, s[4:5], v3, v10390; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v4, v1, vcc391; GFX9-NEXT: v_subbrev_co_u32_e64 v2, s[4:5], 0, v2, s[4:5]392; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v1, v9393; GFX9-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v7394; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc395; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v10396; GFX9-NEXT: v_cndmask_b32_e64 v2, v6, v2, s[4:5]397; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc398; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v9399; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc400; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4401; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc402; GFX9-NEXT: v_cndmask_b32_e64 v2, v3, v8, s[4:5]403; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc404; GFX9-NEXT: v_xor_b32_e32 v0, v0, v5405; GFX9-NEXT: v_xor_b32_e32 v1, v1, v5406; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, v0, v5407; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, v1, v5, vcc408; GFX9-NEXT: ; implicit-def: $vgpr2_vgpr3409; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1410; GFX9-NEXT: .LBB2_2: ; %Flow411; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[8:9]412; GFX9-NEXT: s_cbranch_execz .LBB2_4413; GFX9-NEXT: ; %bb.3:414; GFX9-NEXT: v_cvt_f32_u32_e32 v1, v2415; GFX9-NEXT: v_sub_u32_e32 v3, 0, v2416; GFX9-NEXT: v_mov_b32_e32 v5, 0417; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1418; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1419; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1420; GFX9-NEXT: v_mul_lo_u32 v3, v3, v1421; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3422; GFX9-NEXT: v_add_u32_e32 v1, v1, v3423; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1424; GFX9-NEXT: v_mul_lo_u32 v1, v1, v2425; GFX9-NEXT: v_sub_u32_e32 v0, v0, v1426; GFX9-NEXT: v_sub_u32_e32 v1, v0, v2427; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2428; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc429; GFX9-NEXT: v_sub_u32_e32 v1, v0, v2430; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2431; GFX9-NEXT: v_cndmask_b32_e32 v4, v0, v1, vcc432; GFX9-NEXT: .LBB2_4:433; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]434; GFX9-NEXT: v_mov_b32_e32 v0, v4435; GFX9-NEXT: v_mov_b32_e32 v1, v5436; GFX9-NEXT: s_setpc_b64 s[30:31]437 %d = srem i64 %a, %b438 ret i64 %d439}440 441define i64 @urem64(i64 %a, i64 %b) {442; GFX9-LABEL: urem64:443; GFX9: ; %bb.0:444; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)445; GFX9-NEXT: v_or_b32_e32 v5, v1, v3446; GFX9-NEXT: v_mov_b32_e32 v4, 0447; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]448; GFX9-NEXT: ; implicit-def: $vgpr4_vgpr5449; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc450; GFX9-NEXT: s_xor_b64 s[8:9], exec, s[4:5]451; GFX9-NEXT: s_cbranch_execz .LBB3_2452; GFX9-NEXT: ; %bb.1:453; GFX9-NEXT: v_cvt_f32_u32_e32 v4, v2454; GFX9-NEXT: v_cvt_f32_u32_e32 v5, v3455; GFX9-NEXT: v_sub_co_u32_e32 v10, vcc, 0, v2456; GFX9-NEXT: v_subb_co_u32_e32 v11, vcc, 0, v3, vcc457; GFX9-NEXT: v_madmk_f32 v4, v5, 0x4f800000, v4458; GFX9-NEXT: v_rcp_f32_e32 v4, v4459; GFX9-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4460; GFX9-NEXT: v_mul_f32_e32 v5, 0x2f800000, v4461; GFX9-NEXT: v_trunc_f32_e32 v5, v5462; GFX9-NEXT: v_madmk_f32 v4, v5, 0xcf800000, v4463; GFX9-NEXT: v_cvt_u32_f32_e32 v8, v5464; GFX9-NEXT: v_cvt_u32_f32_e32 v9, v4465; GFX9-NEXT: v_mul_lo_u32 v6, v10, v8466; GFX9-NEXT: v_mul_lo_u32 v7, v11, v9467; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v10, v9, 0468; GFX9-NEXT: v_add3_u32 v7, v5, v6, v7469; GFX9-NEXT: v_mul_hi_u32 v12, v9, v4470; GFX9-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v9, v7, 0471; GFX9-NEXT: v_add_co_u32_e32 v12, vcc, v12, v5472; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v8, v4, 0473; GFX9-NEXT: v_addc_co_u32_e32 v13, vcc, 0, v6, vcc474; GFX9-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v8, v7, 0475; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v12, v4476; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v13, v5, vcc477; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v7, vcc478; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v6479; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc480; GFX9-NEXT: v_add_co_u32_e32 v12, vcc, v9, v4481; GFX9-NEXT: v_addc_co_u32_e32 v13, vcc, v8, v5, vcc482; GFX9-NEXT: v_mul_lo_u32 v6, v10, v13483; GFX9-NEXT: v_mul_lo_u32 v7, v11, v12484; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v10, v12, 0485; GFX9-NEXT: v_add3_u32 v7, v5, v6, v7486; GFX9-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v13, v7, 0487; GFX9-NEXT: v_mad_u64_u32 v[7:8], s[4:5], v12, v7, 0488; GFX9-NEXT: v_mul_hi_u32 v11, v12, v4489; GFX9-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v13, v4, 0490; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v11, v7491; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v8, vcc492; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v9493; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v7, v10, vcc494; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v6, vcc495; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v5496; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v6, vcc497; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v12, v4498; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v13, v5, vcc499; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v0, v7, 0500; GFX9-NEXT: v_mul_hi_u32 v8, v0, v6501; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v8, v4502; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v5, vcc503; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v1, v6, 0504; GFX9-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v1, v7, 0505; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v8, v4506; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v9, v5, vcc507; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v7, vcc508; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v6509; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc510; GFX9-NEXT: v_mul_lo_u32 v6, v3, v4511; GFX9-NEXT: v_mul_lo_u32 v7, v2, v5512; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v2, v4, 0513; GFX9-NEXT: v_add3_u32 v5, v5, v7, v6514; GFX9-NEXT: v_sub_u32_e32 v6, v1, v5515; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v4516; GFX9-NEXT: v_subb_co_u32_e64 v4, s[4:5], v6, v3, vcc517; GFX9-NEXT: v_sub_co_u32_e64 v6, s[4:5], v0, v2518; GFX9-NEXT: v_subbrev_co_u32_e64 v7, s[6:7], 0, v4, s[4:5]519; GFX9-NEXT: v_cmp_ge_u32_e64 s[6:7], v7, v3520; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[6:7]521; GFX9-NEXT: v_cmp_ge_u32_e64 s[6:7], v6, v2522; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v5, vcc523; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[6:7]524; GFX9-NEXT: v_cmp_eq_u32_e64 s[6:7], v7, v3525; GFX9-NEXT: v_subb_co_u32_e64 v4, s[4:5], v4, v3, s[4:5]526; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3527; GFX9-NEXT: v_cndmask_b32_e64 v8, v8, v9, s[6:7]528; GFX9-NEXT: v_sub_co_u32_e64 v9, s[4:5], v6, v2529; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc530; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2531; GFX9-NEXT: v_subbrev_co_u32_e64 v4, s[4:5], 0, v4, s[4:5]532; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc533; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3534; GFX9-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v8535; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc536; GFX9-NEXT: v_cndmask_b32_e64 v4, v7, v4, s[4:5]537; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2538; GFX9-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc539; GFX9-NEXT: v_cndmask_b32_e64 v1, v6, v9, s[4:5]540; GFX9-NEXT: v_cndmask_b32_e32 v4, v0, v1, vcc541; GFX9-NEXT: ; implicit-def: $vgpr2_vgpr3542; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1543; GFX9-NEXT: .LBB3_2: ; %Flow544; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[8:9]545; GFX9-NEXT: s_cbranch_execz .LBB3_4546; GFX9-NEXT: ; %bb.3:547; GFX9-NEXT: v_cvt_f32_u32_e32 v1, v2548; GFX9-NEXT: v_sub_u32_e32 v3, 0, v2549; GFX9-NEXT: v_mov_b32_e32 v5, 0550; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1551; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1552; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1553; GFX9-NEXT: v_mul_lo_u32 v3, v3, v1554; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3555; GFX9-NEXT: v_add_u32_e32 v1, v1, v3556; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1557; GFX9-NEXT: v_mul_lo_u32 v1, v1, v2558; GFX9-NEXT: v_sub_u32_e32 v0, v0, v1559; GFX9-NEXT: v_sub_u32_e32 v1, v0, v2560; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2561; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc562; GFX9-NEXT: v_sub_u32_e32 v1, v0, v2563; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2564; GFX9-NEXT: v_cndmask_b32_e32 v4, v0, v1, vcc565; GFX9-NEXT: .LBB3_4:566; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]567; GFX9-NEXT: v_mov_b32_e32 v0, v4568; GFX9-NEXT: v_mov_b32_e32 v1, v5569; GFX9-NEXT: s_setpc_b64 s[30:31]570 %d = urem i64 %a, %b571 ret i64 %d572}573 574define i32 @sdiv32(i32 %a, i32 %b) {575; GFX9-LABEL: sdiv32:576; GFX9: ; %bb.0:577; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)578; GFX9-NEXT: v_sub_u32_e32 v2, 0, v1579; GFX9-NEXT: v_max_i32_e32 v2, v2, v1580; GFX9-NEXT: v_cvt_f32_u32_e32 v3, v2581; GFX9-NEXT: v_sub_u32_e32 v4, 0, v2582; GFX9-NEXT: v_sub_u32_e32 v5, 0, v0583; GFX9-NEXT: v_max_i32_e32 v5, v5, v0584; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v3585; GFX9-NEXT: v_xor_b32_e32 v0, v0, v1586; GFX9-NEXT: v_ashrrev_i32_e32 v0, 31, v0587; GFX9-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3588; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3589; GFX9-NEXT: v_mul_lo_u32 v4, v4, v3590; GFX9-NEXT: v_mul_hi_u32 v4, v3, v4591; GFX9-NEXT: v_add_u32_e32 v3, v3, v4592; GFX9-NEXT: v_mul_hi_u32 v3, v5, v3593; GFX9-NEXT: v_mul_lo_u32 v4, v3, v2594; GFX9-NEXT: v_add_u32_e32 v1, 1, v3595; GFX9-NEXT: v_sub_u32_e32 v4, v5, v4596; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v4, v2597; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc598; GFX9-NEXT: v_sub_u32_e32 v3, v4, v2599; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc600; GFX9-NEXT: v_add_u32_e32 v4, 1, v1601; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v3, v2602; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc603; GFX9-NEXT: v_xor_b32_e32 v1, v1, v0604; GFX9-NEXT: v_sub_u32_e32 v0, v1, v0605; GFX9-NEXT: s_setpc_b64 s[30:31]606 %d = sdiv i32 %a, %b607 ret i32 %d608}609 610define i32 @udiv32(i32 %a, i32 %b) {611; GFX9-LABEL: udiv32:612; GFX9: ; %bb.0:613; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)614; GFX9-NEXT: v_cvt_f32_u32_e32 v2, v1615; GFX9-NEXT: v_sub_u32_e32 v3, 0, v1616; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v2617; GFX9-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2618; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2619; GFX9-NEXT: v_mul_lo_u32 v3, v3, v2620; GFX9-NEXT: v_mul_hi_u32 v3, v2, v3621; GFX9-NEXT: v_add_u32_e32 v2, v2, v3622; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2623; GFX9-NEXT: v_mul_lo_u32 v3, v2, v1624; GFX9-NEXT: v_add_u32_e32 v4, 1, v2625; GFX9-NEXT: v_sub_u32_e32 v0, v0, v3626; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1627; GFX9-NEXT: v_sub_u32_e32 v3, v0, v1628; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc629; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc630; GFX9-NEXT: v_add_u32_e32 v3, 1, v2631; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1632; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc633; GFX9-NEXT: s_setpc_b64 s[30:31]634 %d = udiv i32 %a, %b635 ret i32 %d636}637 638define i32 @srem32(i32 %a, i32 %b) {639; GFX9-LABEL: srem32:640; GFX9: ; %bb.0:641; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)642; GFX9-NEXT: v_sub_u32_e32 v2, 0, v1643; GFX9-NEXT: v_max_i32_e32 v1, v2, v1644; GFX9-NEXT: v_cvt_f32_u32_e32 v2, v1645; GFX9-NEXT: v_sub_u32_e32 v3, 0, v1646; GFX9-NEXT: v_sub_u32_e32 v4, 0, v0647; GFX9-NEXT: v_max_i32_e32 v4, v4, v0648; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v2649; GFX9-NEXT: v_ashrrev_i32_e32 v0, 31, v0650; GFX9-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2651; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2652; GFX9-NEXT: v_mul_lo_u32 v3, v3, v2653; GFX9-NEXT: v_mul_hi_u32 v3, v2, v3654; GFX9-NEXT: v_add_u32_e32 v2, v2, v3655; GFX9-NEXT: v_mul_hi_u32 v2, v4, v2656; GFX9-NEXT: v_mul_lo_u32 v2, v2, v1657; GFX9-NEXT: v_sub_u32_e32 v2, v4, v2658; GFX9-NEXT: v_sub_u32_e32 v3, v2, v1659; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v2, v1660; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc661; GFX9-NEXT: v_sub_u32_e32 v3, v2, v1662; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v2, v1663; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc664; GFX9-NEXT: v_xor_b32_e32 v1, v1, v0665; GFX9-NEXT: v_sub_u32_e32 v0, v1, v0666; GFX9-NEXT: s_setpc_b64 s[30:31]667 %d = srem i32 %a, %b668 ret i32 %d669}670 671define i32 @urem32(i32 %a, i32 %b) {672; GFX9-LABEL: urem32:673; GFX9: ; %bb.0:674; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)675; GFX9-NEXT: v_cvt_f32_u32_e32 v2, v1676; GFX9-NEXT: v_sub_u32_e32 v3, 0, v1677; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v2678; GFX9-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2679; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2680; GFX9-NEXT: v_mul_lo_u32 v3, v3, v2681; GFX9-NEXT: v_mul_hi_u32 v3, v2, v3682; GFX9-NEXT: v_add_u32_e32 v2, v2, v3683; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2684; GFX9-NEXT: v_mul_lo_u32 v2, v2, v1685; GFX9-NEXT: v_sub_u32_e32 v0, v0, v2686; GFX9-NEXT: v_sub_u32_e32 v2, v0, v1687; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1688; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc689; GFX9-NEXT: v_sub_u32_e32 v2, v0, v1690; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1691; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc692; GFX9-NEXT: s_setpc_b64 s[30:31]693 %d = urem i32 %a, %b694 ret i32 %d695}696 697define <2 x i64> @sdivrem64(i64 %a, i64 %b) {698; GFX9-LABEL: sdivrem64:699; GFX9: ; %bb.0:700; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)701; GFX9-NEXT: v_or_b32_e32 v5, v1, v3702; GFX9-NEXT: v_mov_b32_e32 v4, 0703; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]704; GFX9-NEXT: ; implicit-def: $vgpr6_vgpr7705; GFX9-NEXT: ; implicit-def: $vgpr4_vgpr5706; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc707; GFX9-NEXT: s_xor_b64 s[10:11], exec, s[4:5]708; GFX9-NEXT: s_cbranch_execz .LBB8_2709; GFX9-NEXT: ; %bb.1:710; GFX9-NEXT: v_ashrrev_i32_e32 v9, 31, v3711; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v9712; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v9, vcc713; GFX9-NEXT: v_xor_b32_e32 v10, v3, v9714; GFX9-NEXT: v_xor_b32_e32 v11, v2, v9715; GFX9-NEXT: v_cvt_f32_u32_e32 v2, v11716; GFX9-NEXT: v_cvt_f32_u32_e32 v3, v10717; GFX9-NEXT: v_sub_co_u32_e32 v7, vcc, 0, v11718; GFX9-NEXT: v_subb_co_u32_e32 v8, vcc, 0, v10, vcc719; GFX9-NEXT: v_madmk_f32 v2, v3, 0x4f800000, v2720; GFX9-NEXT: v_rcp_f32_e32 v2, v2721; GFX9-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2722; GFX9-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2723; GFX9-NEXT: v_trunc_f32_e32 v3, v3724; GFX9-NEXT: v_madmk_f32 v2, v3, 0xcf800000, v2725; GFX9-NEXT: v_cvt_u32_f32_e32 v6, v2726; GFX9-NEXT: v_cvt_u32_f32_e32 v12, v3727; GFX9-NEXT: v_mul_lo_u32 v4, v8, v6728; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v7, v6, 0729; GFX9-NEXT: v_mul_lo_u32 v5, v7, v12730; GFX9-NEXT: v_mul_hi_u32 v13, v6, v2731; GFX9-NEXT: v_add3_u32 v5, v3, v5, v4732; GFX9-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v6, v5, 0733; GFX9-NEXT: v_add_co_u32_e32 v13, vcc, v13, v3734; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v12, v2, 0735; GFX9-NEXT: v_addc_co_u32_e32 v14, vcc, 0, v4, vcc736; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v12, v5, 0737; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v13, v2738; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v14, v3, vcc739; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v5, vcc740; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4741; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc742; GFX9-NEXT: v_add_co_u32_e32 v13, vcc, v6, v2743; GFX9-NEXT: v_addc_co_u32_e32 v12, vcc, v12, v3, vcc744; GFX9-NEXT: v_mul_lo_u32 v4, v7, v12745; GFX9-NEXT: v_mul_lo_u32 v5, v8, v13746; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v7, v13, 0747; GFX9-NEXT: v_add3_u32 v5, v3, v4, v5748; GFX9-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v12, v5, 0749; GFX9-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v13, v5, 0750; GFX9-NEXT: v_mul_hi_u32 v14, v13, v2751; GFX9-NEXT: v_mad_u64_u32 v[7:8], s[4:5], v12, v2, 0752; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v14, v5753; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v6, vcc754; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v7755; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v5, v8, vcc756; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v4, vcc757; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v3758; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc759; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v13, v2760; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v12, v3, vcc761; GFX9-NEXT: v_ashrrev_i32_e32 v7, 31, v1762; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v7763; GFX9-NEXT: v_xor_b32_e32 v5, v0, v7764; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v1, v7, vcc765; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v5, v3, 0766; GFX9-NEXT: v_mul_hi_u32 v6, v5, v2767; GFX9-NEXT: v_xor_b32_e32 v4, v4, v7768; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v6, v0769; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v1, vcc770; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v4, v2, 0771; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v4, v3, 0772; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v6, v0773; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v8, v1, vcc774; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc775; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v0, v2776; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v1, vcc777; GFX9-NEXT: v_mul_lo_u32 v6, v10, v2778; GFX9-NEXT: v_mul_lo_u32 v8, v11, v3779; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v11, v2, 0780; GFX9-NEXT: v_add3_u32 v1, v1, v8, v6781; GFX9-NEXT: v_sub_u32_e32 v6, v4, v1782; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, v5, v0783; GFX9-NEXT: v_subb_co_u32_e64 v6, s[4:5], v6, v10, vcc784; GFX9-NEXT: v_sub_co_u32_e64 v8, s[4:5], v0, v11785; GFX9-NEXT: v_subbrev_co_u32_e64 v12, s[6:7], 0, v6, s[4:5]786; GFX9-NEXT: v_cmp_ge_u32_e64 s[6:7], v12, v10787; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[6:7]788; GFX9-NEXT: v_cmp_ge_u32_e64 s[6:7], v8, v11789; GFX9-NEXT: v_cndmask_b32_e64 v13, 0, -1, s[6:7]790; GFX9-NEXT: v_cmp_eq_u32_e64 s[6:7], v12, v10791; GFX9-NEXT: v_cndmask_b32_e64 v5, v5, v13, s[6:7]792; GFX9-NEXT: v_add_co_u32_e64 v13, s[6:7], 2, v2793; GFX9-NEXT: v_addc_co_u32_e64 v14, s[6:7], 0, v3, s[6:7]794; GFX9-NEXT: v_add_co_u32_e64 v15, s[6:7], 1, v2795; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v4, v1, vcc796; GFX9-NEXT: v_addc_co_u32_e64 v16, s[6:7], 0, v3, s[6:7]797; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v1, v10798; GFX9-NEXT: v_cmp_ne_u32_e64 s[6:7], 0, v5799; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc800; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v11801; GFX9-NEXT: v_cndmask_b32_e64 v5, v16, v14, s[6:7]802; GFX9-NEXT: v_cndmask_b32_e64 v14, 0, -1, vcc803; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v10804; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v14, vcc805; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4806; GFX9-NEXT: v_cndmask_b32_e64 v4, v15, v13, s[6:7]807; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc808; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc809; GFX9-NEXT: v_xor_b32_e32 v5, v7, v9810; GFX9-NEXT: v_xor_b32_e32 v2, v2, v5811; GFX9-NEXT: v_xor_b32_e32 v3, v3, v5812; GFX9-NEXT: v_sub_co_u32_e64 v4, s[8:9], v2, v5813; GFX9-NEXT: v_subb_co_u32_e64 v2, s[4:5], v6, v10, s[4:5]814; GFX9-NEXT: v_subb_co_u32_e64 v5, s[8:9], v3, v5, s[8:9]815; GFX9-NEXT: v_sub_co_u32_e64 v3, s[4:5], v8, v11816; GFX9-NEXT: v_subbrev_co_u32_e64 v2, s[4:5], 0, v2, s[4:5]817; GFX9-NEXT: v_cndmask_b32_e64 v2, v12, v2, s[6:7]818; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc819; GFX9-NEXT: v_cndmask_b32_e64 v2, v8, v3, s[6:7]820; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc821; GFX9-NEXT: v_xor_b32_e32 v0, v0, v7822; GFX9-NEXT: v_xor_b32_e32 v1, v1, v7823; GFX9-NEXT: v_sub_co_u32_e32 v6, vcc, v0, v7824; GFX9-NEXT: v_subb_co_u32_e32 v7, vcc, v1, v7, vcc825; GFX9-NEXT: ; implicit-def: $vgpr2_vgpr3826; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1827; GFX9-NEXT: .LBB8_2: ; %Flow828; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[10:11]829; GFX9-NEXT: s_cbranch_execz .LBB8_4830; GFX9-NEXT: ; %bb.3:831; GFX9-NEXT: v_cvt_f32_u32_e32 v1, v2832; GFX9-NEXT: v_sub_u32_e32 v3, 0, v2833; GFX9-NEXT: v_mov_b32_e32 v5, 0834; GFX9-NEXT: v_mov_b32_e32 v7, v5835; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1836; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1837; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1838; GFX9-NEXT: v_mul_lo_u32 v3, v3, v1839; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3840; GFX9-NEXT: v_add_u32_e32 v1, v1, v3841; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1842; GFX9-NEXT: v_mul_lo_u32 v3, v1, v2843; GFX9-NEXT: v_add_u32_e32 v4, 1, v1844; GFX9-NEXT: v_sub_u32_e32 v0, v0, v3845; GFX9-NEXT: v_sub_u32_e32 v3, v0, v2846; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2847; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc848; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc849; GFX9-NEXT: v_sub_u32_e32 v3, v0, v2850; GFX9-NEXT: v_add_u32_e32 v4, 1, v1851; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2852; GFX9-NEXT: v_cndmask_b32_e32 v6, v0, v3, vcc853; GFX9-NEXT: v_cndmask_b32_e32 v4, v1, v4, vcc854; GFX9-NEXT: .LBB8_4:855; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]856; GFX9-NEXT: v_mov_b32_e32 v0, v4857; GFX9-NEXT: v_mov_b32_e32 v1, v5858; GFX9-NEXT: v_mov_b32_e32 v2, v6859; GFX9-NEXT: v_mov_b32_e32 v3, v7860; GFX9-NEXT: s_setpc_b64 s[30:31]861 %d = sdiv i64 %a, %b862 %r = srem i64 %a, %b863 %ins.0 = insertelement <2 x i64> poison, i64 %d, i32 0864 %ins.1 = insertelement <2 x i64> %ins.0, i64 %r, i32 1865 ret <2 x i64> %ins.1866}867 868define <2 x i64> @udivrem64(i64 %a, i64 %b) {869; GFX9-LABEL: udivrem64:870; GFX9: ; %bb.0:871; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)872; GFX9-NEXT: v_or_b32_e32 v5, v1, v3873; GFX9-NEXT: v_mov_b32_e32 v4, 0874; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]875; GFX9-NEXT: ; implicit-def: $vgpr6_vgpr7876; GFX9-NEXT: ; implicit-def: $vgpr4_vgpr5877; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc878; GFX9-NEXT: s_xor_b64 s[8:9], exec, s[4:5]879; GFX9-NEXT: s_cbranch_execz .LBB9_2880; GFX9-NEXT: ; %bb.1:881; GFX9-NEXT: v_cvt_f32_u32_e32 v4, v2882; GFX9-NEXT: v_cvt_f32_u32_e32 v5, v3883; GFX9-NEXT: v_sub_co_u32_e32 v10, vcc, 0, v2884; GFX9-NEXT: v_subb_co_u32_e32 v11, vcc, 0, v3, vcc885; GFX9-NEXT: v_madmk_f32 v4, v5, 0x4f800000, v4886; GFX9-NEXT: v_rcp_f32_e32 v4, v4887; GFX9-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4888; GFX9-NEXT: v_mul_f32_e32 v5, 0x2f800000, v4889; GFX9-NEXT: v_trunc_f32_e32 v5, v5890; GFX9-NEXT: v_madmk_f32 v4, v5, 0xcf800000, v4891; GFX9-NEXT: v_cvt_u32_f32_e32 v8, v5892; GFX9-NEXT: v_cvt_u32_f32_e32 v9, v4893; GFX9-NEXT: v_mul_lo_u32 v6, v10, v8894; GFX9-NEXT: v_mul_lo_u32 v7, v11, v9895; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v10, v9, 0896; GFX9-NEXT: v_add3_u32 v7, v5, v6, v7897; GFX9-NEXT: v_mul_hi_u32 v12, v9, v4898; GFX9-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v9, v7, 0899; GFX9-NEXT: v_add_co_u32_e32 v12, vcc, v12, v5900; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v8, v4, 0901; GFX9-NEXT: v_addc_co_u32_e32 v13, vcc, 0, v6, vcc902; GFX9-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v8, v7, 0903; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v12, v4904; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v13, v5, vcc905; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v7, vcc906; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v6907; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc908; GFX9-NEXT: v_add_co_u32_e32 v12, vcc, v9, v4909; GFX9-NEXT: v_addc_co_u32_e32 v13, vcc, v8, v5, vcc910; GFX9-NEXT: v_mul_lo_u32 v6, v10, v13911; GFX9-NEXT: v_mul_lo_u32 v7, v11, v12912; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v10, v12, 0913; GFX9-NEXT: v_add3_u32 v7, v5, v6, v7914; GFX9-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v13, v7, 0915; GFX9-NEXT: v_mad_u64_u32 v[7:8], s[4:5], v12, v7, 0916; GFX9-NEXT: v_mul_hi_u32 v11, v12, v4917; GFX9-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v13, v4, 0918; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v11, v7919; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v8, vcc920; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v9921; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v7, v10, vcc922; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v6, vcc923; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v5924; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v6, vcc925; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v12, v4926; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v13, v5, vcc927; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v0, v7, 0928; GFX9-NEXT: v_mul_hi_u32 v8, v0, v6929; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v8, v4930; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v5, vcc931; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v1, v6, 0932; GFX9-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v1, v7, 0933; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v8, v4934; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v9, v5, vcc935; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v7, vcc936; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v4, v6937; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v5, vcc938; GFX9-NEXT: v_mul_lo_u32 v8, v3, v6939; GFX9-NEXT: v_mul_lo_u32 v9, v2, v7940; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v2, v6, 0941; GFX9-NEXT: v_add3_u32 v5, v5, v9, v8942; GFX9-NEXT: v_sub_u32_e32 v8, v1, v5943; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v4944; GFX9-NEXT: v_subb_co_u32_e64 v8, s[4:5], v8, v3, vcc945; GFX9-NEXT: v_sub_co_u32_e64 v9, s[4:5], v0, v2946; GFX9-NEXT: v_subbrev_co_u32_e64 v10, s[6:7], 0, v8, s[4:5]947; GFX9-NEXT: v_cmp_ge_u32_e64 s[6:7], v10, v3948; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[6:7]949; GFX9-NEXT: v_cmp_ge_u32_e64 s[6:7], v9, v2950; GFX9-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[6:7]951; GFX9-NEXT: v_cmp_eq_u32_e64 s[6:7], v10, v3952; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, v11, s[6:7]953; GFX9-NEXT: v_add_co_u32_e64 v11, s[6:7], 2, v6954; GFX9-NEXT: v_addc_co_u32_e64 v12, s[6:7], 0, v7, s[6:7]955; GFX9-NEXT: v_add_co_u32_e64 v13, s[6:7], 1, v6956; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v5, vcc957; GFX9-NEXT: v_addc_co_u32_e64 v14, s[6:7], 0, v7, s[6:7]958; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3959; GFX9-NEXT: v_cmp_ne_u32_e64 s[6:7], 0, v4960; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc961; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2962; GFX9-NEXT: v_cndmask_b32_e64 v4, v14, v12, s[6:7]963; GFX9-NEXT: v_cndmask_b32_e64 v12, 0, -1, vcc964; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3965; GFX9-NEXT: v_subb_co_u32_e64 v3, s[4:5], v8, v3, s[4:5]966; GFX9-NEXT: v_sub_co_u32_e64 v2, s[4:5], v9, v2967; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v12, vcc968; GFX9-NEXT: v_subbrev_co_u32_e64 v3, s[4:5], 0, v3, s[4:5]969; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5970; GFX9-NEXT: v_cndmask_b32_e64 v3, v10, v3, s[6:7]971; GFX9-NEXT: v_cndmask_b32_e32 v5, v7, v4, vcc972; GFX9-NEXT: v_cndmask_b32_e64 v4, v13, v11, s[6:7]973; GFX9-NEXT: v_cndmask_b32_e32 v7, v1, v3, vcc974; GFX9-NEXT: v_cndmask_b32_e64 v1, v9, v2, s[6:7]975; GFX9-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc976; GFX9-NEXT: v_cndmask_b32_e32 v6, v0, v1, vcc977; GFX9-NEXT: ; implicit-def: $vgpr2_vgpr3978; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1979; GFX9-NEXT: .LBB9_2: ; %Flow980; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[8:9]981; GFX9-NEXT: s_cbranch_execz .LBB9_4982; GFX9-NEXT: ; %bb.3:983; GFX9-NEXT: v_cvt_f32_u32_e32 v1, v2984; GFX9-NEXT: v_sub_u32_e32 v3, 0, v2985; GFX9-NEXT: v_mov_b32_e32 v5, 0986; GFX9-NEXT: v_mov_b32_e32 v7, v5987; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1988; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1989; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1990; GFX9-NEXT: v_mul_lo_u32 v3, v3, v1991; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3992; GFX9-NEXT: v_add_u32_e32 v1, v1, v3993; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1994; GFX9-NEXT: v_mul_lo_u32 v3, v1, v2995; GFX9-NEXT: v_add_u32_e32 v4, 1, v1996; GFX9-NEXT: v_sub_u32_e32 v0, v0, v3997; GFX9-NEXT: v_sub_u32_e32 v3, v0, v2998; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2999; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc1000; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc1001; GFX9-NEXT: v_sub_u32_e32 v3, v0, v21002; GFX9-NEXT: v_add_u32_e32 v4, 1, v11003; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v21004; GFX9-NEXT: v_cndmask_b32_e32 v6, v0, v3, vcc1005; GFX9-NEXT: v_cndmask_b32_e32 v4, v1, v4, vcc1006; GFX9-NEXT: .LBB9_4:1007; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]1008; GFX9-NEXT: v_mov_b32_e32 v0, v41009; GFX9-NEXT: v_mov_b32_e32 v1, v51010; GFX9-NEXT: v_mov_b32_e32 v2, v61011; GFX9-NEXT: v_mov_b32_e32 v3, v71012; GFX9-NEXT: s_setpc_b64 s[30:31]1013 %d = udiv i64 %a, %b1014 %r = urem i64 %a, %b1015 %ins.0 = insertelement <2 x i64> poison, i64 %d, i32 01016 %ins.1 = insertelement <2 x i64> %ins.0, i64 %r, i32 11017 ret <2 x i64> %ins.11018}1019 1020define i64 @sdiv64_known32(i64 %a, i64 %b) {1021; GFX9-LABEL: sdiv64_known32:1022; GFX9: ; %bb.0:1023; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1024; GFX9-NEXT: v_ashrrev_i32_e32 v2, 31, v11025; GFX9-NEXT: v_ashrrev_i32_e32 v0, 31, v31026; GFX9-NEXT: v_or_b32_e32 v5, v2, v01027; GFX9-NEXT: v_mov_b32_e32 v4, 01028; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]1029; GFX9-NEXT: ; implicit-def: $vgpr4_vgpr51030; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc1031; GFX9-NEXT: s_xor_b64 s[6:7], exec, s[4:5]1032; GFX9-NEXT: s_cbranch_execz .LBB10_21033; GFX9-NEXT: ; %bb.1:1034; GFX9-NEXT: v_cvt_f32_u32_e32 v4, v31035; GFX9-NEXT: v_cvt_f32_u32_e32 v5, v01036; GFX9-NEXT: v_sub_co_u32_e32 v10, vcc, 0, v31037; GFX9-NEXT: v_subb_co_u32_e32 v11, vcc, 0, v0, vcc1038; GFX9-NEXT: v_madmk_f32 v4, v5, 0x4f800000, v41039; GFX9-NEXT: v_rcp_f32_e32 v4, v41040; GFX9-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v41041; GFX9-NEXT: v_mul_f32_e32 v5, 0x2f800000, v41042; GFX9-NEXT: v_trunc_f32_e32 v5, v51043; GFX9-NEXT: v_madmk_f32 v4, v5, 0xcf800000, v41044; GFX9-NEXT: v_cvt_u32_f32_e32 v8, v51045; GFX9-NEXT: v_cvt_u32_f32_e32 v9, v41046; GFX9-NEXT: v_mul_lo_u32 v6, v10, v81047; GFX9-NEXT: v_mul_lo_u32 v7, v11, v91048; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v10, v9, 01049; GFX9-NEXT: v_add3_u32 v7, v5, v6, v71050; GFX9-NEXT: v_mul_hi_u32 v12, v9, v41051; GFX9-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v9, v7, 01052; GFX9-NEXT: v_add_co_u32_e32 v12, vcc, v12, v51053; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v8, v4, 01054; GFX9-NEXT: v_addc_co_u32_e32 v13, vcc, 0, v6, vcc1055; GFX9-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v8, v7, 01056; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v12, v41057; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v13, v5, vcc1058; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v7, vcc1059; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v61060; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc1061; GFX9-NEXT: v_add_co_u32_e32 v12, vcc, v9, v41062; GFX9-NEXT: v_addc_co_u32_e32 v13, vcc, v8, v5, vcc1063; GFX9-NEXT: v_mul_lo_u32 v6, v10, v131064; GFX9-NEXT: v_mul_lo_u32 v7, v11, v121065; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v10, v12, 01066; GFX9-NEXT: v_add3_u32 v7, v5, v6, v71067; GFX9-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v13, v7, 01068; GFX9-NEXT: v_mad_u64_u32 v[7:8], s[4:5], v12, v7, 01069; GFX9-NEXT: v_mul_hi_u32 v11, v12, v41070; GFX9-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v13, v4, 01071; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v11, v71072; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v8, vcc1073; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v91074; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v7, v10, vcc1075; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v6, vcc1076; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v51077; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v6, vcc1078; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v12, v41079; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v13, v5, vcc1080; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v1, v7, 01081; GFX9-NEXT: v_mul_hi_u32 v8, v1, v61082; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v8, v41083; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v5, vcc1084; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v2, v6, 01085; GFX9-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v2, v7, 01086; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v8, v41087; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v9, v5, vcc1088; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v7, vcc1089; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v4, v61090; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v5, vcc1091; GFX9-NEXT: v_mul_lo_u32 v8, v0, v61092; GFX9-NEXT: v_mul_lo_u32 v9, v3, v71093; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v3, v6, 01094; GFX9-NEXT: v_add3_u32 v5, v5, v9, v81095; GFX9-NEXT: v_sub_u32_e32 v8, v2, v51096; GFX9-NEXT: v_sub_co_u32_e32 v1, vcc, v1, v41097; GFX9-NEXT: v_subb_co_u32_e64 v4, s[4:5], v8, v0, vcc1098; GFX9-NEXT: v_sub_co_u32_e64 v8, s[4:5], v1, v31099; GFX9-NEXT: v_subbrev_co_u32_e64 v4, s[4:5], 0, v4, s[4:5]1100; GFX9-NEXT: v_cmp_ge_u32_e64 s[4:5], v4, v01101; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5]1102; GFX9-NEXT: v_cmp_ge_u32_e64 s[4:5], v8, v31103; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[4:5]1104; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], v4, v01105; GFX9-NEXT: v_cndmask_b32_e64 v4, v9, v8, s[4:5]1106; GFX9-NEXT: v_add_co_u32_e64 v8, s[4:5], 2, v61107; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v2, v5, vcc1108; GFX9-NEXT: v_addc_co_u32_e64 v9, s[4:5], 0, v7, s[4:5]1109; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v2, v01110; GFX9-NEXT: v_add_co_u32_e64 v10, s[4:5], 1, v61111; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc1112; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v1, v31113; GFX9-NEXT: v_addc_co_u32_e64 v11, s[4:5], 0, v7, s[4:5]1114; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc1115; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v2, v01116; GFX9-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v41117; GFX9-NEXT: v_cndmask_b32_e32 v0, v5, v1, vcc1118; GFX9-NEXT: v_cndmask_b32_e64 v4, v11, v9, s[4:5]1119; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v01120; GFX9-NEXT: v_cndmask_b32_e64 v0, v10, v8, s[4:5]1121; GFX9-NEXT: v_cndmask_b32_e32 v5, v7, v4, vcc1122; GFX9-NEXT: v_cndmask_b32_e32 v4, v6, v0, vcc1123; GFX9-NEXT: ; implicit-def: $vgpr2_vgpr31124; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr11125; GFX9-NEXT: .LBB10_2: ; %Flow1126; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[6:7]1127; GFX9-NEXT: s_cbranch_execz .LBB10_41128; GFX9-NEXT: ; %bb.3:1129; GFX9-NEXT: v_cvt_f32_u32_e32 v0, v31130; GFX9-NEXT: v_sub_u32_e32 v2, 0, v31131; GFX9-NEXT: v_mov_b32_e32 v5, 01132; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v01133; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v01134; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v01135; GFX9-NEXT: v_mul_lo_u32 v2, v2, v01136; GFX9-NEXT: v_mul_hi_u32 v2, v0, v21137; GFX9-NEXT: v_add_u32_e32 v0, v0, v21138; GFX9-NEXT: v_mul_hi_u32 v0, v1, v01139; GFX9-NEXT: v_mul_lo_u32 v2, v0, v31140; GFX9-NEXT: v_add_u32_e32 v4, 1, v01141; GFX9-NEXT: v_sub_u32_e32 v1, v1, v21142; GFX9-NEXT: v_sub_u32_e32 v2, v1, v31143; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v1, v31144; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc1145; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc1146; GFX9-NEXT: v_add_u32_e32 v2, 1, v01147; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v1, v31148; GFX9-NEXT: v_cndmask_b32_e32 v4, v0, v2, vcc1149; GFX9-NEXT: .LBB10_4:1150; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]1151; GFX9-NEXT: v_mov_b32_e32 v0, v41152; GFX9-NEXT: v_mov_b32_e32 v1, v51153; GFX9-NEXT: s_setpc_b64 s[30:31]1154 %a.ext = ashr i64 %a, 321155 %b.ext = ashr i64 %b, 321156 %d = udiv i64 %a.ext, %b.ext1157 ret i64 %d1158}1159 1160define i64 @udiv64_known32(i64 %a, i64 %b) {1161; GFX9-LABEL: udiv64_known32:1162; GFX9: ; %bb.0:1163; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1164; GFX9-NEXT: v_cvt_f32_u32_e32 v1, v21165; GFX9-NEXT: v_sub_u32_e32 v3, 0, v21166; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v11167; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v11168; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v11169; GFX9-NEXT: v_mul_lo_u32 v3, v3, v11170; GFX9-NEXT: v_mul_hi_u32 v3, v1, v31171; GFX9-NEXT: v_add_u32_e32 v1, v1, v31172; GFX9-NEXT: v_mul_hi_u32 v1, v0, v11173; GFX9-NEXT: v_mul_lo_u32 v3, v1, v21174; GFX9-NEXT: v_add_u32_e32 v4, 1, v11175; GFX9-NEXT: v_sub_u32_e32 v0, v0, v31176; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v21177; GFX9-NEXT: v_sub_u32_e32 v3, v0, v21178; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc1179; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc1180; GFX9-NEXT: v_add_u32_e32 v3, 1, v11181; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v21182; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc1183; GFX9-NEXT: v_mov_b32_e32 v1, 01184; GFX9-NEXT: s_setpc_b64 s[30:31]1185 %a.mask = and i64 %a, 42949672951186 %b.mask = and i64 %b, 42949672951187 %d = udiv i64 %a.mask, %b.mask1188 ret i64 %d1189}1190