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1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 52; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -simplify-mir -stop-after=finalize-isel -verify-machineinstrs < %s | FileCheck -check-prefixes=SDAG %s3; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -simplify-mir -stop-after=finalize-isel -verify-machineinstrs < %s | FileCheck -check-prefixes=GISEL %s4 5; Check that call / asm get an implicit-def $mode added to them in6; strictfp functions.7 8declare protected void @maybe_defs_mode() #09 10define float @call_changes_mode(float %x, float %y) #0 {11 ; SDAG-LABEL: name: call_changes_mode12 ; SDAG: bb.0 (%ir-block.0):13 ; SDAG-NEXT: liveins: $vgpr0, $vgpr114 ; SDAG-NEXT: {{ $}}15 ; SDAG-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr116 ; SDAG-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr017 ; SDAG-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $scc, implicit-def $sgpr32, implicit $sgpr3218 ; SDAG-NEXT: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @maybe_defs_mode, target-flags(amdgpu-rel32-hi) @maybe_defs_mode, implicit-def dead $scc19 ; SDAG-NEXT: [[COPY2:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr320 ; SDAG-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY2]]21 ; SDAG-NEXT: $sgpr30_sgpr31 = SI_CALL killed [[SI_PC_ADD_REL_OFFSET]], @maybe_defs_mode, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit-def $mode22 ; SDAG-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $scc, implicit-def $sgpr32, implicit $sgpr3223 ; SDAG-NEXT: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec24 ; SDAG-NEXT: $vgpr0 = COPY [[V_ADD_F32_e64_]]25 ; SDAG-NEXT: SI_RETURN implicit $vgpr026 ;27 ; GISEL-LABEL: name: call_changes_mode28 ; GISEL: bb.1 (%ir-block.0):29 ; GISEL-NEXT: liveins: $vgpr0, $vgpr130 ; GISEL-NEXT: {{ $}}31 ; GISEL-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr032 ; GISEL-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr133 ; GISEL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc, implicit-def $sgpr32, implicit $sgpr3234 ; GISEL-NEXT: [[COPY2:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr335 ; GISEL-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY2]]36 ; GISEL-NEXT: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @maybe_defs_mode, target-flags(amdgpu-rel32-hi) @maybe_defs_mode, implicit-def $scc37 ; GISEL-NEXT: $sgpr30_sgpr31 = noconvergent SI_CALL [[SI_PC_ADD_REL_OFFSET]], @maybe_defs_mode, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr338 ; GISEL-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc, implicit-def $sgpr32, implicit $sgpr3239 ; GISEL-NEXT: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec40 ; GISEL-NEXT: $vgpr0 = COPY [[V_ADD_F32_e64_]]41 ; GISEL-NEXT: SI_RETURN implicit $vgpr042 call void @maybe_defs_mode()43 %val = call float @llvm.experimental.constrained.fadd.f32(float %x, float %y, metadata !"round.dynamic", metadata !"fpexcept.ignore")44 ret float %val45}46 47define void @tail_call_changes_mode() #0 {48 ; SDAG-LABEL: name: tail_call_changes_mode49 ; SDAG: bb.0 (%ir-block.0):50 ; SDAG-NEXT: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:ccr_sgpr_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @maybe_defs_mode, target-flags(amdgpu-rel32-hi) @maybe_defs_mode, implicit-def dead $scc51 ; SDAG-NEXT: SI_TCRETURN killed [[SI_PC_ADD_REL_OFFSET]], @maybe_defs_mode, 0, csr_amdgpu, implicit-def $mode52 ;53 ; GISEL-LABEL: name: tail_call_changes_mode54 ; GISEL: bb.1 (%ir-block.0):55 ; GISEL-NEXT: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr356 ; GISEL-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY]]57 ; GISEL-NEXT: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:ccr_sgpr_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @maybe_defs_mode, target-flags(amdgpu-rel32-hi) @maybe_defs_mode, implicit-def $scc58 ; GISEL-NEXT: SI_TCRETURN [[SI_PC_ADD_REL_OFFSET]], @maybe_defs_mode, 0, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr359 tail call void @maybe_defs_mode()60 ret void61}62 63define float @asm_changes_mode(float %x, float %y) #0 {64 ; SDAG-LABEL: name: asm_changes_mode65 ; SDAG: bb.0 (%ir-block.0):66 ; SDAG-NEXT: liveins: $vgpr0, $vgpr167 ; SDAG-NEXT: {{ $}}68 ; SDAG-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr169 ; SDAG-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr070 ; SDAG-NEXT: INLINEASM &"; maybe defs mode", 1 /* sideeffect attdialect */, !0, implicit-def $mode71 ; SDAG-NEXT: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec72 ; SDAG-NEXT: $vgpr0 = COPY [[V_ADD_F32_e64_]]73 ; SDAG-NEXT: SI_RETURN implicit $vgpr074 ;75 ; GISEL-LABEL: name: asm_changes_mode76 ; GISEL: bb.1 (%ir-block.0):77 ; GISEL-NEXT: liveins: $vgpr0, $vgpr178 ; GISEL-NEXT: {{ $}}79 ; GISEL-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr080 ; GISEL-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr181 ; GISEL-NEXT: INLINEASM &"; maybe defs mode", 1 /* sideeffect attdialect */, !0, implicit-def $mode82 ; GISEL-NEXT: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec83 ; GISEL-NEXT: $vgpr0 = COPY [[V_ADD_F32_e64_]]84 ; GISEL-NEXT: SI_RETURN implicit $vgpr085 call void asm sideeffect "; maybe defs mode", ""(), !srcloc !086 %val = call float @llvm.experimental.constrained.fadd.f32(float %x, float %y, metadata !"round.dynamic", metadata !"fpexcept.ignore")87 ret float %val88}89 90declare float @llvm.experimental.constrained.fadd.f32(float, float, metadata, metadata)91 92attributes #0 = { strictfp "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-cluster-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-cluster-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-cluster-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" }93 94!0 = !{i64 87}95